[Lldb-commits] [PATCH] D132734: [lldb] Fix member access in GetExpressionPath

[Andy Yankovsky via Phabricator via lldb-commits]

werat added a comment.

In D132734#3887018 , @JDevlieghere 
wrote:

> Thanks Will, let me apply this locally and see if that addresses the issue 
> for which I reverted the original patch.

Hy Jonas, sorry for bumping an old thread, but did you manage to check if the 
latest revision fixes the issue?


Repository:
  rG LLVM Github Monorepo

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[Lldb-commits] [PATCH] D140996: [c++20] P1907R1: Support for generalized non-type template arguments of scalar type.

[Andrey Ali Khan Bolshakov via Phabricator via lldb-commits]

bolshakov-a updated this revision to Diff 558001.
bolshakov-a added a comment.

One more problem has been discovered and fixed: IR emitting didn't work when 
using a subobject as a template argument when the corresponding template 
parameter is used in an lvalue context. A test case has been added into 
`CodeGenCXX/template-arguments.cpp` test (but, maybe, there is a more 
appropriate place?)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140996/new/

https://reviews.llvm.org/D140996

Files:
  clang-tools-extra/clangd/DumpAST.cpp
  clang-tools-extra/clangd/FindTarget.cpp
  clang/docs/ReleaseNotes.rst
  clang/include/clang/AST/ODRHash.h
  clang/include/clang/AST/PropertiesBase.td
  clang/include/clang/AST/RecursiveASTVisitor.h
  clang/include/clang/AST/TemplateArgumentVisitor.h
  clang/include/clang/AST/TemplateBase.h
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ASTImporter.cpp
  clang/lib/AST/ASTStructuralEquivalence.cpp
  clang/lib/AST/Decl.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/ODRHash.cpp
  clang/lib/AST/StmtProfile.cpp
  clang/lib/AST/TemplateBase.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CGExpr.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Sema/SemaLookup.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/lib/Sema/SemaTemplate.cpp
  clang/lib/Sema/SemaTemplateDeduction.cpp
  clang/lib/Sema/SemaTemplateInstantiate.cpp
  clang/lib/Sema/SemaTemplateVariadic.cpp
  clang/lib/Sema/TreeTransform.h
  clang/lib/Serialization/ASTReader.cpp
  clang/lib/Serialization/ASTWriter.cpp
  clang/test/CXX/drs/dr12xx.cpp
  clang/test/CXX/temp/temp.arg/temp.arg.nontype/p1.cpp
  clang/test/CodeGenCXX/mangle-ms-templates.cpp
  clang/test/CodeGenCXX/mangle-template.cpp
  clang/test/CodeGenCXX/template-arguments.cpp
  clang/test/Index/USR/structural-value-tpl-arg.cpp
  clang/test/Modules/odr_hash.cpp
  clang/test/SemaCXX/warn-bool-conversion.cpp
  clang/test/SemaTemplate/temp_arg_nontype_cxx1z.cpp
  clang/test/SemaTemplate/temp_arg_nontype_cxx20.cpp
  clang/tools/libclang/CIndex.cpp
  clang/tools/libclang/CXCursor.cpp
  clang/www/cxx_status.html
  lldb/include/lldb/lldb-enumerations.h
  lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp

Index: lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
===
--- lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
+++ lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
@@ -7218,6 +7218,9 @@
 
   case clang::TemplateArgument::Pack:
 return eTemplateArgumentKindPack;
+
+  case clang::TemplateArgument::StructuralValue:
+return eTemplateArgumentKindStructuralValue;
   }
   llvm_unreachable("Unhandled clang::TemplateArgument::ArgKind");
 }
Index: lldb/include/lldb/lldb-enumerations.h
===
--- lldb/include/lldb/lldb-enumerations.h
+++ lldb/include/lldb/lldb-enumerations.h
@@ -856,6 +856,7 @@
   eTemplateArgumentKindExpression,
   eTemplateArgumentKindPack,
   eTemplateArgumentKindNullPtr,
+  eTemplateArgumentKindStructuralValue,
 };
 
 /// Type of match to be performed when looking for a formatter for a data type.
Index: clang/www/cxx_status.html
===
--- clang/www/cxx_status.html
+++ clang/www/cxx_status.html
@@ -626,13 +626,21 @@
 
 
 
-  Class types as non-type template parameters
+  Class types as non-type template parameters
   https://wg21.link/p0732r2;>P0732R2
-  Partial
+  Clang 12
+
+ 
+  Generalized non-type template parameters of scalar type
+  https://wg21.link/p1907r1;>P1907R1
+  
+
+  Clang 18 (Partial)
+  Reference type template arguments referring to instantiation-dependent objects and subobjects
+  (i.e. declared inside a template but neither type- nor value-dependent) aren't fully supported.
+
+  
 
-   
-https://wg21.link/p1907r1;>P1907R1
-  
 
   Destroying operator delete
   https://wg21.link/p0722r3;>P0722R3
Index: clang/tools/libclang/CXCursor.cpp
===
--- clang/tools/libclang/CXCursor.cpp
+++ clang/tools/libclang/CXCursor.cpp
@@ -1463,6 +1463,9 @@
 return CXTemplateArgumentKind_NullPtr;
   case TemplateArgument::Integral:
 return CXTemplateArgumentKind_Integral;
+  case TemplateArgument::StructuralValue:
+// FIXME: Expose these values.
+return CXTemplateArgumentKind_Invalid;
   case TemplateArgument::Template:
 return CXTemplateArgumentKind_Template;
   case TemplateArgument::TemplateExpansion:
Index: clang/tools/libclang/CIndex.cpp
===
--- clang/tools/libclang/CIndex.cpp
+++ 

[Lldb-commits] [PATCH] D140996: [c++20] P1907R1: Support for generalized non-type template arguments of scalar type.

[Andrey Ali Khan Bolshakov via Phabricator via lldb-commits]

bolshakov-a updated this revision to Diff 557997.
bolshakov-a added a comment.

Fixes after review.


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  https://reviews.llvm.org/D140996/new/

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Files:
  clang-tools-extra/clangd/DumpAST.cpp
  clang-tools-extra/clangd/FindTarget.cpp
  clang/docs/ReleaseNotes.rst
  clang/include/clang/AST/ODRHash.h
  clang/include/clang/AST/PropertiesBase.td
  clang/include/clang/AST/RecursiveASTVisitor.h
  clang/include/clang/AST/TemplateArgumentVisitor.h
  clang/include/clang/AST/TemplateBase.h
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ASTImporter.cpp
  clang/lib/AST/ASTStructuralEquivalence.cpp
  clang/lib/AST/Decl.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/ODRHash.cpp
  clang/lib/AST/StmtProfile.cpp
  clang/lib/AST/TemplateBase.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Sema/SemaLookup.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/lib/Sema/SemaTemplate.cpp
  clang/lib/Sema/SemaTemplateDeduction.cpp
  clang/lib/Sema/SemaTemplateInstantiate.cpp
  clang/lib/Sema/SemaTemplateVariadic.cpp
  clang/lib/Sema/TreeTransform.h
  clang/lib/Serialization/ASTReader.cpp
  clang/lib/Serialization/ASTWriter.cpp
  clang/test/CXX/drs/dr12xx.cpp
  clang/test/CXX/temp/temp.arg/temp.arg.nontype/p1.cpp
  clang/test/CodeGenCXX/mangle-ms-templates.cpp
  clang/test/CodeGenCXX/mangle-template.cpp
  clang/test/CodeGenCXX/template-arguments.cpp
  clang/test/Index/USR/structural-value-tpl-arg.cpp
  clang/test/Modules/odr_hash.cpp
  clang/test/SemaCXX/warn-bool-conversion.cpp
  clang/test/SemaTemplate/temp_arg_nontype_cxx1z.cpp
  clang/test/SemaTemplate/temp_arg_nontype_cxx20.cpp
  clang/tools/libclang/CIndex.cpp
  clang/tools/libclang/CXCursor.cpp
  clang/www/cxx_status.html
  lldb/include/lldb/lldb-enumerations.h
  lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp

Index: lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
===
--- lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
+++ lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
@@ -7218,6 +7218,9 @@
 
   case clang::TemplateArgument::Pack:
 return eTemplateArgumentKindPack;
+
+  case clang::TemplateArgument::StructuralValue:
+return eTemplateArgumentKindStructuralValue;
   }
   llvm_unreachable("Unhandled clang::TemplateArgument::ArgKind");
 }
Index: lldb/include/lldb/lldb-enumerations.h
===
--- lldb/include/lldb/lldb-enumerations.h
+++ lldb/include/lldb/lldb-enumerations.h
@@ -856,6 +856,7 @@
   eTemplateArgumentKindExpression,
   eTemplateArgumentKindPack,
   eTemplateArgumentKindNullPtr,
+  eTemplateArgumentKindStructuralValue,
 };
 
 /// Type of match to be performed when looking for a formatter for a data type.
Index: clang/www/cxx_status.html
===
--- clang/www/cxx_status.html
+++ clang/www/cxx_status.html
@@ -626,13 +626,21 @@
 
 
 
-  Class types as non-type template parameters
+  Class types as non-type template parameters
   https://wg21.link/p0732r2;>P0732R2
-  Partial
+  Clang 12
+
+ 
+  Generalized non-type template parameters of scalar type
+  https://wg21.link/p1907r1;>P1907R1
+  
+
+  Clang 18 (Partial)
+  Reference type template arguments referring to instantiation-dependent objects and subobjects
+  (i.e. declared inside a template but neither type- nor value-dependent) aren't fully supported.
+
+  
 
-   
-https://wg21.link/p1907r1;>P1907R1
-  
 
   Destroying operator delete
   https://wg21.link/p0722r3;>P0722R3
Index: clang/tools/libclang/CXCursor.cpp
===
--- clang/tools/libclang/CXCursor.cpp
+++ clang/tools/libclang/CXCursor.cpp
@@ -1463,6 +1463,9 @@
 return CXTemplateArgumentKind_NullPtr;
   case TemplateArgument::Integral:
 return CXTemplateArgumentKind_Integral;
+  case TemplateArgument::StructuralValue:
+// FIXME: Expose these values.
+return CXTemplateArgumentKind_Invalid;
   case TemplateArgument::Template:
 return CXTemplateArgumentKind_Template;
   case TemplateArgument::TemplateExpansion:
Index: clang/tools/libclang/CIndex.cpp
===
--- clang/tools/libclang/CIndex.cpp
+++ clang/tools/libclang/CIndex.cpp
@@ -1574,6 +1574,11 @@
   return Visit(MakeCXCursor(E, StmtParent, TU, RegionOfInterest));
 return false;
 
+  case TemplateArgument::StructuralValue:
+if (Expr *E = TAL.getSourceStructuralValueExpression())
+  return Visit(MakeCXCursor(E, StmtParent, TU, RegionOfInterest));
+return false;
+

[Lldb-commits] [PATCH] D140996: [c++20] P1907R1: Support for generalized non-type template arguments of scalar type.

[Andrey Ali Khan Bolshakov via Phabricator via lldb-commits]

bolshakov-a added inline comments.



Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:2205-2206
   "bit-field%select{| %1}2">;
+def err_reference_bind_to_bitfield_in_cce : Error<
+  "reference cannot bind to bit-field in converted constant expression">;
 def err_reference_bind_to_vector_element : Error<

aaron.ballman wrote:
> This change seems somewhat orthogonal to the rest of the patch; should this 
> be split out? Also, there doesn't appear to be test coverage for the new 
> diagnostic.
Separated into https://github.com/llvm/llvm-project/pull/71077

The problem showed up after one of rebasings when C++20 mode was turned on for 
`CXX/drs/dr12xx.cpp` test in [that 
commit](https://github.com/llvm/llvm-project/commit/653a82e95257a7cd3f22c24e40d54459a6608429).



Comment at: clang/lib/AST/ItaniumMangle.cpp:4397
+// argument.
+// As proposed in https://github.com/itanium-cxx-abi/cxx-abi/issues/111.
+auto *SNTTPE = cast(E);

aaron.ballman wrote:
> bolshakov-a wrote:
> > bolshakov-a wrote:
> > > efriedma wrote:
> > > > bolshakov-a wrote:
> > > > > erichkeane wrote:
> > > > > > erichkeane wrote:
> > > > > > > aaron.ballman wrote:
> > > > > > > > We should get this nailed down. It was proposed in Nov 2020 and 
> > > > > > > > the issue is still open. CC @rjmccall 
> > > > > > > This definitely needs to happen.  @rjmccall or @eli.friedman ^^ 
> > > > > > > Any idea what the actual mangling should be?
> > > > > > This is still an open, and we need @rjmccall @eli.friedman or @asl 
> > > > > > to help out here.
> > > > > Ping @efriedma, @rjmccall, @asl.
> > > > I'm not really familiar with the mangling implications for this 
> > > > particular construct, nor am I actively involved with the Itanium ABI 
> > > > specification, so I'm not sure how I can help you directly.
> > > > 
> > > > That said, as a general opinion, I don't think it's worth waiting for 
> > > > updates to the Itanuim ABI  document to be merged; such updates are 
> > > > happening slowly at the moment, and having a consistent mangling is 
> > > > clearly an improvement even if it's not specified.  My suggested plan 
> > > > of action:
> > > > 
> > > > - Make sure you're satisfied the proposed mangling doesn't have any 
> > > > holes you're concerned about (i.e. it produces a unique mangling for 
> > > > all the relevant cases).  If you're not sure, I can try to spend some 
> > > > time understanding this, but it doesn't sound like you have any 
> > > > concerns about this.
> > > > - Put a note on the issue in the Itanium ABI repo that you're planning 
> > > > to go ahead with using this mangling in clang.  Also send an email 
> > > > directly to @rjmccall and @rsmith in case they miss the notifications.
> > > > - Go ahead with this.
> > > > Put a note on the issue in the Itanium ABI repo that you're planning to 
> > > > go ahead with using this mangling in clang. Also send an email directly 
> > > > to @rjmccall and @rsmith in case they miss the notifications.
> > > 
> > > I'm sorry for noting one more time that Richard already pushed these 
> > > changes in clang upstream, but they had been just reverted.
> > > 
> > > Maybe, I should make a PR into Itanium API repository, but I probably 
> > > need some time to dig into the theory and all the discussions. But yes, 
> > > even NTTP argument mangling rules are not still merged: 
> > > https://github.com/itanium-cxx-abi/cxx-abi/pull/140
> > @aaron.ballman, @erichkeane, seems like it is already fixed in the ABI 
> > document:
> > > Typically, only references to function template parameters occurring 
> > > within the dependent signature of the template are mangled this way. In 
> > > other contexts, template instantiation replaces references to template 
> > > parameters with the actual template arguments, and mangling should mangle 
> > > such references exactly as if they were that template argument.
> > 
> > https://itanium-cxx-abi.github.io/cxx-abi/abi.html#mangle.template-param
> > 
> > See also [the discussion in the 
> > issue](https://github.com/itanium-cxx-abi/cxx-abi/issues/111#issuecomment-1567486892).
> Okay, I think I agree that this is already addressed in the ABI document. I 
> think we can drop the comment referencing the ABI issue, wdyt?
Ok, dropped.



Comment at: clang/lib/Sema/SemaTemplate.cpp:7968
+  case APValue::FixedPoint:
+return FixedPointLiteral::CreateFromRawInt(
+S.Context, Val.getFixedPoint().getValue(), T, Loc,

aaron.ballman wrote:
> What should happen if `T` isn't a fixed point type? (Should we assert here?)
I don't expect that it will happen. Non-type template argument is a constant 
expression converted to the type of the template parameter. Hence, a value 
produced by such an expression should correspond to the NTTP type.

Should an assert be placed here, it should be placed in the other `switch` 
branches as well, I think. The 

[Lldb-commits] [PATCH] D140996: [c++20] P1907R1: Support for generalized non-type template arguments of scalar type.

[Aaron Ballman via Phabricator via lldb-commits]

aaron.ballman added a comment.

In D140996#4655288 , @bolshakov-a 
wrote:

> Sorry, but I don't know what remains to be done here. It seems that the only 
> important question is about ABI, but I've already answered that the changes 
> under discussion seem to be already fixed in the Itanium ABI document.

Oh gosh, this must have fallen through the cracks then -- I thought it was 
waiting on further changes, so I hadn't been re-reviewing it. I'm sorry about 
that! Let's get this ball rolling again to try to get this landed. CC 
@erichkeane (who may not be available for the next while due to WG21 meetings, 
FYI).




Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:2205-2206
   "bit-field%select{| %1}2">;
+def err_reference_bind_to_bitfield_in_cce : Error<
+  "reference cannot bind to bit-field in converted constant expression">;
 def err_reference_bind_to_vector_element : Error<

This change seems somewhat orthogonal to the rest of the patch; should this be 
split out? Also, there doesn't appear to be test coverage for the new 
diagnostic.



Comment at: clang/lib/AST/ItaniumMangle.cpp:4397
+// argument.
+// As proposed in https://github.com/itanium-cxx-abi/cxx-abi/issues/111.
+auto *SNTTPE = cast(E);

bolshakov-a wrote:
> bolshakov-a wrote:
> > efriedma wrote:
> > > bolshakov-a wrote:
> > > > erichkeane wrote:
> > > > > erichkeane wrote:
> > > > > > aaron.ballman wrote:
> > > > > > > We should get this nailed down. It was proposed in Nov 2020 and 
> > > > > > > the issue is still open. CC @rjmccall 
> > > > > > This definitely needs to happen.  @rjmccall or @eli.friedman ^^ Any 
> > > > > > idea what the actual mangling should be?
> > > > > This is still an open, and we need @rjmccall @eli.friedman or @asl to 
> > > > > help out here.
> > > > Ping @efriedma, @rjmccall, @asl.
> > > I'm not really familiar with the mangling implications for this 
> > > particular construct, nor am I actively involved with the Itanium ABI 
> > > specification, so I'm not sure how I can help you directly.
> > > 
> > > That said, as a general opinion, I don't think it's worth waiting for 
> > > updates to the Itanuim ABI  document to be merged; such updates are 
> > > happening slowly at the moment, and having a consistent mangling is 
> > > clearly an improvement even if it's not specified.  My suggested plan of 
> > > action:
> > > 
> > > - Make sure you're satisfied the proposed mangling doesn't have any holes 
> > > you're concerned about (i.e. it produces a unique mangling for all the 
> > > relevant cases).  If you're not sure, I can try to spend some time 
> > > understanding this, but it doesn't sound like you have any concerns about 
> > > this.
> > > - Put a note on the issue in the Itanium ABI repo that you're planning to 
> > > go ahead with using this mangling in clang.  Also send an email directly 
> > > to @rjmccall and @rsmith in case they miss the notifications.
> > > - Go ahead with this.
> > > Put a note on the issue in the Itanium ABI repo that you're planning to 
> > > go ahead with using this mangling in clang. Also send an email directly 
> > > to @rjmccall and @rsmith in case they miss the notifications.
> > 
> > I'm sorry for noting one more time that Richard already pushed these 
> > changes in clang upstream, but they had been just reverted.
> > 
> > Maybe, I should make a PR into Itanium API repository, but I probably need 
> > some time to dig into the theory and all the discussions. But yes, even 
> > NTTP argument mangling rules are not still merged: 
> > https://github.com/itanium-cxx-abi/cxx-abi/pull/140
> @aaron.ballman, @erichkeane, seems like it is already fixed in the ABI 
> document:
> > Typically, only references to function template parameters occurring within 
> > the dependent signature of the template are mangled this way. In other 
> > contexts, template instantiation replaces references to template parameters 
> > with the actual template arguments, and mangling should mangle such 
> > references exactly as if they were that template argument.
> 
> https://itanium-cxx-abi.github.io/cxx-abi/abi.html#mangle.template-param
> 
> See also [the discussion in the 
> issue](https://github.com/itanium-cxx-abi/cxx-abi/issues/111#issuecomment-1567486892).
Okay, I think I agree that this is already addressed in the ABI document. I 
think we can drop the comment referencing the ABI issue, wdyt?



Comment at: clang/lib/AST/TemplateBase.cpp:408-409
   case Integral:
-getAsIntegral().Profile(ID);
 getIntegralType().Profile(ID);
+getAsIntegral().Profile(ID);
+break;

bolshakov-a wrote:
> aaron.ballman wrote:
> > Why did the order of these calls change?
> I don't know, it is from 9e08e51a20d0d2. I've tried to invert the order along 
> with the order for `StructuralValue`, and all tests have been passed.
I don't think the 

[Lldb-commits] [PATCH] D159127: [lldb][libc++] Adds chrono data formatters.

[Michael Buch via Phabricator via lldb-commits]

Michael137 added a comment.

In D159127#4655450 , @aprantl wrote:

> @Mordante @Michael137  This seems to fail on older versions of 
> compiler/libcxx 
> https://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake-matrix/7247/ You 
> can probably fix this by just requiring a minimum clang version in the tests

https://github.com/llvm/llvm-project/pull/70544


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[Lldb-commits] [PATCH] D159127: [lldb][libc++] Adds chrono data formatters.

[Adrian Prantl via Phabricator via lldb-commits]

aprantl added a comment.

@Mordante @Michael137  This seems to fail on older versions of compiler/libcxx 
https://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake-matrix/7247/ You can 
probably fix this by just requiring a minimum clang version in the tests


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[Lldb-commits] [PATCH] D159315: [lldb] Add OperatingSystem base class to the lldb python module

[Med Ismail Bennani via Phabricator via lldb-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGec456ba9ca0a: [lldb] Add OperatingSystem base class to the 
lldb python module (authored by mib).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  lldb/bindings/python/CMakeLists.txt
  lldb/examples/python/templates/operating_system.py
  lldb/examples/python/templates/scripted_process.py
  lldb/test/API/functionalities/plugins/python_os_plugin/operating_system.py

Index: lldb/test/API/functionalities/plugins/python_os_plugin/operating_system.py
===
--- lldb/test/API/functionalities/plugins/python_os_plugin/operating_system.py
+++ lldb/test/API/functionalities/plugins/python_os_plugin/operating_system.py
@@ -1,29 +1,14 @@
-#!/usr/bin/env python
-
 import lldb
 import struct
 
+from lldb.plugins.operating_system import OperatingSystem
+
 
-class OperatingSystemPlugIn(object):
+class OperatingSystemPlugIn(OperatingSystem):
 """Class that provides data for an instance of a LLDB 'OperatingSystemPython' plug-in class"""
 
 def __init__(self, process):
-"""Initialization needs a valid.SBProcess object.
-
-This plug-in will get created after a live process is valid and has stopped for the
-first time."""
-self.process = None
-self.registers = None
-self.threads = None
-if isinstance(process, lldb.SBProcess) and process.IsValid():
-self.process = process
-self.threads = None  # Will be an dictionary containing info for each thread
-
-def get_target(self):
-# NOTE: Don't use "lldb.target" when trying to get your target as the "lldb.target"
-# tracks the current target in the LLDB command interpreter which isn't the
-# correct thing to use for this plug-in.
-return self.process.target
+super().__init__(process)
 
 def create_thread(self, tid, context):
 if tid == 0x4:
@@ -40,23 +25,6 @@
 
 def get_thread_info(self):
 if not self.threads:
-# The sample dictionary below shows the values that can be returned for a thread
-# tid => thread ID (mandatory)
-# name => thread name (optional key/value pair)
-# queue => thread dispatch queue name (optional key/value pair)
-# state => thred state (mandatory, set to 'stopped' for now)
-# stop_reason => thread stop reason. (mandatory, usually set to 'none')
-#  Possible values include:
-#   'breakpoint' if the thread is stopped at a breakpoint
-#   'none' thread is just stopped because the process is stopped
-#   'trace' the thread just single stepped
-#   The usual value for this while threads are in memory is 'none'
-# register_data_addr => the address of the register data in memory (optional key/value pair)
-#   Specifying this key/value pair for a thread will avoid a call to get_register_data()
-#   and can be used when your registers are in a thread context structure that is contiguous
-#   in memory. Don't specify this if your register layout in memory doesn't match the layout
-# described by the dictionary returned from a call to the
-# get_register_info() method.
 self.threads = [
 {
 "tid": 0x1,
Index: lldb/examples/python/templates/scripted_process.py
===
--- lldb/examples/python/templates/scripted_process.py
+++ lldb/examples/python/templates/scripted_process.py
@@ -244,16 +244,16 @@
 """
 
 @abstractmethod
-def __init__(self, scripted_process, args):
+def __init__(self, process, args):
 """Construct a scripted thread.
 
 Args:
-process (ScriptedProcess): The scripted process owning this thread.
+process (ScriptedProcess/lldb.SBProcess): The process owning this thread.
 args (lldb.SBStructuredData): A Dictionary holding arbitrary
 key/value pairs used by the scripted thread.
 """
 self.target = None
-self.scripted_process = None
+self.originating_process = None
 self.process = None
 self.args = None
 self.idx = 0
@@ -268,9 +268,13 @@
 self.frames = []
 self.extended_info = []
 
-if isinstance(scripted_process, ScriptedProcess):
-self.target = scripted_process.target
-self.scripted_process = scripted_process
+if (
+isinstance(process, ScriptedProcess)
+or isinstance(process, lldb.SBProcess)
+and process.IsValid()
+):
+self.target = process.target
+self.originating_process = 

[Lldb-commits] [PATCH] D159314: [lldb] Introduce OperatingSystem{, Python}Interface and make use it

[Med Ismail Bennani via Phabricator via lldb-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7a1e8783586e: [lldb] Introduce 
OperatingSystem{,Python}Interface and make use it (authored by mib).

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Files:
  lldb/include/lldb/Interpreter/Interfaces/OperatingSystemInterface.h
  lldb/include/lldb/Interpreter/ScriptInterpreter.h
  lldb/include/lldb/lldb-forward.h
  lldb/source/Plugins/OperatingSystem/Python/OperatingSystemPython.cpp
  lldb/source/Plugins/OperatingSystem/Python/OperatingSystemPython.h
  lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/CMakeLists.txt
  
lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/OperatingSystemPythonInterface.cpp
  
lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/OperatingSystemPythonInterface.h
  
lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.h
  lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
  lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
  lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp

Index: lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp
===
--- lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp
+++ lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp
@@ -320,6 +320,11 @@
 }
 
 python::PythonObject
-lldb_private::python::SWIGBridge::ToSWIGWrapper(const StructuredDataImpl &) {
+lldb_private::python::SWIGBridge::ToSWIGWrapper(lldb::ProcessSP) {
+  return python::PythonObject();
+}
+
+python::PythonObject lldb_private::python::SWIGBridge::ToSWIGWrapper(
+const lldb_private::StructuredDataImpl &) {
   return python::PythonObject();
 }
Index: lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
===
--- lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
+++ lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
@@ -134,24 +134,9 @@
 
   lldb::ScriptedProcessInterfaceUP CreateScriptedProcessInterface() override;
 
-  StructuredData::GenericSP
-  OSPlugin_CreatePluginObject(const char *class_name,
-  lldb::ProcessSP process_sp) override;
-
-  StructuredData::DictionarySP
-  OSPlugin_RegisterInfo(StructuredData::ObjectSP os_plugin_object_sp) override;
   lldb::ScriptedThreadInterfaceSP CreateScriptedThreadInterface() override;
 
-  StructuredData::ArraySP
-  OSPlugin_ThreadsInfo(StructuredData::ObjectSP os_plugin_object_sp) override;
-
-  StructuredData::StringSP
-  OSPlugin_RegisterContextData(StructuredData::ObjectSP os_plugin_object_sp,
-   lldb::tid_t thread_id) override;
-
-  StructuredData::DictionarySP
-  OSPlugin_CreateThread(StructuredData::ObjectSP os_plugin_object_sp,
-lldb::tid_t tid, lldb::addr_t context) override;
+  lldb::OperatingSystemInterfaceSP CreateOperatingSystemInterface() override;
 
   StructuredData::ObjectSP
   LoadPluginModule(const FileSpec _spec,
Index: lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
===
--- lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
+++ lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
@@ -14,6 +14,7 @@
 // LLDB Python header must be included first
 #include "lldb-python.h"
 
+#include "Interfaces/OperatingSystemPythonInterface.h"
 #include "Interfaces/ScriptedPlatformPythonInterface.h"
 #include "Interfaces/ScriptedProcessPythonInterface.h"
 #include "Interfaces/ScriptedThreadPythonInterface.h"
@@ -1521,6 +1522,11 @@
   return std::make_shared(*this);
 }
 
+OperatingSystemInterfaceSP
+ScriptInterpreterPythonImpl::CreateOperatingSystemInterface() {
+  return std::make_shared(*this);
+}
+
 StructuredData::ObjectSP
 ScriptInterpreterPythonImpl::CreateStructuredDataFromScriptObject(
 ScriptObject obj) {
@@ -1532,159 +1538,6 @@
   return py_obj.CreateStructuredObject();
 }
 
-StructuredData::GenericSP
-ScriptInterpreterPythonImpl::OSPlugin_CreatePluginObject(
-const char *class_name, lldb::ProcessSP process_sp) {
-  if (class_name == nullptr || class_name[0] == '\0')
-return StructuredData::GenericSP();
-
-  if (!process_sp)
-return StructuredData::GenericSP();
-
-  Locker py_lock(this, Locker::AcquireLock | Locker::NoSTDIN, Locker::FreeLock);
-  PythonObject ret_val = SWIGBridge::LLDBSWIGPythonCreateOSPlugin(
-  class_name, m_dictionary_name.c_str(), process_sp);
-
-  return StructuredData::GenericSP(
-  new StructuredPythonObject(std::move(ret_val)));
-}
-
-StructuredData::DictionarySP ScriptInterpreterPythonImpl::OSPlugin_RegisterInfo(
-

[Lldb-commits] [PATCH] D159314: [lldb] Introduce OperatingSystem{, Python}Interface and make use it

[Med Ismail Bennani via Phabricator via lldb-commits]

mib added a comment.

In D159314#4655289 , @bulbazord wrote:

> Ok, makes sense to me. Since this is a refactor, I assume that the current 
> test suite should be enough to cover this change?

@bulbazord yes!


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[Lldb-commits] [PATCH] D159314: [lldb] Introduce OperatingSystem{, Python}Interface and make use it

[Alex Langford via Phabricator via lldb-commits]

bulbazord accepted this revision.
bulbazord added a comment.
This revision is now accepted and ready to land.

Ok, makes sense to me. Since this is a refactor, I assume that the current test 
suite should be enough to cover this change?


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[Lldb-commits] [PATCH] D140996: [c++20] P1907R1: Support for generalized non-type template arguments of scalar type.

[Andrey Ali Khan Bolshakov via Phabricator via lldb-commits]

bolshakov-a added a comment.

Sorry, but I don't know what remains to be done here. It seems that the only 
important question is about ABI, but I've already answered that the changes 
under discussion seem to be already fixed in the Itanium ABI document.


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[Lldb-commits] [PATCH] D140996: [c++20] P1907R1: Support for generalized non-type template arguments of scalar type.

[Aaron Ballman via Phabricator via lldb-commits]

aaron.ballman added a comment.

In D140996#4646880 , @cor3ntin wrote:

> It would be nice to figure out a plan for this PR in the next few weeks, 
> before we get kicked out of Phab!

Agreed -- @bolshakov-a are you still planning to actively work on this patch 
(it's okay if you're not, but in that case, do you mind if someone commandeers 
the patch)? We've got a few weeks left until Phabricator is going into 
read-only mode, so it would be good if we could get this review across the 
finish line before mid-Nov if possible.


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[Lldb-commits] [PATCH] D159127: [lldb][libc++] Adds chrono data formatters.

[Mark de Wever via Phabricator via lldb-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0e4264ab1e7a: [lldb][libc++] Adds chrono data formatters. 
(authored by Mordante).

Repository:
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Files:
  lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
  
lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/Makefile
  
lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/TestDataFormatterLibcxxChrono.py
  
lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/main.cpp

Index: lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/main.cpp
===
--- /dev/null
+++ lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/main.cpp
@@ -0,0 +1,19 @@
+#include 
+#include 
+
+int main() {
+  // break here
+  std::chrono::nanoseconds ns{1};
+  std::chrono::microseconds us{12};
+  std::chrono::milliseconds ms{123};
+  std::chrono::seconds s{1234};
+  std::chrono::minutes min{12345};
+  std::chrono::hours h{123456};
+
+  std::chrono::days d{654321};
+  std::chrono::weeks w{54321};
+  std::chrono::months m{4321};
+  std::chrono::years y{321};
+
+  std::cout << "break here\n";
+}
Index: lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/TestDataFormatterLibcxxChrono.py
===
--- /dev/null
+++ lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/TestDataFormatterLibcxxChrono.py
@@ -0,0 +1,33 @@
+"""
+Test lldb data formatter subsystem.
+"""
+
+
+import lldb
+from lldbsuite.test.decorators import *
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test import lldbutil
+
+
+class LibcxxChronoDataFormatterTestCase(TestBase):
+@add_test_categories(["libc++"])
+def test_with_run_command(self):
+"""Test that that file and class static variables display correctly."""
+self.build()
+(self.target, process, thread, bkpt) = lldbutil.run_to_source_breakpoint(
+self, "break here", lldb.SBFileSpec("main.cpp", False)
+)
+
+lldbutil.continue_to_breakpoint(process, bkpt)
+self.expect("frame variable ns", substrs=["ns = 1 ns"])
+self.expect("frame variable us", substrs=["us = 12 µs"])
+self.expect("frame variable ms", substrs=["ms = 123 ms"])
+self.expect("frame variable s", substrs=["s = 1234 s"])
+self.expect("frame variable min", substrs=["min = 12345 min"])
+self.expect("frame variable h", substrs=["h = 123456 h"])
+
+self.expect("frame variable d", substrs=["d = 654321 days"])
+self.expect("frame variable w", substrs=["w = 54321 weeks"])
+self.expect("frame variable m", substrs=["m = 4321 months"])
+self.expect("frame variable y", substrs=["y = 321 years"])
+
Index: lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/Makefile
===
--- /dev/null
+++ lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/Makefile
@@ -0,0 +1,6 @@
+CXX_SOURCES := main.cpp
+
+USE_LIBCPP := 1
+
+CXXFLAGS_EXTRAS := -std=c++20
+include Makefile.rules
Index: lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
===
--- lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
+++ lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
@@ -979,6 +979,57 @@
   "std::unordered_map iterator synthetic children",
   "^std::__[[:alnum:]]+::__hash_map_(const_)?iterator<.+>$",
   stl_synth_flags, true);
+  // Chrono duration typedefs
+  cpp_category_sp->AddTypeSummary(
+  "^std::__[[:alnum:]]+::chrono::nanoseconds", eFormatterMatchRegex,
+  TypeSummaryImplSP(new StringSummaryFormat(
+  eTypeOptionHideChildren | eTypeOptionHideValue, "${var.__rep_} ns")));
+  cpp_category_sp->AddTypeSummary(
+  "^std::__[[:alnum:]]+::chrono::microseconds", eFormatterMatchRegex,
+  TypeSummaryImplSP(new StringSummaryFormat(
+  eTypeOptionHideChildren | eTypeOptionHideValue, "${var.__rep_} µs")));
+  cpp_category_sp->AddTypeSummary(
+  "^std::__[[:alnum:]]+::chrono::milliseconds", eFormatterMatchRegex,
+  TypeSummaryImplSP(new StringSummaryFormat(
+  eTypeOptionHideChildren | eTypeOptionHideValue, "${var.__rep_} ms")));
+  cpp_category_sp->AddTypeSummary(
+  "^std::__[[:alnum:]]+::chrono::seconds", eFormatterMatchRegex,
+  TypeSummaryImplSP(new StringSummaryFormat(
+  eTypeOptionHideChildren | eTypeOptionHideValue, "${var.__rep_} s")));
+  

[Lldb-commits] [PATCH] D159127: [lldb][libc++] Adds chrono data formatters.

[Mark de Wever via Phabricator via lldb-commits]

Mordante added a comment.

In D159127#4654774 , @Michael137 
wrote:

> Was looking at leftover reviews, would be nice to land this

Thanks for the review!


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[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Aditya Kumar via Phabricator via lldb-commits]

hiraditya added a comment.
Herald added subscribers: wangpc, jobnoorman, luke.

We should close this as it has been pushed upstream as part of 
https://reviews.llvm.org/rG847de9c332775d1841fec9fea5cb5c41592a4c8f


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[Lldb-commits] [PATCH] D159314: [lldb] Introduce OperatingSystem{, Python}Interface and make use it

[Med Ismail Bennani via Phabricator via lldb-commits]

mib added a comment.

Since @bulbazord asked me offline, all the repeat it here: Everything that was 
deleted here was replaced by either a call to the existing 
`ScriptedPythonInterface::Dispatch` method or depends on the new way to create 
scripted plugin objects .




Comment at: 
lldb/source/Plugins/OperatingSystem/Python/OperatingSystemPython.cpp:112-114
+//return llvm::createStringError(
+//llvm::inconvertibleErrorCode(),
+//"Failed to create scripted thread interface.");

bulbazord wrote:
> nit: Remove commented out code.
> 
> side note, maybe OperatingSystemPython should have a static factory method so 
> we can actually return a meaningful error like this? Since the constructor 
> can fail, we might end up with a half-initialized object. Doesn't have to be 
> in this change, I think it would make sense for a follow-up.
I added a `// FIXME:` and I'll do the error handling in a followup.


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[Lldb-commits] [PATCH] D159314: [lldb] Introduce OperatingSystem{, Python}Interface and make us it

[Med Ismail Bennani via Phabricator via lldb-commits]

mib updated this revision to Diff 557856.
mib marked 2 inline comments as done.
mib added a comment.

Address @bulbazord comments.


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Files:
  lldb/include/lldb/Interpreter/Interfaces/OperatingSystemInterface.h
  lldb/include/lldb/Interpreter/ScriptInterpreter.h
  lldb/include/lldb/lldb-forward.h
  lldb/source/Plugins/OperatingSystem/Python/OperatingSystemPython.cpp
  lldb/source/Plugins/OperatingSystem/Python/OperatingSystemPython.h
  lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/CMakeLists.txt
  
lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/OperatingSystemPythonInterface.cpp
  
lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/OperatingSystemPythonInterface.h
  
lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.h
  lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
  lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
  lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp

Index: lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp
===
--- lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp
+++ lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp
@@ -320,6 +320,11 @@
 }
 
 python::PythonObject
-lldb_private::python::SWIGBridge::ToSWIGWrapper(const StructuredDataImpl &) {
+lldb_private::python::SWIGBridge::ToSWIGWrapper(lldb::ProcessSP) {
+  return python::PythonObject();
+}
+
+python::PythonObject lldb_private::python::SWIGBridge::ToSWIGWrapper(
+const lldb_private::StructuredDataImpl &) {
   return python::PythonObject();
 }
Index: lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
===
--- lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
+++ lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
@@ -134,24 +134,9 @@
 
   lldb::ScriptedProcessInterfaceUP CreateScriptedProcessInterface() override;
 
-  StructuredData::GenericSP
-  OSPlugin_CreatePluginObject(const char *class_name,
-  lldb::ProcessSP process_sp) override;
-
-  StructuredData::DictionarySP
-  OSPlugin_RegisterInfo(StructuredData::ObjectSP os_plugin_object_sp) override;
   lldb::ScriptedThreadInterfaceSP CreateScriptedThreadInterface() override;
 
-  StructuredData::ArraySP
-  OSPlugin_ThreadsInfo(StructuredData::ObjectSP os_plugin_object_sp) override;
-
-  StructuredData::StringSP
-  OSPlugin_RegisterContextData(StructuredData::ObjectSP os_plugin_object_sp,
-   lldb::tid_t thread_id) override;
-
-  StructuredData::DictionarySP
-  OSPlugin_CreateThread(StructuredData::ObjectSP os_plugin_object_sp,
-lldb::tid_t tid, lldb::addr_t context) override;
+  lldb::OperatingSystemInterfaceSP CreateOperatingSystemInterface() override;
 
   StructuredData::ObjectSP
   LoadPluginModule(const FileSpec _spec,
Index: lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
===
--- lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
+++ lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
@@ -14,6 +14,7 @@
 // LLDB Python header must be included first
 #include "lldb-python.h"
 
+#include "Interfaces/OperatingSystemPythonInterface.h"
 #include "Interfaces/ScriptedPlatformPythonInterface.h"
 #include "Interfaces/ScriptedProcessPythonInterface.h"
 #include "Interfaces/ScriptedThreadPythonInterface.h"
@@ -1521,6 +1522,11 @@
   return std::make_shared(*this);
 }
 
+OperatingSystemInterfaceSP
+ScriptInterpreterPythonImpl::CreateOperatingSystemInterface() {
+  return std::make_shared(*this);
+}
+
 StructuredData::ObjectSP
 ScriptInterpreterPythonImpl::CreateStructuredDataFromScriptObject(
 ScriptObject obj) {
@@ -1532,159 +1538,6 @@
   return py_obj.CreateStructuredObject();
 }
 
-StructuredData::GenericSP
-ScriptInterpreterPythonImpl::OSPlugin_CreatePluginObject(
-const char *class_name, lldb::ProcessSP process_sp) {
-  if (class_name == nullptr || class_name[0] == '\0')
-return StructuredData::GenericSP();
-
-  if (!process_sp)
-return StructuredData::GenericSP();
-
-  Locker py_lock(this, Locker::AcquireLock | Locker::NoSTDIN, Locker::FreeLock);
-  PythonObject ret_val = SWIGBridge::LLDBSWIGPythonCreateOSPlugin(
-  class_name, m_dictionary_name.c_str(), process_sp);
-
-  return StructuredData::GenericSP(
-  new StructuredPythonObject(std::move(ret_val)));
-}
-
-StructuredData::DictionarySP ScriptInterpreterPythonImpl::OSPlugin_RegisterInfo(
-StructuredData::ObjectSP os_plugin_object_sp) {
-  Locker py_lock(this, Locker::AcquireLock | Locker::NoSTDIN, Locker::FreeLock);
-
-  if (!os_plugin_object_sp)
-

[Lldb-commits] [PATCH] D158833: [lldb] Move ScriptInterpreter Interfaces to subdirectory (NFC)

[Med Ismail Bennani via Phabricator via lldb-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG77374d3b53ce: [lldb] Move ScriptInterpreter Interfaces to 
subdirectory (NFC) (authored by mib).

Changed prior to commit:
  https://reviews.llvm.org/D158833?vs=554991=557844#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158833/new/

https://reviews.llvm.org/D158833

Files:
  lldb/include/lldb/Interpreter/Interfaces/ScriptedInterface.h
  lldb/include/lldb/Interpreter/Interfaces/ScriptedPlatformInterface.h
  lldb/include/lldb/Interpreter/Interfaces/ScriptedProcessInterface.h
  lldb/include/lldb/Interpreter/Interfaces/ScriptedThreadInterface.h
  lldb/include/lldb/Interpreter/ScriptInterpreter.h
  lldb/include/lldb/Interpreter/ScriptedInterface.h
  lldb/include/lldb/Interpreter/ScriptedPlatformInterface.h
  lldb/include/lldb/Interpreter/ScriptedProcessInterface.h
  lldb/source/Plugins/ScriptInterpreter/Python/CMakeLists.txt
  lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/CMakeLists.txt
  
lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPlatformPythonInterface.cpp
  
lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPlatformPythonInterface.h
  
lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface.cpp
  
lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface.h
  
lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.cpp
  
lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.h
  
lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.cpp
  
lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.h
  lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
  lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
  
lldb/source/Plugins/ScriptInterpreter/Python/ScriptedPlatformPythonInterface.cpp
  lldb/source/Plugins/ScriptInterpreter/Python/ScriptedPlatformPythonInterface.h
  
lldb/source/Plugins/ScriptInterpreter/Python/ScriptedProcessPythonInterface.cpp
  lldb/source/Plugins/ScriptInterpreter/Python/ScriptedProcessPythonInterface.h
  lldb/source/Plugins/ScriptInterpreter/Python/ScriptedPythonInterface.cpp
  lldb/source/Plugins/ScriptInterpreter/Python/ScriptedPythonInterface.h
  lldb/source/Plugins/ScriptInterpreter/Python/ScriptedThreadPythonInterface.cpp
  lldb/source/Plugins/ScriptInterpreter/Python/ScriptedThreadPythonInterface.h

Index: lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
===
--- lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
+++ lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
@@ -140,6 +140,7 @@
 
   StructuredData::DictionarySP
   OSPlugin_RegisterInfo(StructuredData::ObjectSP os_plugin_object_sp) override;
+  lldb::ScriptedThreadInterfaceSP CreateScriptedThreadInterface() override;
 
   StructuredData::ArraySP
   OSPlugin_ThreadsInfo(StructuredData::ObjectSP os_plugin_object_sp) override;
Index: lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
===
--- lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
+++ lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
@@ -14,12 +14,13 @@
 // LLDB Python header must be included first
 #include "lldb-python.h"
 
+#include "Interfaces/ScriptedPlatformPythonInterface.h"
+#include "Interfaces/ScriptedProcessPythonInterface.h"
+#include "Interfaces/ScriptedThreadPythonInterface.h"
 #include "PythonDataObjects.h"
 #include "PythonReadline.h"
 #include "SWIGPythonBridge.h"
 #include "ScriptInterpreterPythonImpl.h"
-#include "ScriptedPlatformPythonInterface.h"
-#include "ScriptedProcessPythonInterface.h"
 
 #include "lldb/API/SBError.h"
 #include "lldb/API/SBFrame.h"
@@ -1515,6 +1516,11 @@
   return std::make_unique(*this);
 }
 
+ScriptedThreadInterfaceSP
+ScriptInterpreterPythonImpl::CreateScriptedThreadInterface() {
+  return std::make_shared(*this);
+}
+
 StructuredData::ObjectSP
 ScriptInterpreterPythonImpl::CreateStructuredDataFromScriptObject(
 ScriptObject obj) {
Index: lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.h
===
--- lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.h
+++ lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.h
@@ -6,15 +6,15 @@
 //
 //===--===//
 
-#ifndef LLDB_PLUGINS_SCRIPTINTERPRETER_PYTHON_SCRIPTEDTHREADPYTHONINTERFACE_H
-#define 

[Lldb-commits] [PATCH] D159310: [lldb] Move template python files to separate directory

[Med Ismail Bennani via Phabricator via lldb-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG6bff2d51dcc7: [lldb] Move template python files to separate 
directory (authored by mib).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159310/new/

https://reviews.llvm.org/D159310

Files:
  lldb/bindings/python/CMakeLists.txt
  lldb/examples/python/crashlog_scripted_process.py
  lldb/examples/python/scripted_process/crashlog_scripted_process.py
  lldb/examples/python/scripted_process/scripted_platform.py
  lldb/examples/python/scripted_process/scripted_process.py
  lldb/examples/python/templates/scripted_platform.py
  lldb/examples/python/templates/scripted_process.py


Index: lldb/bindings/python/CMakeLists.txt
===
--- lldb/bindings/python/CMakeLists.txt
+++ lldb/bindings/python/CMakeLists.txt
@@ -103,15 +103,15 @@
 ${lldb_python_target_dir}
 "plugins"
 FILES
-"${LLDB_SOURCE_DIR}/examples/python/scripted_process/scripted_process.py"
-"${LLDB_SOURCE_DIR}/examples/python/scripted_process/scripted_platform.py")
+"${LLDB_SOURCE_DIR}/examples/python/templates/scripted_process.py"
+"${LLDB_SOURCE_DIR}/examples/python/templates/scripted_platform.py")
 
   if(APPLE)
 create_python_package(
   ${swig_target}
   ${lldb_python_target_dir} "macosx"
   FILES "${LLDB_SOURCE_DIR}/examples/python/crashlog.py"
-
"${LLDB_SOURCE_DIR}/examples/python/scripted_process/crashlog_scripted_process.py"
+"${LLDB_SOURCE_DIR}/examples/python/crashlog_scripted_process.py"
 "${LLDB_SOURCE_DIR}/examples/darwin/heap_find/heap.py")
 
 create_python_package(


Index: lldb/bindings/python/CMakeLists.txt
===
--- lldb/bindings/python/CMakeLists.txt
+++ lldb/bindings/python/CMakeLists.txt
@@ -103,15 +103,15 @@
 ${lldb_python_target_dir}
 "plugins"
 FILES
-"${LLDB_SOURCE_DIR}/examples/python/scripted_process/scripted_process.py"
-"${LLDB_SOURCE_DIR}/examples/python/scripted_process/scripted_platform.py")
+"${LLDB_SOURCE_DIR}/examples/python/templates/scripted_process.py"
+"${LLDB_SOURCE_DIR}/examples/python/templates/scripted_platform.py")
 
   if(APPLE)
 create_python_package(
   ${swig_target}
   ${lldb_python_target_dir} "macosx"
   FILES "${LLDB_SOURCE_DIR}/examples/python/crashlog.py"
-"${LLDB_SOURCE_DIR}/examples/python/scripted_process/crashlog_scripted_process.py"
+"${LLDB_SOURCE_DIR}/examples/python/crashlog_scripted_process.py"
 "${LLDB_SOURCE_DIR}/examples/darwin/heap_find/heap.py")
 
 create_python_package(
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[Lldb-commits] [PATCH] D159127: [lldb][libc++] Adds chrono data formatters.

[Michael Buch via Phabricator via lldb-commits]

Michael137 accepted this revision.
Michael137 added a comment.
This revision is now accepted and ready to land.

Was looking at leftover reviews, would be nice to land this


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[Lldb-commits] [PATCH] D151919: [lldb][NFCI] Apply IndexEntry to DWARFUnitHeader outside of extraction

[Alex Langford via Phabricator via lldb-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGdd76375c8009: [lldb][NFCI] Apply IndexEntry to 
DWARFUnitHeader outside of extraction (authored by bulbazord).

Changed prior to commit:
  https://reviews.llvm.org/D151919?vs=529769=557568#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151919/new/

https://reviews.llvm.org/D151919

Files:
  lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
  lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h

Index: lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
===
--- lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
+++ lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
@@ -76,6 +76,8 @@
   }
   uint32_t GetNextUnitOffset() const { return m_offset + m_length + 4; }
 
+  llvm::Error ApplyIndexEntry(const llvm::DWARFUnitIndex::Entry *index_entry);
+
   static llvm::Expected
   extract(const lldb_private::DWARFDataExtractor , DIERef::Section section,
   lldb_private::DWARFContext _context,
Index: lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
===
--- lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
+++ lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
@@ -877,11 +877,37 @@
   return *m_func_aranges_up;
 }
 
-llvm::Expected
-DWARFUnitHeader::extract(const DWARFDataExtractor ,
- DIERef::Section section,
- lldb_private::DWARFContext ,
- lldb::offset_t *offset_ptr) {
+llvm::Error DWARFUnitHeader::ApplyIndexEntry(
+const llvm::DWARFUnitIndex::Entry *index_entry) {
+  // We should only be calling this function when the index entry is not set and
+  // we have a valid one to set it to.
+  assert(index_entry);
+  assert(!m_index_entry);
+
+  if (m_abbr_offset)
+return llvm::createStringError(
+llvm::inconvertibleErrorCode(),
+"Package unit with a non-zero abbreviation offset");
+
+  auto *unit_contrib = index_entry->getContribution();
+  if (!unit_contrib || unit_contrib->getLength32() != m_length + 4)
+return llvm::createStringError(llvm::inconvertibleErrorCode(),
+   "Inconsistent DWARF package unit index");
+
+  auto *abbr_entry = index_entry->getContribution(llvm::DW_SECT_ABBREV);
+  if (!abbr_entry)
+return llvm::createStringError(
+llvm::inconvertibleErrorCode(),
+"DWARF package index missing abbreviation column");
+
+  m_abbr_offset = abbr_entry->getOffset();
+  m_index_entry = index_entry;
+  return llvm::Error::success();
+}
+
+llvm::Expected DWARFUnitHeader::extract(
+const DWARFDataExtractor , DIERef::Section section,
+lldb_private::DWARFContext , lldb::offset_t *offset_ptr) {
   DWARFUnitHeader header;
   header.m_offset = *offset_ptr;
   header.m_length = data.GetDWARFInitialLength(offset_ptr);
@@ -905,42 +931,6 @@
 header.m_type_offset = data.GetDWARFOffset(offset_ptr);
   }
 
-  if (context.isDwo()) {
-const llvm::DWARFUnitIndex *Index;
-if (header.IsTypeUnit()) {
-  Index = ().getTUIndex();
-  if (*Index)
-header.m_index_entry = Index->getFromHash(header.m_type_hash);
-} else {
-  Index = ().getCUIndex();
-  if (*Index && header.m_version >= 5 && header.m_dwo_id)
-header.m_index_entry = Index->getFromHash(*header.m_dwo_id);
-}
-if (!header.m_index_entry)
-  header.m_index_entry = Index->getFromOffset(header.m_offset);
-  }
-
-  if (header.m_index_entry) {
-if (header.m_abbr_offset) {
-  return llvm::createStringError(
-  llvm::inconvertibleErrorCode(),
-  "Package unit with a non-zero abbreviation offset");
-}
-auto *unit_contrib = header.m_index_entry->getContribution();
-if (!unit_contrib || unit_contrib->getLength32() != header.m_length + 4) {
-  return llvm::createStringError(llvm::inconvertibleErrorCode(),
- "Inconsistent DWARF package unit index");
-}
-auto *abbr_entry =
-header.m_index_entry->getContribution(llvm::DW_SECT_ABBREV);
-if (!abbr_entry) {
-  return llvm::createStringError(
-  llvm::inconvertibleErrorCode(),
-  "DWARF package index missing abbreviation column");
-}
-header.m_abbr_offset = abbr_entry->getOffset();
-  }
-
   bool length_OK = data.ValidOffset(header.GetNextUnitOffset() - 1);
   bool version_OK = SymbolFileDWARF::SupportedVersion(header.m_version);
   bool addr_size_OK = (header.m_addr_size == 2) || (header.m_addr_size == 4) ||
@@ -970,11 +960,30 @@
DIERef::Section section, lldb::offset_t *offset_ptr) {
   assert(debug_info.ValidOffset(*offset_ptr));
 
-  auto expected_header = DWARFUnitHeader::extract(
-  debug_info, section, dwarf.GetDWARFContext(), offset_ptr);
+  DWARFContext  = dwarf.GetDWARFContext();
+  auto expected_header =
+  

[Lldb-commits] [PATCH] D159550: Remove unused #include

[Ted Woodward via Phabricator via lldb-commits]

ted added a subscriber: jasonmolenda.
ted added a comment.

Remove unused #include pointed out by @jasonmolenda in D159101 



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[Lldb-commits] [PATCH] D159550: Remove unused #include

[Ted Woodward via Phabricator via lldb-commits]

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb14153490134: Remove unused #include (authored by ted).
Herald added a subscriber: JDevlieghere.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D159550

Files:
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h


Index: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
===
--- lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
+++ lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
@@ -10,8 +10,6 @@
 #define liblldb_ABISysV_riscv_h_
 
 // Other libraries and framework includes
-#include 
-
 #include "llvm/TargetParser/Triple.h"
 
 // Project includes


Index: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
===
--- lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
+++ lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
@@ -10,8 +10,6 @@
 #define liblldb_ABISysV_riscv_h_
 
 // Other libraries and framework includes
-#include 
-
 #include "llvm/TargetParser/Triple.h"
 
 // Project includes
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[Lldb-commits] [PATCH] D159550: Remove unused #include

[Ted Woodward via Phabricator via lldb-commits]

ted created this revision.
Herald added subscribers: luke, sunshaoce, frasercrmck, luismarques, apazos, 
sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, 
simoncook, johnrusso, rbar, asb.
Herald added a project: All.
ted requested review of this revision.
Herald added subscribers: lldb-commits, wangpc, MaskRay.
Herald added a project: LLDB.

Repository:
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https://reviews.llvm.org/D159550

Files:
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h


Index: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
===
--- lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
+++ lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
@@ -10,8 +10,6 @@
 #define liblldb_ABISysV_riscv_h_
 
 // Other libraries and framework includes
-#include 
-
 #include "llvm/TargetParser/Triple.h"
 
 // Project includes


Index: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
===
--- lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
+++ lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
@@ -10,8 +10,6 @@
 #define liblldb_ABISysV_riscv_h_
 
 // Other libraries and framework includes
-#include 
-
 #include "llvm/TargetParser/Triple.h"
 
 // Project includes
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[Lldb-commits] [PATCH] D159101: [RISC-V] Add RISC-V ABI plugin

[Ted Woodward via Phabricator via lldb-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG847de9c33277: [RISC-V] Add RISC-V ABI plugin (authored by 
ted).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159101/new/

https://reviews.llvm.org/D159101

Files:
  lldb/source/Plugins/ABI/CMakeLists.txt
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
  lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
  lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp

Index: lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
===
--- lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+++ lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
@@ -1576,6 +1576,8 @@
 ArchSpec::eRISCV_float_abi_quad)
   features_str += "+f,+d,+q,";
 // FIXME: how do we detect features such as `+a`, `+m`?
+// Turn them on by default now, since everyone seems to use them
+features_str += "+a,+m,";
   }
 
   // We use m_disasm_up.get() to tell whether we are valid or not, so if this
Index: lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
@@ -0,0 +1,12 @@
+add_lldb_library(lldbPluginABIRISCV PLUGIN
+  ABISysV_riscv.cpp
+
+  LINK_LIBS
+lldbCore
+lldbSymbol
+lldbTarget
+lldbPluginProcessUtility
+  LINK_COMPONENTS
+Support
+TargetParser
+  )
Index: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
@@ -0,0 +1,131 @@
+//===-- ABISysV_riscv.h -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef liblldb_ABISysV_riscv_h_
+#define liblldb_ABISysV_riscv_h_
+
+// Other libraries and framework includes
+#include 
+
+#include "llvm/TargetParser/Triple.h"
+
+// Project includes
+#include "lldb/Target/ABI.h"
+#include "lldb/Target/Process.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-private.h"
+
+class ABISysV_riscv : public lldb_private::RegInfoBasedABI {
+public:
+  ~ABISysV_riscv() override = default;
+
+  size_t GetRedZoneSize() const override { return 0; }
+
+  bool PrepareTrivialCall(lldb_private::Thread , lldb::addr_t sp,
+  lldb::addr_t functionAddress,
+  lldb::addr_t returnAddress,
+  llvm::ArrayRef args) const override;
+
+  // Special thread plan for GDB style non-jit function calls.
+  bool
+  PrepareTrivialCall(lldb_private::Thread , lldb::addr_t sp,
+ lldb::addr_t functionAddress, lldb::addr_t returnAddress,
+ llvm::Type ,
+ llvm::ArrayRef args) const override;
+
+  bool GetArgumentValues(lldb_private::Thread ,
+ lldb_private::ValueList ) const override;
+
+  lldb_private::Status
+  SetReturnValueObject(lldb::StackFrameSP _sp,
+   lldb::ValueObjectSP _value) override;
+
+  lldb::ValueObjectSP
+  GetReturnValueObjectImpl(lldb_private::Thread ,
+   lldb_private::CompilerType ) const override;
+
+  // Specialized to work with llvm IR types.
+  lldb::ValueObjectSP GetReturnValueObjectImpl(lldb_private::Thread ,
+   llvm::Type ) const override;
+
+  bool
+  CreateFunctionEntryUnwindPlan(lldb_private::UnwindPlan _plan) override;
+
+  bool CreateDefaultUnwindPlan(lldb_private::UnwindPlan _plan) override;
+
+  bool RegisterIsVolatile(const lldb_private::RegisterInfo *reg_info) override;
+
+  bool CallFrameAddressIsValid(lldb::addr_t cfa) override {
+// The CFA must be 128 bit aligned, unless the E ABI is used
+lldb_private::ArchSpec arch = GetProcessSP()->GetTarget().GetArchitecture();
+lldb_private::Flags arch_flags = arch.GetFlags();
+if (arch_flags.Test(lldb_private::ArchSpec::eRISCV_rve))
+  return (cfa & 0x3ull) == 0;
+return (cfa & 0xfull) == 0;
+  }
+
+  void SetIsRV64(bool is_rv64) { m_is_rv64 = is_rv64; }
+
+  bool CodeAddressIsValid(lldb::addr_t pc) override {
+// Calls can use the least significant bit to store auxiliary information,
+// so no strict check is done for alignment.
+
+lldb_private::ArchSpec arch = GetProcessSP()->GetTarget().GetArchitecture();
+
+//  & 2 set is a fault if C extension is not used.
+lldb_private::Flags arch_flags(arch.GetFlags());
+if 

[Lldb-commits] [PATCH] D159101: [RISC-V] Add RISC-V ABI plugin

[Jason Molenda via Phabricator via lldb-commits]

jasonmolenda accepted this revision.
jasonmolenda added a comment.
This revision is now accepted and ready to land.

This looks good to me, thanks for reviving this and finishing it up.  We should 
land before phabracator is flash frozen, we can iterate issues are found in the 
future.




Comment at: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h:13
+// Other libraries and framework includes
+#include 
+

I don't see this used anywhere.


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[Lldb-commits] [PATCH] D159101: [RISC-V] Add RISC-V ABI plugin

[Ted Woodward via Phabricator via lldb-commits]

ted updated this revision to Diff 557323.
ted marked 4 inline comments as done.
ted added a comment.

Fix comment about "a" registers


Repository:
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Files:
  lldb/source/Plugins/ABI/CMakeLists.txt
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
  lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
  lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp

Index: lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
===
--- lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+++ lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
@@ -1550,6 +1550,8 @@
 ArchSpec::eRISCV_float_abi_quad)
   features_str += "+f,+d,+q,";
 // FIXME: how do we detect features such as `+a`, `+m`?
+// Turn them on by default now, since everyone seems to use them
+features_str += "+a,+m,";
   }
 
   // We use m_disasm_up.get() to tell whether we are valid or not, so if this
Index: lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
@@ -0,0 +1,12 @@
+add_lldb_library(lldbPluginABIRISCV PLUGIN
+  ABISysV_riscv.cpp
+
+  LINK_LIBS
+lldbCore
+lldbSymbol
+lldbTarget
+lldbPluginProcessUtility
+  LINK_COMPONENTS
+Support
+TargetParser
+  )
Index: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
@@ -0,0 +1,131 @@
+//===-- ABISysV_riscv.h -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef liblldb_ABISysV_riscv_h_
+#define liblldb_ABISysV_riscv_h_
+
+// Other libraries and framework includes
+#include 
+
+#include "llvm/TargetParser/Triple.h"
+
+// Project includes
+#include "lldb/Target/ABI.h"
+#include "lldb/Target/Process.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-private.h"
+
+class ABISysV_riscv : public lldb_private::RegInfoBasedABI {
+public:
+  ~ABISysV_riscv() override = default;
+
+  size_t GetRedZoneSize() const override { return 0; }
+
+  bool PrepareTrivialCall(lldb_private::Thread , lldb::addr_t sp,
+  lldb::addr_t functionAddress,
+  lldb::addr_t returnAddress,
+  llvm::ArrayRef args) const override;
+
+  // Special thread plan for GDB style non-jit function calls.
+  bool
+  PrepareTrivialCall(lldb_private::Thread , lldb::addr_t sp,
+ lldb::addr_t functionAddress, lldb::addr_t returnAddress,
+ llvm::Type ,
+ llvm::ArrayRef args) const override;
+
+  bool GetArgumentValues(lldb_private::Thread ,
+ lldb_private::ValueList ) const override;
+
+  lldb_private::Status
+  SetReturnValueObject(lldb::StackFrameSP _sp,
+   lldb::ValueObjectSP _value) override;
+
+  lldb::ValueObjectSP
+  GetReturnValueObjectImpl(lldb_private::Thread ,
+   lldb_private::CompilerType ) const override;
+
+  // Specialized to work with llvm IR types.
+  lldb::ValueObjectSP GetReturnValueObjectImpl(lldb_private::Thread ,
+   llvm::Type ) const override;
+
+  bool
+  CreateFunctionEntryUnwindPlan(lldb_private::UnwindPlan _plan) override;
+
+  bool CreateDefaultUnwindPlan(lldb_private::UnwindPlan _plan) override;
+
+  bool RegisterIsVolatile(const lldb_private::RegisterInfo *reg_info) override;
+
+  bool CallFrameAddressIsValid(lldb::addr_t cfa) override {
+// The CFA must be 128 bit aligned, unless the E ABI is used
+lldb_private::ArchSpec arch = GetProcessSP()->GetTarget().GetArchitecture();
+lldb_private::Flags arch_flags = arch.GetFlags();
+if (arch_flags.Test(lldb_private::ArchSpec::eRISCV_rve))
+  return (cfa & 0x3ull) == 0;
+return (cfa & 0xfull) == 0;
+  }
+
+  void SetIsRV64(bool is_rv64) { m_is_rv64 = is_rv64; }
+
+  bool CodeAddressIsValid(lldb::addr_t pc) override {
+// Calls can use the least significant bit to store auxiliary information,
+// so no strict check is done for alignment.
+
+lldb_private::ArchSpec arch = GetProcessSP()->GetTarget().GetArchitecture();
+
+//  & 2 set is a fault if C extension is not used.
+lldb_private::Flags arch_flags(arch.GetFlags());
+if (!arch_flags.Test(lldb_private::ArchSpec::eRISCV_rvc) && (pc & 2))
+  return false;
+
+// Make sure 64 bit addr_t 

[Lldb-commits] [PATCH] D159101: [RISC-V] Add RISC-V ABI plugin

[Ted Woodward via Phabricator via lldb-commits]

ted updated this revision to Diff 557322.
ted marked 3 inline comments as done.
ted added a comment.

Change "word_size = m_is_rv64 ? 8 : 4" to "word_size = reg_size"


Repository:
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Files:
  lldb/source/Plugins/ABI/CMakeLists.txt
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
  lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
  lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp

Index: lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
===
--- lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+++ lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
@@ -1550,6 +1550,8 @@
 ArchSpec::eRISCV_float_abi_quad)
   features_str += "+f,+d,+q,";
 // FIXME: how do we detect features such as `+a`, `+m`?
+// Turn them on by default now, since everyone seems to use them
+features_str += "+a,+m,";
   }
 
   // We use m_disasm_up.get() to tell whether we are valid or not, so if this
Index: lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
@@ -0,0 +1,12 @@
+add_lldb_library(lldbPluginABIRISCV PLUGIN
+  ABISysV_riscv.cpp
+
+  LINK_LIBS
+lldbCore
+lldbSymbol
+lldbTarget
+lldbPluginProcessUtility
+  LINK_COMPONENTS
+Support
+TargetParser
+  )
Index: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
@@ -0,0 +1,131 @@
+//===-- ABISysV_riscv.h -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef liblldb_ABISysV_riscv_h_
+#define liblldb_ABISysV_riscv_h_
+
+// Other libraries and framework includes
+#include 
+
+#include "llvm/TargetParser/Triple.h"
+
+// Project includes
+#include "lldb/Target/ABI.h"
+#include "lldb/Target/Process.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-private.h"
+
+class ABISysV_riscv : public lldb_private::RegInfoBasedABI {
+public:
+  ~ABISysV_riscv() override = default;
+
+  size_t GetRedZoneSize() const override { return 0; }
+
+  bool PrepareTrivialCall(lldb_private::Thread , lldb::addr_t sp,
+  lldb::addr_t functionAddress,
+  lldb::addr_t returnAddress,
+  llvm::ArrayRef args) const override;
+
+  // Special thread plan for GDB style non-jit function calls.
+  bool
+  PrepareTrivialCall(lldb_private::Thread , lldb::addr_t sp,
+ lldb::addr_t functionAddress, lldb::addr_t returnAddress,
+ llvm::Type ,
+ llvm::ArrayRef args) const override;
+
+  bool GetArgumentValues(lldb_private::Thread ,
+ lldb_private::ValueList ) const override;
+
+  lldb_private::Status
+  SetReturnValueObject(lldb::StackFrameSP _sp,
+   lldb::ValueObjectSP _value) override;
+
+  lldb::ValueObjectSP
+  GetReturnValueObjectImpl(lldb_private::Thread ,
+   lldb_private::CompilerType ) const override;
+
+  // Specialized to work with llvm IR types.
+  lldb::ValueObjectSP GetReturnValueObjectImpl(lldb_private::Thread ,
+   llvm::Type ) const override;
+
+  bool
+  CreateFunctionEntryUnwindPlan(lldb_private::UnwindPlan _plan) override;
+
+  bool CreateDefaultUnwindPlan(lldb_private::UnwindPlan _plan) override;
+
+  bool RegisterIsVolatile(const lldb_private::RegisterInfo *reg_info) override;
+
+  bool CallFrameAddressIsValid(lldb::addr_t cfa) override {
+// The CFA must be 128 bit aligned, unless the E ABI is used
+lldb_private::ArchSpec arch = GetProcessSP()->GetTarget().GetArchitecture();
+lldb_private::Flags arch_flags = arch.GetFlags();
+if (arch_flags.Test(lldb_private::ArchSpec::eRISCV_rve))
+  return (cfa & 0x3ull) == 0;
+return (cfa & 0xfull) == 0;
+  }
+
+  void SetIsRV64(bool is_rv64) { m_is_rv64 = is_rv64; }
+
+  bool CodeAddressIsValid(lldb::addr_t pc) override {
+// Calls can use the least significant bit to store auxiliary information,
+// so no strict check is done for alignment.
+
+lldb_private::ArchSpec arch = GetProcessSP()->GetTarget().GetArchitecture();
+
+//  & 2 set is a fault if C extension is not used.
+lldb_private::Flags arch_flags(arch.GetFlags());
+if (!arch_flags.Test(lldb_private::ArchSpec::eRISCV_rvc) && (pc & 2))
+  return false;

[Lldb-commits] [PATCH] D159101: [RISC-V] Add RISC-V ABI plugin

[Ted Woodward via Phabricator via lldb-commits]

ted updated this revision to Diff 557321.
ted added a comment.

Remove disabling JIT and enabling IR Interpreter function calls, as requested
by Jason Molenda.

Added default unwind plan as suggested by Jason Molenda.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159101/new/

https://reviews.llvm.org/D159101

Files:
  lldb/source/Plugins/ABI/CMakeLists.txt
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
  lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
  lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp

Index: lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
===
--- lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+++ lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
@@ -1550,6 +1550,8 @@
 ArchSpec::eRISCV_float_abi_quad)
   features_str += "+f,+d,+q,";
 // FIXME: how do we detect features such as `+a`, `+m`?
+// Turn them on by default now, since everyone seems to use them
+features_str += "+a,+m,";
   }
 
   // We use m_disasm_up.get() to tell whether we are valid or not, so if this
Index: lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
@@ -0,0 +1,12 @@
+add_lldb_library(lldbPluginABIRISCV PLUGIN
+  ABISysV_riscv.cpp
+
+  LINK_LIBS
+lldbCore
+lldbSymbol
+lldbTarget
+lldbPluginProcessUtility
+  LINK_COMPONENTS
+Support
+TargetParser
+  )
Index: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
@@ -0,0 +1,131 @@
+//===-- ABISysV_riscv.h -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef liblldb_ABISysV_riscv_h_
+#define liblldb_ABISysV_riscv_h_
+
+// Other libraries and framework includes
+#include 
+
+#include "llvm/TargetParser/Triple.h"
+
+// Project includes
+#include "lldb/Target/ABI.h"
+#include "lldb/Target/Process.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-private.h"
+
+class ABISysV_riscv : public lldb_private::RegInfoBasedABI {
+public:
+  ~ABISysV_riscv() override = default;
+
+  size_t GetRedZoneSize() const override { return 0; }
+
+  bool PrepareTrivialCall(lldb_private::Thread , lldb::addr_t sp,
+  lldb::addr_t functionAddress,
+  lldb::addr_t returnAddress,
+  llvm::ArrayRef args) const override;
+
+  // Special thread plan for GDB style non-jit function calls.
+  bool
+  PrepareTrivialCall(lldb_private::Thread , lldb::addr_t sp,
+ lldb::addr_t functionAddress, lldb::addr_t returnAddress,
+ llvm::Type ,
+ llvm::ArrayRef args) const override;
+
+  bool GetArgumentValues(lldb_private::Thread ,
+ lldb_private::ValueList ) const override;
+
+  lldb_private::Status
+  SetReturnValueObject(lldb::StackFrameSP _sp,
+   lldb::ValueObjectSP _value) override;
+
+  lldb::ValueObjectSP
+  GetReturnValueObjectImpl(lldb_private::Thread ,
+   lldb_private::CompilerType ) const override;
+
+  // Specialized to work with llvm IR types.
+  lldb::ValueObjectSP GetReturnValueObjectImpl(lldb_private::Thread ,
+   llvm::Type ) const override;
+
+  bool
+  CreateFunctionEntryUnwindPlan(lldb_private::UnwindPlan _plan) override;
+
+  bool CreateDefaultUnwindPlan(lldb_private::UnwindPlan _plan) override;
+
+  bool RegisterIsVolatile(const lldb_private::RegisterInfo *reg_info) override;
+
+  bool CallFrameAddressIsValid(lldb::addr_t cfa) override {
+// The CFA must be 128 bit aligned, unless the E ABI is used
+lldb_private::ArchSpec arch = GetProcessSP()->GetTarget().GetArchitecture();
+lldb_private::Flags arch_flags = arch.GetFlags();
+if (arch_flags.Test(lldb_private::ArchSpec::eRISCV_rve))
+  return (cfa & 0x3ull) == 0;
+return (cfa & 0xfull) == 0;
+  }
+
+  void SetIsRV64(bool is_rv64) { m_is_rv64 = is_rv64; }
+
+  bool CodeAddressIsValid(lldb::addr_t pc) override {
+// Calls can use the least significant bit to store auxiliary information,
+// so no strict check is done for alignment.
+
+lldb_private::ArchSpec arch = GetProcessSP()->GetTarget().GetArchitecture();
+
+//  & 2 set is a fault if C extension is not used.
+lldb_private::Flags arch_flags(arch.GetFlags());
+if 

[Lldb-commits] [PATCH] D159542: Lazy deference underlying object for shared/weak/unique_ptr synthetic provider

[jeffrey tan via Phabricator via lldb-commits]

yinghuitan abandoned this revision.
yinghuitan added a comment.

Abandon to use the github workflow


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[Lldb-commits] [PATCH] D159542: Lazy deference underlying object for shared/weak/unique_ptr synthetic provider

[jeffrey tan via Phabricator via lldb-commits]

yinghuitan created this revision.
yinghuitan added reviewers: clayborg, labath, jingham, jdoerfert, JDevlieghere, 
kusmour, GeorgeHuyubo.
Herald added a project: All.
yinghuitan requested review of this revision.
Herald added subscribers: lldb-commits, wangpc.
Herald added a project: LLDB.

We noticed some performance issue while in lldb-vscode for grabing the name of 
the SBValue. 
Profiling shows SBValue::GetName() can cause synthetic children provider of 
shared/unique_ptr
to deference underlying object and complete it type.

This patch lazily moves the dereference from synthetic child provider's 
Update() method to
GetChildAtIndex() so that SBValue::GetName() won't trigger the slow code path.

Here is the culprit slow code path:

  ...
  frame #59: 0x7ff4102e0660 
liblldb.so.15`SymbolFileDWARF::CompleteType(this=, 
compiler_type=0x7ffdd9829450) at SymbolFileDWARF.cpp:1567:25 [opt]
  ...
  frame #67: 0x7ff40fdf9bd4 
liblldb.so.15`lldb_private::ValueObject::Dereference(this=0x022bb5dfe980, 
error=0x7ffdd9829970) at ValueObject.cpp:2672:41 [opt]
  frame #68: 0x7ff41011bb0a liblldb.so.15`(anonymous 
namespace)::LibStdcppSharedPtrSyntheticFrontEnd::Update(this=0x02298fb94380)
 at LibStdcpp.cpp:403:40 [opt]
  frame #69: 0x7ff41011af9a 
liblldb.so.15`lldb_private::formatters::LibStdcppSharedPtrSyntheticFrontEndCreator(lldb_private::CXXSyntheticChildren*,
 std::shared_ptr) [inlined] (anonymous 
namespace)::LibStdcppSharedPtrSyntheticFrontEnd::LibStdcppSharedPtrSyntheticFrontEnd(this=0x02298fb94380,
 valobj_sp=) at LibStdcpp.cpp:371:5 [opt]
  ...
  frame #78: 0x7ff40fdf6e42 
liblldb.so.15`lldb_private::ValueObject::CalculateSyntheticValue(this=0x02296c66a500)
 at ValueObject.cpp:1836:27 [opt]
  frame #79: 0x7ff40fdf1939 
liblldb.so.15`lldb_private::ValueObject::GetSyntheticValue(this=) 
at ValueObject.cpp:1867:3 [opt]
  frame #80: 0x7ff40fc89008 
liblldb.so.15`ValueImpl::GetSP(this=0x022c71b90de0, 
stop_locker=0x7ffdd9829d00, lock=0x7ffdd9829d08, 
error=0x7ffdd9829d18) at SBValue.cpp:141:46 [opt]
  frame #81: 0x7ff40fc7d82a 
liblldb.so.15`lldb::SBValue::GetSP(ValueLocker&) const [inlined] 
ValueLocker::GetLockedSP(this=0x7ffdd9829d00, in_value=) at 
SBValue.cpp:208:21 [opt]
  frame #82: 0x7ff40fc7d817 
liblldb.so.15`lldb::SBValue::GetSP(this=0x7ffdd9829d90, 
locker=0x7ffdd9829d00) const at SBValue.cpp:1047:17 [opt]
  frame #83: 0x7ff40fc7da6f 
liblldb.so.15`lldb::SBValue::GetName(this=0x7ffdd9829d90) at 
SBValue.cpp:294:32 [opt]
  ...


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D159542

Files:
  lldb/source/Plugins/Language/CPlusPlus/LibStdcpp.cpp
  lldb/source/Plugins/Language/CPlusPlus/LibStdcppUniquePointer.cpp


Index: lldb/source/Plugins/Language/CPlusPlus/LibStdcppUniquePointer.cpp
===
--- lldb/source/Plugins/Language/CPlusPlus/LibStdcppUniquePointer.cpp
+++ lldb/source/Plugins/Language/CPlusPlus/LibStdcppUniquePointer.cpp
@@ -108,14 +108,7 @@
 if (del_obj)
   m_del_obj = del_obj->Clone(ConstString("deleter")).get();
   }
-
-  if (m_ptr_obj) {
-Status error;
-ValueObjectSP obj_obj = m_ptr_obj->Dereference(error);
-if (error.Success()) {
-  m_obj_obj = obj_obj->Clone(ConstString("object")).get();
-}
-  }
+  m_obj_obj = nullptr;
 
   return false;
 }
@@ -128,8 +121,17 @@
 return m_ptr_obj->GetSP();
   if (idx == 1 && m_del_obj)
 return m_del_obj->GetSP();
-  if (idx == 2 && m_obj_obj)
-return m_obj_obj->GetSP();
+  if (idx == 2) {
+if (m_ptr_obj && !m_obj_obj) {
+  Status error;
+  ValueObjectSP obj_obj = m_ptr_obj->Dereference(error);
+  if (error.Success()) {
+m_obj_obj = obj_obj->Clone(ConstString("object")).get();
+  }
+}
+if (m_obj_obj)
+  return m_obj_obj->GetSP();
+  }
   return lldb::ValueObjectSP();
 }
 
Index: lldb/source/Plugins/Language/CPlusPlus/LibStdcpp.cpp
===
--- lldb/source/Plugins/Language/CPlusPlus/LibStdcpp.cpp
+++ lldb/source/Plugins/Language/CPlusPlus/LibStdcpp.cpp
@@ -377,9 +377,16 @@
 LibStdcppSharedPtrSyntheticFrontEnd::GetChildAtIndex(size_t idx) {
   if (idx == 0)
 return m_ptr_obj->GetSP();
-  if (idx == 1)
-return m_obj_obj->GetSP();
-
+  if (idx == 1) {
+if (m_ptr_obj && !m_obj_obj) {
+  Status error;
+  ValueObjectSP obj_obj = m_ptr_obj->Dereference(error);
+  if (error.Success())
+m_obj_obj = obj_obj->Clone(ConstString("object")).get();
+}
+if (m_obj_obj)
+  return m_obj_obj->GetSP();
+  }
   return lldb::ValueObjectSP();
 }
 
@@ -397,14 +404,7 @@
 return false;
 
   m_ptr_obj = ptr_obj_sp->Clone(ConstString("pointer")).get();
-
-  if (m_ptr_obj) {
-Status error;
-ValueObjectSP obj_obj = m_ptr_obj->Dereference(error);
-if (error.Success()) {
-  m_obj_obj = 

[Lldb-commits] [PATCH] D54053: [NativePDB] Add the ability to create clang record decls from mangled names.

[Shafik Yaghmour via Phabricator via lldb-commits]

shafik added a comment.
Herald added a project: All.

Is this PR still relevant or can it be closed?


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[Lldb-commits] [PATCH] D159101: [RISC-V] Add RISC-V ABI plugin

[Ted Woodward via Phabricator via lldb-commits]

ted added inline comments.



Comment at: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp:133
+ABISysV_riscv::CreateInstance(ProcessSP process_sp, const ArchSpec ) {
+  if (process_sp) {
+process_sp->SetCanInterpretFunctionCalls(true);

DavidSpickett wrote:
> Do you know why this check is needed? Is there a specific test that hits this?
> 
> The other ABI plugins seem to sidestep this by not having to `->` on it, but 
> that could just be luck.
Without that check, certain tests crashed when they instantiated the ABI plugin 
without a process.



Comment at: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp:135
+process_sp->SetCanInterpretFunctionCalls(true);
+process_sp->SetCanJIT(false);
+  }

jasonmolenda wrote:
> These should not be set in the ABI, please remove these.  These are probably 
> correct for the qemu environment you're testing against, but if we're 
> connected to a remote stub that can allocate memory (_M packet), we can JIT 
> code. 
I can remove these, but for the current environment they're correct. We don't 
have function calling for JIT, or RuntimeDyld set up for RISC-V.


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[Lldb-commits] [PATCH] D158500: [lldb][AArch64] Linux corefile support for SME

[David Spickett via Phabricator via lldb-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG43812c8c87b1: [lldb][AArch64] Linux corefile support for SME 
(authored by DavidSpickett).

Repository:
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Files:
  lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h
  lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
  lldb/test/API/linux/aarch64/sme_core_file/TestAArch64LinuxSMECoreFile.py
  lldb/test/API/linux/aarch64/sme_core_file/core_0_16_32_1
  lldb/test/API/linux/aarch64/sme_core_file/core_0_32_16_0
  lldb/test/API/linux/aarch64/sme_core_file/core_1_16_32_0
  lldb/test/API/linux/aarch64/sme_core_file/core_1_32_16_1
  lldb/test/API/linux/aarch64/sme_core_file/main.c

Index: lldb/test/API/linux/aarch64/sme_core_file/main.c
===
--- /dev/null
+++ lldb/test/API/linux/aarch64/sme_core_file/main.c
@@ -0,0 +1,140 @@
+// clang-format off
+// Compile with:
+// clang -target aarch64-unknown-linux-gnu main.c -o a.out -g -march=armv8.6-a+sve+sme
+//
+// For minimal corefile size, do this before running the program:
+// echo 0x20 > /proc/self/coredeump_filter
+//
+// Must be run on a system that has SVE and SME, including the smefa64
+// extension. Example command:
+// main 0 32 64 1
+//
+// This would not enter streaming mode, set non-streaming VL to 32
+// bytes, streaming VL to 64 bytes and enable ZA.
+// clang-format on
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#endif
+
+#define SM_INST(c) asm volatile("msr s0_3_c4_c" #c "_3, xzr")
+#define SMSTART_SM SM_INST(3)
+#define SMSTART_ZA SM_INST(5)
+
+void set_sve_registers() {
+  // We assume the smefa64 feature is present, which allows ffr access
+  // in streaming mode.
+  asm volatile("setffr\n\t");
+  asm volatile("ptrue p0.b\n\t");
+  asm volatile("ptrue p1.h\n\t");
+  asm volatile("ptrue p2.s\n\t");
+  asm volatile("ptrue p3.d\n\t");
+  asm volatile("pfalse p4.b\n\t");
+  asm volatile("ptrue p5.b\n\t");
+  asm volatile("ptrue p6.h\n\t");
+  asm volatile("ptrue p7.s\n\t");
+  asm volatile("ptrue p8.d\n\t");
+  asm volatile("pfalse p9.b\n\t");
+  asm volatile("ptrue p10.b\n\t");
+  asm volatile("ptrue p11.h\n\t");
+  asm volatile("ptrue p12.s\n\t");
+  asm volatile("ptrue p13.d\n\t");
+  asm volatile("pfalse p14.b\n\t");
+  asm volatile("ptrue p15.b\n\t");
+
+  asm volatile("cpy  z0.b, p0/z, #1\n\t");
+  asm volatile("cpy  z1.b, p5/z, #2\n\t");
+  asm volatile("cpy  z2.b, p10/z, #3\n\t");
+  asm volatile("cpy  z3.b, p15/z, #4\n\t");
+  asm volatile("cpy  z4.b, p0/z, #5\n\t");
+  asm volatile("cpy  z5.b, p5/z, #6\n\t");
+  asm volatile("cpy  z6.b, p10/z, #7\n\t");
+  asm volatile("cpy  z7.b, p15/z, #8\n\t");
+  asm volatile("cpy  z8.b, p0/z, #9\n\t");
+  asm volatile("cpy  z9.b, p5/z, #10\n\t");
+  asm volatile("cpy  z10.b, p10/z, #11\n\t");
+  asm volatile("cpy  z11.b, p15/z, #12\n\t");
+  asm volatile("cpy  z12.b, p0/z, #13\n\t");
+  asm volatile("cpy  z13.b, p5/z, #14\n\t");
+  asm volatile("cpy  z14.b, p10/z, #15\n\t");
+  asm volatile("cpy  z15.b, p15/z, #16\n\t");
+  asm volatile("cpy  z16.b, p0/z, #17\n\t");
+  asm volatile("cpy  z17.b, p5/z, #18\n\t");
+  asm volatile("cpy  z18.b, p10/z, #19\n\t");
+  asm volatile("cpy  z19.b, p15/z, #20\n\t");
+  asm volatile("cpy  z20.b, p0/z, #21\n\t");
+  asm volatile("cpy  z21.b, p5/z, #22\n\t");
+  asm volatile("cpy  z22.b, p10/z, #23\n\t");
+  asm volatile("cpy  z23.b, p15/z, #24\n\t");
+  asm volatile("cpy  z24.b, p0/z, #25\n\t");
+  asm volatile("cpy  z25.b, p5/z, #26\n\t");
+  asm volatile("cpy  z26.b, p10/z, #27\n\t");
+  asm volatile("cpy  z27.b, p15/z, #28\n\t");
+  asm volatile("cpy  z28.b, p0/z, #29\n\t");
+  asm volatile("cpy  z29.b, p5/z, #30\n\t");
+  asm volatile("cpy  z30.b, p10/z, #31\n\t");
+  asm volatile("cpy  z31.b, p15/z, #32\n\t");
+}
+
+void set_za_register(int streaming_vl) {
+#define MAX_VL_BYTES 256
+  uint8_t data[MAX_VL_BYTES];
+
+  for (unsigned i = 0; i < streaming_vl; ++i) {
+for (unsigned j = 0; j < MAX_VL_BYTES; ++j)
+  data[j] = i + 1;
+asm volatile("mov w12, %w0\n\t"
+ "ldr za[w12, 0], [%1]\n\t" ::"r"(i),
+ "r"()
+ : "w12");
+  }
+}
+
+void set_tpidr2(uint64_t value) {
+  __asm__ volatile("msr S3_3_C13_C0_5, %0" ::"r"(value));
+}
+
+int main(int argc, char **argv) {
+  // Arguments:
+  //  SVE mode: 1 for streaming SVE (SSVE), any other value
+  //  for non-streaming SVE mode.
+  //   Non-Streaming Vector length: In bytes, an integer e.g. "32".
+  //   Streaming Vector length: As above, but for streaming mode.
+  

[Lldb-commits] [PATCH] D158500: [lldb][AArch64] Linux corefile support for SME

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 557171.
DavidSpickett added a comment.

Remove redundant if.


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Files:
  lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h
  lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
  lldb/test/API/linux/aarch64/sme_core_file/TestAArch64LinuxSMECoreFile.py
  lldb/test/API/linux/aarch64/sme_core_file/core_0_16_32_1
  lldb/test/API/linux/aarch64/sme_core_file/core_0_32_16_0
  lldb/test/API/linux/aarch64/sme_core_file/core_1_16_32_0
  lldb/test/API/linux/aarch64/sme_core_file/core_1_32_16_1
  lldb/test/API/linux/aarch64/sme_core_file/main.c

Index: lldb/test/API/linux/aarch64/sme_core_file/main.c
===
--- /dev/null
+++ lldb/test/API/linux/aarch64/sme_core_file/main.c
@@ -0,0 +1,140 @@
+// clang-format off
+// Compile with:
+// clang -target aarch64-unknown-linux-gnu main.c -o a.out -g -march=armv8.6-a+sve+sme
+//
+// For minimal corefile size, do this before running the program:
+// echo 0x20 > /proc/self/coredeump_filter
+//
+// Must be run on a system that has SVE and SME, including the smefa64
+// extension. Example command:
+// main 0 32 64 1
+//
+// This would not enter streaming mode, set non-streaming VL to 32
+// bytes, streaming VL to 64 bytes and enable ZA.
+// clang-format on
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#endif
+
+#define SM_INST(c) asm volatile("msr s0_3_c4_c" #c "_3, xzr")
+#define SMSTART_SM SM_INST(3)
+#define SMSTART_ZA SM_INST(5)
+
+void set_sve_registers() {
+  // We assume the smefa64 feature is present, which allows ffr access
+  // in streaming mode.
+  asm volatile("setffr\n\t");
+  asm volatile("ptrue p0.b\n\t");
+  asm volatile("ptrue p1.h\n\t");
+  asm volatile("ptrue p2.s\n\t");
+  asm volatile("ptrue p3.d\n\t");
+  asm volatile("pfalse p4.b\n\t");
+  asm volatile("ptrue p5.b\n\t");
+  asm volatile("ptrue p6.h\n\t");
+  asm volatile("ptrue p7.s\n\t");
+  asm volatile("ptrue p8.d\n\t");
+  asm volatile("pfalse p9.b\n\t");
+  asm volatile("ptrue p10.b\n\t");
+  asm volatile("ptrue p11.h\n\t");
+  asm volatile("ptrue p12.s\n\t");
+  asm volatile("ptrue p13.d\n\t");
+  asm volatile("pfalse p14.b\n\t");
+  asm volatile("ptrue p15.b\n\t");
+
+  asm volatile("cpy  z0.b, p0/z, #1\n\t");
+  asm volatile("cpy  z1.b, p5/z, #2\n\t");
+  asm volatile("cpy  z2.b, p10/z, #3\n\t");
+  asm volatile("cpy  z3.b, p15/z, #4\n\t");
+  asm volatile("cpy  z4.b, p0/z, #5\n\t");
+  asm volatile("cpy  z5.b, p5/z, #6\n\t");
+  asm volatile("cpy  z6.b, p10/z, #7\n\t");
+  asm volatile("cpy  z7.b, p15/z, #8\n\t");
+  asm volatile("cpy  z8.b, p0/z, #9\n\t");
+  asm volatile("cpy  z9.b, p5/z, #10\n\t");
+  asm volatile("cpy  z10.b, p10/z, #11\n\t");
+  asm volatile("cpy  z11.b, p15/z, #12\n\t");
+  asm volatile("cpy  z12.b, p0/z, #13\n\t");
+  asm volatile("cpy  z13.b, p5/z, #14\n\t");
+  asm volatile("cpy  z14.b, p10/z, #15\n\t");
+  asm volatile("cpy  z15.b, p15/z, #16\n\t");
+  asm volatile("cpy  z16.b, p0/z, #17\n\t");
+  asm volatile("cpy  z17.b, p5/z, #18\n\t");
+  asm volatile("cpy  z18.b, p10/z, #19\n\t");
+  asm volatile("cpy  z19.b, p15/z, #20\n\t");
+  asm volatile("cpy  z20.b, p0/z, #21\n\t");
+  asm volatile("cpy  z21.b, p5/z, #22\n\t");
+  asm volatile("cpy  z22.b, p10/z, #23\n\t");
+  asm volatile("cpy  z23.b, p15/z, #24\n\t");
+  asm volatile("cpy  z24.b, p0/z, #25\n\t");
+  asm volatile("cpy  z25.b, p5/z, #26\n\t");
+  asm volatile("cpy  z26.b, p10/z, #27\n\t");
+  asm volatile("cpy  z27.b, p15/z, #28\n\t");
+  asm volatile("cpy  z28.b, p0/z, #29\n\t");
+  asm volatile("cpy  z29.b, p5/z, #30\n\t");
+  asm volatile("cpy  z30.b, p10/z, #31\n\t");
+  asm volatile("cpy  z31.b, p15/z, #32\n\t");
+}
+
+void set_za_register(int streaming_vl) {
+#define MAX_VL_BYTES 256
+  uint8_t data[MAX_VL_BYTES];
+
+  for (unsigned i = 0; i < streaming_vl; ++i) {
+for (unsigned j = 0; j < MAX_VL_BYTES; ++j)
+  data[j] = i + 1;
+asm volatile("mov w12, %w0\n\t"
+ "ldr za[w12, 0], [%1]\n\t" ::"r"(i),
+ "r"()
+ : "w12");
+  }
+}
+
+void set_tpidr2(uint64_t value) {
+  __asm__ volatile("msr S3_3_C13_C0_5, %0" ::"r"(value));
+}
+
+int main(int argc, char **argv) {
+  // Arguments:
+  //  SVE mode: 1 for streaming SVE (SSVE), any other value
+  //  for non-streaming SVE mode.
+  //   Non-Streaming Vector length: In bytes, an integer e.g. "32".
+  //   Streaming Vector length: As above, but for streaming mode.
+  //   ZA mode: 1 for enabled, any other value for disabled.
+  if (argc != 5)
+return 1;
+
+  // We assume this 

[Lldb-commits] [PATCH] D158500: [lldb][AArch64] Linux corefile support for SME

[Muhammad Omair Javaid via Phabricator via lldb-commits]

omjavaid accepted this revision.
omjavaid added a comment.
This revision is now accepted and ready to land.

This looks good with just one nit above.




Comment at: 
lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp:74
 
-  if (m_register_info_up->IsSVEEnabled())
+  if (m_register_info_up->IsSSVEEnabled()) {
+m_sve_data = getRegset(notes, target_triple, AARCH64_SSVE_Desc);

 if (m_sve_data.GetByteSize() >= sizeof(sve::user_sve_header)) {
below seems redundant because IsSSVEEnabled returns true when
```
  if (ssve_data.GetByteSize() >= sizeof(sve::user_sve_header))
opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskSSVE);
```
has set it enabled. 



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[Lldb-commits] [PATCH] D156774: [lldb][DWARFASTParserClang] Resolve nested types when parsing structures

[Vlad Serebrennikov via Phabricator via lldb-commits]

Endill abandoned this revision.
Endill added a comment.

Moved to GitHub: https://github.com/llvm/llvm-project/pull/66879


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[Lldb-commits] [PATCH] D157609: [lldb] Add more ways to find split DWARF files

[David Blaikie via Phabricator via lldb-commits]

dblaikie added a comment.

In D157609#4645298 , @clayborg wrote:

> In D157609#4644194 , @DavidSpickett 
> wrote:
>
>>> Any chance we could simplify this situation and have dwo searches use 
>>> exactly the same/shared logic as source file searches?
>>
>> I'm not sure what exactly this means, can you clarify?
>>
>> I know that DWP and DWO have different search functions, that could 
>> certainly be unified. Not sure how source files work.
>
> Source file search paths and debug info search paths are different in LLDB. 
> GDB had one setting IIRC that handled both. These settings have been in LLDB 
> for a while so I wouldn't recommend changing this up at this point.

I don't think that's a great motivation to diverge them further.

We could make the DWO search fallback to the source search - and add new 
features to the source search if needed. That'd at least align things a bit 
closer, rather than diverging further.


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[Lldb-commits] [PATCH] D158663: [lldb] Fix stdcpp type summary mistakenly marked as regex (NFC)

[Dave Lee via Phabricator via lldb-commits]

kastiglione added a comment.

Merged in https://github.com/llvm/llvm-project/pull/66949


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[Lldb-commits] [PATCH] D158663: [lldb] Fix stdcpp type summary mistakenly marked as regex (NFC)

[Phabricator via lldb-commits]

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rG56b148aa8d6f: [lldb] Fix stdcpp type summary mistakenly 
marked as regex (NFC) (#66949) (authored by kastiglione, committed by GitHub 
nore...@github.com).

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Files:
  lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp


Index: lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
===
--- lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
+++ lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
@@ -1009,7 +1009,7 @@
   cpp_category_sp->AddTypeSummary("std::string", eFormatterMatchExact,
   std_string_summary_sp);
   cpp_category_sp->AddTypeSummary("std::basic_string",
-  eFormatterMatchRegex, std_string_summary_sp);
+  eFormatterMatchExact, std_string_summary_sp);
   cpp_category_sp->AddTypeSummary(
   "std::basic_string,std::allocator >",
   eFormatterMatchExact, std_string_summary_sp);


Index: lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
===
--- lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
+++ lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
@@ -1009,7 +1009,7 @@
   cpp_category_sp->AddTypeSummary("std::string", eFormatterMatchExact,
   std_string_summary_sp);
   cpp_category_sp->AddTypeSummary("std::basic_string",
-  eFormatterMatchRegex, std_string_summary_sp);
+  eFormatterMatchExact, std_string_summary_sp);
   cpp_category_sp->AddTypeSummary(
   "std::basic_string,std::allocator >",
   eFormatterMatchExact, std_string_summary_sp);
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[Lldb-commits] [PATCH] D156774: [lldb][DWARFASTParserClang] Resolve nested types when parsing structures

[Vlad Serebrennikov via Phabricator via lldb-commits]

Endill added a comment.

@Michael137 I moved this over to GitHub 
, and I need your help there 
writing the unit test.


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[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

[David Spickett via Phabricator via lldb-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGd7fab666955e: [lldb][AArch64] Add SMEs streaming 
vector control register (authored by DavidSpickett).

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  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
  
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py

Index: lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
===
--- lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
+++ lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
@@ -164,6 +164,10 @@
 self.runCmd("register read " + sve_reg_names)
 sve_values = self.res.GetOutput()
 
+svcr_value = 1 if sve_mode == Mode.SSVE else 0
+if za_state == ZA.Enabled:
+svcr_value += 2
+
 def check_regs():
 if za_state == ZA.Enabled:
 self.check_za(start_vl)
@@ -175,6 +179,7 @@
 self.assertEqual(start_vg, self.read_vg())
 
 self.expect("register read " + sve_reg_names, substrs=[sve_values])
+self.expect("register read svcr", substrs=["0x{:016x}".format(svcr_value)])
 
 for expr in exprs:
 expr_cmd = "expression {}()".format(expr)
Index: lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
===
--- lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
+++ lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
@@ -9,7 +9,7 @@
 #define PR_SME_SET_VL 63
 #endif
 
-#define SMSTART() asm volatile("msr  s0_3_c4_c7_3, xzr" /*smstart*/)
+#define SMSTART_SM() asm volatile("msr  s0_3_c4_c3_3, xzr" /*smstart sm*/)
 
 void write_sve_regs() {
   // We assume the smefa64 feature is present, which allows ffr access
@@ -130,18 +130,18 @@
   // Note that doing a syscall brings you back to non-streaming mode, so we
   // don't need to SMSTOP here.
   if (streaming)
-SMSTART();
+SMSTART_SM();
   write_sve_regs_expr();
   prctl(SET_VL_OPT, 8 * 4);
   if (streaming)
-SMSTART();
+SMSTART_SM();
   write_sve_regs_expr();
   return 1;
 }
 
 int main() {
 #ifdef START_SSVE
-  SMSTART();
+  SMSTART_SM();
 #endif
   write_sve_regs();
 
Index: lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
===
--- lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
+++ lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
@@ -24,7 +24,15 @@
 reg_value.GetByteSize(), expected, 'Verify "%s" == %i' % (name, expected)
 )
 
-def check_sve_regs_read(self, z_reg_size):
+def check_sve_regs_read(self, z_reg_size, expected_mode):
+if self.isAArch64SME():
+# This test uses SMSTART SM, which only enables streaming mode,
+# leaving ZA disabled.
+expected_value = "1" if expected_mode == Mode.SSVE else "0"
+self.expect(
+"register read svcr", substrs=["0x000" + expected_value]
+)
+
 p_reg_size = int(z_reg_size / 8)
 
 for i in range(32):
@@ -168,7 +176,7 @@
 
 vg_reg_value = sve_registers.GetChildMemberWithName("vg").GetValueAsUnsigned()
 z_reg_size = vg_reg_value * 8
-self.check_sve_regs_read(z_reg_size)
+self.check_sve_regs_read(z_reg_size, start_mode)
 
 # Evaluate simple expression and print function expr_eval_func address.
 self.expect("expression expr_eval_func", substrs=["= 0x"])
@@ -184,7 +192,7 @@
 
 # We called a jitted function above which must not have changed SVE
 # vector length or register values.
-self.check_sve_regs_read(z_reg_size)
+self.check_sve_regs_read(z_reg_size, start_mode)
 
 self.check_sve_regs_read_after_write(z_reg_size)
 
Index: 

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

[Muhammad Omair Javaid via Phabricator via lldb-commits]

omjavaid accepted this revision.
omjavaid added a comment.
This revision is now accepted and ready to land.

This is good too. Thanks!!!


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[Lldb-commits] [PATCH] D158500: [lldb][AArch64] Linux corefile support for SME

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 557101.
DavidSpickett added a comment.

Rebase


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Files:
  lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h
  lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
  lldb/test/API/linux/aarch64/sme_core_file/TestAArch64LinuxSMECoreFile.py
  lldb/test/API/linux/aarch64/sme_core_file/core_0_16_32_1
  lldb/test/API/linux/aarch64/sme_core_file/core_0_32_16_0
  lldb/test/API/linux/aarch64/sme_core_file/core_1_16_32_0
  lldb/test/API/linux/aarch64/sme_core_file/core_1_32_16_1
  lldb/test/API/linux/aarch64/sme_core_file/main.c

Index: lldb/test/API/linux/aarch64/sme_core_file/main.c
===
--- /dev/null
+++ lldb/test/API/linux/aarch64/sme_core_file/main.c
@@ -0,0 +1,140 @@
+// clang-format off
+// Compile with:
+// clang -target aarch64-unknown-linux-gnu main.c -o a.out -g -march=armv8.6-a+sve+sme
+//
+// For minimal corefile size, do this before running the program:
+// echo 0x20 > /proc/self/coredeump_filter
+//
+// Must be run on a system that has SVE and SME, including the smefa64
+// extension. Example command:
+// main 0 32 64 1
+//
+// This would not enter streaming mode, set non-streaming VL to 32
+// bytes, streaming VL to 64 bytes and enable ZA.
+// clang-format on
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#endif
+
+#define SM_INST(c) asm volatile("msr s0_3_c4_c" #c "_3, xzr")
+#define SMSTART_SM SM_INST(3)
+#define SMSTART_ZA SM_INST(5)
+
+void set_sve_registers() {
+  // We assume the smefa64 feature is present, which allows ffr access
+  // in streaming mode.
+  asm volatile("setffr\n\t");
+  asm volatile("ptrue p0.b\n\t");
+  asm volatile("ptrue p1.h\n\t");
+  asm volatile("ptrue p2.s\n\t");
+  asm volatile("ptrue p3.d\n\t");
+  asm volatile("pfalse p4.b\n\t");
+  asm volatile("ptrue p5.b\n\t");
+  asm volatile("ptrue p6.h\n\t");
+  asm volatile("ptrue p7.s\n\t");
+  asm volatile("ptrue p8.d\n\t");
+  asm volatile("pfalse p9.b\n\t");
+  asm volatile("ptrue p10.b\n\t");
+  asm volatile("ptrue p11.h\n\t");
+  asm volatile("ptrue p12.s\n\t");
+  asm volatile("ptrue p13.d\n\t");
+  asm volatile("pfalse p14.b\n\t");
+  asm volatile("ptrue p15.b\n\t");
+
+  asm volatile("cpy  z0.b, p0/z, #1\n\t");
+  asm volatile("cpy  z1.b, p5/z, #2\n\t");
+  asm volatile("cpy  z2.b, p10/z, #3\n\t");
+  asm volatile("cpy  z3.b, p15/z, #4\n\t");
+  asm volatile("cpy  z4.b, p0/z, #5\n\t");
+  asm volatile("cpy  z5.b, p5/z, #6\n\t");
+  asm volatile("cpy  z6.b, p10/z, #7\n\t");
+  asm volatile("cpy  z7.b, p15/z, #8\n\t");
+  asm volatile("cpy  z8.b, p0/z, #9\n\t");
+  asm volatile("cpy  z9.b, p5/z, #10\n\t");
+  asm volatile("cpy  z10.b, p10/z, #11\n\t");
+  asm volatile("cpy  z11.b, p15/z, #12\n\t");
+  asm volatile("cpy  z12.b, p0/z, #13\n\t");
+  asm volatile("cpy  z13.b, p5/z, #14\n\t");
+  asm volatile("cpy  z14.b, p10/z, #15\n\t");
+  asm volatile("cpy  z15.b, p15/z, #16\n\t");
+  asm volatile("cpy  z16.b, p0/z, #17\n\t");
+  asm volatile("cpy  z17.b, p5/z, #18\n\t");
+  asm volatile("cpy  z18.b, p10/z, #19\n\t");
+  asm volatile("cpy  z19.b, p15/z, #20\n\t");
+  asm volatile("cpy  z20.b, p0/z, #21\n\t");
+  asm volatile("cpy  z21.b, p5/z, #22\n\t");
+  asm volatile("cpy  z22.b, p10/z, #23\n\t");
+  asm volatile("cpy  z23.b, p15/z, #24\n\t");
+  asm volatile("cpy  z24.b, p0/z, #25\n\t");
+  asm volatile("cpy  z25.b, p5/z, #26\n\t");
+  asm volatile("cpy  z26.b, p10/z, #27\n\t");
+  asm volatile("cpy  z27.b, p15/z, #28\n\t");
+  asm volatile("cpy  z28.b, p0/z, #29\n\t");
+  asm volatile("cpy  z29.b, p5/z, #30\n\t");
+  asm volatile("cpy  z30.b, p10/z, #31\n\t");
+  asm volatile("cpy  z31.b, p15/z, #32\n\t");
+}
+
+void set_za_register(int streaming_vl) {
+#define MAX_VL_BYTES 256
+  uint8_t data[MAX_VL_BYTES];
+
+  for (unsigned i = 0; i < streaming_vl; ++i) {
+for (unsigned j = 0; j < MAX_VL_BYTES; ++j)
+  data[j] = i + 1;
+asm volatile("mov w12, %w0\n\t"
+ "ldr za[w12, 0], [%1]\n\t" ::"r"(i),
+ "r"()
+ : "w12");
+  }
+}
+
+void set_tpidr2(uint64_t value) {
+  __asm__ volatile("msr S3_3_C13_C0_5, %0" ::"r"(value));
+}
+
+int main(int argc, char **argv) {
+  // Arguments:
+  //  SVE mode: 1 for streaming SVE (SSVE), any other value
+  //  for non-streaming SVE mode.
+  //   Non-Streaming Vector length: In bytes, an integer e.g. "32".
+  //   Streaming Vector length: As above, but for streaming mode.
+  //   ZA mode: 1 for enabled, any other value for disabled.
+  if (argc != 5)
+return 1;
+
+  // We assume this is run on a 

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

[David Spickett via Phabricator via lldb-commits]

DavidSpickett marked 2 inline comments as done.
DavidSpickett added inline comments.



Comment at: 
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:1181
+
+  return {};
+}

DavidSpickett wrote:
> omjavaid wrote:
> > Shouldnt we build a relevant error message here incase ReadSMEControl fails 
> > on ReadZAHeader
> I think this should be `return error` in fact, let me check what that does.
I now return the underlying error so it won't fail silently.



Comment at: 
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py:183
+self.expect("register read svcr", 
substrs=["0x{:016x}".format(svcr_value)])
 
 for expr in exprs:

DavidSpickett wrote:
> omjavaid wrote:
> > should we also add a svcr write test here? 
> It's read only. We could allow writes but it introduces a lot more ways to 
> change state, most of which aren't obviously useful for the user. If someone 
> really wants it, it can be added.
> 
> I will note this in a comment here.
I've actually added comments to the other file, where it makes more sense that 
you might be writing to svcr.

Here the whole test is about having the program setup the registers, and modify 
them. So there's less expectation that you'd check writing here.

The fact that SVCR is read only (as is SVG) will be documented in fully 
https://github.com/llvm/llvm-project/pull/66767.


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[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 557100.
DavidSpickett added a comment.

- Return error in SVCR read.
- Note absence of write tests of SVCR because it's read only.


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Files:
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
  
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py

Index: lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
===
--- lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
+++ lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
@@ -164,6 +164,10 @@
 self.runCmd("register read " + sve_reg_names)
 sve_values = self.res.GetOutput()
 
+svcr_value = 1 if sve_mode == Mode.SSVE else 0
+if za_state == ZA.Enabled:
+svcr_value += 2
+
 def check_regs():
 if za_state == ZA.Enabled:
 self.check_za(start_vl)
@@ -175,6 +179,7 @@
 self.assertEqual(start_vg, self.read_vg())
 
 self.expect("register read " + sve_reg_names, substrs=[sve_values])
+self.expect("register read svcr", substrs=["0x{:016x}".format(svcr_value)])
 
 for expr in exprs:
 expr_cmd = "expression {}()".format(expr)
Index: lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
===
--- lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
+++ lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
@@ -9,7 +9,7 @@
 #define PR_SME_SET_VL 63
 #endif
 
-#define SMSTART() asm volatile("msr  s0_3_c4_c7_3, xzr" /*smstart*/)
+#define SMSTART_SM() asm volatile("msr  s0_3_c4_c3_3, xzr" /*smstart sm*/)
 
 void write_sve_regs() {
   // We assume the smefa64 feature is present, which allows ffr access
@@ -130,18 +130,18 @@
   // Note that doing a syscall brings you back to non-streaming mode, so we
   // don't need to SMSTOP here.
   if (streaming)
-SMSTART();
+SMSTART_SM();
   write_sve_regs_expr();
   prctl(SET_VL_OPT, 8 * 4);
   if (streaming)
-SMSTART();
+SMSTART_SM();
   write_sve_regs_expr();
   return 1;
 }
 
 int main() {
 #ifdef START_SSVE
-  SMSTART();
+  SMSTART_SM();
 #endif
   write_sve_regs();
 
Index: lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
===
--- lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
+++ lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
@@ -24,7 +24,15 @@
 reg_value.GetByteSize(), expected, 'Verify "%s" == %i' % (name, expected)
 )
 
-def check_sve_regs_read(self, z_reg_size):
+def check_sve_regs_read(self, z_reg_size, expected_mode):
+if self.isAArch64SME():
+# This test uses SMSTART SM, which only enables streaming mode,
+# leaving ZA disabled.
+expected_value = "1" if expected_mode == Mode.SSVE else "0"
+self.expect(
+"register read svcr", substrs=["0x000" + expected_value]
+)
+
 p_reg_size = int(z_reg_size / 8)
 
 for i in range(32):
@@ -168,7 +176,7 @@
 
 vg_reg_value = sve_registers.GetChildMemberWithName("vg").GetValueAsUnsigned()
 z_reg_size = vg_reg_value * 8
-self.check_sve_regs_read(z_reg_size)
+self.check_sve_regs_read(z_reg_size, start_mode)
 
 # Evaluate simple expression and print function expr_eval_func address.
 self.expect("expression expr_eval_func", substrs=["= 0x"])
@@ -184,7 +192,7 @@
 
 # We called a jitted function above which must not have changed SVE
 # vector length or register values.
-self.check_sve_regs_read(z_reg_size)
+self.check_sve_regs_read(z_reg_size, start_mode)
 
 self.check_sve_regs_read_after_write(z_reg_size)
 
Index: lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

[David Spickett via Phabricator via lldb-commits]

DavidSpickett added inline comments.



Comment at: 
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:1181
+
+  return {};
+}

omjavaid wrote:
> Shouldnt we build a relevant error message here incase ReadSMEControl fails 
> on ReadZAHeader
I think this should be `return error` in fact, let me check what that does.



Comment at: 
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py:183
+self.expect("register read svcr", 
substrs=["0x{:016x}".format(svcr_value)])
 
 for expr in exprs:

omjavaid wrote:
> should we also add a svcr write test here? 
It's read only. We could allow writes but it introduces a lot more ways to 
change state, most of which aren't obviously useful for the user. If someone 
really wants it, it can be added.

I will note this in a comment here.


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[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

[Muhammad Omair Javaid via Phabricator via lldb-commits]

omjavaid added a comment.

Are




Comment at: 
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:1181
+
+  return {};
+}

Shouldnt we build a relevant error message here incase ReadSMEControl fails on 
ReadZAHeader



Comment at: 
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py:183
+self.expect("register read svcr", 
substrs=["0x{:016x}".format(svcr_value)])
 
 for expr in exprs:

should we also add a svcr write test here? 


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[Lldb-commits] [PATCH] D159101: [RISC-V] Add RISC-V ABI plugin

[Jason Molenda via Phabricator via lldb-commits]

jasonmolenda added inline comments.



Comment at: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp:135
+process_sp->SetCanInterpretFunctionCalls(true);
+process_sp->SetCanJIT(false);
+  }

These should not be set in the ABI, please remove these.  These are probably 
correct for the qemu environment you're testing against, but if we're connected 
to a remote stub that can allocate memory (_M packet), we can JIT code. 


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[Lldb-commits] [PATCH] D159101: [RISC-V] Add RISC-V ABI plugin

[David Spickett via Phabricator via lldb-commits]

DavidSpickett added a comment.

FYI I will be away next week, and the week after that Phab is supposed to be 
made read-only. So look to @jasonmolenda to approve in that time frame, or we 
can take this to a PR after that.




Comment at: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp:133
+ABISysV_riscv::CreateInstance(ProcessSP process_sp, const ArchSpec ) {
+  if (process_sp) {
+process_sp->SetCanInterpretFunctionCalls(true);

Do you know why this check is needed? Is there a specific test that hits this?

The other ABI plugins seem to sidestep this by not having to `->` on it, but 
that could just be luck.


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[Lldb-commits] [PATCH] D159101: [RISC-V] Add RISC-V ABI plugin

[David Spickett via Phabricator via lldb-commits]

DavidSpickett added inline comments.



Comment at: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp:262
+  // NOTE: It's unsafe to iterate through LLDB_REGNUM_GENERICs
+  // But the a registers re sequential in the RISC-V register space
+  ++reg_index;

Seems like `are` got split up here.



Comment at: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp:203
+  size_t reg_size = m_is_rv64 ? 8 : 4;
+  size_t word_size = m_is_rv64 ? 8 : 4;
+  // Push host data onto target.

DavidSpickett wrote:
> word_size = reg_size; ?
This.


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[Lldb-commits] [PATCH] D159101: [RISC-V] Add RISC-V ABI plugin

[Ted Woodward via Phabricator via lldb-commits]

ted updated this revision to Diff 557049.
ted added a comment.

Fix crash when there was no process.
Remove bugs in function call setup when using IR interpreter.
Change flag tests to use lldb_private::Flags for flags testing


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Files:
  lldb/source/Plugins/ABI/CMakeLists.txt
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
  lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
  lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp

Index: lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
===
--- lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+++ lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
@@ -1550,6 +1550,8 @@
 ArchSpec::eRISCV_float_abi_quad)
   features_str += "+f,+d,+q,";
 // FIXME: how do we detect features such as `+a`, `+m`?
+// Turn them on by default now, since everyone seems to use them
+features_str += "+a,+m,";
   }
 
   // We use m_disasm_up.get() to tell whether we are valid or not, so if this
Index: lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
@@ -0,0 +1,12 @@
+add_lldb_library(lldbPluginABIRISCV PLUGIN
+  ABISysV_riscv.cpp
+
+  LINK_LIBS
+lldbCore
+lldbSymbol
+lldbTarget
+lldbPluginProcessUtility
+  LINK_COMPONENTS
+Support
+TargetParser
+  )
Index: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
@@ -0,0 +1,131 @@
+//===-- ABISysV_riscv.h -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef liblldb_ABISysV_riscv_h_
+#define liblldb_ABISysV_riscv_h_
+
+// Other libraries and framework includes
+#include 
+
+#include "llvm/TargetParser/Triple.h"
+
+// Project includes
+#include "lldb/Target/ABI.h"
+#include "lldb/Target/Process.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-private.h"
+
+class ABISysV_riscv : public lldb_private::RegInfoBasedABI {
+public:
+  ~ABISysV_riscv() override = default;
+
+  size_t GetRedZoneSize() const override { return 0; }
+
+  bool PrepareTrivialCall(lldb_private::Thread , lldb::addr_t sp,
+  lldb::addr_t functionAddress,
+  lldb::addr_t returnAddress,
+  llvm::ArrayRef args) const override;
+
+  // Special thread plan for GDB style non-jit function calls.
+  bool
+  PrepareTrivialCall(lldb_private::Thread , lldb::addr_t sp,
+ lldb::addr_t functionAddress, lldb::addr_t returnAddress,
+ llvm::Type ,
+ llvm::ArrayRef args) const override;
+
+  bool GetArgumentValues(lldb_private::Thread ,
+ lldb_private::ValueList ) const override;
+
+  lldb_private::Status
+  SetReturnValueObject(lldb::StackFrameSP _sp,
+   lldb::ValueObjectSP _value) override;
+
+  lldb::ValueObjectSP
+  GetReturnValueObjectImpl(lldb_private::Thread ,
+   lldb_private::CompilerType ) const override;
+
+  // Specialized to work with llvm IR types.
+  lldb::ValueObjectSP GetReturnValueObjectImpl(lldb_private::Thread ,
+   llvm::Type ) const override;
+
+  bool
+  CreateFunctionEntryUnwindPlan(lldb_private::UnwindPlan _plan) override;
+
+  bool CreateDefaultUnwindPlan(lldb_private::UnwindPlan _plan) override;
+
+  bool RegisterIsVolatile(const lldb_private::RegisterInfo *reg_info) override;
+
+  bool CallFrameAddressIsValid(lldb::addr_t cfa) override {
+// The CFA must be 128 bit aligned, unless the E ABI is used
+lldb_private::ArchSpec arch = GetProcessSP()->GetTarget().GetArchitecture();
+lldb_private::Flags arch_flags = arch.GetFlags();
+if (arch_flags.Test(lldb_private::ArchSpec::eRISCV_rve))
+  return (cfa & 0x3ull) == 0;
+return (cfa & 0xfull) == 0;
+  }
+
+  void SetIsRV64(bool is_rv64) { m_is_rv64 = is_rv64; }
+
+  bool CodeAddressIsValid(lldb::addr_t pc) override {
+// Calls can use the least significant bit to store auxiliary information,
+// so no strict check is done for alignment.
+
+lldb_private::ArchSpec arch = GetProcessSP()->GetTarget().GetArchitecture();
+
+//  & 2 set is a fault if C extension is not used.
+lldb_private::Flags arch_flags(arch.GetFlags());
+if 

[Lldb-commits] [PATCH] D158514: [lldb][AArch64] Invalidate SVG prior to reconfiguring ZA regdef

[David Spickett via Phabricator via lldb-commits]

DavidSpickett abandoned this revision.
DavidSpickett added a comment.

Moved to https://github.com/llvm/llvm-project/pull/66768.


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[Lldb-commits] [PATCH] D158506: [lldb][AArch64] Add release notes and documentation for SME

[David Spickett via Phabricator via lldb-commits]

DavidSpickett abandoned this revision.
DavidSpickett added a comment.

Moved to https://github.com/llvm/llvm-project/pull/66767.


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[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

[David Spickett via Phabricator via lldb-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGe96adfd0dbcf: [lldb][AArch64] Add testing for SMEs ZA 
and SVG registers (authored by DavidSpickett).

Repository:
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Files:
  
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/Makefile
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/main.c
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/Makefile
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c

Index: lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c
===
--- /dev/null
+++ lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c
@@ -0,0 +1,225 @@
+#include 
+#include 
+#include 
+#include 
+#include 
+
+// Important details for this program:
+// * Making a syscall will disable streaming mode if it is active.
+// * Changing the vector length will make streaming mode and ZA inactive.
+// * ZA can be active independent of streaming mode.
+// * ZA's size is the streaming vector length squared.
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#endif
+
+#ifndef PR_SME_GET_VL
+#define PR_SME_GET_VL 64
+#endif
+
+#ifndef PR_SME_VL_LEN_MASK
+#define PR_SME_VL_LEN_MASK 0x
+#endif
+
+#define SM_INST(c) asm volatile("msr s0_3_c4_c" #c "_3, xzr")
+#define SMSTART SM_INST(7)
+#define SMSTART_SM SM_INST(3)
+#define SMSTART_ZA SM_INST(5)
+#define SMSTOP SM_INST(6)
+#define SMSTOP_SM SM_INST(2)
+#define SMSTOP_ZA SM_INST(4)
+
+int start_vl = 0;
+int other_vl = 0;
+
+void write_sve_regs() {
+  // We assume the smefa64 feature is present, which allows ffr access
+  // in streaming mode.
+  asm volatile("setffr\n\t");
+  asm volatile("ptrue p0.b\n\t");
+  asm volatile("ptrue p1.h\n\t");
+  asm volatile("ptrue p2.s\n\t");
+  asm volatile("ptrue p3.d\n\t");
+  asm volatile("pfalse p4.b\n\t");
+  asm volatile("ptrue p5.b\n\t");
+  asm volatile("ptrue p6.h\n\t");
+  asm volatile("ptrue p7.s\n\t");
+  asm volatile("ptrue p8.d\n\t");
+  asm volatile("pfalse p9.b\n\t");
+  asm volatile("ptrue p10.b\n\t");
+  asm volatile("ptrue p11.h\n\t");
+  asm volatile("ptrue p12.s\n\t");
+  asm volatile("ptrue p13.d\n\t");
+  asm volatile("pfalse p14.b\n\t");
+  asm volatile("ptrue p15.b\n\t");
+
+  asm volatile("cpy  z0.b, p0/z, #1\n\t");
+  asm volatile("cpy  z1.b, p5/z, #2\n\t");
+  asm volatile("cpy  z2.b, p10/z, #3\n\t");
+  asm volatile("cpy  z3.b, p15/z, #4\n\t");
+  asm volatile("cpy  z4.b, p0/z, #5\n\t");
+  asm volatile("cpy  z5.b, p5/z, #6\n\t");
+  asm volatile("cpy  z6.b, p10/z, #7\n\t");
+  asm volatile("cpy  z7.b, p15/z, #8\n\t");
+  asm volatile("cpy  z8.b, p0/z, #9\n\t");
+  asm volatile("cpy  z9.b, p5/z, #10\n\t");
+  asm volatile("cpy  z10.b, p10/z, #11\n\t");
+  asm volatile("cpy  z11.b, p15/z, #12\n\t");
+  asm volatile("cpy  z12.b, p0/z, #13\n\t");
+  asm volatile("cpy  z13.b, p5/z, #14\n\t");
+  asm volatile("cpy  z14.b, p10/z, #15\n\t");
+  asm volatile("cpy  z15.b, p15/z, #16\n\t");
+  asm volatile("cpy  z16.b, p0/z, #17\n\t");
+  asm volatile("cpy  z17.b, p5/z, #18\n\t");
+  asm volatile("cpy  z18.b, p10/z, #19\n\t");
+  asm volatile("cpy  z19.b, p15/z, #20\n\t");
+  asm volatile("cpy  z20.b, p0/z, #21\n\t");
+  asm volatile("cpy  z21.b, p5/z, #22\n\t");
+  asm volatile("cpy  z22.b, p10/z, #23\n\t");
+  asm volatile("cpy  z23.b, p15/z, #24\n\t");
+  asm volatile("cpy  z24.b, p0/z, #25\n\t");
+  asm volatile("cpy  z25.b, p5/z, #26\n\t");
+  asm volatile("cpy  z26.b, p10/z, #27\n\t");
+  asm volatile("cpy  z27.b, p15/z, #28\n\t");
+  asm volatile("cpy  z28.b, p0/z, #29\n\t");
+  asm volatile("cpy  z29.b, p5/z, #30\n\t");
+  asm volatile("cpy  z30.b, p10/z, #31\n\t");
+  asm volatile("cpy  z31.b, p15/z, #32\n\t");
+}
+
+// Write something different so we will know if we didn't restore them
+// correctly.
+void write_sve_regs_expr() {
+  asm volatile("pfalse p0.b\n\t");
+  asm volatile("wrffr p0.b\n\t");
+  asm volatile("pfalse p1.b\n\t");
+  asm volatile("pfalse p2.b\n\t");
+  asm volatile("pfalse p3.b\n\t");
+  asm volatile("ptrue p4.b\n\t");
+  asm volatile("pfalse p5.b\n\t");
+  asm volatile("pfalse p6.b\n\t");
+  asm volatile("pfalse p7.b\n\t");
+  asm volatile("pfalse p8.b\n\t");
+  asm volatile("ptrue p9.b\n\t");
+  asm volatile("pfalse p10.b\n\t");
+  asm 

[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 557034.
DavidSpickett added a comment.

Fix some python formatting.


Repository:
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Files:
  
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/Makefile
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/main.c
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/Makefile
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c

Index: lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c
===
--- /dev/null
+++ lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c
@@ -0,0 +1,225 @@
+#include 
+#include 
+#include 
+#include 
+#include 
+
+// Important details for this program:
+// * Making a syscall will disable streaming mode if it is active.
+// * Changing the vector length will make streaming mode and ZA inactive.
+// * ZA can be active independent of streaming mode.
+// * ZA's size is the streaming vector length squared.
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#endif
+
+#ifndef PR_SME_GET_VL
+#define PR_SME_GET_VL 64
+#endif
+
+#ifndef PR_SME_VL_LEN_MASK
+#define PR_SME_VL_LEN_MASK 0x
+#endif
+
+#define SM_INST(c) asm volatile("msr s0_3_c4_c" #c "_3, xzr")
+#define SMSTART SM_INST(7)
+#define SMSTART_SM SM_INST(3)
+#define SMSTART_ZA SM_INST(5)
+#define SMSTOP SM_INST(6)
+#define SMSTOP_SM SM_INST(2)
+#define SMSTOP_ZA SM_INST(4)
+
+int start_vl = 0;
+int other_vl = 0;
+
+void write_sve_regs() {
+  // We assume the smefa64 feature is present, which allows ffr access
+  // in streaming mode.
+  asm volatile("setffr\n\t");
+  asm volatile("ptrue p0.b\n\t");
+  asm volatile("ptrue p1.h\n\t");
+  asm volatile("ptrue p2.s\n\t");
+  asm volatile("ptrue p3.d\n\t");
+  asm volatile("pfalse p4.b\n\t");
+  asm volatile("ptrue p5.b\n\t");
+  asm volatile("ptrue p6.h\n\t");
+  asm volatile("ptrue p7.s\n\t");
+  asm volatile("ptrue p8.d\n\t");
+  asm volatile("pfalse p9.b\n\t");
+  asm volatile("ptrue p10.b\n\t");
+  asm volatile("ptrue p11.h\n\t");
+  asm volatile("ptrue p12.s\n\t");
+  asm volatile("ptrue p13.d\n\t");
+  asm volatile("pfalse p14.b\n\t");
+  asm volatile("ptrue p15.b\n\t");
+
+  asm volatile("cpy  z0.b, p0/z, #1\n\t");
+  asm volatile("cpy  z1.b, p5/z, #2\n\t");
+  asm volatile("cpy  z2.b, p10/z, #3\n\t");
+  asm volatile("cpy  z3.b, p15/z, #4\n\t");
+  asm volatile("cpy  z4.b, p0/z, #5\n\t");
+  asm volatile("cpy  z5.b, p5/z, #6\n\t");
+  asm volatile("cpy  z6.b, p10/z, #7\n\t");
+  asm volatile("cpy  z7.b, p15/z, #8\n\t");
+  asm volatile("cpy  z8.b, p0/z, #9\n\t");
+  asm volatile("cpy  z9.b, p5/z, #10\n\t");
+  asm volatile("cpy  z10.b, p10/z, #11\n\t");
+  asm volatile("cpy  z11.b, p15/z, #12\n\t");
+  asm volatile("cpy  z12.b, p0/z, #13\n\t");
+  asm volatile("cpy  z13.b, p5/z, #14\n\t");
+  asm volatile("cpy  z14.b, p10/z, #15\n\t");
+  asm volatile("cpy  z15.b, p15/z, #16\n\t");
+  asm volatile("cpy  z16.b, p0/z, #17\n\t");
+  asm volatile("cpy  z17.b, p5/z, #18\n\t");
+  asm volatile("cpy  z18.b, p10/z, #19\n\t");
+  asm volatile("cpy  z19.b, p15/z, #20\n\t");
+  asm volatile("cpy  z20.b, p0/z, #21\n\t");
+  asm volatile("cpy  z21.b, p5/z, #22\n\t");
+  asm volatile("cpy  z22.b, p10/z, #23\n\t");
+  asm volatile("cpy  z23.b, p15/z, #24\n\t");
+  asm volatile("cpy  z24.b, p0/z, #25\n\t");
+  asm volatile("cpy  z25.b, p5/z, #26\n\t");
+  asm volatile("cpy  z26.b, p10/z, #27\n\t");
+  asm volatile("cpy  z27.b, p15/z, #28\n\t");
+  asm volatile("cpy  z28.b, p0/z, #29\n\t");
+  asm volatile("cpy  z29.b, p5/z, #30\n\t");
+  asm volatile("cpy  z30.b, p10/z, #31\n\t");
+  asm volatile("cpy  z31.b, p15/z, #32\n\t");
+}
+
+// Write something different so we will know if we didn't restore them
+// correctly.
+void write_sve_regs_expr() {
+  asm volatile("pfalse p0.b\n\t");
+  asm volatile("wrffr p0.b\n\t");
+  asm volatile("pfalse p1.b\n\t");
+  asm volatile("pfalse p2.b\n\t");
+  asm volatile("pfalse p3.b\n\t");
+  asm volatile("ptrue p4.b\n\t");
+  asm volatile("pfalse p5.b\n\t");
+  asm volatile("pfalse p6.b\n\t");
+  asm volatile("pfalse p7.b\n\t");
+  asm volatile("pfalse p8.b\n\t");
+  asm volatile("ptrue p9.b\n\t");
+  asm volatile("pfalse p10.b\n\t");
+  asm volatile("pfalse p11.b\n\t");
+  asm volatile("pfalse p12.b\n\t");
+  asm volatile("pfalse 

[Lldb-commits] [PATCH] D159504: [lldb][AArch64] Implement resizing of SME's ZA register

[David Spickett via Phabricator via lldb-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG46b961f36bc5: [lldb][AArch64] Implement resizing of 
SMEs ZA register (authored by DavidSpickett).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159504/new/

https://reviews.llvm.org/D159504

Files:
  lldb/include/lldb/Target/DynamicRegisterInfo.h
  lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
  lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
  lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
  lldb/source/Target/DynamicRegisterInfo.cpp

Index: lldb/source/Target/DynamicRegisterInfo.cpp
===
--- lldb/source/Target/DynamicRegisterInfo.cpp
+++ lldb/source/Target/DynamicRegisterInfo.cpp
@@ -614,10 +614,11 @@
   ConfigureOffsets();
 
   // Check if register info is reconfigurable
-  // AArch64 SVE register set has configurable register sizes
+  // AArch64 SVE register set has configurable register sizes, as does the ZA
+  // register that SME added (the streaming state of SME reuses the SVE state).
   if (arch.GetTriple().isAArch64()) {
 for (const auto  : m_regs) {
-  if (strcmp(reg.name, "vg") == 0) {
+  if ((strcmp(reg.name, "vg") == 0) || (strcmp(reg.name, "svg") == 0)) {
 m_is_reconfigurable = true;
 break;
   }
Index: lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
===
--- lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+++ lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
@@ -1660,17 +1660,18 @@
 gdb_thread->PrivateSetRegisterValue(lldb_regnum, buffer_sp->GetData());
   }
 
-  // AArch64 SVE specific code below calls AArch64SVEReconfigure to update
-  // SVE register sizes and offsets if value of VG register has changed
-  // since last stop.
+  // AArch64 SVE/SME specific code below updates SVE and ZA register sizes and
+  // offsets if value of VG or SVG registers has changed since last stop.
   const ArchSpec  = GetTarget().GetArchitecture();
   if (arch.IsValid() && arch.GetTriple().isAArch64()) {
 GDBRemoteRegisterContext *reg_ctx_sp =
 static_cast(
 gdb_thread->GetRegisterContext().get());
 
-if (reg_ctx_sp)
-  reg_ctx_sp->AArch64SVEReconfigure();
+if (reg_ctx_sp) {
+  reg_ctx_sp->AArch64Reconfigure();
+  reg_ctx_sp->InvalidateAllRegisters();
+}
   }
 
   thread_sp->SetName(thread_name.empty() ? nullptr : thread_name.c_str());
Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
===
--- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
+++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
@@ -39,6 +39,7 @@
   ~GDBRemoteDynamicRegisterInfo() override = default;
 
   void UpdateARM64SVERegistersInfos(uint64_t vg);
+  void UpdateARM64SMERegistersInfos(uint64_t svg);
 };
 
 class GDBRemoteRegisterContext : public RegisterContext {
@@ -77,7 +78,8 @@
   uint32_t ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind,
uint32_t num) override;
 
-  bool AArch64SVEReconfigure();
+  // Reconfigure variable sized registers for AArch64 SVE and SME.
+  void AArch64Reconfigure();
 
 protected:
   friend class ThreadGDBRemote;
Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
===
--- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
+++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
@@ -373,14 +373,14 @@
   if (dst == nullptr)
 return false;
 
-  // Code below is specific to AArch64 target in SVE state
+  // Code below is specific to AArch64 target in SVE or SME state
   // If vector granule (vg) register is being written then thread's
   // register context reconfiguration is triggered on success.
-  bool do_reconfigure_arm64_sve = false;
+  // We do not allow writes to SVG so it is not mentioned here.
   const ArchSpec  = process->GetTarget().GetArchitecture();
-  if (arch.IsValid() && arch.GetTriple().isAArch64())
-if (strcmp(reg_info->name, "vg") == 0)
-  do_reconfigure_arm64_sve = true;
+  bool do_reconfigure_arm64_sve = arch.IsValid() &&
+  arch.GetTriple().isAArch64() &&
+  (strcmp(reg_info->name, "vg") == 0);
 
   if (data.CopyByteOrderedData(data_offset,// src offset
reg_info->byte_size,// src length
@@ -400,10 +400,10 @@
 {m_reg_data.GetDataStart(), size_t(m_reg_data.GetByteSize())}))
 
 {
-  SetAllRegisterValid(false);
-
   if (do_reconfigure_arm64_sve)
-AArch64SVEReconfigure();
+

[Lldb-commits] [PATCH] D159503: [lldb][AArch64] Add SME streaming vector length pseduo register

[David Spickett via Phabricator via lldb-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa0768b8237ad: [lldb][AArch64] Add SME streaming vector 
length pseduo register (authored by DavidSpickett).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159503/new/

https://reviews.llvm.org/D159503

Files:
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
@@ -135,12 +135,14 @@
   bool IsMTEReg(unsigned reg) const;
   bool IsTLSReg(unsigned reg) const;
   bool IsSMEReg(unsigned reg) const;
+  bool IsSMERegZA(unsigned reg) const;
 
   uint32_t GetRegNumSVEZ0() const;
   uint32_t GetRegNumSVEFFR() const;
   uint32_t GetRegNumFPCR() const;
   uint32_t GetRegNumFPSR() const;
   uint32_t GetRegNumSVEVG() const;
+  uint32_t GetRegNumSMESVG() const;
   uint32_t GetPAuthOffset() const;
   uint32_t GetMTEOffset() const;
   uint32_t GetTLSOffset() const;
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
@@ -83,10 +83,11 @@
 // Only present when SME is present
 DEFINE_EXTENSION_REG(tpidr2)};
 
-static lldb_private::RegisterInfo g_register_infos_sme[] =
+static lldb_private::RegisterInfo g_register_infos_sme[] = {
+DEFINE_EXTENSION_REG(svg),
 // 16 is a default size we will change later.
-{{"za", nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,
-  KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
+{"za", nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,
+ KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
 
 // Number of register sets provided by this context.
 enum {
@@ -96,7 +97,7 @@
   k_num_mte_register = 1,
   // Number of TLS registers is dynamic so it is not listed here.
   k_num_pauth_register = 2,
-  k_num_sme_register = 1,
+  k_num_sme_register = 2,
   k_num_register_sets_default = 2,
   k_num_register_sets = 3
 };
@@ -448,7 +449,7 @@
   // dynamic set and is just 1 register so we make an exception to const here.
   lldb_private::RegisterInfo *non_const_reginfo =
   const_cast(m_register_info_p);
-  non_const_reginfo[m_sme_regnum_collection[0]].byte_size =
+  non_const_reginfo[m_sme_regnum_collection[1]].byte_size =
   (za_vq * 16) * (za_vq * 16);
 }
 
@@ -471,6 +472,10 @@
   return sve_vg == reg;
 }
 
+bool RegisterInfoPOSIX_arm64::IsSMERegZA(unsigned reg) const {
+  return reg == m_sme_regnum_collection[1];
+}
+
 bool RegisterInfoPOSIX_arm64::IsPAuthReg(unsigned reg) const {
   return llvm::is_contained(pauth_regnum_collection, reg);
 }
@@ -497,6 +502,10 @@
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; }
 
+uint32_t RegisterInfoPOSIX_arm64::GetRegNumSMESVG() const {
+  return m_sme_regnum_collection[0];
+}
+
 uint32_t RegisterInfoPOSIX_arm64::GetPAuthOffset() const {
   return m_register_info_p[pauth_regnum_collection[0]].byte_offset;
 }
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
===
--- lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
+++ lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
@@ -114,6 +114,12 @@
 
   uint64_t m_mte_ctrl_reg;
 
+  struct sme_pseudo_regs {
+uint64_t svg_reg;
+  };
+
+  struct sme_pseudo_regs m_sme_pseudo_regs;
+
   struct tls_regs {
 uint64_t tpidr_reg;
 // Only valid when SME is present.
@@ -144,6 +150,8 @@
 
   Status WriteTLS();
 
+  Status ReadSMESVG();
+
   Status ReadZAHeader();
 
   Status ReadZA();
@@ -176,6 +184,8 @@
 
   void *GetTLSBuffer() { return _tls_regs; }
 
+  void *GetSMEPseudoBuffer() { return _sme_pseudo_regs; }
+
   void *GetSVEBuffer() { return m_sve_ptrace_payload.data(); }
 
   size_t GetSVEHeaderSize() { return sizeof(m_sve_header); }
@@ -194,6 +204,8 @@
 
   size_t GetTLSBufferSize() { return m_tls_size; }
 
+  size_t GetSMEPseudoBufferSize() { return sizeof(m_sme_pseudo_regs); }
+
   llvm::Error ReadHardwareDebugInfo() override;
 
   llvm::Error WriteHardwareDebugRegs(DREGType hwbType) override;
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
===
--- lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+++ 

[Lldb-commits] [PATCH] D159502: [lldb][AArch64] Add SME's Array Storage (ZA) register

[David Spickett via Phabricator via lldb-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGd99d9d8b74ff: [lldb][AArch64] Add SMEs Array Storage 
(ZA) register (authored by DavidSpickett).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159502/new/

https://reviews.llvm.org/D159502

Files:
  lldb/include/lldb/Utility/RegisterValue.h
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
  lldb/source/Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h
  lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.cpp
  lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
  lldb/source/Plugins/Process/elf-core/RegisterUtilities.h

Index: lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
===
--- lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
+++ lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
@@ -119,6 +119,10 @@
 {llvm::Triple::Linux, llvm::Triple::aarch64, llvm::ELF::NT_ARM_SVE},
 };
 
+constexpr RegsetDesc AARCH64_ZA_Desc[] = {
+{llvm::Triple::Linux, llvm::Triple::aarch64, llvm::ELF::NT_ARM_ZA},
+};
+
 constexpr RegsetDesc AARCH64_PAC_Desc[] = {
 {llvm::Triple::Linux, llvm::Triple::aarch64, llvm::ELF::NT_ARM_PAC_MASK},
 };
Index: lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
===
--- lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
+++ lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
@@ -113,7 +113,7 @@
 m_sve_state = SVEState::Disabled;
 
   if (m_sve_state != SVEState::Disabled)
-m_register_info_up->ConfigureVectorLength(
+m_register_info_up->ConfigureVectorLengthSVE(
 sve::vq_from_vl(m_sve_vector_length));
 }
 
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
@@ -30,6 +30,7 @@
 eRegsetMaskPAuth = 4,
 eRegsetMaskMTE = 8,
 eRegsetMaskTLS = 16,
+eRegsetMaskZA = 32,
 eRegsetMaskDynamic = ~1,
   };
 
@@ -106,7 +107,11 @@
 
   void AddRegSetTLS(bool has_tpidr2);
 
-  uint32_t ConfigureVectorLength(uint32_t sve_vq);
+  void AddRegSetSME();
+
+  uint32_t ConfigureVectorLengthSVE(uint32_t sve_vq);
+
+  void ConfigureVectorLengthZA(uint32_t za_vq);
 
   bool VectorSizeIsValid(uint32_t vq) {
 // coverity[unsigned_compare]
@@ -117,6 +122,7 @@
 
   bool IsSVEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskSVE); }
   bool IsSSVEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskSSVE); }
+  bool IsZAEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskZA); }
   bool IsPAuthEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskPAuth); }
   bool IsMTEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskMTE); }
   bool IsTLSEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskTLS); }
@@ -128,6 +134,7 @@
   bool IsPAuthReg(unsigned reg) const;
   bool IsMTEReg(unsigned reg) const;
   bool IsTLSReg(unsigned reg) const;
+  bool IsSMEReg(unsigned reg) const;
 
   uint32_t GetRegNumSVEZ0() const;
   uint32_t GetRegNumSVEFFR() const;
@@ -137,6 +144,7 @@
   uint32_t GetPAuthOffset() const;
   uint32_t GetMTEOffset() const;
   uint32_t GetTLSOffset() const;
+  uint32_t GetSMEOffset() const;
 
 private:
   typedef std::map>
@@ -145,7 +153,10 @@
   per_vq_register_infos m_per_vq_reg_infos;
 
   uint32_t m_vector_reg_vq = eVectorQuadwordAArch64;
+  uint32_t m_za_reg_vq = eVectorQuadwordAArch64;
 
+  // In normal operation this is const. Only when SVE or SME registers change
+  // size is it either replaced or the content modified.
   const lldb_private::RegisterInfo *m_register_info_p;
   uint32_t m_register_info_count;
 
@@ -164,6 +175,7 @@
   std::vector pauth_regnum_collection;
   std::vector m_mte_regnum_collection;
   std::vector m_tls_regnum_collection;
+  std::vector m_sme_regnum_collection;
 };
 
 #endif
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
@@ -83,6 +83,11 @@
 // Only present when SME is present
 DEFINE_EXTENSION_REG(tpidr2)};
 
+static lldb_private::RegisterInfo g_register_infos_sme[] =
+// 16 is a default size we will change later.
+{{"za", nullptr, 16, 0, lldb::eEncodingVector, 

[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 557021.
DavidSpickett added a comment.

Clarify comment about SIGILL from inactive ZA.

Fix some leftover clang-format issues.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159505/new/

https://reviews.llvm.org/D159505

Files:
  
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/Makefile
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/main.c
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/Makefile
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c

Index: lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c
===
--- /dev/null
+++ lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c
@@ -0,0 +1,225 @@
+#include 
+#include 
+#include 
+#include 
+#include 
+
+// Important details for this program:
+// * Making a syscall will disable streaming mode if it is active.
+// * Changing the vector length will make streaming mode and ZA inactive.
+// * ZA can be active independent of streaming mode.
+// * ZA's size is the streaming vector length squared.
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#endif
+
+#ifndef PR_SME_GET_VL
+#define PR_SME_GET_VL 64
+#endif
+
+#ifndef PR_SME_VL_LEN_MASK
+#define PR_SME_VL_LEN_MASK 0x
+#endif
+
+#define SM_INST(c) asm volatile("msr s0_3_c4_c" #c "_3, xzr")
+#define SMSTART SM_INST(7)
+#define SMSTART_SM SM_INST(3)
+#define SMSTART_ZA SM_INST(5)
+#define SMSTOP SM_INST(6)
+#define SMSTOP_SM SM_INST(2)
+#define SMSTOP_ZA SM_INST(4)
+
+int start_vl = 0;
+int other_vl = 0;
+
+void write_sve_regs() {
+  // We assume the smefa64 feature is present, which allows ffr access
+  // in streaming mode.
+  asm volatile("setffr\n\t");
+  asm volatile("ptrue p0.b\n\t");
+  asm volatile("ptrue p1.h\n\t");
+  asm volatile("ptrue p2.s\n\t");
+  asm volatile("ptrue p3.d\n\t");
+  asm volatile("pfalse p4.b\n\t");
+  asm volatile("ptrue p5.b\n\t");
+  asm volatile("ptrue p6.h\n\t");
+  asm volatile("ptrue p7.s\n\t");
+  asm volatile("ptrue p8.d\n\t");
+  asm volatile("pfalse p9.b\n\t");
+  asm volatile("ptrue p10.b\n\t");
+  asm volatile("ptrue p11.h\n\t");
+  asm volatile("ptrue p12.s\n\t");
+  asm volatile("ptrue p13.d\n\t");
+  asm volatile("pfalse p14.b\n\t");
+  asm volatile("ptrue p15.b\n\t");
+
+  asm volatile("cpy  z0.b, p0/z, #1\n\t");
+  asm volatile("cpy  z1.b, p5/z, #2\n\t");
+  asm volatile("cpy  z2.b, p10/z, #3\n\t");
+  asm volatile("cpy  z3.b, p15/z, #4\n\t");
+  asm volatile("cpy  z4.b, p0/z, #5\n\t");
+  asm volatile("cpy  z5.b, p5/z, #6\n\t");
+  asm volatile("cpy  z6.b, p10/z, #7\n\t");
+  asm volatile("cpy  z7.b, p15/z, #8\n\t");
+  asm volatile("cpy  z8.b, p0/z, #9\n\t");
+  asm volatile("cpy  z9.b, p5/z, #10\n\t");
+  asm volatile("cpy  z10.b, p10/z, #11\n\t");
+  asm volatile("cpy  z11.b, p15/z, #12\n\t");
+  asm volatile("cpy  z12.b, p0/z, #13\n\t");
+  asm volatile("cpy  z13.b, p5/z, #14\n\t");
+  asm volatile("cpy  z14.b, p10/z, #15\n\t");
+  asm volatile("cpy  z15.b, p15/z, #16\n\t");
+  asm volatile("cpy  z16.b, p0/z, #17\n\t");
+  asm volatile("cpy  z17.b, p5/z, #18\n\t");
+  asm volatile("cpy  z18.b, p10/z, #19\n\t");
+  asm volatile("cpy  z19.b, p15/z, #20\n\t");
+  asm volatile("cpy  z20.b, p0/z, #21\n\t");
+  asm volatile("cpy  z21.b, p5/z, #22\n\t");
+  asm volatile("cpy  z22.b, p10/z, #23\n\t");
+  asm volatile("cpy  z23.b, p15/z, #24\n\t");
+  asm volatile("cpy  z24.b, p0/z, #25\n\t");
+  asm volatile("cpy  z25.b, p5/z, #26\n\t");
+  asm volatile("cpy  z26.b, p10/z, #27\n\t");
+  asm volatile("cpy  z27.b, p15/z, #28\n\t");
+  asm volatile("cpy  z28.b, p0/z, #29\n\t");
+  asm volatile("cpy  z29.b, p5/z, #30\n\t");
+  asm volatile("cpy  z30.b, p10/z, #31\n\t");
+  asm volatile("cpy  z31.b, p15/z, #32\n\t");
+}
+
+// Write something different so we will know if we didn't restore them
+// correctly.
+void write_sve_regs_expr() {
+  asm volatile("pfalse p0.b\n\t");
+  asm volatile("wrffr p0.b\n\t");
+  asm volatile("pfalse p1.b\n\t");
+  asm volatile("pfalse p2.b\n\t");
+  asm volatile("pfalse p3.b\n\t");
+  asm volatile("ptrue p4.b\n\t");
+  asm volatile("pfalse p5.b\n\t");
+  asm volatile("pfalse p6.b\n\t");
+  asm volatile("pfalse p7.b\n\t");
+  asm volatile("pfalse p8.b\n\t");
+  asm volatile("ptrue p9.b\n\t");
+  asm volatile("pfalse p10.b\n\t");
+  asm volatile("pfalse p11.b\n\t");
+  asm 

[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

[David Spickett via Phabricator via lldb-commits]

DavidSpickett added inline comments.



Comment at: 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/main.c:12
+//   (this is just how ptrace works).
+// * Writing to an inactive ZA produces a SIGILL.
+

omjavaid wrote:
> Is this a kernel requirement or just the way ptrace is implemented.?
It's an architecture decision, I'll clarify the comment.


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[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

[Muhammad Omair Javaid via Phabricator via lldb-commits]

omjavaid accepted this revision.
omjavaid added a comment.
This revision is now accepted and ready to land.

this looks good




Comment at: 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/main.c:12
+//   (this is just how ptrace works).
+// * Writing to an inactive ZA produces a SIGILL.
+

Is this a kernel requirement or just the way ptrace is implemented.?


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[Lldb-commits] [PATCH] D158514: [lldb][AArch64] Invalidate SVG prior to reconfiguring ZA regdef

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 557014.
DavidSpickett added a comment.

Rebase


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Files:
  lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py


Index: 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
===
--- 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
+++ 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
@@ -125,11 +125,13 @@
 self.runCmd("thread select %d" % (idx + 1))
 self.check_za_register(4, 2)
 self.runCmd("register write vg 2")
+self.check_disabled_za_register(2)
 
 elif stopped_at_line_number == thY_break_line1:
 self.runCmd("thread select %d" % (idx + 1))
 self.check_za_register(2, 3)
 self.runCmd("register write vg 4")
+self.check_disabled_za_register(4)
 
 self.runCmd("thread continue 2")
 self.runCmd("thread continue 3")
Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
===
--- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
+++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
@@ -781,6 +781,11 @@
   std::optional svg_reg_value;
   const RegisterInfo *svg_reg_info = m_reg_info_sp->GetRegisterInfo("svg");
   if (svg_reg_info) {
+// When vg is written it is automatically made invalid. Writing vg will 
also
+// change svg if we're in streaming mode but it will not be made invalid
+// so do this manually so the following read gets the latest svg value.
+SetRegisterIsValid(svg_reg_info, false);
+
 uint32_t svg_reg_num = svg_reg_info->kinds[eRegisterKindLLDB];
 uint64_t reg_value = ReadRegisterAsUnsigned(svg_reg_num, fail_value);
 if (reg_value != fail_value && reg_value <= 32)


Index: lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
===
--- lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
+++ lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
@@ -125,11 +125,13 @@
 self.runCmd("thread select %d" % (idx + 1))
 self.check_za_register(4, 2)
 self.runCmd("register write vg 2")
+self.check_disabled_za_register(2)
 
 elif stopped_at_line_number == thY_break_line1:
 self.runCmd("thread select %d" % (idx + 1))
 self.check_za_register(2, 3)
 self.runCmd("register write vg 4")
+self.check_disabled_za_register(4)
 
 self.runCmd("thread continue 2")
 self.runCmd("thread continue 3")
Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
===
--- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
+++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
@@ -781,6 +781,11 @@
   std::optional svg_reg_value;
   const RegisterInfo *svg_reg_info = m_reg_info_sp->GetRegisterInfo("svg");
   if (svg_reg_info) {
+// When vg is written it is automatically made invalid. Writing vg will also
+// change svg if we're in streaming mode but it will not be made invalid
+// so do this manually so the following read gets the latest svg value.
+SetRegisterIsValid(svg_reg_info, false);
+
 uint32_t svg_reg_num = svg_reg_info->kinds[eRegisterKindLLDB];
 uint64_t reg_value = ReadRegisterAsUnsigned(svg_reg_num, fail_value);
 if (reg_value != fail_value && reg_value <= 32)
___
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[Lldb-commits] [PATCH] D158506: [lldb][AArch64] Add release notes and documentation for SME

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 557013.
DavidSpickett added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158506/new/

https://reviews.llvm.org/D158506

Files:
  lldb/docs/index.rst
  lldb/docs/use/aarch64-linux.rst
  llvm/docs/ReleaseNotes.rst

Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -183,6 +183,10 @@
 * Methods in SBHostOS related to threads have had their implementations
   removed. These methods will return a value indicating failure.
 
+* LLDB now supports debugging the Scalable Matrix Extension (SME) on AArch64
+  Linux for both running processes and core files. For details refer to the
+  `AArch64 Linux documentation `_.
+
 Changes to Sanitizers
 -
 * HWASan now defaults to detecting use-after-scope bugs.
Index: lldb/docs/use/aarch64-linux.rst
===
--- /dev/null
+++ lldb/docs/use/aarch64-linux.rst
@@ -0,0 +1,190 @@
+Using LLDB On AArch64 Linux
+===
+
+This page explains the details of debugging certain AArch64 extensions using
+LLDB. If something is not mentioned here, it likely works as you would expect.
+
+This is not a replacement for ptrace and Linux Kernel documentation. This covers
+how LLDB has chosen to use those things and how that effects your experience as
+a user.
+
+Scalable Vector Extension (SVE)
+---
+
+See `here `__
+to learn about the extension and `here `__
+for the Linux Kernel's handling of it.
+
+In LLDB you will be able to see the following new registers:
+
+* ``z0-z31`` vector registers, each one has size equal to the vector length.
+* ``p0-p15`` predicate registers, each one containing 1 bit per byte in the vector
+  length. Making each one vector length / 8 sized.
+* ``ffr`` the first fault register, same size as a predicate register.
+* ``vg``, the vector length in "granules". Each granule is 8 bytes.
+
+.. code-block::
+
+   Scalable Vector Extension Registers:
+ vg = 0x0002
+ z0 = {0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 <...> }
+   <...>
+ p0 = {0xff 0xff}
+   <...>
+ffr = {0xff 0xff}
+
+The example above has a vector length of 16 bytes. Within LLDB you will always
+see "vg" as in the ``vg`` register, which is 2 in this case (8*2 = 16).
+Elsewhere you may see "vq" which is the vector length in quadwords (16 bytes)
+elsewhere. Where you see "vl", it is in bytes.
+
+Changing the Vector Length
+..
+
+While you can count the size of a P or Z register, it is intended that ``vg`` be
+used to find the current vector length.
+
+vg can be written. Writing the current vector length changes nothing. If you
+increase the vector length, the registers will likely be reset to 0. If you
+decrease it, LLDB will truncate the Z registers but everything else will be reset
+to 0.
+
+Generally you should not assume that SVE state after changing the vector length
+is in any way the same as it was previously. If you need to do it, do it before
+a function's first use of SVE.
+
+Z Register Presentation
+...
+
+LLDB makes no attempt to predict how an SVE Z register will be used. Even if the
+next SVE instruction (which may some distance away) would use, for example, 32
+bit elements, LLDB prints ``z0`` as single bytes.
+
+If you know what format you are going to use, give a format option::
+
+  (lldb) register read z0 -f uint32_t[]
+  z0 = {0x01010101 0x01010101 0x01010101 0x01010101}
+
+FPSIMD and SVE Modes
+
+
+Prior to the debugee's first use of SVE, it is in what the Linux Kernel terms
+SIMD mode. Only the FPU is being used. In this state LLDB will still show the
+SVE registers however the values are simply the FPU values zero extended up to
+the vector length.
+
+On first access to SVE, the process goes into SVE mode. Now the Z values are
+in the real Z registers.
+
+You can also trigger this with LLDB by writing to an SVE register. Note that
+there is no way to undo this change from within LLDB. However, the debugee
+itself could do something to end up back in SIMD mode.
+
+Expression evaluation
+.
+
+If you evaluate an expression, all SVE state is saved prior to, and restored
+after the expression has been evaluated. Including the register values and
+vector length.
+
+Scalable Matrix Extension (SME)
+---
+
+See `here `__
+to learn about the extension and 

[Lldb-commits] [PATCH] D158500: [lldb][AArch64] Linux corefile support for SME

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 557012.
DavidSpickett added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158500/new/

https://reviews.llvm.org/D158500

Files:
  lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h
  lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
  lldb/test/API/linux/aarch64/sme_core_file/TestAArch64LinuxSMECoreFile.py
  lldb/test/API/linux/aarch64/sme_core_file/core_0_16_32_1
  lldb/test/API/linux/aarch64/sme_core_file/core_0_32_16_0
  lldb/test/API/linux/aarch64/sme_core_file/core_1_16_32_0
  lldb/test/API/linux/aarch64/sme_core_file/core_1_32_16_1
  lldb/test/API/linux/aarch64/sme_core_file/main.c

Index: lldb/test/API/linux/aarch64/sme_core_file/main.c
===
--- /dev/null
+++ lldb/test/API/linux/aarch64/sme_core_file/main.c
@@ -0,0 +1,140 @@
+// clang-format off
+// Compile with:
+// clang -target aarch64-unknown-linux-gnu main.c -o a.out -g -march=armv8.6-a+sve+sme
+//
+// For minimal corefile size, do this before running the program:
+// echo 0x20 > /proc/self/coredeump_filter
+//
+// Must be run on a system that has SVE and SME, including the smefa64
+// extension. Example command:
+// main 0 32 64 1
+//
+// This would not enter streaming mode, set non-streaming VL to 32
+// bytes, streaming VL to 64 bytes and enable ZA.
+// clang-format on
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#endif
+
+#define SM_INST(c) asm volatile("msr s0_3_c4_c" #c "_3, xzr")
+#define SMSTART_SM SM_INST(3)
+#define SMSTART_ZA SM_INST(5)
+
+void set_sve_registers() {
+  // We assume the smefa64 feature is present, which allows ffr access
+  // in streaming mode.
+  asm volatile("setffr\n\t");
+  asm volatile("ptrue p0.b\n\t");
+  asm volatile("ptrue p1.h\n\t");
+  asm volatile("ptrue p2.s\n\t");
+  asm volatile("ptrue p3.d\n\t");
+  asm volatile("pfalse p4.b\n\t");
+  asm volatile("ptrue p5.b\n\t");
+  asm volatile("ptrue p6.h\n\t");
+  asm volatile("ptrue p7.s\n\t");
+  asm volatile("ptrue p8.d\n\t");
+  asm volatile("pfalse p9.b\n\t");
+  asm volatile("ptrue p10.b\n\t");
+  asm volatile("ptrue p11.h\n\t");
+  asm volatile("ptrue p12.s\n\t");
+  asm volatile("ptrue p13.d\n\t");
+  asm volatile("pfalse p14.b\n\t");
+  asm volatile("ptrue p15.b\n\t");
+
+  asm volatile("cpy  z0.b, p0/z, #1\n\t");
+  asm volatile("cpy  z1.b, p5/z, #2\n\t");
+  asm volatile("cpy  z2.b, p10/z, #3\n\t");
+  asm volatile("cpy  z3.b, p15/z, #4\n\t");
+  asm volatile("cpy  z4.b, p0/z, #5\n\t");
+  asm volatile("cpy  z5.b, p5/z, #6\n\t");
+  asm volatile("cpy  z6.b, p10/z, #7\n\t");
+  asm volatile("cpy  z7.b, p15/z, #8\n\t");
+  asm volatile("cpy  z8.b, p0/z, #9\n\t");
+  asm volatile("cpy  z9.b, p5/z, #10\n\t");
+  asm volatile("cpy  z10.b, p10/z, #11\n\t");
+  asm volatile("cpy  z11.b, p15/z, #12\n\t");
+  asm volatile("cpy  z12.b, p0/z, #13\n\t");
+  asm volatile("cpy  z13.b, p5/z, #14\n\t");
+  asm volatile("cpy  z14.b, p10/z, #15\n\t");
+  asm volatile("cpy  z15.b, p15/z, #16\n\t");
+  asm volatile("cpy  z16.b, p0/z, #17\n\t");
+  asm volatile("cpy  z17.b, p5/z, #18\n\t");
+  asm volatile("cpy  z18.b, p10/z, #19\n\t");
+  asm volatile("cpy  z19.b, p15/z, #20\n\t");
+  asm volatile("cpy  z20.b, p0/z, #21\n\t");
+  asm volatile("cpy  z21.b, p5/z, #22\n\t");
+  asm volatile("cpy  z22.b, p10/z, #23\n\t");
+  asm volatile("cpy  z23.b, p15/z, #24\n\t");
+  asm volatile("cpy  z24.b, p0/z, #25\n\t");
+  asm volatile("cpy  z25.b, p5/z, #26\n\t");
+  asm volatile("cpy  z26.b, p10/z, #27\n\t");
+  asm volatile("cpy  z27.b, p15/z, #28\n\t");
+  asm volatile("cpy  z28.b, p0/z, #29\n\t");
+  asm volatile("cpy  z29.b, p5/z, #30\n\t");
+  asm volatile("cpy  z30.b, p10/z, #31\n\t");
+  asm volatile("cpy  z31.b, p15/z, #32\n\t");
+}
+
+void set_za_register(int streaming_vl) {
+#define MAX_VL_BYTES 256
+  uint8_t data[MAX_VL_BYTES];
+
+  for (unsigned i = 0; i < streaming_vl; ++i) {
+for (unsigned j = 0; j < MAX_VL_BYTES; ++j)
+  data[j] = i + 1;
+asm volatile("mov w12, %w0\n\t"
+ "ldr za[w12, 0], [%1]\n\t" ::"r"(i),
+ "r"()
+ : "w12");
+  }
+}
+
+void set_tpidr2(uint64_t value) {
+  __asm__ volatile("msr S3_3_C13_C0_5, %0" ::"r"(value));
+}
+
+int main(int argc, char **argv) {
+  // Arguments:
+  //  SVE mode: 1 for streaming SVE (SSVE), any other value
+  //  for non-streaming SVE mode.
+  //   Non-Streaming Vector length: In bytes, an integer e.g. "32".
+  //   Streaming Vector length: As above, but for streaming mode.
+  //   ZA mode: 1 for enabled, any other value for disabled.
+  if (argc != 5)
+return 1;
+
+  // We assume this is run on a 

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 557011.
DavidSpickett added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154927/new/

https://reviews.llvm.org/D154927

Files:
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
  
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py

Index: lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
===
--- lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
+++ lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
@@ -164,6 +164,10 @@
 self.runCmd("register read " + sve_reg_names)
 sve_values = self.res.GetOutput()
 
+svcr_value = 1 if sve_mode == Mode.SSVE else 0
+if za_state == ZA.Enabled:
+svcr_value += 2
+
 def check_regs():
 if za_state == ZA.Enabled:
 self.check_za(start_vl)
@@ -175,6 +179,7 @@
 self.assertEqual(start_vg, self.read_vg())
 
 self.expect("register read " + sve_reg_names, substrs=[sve_values])
+self.expect("register read svcr", substrs=["0x{:016x}".format(svcr_value)])
 
 for expr in exprs:
 expr_cmd = "expression {}()".format(expr)
Index: lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
===
--- lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
+++ lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
@@ -9,7 +9,7 @@
 #define PR_SME_SET_VL 63
 #endif
 
-#define SMSTART() asm volatile("msr  s0_3_c4_c7_3, xzr" /*smstart*/)
+#define SMSTART_SM() asm volatile("msr  s0_3_c4_c3_3, xzr" /*smstart sm*/)
 
 void write_sve_regs() {
   // We assume the smefa64 feature is present, which allows ffr access
@@ -130,18 +130,18 @@
   // Note that doing a syscall brings you back to non-streaming mode, so we
   // don't need to SMSTOP here.
   if (streaming)
-SMSTART();
+SMSTART_SM();
   write_sve_regs_expr();
   prctl(SET_VL_OPT, 8 * 4);
   if (streaming)
-SMSTART();
+SMSTART_SM();
   write_sve_regs_expr();
   return 1;
 }
 
 int main() {
 #ifdef START_SSVE
-  SMSTART();
+  SMSTART_SM();
 #endif
   write_sve_regs();
 
Index: lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
===
--- lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
+++ lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
@@ -24,7 +24,15 @@
 reg_value.GetByteSize(), expected, 'Verify "%s" == %i' % (name, expected)
 )
 
-def check_sve_regs_read(self, z_reg_size):
+def check_sve_regs_read(self, z_reg_size, expected_mode):
+if self.isAArch64SME():
+# This test uses SMSTART SM, which only enables streaming mode,
+# leaving ZA disabled.
+expected_value = "1" if expected_mode == Mode.SSVE else "0"
+self.expect(
+"register read svcr", substrs=["0x000" + expected_value]
+)
+
 p_reg_size = int(z_reg_size / 8)
 
 for i in range(32):
@@ -168,7 +176,7 @@
 
 vg_reg_value = sve_registers.GetChildMemberWithName("vg").GetValueAsUnsigned()
 z_reg_size = vg_reg_value * 8
-self.check_sve_regs_read(z_reg_size)
+self.check_sve_regs_read(z_reg_size, start_mode)
 
 # Evaluate simple expression and print function expr_eval_func address.
 self.expect("expression expr_eval_func", substrs=["= 0x"])
@@ -184,7 +192,7 @@
 
 # We called a jitted function above which must not have changed SVE
 # vector length or register values.
-self.check_sve_regs_read(z_reg_size)
+self.check_sve_regs_read(z_reg_size, start_mode)
 
 self.check_sve_regs_read_after_write(z_reg_size)
 
Index: lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
===
--- 

[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 557010.
DavidSpickett added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159505/new/

https://reviews.llvm.org/D159505

Files:
  
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/Makefile
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/main.c
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/Makefile
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c

Index: lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c
===
--- /dev/null
+++ lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c
@@ -0,0 +1,226 @@
+#include 
+#include 
+#include 
+#include 
+#include 
+
+// Important details for this program:
+// * Making a syscall will disable streaming mode if it is active.
+// * Changing the vector length will make streaming mode and ZA inactive.
+// * ZA can be active independent of streaming mode.
+// * ZA's size is the streaming vector length squared.
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#endif
+
+#ifndef PR_SME_GET_VL
+#define PR_SME_GET_VL 64
+#endif
+
+#ifndef PR_SME_VL_LEN_MASK
+#define PR_SME_VL_LEN_MASK 0x
+#endif
+
+#define SM_INST(c) asm volatile("msr s0_3_c4_c" #c "_3, xzr")
+#define SMSTART SM_INST(7)
+#define SMSTART_SM SM_INST(3)
+#define SMSTART_ZA SM_INST(5)
+#define SMSTOP SM_INST(6)
+#define SMSTOP_SM SM_INST(2)
+#define SMSTOP_ZA SM_INST(4)
+
+int start_vl = 0;
+int other_vl = 0;
+
+void write_sve_regs() {
+  // We assume the smefa64 feature is present, which allows ffr access
+  // in streaming mode.
+  asm volatile("setffr\n\t");
+  asm volatile("ptrue p0.b\n\t");
+  asm volatile("ptrue p1.h\n\t");
+  asm volatile("ptrue p2.s\n\t");
+  asm volatile("ptrue p3.d\n\t");
+  asm volatile("pfalse p4.b\n\t");
+  asm volatile("ptrue p5.b\n\t");
+  asm volatile("ptrue p6.h\n\t");
+  asm volatile("ptrue p7.s\n\t");
+  asm volatile("ptrue p8.d\n\t");
+  asm volatile("pfalse p9.b\n\t");
+  asm volatile("ptrue p10.b\n\t");
+  asm volatile("ptrue p11.h\n\t");
+  asm volatile("ptrue p12.s\n\t");
+  asm volatile("ptrue p13.d\n\t");
+  asm volatile("pfalse p14.b\n\t");
+  asm volatile("ptrue p15.b\n\t");
+
+  asm volatile("cpy  z0.b, p0/z, #1\n\t");
+  asm volatile("cpy  z1.b, p5/z, #2\n\t");
+  asm volatile("cpy  z2.b, p10/z, #3\n\t");
+  asm volatile("cpy  z3.b, p15/z, #4\n\t");
+  asm volatile("cpy  z4.b, p0/z, #5\n\t");
+  asm volatile("cpy  z5.b, p5/z, #6\n\t");
+  asm volatile("cpy  z6.b, p10/z, #7\n\t");
+  asm volatile("cpy  z7.b, p15/z, #8\n\t");
+  asm volatile("cpy  z8.b, p0/z, #9\n\t");
+  asm volatile("cpy  z9.b, p5/z, #10\n\t");
+  asm volatile("cpy  z10.b, p10/z, #11\n\t");
+  asm volatile("cpy  z11.b, p15/z, #12\n\t");
+  asm volatile("cpy  z12.b, p0/z, #13\n\t");
+  asm volatile("cpy  z13.b, p5/z, #14\n\t");
+  asm volatile("cpy  z14.b, p10/z, #15\n\t");
+  asm volatile("cpy  z15.b, p15/z, #16\n\t");
+  asm volatile("cpy  z16.b, p0/z, #17\n\t");
+  asm volatile("cpy  z17.b, p5/z, #18\n\t");
+  asm volatile("cpy  z18.b, p10/z, #19\n\t");
+  asm volatile("cpy  z19.b, p15/z, #20\n\t");
+  asm volatile("cpy  z20.b, p0/z, #21\n\t");
+  asm volatile("cpy  z21.b, p5/z, #22\n\t");
+  asm volatile("cpy  z22.b, p10/z, #23\n\t");
+  asm volatile("cpy  z23.b, p15/z, #24\n\t");
+  asm volatile("cpy  z24.b, p0/z, #25\n\t");
+  asm volatile("cpy  z25.b, p5/z, #26\n\t");
+  asm volatile("cpy  z26.b, p10/z, #27\n\t");
+  asm volatile("cpy  z27.b, p15/z, #28\n\t");
+  asm volatile("cpy  z28.b, p0/z, #29\n\t");
+  asm volatile("cpy  z29.b, p5/z, #30\n\t");
+  asm volatile("cpy  z30.b, p10/z, #31\n\t");
+  asm volatile("cpy  z31.b, p15/z, #32\n\t");
+}
+
+// Write something different so we will know if we didn't restore them
+// correctly.
+void write_sve_regs_expr() {
+  asm volatile("pfalse p0.b\n\t");
+  asm volatile("wrffr p0.b\n\t");
+  asm volatile("pfalse p1.b\n\t");
+  asm volatile("pfalse p2.b\n\t");
+  asm volatile("pfalse p3.b\n\t");
+  asm volatile("ptrue p4.b\n\t");
+  asm volatile("pfalse p5.b\n\t");
+  asm volatile("pfalse p6.b\n\t");
+  asm volatile("pfalse p7.b\n\t");
+  asm volatile("pfalse p8.b\n\t");
+  asm volatile("ptrue p9.b\n\t");
+  asm volatile("pfalse p10.b\n\t");
+  asm volatile("pfalse p11.b\n\t");
+  asm volatile("pfalse p12.b\n\t");
+  asm volatile("pfalse p13.b\n\t");
+  asm 

[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

[David Spickett via Phabricator via lldb-commits]

DavidSpickett marked 2 inline comments as done.
DavidSpickett added inline comments.



Comment at: 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/Makefile:3
+
+CFLAGS_EXTRAS := -march=armv8-a+sve+sme -lpthread
+

DavidSpickett wrote:
> omjavaid wrote:
> > is USE_SSVE a subset of sve+sme? 
> It's a define I made up for the purposes of the test, it's in the existing 
> tests but not well documented. I'll push something to address that in the 
> existing tests and check the new ones here for this and other defines I've 
> added.
> 
> We need sve to update sve registers and sme to be able to move into the za 
> register (/the rows of the za register).
https://github.com/llvm/llvm-project/commit/91f46ece9efca7a1109b5837a1b24f2a251bb0cc

USE_SSVE and friends are just defines `-D...` made up for specific tests.


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[Lldb-commits] [PATCH] D159504: [lldb][AArch64] Implement resizing of SME's ZA register

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 557009.
DavidSpickett marked an inline comment as done.
DavidSpickett added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159504/new/

https://reviews.llvm.org/D159504

Files:
  lldb/include/lldb/Target/DynamicRegisterInfo.h
  lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
  lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
  lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
  lldb/source/Target/DynamicRegisterInfo.cpp

Index: lldb/source/Target/DynamicRegisterInfo.cpp
===
--- lldb/source/Target/DynamicRegisterInfo.cpp
+++ lldb/source/Target/DynamicRegisterInfo.cpp
@@ -614,10 +614,11 @@
   ConfigureOffsets();
 
   // Check if register info is reconfigurable
-  // AArch64 SVE register set has configurable register sizes
+  // AArch64 SVE register set has configurable register sizes, as does the ZA
+  // register that SME added (the streaming state of SME reuses the SVE state).
   if (arch.GetTriple().isAArch64()) {
 for (const auto  : m_regs) {
-  if (strcmp(reg.name, "vg") == 0) {
+  if ((strcmp(reg.name, "vg") == 0) || (strcmp(reg.name, "svg") == 0)) {
 m_is_reconfigurable = true;
 break;
   }
Index: lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
===
--- lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+++ lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
@@ -1660,17 +1660,18 @@
 gdb_thread->PrivateSetRegisterValue(lldb_regnum, buffer_sp->GetData());
   }
 
-  // AArch64 SVE specific code below calls AArch64SVEReconfigure to update
-  // SVE register sizes and offsets if value of VG register has changed
-  // since last stop.
+  // AArch64 SVE/SME specific code below updates SVE and ZA register sizes and
+  // offsets if value of VG or SVG registers has changed since last stop.
   const ArchSpec  = GetTarget().GetArchitecture();
   if (arch.IsValid() && arch.GetTriple().isAArch64()) {
 GDBRemoteRegisterContext *reg_ctx_sp =
 static_cast(
 gdb_thread->GetRegisterContext().get());
 
-if (reg_ctx_sp)
-  reg_ctx_sp->AArch64SVEReconfigure();
+if (reg_ctx_sp) {
+  reg_ctx_sp->AArch64Reconfigure();
+  reg_ctx_sp->InvalidateAllRegisters();
+}
   }
 
   thread_sp->SetName(thread_name.empty() ? nullptr : thread_name.c_str());
Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
===
--- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
+++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
@@ -39,6 +39,7 @@
   ~GDBRemoteDynamicRegisterInfo() override = default;
 
   void UpdateARM64SVERegistersInfos(uint64_t vg);
+  void UpdateARM64SMERegistersInfos(uint64_t svg);
 };
 
 class GDBRemoteRegisterContext : public RegisterContext {
@@ -77,7 +78,8 @@
   uint32_t ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind,
uint32_t num) override;
 
-  bool AArch64SVEReconfigure();
+  // Reconfigure variable sized registers for AArch64 SVE and SME.
+  void AArch64Reconfigure();
 
 protected:
   friend class ThreadGDBRemote;
Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
===
--- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
+++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
@@ -373,14 +373,14 @@
   if (dst == nullptr)
 return false;
 
-  // Code below is specific to AArch64 target in SVE state
+  // Code below is specific to AArch64 target in SVE or SME state
   // If vector granule (vg) register is being written then thread's
   // register context reconfiguration is triggered on success.
-  bool do_reconfigure_arm64_sve = false;
+  // We do not allow writes to SVG so it is not mentioned here.
   const ArchSpec  = process->GetTarget().GetArchitecture();
-  if (arch.IsValid() && arch.GetTriple().isAArch64())
-if (strcmp(reg_info->name, "vg") == 0)
-  do_reconfigure_arm64_sve = true;
+  bool do_reconfigure_arm64_sve = arch.IsValid() &&
+  arch.GetTriple().isAArch64() &&
+  (strcmp(reg_info->name, "vg") == 0);
 
   if (data.CopyByteOrderedData(data_offset,// src offset
reg_info->byte_size,// src length
@@ -400,10 +400,10 @@
 {m_reg_data.GetDataStart(), size_t(m_reg_data.GetByteSize())}))
 
 {
-  SetAllRegisterValid(false);
-
   if (do_reconfigure_arm64_sve)
-AArch64SVEReconfigure();
+AArch64Reconfigure();
+
+  InvalidateAllRegisters();

[Lldb-commits] [PATCH] D159503: [lldb][AArch64] Add SME streaming vector length pseduo register

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 557008.
DavidSpickett added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159503/new/

https://reviews.llvm.org/D159503

Files:
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
@@ -135,12 +135,14 @@
   bool IsMTEReg(unsigned reg) const;
   bool IsTLSReg(unsigned reg) const;
   bool IsSMEReg(unsigned reg) const;
+  bool IsSMERegZA(unsigned reg) const;
 
   uint32_t GetRegNumSVEZ0() const;
   uint32_t GetRegNumSVEFFR() const;
   uint32_t GetRegNumFPCR() const;
   uint32_t GetRegNumFPSR() const;
   uint32_t GetRegNumSVEVG() const;
+  uint32_t GetRegNumSMESVG() const;
   uint32_t GetPAuthOffset() const;
   uint32_t GetMTEOffset() const;
   uint32_t GetTLSOffset() const;
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
@@ -83,10 +83,11 @@
 // Only present when SME is present
 DEFINE_EXTENSION_REG(tpidr2)};
 
-static lldb_private::RegisterInfo g_register_infos_sme[] =
+static lldb_private::RegisterInfo g_register_infos_sme[] = {
+DEFINE_EXTENSION_REG(svg),
 // 16 is a default size we will change later.
-{{"za", nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,
-  KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
+{"za", nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,
+ KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
 
 // Number of register sets provided by this context.
 enum {
@@ -96,7 +97,7 @@
   k_num_mte_register = 1,
   // Number of TLS registers is dynamic so it is not listed here.
   k_num_pauth_register = 2,
-  k_num_sme_register = 1,
+  k_num_sme_register = 2,
   k_num_register_sets_default = 2,
   k_num_register_sets = 3
 };
@@ -448,7 +449,7 @@
   // dynamic set and is just 1 register so we make an exception to const here.
   lldb_private::RegisterInfo *non_const_reginfo =
   const_cast(m_register_info_p);
-  non_const_reginfo[m_sme_regnum_collection[0]].byte_size =
+  non_const_reginfo[m_sme_regnum_collection[1]].byte_size =
   (za_vq * 16) * (za_vq * 16);
 }
 
@@ -471,6 +472,10 @@
   return sve_vg == reg;
 }
 
+bool RegisterInfoPOSIX_arm64::IsSMERegZA(unsigned reg) const {
+  return reg == m_sme_regnum_collection[1];
+}
+
 bool RegisterInfoPOSIX_arm64::IsPAuthReg(unsigned reg) const {
   return llvm::is_contained(pauth_regnum_collection, reg);
 }
@@ -497,6 +502,10 @@
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; }
 
+uint32_t RegisterInfoPOSIX_arm64::GetRegNumSMESVG() const {
+  return m_sme_regnum_collection[0];
+}
+
 uint32_t RegisterInfoPOSIX_arm64::GetPAuthOffset() const {
   return m_register_info_p[pauth_regnum_collection[0]].byte_offset;
 }
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
===
--- lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
+++ lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
@@ -114,6 +114,12 @@
 
   uint64_t m_mte_ctrl_reg;
 
+  struct sme_pseudo_regs {
+uint64_t svg_reg;
+  };
+
+  struct sme_pseudo_regs m_sme_pseudo_regs;
+
   struct tls_regs {
 uint64_t tpidr_reg;
 // Only valid when SME is present.
@@ -144,6 +150,8 @@
 
   Status WriteTLS();
 
+  Status ReadSMESVG();
+
   Status ReadZAHeader();
 
   Status ReadZA();
@@ -176,6 +184,8 @@
 
   void *GetTLSBuffer() { return _tls_regs; }
 
+  void *GetSMEPseudoBuffer() { return _sme_pseudo_regs; }
+
   void *GetSVEBuffer() { return m_sve_ptrace_payload.data(); }
 
   size_t GetSVEHeaderSize() { return sizeof(m_sve_header); }
@@ -194,6 +204,8 @@
 
   size_t GetTLSBufferSize() { return m_tls_size; }
 
+  size_t GetSMEPseudoBufferSize() { return sizeof(m_sme_pseudo_regs); }
+
   llvm::Error ReadHardwareDebugInfo() override;
 
   llvm::Error WriteHardwareDebugRegs(DREGType hwbType) override;
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
===
--- lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+++ lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
@@ -147,6 +147,7 @@
   ::memset(_sve_header, 0, sizeof(m_sve_header));
   

[Lldb-commits] [PATCH] D159502: [lldb][AArch64] Add SME's Array Storage (ZA) register

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 557007.
DavidSpickett added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159502/new/

https://reviews.llvm.org/D159502

Files:
  lldb/include/lldb/Utility/RegisterValue.h
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
  lldb/source/Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h
  lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.cpp
  lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
  lldb/source/Plugins/Process/elf-core/RegisterUtilities.h

Index: lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
===
--- lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
+++ lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
@@ -119,6 +119,10 @@
 {llvm::Triple::Linux, llvm::Triple::aarch64, llvm::ELF::NT_ARM_SVE},
 };
 
+constexpr RegsetDesc AARCH64_ZA_Desc[] = {
+{llvm::Triple::Linux, llvm::Triple::aarch64, llvm::ELF::NT_ARM_ZA},
+};
+
 constexpr RegsetDesc AARCH64_PAC_Desc[] = {
 {llvm::Triple::Linux, llvm::Triple::aarch64, llvm::ELF::NT_ARM_PAC_MASK},
 };
Index: lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
===
--- lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
+++ lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
@@ -113,7 +113,7 @@
 m_sve_state = SVEState::Disabled;
 
   if (m_sve_state != SVEState::Disabled)
-m_register_info_up->ConfigureVectorLength(
+m_register_info_up->ConfigureVectorLengthSVE(
 sve::vq_from_vl(m_sve_vector_length));
 }
 
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
@@ -30,6 +30,7 @@
 eRegsetMaskPAuth = 4,
 eRegsetMaskMTE = 8,
 eRegsetMaskTLS = 16,
+eRegsetMaskZA = 32,
 eRegsetMaskDynamic = ~1,
   };
 
@@ -106,7 +107,11 @@
 
   void AddRegSetTLS(bool has_tpidr2);
 
-  uint32_t ConfigureVectorLength(uint32_t sve_vq);
+  void AddRegSetSME();
+
+  uint32_t ConfigureVectorLengthSVE(uint32_t sve_vq);
+
+  void ConfigureVectorLengthZA(uint32_t za_vq);
 
   bool VectorSizeIsValid(uint32_t vq) {
 // coverity[unsigned_compare]
@@ -117,6 +122,7 @@
 
   bool IsSVEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskSVE); }
   bool IsSSVEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskSSVE); }
+  bool IsZAEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskZA); }
   bool IsPAuthEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskPAuth); }
   bool IsMTEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskMTE); }
   bool IsTLSEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskTLS); }
@@ -128,6 +134,7 @@
   bool IsPAuthReg(unsigned reg) const;
   bool IsMTEReg(unsigned reg) const;
   bool IsTLSReg(unsigned reg) const;
+  bool IsSMEReg(unsigned reg) const;
 
   uint32_t GetRegNumSVEZ0() const;
   uint32_t GetRegNumSVEFFR() const;
@@ -137,6 +144,7 @@
   uint32_t GetPAuthOffset() const;
   uint32_t GetMTEOffset() const;
   uint32_t GetTLSOffset() const;
+  uint32_t GetSMEOffset() const;
 
 private:
   typedef std::map>
@@ -145,7 +153,10 @@
   per_vq_register_infos m_per_vq_reg_infos;
 
   uint32_t m_vector_reg_vq = eVectorQuadwordAArch64;
+  uint32_t m_za_reg_vq = eVectorQuadwordAArch64;
 
+  // In normal operation this is const. Only when SVE or SME registers change
+  // size is it either replaced or the content modified.
   const lldb_private::RegisterInfo *m_register_info_p;
   uint32_t m_register_info_count;
 
@@ -164,6 +175,7 @@
   std::vector pauth_regnum_collection;
   std::vector m_mte_regnum_collection;
   std::vector m_tls_regnum_collection;
+  std::vector m_sme_regnum_collection;
 };
 
 #endif
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
@@ -83,6 +83,11 @@
 // Only present when SME is present
 DEFINE_EXTENSION_REG(tpidr2)};
 
+static lldb_private::RegisterInfo g_register_infos_sme[] =
+// 16 is a default size we will change later.
+{{"za", nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,
+  KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
+
 // Number of register sets provided 

[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

[David Spickett via Phabricator via lldb-commits]

DavidSpickett added inline comments.



Comment at: 
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py:201
+self.runCmd("register write za '{}'".format(za_value))
+self.expect("register read za", substrs=[za_value])

omjavaid wrote:
> How can we differentiate between disabled ZA (read as all zeros) and enabled 
> ZA actually set to all zeros?
In this specific test we write a non-zero value to avoid that issue, but I 
assume you mean generally.

The user should refer to the SVCR register, SVCR.ZA specifically, to know if 
the value they're seeing is the active ZA or not. You can see an example of 
that if you look at the changes to this file in 
https://reviews.llvm.org/D154927.

Again, the user has to know what bit to look for but I'll eventually address 
that with the register fields work.



Comment at: 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/Makefile:3
+
+CFLAGS_EXTRAS := -march=armv8-a+sve+sme -lpthread
+

omjavaid wrote:
> is USE_SSVE a subset of sve+sme? 
It's a define I made up for the purposes of the test, it's in the existing 
tests but not well documented. I'll push something to address that in the 
existing tests and check the new ones here for this and other defines I've 
added.

We need sve to update sve registers and sme to be able to move into the za 
register (/the rows of the za register).


Repository:
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[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

[Muhammad Omair Javaid via Phabricator via lldb-commits]

omjavaid added inline comments.



Comment at: 
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py:201
+self.runCmd("register write za '{}'".format(za_value))
+self.expect("register read za", substrs=[za_value])

How can we differentiate between disabled ZA (read as all zeros) and enabled ZA 
actually set to all zeros?



Comment at: 
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py:104
+if mode == Mode.SSVE:
+cflags += " -DUSE_SSVE"
+self.build(dictionary={"CFLAGS_EXTRAS": cflags})

is there a reference somewhere in clang or gcc documentation for USE_SSVE flag?



Comment at: 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/Makefile:3
+
+CFLAGS_EXTRAS := -march=armv8-a+sve+sme -lpthread
+

is USE_SSVE a subset of sve+sme? 


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[Lldb-commits] [PATCH] D140996: [c++20] P1907R1: Support for generalized non-type template arguments of scalar type.

[Corentin Jabot via Phabricator via lldb-commits]

cor3ntin added a comment.

It would be nice to figure out a plan for this PR in the next few weeks, before 
we get kicked out of Phab!


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[Lldb-commits] [PATCH] D159504: [lldb][AArch64] Implement resizing of SME's ZA register

[Muhammad Omair Javaid via Phabricator via lldb-commits]

omjavaid accepted this revision.
omjavaid added a comment.
This revision is now accepted and ready to land.

This look good


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[Lldb-commits] [PATCH] D159503: [lldb][AArch64] Add SME streaming vector length pseduo register

[Muhammad Omair Javaid via Phabricator via lldb-commits]

omjavaid accepted this revision.
omjavaid added a comment.
This revision is now accepted and ready to land.

This is LGTM as you suggested pending child reviews.


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[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

[David Spickett via Phabricator via lldb-commits]

DavidSpickett added a comment.

I'll hold off landing any of the prior patches until this is reviewed, in case 
I have to go back and move things.


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[Lldb-commits] [PATCH] D158506: [lldb][AArch64] Add release notes and documentation for SME

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 556856.
DavidSpickett added a comment.

Rebase


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Files:
  lldb/docs/index.rst
  lldb/docs/use/aarch64-linux.rst
  llvm/docs/ReleaseNotes.rst

Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -183,6 +183,10 @@
 * Methods in SBHostOS related to threads have had their implementations
   removed. These methods will return a value indicating failure.
 
+* LLDB now supports debugging the Scalable Matrix Extension (SME) on AArch64
+  Linux for both running processes and core files. For details refer to the
+  `AArch64 Linux documentation `_.
+
 Changes to Sanitizers
 -
 * HWASan now defaults to detecting use-after-scope bugs.
Index: lldb/docs/use/aarch64-linux.rst
===
--- /dev/null
+++ lldb/docs/use/aarch64-linux.rst
@@ -0,0 +1,190 @@
+Using LLDB On AArch64 Linux
+===
+
+This page explains the details of debugging certain AArch64 extensions using
+LLDB. If something is not mentioned here, it likely works as you would expect.
+
+This is not a replacement for ptrace and Linux Kernel documentation. This covers
+how LLDB has chosen to use those things and how that effects your experience as
+a user.
+
+Scalable Vector Extension (SVE)
+---
+
+See `here `__
+to learn about the extension and `here `__
+for the Linux Kernel's handling of it.
+
+In LLDB you will be able to see the following new registers:
+
+* ``z0-z31`` vector registers, each one has size equal to the vector length.
+* ``p0-p15`` predicate registers, each one containing 1 bit per byte in the vector
+  length. Making each one vector length / 8 sized.
+* ``ffr`` the first fault register, same size as a predicate register.
+* ``vg``, the vector length in "granules". Each granule is 8 bytes.
+
+.. code-block::
+
+   Scalable Vector Extension Registers:
+ vg = 0x0002
+ z0 = {0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 <...> }
+   <...>
+ p0 = {0xff 0xff}
+   <...>
+ffr = {0xff 0xff}
+
+The example above has a vector length of 16 bytes. Within LLDB you will always
+see "vg" as in the ``vg`` register, which is 2 in this case (8*2 = 16).
+Elsewhere you may see "vq" which is the vector length in quadwords (16 bytes)
+elsewhere. Where you see "vl", it is in bytes.
+
+Changing the Vector Length
+..
+
+While you can count the size of a P or Z register, it is intended that ``vg`` be
+used to find the current vector length.
+
+vg can be written. Writing the current vector length changes nothing. If you
+increase the vector length, the registers will likely be reset to 0. If you
+decrease it, LLDB will truncate the Z registers but everything else will be reset
+to 0.
+
+Generally you should not assume that SVE state after changing the vector length
+is in any way the same as it was previously. If you need to do it, do it before
+a function's first use of SVE.
+
+Z Register Presentation
+...
+
+LLDB makes no attempt to predict how an SVE Z register will be used. Even if the
+next SVE instruction (which may some distance away) would use, for example, 32
+bit elements, LLDB prints ``z0`` as single bytes.
+
+If you know what format you are going to use, give a format option::
+
+  (lldb) register read z0 -f uint32_t[]
+  z0 = {0x01010101 0x01010101 0x01010101 0x01010101}
+
+FPSIMD and SVE Modes
+
+
+Prior to the debugee's first use of SVE, it is in what the Linux Kernel terms
+SIMD mode. Only the FPU is being used. In this state LLDB will still show the
+SVE registers however the values are simply the FPU values zero extended up to
+the vector length.
+
+On first access to SVE, the process goes into SVE mode. Now the Z values are
+in the real Z registers.
+
+You can also trigger this with LLDB by writing to an SVE register. Note that
+there is no way to undo this change from within LLDB. However, the debugee
+itself could do something to end up back in SIMD mode.
+
+Expression evaluation
+.
+
+If you evaluate an expression, all SVE state is saved prior to, and restored
+after the expression has been evaluated. Including the register values and
+vector length.
+
+Scalable Matrix Extension (SME)
+---
+
+See `here `__
+to learn about the extension and 

[Lldb-commits] [PATCH] D158500: [lldb][AArch64] Linux corefile support for SME

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 556855.
DavidSpickett added a comment.

sme_regs -> sme_pseudo_regs and rebase.


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Files:
  lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h
  lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
  lldb/test/API/linux/aarch64/sme_core_file/TestAArch64LinuxSMECoreFile.py
  lldb/test/API/linux/aarch64/sme_core_file/core_0_16_32_1
  lldb/test/API/linux/aarch64/sme_core_file/core_0_32_16_0
  lldb/test/API/linux/aarch64/sme_core_file/core_1_16_32_0
  lldb/test/API/linux/aarch64/sme_core_file/core_1_32_16_1
  lldb/test/API/linux/aarch64/sme_core_file/main.c

Index: lldb/test/API/linux/aarch64/sme_core_file/main.c
===
--- /dev/null
+++ lldb/test/API/linux/aarch64/sme_core_file/main.c
@@ -0,0 +1,140 @@
+// clang-format off
+// Compile with:
+// clang -target aarch64-unknown-linux-gnu main.c -o a.out -g -march=armv8.6-a+sve+sme
+//
+// For minimal corefile size, do this before running the program:
+// echo 0x20 > /proc/self/coredeump_filter
+//
+// Must be run on a system that has SVE and SME, including the smefa64
+// extension. Example command:
+// main 0 32 64 1
+//
+// This would not enter streaming mode, set non-streaming VL to 32
+// bytes, streaming VL to 64 bytes and enable ZA.
+// clang-format on
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#endif
+
+#define SM_INST(c) asm volatile("msr s0_3_c4_c" #c "_3, xzr")
+#define SMSTART_SM SM_INST(3)
+#define SMSTART_ZA SM_INST(5)
+
+void set_sve_registers() {
+  // We assume the smefa64 feature is present, which allows ffr access
+  // in streaming mode.
+  asm volatile("setffr\n\t");
+  asm volatile("ptrue p0.b\n\t");
+  asm volatile("ptrue p1.h\n\t");
+  asm volatile("ptrue p2.s\n\t");
+  asm volatile("ptrue p3.d\n\t");
+  asm volatile("pfalse p4.b\n\t");
+  asm volatile("ptrue p5.b\n\t");
+  asm volatile("ptrue p6.h\n\t");
+  asm volatile("ptrue p7.s\n\t");
+  asm volatile("ptrue p8.d\n\t");
+  asm volatile("pfalse p9.b\n\t");
+  asm volatile("ptrue p10.b\n\t");
+  asm volatile("ptrue p11.h\n\t");
+  asm volatile("ptrue p12.s\n\t");
+  asm volatile("ptrue p13.d\n\t");
+  asm volatile("pfalse p14.b\n\t");
+  asm volatile("ptrue p15.b\n\t");
+
+  asm volatile("cpy  z0.b, p0/z, #1\n\t");
+  asm volatile("cpy  z1.b, p5/z, #2\n\t");
+  asm volatile("cpy  z2.b, p10/z, #3\n\t");
+  asm volatile("cpy  z3.b, p15/z, #4\n\t");
+  asm volatile("cpy  z4.b, p0/z, #5\n\t");
+  asm volatile("cpy  z5.b, p5/z, #6\n\t");
+  asm volatile("cpy  z6.b, p10/z, #7\n\t");
+  asm volatile("cpy  z7.b, p15/z, #8\n\t");
+  asm volatile("cpy  z8.b, p0/z, #9\n\t");
+  asm volatile("cpy  z9.b, p5/z, #10\n\t");
+  asm volatile("cpy  z10.b, p10/z, #11\n\t");
+  asm volatile("cpy  z11.b, p15/z, #12\n\t");
+  asm volatile("cpy  z12.b, p0/z, #13\n\t");
+  asm volatile("cpy  z13.b, p5/z, #14\n\t");
+  asm volatile("cpy  z14.b, p10/z, #15\n\t");
+  asm volatile("cpy  z15.b, p15/z, #16\n\t");
+  asm volatile("cpy  z16.b, p0/z, #17\n\t");
+  asm volatile("cpy  z17.b, p5/z, #18\n\t");
+  asm volatile("cpy  z18.b, p10/z, #19\n\t");
+  asm volatile("cpy  z19.b, p15/z, #20\n\t");
+  asm volatile("cpy  z20.b, p0/z, #21\n\t");
+  asm volatile("cpy  z21.b, p5/z, #22\n\t");
+  asm volatile("cpy  z22.b, p10/z, #23\n\t");
+  asm volatile("cpy  z23.b, p15/z, #24\n\t");
+  asm volatile("cpy  z24.b, p0/z, #25\n\t");
+  asm volatile("cpy  z25.b, p5/z, #26\n\t");
+  asm volatile("cpy  z26.b, p10/z, #27\n\t");
+  asm volatile("cpy  z27.b, p15/z, #28\n\t");
+  asm volatile("cpy  z28.b, p0/z, #29\n\t");
+  asm volatile("cpy  z29.b, p5/z, #30\n\t");
+  asm volatile("cpy  z30.b, p10/z, #31\n\t");
+  asm volatile("cpy  z31.b, p15/z, #32\n\t");
+}
+
+void set_za_register(int streaming_vl) {
+#define MAX_VL_BYTES 256
+  uint8_t data[MAX_VL_BYTES];
+
+  for (unsigned i = 0; i < streaming_vl; ++i) {
+for (unsigned j = 0; j < MAX_VL_BYTES; ++j)
+  data[j] = i + 1;
+asm volatile("mov w12, %w0\n\t"
+ "ldr za[w12, 0], [%1]\n\t" ::"r"(i),
+ "r"()
+ : "w12");
+  }
+}
+
+void set_tpidr2(uint64_t value) {
+  __asm__ volatile("msr S3_3_C13_C0_5, %0" ::"r"(value));
+}
+
+int main(int argc, char **argv) {
+  // Arguments:
+  //  SVE mode: 1 for streaming SVE (SSVE), any other value
+  //  for non-streaming SVE mode.
+  //   Non-Streaming Vector length: In bytes, an integer e.g. "32".
+  //   Streaming Vector length: As above, but for streaming mode.
+  //   ZA mode: 1 for enabled, any other value for disabled.
+  if (argc != 5)
+return 1;
+
+  

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 556854.
DavidSpickett added a comment.

Rebase, use new sme_pseudo_regs naming.


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Files:
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
  
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py

Index: lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
===
--- lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
+++ lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
@@ -164,6 +164,10 @@
 self.runCmd("register read " + sve_reg_names)
 sve_values = self.res.GetOutput()
 
+svcr_value = 1 if sve_mode == Mode.SSVE else 0
+if za_state == ZA.Enabled:
+svcr_value += 2
+
 def check_regs():
 if za_state == ZA.Enabled:
 self.check_za(start_vl)
@@ -175,6 +179,7 @@
 self.assertEqual(start_vg, self.read_vg())
 
 self.expect("register read " + sve_reg_names, substrs=[sve_values])
+self.expect("register read svcr", substrs=["0x{:016x}".format(svcr_value)])
 
 for expr in exprs:
 expr_cmd = "expression {}()".format(expr)
Index: lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
===
--- lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
+++ lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
@@ -5,7 +5,7 @@
 #define PR_SME_SET_VL 63
 #endif
 
-#define SMSTART() asm volatile("msr  s0_3_c4_c7_3, xzr" /*smstart*/)
+#define SMSTART_SM() asm volatile("msr  s0_3_c4_c3_3, xzr" /*smstart sm*/)
 
 void write_sve_regs() {
   // We assume the smefa64 feature is present, which allows ffr access
@@ -126,18 +126,18 @@
   // Note that doing a syscall brings you back to non-streaming mode, so we
   // don't need to SMSTOP here.
   if (streaming)
-SMSTART();
+SMSTART_SM();
   write_sve_regs_expr();
   prctl(SET_VL_OPT, 8 * 4);
   if (streaming)
-SMSTART();
+SMSTART_SM();
   write_sve_regs_expr();
   return 1;
 }
 
 int main() {
 #ifdef START_SSVE
-  SMSTART();
+  SMSTART_SM();
 #endif
   write_sve_regs();
 
Index: lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
===
--- lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
+++ lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
@@ -24,7 +24,15 @@
 reg_value.GetByteSize(), expected, 'Verify "%s" == %i' % (name, expected)
 )
 
-def check_sve_regs_read(self, z_reg_size):
+def check_sve_regs_read(self, z_reg_size, expected_mode):
+if self.isAArch64SME():
+# This test uses SMSTART SM, which only enables streaming mode,
+# leaving ZA disabled.
+expected_value = "1" if expected_mode == Mode.SSVE else "0"
+self.expect(
+"register read svcr", substrs=["0x000" + expected_value]
+)
+
 p_reg_size = int(z_reg_size / 8)
 
 for i in range(32):
@@ -168,7 +176,7 @@
 
 vg_reg_value = sve_registers.GetChildMemberWithName("vg").GetValueAsUnsigned()
 z_reg_size = vg_reg_value * 8
-self.check_sve_regs_read(z_reg_size)
+self.check_sve_regs_read(z_reg_size, start_mode)
 
 # Evaluate simple expression and print function expr_eval_func address.
 self.expect("expression expr_eval_func", substrs=["= 0x"])
@@ -184,7 +192,7 @@
 
 # We called a jitted function above which must not have changed SVE
 # vector length or register values.
-self.check_sve_regs_read(z_reg_size)
+self.check_sve_regs_read(z_reg_size, start_mode)
 
 self.check_sve_regs_read_after_write(z_reg_size)
 
Index: lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py

[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 556853.
DavidSpickett added a comment.

Rebase


Repository:
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Files:
  
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
  
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/Makefile
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/main.c
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/Makefile
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py
  
lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c

Index: lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c
===
--- /dev/null
+++ lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/main.c
@@ -0,0 +1,226 @@
+#include 
+#include 
+#include 
+#include 
+#include 
+
+// Important details for this program:
+// * Making a syscall will disable streaming mode if it is active.
+// * Changing the vector length will make streaming mode and ZA inactive.
+// * ZA can be active independent of streaming mode.
+// * ZA's size is the streaming vector length squared.
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#endif
+
+#ifndef PR_SME_GET_VL
+#define PR_SME_GET_VL 64
+#endif
+
+#ifndef PR_SME_VL_LEN_MASK
+#define PR_SME_VL_LEN_MASK 0x
+#endif
+
+#define SM_INST(c) asm volatile("msr s0_3_c4_c" #c "_3, xzr")
+#define SMSTART SM_INST(7)
+#define SMSTART_SM SM_INST(3)
+#define SMSTART_ZA SM_INST(5)
+#define SMSTOP SM_INST(6)
+#define SMSTOP_SM SM_INST(2)
+#define SMSTOP_ZA SM_INST(4)
+
+int start_vl = 0;
+int other_vl = 0;
+
+void write_sve_regs() {
+  // We assume the smefa64 feature is present, which allows ffr access
+  // in streaming mode.
+  asm volatile("setffr\n\t");
+  asm volatile("ptrue p0.b\n\t");
+  asm volatile("ptrue p1.h\n\t");
+  asm volatile("ptrue p2.s\n\t");
+  asm volatile("ptrue p3.d\n\t");
+  asm volatile("pfalse p4.b\n\t");
+  asm volatile("ptrue p5.b\n\t");
+  asm volatile("ptrue p6.h\n\t");
+  asm volatile("ptrue p7.s\n\t");
+  asm volatile("ptrue p8.d\n\t");
+  asm volatile("pfalse p9.b\n\t");
+  asm volatile("ptrue p10.b\n\t");
+  asm volatile("ptrue p11.h\n\t");
+  asm volatile("ptrue p12.s\n\t");
+  asm volatile("ptrue p13.d\n\t");
+  asm volatile("pfalse p14.b\n\t");
+  asm volatile("ptrue p15.b\n\t");
+
+  asm volatile("cpy  z0.b, p0/z, #1\n\t");
+  asm volatile("cpy  z1.b, p5/z, #2\n\t");
+  asm volatile("cpy  z2.b, p10/z, #3\n\t");
+  asm volatile("cpy  z3.b, p15/z, #4\n\t");
+  asm volatile("cpy  z4.b, p0/z, #5\n\t");
+  asm volatile("cpy  z5.b, p5/z, #6\n\t");
+  asm volatile("cpy  z6.b, p10/z, #7\n\t");
+  asm volatile("cpy  z7.b, p15/z, #8\n\t");
+  asm volatile("cpy  z8.b, p0/z, #9\n\t");
+  asm volatile("cpy  z9.b, p5/z, #10\n\t");
+  asm volatile("cpy  z10.b, p10/z, #11\n\t");
+  asm volatile("cpy  z11.b, p15/z, #12\n\t");
+  asm volatile("cpy  z12.b, p0/z, #13\n\t");
+  asm volatile("cpy  z13.b, p5/z, #14\n\t");
+  asm volatile("cpy  z14.b, p10/z, #15\n\t");
+  asm volatile("cpy  z15.b, p15/z, #16\n\t");
+  asm volatile("cpy  z16.b, p0/z, #17\n\t");
+  asm volatile("cpy  z17.b, p5/z, #18\n\t");
+  asm volatile("cpy  z18.b, p10/z, #19\n\t");
+  asm volatile("cpy  z19.b, p15/z, #20\n\t");
+  asm volatile("cpy  z20.b, p0/z, #21\n\t");
+  asm volatile("cpy  z21.b, p5/z, #22\n\t");
+  asm volatile("cpy  z22.b, p10/z, #23\n\t");
+  asm volatile("cpy  z23.b, p15/z, #24\n\t");
+  asm volatile("cpy  z24.b, p0/z, #25\n\t");
+  asm volatile("cpy  z25.b, p5/z, #26\n\t");
+  asm volatile("cpy  z26.b, p10/z, #27\n\t");
+  asm volatile("cpy  z27.b, p15/z, #28\n\t");
+  asm volatile("cpy  z28.b, p0/z, #29\n\t");
+  asm volatile("cpy  z29.b, p5/z, #30\n\t");
+  asm volatile("cpy  z30.b, p10/z, #31\n\t");
+  asm volatile("cpy  z31.b, p15/z, #32\n\t");
+}
+
+// Write something different so we will know if we didn't restore them
+// correctly.
+void write_sve_regs_expr() {
+  asm volatile("pfalse p0.b\n\t");
+  asm volatile("wrffr p0.b\n\t");
+  asm volatile("pfalse p1.b\n\t");
+  asm volatile("pfalse p2.b\n\t");
+  asm volatile("pfalse p3.b\n\t");
+  asm volatile("ptrue p4.b\n\t");
+  asm volatile("pfalse p5.b\n\t");
+  asm volatile("pfalse p6.b\n\t");
+  asm volatile("pfalse p7.b\n\t");
+  asm volatile("pfalse p8.b\n\t");
+  asm volatile("ptrue p9.b\n\t");
+  asm volatile("pfalse p10.b\n\t");
+  asm volatile("pfalse p11.b\n\t");
+  asm volatile("pfalse p12.b\n\t");
+  asm volatile("pfalse p13.b\n\t");
+  asm 

[Lldb-commits] [PATCH] D159504: [lldb][AArch64] Implement resizing of SME's ZA register

[David Spickett via Phabricator via lldb-commits]

DavidSpickett marked an inline comment as done.
DavidSpickett added inline comments.



Comment at: 
lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp:839
+
+void GDBRemoteDynamicRegisterInfo::UpdateARM64SMERegistersInfos(uint64_t svg) {
+  for (auto  : m_regs) {

omjavaid wrote:
> can we combine UpdateARM64SVERegistersInfos and UpdateARM64SMERegistersInfos 
> to avoid back to back calls of ConfigureOffsets
Yes, done. See comments for weird details.


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[Lldb-commits] [PATCH] D159504: [lldb][AArch64] Implement resizing of SME's ZA register

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 556852.
DavidSpickett added a comment.

Combine reconfigure into one function. The tricky thing is we have to read
svg and vg up front because we can't read registers while we're messing
with register offsets.

Otherwise, the result is a bit clearer and it also avoids a second heap
allocation for the storage.


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Files:
  lldb/include/lldb/Target/DynamicRegisterInfo.h
  lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
  lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
  lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
  lldb/source/Target/DynamicRegisterInfo.cpp

Index: lldb/source/Target/DynamicRegisterInfo.cpp
===
--- lldb/source/Target/DynamicRegisterInfo.cpp
+++ lldb/source/Target/DynamicRegisterInfo.cpp
@@ -614,10 +614,11 @@
   ConfigureOffsets();
 
   // Check if register info is reconfigurable
-  // AArch64 SVE register set has configurable register sizes
+  // AArch64 SVE register set has configurable register sizes, as does the ZA
+  // register that SME added (the streaming state of SME reuses the SVE state).
   if (arch.GetTriple().isAArch64()) {
 for (const auto  : m_regs) {
-  if (strcmp(reg.name, "vg") == 0) {
+  if ((strcmp(reg.name, "vg") == 0) || (strcmp(reg.name, "svg") == 0)) {
 m_is_reconfigurable = true;
 break;
   }
Index: lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
===
--- lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+++ lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
@@ -1660,17 +1660,18 @@
 gdb_thread->PrivateSetRegisterValue(lldb_regnum, buffer_sp->GetData());
   }
 
-  // AArch64 SVE specific code below calls AArch64SVEReconfigure to update
-  // SVE register sizes and offsets if value of VG register has changed
-  // since last stop.
+  // AArch64 SVE/SME specific code below updates SVE and ZA register sizes and
+  // offsets if value of VG or SVG registers has changed since last stop.
   const ArchSpec  = GetTarget().GetArchitecture();
   if (arch.IsValid() && arch.GetTriple().isAArch64()) {
 GDBRemoteRegisterContext *reg_ctx_sp =
 static_cast(
 gdb_thread->GetRegisterContext().get());
 
-if (reg_ctx_sp)
-  reg_ctx_sp->AArch64SVEReconfigure();
+if (reg_ctx_sp) {
+  reg_ctx_sp->AArch64Reconfigure();
+  reg_ctx_sp->InvalidateAllRegisters();
+}
   }
 
   thread_sp->SetName(thread_name.empty() ? nullptr : thread_name.c_str());
Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
===
--- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
+++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
@@ -39,6 +39,7 @@
   ~GDBRemoteDynamicRegisterInfo() override = default;
 
   void UpdateARM64SVERegistersInfos(uint64_t vg);
+  void UpdateARM64SMERegistersInfos(uint64_t svg);
 };
 
 class GDBRemoteRegisterContext : public RegisterContext {
@@ -77,7 +78,8 @@
   uint32_t ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind,
uint32_t num) override;
 
-  bool AArch64SVEReconfigure();
+  // Reconfigure variable sized registers for AArch64 SVE and SME.
+  void AArch64Reconfigure();
 
 protected:
   friend class ThreadGDBRemote;
Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
===
--- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
+++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
@@ -373,14 +373,14 @@
   if (dst == nullptr)
 return false;
 
-  // Code below is specific to AArch64 target in SVE state
+  // Code below is specific to AArch64 target in SVE or SME state
   // If vector granule (vg) register is being written then thread's
   // register context reconfiguration is triggered on success.
-  bool do_reconfigure_arm64_sve = false;
+  // We do not allow writes to SVG so it is not mentioned here.
   const ArchSpec  = process->GetTarget().GetArchitecture();
-  if (arch.IsValid() && arch.GetTriple().isAArch64())
-if (strcmp(reg_info->name, "vg") == 0)
-  do_reconfigure_arm64_sve = true;
+  bool do_reconfigure_arm64_sve = arch.IsValid() &&
+  arch.GetTriple().isAArch64() &&
+  (strcmp(reg_info->name, "vg") == 0);
 
   if (data.CopyByteOrderedData(data_offset,// src offset
reg_info->byte_size,// src length
@@ -400,10 +400,10 @@
 {m_reg_data.GetDataStart(), 

[Lldb-commits] [PATCH] D159503: [lldb][AArch64] Add SME streaming vector length pseduo register

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 556851.
DavidSpickett added a comment.

Rebase


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Files:
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
@@ -135,12 +135,14 @@
   bool IsMTEReg(unsigned reg) const;
   bool IsTLSReg(unsigned reg) const;
   bool IsSMEReg(unsigned reg) const;
+  bool IsSMERegZA(unsigned reg) const;
 
   uint32_t GetRegNumSVEZ0() const;
   uint32_t GetRegNumSVEFFR() const;
   uint32_t GetRegNumFPCR() const;
   uint32_t GetRegNumFPSR() const;
   uint32_t GetRegNumSVEVG() const;
+  uint32_t GetRegNumSMESVG() const;
   uint32_t GetPAuthOffset() const;
   uint32_t GetMTEOffset() const;
   uint32_t GetTLSOffset() const;
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
@@ -83,10 +83,11 @@
 // Only present when SME is present
 DEFINE_EXTENSION_REG(tpidr2)};
 
-static lldb_private::RegisterInfo g_register_infos_sme[] =
+static lldb_private::RegisterInfo g_register_infos_sme[] = {
+DEFINE_EXTENSION_REG(svg),
 // 16 is a default size we will change later.
-{{"za", nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,
-  KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
+{"za", nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,
+ KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
 
 // Number of register sets provided by this context.
 enum {
@@ -96,7 +97,7 @@
   k_num_mte_register = 1,
   // Number of TLS registers is dynamic so it is not listed here.
   k_num_pauth_register = 2,
-  k_num_sme_register = 1,
+  k_num_sme_register = 2,
   k_num_register_sets_default = 2,
   k_num_register_sets = 3
 };
@@ -448,7 +449,7 @@
   // dynamic set and is just 1 register so we make an exception to const here.
   lldb_private::RegisterInfo *non_const_reginfo =
   const_cast(m_register_info_p);
-  non_const_reginfo[m_sme_regnum_collection[0]].byte_size =
+  non_const_reginfo[m_sme_regnum_collection[1]].byte_size =
   (za_vq * 16) * (za_vq * 16);
 }
 
@@ -471,6 +472,10 @@
   return sve_vg == reg;
 }
 
+bool RegisterInfoPOSIX_arm64::IsSMERegZA(unsigned reg) const {
+  return reg == m_sme_regnum_collection[1];
+}
+
 bool RegisterInfoPOSIX_arm64::IsPAuthReg(unsigned reg) const {
   return llvm::is_contained(pauth_regnum_collection, reg);
 }
@@ -497,6 +502,10 @@
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; }
 
+uint32_t RegisterInfoPOSIX_arm64::GetRegNumSMESVG() const {
+  return m_sme_regnum_collection[0];
+}
+
 uint32_t RegisterInfoPOSIX_arm64::GetPAuthOffset() const {
   return m_register_info_p[pauth_regnum_collection[0]].byte_offset;
 }
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
===
--- lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
+++ lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
@@ -114,6 +114,12 @@
 
   uint64_t m_mte_ctrl_reg;
 
+  struct sme_pseudo_regs {
+uint64_t svg_reg;
+  };
+
+  struct sme_pseudo_regs m_sme_pseudo_regs;
+
   struct tls_regs {
 uint64_t tpidr_reg;
 // Only valid when SME is present.
@@ -144,6 +150,8 @@
 
   Status WriteTLS();
 
+  Status ReadSMESVG();
+
   Status ReadZAHeader();
 
   Status ReadZA();
@@ -176,6 +184,8 @@
 
   void *GetTLSBuffer() { return _tls_regs; }
 
+  void *GetSMEPseudoBuffer() { return _sme_pseudo_regs; }
+
   void *GetSVEBuffer() { return m_sve_ptrace_payload.data(); }
 
   size_t GetSVEHeaderSize() { return sizeof(m_sve_header); }
@@ -194,6 +204,8 @@
 
   size_t GetTLSBufferSize() { return m_tls_size; }
 
+  size_t GetSMEPseudoBufferSize() { return sizeof(m_sme_pseudo_regs); }
+
   llvm::Error ReadHardwareDebugInfo() override;
 
   llvm::Error WriteHardwareDebugRegs(DREGType hwbType) override;
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
===
--- lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+++ lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
@@ -147,6 +147,7 @@
   ::memset(_sve_header, 0, sizeof(m_sve_header));
   

[Lldb-commits] [PATCH] D159503: [lldb][AArch64] Add SME streaming vector length pseduo register

[David Spickett via Phabricator via lldb-commits]

DavidSpickett added a comment.

Note that GetSMEOffset refers to the whole register set which does include ZA, 
so no change of name there.


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[Lldb-commits] [PATCH] D159503: [lldb][AArch64] Add SME streaming vector length pseduo register

[David Spickett via Phabricator via lldb-commits]

DavidSpickett marked 2 inline comments as done.
DavidSpickett added a comment.

Will apply the rename in core files as well later.


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[Lldb-commits] [PATCH] D159503: [lldb][AArch64] Add SME streaming vector length pseduo register

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 556844.
DavidSpickett added a comment.

- sme_regs -> sme_pseudo_regs, also changed the accesor method names.
- clang-format


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Files:
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
@@ -135,12 +135,14 @@
   bool IsMTEReg(unsigned reg) const;
   bool IsTLSReg(unsigned reg) const;
   bool IsSMEReg(unsigned reg) const;
+  bool IsSMERegZA(unsigned reg) const;
 
   uint32_t GetRegNumSVEZ0() const;
   uint32_t GetRegNumSVEFFR() const;
   uint32_t GetRegNumFPCR() const;
   uint32_t GetRegNumFPSR() const;
   uint32_t GetRegNumSVEVG() const;
+  uint32_t GetRegNumSMESVG() const;
   uint32_t GetPAuthOffset() const;
   uint32_t GetMTEOffset() const;
   uint32_t GetTLSOffset() const;
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
===
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
@@ -83,10 +83,11 @@
 // Only present when SME is present
 DEFINE_EXTENSION_REG(tpidr2)};
 
-static lldb_private::RegisterInfo g_register_infos_sme[] =
+static lldb_private::RegisterInfo g_register_infos_sme[] = {
+DEFINE_EXTENSION_REG(svg),
 // 16 is a default size we will change later.
-{{"za", nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,
-  KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
+{"za", nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,
+ KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
 
 // Number of register sets provided by this context.
 enum {
@@ -96,7 +97,7 @@
   k_num_mte_register = 1,
   // Number of TLS registers is dynamic so it is not listed here.
   k_num_pauth_register = 2,
-  k_num_sme_register = 1,
+  k_num_sme_register = 2,
   k_num_register_sets_default = 2,
   k_num_register_sets = 3
 };
@@ -448,7 +449,7 @@
   // dynamic set and is just 1 register so we make an exception to const here.
   lldb_private::RegisterInfo *non_const_reginfo =
   const_cast(m_register_info_p);
-  non_const_reginfo[m_sme_regnum_collection[0]].byte_size =
+  non_const_reginfo[m_sme_regnum_collection[1]].byte_size =
   (za_vq * 16) * (za_vq * 16);
 }
 
@@ -471,6 +472,10 @@
   return sve_vg == reg;
 }
 
+bool RegisterInfoPOSIX_arm64::IsSMERegZA(unsigned reg) const {
+  return reg == m_sme_regnum_collection[1];
+}
+
 bool RegisterInfoPOSIX_arm64::IsPAuthReg(unsigned reg) const {
   return llvm::is_contained(pauth_regnum_collection, reg);
 }
@@ -497,6 +502,10 @@
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; }
 
+uint32_t RegisterInfoPOSIX_arm64::GetRegNumSMESVG() const {
+  return m_sme_regnum_collection[0];
+}
+
 uint32_t RegisterInfoPOSIX_arm64::GetPAuthOffset() const {
   return m_register_info_p[pauth_regnum_collection[0]].byte_offset;
 }
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
===
--- lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
+++ lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
@@ -114,6 +114,12 @@
 
   uint64_t m_mte_ctrl_reg;
 
+  struct sme_pseudo_regs {
+uint64_t svg_reg;
+  };
+
+  struct sme_pseudo_regs m_sme_pseudo_regs;
+
   struct tls_regs {
 uint64_t tpidr_reg;
 // Only valid when SME is present.
@@ -144,6 +150,8 @@
 
   Status WriteTLS();
 
+  Status ReadSMESVG();
+
   Status ReadZAHeader();
 
   Status ReadZA();
@@ -176,6 +184,8 @@
 
   void *GetTLSBuffer() { return _tls_regs; }
 
+  void *GetSMEPseudoBuffer() { return _sme_pseudo_regs; }
+
   void *GetSVEBuffer() { return m_sve_ptrace_payload.data(); }
 
   size_t GetSVEHeaderSize() { return sizeof(m_sve_header); }
@@ -194,6 +204,8 @@
 
   size_t GetTLSBufferSize() { return m_tls_size; }
 
+  size_t GetSMEPseudoBufferSize() { return sizeof(m_sme_pseudo_regs); }
+
   llvm::Error ReadHardwareDebugInfo() override;
 
   llvm::Error WriteHardwareDebugRegs(DREGType hwbType) override;
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
===
--- lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+++ lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
@@ 

[Lldb-commits] [PATCH] D159504: [lldb][AArch64] Implement resizing of SME's ZA register

[Muhammad Omair Javaid via Phabricator via lldb-commits]

omjavaid added inline comments.



Comment at: 
lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp:839
+
+void GDBRemoteDynamicRegisterInfo::UpdateARM64SMERegistersInfos(uint64_t svg) {
+  for (auto  : m_regs) {

can we combine UpdateARM64SVERegistersInfos and UpdateARM64SMERegistersInfos to 
avoid back to back calls of ConfigureOffsets


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[Lldb-commits] [PATCH] D159503: [lldb][AArch64] Add SME streaming vector length pseduo register

[Muhammad Omair Javaid via Phabricator via lldb-commits]

omjavaid added a comment.

This looks find just couple of nits inline.




Comment at: 
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:354
+
+  // ZA is part of the SME set but uses a seperate member buffer for 
storage.
+  // Therefore its effective byte offset is always 0 even if it isn't 0 
within

this block of code requires clang-format run



Comment at: 
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h:117
 
+  struct sme_regs {
+uint64_t svg_reg;

should we name this to sme_pseudo_regs ? sme_regs suggests struct could include 
ZA as well.


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[Lldb-commits] [PATCH] D159502: [lldb][AArch64] Add SME's Array Storage (ZA) register

[Muhammad Omair Javaid via Phabricator via lldb-commits]

omjavaid accepted this revision.
omjavaid added a comment.
This revision is now accepted and ready to land.

This is LGTM. Thanks for your patience.


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[Lldb-commits] [PATCH] D159313: [lldb][NFCI] Remove use of ConstString in StructuredData

[Alex Langford via Phabricator via lldb-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa5a2a5a3eca0: [lldb][NFCI] Remove use of ConstString in 
StructuredData (authored by bulbazord).

Repository:
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Files:
  lldb/include/lldb/Utility/StructuredData.h
  lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
  lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
  lldb/source/Plugins/SymbolVendor/MacOSX/SymbolVendorMacOSX.cpp
  lldb/source/Target/Target.cpp
  lldb/source/Utility/StructuredData.cpp

Index: lldb/source/Utility/StructuredData.cpp
===
--- lldb/source/Utility/StructuredData.cpp
+++ lldb/source/Utility/StructuredData.cpp
@@ -162,8 +162,18 @@
 
 void StructuredData::Dictionary::Serialize(json::OStream ) const {
   s.objectBegin();
-  for (const auto  : m_dict) {
-s.attributeBegin(pair.first.GetStringRef());
+
+  // To ensure the output format is always stable, we sort the dictionary by key
+  // first.
+  using Entry = std::pair;
+  std::vector sorted_entries;
+  for (const auto  : m_dict)
+sorted_entries.push_back({pair.first(), pair.second});
+
+  llvm::sort(sorted_entries);
+
+  for (const auto  : sorted_entries) {
+s.attributeBegin(pair.first);
 pair.second->Serialize(s);
 s.attributeEnd();
   }
@@ -228,9 +238,20 @@
 
 void StructuredData::Dictionary::GetDescription(lldb_private::Stream ) const {
   size_t indentation_level = s.GetIndentLevel();
-  for (auto iter = m_dict.begin(); iter != m_dict.end(); iter++) {
+
+  // To ensure the output format is always stable, we sort the dictionary by key
+  // first.
+  using Entry = std::pair;
+  std::vector sorted_entries;
+  for (const auto  : m_dict)
+sorted_entries.push_back({pair.first(), pair.second});
+
+  llvm::sort(sorted_entries);
+
+  for (auto iter = sorted_entries.begin(); iter != sorted_entries.end();
+   iter++) {
 // Sanitize.
-if (iter->first.IsNull() || iter->first.IsEmpty() || !iter->second)
+if (iter->first.empty() || !iter->second)
   continue;
 
 // Reset original indentation level.
@@ -238,7 +259,7 @@
 s.Indent();
 
 // Print key.
-s.Printf("%s:", iter->first.AsCString());
+s.Format("{0}:", iter->first);
 
 // Return to new line and increase indentation if value is record type.
 // Otherwise add spacing.
@@ -252,7 +273,7 @@
 
 // Print value and new line if now last pair.
 iter->second->GetDescription(s);
-if (std::next(iter) != m_dict.end())
+if (std::next(iter) != sorted_entries.end())
   s.EOL();
 
 // Reset indentation level if it was incremented previously.
Index: lldb/source/Target/Target.cpp
===
--- lldb/source/Target/Target.cpp
+++ lldb/source/Target/Target.cpp
@@ -3859,11 +3859,10 @@
   s.Indent("Args:\n");
   s.SetIndentLevel(s.GetIndentLevel() + 4);
 
-  auto print_one_element = [](ConstString key,
+  auto print_one_element = [](llvm::StringRef key,
 StructuredData::Object *object) {
 s.Indent();
-s.Printf("%s : %s\n", key.GetCString(),
-  object->GetStringValue().str().c_str());
+s.Format("{0} : {1}\n", key, object->GetStringValue());
 return true;
   };
 
Index: lldb/source/Plugins/SymbolVendor/MacOSX/SymbolVendorMacOSX.cpp
===
--- lldb/source/Plugins/SymbolVendor/MacOSX/SymbolVendorMacOSX.cpp
+++ lldb/source/Plugins/SymbolVendor/MacOSX/SymbolVendorMacOSX.cpp
@@ -224,7 +224,7 @@
   [_sp, new_style_source_remapping_dictionary,
original_DBGSourcePath_value,
do_truncate_remapping_names](
-  ConstString key,
+  llvm::StringRef key,
   StructuredData::Object *object) -> bool {
 if (object && object->GetAsString()) {
 
@@ -237,7 +237,7 @@
 DBGSourcePath = original_DBGSourcePath_value;
   }
   module_sp->GetSourceMappingList().Append(
-  key.GetStringRef(), DBGSourcePath, true);
+  key, DBGSourcePath, true);
   // With version 2 of DBGSourcePathRemapping, we
   // can chop off the last two filename parts
   // from the source remapping and get a more
@@ -245,7 +245,7 @@
   // Add this as another option in addition to
   // the full source path remap.
   if (do_truncate_remapping_names) {
-FileSpec 

[Lldb-commits] [PATCH] D159313: [lldb][NFCI] Remove use of ConstString in StructuredData

[Felipe de Azevedo Piovezan via Phabricator via lldb-commits]

fdeazeve accepted this revision.
fdeazeve added a comment.
This revision is now accepted and ready to land.

LGTM!


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[Lldb-commits] [PATCH] D159313: [lldb][NFCI] Remove use of ConstString in StructuredData

[Alex Langford via Phabricator via lldb-commits]

bulbazord updated this revision to Diff 556798.
bulbazord added a comment.

Remove unneeded lambda


Repository:
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Files:
  lldb/include/lldb/Utility/StructuredData.h
  lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
  lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
  lldb/source/Plugins/SymbolVendor/MacOSX/SymbolVendorMacOSX.cpp
  lldb/source/Target/Target.cpp
  lldb/source/Utility/StructuredData.cpp

Index: lldb/source/Utility/StructuredData.cpp
===
--- lldb/source/Utility/StructuredData.cpp
+++ lldb/source/Utility/StructuredData.cpp
@@ -162,8 +162,18 @@
 
 void StructuredData::Dictionary::Serialize(json::OStream ) const {
   s.objectBegin();
-  for (const auto  : m_dict) {
-s.attributeBegin(pair.first.GetStringRef());
+
+  // To ensure the output format is always stable, we sort the dictionary by key
+  // first.
+  using Entry = std::pair;
+  std::vector sorted_entries;
+  for (const auto  : m_dict)
+sorted_entries.push_back({pair.first(), pair.second});
+
+  llvm::sort(sorted_entries);
+
+  for (const auto  : sorted_entries) {
+s.attributeBegin(pair.first);
 pair.second->Serialize(s);
 s.attributeEnd();
   }
@@ -228,9 +238,20 @@
 
 void StructuredData::Dictionary::GetDescription(lldb_private::Stream ) const {
   size_t indentation_level = s.GetIndentLevel();
-  for (auto iter = m_dict.begin(); iter != m_dict.end(); iter++) {
+
+  // To ensure the output format is always stable, we sort the dictionary by key
+  // first.
+  using Entry = std::pair;
+  std::vector sorted_entries;
+  for (const auto  : m_dict)
+sorted_entries.push_back({pair.first(), pair.second});
+
+  llvm::sort(sorted_entries);
+
+  for (auto iter = sorted_entries.begin(); iter != sorted_entries.end();
+   iter++) {
 // Sanitize.
-if (iter->first.IsNull() || iter->first.IsEmpty() || !iter->second)
+if (iter->first.empty() || !iter->second)
   continue;
 
 // Reset original indentation level.
@@ -238,7 +259,7 @@
 s.Indent();
 
 // Print key.
-s.Printf("%s:", iter->first.AsCString());
+s.Format("{0}:", iter->first);
 
 // Return to new line and increase indentation if value is record type.
 // Otherwise add spacing.
@@ -252,7 +273,7 @@
 
 // Print value and new line if now last pair.
 iter->second->GetDescription(s);
-if (std::next(iter) != m_dict.end())
+if (std::next(iter) != sorted_entries.end())
   s.EOL();
 
 // Reset indentation level if it was incremented previously.
Index: lldb/source/Target/Target.cpp
===
--- lldb/source/Target/Target.cpp
+++ lldb/source/Target/Target.cpp
@@ -3859,11 +3859,10 @@
   s.Indent("Args:\n");
   s.SetIndentLevel(s.GetIndentLevel() + 4);
 
-  auto print_one_element = [](ConstString key,
+  auto print_one_element = [](llvm::StringRef key,
 StructuredData::Object *object) {
 s.Indent();
-s.Printf("%s : %s\n", key.GetCString(),
-  object->GetStringValue().str().c_str());
+s.Format("{0} : {1}\n", key, object->GetStringValue());
 return true;
   };
 
Index: lldb/source/Plugins/SymbolVendor/MacOSX/SymbolVendorMacOSX.cpp
===
--- lldb/source/Plugins/SymbolVendor/MacOSX/SymbolVendorMacOSX.cpp
+++ lldb/source/Plugins/SymbolVendor/MacOSX/SymbolVendorMacOSX.cpp
@@ -224,7 +224,7 @@
   [_sp, new_style_source_remapping_dictionary,
original_DBGSourcePath_value,
do_truncate_remapping_names](
-  ConstString key,
+  llvm::StringRef key,
   StructuredData::Object *object) -> bool {
 if (object && object->GetAsString()) {
 
@@ -237,7 +237,7 @@
 DBGSourcePath = original_DBGSourcePath_value;
   }
   module_sp->GetSourceMappingList().Append(
-  key.GetStringRef(), DBGSourcePath, true);
+  key, DBGSourcePath, true);
   // With version 2 of DBGSourcePathRemapping, we
   // can chop off the last two filename parts
   // from the source remapping and get a more
@@ -245,7 +245,7 @@
   // Add this as another option in addition to
   // the full source path remap.
   if (do_truncate_remapping_names) {
-FileSpec build_path(key.AsCString());
+FileSpec build_path(key);
  

[Lldb-commits] [PATCH] D159313: [lldb][NFCI] Remove use of ConstString in StructuredData

[Alex Langford via Phabricator via lldb-commits]

bulbazord added inline comments.



Comment at: lldb/source/Utility/StructuredData.cpp:249-251
+  llvm::sort(sorted_entries, [&](const Entry , const Entry ) -> bool {
+return lhs.first < rhs.first;
+  });

Oh I can remove this lambda too -- Let me update.


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[Lldb-commits] [PATCH] D159011: [lldb][NFCI] Remove use of ConstString from UnixSignals

[Alex Langford via Phabricator via lldb-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2f377c5bd713: [lldb][NFCI] Remove use of ConstString from 
UnixSignals (authored by bulbazord).

Repository:
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Files:
  lldb/include/lldb/Target/UnixSignals.h
  lldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp
  lldb/source/Target/UnixSignals.cpp

Index: lldb/source/Target/UnixSignals.cpp
===
--- lldb/source/Target/UnixSignals.cpp
+++ lldb/source/Target/UnixSignals.cpp
@@ -18,17 +18,13 @@
 using namespace lldb_private;
 using namespace llvm;
 
-UnixSignals::Signal::Signal(const char *name, bool default_suppress,
+UnixSignals::Signal::Signal(llvm::StringRef name, bool default_suppress,
 bool default_stop, bool default_notify,
-const char *description, const char *alias)
-: m_name(name), m_alias(alias), m_description(),
+llvm::StringRef description, llvm::StringRef alias)
+: m_name(name), m_alias(alias), m_description(description),
   m_suppress(default_suppress), m_stop(default_stop),
-  m_notify(default_notify),
-  m_default_suppress(default_suppress), m_default_stop(default_stop),
-  m_default_notify(default_notify) {
-  if (description)
-m_description.assign(description);
-}
+  m_notify(default_notify), m_default_suppress(default_suppress),
+  m_default_stop(default_stop), m_default_notify(default_notify) {}
 
 lldb::UnixSignalsSP UnixSignals::Create(const ArchSpec ) {
   const auto  = arch.GetTriple();
@@ -104,9 +100,10 @@
   // clang-format on
 }
 
-void UnixSignals::AddSignal(int signo, const char *name, bool default_suppress,
-bool default_stop, bool default_notify,
-const char *description, const char *alias) {
+void UnixSignals::AddSignal(int signo, llvm::StringRef name,
+bool default_suppress, bool default_stop,
+bool default_notify, llvm::StringRef description,
+llvm::StringRef alias) {
   Signal new_signal(name, default_suppress, default_stop, default_notify,
 description, alias);
   m_signals.insert(std::make_pair(signo, new_signal));
@@ -135,7 +132,7 @@
   const auto pos = m_signals.find(signo);
   if (pos == m_signals.end())
 return {};
-  return pos->second.m_name.GetStringRef();
+  return pos->second.m_name;
 }
 
 std::string
@@ -147,7 +144,7 @@
 
   collection::const_iterator pos = m_signals.find(signo);
   if (pos != m_signals.end()) {
-str = pos->second.m_name.GetCString();
+str = pos->second.m_name.str();
 
 if (code) {
   std::map::const_iterator cpos =
@@ -199,14 +196,13 @@
 }
 
 int32_t UnixSignals::GetSignalNumberFromName(const char *name) const {
-  ConstString const_name(name);
+  llvm::StringRef name_ref(name);
 
   collection::const_iterator pos, end = m_signals.end();
   for (pos = m_signals.begin(); pos != end; pos++) {
-if ((const_name == pos->second.m_name) ||
-(const_name == pos->second.m_alias) ||
-(const_name == GetShortName(pos->second.m_name)) ||
-(const_name == GetShortName(pos->second.m_alias)))
+if ((name_ref == pos->second.m_name) || (name_ref == pos->second.m_alias) ||
+(name_ref == GetShortName(pos->second.m_name)) ||
+(name_ref == GetShortName(pos->second.m_alias)))
   return pos->first;
   }
 
@@ -373,11 +369,10 @@
 
 json::Value UnixSignals::GetHitCountStatistics() const {
   json::Array json_signals;
-  for (const auto : m_signals) {
+  for (const auto  : m_signals) {
 if (pair.second.m_hit_count > 0)
-  json_signals.emplace_back(json::Object{
-{ pair.second.m_name.GetCString(), pair.second.m_hit_count }
-  });
+  json_signals.emplace_back(
+  json::Object{{pair.second.m_name, pair.second.m_hit_count}});
   }
   return std::move(json_signals);
 }
Index: lldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp
===
--- lldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp
+++ lldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp
@@ -28,10 +28,12 @@
 #include "lldb/Utility/Status.h"
 #include "lldb/Utility/StreamString.h"
 #include "lldb/Utility/UriParser.h"
+#include "llvm/ADT/StringSet.h"
 #include "llvm/Support/FormatAdapters.h"
 
 #include "Plugins/Process/Utility/GDBRemoteSignals.h"
 #include "Plugins/Process/gdb-remote/ProcessGDBRemote.h"
+#include 
 #include 
 
 using namespace lldb;
@@ -41,6 +43,11 @@
 LLDB_PLUGIN_DEFINE_ADV(PlatformRemoteGDBServer, PlatformGDB)
 
 static bool g_initialized = false;
+// UnixSignals does not 

[Lldb-commits] [PATCH] D159011: [lldb][NFCI] Remove use of ConstString from UnixSignals

[Felipe de Azevedo Piovezan via Phabricator via lldb-commits]

fdeazeve accepted this revision.
fdeazeve added a comment.

LGTM!


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[Lldb-commits] [PATCH] D158514: [lldb][AArch64] Invalidate SVG prior to reconfiguring ZA regdef

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 556759.
DavidSpickett added a comment.

Rebase


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Files:
  lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
  
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py


Index: 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
===
--- 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
+++ 
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
@@ -125,11 +125,13 @@
 self.runCmd("thread select %d" % (idx + 1))
 self.check_za_register(4, 2)
 self.runCmd("register write vg 2")
+self.check_disabled_za_register(2)
 
 elif stopped_at_line_number == thY_break_line1:
 self.runCmd("thread select %d" % (idx + 1))
 self.check_za_register(2, 3)
 self.runCmd("register write vg 4")
+self.check_disabled_za_register(4)
 
 self.runCmd("thread continue 2")
 self.runCmd("thread continue 3")
Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
===
--- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
+++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
@@ -799,6 +799,11 @@
   if (!reg_info)
 return;
 
+  // When vg is written it is automatically made invalid. Writing vg will also
+  // change svg if we're in streaming mode, so we must fetch the latest value
+  // from the remote.
+  SetRegisterIsValid(reg_info, false);
+
   uint64_t fail_value = LLDB_INVALID_ADDRESS;
   uint32_t svg_reg_num = reg_info->kinds[eRegisterKindLLDB];
   uint64_t svg_reg_value = ReadRegisterAsUnsigned(svg_reg_num, fail_value);


Index: lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
===
--- lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
+++ lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/TestZAThreadedDynamic.py
@@ -125,11 +125,13 @@
 self.runCmd("thread select %d" % (idx + 1))
 self.check_za_register(4, 2)
 self.runCmd("register write vg 2")
+self.check_disabled_za_register(2)
 
 elif stopped_at_line_number == thY_break_line1:
 self.runCmd("thread select %d" % (idx + 1))
 self.check_za_register(2, 3)
 self.runCmd("register write vg 4")
+self.check_disabled_za_register(4)
 
 self.runCmd("thread continue 2")
 self.runCmd("thread continue 3")
Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
===
--- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
+++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
@@ -799,6 +799,11 @@
   if (!reg_info)
 return;
 
+  // When vg is written it is automatically made invalid. Writing vg will also
+  // change svg if we're in streaming mode, so we must fetch the latest value
+  // from the remote.
+  SetRegisterIsValid(reg_info, false);
+
   uint64_t fail_value = LLDB_INVALID_ADDRESS;
   uint32_t svg_reg_num = reg_info->kinds[eRegisterKindLLDB];
   uint64_t svg_reg_value = ReadRegisterAsUnsigned(svg_reg_num, fail_value);
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[Lldb-commits] [PATCH] D158506: [lldb][AArch64] Add release notes and documentation for SME

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 556758.
DavidSpickett added a comment.

Rebase


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Files:
  lldb/docs/index.rst
  lldb/docs/use/aarch64-linux.rst
  llvm/docs/ReleaseNotes.rst

Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -183,6 +183,10 @@
 * Methods in SBHostOS related to threads have had their implementations
   removed. These methods will return a value indicating failure.
 
+* LLDB now supports debugging the Scalable Matrix Extension (SME) on AArch64
+  Linux for both running processes and core files. For details refer to the
+  `AArch64 Linux documentation `_.
+
 Changes to Sanitizers
 -
 * HWASan now defaults to detecting use-after-scope bugs.
Index: lldb/docs/use/aarch64-linux.rst
===
--- /dev/null
+++ lldb/docs/use/aarch64-linux.rst
@@ -0,0 +1,190 @@
+Using LLDB On AArch64 Linux
+===
+
+This page explains the details of debugging certain AArch64 extensions using
+LLDB. If something is not mentioned here, it likely works as you would expect.
+
+This is not a replacement for ptrace and Linux Kernel documentation. This covers
+how LLDB has chosen to use those things and how that effects your experience as
+a user.
+
+Scalable Vector Extension (SVE)
+---
+
+See `here `__
+to learn about the extension and `here `__
+for the Linux Kernel's handling of it.
+
+In LLDB you will be able to see the following new registers:
+
+* ``z0-z31`` vector registers, each one has size equal to the vector length.
+* ``p0-p15`` predicate registers, each one containing 1 bit per byte in the vector
+  length. Making each one vector length / 8 sized.
+* ``ffr`` the first fault register, same size as a predicate register.
+* ``vg``, the vector length in "granules". Each granule is 8 bytes.
+
+.. code-block::
+
+   Scalable Vector Extension Registers:
+ vg = 0x0002
+ z0 = {0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 <...> }
+   <...>
+ p0 = {0xff 0xff}
+   <...>
+ffr = {0xff 0xff}
+
+The example above has a vector length of 16 bytes. Within LLDB you will always
+see "vg" as in the ``vg`` register, which is 2 in this case (8*2 = 16).
+Elsewhere you may see "vq" which is the vector length in quadwords (16 bytes)
+elsewhere. Where you see "vl", it is in bytes.
+
+Changing the Vector Length
+..
+
+While you can count the size of a P or Z register, it is intended that ``vg`` be
+used to find the current vector length.
+
+vg can be written. Writing the current vector length changes nothing. If you
+increase the vector length, the registers will likely be reset to 0. If you
+decrease it, LLDB will truncate the Z registers but everything else will be reset
+to 0.
+
+Generally you should not assume that SVE state after changing the vector length
+is in any way the same as it was previously. If you need to do it, do it before
+a function's first use of SVE.
+
+Z Register Presentation
+...
+
+LLDB makes no attempt to predict how an SVE Z register will be used. Even if the
+next SVE instruction (which may some distance away) would use, for example, 32
+bit elements, LLDB prints ``z0`` as single bytes.
+
+If you know what format you are going to use, give a format option::
+
+  (lldb) register read z0 -f uint32_t[]
+  z0 = {0x01010101 0x01010101 0x01010101 0x01010101}
+
+FPSIMD and SVE Modes
+
+
+Prior to the debugee's first use of SVE, it is in what the Linux Kernel terms
+SIMD mode. Only the FPU is being used. In this state LLDB will still show the
+SVE registers however the values are simply the FPU values zero extended up to
+the vector length.
+
+On first access to SVE, the process goes into SVE mode. Now the Z values are
+in the real Z registers.
+
+You can also trigger this with LLDB by writing to an SVE register. Note that
+there is no way to undo this change from within LLDB. However, the debugee
+itself could do something to end up back in SIMD mode.
+
+Expression evaluation
+.
+
+If you evaluate an expression, all SVE state is saved prior to, and restored
+after the expression has been evaluated. Including the register values and
+vector length.
+
+Scalable Matrix Extension (SME)
+---
+
+See `here `__
+to learn about the extension and 

[Lldb-commits] [PATCH] D158500: [lldb][AArch64] Linux corefile support for SME

[David Spickett via Phabricator via lldb-commits]

DavidSpickett updated this revision to Diff 556757.
DavidSpickett added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158500/new/

https://reviews.llvm.org/D158500

Files:
  lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
  lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h
  lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
  lldb/test/API/linux/aarch64/sme_core_file/TestAArch64LinuxSMECoreFile.py
  lldb/test/API/linux/aarch64/sme_core_file/core_0_16_32_1
  lldb/test/API/linux/aarch64/sme_core_file/core_0_32_16_0
  lldb/test/API/linux/aarch64/sme_core_file/core_1_16_32_0
  lldb/test/API/linux/aarch64/sme_core_file/core_1_32_16_1
  lldb/test/API/linux/aarch64/sme_core_file/main.c

Index: lldb/test/API/linux/aarch64/sme_core_file/main.c
===
--- /dev/null
+++ lldb/test/API/linux/aarch64/sme_core_file/main.c
@@ -0,0 +1,140 @@
+// clang-format off
+// Compile with:
+// clang -target aarch64-unknown-linux-gnu main.c -o a.out -g -march=armv8.6-a+sve+sme
+//
+// For minimal corefile size, do this before running the program:
+// echo 0x20 > /proc/self/coredeump_filter
+//
+// Must be run on a system that has SVE and SME, including the smefa64
+// extension. Example command:
+// main 0 32 64 1
+//
+// This would not enter streaming mode, set non-streaming VL to 32
+// bytes, streaming VL to 64 bytes and enable ZA.
+// clang-format on
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#endif
+
+#define SM_INST(c) asm volatile("msr s0_3_c4_c" #c "_3, xzr")
+#define SMSTART_SM SM_INST(3)
+#define SMSTART_ZA SM_INST(5)
+
+void set_sve_registers() {
+  // We assume the smefa64 feature is present, which allows ffr access
+  // in streaming mode.
+  asm volatile("setffr\n\t");
+  asm volatile("ptrue p0.b\n\t");
+  asm volatile("ptrue p1.h\n\t");
+  asm volatile("ptrue p2.s\n\t");
+  asm volatile("ptrue p3.d\n\t");
+  asm volatile("pfalse p4.b\n\t");
+  asm volatile("ptrue p5.b\n\t");
+  asm volatile("ptrue p6.h\n\t");
+  asm volatile("ptrue p7.s\n\t");
+  asm volatile("ptrue p8.d\n\t");
+  asm volatile("pfalse p9.b\n\t");
+  asm volatile("ptrue p10.b\n\t");
+  asm volatile("ptrue p11.h\n\t");
+  asm volatile("ptrue p12.s\n\t");
+  asm volatile("ptrue p13.d\n\t");
+  asm volatile("pfalse p14.b\n\t");
+  asm volatile("ptrue p15.b\n\t");
+
+  asm volatile("cpy  z0.b, p0/z, #1\n\t");
+  asm volatile("cpy  z1.b, p5/z, #2\n\t");
+  asm volatile("cpy  z2.b, p10/z, #3\n\t");
+  asm volatile("cpy  z3.b, p15/z, #4\n\t");
+  asm volatile("cpy  z4.b, p0/z, #5\n\t");
+  asm volatile("cpy  z5.b, p5/z, #6\n\t");
+  asm volatile("cpy  z6.b, p10/z, #7\n\t");
+  asm volatile("cpy  z7.b, p15/z, #8\n\t");
+  asm volatile("cpy  z8.b, p0/z, #9\n\t");
+  asm volatile("cpy  z9.b, p5/z, #10\n\t");
+  asm volatile("cpy  z10.b, p10/z, #11\n\t");
+  asm volatile("cpy  z11.b, p15/z, #12\n\t");
+  asm volatile("cpy  z12.b, p0/z, #13\n\t");
+  asm volatile("cpy  z13.b, p5/z, #14\n\t");
+  asm volatile("cpy  z14.b, p10/z, #15\n\t");
+  asm volatile("cpy  z15.b, p15/z, #16\n\t");
+  asm volatile("cpy  z16.b, p0/z, #17\n\t");
+  asm volatile("cpy  z17.b, p5/z, #18\n\t");
+  asm volatile("cpy  z18.b, p10/z, #19\n\t");
+  asm volatile("cpy  z19.b, p15/z, #20\n\t");
+  asm volatile("cpy  z20.b, p0/z, #21\n\t");
+  asm volatile("cpy  z21.b, p5/z, #22\n\t");
+  asm volatile("cpy  z22.b, p10/z, #23\n\t");
+  asm volatile("cpy  z23.b, p15/z, #24\n\t");
+  asm volatile("cpy  z24.b, p0/z, #25\n\t");
+  asm volatile("cpy  z25.b, p5/z, #26\n\t");
+  asm volatile("cpy  z26.b, p10/z, #27\n\t");
+  asm volatile("cpy  z27.b, p15/z, #28\n\t");
+  asm volatile("cpy  z28.b, p0/z, #29\n\t");
+  asm volatile("cpy  z29.b, p5/z, #30\n\t");
+  asm volatile("cpy  z30.b, p10/z, #31\n\t");
+  asm volatile("cpy  z31.b, p15/z, #32\n\t");
+}
+
+void set_za_register(int streaming_vl) {
+#define MAX_VL_BYTES 256
+  uint8_t data[MAX_VL_BYTES];
+
+  for (unsigned i = 0; i < streaming_vl; ++i) {
+for (unsigned j = 0; j < MAX_VL_BYTES; ++j)
+  data[j] = i + 1;
+asm volatile("mov w12, %w0\n\t"
+ "ldr za[w12, 0], [%1]\n\t" ::"r"(i),
+ "r"()
+ : "w12");
+  }
+}
+
+void set_tpidr2(uint64_t value) {
+  __asm__ volatile("msr S3_3_C13_C0_5, %0" ::"r"(value));
+}
+
+int main(int argc, char **argv) {
+  // Arguments:
+  //  SVE mode: 1 for streaming SVE (SSVE), any other value
+  //  for non-streaming SVE mode.
+  //   Non-Streaming Vector length: In bytes, an integer e.g. "32".
+  //   Streaming Vector length: As above, but for streaming mode.
+  //   ZA mode: 1 for enabled, any other value for disabled.
+  if (argc != 5)
+return 1;
+
+  // We assume this is run on a