[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
https://github.com/AtariDreams closed https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
https://github.com/AtariDreams updated
https://github.com/llvm/llvm-project/pull/91038
>From a62c1fce19ad9c1bf6899e9b528a07593909be8f Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Fri, 3 May 2024 09:59:33 -0700
Subject: [PATCH] [DAGCombiner] In mergeTruncStore, make sure we aren't storing
shifted in bits. (#90939)
When looking through a right shift, we need to make sure that all of
the bits we are using from the shift come from the shift input and
not the sign or zero bits that are shifted in.
Fixes #90936.
(cherry picked from commit 3563af6c06ebc92bcaacef0e33285148ef0f75bd)
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4
llvm/test/CodeGen/AArch64/pr90936.ll | 20 +++
2 files changed, 24 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/pr90936.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5038f8a1fc156..4951e45edb9ed 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8952,6 +8952,10 @@ SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) {
if (ShiftAmtC % NarrowNumBits != 0)
return SDValue();
+ // Make sure we aren't reading bits that are shifted in.
+ if (ShiftAmtC > WideVal.getScalarValueSizeInBits() - NarrowNumBits)
+return SDValue();
+
Offset = ShiftAmtC / NarrowNumBits;
WideVal = WideVal.getOperand(0);
}
diff --git a/llvm/test/CodeGen/AArch64/pr90936.ll
b/llvm/test/CodeGen/AArch64/pr90936.ll
new file mode 100644
index 0..38cda8d388945
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr90936.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+
+define void @f(i16 %arg, ptr %arg1) {
+; CHECK-LABEL: f:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ubfx w8, w0, #8, #6
+; CHECK-NEXT:strb w0, [x1]
+; CHECK-NEXT:strb w8, [x1, #1]
+; CHECK-NEXT:ret
+bb:
+ %i = trunc i16 %arg to i8
+ %i2 = trunc i16 %arg to i14
+ %i3 = lshr i14 %i2, 8
+ store i8 %i, ptr %arg1, align 1
+ %i4 = getelementptr i8, ptr %arg1, i64 1
+ %i5 = trunc i14 %i3 to i8
+ store i8 %i5, ptr %i4, align 1
+ ret void
+}
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
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[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
https://github.com/AtariDreams updated
https://github.com/llvm/llvm-project/pull/91038
>From 7f8d5e96e879f2e63a0c751547b4754f2634 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Fri, 3 May 2024 09:59:33 -0700
Subject: [PATCH 1/3] [DAGCombiner] In mergeTruncStore, make sure we aren't
storing shifted in bits. (#90939)
When looking through a right shift, we need to make sure that all of
the bits we are using from the shift come from the shift input and
not the sign or zero bits that are shifted in.
Fixes #90936.
(cherry picked from commit 3563af6c06ebc92bcaacef0e33285148ef0f75bd)
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4
llvm/test/CodeGen/AArch64/pr90936.ll | 20 +++
2 files changed, 24 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/pr90936.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5038f8a1fc156..4951e45edb9ed 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8952,6 +8952,10 @@ SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) {
if (ShiftAmtC % NarrowNumBits != 0)
return SDValue();
+ // Make sure we aren't reading bits that are shifted in.
+ if (ShiftAmtC > WideVal.getScalarValueSizeInBits() - NarrowNumBits)
+return SDValue();
+
Offset = ShiftAmtC / NarrowNumBits;
WideVal = WideVal.getOperand(0);
}
diff --git a/llvm/test/CodeGen/AArch64/pr90936.ll
b/llvm/test/CodeGen/AArch64/pr90936.ll
new file mode 100644
index 0..38cda8d388945
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr90936.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+
+define void @f(i16 %arg, ptr %arg1) {
+; CHECK-LABEL: f:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ubfx w8, w0, #8, #6
+; CHECK-NEXT:strb w0, [x1]
+; CHECK-NEXT:strb w8, [x1, #1]
+; CHECK-NEXT:ret
+bb:
+ %i = trunc i16 %arg to i8
+ %i2 = trunc i16 %arg to i14
+ %i3 = lshr i14 %i2, 8
+ store i8 %i, ptr %arg1, align 1
+ %i4 = getelementptr i8, ptr %arg1, i64 1
+ %i5 = trunc i14 %i3 to i8
+ store i8 %i5, ptr %i4, align 1
+ ret void
+}
>From c194040f2f57e1a2270ad3d77e50be010e76a54b Mon Sep 17 00:00:00 2001
From: AtariDreams
Date: Sat, 1 Jun 2024 21:54:37 -0400
Subject: [PATCH 2/3] Update DAGCombiner.cpp
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 4951e45edb9ed..c8f7a0bfbd4b3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8952,7 +8952,7 @@ SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) {
if (ShiftAmtC % NarrowNumBits != 0)
return SDValue();
- // Make sure we aren't reading bits that are shifted in.
+ // Make sure we aren't reading the bits that are shifted in.
if (ShiftAmtC > WideVal.getScalarValueSizeInBits() - NarrowNumBits)
return SDValue();
>From 371f035fb685dd9ccf9ad3f977e1e153a522ca69 Mon Sep 17 00:00:00 2001
From: AtariDreams
Date: Sat, 1 Jun 2024 21:55:02 -0400
Subject: [PATCH 3/3] Update DAGCombiner.cpp
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index c8f7a0bfbd4b3..4951e45edb9ed 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8952,7 +8952,7 @@ SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) {
if (ShiftAmtC % NarrowNumBits != 0)
return SDValue();
- // Make sure we aren't reading the bits that are shifted in.
+ // Make sure we aren't reading bits that are shifted in.
if (ShiftAmtC > WideVal.getScalarValueSizeInBits() - NarrowNumBits)
return SDValue();
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
https://github.com/AtariDreams updated
https://github.com/llvm/llvm-project/pull/91038
>From 094e4fbb65a5f24474cbe556f895ee784f6bdffb Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Fri, 3 May 2024 09:59:33 -0700
Subject: [PATCH 1/3] [DAGCombiner] In mergeTruncStore, make sure we aren't
storing shifted in bits. (#90939)
When looking through a right shift, we need to make sure that all of
the bits we are using from the shift come from the shift input and
not the sign or zero bits that are shifted in.
Fixes #90936.
(cherry picked from commit 3563af6c06ebc92bcaacef0e33285148ef0f75bd)
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4
llvm/test/CodeGen/AArch64/pr90936.ll | 20 +++
2 files changed, 24 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/pr90936.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5038f8a1fc156..4951e45edb9ed 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8952,6 +8952,10 @@ SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) {
if (ShiftAmtC % NarrowNumBits != 0)
return SDValue();
+ // Make sure we aren't reading bits that are shifted in.
+ if (ShiftAmtC > WideVal.getScalarValueSizeInBits() - NarrowNumBits)
+return SDValue();
+
Offset = ShiftAmtC / NarrowNumBits;
WideVal = WideVal.getOperand(0);
}
diff --git a/llvm/test/CodeGen/AArch64/pr90936.ll
b/llvm/test/CodeGen/AArch64/pr90936.ll
new file mode 100644
index 0..38cda8d388945
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr90936.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+
+define void @f(i16 %arg, ptr %arg1) {
+; CHECK-LABEL: f:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ubfx w8, w0, #8, #6
+; CHECK-NEXT:strb w0, [x1]
+; CHECK-NEXT:strb w8, [x1, #1]
+; CHECK-NEXT:ret
+bb:
+ %i = trunc i16 %arg to i8
+ %i2 = trunc i16 %arg to i14
+ %i3 = lshr i14 %i2, 8
+ store i8 %i, ptr %arg1, align 1
+ %i4 = getelementptr i8, ptr %arg1, i64 1
+ %i5 = trunc i14 %i3 to i8
+ store i8 %i5, ptr %i4, align 1
+ ret void
+}
>From fa3758ab061aaf545bfbbd611992c9cd23a80390 Mon Sep 17 00:00:00 2001
From: AtariDreams
Date: Sat, 1 Jun 2024 21:54:37 -0400
Subject: [PATCH 2/3] Update DAGCombiner.cpp
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 4951e45edb9ed..c8f7a0bfbd4b3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8952,7 +8952,7 @@ SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) {
if (ShiftAmtC % NarrowNumBits != 0)
return SDValue();
- // Make sure we aren't reading bits that are shifted in.
+ // Make sure we aren't reading the bits that are shifted in.
if (ShiftAmtC > WideVal.getScalarValueSizeInBits() - NarrowNumBits)
return SDValue();
>From 2eb8863a43c88b63433f91580a83862e60702c99 Mon Sep 17 00:00:00 2001
From: AtariDreams
Date: Sat, 1 Jun 2024 21:55:02 -0400
Subject: [PATCH 3/3] Update DAGCombiner.cpp
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index c8f7a0bfbd4b3..4951e45edb9ed 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8952,7 +8952,7 @@ SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) {
if (ShiftAmtC % NarrowNumBits != 0)
return SDValue();
- // Make sure we aren't reading the bits that are shifted in.
+ // Make sure we aren't reading bits that are shifted in.
if (ShiftAmtC > WideVal.getScalarValueSizeInBits() - NarrowNumBits)
return SDValue();
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
https://github.com/AtariDreams updated
https://github.com/llvm/llvm-project/pull/91038
>From 094e4fbb65a5f24474cbe556f895ee784f6bdffb Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Fri, 3 May 2024 09:59:33 -0700
Subject: [PATCH 1/2] [DAGCombiner] In mergeTruncStore, make sure we aren't
storing shifted in bits. (#90939)
When looking through a right shift, we need to make sure that all of
the bits we are using from the shift come from the shift input and
not the sign or zero bits that are shifted in.
Fixes #90936.
(cherry picked from commit 3563af6c06ebc92bcaacef0e33285148ef0f75bd)
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4
llvm/test/CodeGen/AArch64/pr90936.ll | 20 +++
2 files changed, 24 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/pr90936.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5038f8a1fc156..4951e45edb9ed 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8952,6 +8952,10 @@ SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) {
if (ShiftAmtC % NarrowNumBits != 0)
return SDValue();
+ // Make sure we aren't reading bits that are shifted in.
+ if (ShiftAmtC > WideVal.getScalarValueSizeInBits() - NarrowNumBits)
+return SDValue();
+
Offset = ShiftAmtC / NarrowNumBits;
WideVal = WideVal.getOperand(0);
}
diff --git a/llvm/test/CodeGen/AArch64/pr90936.ll
b/llvm/test/CodeGen/AArch64/pr90936.ll
new file mode 100644
index 0..38cda8d388945
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr90936.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+
+define void @f(i16 %arg, ptr %arg1) {
+; CHECK-LABEL: f:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ubfx w8, w0, #8, #6
+; CHECK-NEXT:strb w0, [x1]
+; CHECK-NEXT:strb w8, [x1, #1]
+; CHECK-NEXT:ret
+bb:
+ %i = trunc i16 %arg to i8
+ %i2 = trunc i16 %arg to i14
+ %i3 = lshr i14 %i2, 8
+ store i8 %i, ptr %arg1, align 1
+ %i4 = getelementptr i8, ptr %arg1, i64 1
+ %i5 = trunc i14 %i3 to i8
+ store i8 %i5, ptr %i4, align 1
+ ret void
+}
>From fa3758ab061aaf545bfbbd611992c9cd23a80390 Mon Sep 17 00:00:00 2001
From: AtariDreams
Date: Sat, 1 Jun 2024 21:54:37 -0400
Subject: [PATCH 2/2] Update DAGCombiner.cpp
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 4951e45edb9ed..c8f7a0bfbd4b3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8952,7 +8952,7 @@ SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) {
if (ShiftAmtC % NarrowNumBits != 0)
return SDValue();
- // Make sure we aren't reading bits that are shifted in.
+ // Make sure we aren't reading the bits that are shifted in.
if (ShiftAmtC > WideVal.getScalarValueSizeInBits() - NarrowNumBits)
return SDValue();
___
llvm-branch-commits mailing list
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[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
https://github.com/AtariDreams reopened https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
https://github.com/AtariDreams closed https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
https://github.com/AtariDreams reopened https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
RKSimon wrote: > > @AtariDreams I've noticed you've filed a lot of backport requests. How are > > you choosing which fixes to backport? Is there a specific use case you care > > about? > > There a particular LLVM miscompile bug in WebKit I'm trying to figure out. > It's been there since 2019. Backports is literally just avoiding > miscompilations @AtariDreams Has the bug disappeared in llvm trunk and you think a recent commit has fixed/hidden it? Has this bug been reported either to WebKit or LLVM that we can track please? Have you been able to confirm if its a llvm bug or UB in WebKit? https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
https://github.com/AtariDreams closed https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
https://github.com/AtariDreams updated
https://github.com/llvm/llvm-project/pull/91038
>From 094e4fbb65a5f24474cbe556f895ee784f6bdffb Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Fri, 3 May 2024 09:59:33 -0700
Subject: [PATCH] [DAGCombiner] In mergeTruncStore, make sure we aren't storing
shifted in bits. (#90939)
When looking through a right shift, we need to make sure that all of
the bits we are using from the shift come from the shift input and
not the sign or zero bits that are shifted in.
Fixes #90936.
(cherry picked from commit 3563af6c06ebc92bcaacef0e33285148ef0f75bd)
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4
llvm/test/CodeGen/AArch64/pr90936.ll | 20 +++
2 files changed, 24 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/pr90936.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5038f8a1fc156..4951e45edb9ed 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8952,6 +8952,10 @@ SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) {
if (ShiftAmtC % NarrowNumBits != 0)
return SDValue();
+ // Make sure we aren't reading bits that are shifted in.
+ if (ShiftAmtC > WideVal.getScalarValueSizeInBits() - NarrowNumBits)
+return SDValue();
+
Offset = ShiftAmtC / NarrowNumBits;
WideVal = WideVal.getOperand(0);
}
diff --git a/llvm/test/CodeGen/AArch64/pr90936.ll
b/llvm/test/CodeGen/AArch64/pr90936.ll
new file mode 100644
index 0..38cda8d388945
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr90936.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+
+define void @f(i16 %arg, ptr %arg1) {
+; CHECK-LABEL: f:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ubfx w8, w0, #8, #6
+; CHECK-NEXT:strb w0, [x1]
+; CHECK-NEXT:strb w8, [x1, #1]
+; CHECK-NEXT:ret
+bb:
+ %i = trunc i16 %arg to i8
+ %i2 = trunc i16 %arg to i14
+ %i3 = lshr i14 %i2, 8
+ store i8 %i, ptr %arg1, align 1
+ %i4 = getelementptr i8, ptr %arg1, i64 1
+ %i5 = trunc i14 %i3 to i8
+ store i8 %i5, ptr %i4, align 1
+ ret void
+}
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
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[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
nikic wrote: @tstellar AtariDreams is requesting backports for random commits that somehow mention miscompilations or crashes, without having any understanding of what the changes are about or how they relate to other changes. They have submitted a large amount of invalid or nonsensical backports for that reason, despite many requests to stop doing so. When there is any doubt, you should not merge backport PRs created by this user. That said, this specific one does look harmless to me. https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
AtariDreams wrote: > @AtariDreams I've noticed you've filed a lot of backport requests. How are > you choosing which fixes to backport? Is there a specific use case you care > about? There a particular LLVM miscompile bug in WebKit I'm trying to figure out. It's been there since 2019. Backports is literally just avoiding miscompilations https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
tstellar wrote: @AtariDreams I've noticed you've filed a lot of backport requests. How are you choosing which fixes to backport? Is there a specific use case you care about? https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
topperc wrote: > @topperc Do you have any strong objections to backporting this? This looks > small to me and I think it's OK to fix long-standing bugs. No objection. https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
tstellar wrote: @topperc Do you have any strong objections to backporting this? This looks small to me and I think it's OK to fix long-standing bugs. https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
AtariDreams wrote: We do not need to know how to fold every single possible permutation that comes our way, especially if they are so rare that writing compile code optimizing it isn't even worth it. We do, however, need to strive to avoid miscompiles wherever we can, no matter how esoteric the code is. Now, this isn't always possible, but in this case, the alternative codepath given just bails the transform, which is preferable to folding something that should not be. https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
AtariDreams wrote: > @AtariDreams This bug has existed since at least LLVM 10. What makes it a > candidate for backporting? At best, if the code triggers, we abort the fold, so there is no risk of anything crazy going on if this is added. https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: AtariDreams (AtariDreams)
Changes
When looking through a right shift, we need to make sure that all of the bits
we are using from the shift come from the shift input and not the sign or zero
bits that are shifted in.
Fixes #90936.
(cherry picked from commit 3563af6c06ebc92bcaacef0e33285148ef0f75bd)
---
Full diff: https://github.com/llvm/llvm-project/pull/91038.diff
2 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+4)
- (added) llvm/test/CodeGen/AArch64/pr90936.ll (+20)
``diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5038f8a1fc156..4951e45edb9ed 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8952,6 +8952,10 @@ SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) {
if (ShiftAmtC % NarrowNumBits != 0)
return SDValue();
+ // Make sure we aren't reading bits that are shifted in.
+ if (ShiftAmtC > WideVal.getScalarValueSizeInBits() - NarrowNumBits)
+return SDValue();
+
Offset = ShiftAmtC / NarrowNumBits;
WideVal = WideVal.getOperand(0);
}
diff --git a/llvm/test/CodeGen/AArch64/pr90936.ll
b/llvm/test/CodeGen/AArch64/pr90936.ll
new file mode 100644
index 0..38cda8d388945
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr90936.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+
+define void @f(i16 %arg, ptr %arg1) {
+; CHECK-LABEL: f:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ubfx w8, w0, #8, #6
+; CHECK-NEXT:strb w0, [x1]
+; CHECK-NEXT:strb w8, [x1, #1]
+; CHECK-NEXT:ret
+bb:
+ %i = trunc i16 %arg to i8
+ %i2 = trunc i16 %arg to i14
+ %i3 = lshr i14 %i2, 8
+ store i8 %i, ptr %arg1, align 1
+ %i4 = getelementptr i8, ptr %arg1, i64 1
+ %i5 = trunc i14 %i3 to i8
+ store i8 %i5, ptr %i4, align 1
+ ret void
+}
``
https://github.com/llvm/llvm-project/pull/91038
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[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
https://github.com/AtariDreams updated
https://github.com/llvm/llvm-project/pull/91038
>From 4f8b0b5ef6a16648aa42a10bbf8c0e18ddd1a577 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Fri, 3 May 2024 09:59:33 -0700
Subject: [PATCH] [DAGCombiner] In mergeTruncStore, make sure we aren't storing
shifted in bits. (#90939)
When looking through a right shift, we need to make sure that all of
the bits we are using from the shift come from the shift input and
not the sign or zero bits that are shifted in.
Fixes #90936.
(cherry picked from commit 3563af6c06ebc92bcaacef0e33285148ef0f75bd)
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4
llvm/test/CodeGen/AArch64/pr90936.ll | 20 +++
2 files changed, 24 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/pr90936.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5038f8a1fc156..4951e45edb9ed 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8952,6 +8952,10 @@ SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) {
if (ShiftAmtC % NarrowNumBits != 0)
return SDValue();
+ // Make sure we aren't reading bits that are shifted in.
+ if (ShiftAmtC > WideVal.getScalarValueSizeInBits() - NarrowNumBits)
+return SDValue();
+
Offset = ShiftAmtC / NarrowNumBits;
WideVal = WideVal.getOperand(0);
}
diff --git a/llvm/test/CodeGen/AArch64/pr90936.ll
b/llvm/test/CodeGen/AArch64/pr90936.ll
new file mode 100644
index 0..38cda8d388945
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr90936.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+
+define void @f(i16 %arg, ptr %arg1) {
+; CHECK-LABEL: f:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ubfx w8, w0, #8, #6
+; CHECK-NEXT:strb w0, [x1]
+; CHECK-NEXT:strb w8, [x1, #1]
+; CHECK-NEXT:ret
+bb:
+ %i = trunc i16 %arg to i8
+ %i2 = trunc i16 %arg to i14
+ %i3 = lshr i14 %i2, 8
+ store i8 %i, ptr %arg1, align 1
+ %i4 = getelementptr i8, ptr %arg1, i64 1
+ %i5 = trunc i14 %i3 to i8
+ store i8 %i5, ptr %i4, align 1
+ ret void
+}
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[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
topperc wrote: @AtariDreams This bug has existed since at least LLVM 10. What makes it a candidate for backporting? https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
https://github.com/nikic milestoned https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
https://github.com/AtariDreams created
https://github.com/llvm/llvm-project/pull/91038
When looking through a right shift, we need to make sure that all of the bits
we are using from the shift come from the shift input and not the sign or zero
bits that are shifted in.
Fixes #90936.
(cherry picked from commit 3563af6c06ebc92bcaacef0e33285148ef0f75bd)
>From 9212565cd56b6524f05a05bcafb43b458cb82900 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Fri, 3 May 2024 09:59:33 -0700
Subject: [PATCH] [DAGCombiner] In mergeTruncStore, make sure we aren't storing
shifted in bits. (#90939)
When looking through a right shift, we need to make sure that all of
the bits we are using from the shift come from the shift input and
not the sign or zero bits that are shifted in.
Fixes #90936.
(cherry picked from commit 3563af6c06ebc92bcaacef0e33285148ef0f75bd)
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4
llvm/test/CodeGen/AArch64/pr90936.ll | 20 +++
2 files changed, 24 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/pr90936.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5038f8a1fc1562..4951e45edb9ed7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8952,6 +8952,10 @@ SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) {
if (ShiftAmtC % NarrowNumBits != 0)
return SDValue();
+ // Make sure we aren't reading bits that are shifted in.
+ if (ShiftAmtC > WideVal.getScalarValueSizeInBits() - NarrowNumBits)
+return SDValue();
+
Offset = ShiftAmtC / NarrowNumBits;
WideVal = WideVal.getOperand(0);
}
diff --git a/llvm/test/CodeGen/AArch64/pr90936.ll
b/llvm/test/CodeGen/AArch64/pr90936.ll
new file mode 100644
index 00..38cda8d388945f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr90936.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+
+define void @f(i16 %arg, ptr %arg1) {
+; CHECK-LABEL: f:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ubfx w8, w0, #8, #6
+; CHECK-NEXT:strb w0, [x1]
+; CHECK-NEXT:strb w8, [x1, #1]
+; CHECK-NEXT:ret
+bb:
+ %i = trunc i16 %arg to i8
+ %i2 = trunc i16 %arg to i14
+ %i3 = lshr i14 %i2, 8
+ store i8 %i, ptr %arg1, align 1
+ %i4 = getelementptr i8, ptr %arg1, i64 1
+ %i5 = trunc i14 %i3 to i8
+ store i8 %i5, ptr %i4, align 1
+ ret void
+}
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