[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.84 - 1.85
---
Log message:
Add virtual method spillCalleeSaveRegisters() and restoreCalleeSaveRegisters()
to MRegisterInfo. These allow the target to issue instructions to spill and
restore callee saved registers in case where individual stores / loads aren't
the correct / profitable choice.
---
Diffs of the changes: (+21 -0)
MRegisterInfo.h | 21 +
1 files changed, 21 insertions(+)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.84
llvm/include/llvm/Target/MRegisterInfo.h:1.85
--- llvm/include/llvm/Target/MRegisterInfo.h:1.84 Wed Sep 27 19:07:19 2006
+++ llvm/include/llvm/Target/MRegisterInfo.hTue Jan 2 14:55:17 2007
@@ -29,6 +29,7 @@
class MachineLocation;
class MachineMove;
class TargetRegisterClass;
+class CalleeSavedInfo;
/// TargetRegisterDesc - This record contains all of the information known
about
/// a particular register. The AliasSet field (if not null) contains a pointer
@@ -319,6 +320,26 @@
// immediates and memory. FIXME: Move these to TargetInstrInfo.h.
//
+ /// spillCalleeSaveRegisters - Issues instruction(s) to spill all callee
saved
+ /// registers and returns true if it isn't possible / profitable to do so by
+ /// issuing a series of store instructions via storeRegToStackSlot(). Returns
+ /// false otherwise.
+ virtual bool spillCalleeSaveRegisters(MachineBasicBlock MBB,
+MachineBasicBlock::iterator MI,
+const std::vectorCalleeSavedInfo CSI) const
{
+return false;
+ }
+
+ /// restoreCalleeSaveRegisters - Issues instruction(s) to restore all callee
+ /// saved registers and returns true if it isn't possible / profitable to do
+ /// so by issuing a series of load instructions via loadRegToStackSlot().
+ /// Returns false otherwise.
+ virtual bool restoreCalleeSaveRegisters(MachineBasicBlock MBB,
+ MachineBasicBlock::iterator MI,
+const std::vectorCalleeSavedInfo CSI) const
{
+return false;
+ }
+
virtual void storeRegToStackSlot(MachineBasicBlock MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIndex,
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[llvm-commits] CVS: llvm/lib/CodeGen/PrologEpilogInserter.cpp
Changes in directory llvm/lib/CodeGen:
PrologEpilogInserter.cpp updated: 1.62 - 1.63
---
Log message:
- Fixing naming inconsistency: calleesave - calleesaved.
- Make use of spillCalleeSavedRegisters() and restoreCalleeSavedRegisters().
---
Diffs of the changes: (+30 -24)
PrologEpilogInserter.cpp | 54 ++-
1 files changed, 30 insertions(+), 24 deletions(-)
Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp
diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.62
llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.63
--- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.62 Wed Dec 6 20:25:34 2006
+++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Tue Jan 2 15:31:15 2007
@@ -46,7 +46,8 @@
// Allow the target machine to make some adjustments to the function
// e.g. UsedPhysRegs before calculateCalleeSavedRegisters.
-
Fn.getTarget().getRegisterInfo()-processFunctionBeforeCalleeSaveScan(Fn);
+ Fn.getTarget().getRegisterInfo()
+-processFunctionBeforeCalleeSavedScan(Fn);
// Scan the function for modified callee saved registers and insert spill
// code for any callee saved registers that are modified. Also calculate
@@ -80,7 +81,7 @@
}
private:
-// MinCSFrameIndex, MaxCSFrameIndex - Keeps the range of callee save
+// MinCSFrameIndex, MaxCSFrameIndex - Keeps the range of callee saved
// stack frame indexes.
unsigned MinCSFrameIndex, MaxCSFrameIndex;
@@ -109,7 +110,7 @@
const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo();
// Get the callee saved register list...
- const unsigned *CSRegs = RegInfo-getCalleeSaveRegs();
+ const unsigned *CSRegs = RegInfo-getCalleeSavedRegs();
// Get the function call frame set-up and tear-down instruction opcode
int FrameSetupOpcode = RegInfo-getCallFrameSetupOpcode();
@@ -151,7 +152,7 @@
//
const bool *PhysRegsUsed = Fn.getUsedPhysregs();
const TargetRegisterClass* const *CSRegClasses =
-RegInfo-getCalleeSaveRegClasses();
+RegInfo-getCalleeSavedRegClasses();
std::vectorCalleeSavedInfo CSI;
for (unsigned i = 0; CSRegs[i]; ++i) {
unsigned Reg = CSRegs[i];
@@ -174,7 +175,7 @@
unsigned NumFixedSpillSlots;
const std::pairunsigned,int *FixedSpillSlots =
-TFI-getCalleeSaveSpillSlots(NumFixedSpillSlots);
+TFI-getCalleeSavedSpillSlots(NumFixedSpillSlots);
// Now that we know which registers need to be saved and restored, allocate
// stack slots for them.
@@ -228,10 +229,13 @@
// code into the entry block.
MachineBasicBlock *MBB = Fn.begin();
MachineBasicBlock::iterator I = MBB-begin();
- for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
-// Insert the spill to the stack frame.
-RegInfo-storeRegToStackSlot(*MBB, I, CSI[i].getReg(),
CSI[i].getFrameIdx(),
- CSI[i].getRegClass());
+ if (!RegInfo-spillCalleeSavedRegisters(*MBB, I, CSI)) {
+for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
+ // Insert the spill to the stack frame.
+ RegInfo-storeRegToStackSlot(*MBB, I, CSI[i].getReg(),
+ CSI[i].getFrameIdx(),
+ CSI[i].getRegClass());
+}
}
// Add code to restore the callee-save registers in each exiting block.
@@ -255,19 +259,21 @@
// Restore all registers immediately before the return and any
terminators
// that preceed it.
- for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
-RegInfo-loadRegFromStackSlot(*MBB, I, CSI[i].getReg(),
- CSI[i].getFrameIdx(),
- CSI[i].getRegClass());
-assert(I != MBB-begin()
- loadRegFromStackSlot didn't insert any code!);
-// Insert in reverse order. loadRegFromStackSlot can insert multiple
-// instructions.
-if (AtStart)
- I = MBB-begin();
-else {
- I = BeforeI;
- ++I;
+ if (!RegInfo-restoreCalleeSavedRegisters(*MBB, I, CSI)) {
+for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
+ RegInfo-loadRegFromStackSlot(*MBB, I, CSI[i].getReg(),
+CSI[i].getFrameIdx(),
+CSI[i].getRegClass());
+ assert(I != MBB-begin()
+ loadRegFromStackSlot didn't insert any code!);
+ // Insert in reverse order. loadRegFromStackSlot can insert multiple
+ // instructions.
+ if (AtStart)
+I = MBB-begin();
+ else {
+I = BeforeI;
+++I;
+ }
}
}
}
@@ -319,7 +325,7 @@
}
// First assign frame offsets to stack objects that are used to spill
- // callee save registers.
+ // callee saved registers.
if (StackGrowsDown) {
for (unsigned i = 0, e = FFI-getObjectIndexEnd(); i != e; ++i) {
if (i MinCSFrameIndex || i
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp AlphaRegisterInfo.h
Changes in directory llvm/lib/Target/Alpha:
AlphaRegisterInfo.cpp updated: 1.54 - 1.55
AlphaRegisterInfo.h updated: 1.15 - 1.16
---
Log message:
Fix naming inconsistency.
---
Diffs of the changes: (+8 -8)
AlphaRegisterInfo.cpp | 12 ++--
AlphaRegisterInfo.h |4 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.54
llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.55
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.54Thu Dec 7 16:21:48 2006
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Tue Jan 2 15:32:26 2007
@@ -151,8 +151,8 @@
}
}
-const unsigned* AlphaRegisterInfo::getCalleeSaveRegs() const {
- static const unsigned CalleeSaveRegs[] = {
+const unsigned* AlphaRegisterInfo::getCalleeSavedRegs() const {
+ static const unsigned CalleeSavedRegs[] = {
Alpha::R9, Alpha::R10,
Alpha::R11, Alpha::R12,
Alpha::R13, Alpha::R14,
@@ -161,12 +161,12 @@
Alpha::F6, Alpha::F7,
Alpha::F8, Alpha::F9, 0
};
- return CalleeSaveRegs;
+ return CalleeSavedRegs;
}
const TargetRegisterClass* const*
-AlphaRegisterInfo::getCalleeSaveRegClasses() const {
- static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
+AlphaRegisterInfo::getCalleeSavedRegClasses() const {
+ static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
Alpha::GPRCRegClass, Alpha::GPRCRegClass,
Alpha::GPRCRegClass, Alpha::GPRCRegClass,
Alpha::GPRCRegClass, Alpha::GPRCRegClass,
@@ -175,7 +175,7 @@
Alpha::F8RCRegClass, Alpha::F8RCRegClass,
Alpha::F8RCRegClass, Alpha::F8RCRegClass, 0
};
- return CalleeSaveRegClasses;
+ return CalleeSavedRegClasses;
}
//===--===//
Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.h
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.15
llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.16
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.15 Mon Nov 27 17:37:22 2006
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.h Tue Jan 2 15:32:26 2007
@@ -45,9 +45,9 @@
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
- const unsigned *getCalleeSaveRegs() const;
+ const unsigned *getCalleeSavedRegs() const;
- const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
+ const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction MF,
MachineBasicBlock MBB,
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.94 - 1.95
PPCRegisterInfo.h updated: 1.20 - 1.21
---
Log message:
Fix naming inconsistency.
---
Diffs of the changes: (+12 -12)
PPCRegisterInfo.cpp | 20 ++--
PPCRegisterInfo.h |4 ++--
2 files changed, 12 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.94
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.95
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.94Thu Dec 7 16:21:48 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Jan 2 15:33:01 2007
@@ -238,9 +238,9 @@
}
}
-const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
+const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const {
// 32-bit Darwin calling convention.
- static const unsigned Darwin32_CalleeSaveRegs[] = {
+ static const unsigned Darwin32_CalleeSavedRegs[] = {
PPC::R13, PPC::R14, PPC::R15,
PPC::R16, PPC::R17, PPC::R18, PPC::R19,
PPC::R20, PPC::R21, PPC::R22, PPC::R23,
@@ -261,7 +261,7 @@
PPC::LR, 0
};
// 64-bit Darwin calling convention.
- static const unsigned Darwin64_CalleeSaveRegs[] = {
+ static const unsigned Darwin64_CalleeSavedRegs[] = {
PPC::X14, PPC::X15,
PPC::X16, PPC::X17, PPC::X18, PPC::X19,
PPC::X20, PPC::X21, PPC::X22, PPC::X23,
@@ -282,14 +282,14 @@
PPC::LR8, 0
};
- return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegs :
- Darwin32_CalleeSaveRegs;
+ return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
+ Darwin32_CalleeSavedRegs;
}
const TargetRegisterClass* const*
-PPCRegisterInfo::getCalleeSaveRegClasses() const {
+PPCRegisterInfo::getCalleeSavedRegClasses() const {
// 32-bit Darwin calling convention.
- static const TargetRegisterClass * const Darwin32_CalleeSaveRegClasses[] = {
+ static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = {
PPC::GPRCRegClass,PPC::GPRCRegClass,PPC::GPRCRegClass,
PPC::GPRCRegClass,PPC::GPRCRegClass,PPC::GPRCRegClass,PPC::GPRCRegClass,
PPC::GPRCRegClass,PPC::GPRCRegClass,PPC::GPRCRegClass,PPC::GPRCRegClass,
@@ -312,7 +312,7 @@
};
// 64-bit Darwin calling convention.
- static const TargetRegisterClass * const Darwin64_CalleeSaveRegClasses[] = {
+ static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = {
PPC::G8RCRegClass,PPC::G8RCRegClass,
PPC::G8RCRegClass,PPC::G8RCRegClass,PPC::G8RCRegClass,PPC::G8RCRegClass,
PPC::G8RCRegClass,PPC::G8RCRegClass,PPC::G8RCRegClass,PPC::G8RCRegClass,
@@ -334,8 +334,8 @@
PPC::G8RCRegClass, 0
};
- return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegClasses :
- Darwin32_CalleeSaveRegClasses;
+ return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses :
+ Darwin32_CalleeSavedRegClasses;
}
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.20
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.21
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.20 Wed Dec 6 11:42:06 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Tue Jan 2 15:33:01 2007
@@ -54,9 +54,9 @@
virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
int FrameIndex) const;
- const unsigned *getCalleeSaveRegs() const;
+ const unsigned *getCalleeSavedRegs() const;
- const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
+ const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction MF,
MachineBasicBlock MBB,
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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp SparcRegisterInfo.h
Changes in directory llvm/lib/Target/Sparc:
SparcRegisterInfo.cpp updated: 1.49 - 1.50
SparcRegisterInfo.h updated: 1.15 - 1.16
---
Log message:
Fix naming inconsistency.
---
Diffs of the changes: (+8 -8)
SparcRegisterInfo.cpp | 12 ++--
SparcRegisterInfo.h |4 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.49
llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.50
--- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.49Thu Dec 7 16:21:48 2006
+++ llvm/lib/Target/Sparc/SparcRegisterInfo.cpp Tue Jan 2 15:33:17 2007
@@ -111,15 +111,15 @@
return NewMI;
}
-const unsigned* SparcRegisterInfo::getCalleeSaveRegs() const {
- static const unsigned CalleeSaveRegs[] = { 0 };
- return CalleeSaveRegs;
+const unsigned* SparcRegisterInfo::getCalleeSavedRegs() const {
+ static const unsigned CalleeSavedRegs[] = { 0 };
+ return CalleeSavedRegs;
}
const TargetRegisterClass* const*
-SparcRegisterInfo::getCalleeSaveRegClasses() const {
- static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 };
- return CalleeSaveRegClasses;
+SparcRegisterInfo::getCalleeSavedRegClasses() const {
+ static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
+ return CalleeSavedRegClasses;
}
Index: llvm/lib/Target/Sparc/SparcRegisterInfo.h
diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.15
llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.16
--- llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.15 Mon Nov 27 17:37:22 2006
+++ llvm/lib/Target/Sparc/SparcRegisterInfo.h Tue Jan 2 15:33:17 2007
@@ -48,9 +48,9 @@
unsigned OpNum,
int FrameIndex) const;
- const unsigned *getCalleeSaveRegs() const;
+ const unsigned *getCalleeSavedRegs() const;
- const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
+ const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction MF,
MachineBasicBlock MBB,
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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86RegisterInfo.h
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.186 - 1.187
X86RegisterInfo.h updated: 1.42 - 1.43
---
Log message:
Fix naming inconsistency.
---
Diffs of the changes: (+13 -13)
X86RegisterInfo.cpp | 16
X86RegisterInfo.h | 10 +-
2 files changed, 13 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.186
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.187
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.186 Thu Dec 14 15:55:39 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Jan 2 15:33:40 2007
@@ -853,30 +853,30 @@
}
-const unsigned *X86RegisterInfo::getCalleeSaveRegs() const {
- static const unsigned CalleeSaveRegs32Bit[] = {
+const unsigned *X86RegisterInfo::getCalleeSavedRegs() const {
+ static const unsigned CalleeSavedRegs32Bit[] = {
X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
};
- static const unsigned CalleeSaveRegs64Bit[] = {
+ static const unsigned CalleeSavedRegs64Bit[] = {
X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
};
- return Is64Bit ? CalleeSaveRegs64Bit : CalleeSaveRegs32Bit;
+ return Is64Bit ? CalleeSavedRegs64Bit : CalleeSavedRegs32Bit;
}
const TargetRegisterClass* const*
-X86RegisterInfo::getCalleeSaveRegClasses() const {
- static const TargetRegisterClass * const CalleeSaveRegClasses32Bit[] = {
+X86RegisterInfo::getCalleeSavedRegClasses() const {
+ static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
X86::GR32RegClass, X86::GR32RegClass,
X86::GR32RegClass, X86::GR32RegClass, 0
};
- static const TargetRegisterClass * const CalleeSaveRegClasses64Bit[] = {
+ static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
X86::GR64RegClass, X86::GR64RegClass,
X86::GR64RegClass, X86::GR64RegClass,
X86::GR64RegClass, X86::GR64RegClass, 0
};
- return Is64Bit ? CalleeSaveRegClasses64Bit : CalleeSaveRegClasses32Bit;
+ return Is64Bit ? CalleeSavedRegClasses64Bit : CalleeSavedRegClasses32Bit;
}
//===--===//
Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.42
llvm/lib/Target/X86/X86RegisterInfo.h:1.43
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.42 Sun Nov 5 13:31:28 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.h Tue Jan 2 15:33:40 2007
@@ -69,14 +69,14 @@
unsigned OpNum,
int FrameIndex) const;
- /// getCalleeSaveRegs - Return a null-terminated list of all of the
+ /// getCalleeSavedRegs - Return a null-terminated list of all of the
/// callee-save registers on this target.
- const unsigned *getCalleeSaveRegs() const;
+ const unsigned *getCalleeSavedRegs() const;
- /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
+ /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
/// register classes to spill each callee-saved register with. The order and
- /// length of this list match the getCalleeSaveRegs() list.
- const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
+ /// length of this list match the getCalleeSavedRegs() list.
+ const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction MF,
MachineBasicBlock MBB,
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h TargetFrameInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.85 - 1.86
TargetFrameInfo.h updated: 1.21 - 1.22
---
Log message:
Fix naming inconsistency: calleesave - calleesaved.
---
Diffs of the changes: (+18 -18)
MRegisterInfo.h | 30 +++---
TargetFrameInfo.h |6 +++---
2 files changed, 18 insertions(+), 18 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.85
llvm/include/llvm/Target/MRegisterInfo.h:1.86
--- llvm/include/llvm/Target/MRegisterInfo.h:1.85 Tue Jan 2 14:55:17 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hTue Jan 2 15:30:17 2007
@@ -283,16 +283,16 @@
return false;
}
- /// getCalleeSaveRegs - Return a null-terminated list of all of the
- /// callee-save registers on this target. The register should be in the
+ /// getCalleeSavedRegs - Return a null-terminated list of all of the
+ /// callee saved registers on this target. The register should be in the
/// order of desired callee-save stack frame offset. The first register is
/// closed to the incoming stack pointer if stack grows down, and vice versa.
- virtual const unsigned* getCalleeSaveRegs() const = 0;
+ virtual const unsigned* getCalleeSavedRegs() const = 0;
- /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
- /// register classes to spill each callee-saved register with. The order and
+ /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
+ /// register classes to spill each callee saved register with. The order and
/// length of this list match the getCalleeSaveRegs() list.
- virtual const TargetRegisterClass* const *getCalleeSaveRegClasses() const =
0;
+ virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const
=0;
//======//
// Register Class Information
@@ -320,22 +320,22 @@
// immediates and memory. FIXME: Move these to TargetInstrInfo.h.
//
- /// spillCalleeSaveRegisters - Issues instruction(s) to spill all callee
saved
+ /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
saved
/// registers and returns true if it isn't possible / profitable to do so by
/// issuing a series of store instructions via storeRegToStackSlot(). Returns
/// false otherwise.
- virtual bool spillCalleeSaveRegisters(MachineBasicBlock MBB,
-MachineBasicBlock::iterator MI,
+ virtual bool spillCalleeSavedRegisters(MachineBasicBlock MBB,
+ MachineBasicBlock::iterator MI,
const std::vectorCalleeSavedInfo CSI) const
{
return false;
}
- /// restoreCalleeSaveRegisters - Issues instruction(s) to restore all callee
+ /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
/// saved registers and returns true if it isn't possible / profitable to do
/// so by issuing a series of load instructions via loadRegToStackSlot().
/// Returns false otherwise.
- virtual bool restoreCalleeSaveRegisters(MachineBasicBlock MBB,
- MachineBasicBlock::iterator MI,
+ virtual bool restoreCalleeSavedRegisters(MachineBasicBlock MBB,
+ MachineBasicBlock::iterator MI,
const std::vectorCalleeSavedInfo CSI) const
{
return false;
}
@@ -394,10 +394,10 @@
assert(0 Call Frame Pseudo Instructions do not exist on this target!);
}
- /// processFunctionBeforeCalleeSaveScan - This method is called immediately
+ /// processFunctionBeforeCalleeSavedScan - This method is called immediately
/// before PrologEpilogInserter scans the physical registers used to
determine
- /// what callee-save registers should be spilled. This method is optional.
- virtual void processFunctionBeforeCalleeSaveScan(MachineFunction MF) const {
+ /// what callee saved registers should be spilled. This method is optional.
+ virtual void processFunctionBeforeCalleeSavedScan(MachineFunction MF) const
{
}
/// processFunctionBeforeFrameFinalized - This method is called immediately
Index: llvm/include/llvm/Target/TargetFrameInfo.h
diff -u llvm/include/llvm/Target/TargetFrameInfo.h:1.21
llvm/include/llvm/Target/TargetFrameInfo.h:1.22
--- llvm/include/llvm/Target/TargetFrameInfo.h:1.21 Thu Aug 3 13:55:44 2006
+++ llvm/include/llvm/Target/TargetFrameInfo.h Tue Jan 2 15:30:17 2007
@@ -61,8 +61,8 @@
///
int getOffsetOfLocalArea() const { return LocalAreaOffset; }
- /// getCalleeSaveSpillSlots - This method returns a pointer to an array of
- /// pairs, that contains an entry for each callee save register that must be
+ /// getCalleeSavedSpillSlots - This method returns a pointer to an array of
+ /// pairs, that contains an entry for each callee saved
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp ARMRegisterInfo.h
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.30 - 1.31
ARMRegisterInfo.h updated: 1.3 - 1.4
---
Log message:
Fix naming inconsistency.
---
Diffs of the changes: (+8 -8)
ARMRegisterInfo.cpp | 12 ++--
ARMRegisterInfo.h |4 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.30
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.31
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.30Mon Dec 18 05:07:09 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Tue Jan 2 15:31:55 2007
@@ -157,23 +157,23 @@
return NULL;
}
-const unsigned* ARMRegisterInfo::getCalleeSaveRegs() const {
- static const unsigned CalleeSaveRegs[] = {
+const unsigned* ARMRegisterInfo::getCalleeSavedRegs() const {
+ static const unsigned CalleeSavedRegs[] = {
ARM::R4, ARM::R5, ARM::R6, ARM::R7,
ARM::R8, ARM::R9, ARM::R10, ARM::R11,
ARM::R14, 0
};
- return CalleeSaveRegs;
+ return CalleeSavedRegs;
}
const TargetRegisterClass* const *
-ARMRegisterInfo::getCalleeSaveRegClasses() const {
- static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
+ARMRegisterInfo::getCalleeSavedRegClasses() const {
+ static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
ARM::IntRegsRegClass, ARM::IntRegsRegClass, ARM::IntRegsRegClass,
ARM::IntRegsRegClass,
ARM::IntRegsRegClass, ARM::IntRegsRegClass, ARM::IntRegsRegClass,
ARM::IntRegsRegClass,
ARM::IntRegsRegClass, 0
};
- return CalleeSaveRegClasses;
+ return CalleeSavedRegClasses;
}
void ARMRegisterInfo::
Index: llvm/lib/Target/ARM/ARMRegisterInfo.h
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.3
llvm/lib/Target/ARM/ARMRegisterInfo.h:1.4
--- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.3 Mon Nov 27 17:37:22 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.h Tue Jan 2 15:31:55 2007
@@ -47,9 +47,9 @@
unsigned OpNum,
int FrameIndex) const;
- const unsigned *getCalleeSaveRegs() const;
+ const unsigned *getCalleeSavedRegs() const;
- const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
+ const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction MF,
MachineBasicBlock MBB,
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.cpp IA64RegisterInfo.h
Changes in directory llvm/lib/Target/IA64:
IA64RegisterInfo.cpp updated: 1.25 - 1.26
IA64RegisterInfo.h updated: 1.9 - 1.10
---
Log message:
Fix naming inconsistency.
---
Diffs of the changes: (+8 -8)
IA64RegisterInfo.cpp | 12 ++--
IA64RegisterInfo.h |4 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.25
llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.26
--- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.25 Thu Dec 7 16:21:48 2006
+++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp Tue Jan 2 15:32:44 2007
@@ -91,19 +91,19 @@
BuildMI(MBB, MI, TII.get(IA64::MOV), DestReg).addReg(SrcReg);
}
-const unsigned* IA64RegisterInfo::getCalleeSaveRegs() const {
- static const unsigned CalleeSaveRegs[] = {
+const unsigned* IA64RegisterInfo::getCalleeSavedRegs() const {
+ static const unsigned CalleeSavedRegs[] = {
IA64::r5, 0
};
- return CalleeSaveRegs;
+ return CalleeSavedRegs;
}
const TargetRegisterClass* const*
-IA64RegisterInfo::getCalleeSaveRegClasses() const {
- static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
+IA64RegisterInfo::getCalleeSavedRegClasses() const {
+ static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
IA64::GRRegClass, 0
};
- return CalleeSaveRegClasses;
+ return CalleeSavedRegClasses;
}
//===--===//
Index: llvm/lib/Target/IA64/IA64RegisterInfo.h
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.h:1.9
llvm/lib/Target/IA64/IA64RegisterInfo.h:1.10
--- llvm/lib/Target/IA64/IA64RegisterInfo.h:1.9 Mon Nov 27 17:37:22 2006
+++ llvm/lib/Target/IA64/IA64RegisterInfo.h Tue Jan 2 15:32:44 2007
@@ -44,9 +44,9 @@
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
- const unsigned *getCalleeSaveRegs() const;
+ const unsigned *getCalleeSavedRegs() const;
- const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
+ const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction MF,
MachineBasicBlock MBB,
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[llvm-commits] CVS: llvm/lib/AsmParser/llvmAsmParser.y
Changes in directory llvm/lib/AsmParser:
llvmAsmParser.y updated: 1.295 - 1.296
---
Log message:
Implement checking for unresolved types in the argument types and result
type of function definitions.
This fixes test/Regression/Assember/2007-01-02-Undefined-Arg-Type.ll
---
Diffs of the changes: (+59 -0)
llvmAsmParser.y | 59
1 files changed, 59 insertions(+)
Index: llvm/lib/AsmParser/llvmAsmParser.y
diff -u llvm/lib/AsmParser/llvmAsmParser.y:1.295
llvm/lib/AsmParser/llvmAsmParser.y:1.296
--- llvm/lib/AsmParser/llvmAsmParser.y:1.295Sun Dec 31 15:46:36 2006
+++ llvm/lib/AsmParser/llvmAsmParser.y Tue Jan 2 15:53:43 2007
@@ -149,6 +149,58 @@
}
return Ret;
}
+
+ bool TypeIsUnresolved(PATypeHolder* PATy) {
+// If it isn't abstract, its resolved
+const Type* Ty = PATy-get();
+if (!Ty-isAbstract())
+ return false;
+// Traverse the type looking for abstract types. If it isn't abstract then
+// we don't need to traverse that leg of the type.
+std::vectorconst Type* WorkList, SeenList;
+WorkList.push_back(Ty);
+while (!WorkList.empty()) {
+ const Type* Ty = WorkList.back();
+ SeenList.push_back(Ty);
+ WorkList.pop_back();
+ if (const OpaqueType* OpTy = dyn_castOpaqueType(Ty)) {
+// Check to see if this is an unresolved type
+std::mapValID, PATypeHolder::iterator I = LateResolveTypes.begin();
+std::mapValID, PATypeHolder::iterator E = LateResolveTypes.end();
+for ( ; I != E; ++I) {
+ if (I-second.get() == OpTy)
+return true;
+}
+ } else if (const SequentialType* SeqTy = dyn_castSequentialType(Ty)) {
+const Type* TheTy = SeqTy-getElementType();
+if (TheTy-isAbstract() TheTy != Ty) {
+ std::vectorconst Type*::iterator I = SeenList.begin(),
+ E = SeenList.end();
+ for ( ; I != E; ++I)
+if (*I == TheTy)
+ break;
+ if (I == E)
+WorkList.push_back(TheTy);
+}
+ } else if (const StructType* StrTy = dyn_castStructType(Ty)) {
+for (unsigned i = 0; i StrTy-getNumElements(); ++i) {
+ const Type* TheTy = StrTy-getElementType(i);
+ if (TheTy-isAbstract() TheTy != Ty) {
+std::vectorconst Type*::iterator I = SeenList.begin(),
+ E = SeenList.end();
+for ( ; I != E; ++I)
+ if (*I == TheTy)
+break;
+if (I == E)
+ WorkList.push_back(TheTy);
+ }
+}
+ }
+}
+return false;
+ }
+
+
} CurModule;
static struct PerFunctionInfo {
@@ -1943,12 +1995,19 @@
std::string FunctionName($3);
free($3); // Free strdup'd memory!
+ // Check the function result for abstractness if this is a define. We should
+ // have no abstract types at this point
+ if (!CurFun.isDeclare CurModule.TypeIsUnresolved($2.Ty))
+GEN_ERROR(Reference to abstract result: +
$2.Ty-get()-getDescription());
+
std::vectorconst Type* ParamTypeList;
std::vectorFunctionType::ParameterAttributes ParamAttrs;
ParamAttrs.push_back($2.Attrs);
if ($5) { // If there are arguments...
for (ArgListType::iterator I = $5-begin(); I != $5-end(); ++I) {
const Type* Ty = I-Ty-get();
+ if (!CurFun.isDeclare CurModule.TypeIsUnresolved(I-Ty))
+GEN_ERROR(Reference to abstract argument: + Ty-getDescription());
ParamTypeList.push_back(Ty);
if (Ty != Type::VoidTy)
ParamAttrs.push_back(I-Attrs);
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/2005-07-12-TwoMallocCalls.ll
Changes in directory llvm/test/Regression/CodeGen/Alpha: 2005-07-12-TwoMallocCalls.ll updated: 1.5 - 1.6 --- Log message: This test case previously passed the assembler without error even though it used an undefined type name as a parameter argument. This bug in the assembler has been fixed and it is now necessary to define the type. --- Diffs of the changes: (+2 -0) 2005-07-12-TwoMallocCalls.ll |2 ++ 1 files changed, 2 insertions(+) Index: llvm/test/Regression/CodeGen/Alpha/2005-07-12-TwoMallocCalls.ll diff -u llvm/test/Regression/CodeGen/Alpha/2005-07-12-TwoMallocCalls.ll:1.5 llvm/test/Regression/CodeGen/Alpha/2005-07-12-TwoMallocCalls.ll:1.6 --- llvm/test/Regression/CodeGen/Alpha/2005-07-12-TwoMallocCalls.ll:1.5 Mon Jan 1 22:30:40 2007 +++ llvm/test/Regression/CodeGen/Alpha/2005-07-12-TwoMallocCalls.ll Tue Jan 2 15:56:26 2007 @@ -1,6 +1,8 @@ ; There should be exactly two calls here (memset and malloc), no more. ; RUN: llvm-upgrade %s | llvm-as | llc -march=alpha | grep jsr | wc -l | grep 2 +%typedef.bc_struct = type opaque + implementation ; Functions: declare void %llvm.memset.i64(sbyte*, ubyte, ulong, uint) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/add.ll i32_sub_1.ll
Changes in directory llvm/test/Regression/CodeGen/Alpha:
add.ll updated: 1.3 - 1.4
i32_sub_1.ll updated: 1.2 - 1.3
---
Log message:
Fix this test cases to use parameter attributes for its parameter and
result types. These tests are checking for sext behavior and it won't
happen unless requested with the parameter attribute.
---
Diffs of the changes: (+111 -114)
add.ll | 217 +--
i32_sub_1.ll |8 +-
2 files changed, 111 insertions(+), 114 deletions(-)
Index: llvm/test/Regression/CodeGen/Alpha/add.ll
diff -u llvm/test/Regression/CodeGen/Alpha/add.ll:1.3
llvm/test/Regression/CodeGen/Alpha/add.ll:1.4
--- llvm/test/Regression/CodeGen/Alpha/add.ll:1.3 Fri Dec 1 22:23:08 2006
+++ llvm/test/Regression/CodeGen/Alpha/add.ll Tue Jan 2 22:20:23 2007
@@ -1,183 +1,180 @@
;test all the shifted and signextending adds and subs with and without consts
-
-; RUN: llvm-upgrade %s | llvm-as | llc -march=alpha | grep ' addl' |wc -l
|grep 2
-; RUN: llvm-upgrade %s | llvm-as | llc -march=alpha | grep ' addq' |wc -l
|grep 2
-; RUN: llvm-upgrade %s | llvm-as | llc -march=alpha | grep ' subl' |wc -l
|grep 2
-; RUN: llvm-upgrade %s | llvm-as | llc -march=alpha | grep ' subq' |wc -l
|grep 1
-; RUN: llvm-upgrade %s | llvm-as | llc -march=alpha | grep 'lda
$0,-100($16)' |wc -l |grep 1
-
-; RUN: llvm-upgrade %s | llvm-as | llc -march=alpha | grep 's4addl' |wc -l
|grep 2
-; RUN: llvm-upgrade %s | llvm-as | llc -march=alpha | grep 's8addl' |wc -l
|grep 2
-; RUN: llvm-upgrade %s | llvm-as | llc -march=alpha | grep 's4addq' |wc -l
|grep 2
-; RUN: llvm-upgrade %s | llvm-as | llc -march=alpha | grep 's8addq' |wc -l
|grep 2
-
-; RUN: llvm-upgrade %s | llvm-as | llc -march=alpha | grep 's4subl' |wc -l
|grep 2
-; RUN: llvm-upgrade %s | llvm-as | llc -march=alpha | grep 's8subl' |wc -l
|grep 2
-; RUN: llvm-upgrade %s | llvm-as | llc -march=alpha | grep 's4subq' |wc -l
|grep 2
-; RUN: llvm-upgrade %s | llvm-as | llc -march=alpha | grep 's8subq' |wc -l
|grep 2
+;
+; RUN: llvm-as %s | llc -march=alpha -o %t.s -f
+; RUN: grep ' addl' %t.s | wc -l | grep 2
+; RUN: grep ' addq' %t.s | wc -l | grep 2
+; RUN: grep ' subl' %t.s | wc -l | grep 2
+; RUN: grep ' subq' %t.s | wc -l | grep 1
+;
+; RUN: grep 'lda $0,-100($16)' %t.s | wc -l | grep 1
+; RUN: grep 's4addl' %t.s | wc -l | grep 2
+; RUN: grep 's8addl' %t.s | wc -l | grep 2
+; RUN: grep 's4addq' %t.s | wc -l | grep 2
+; RUN: grep 's8addq' %t.s | wc -l | grep 2
+;
+; RUN: grep 's4subl' %t.s | wc -l | grep 2
+; RUN: grep 's8subl' %t.s | wc -l | grep 2
+; RUN: grep 's4subq' %t.s | wc -l | grep 2
+; RUN: grep 's8subq' %t.s | wc -l | grep 2
implementation ; Functions:
-int %al(int %x, int %y) {
+define i32 @sext %al(i32 @sext %x.s, i32 @sext %y.s) {
entry:
-%tmp.3 = add int %y, %x
-ret int %tmp.3
+ %tmp.3.s = add i32 %y.s, %x.s ; i32 [#uses=1]
+ ret i32 %tmp.3.s
}
-int %ali(int %x) {
+define i32 @sext %ali(i32 @sext %x.s) {
entry:
-%tmp.3 = add int 100, %x
-ret int %tmp.3
+ %tmp.3.s = add i32 100, %x.s; i32 [#uses=1]
+ ret i32 %tmp.3.s
}
-long %aq(long %x, long %y) {
+define i64 @sext %aq(i64 @sext %x.s, i64 @sext %y.s) {
entry:
-%tmp.3 = add long %y, %x
-ret long %tmp.3
+ %tmp.3.s = add i64 %y.s, %x.s ; i64 [#uses=1]
+ ret i64 %tmp.3.s
}
-long %aqi(long %x) {
+
+define i64 %aqi(i64 %x.s) {
entry:
-%tmp.3 = add long 100, %x
-ret long %tmp.3
+ %tmp.3.s = add i64 100, %x.s; i64 [#uses=1]
+ ret i64 %tmp.3.s
}
-int %sl(int %x, int %y) {
+define i32 @sext %sl(i32 @sext %x.s, i32 @sext %y.s) {
entry:
-%tmp.3 = sub int %y, %x
-ret int %tmp.3
+ %tmp.3.s = sub i32 %y.s, %x.s ; i32 [#uses=1]
+ ret i32 %tmp.3.s
}
-int %sli(int %x) {
+define i32 @sext %sli(i32 @sext %x.s) {
entry:
-%tmp.3 = sub int %x, 100
-ret int %tmp.3
+ %tmp.3.s = sub i32 %x.s, 100; i32 [#uses=1]
+ ret i32 %tmp.3.s
}
-long %sq(long %x, long %y) {
+define i64 %sq(i64 %x.s, i64 %y.s) {
entry:
-%tmp.3 = sub long %y, %x
-ret long %tmp.3
+ %tmp.3.s = sub i64 %y.s, %x.s ; i64 [#uses=1]
+ ret i64 %tmp.3.s
}
-long %sqi(long %x) {
+
+define i64 %sqi(i64 %x.s) {
entry:
-%tmp.3 = sub long %x, 100
-ret long %tmp.3
+ %tmp.3.s = sub i64 %x.s, 100; i64 [#uses=1]
+ ret i64 %tmp.3.s
}
-
-
-int %a4l(int %x, int %y) {
+define i32 @sext %a4l(i32 @sext %x.s, i32 @sext %y.s) {
entry:
-%tmp.1 = shl int %y, ubyte 2
-%tmp.3 = add int %tmp.1, %x
-ret int %tmp.3
+ %tmp.1.s = shl i32 %y.s, i8 2 ; i32 [#uses=1]
+ %tmp.3.s = add i32 %tmp.1.s, %x.s ; i32 [#uses=1]
+ ret i32 %tmp.3.s
}
-int %a8l(int %x, int %y) {
+define i32
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.450 - 1.451
---
Log message:
Clean up from recent changes. Comment the new parameter to ExpandLibCall.
Consolidate some lines of code and remove duplication.
---
Diffs of the changes: (+20 -24)
LegalizeDAG.cpp | 44
1 files changed, 20 insertions(+), 24 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.450
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.451
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.450 Sat Dec 30 23:55:36 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Jan 2 22:22:32 2007
@@ -2127,9 +2127,7 @@
const char *FnName = 0;
if (Node-getOpcode() == ISD::MEMSET) {
-Entry.Node = Tmp2;
-Entry.Ty = IntPtrTy;
-Entry.isSigned = false;
+Entry.Node = Tmp2; Entry.isSigned = false; Entry.Ty = IntPtrTy;
Args.push_back(Entry);
// Extend the (previously legalized) ubyte argument to be an int value
// for the call.
@@ -2145,12 +2143,10 @@
FnName = memset;
} else if (Node-getOpcode() == ISD::MEMCPY ||
Node-getOpcode() == ISD::MEMMOVE) {
-Entry.Node = Tmp2; Entry.Ty = IntPtrTy; Entry.isSigned = false;
-Args.push_back(Entry);
-Entry.Node = Tmp3; Entry.Ty = IntPtrTy; Entry.isSigned = false;
-Args.push_back(Entry);
-Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSigned = false;
-Args.push_back(Entry);
+Entry.Ty = IntPtrTy; Entry.isSigned = false;
+Entry.Node = Tmp2; Args.push_back(Entry);
+Entry.Node = Tmp3; Args.push_back(Entry);
+Entry.Node = Tmp4; Args.push_back(Entry);
FnName = Node-getOpcode() == ISD::MEMMOVE ? memmove : memcpy;
} else {
assert(0 Unknown op!);
@@ -2356,7 +2352,7 @@
DAG.getNode(ISD::FP_EXTEND, MVT::f64,
Tmp2));
}
SDOperand Dummy;
- Result = ExpandLibCall(FnName, Node, false, Dummy);
+ Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
break;
}
break;
@@ -2450,7 +2446,7 @@
// Floating point mod - fmod libcall.
const char *FnName = Node-getValueType(0) == MVT::f32 ?
fmodf:fmod;
SDOperand Dummy;
-Result = ExpandLibCall(FnName, Node, false, Dummy);
+Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
}
break;
}
@@ -2699,7 +2695,7 @@
default: assert(0 Unreachable!);
}
SDOperand Dummy;
-Result = ExpandLibCall(FnName, Node, false, Dummy);
+Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
break;
}
}
@@ -2711,7 +2707,7 @@
const char *FnName = Node-getValueType(0) == MVT::f32
? __powisf2 : __powidf2;
SDOperand Dummy;
-Result = ExpandLibCall(FnName, Node, false, Dummy);
+Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
break;
}
case ISD::BIT_CONVERT:
@@ -2897,7 +2893,7 @@
default: assert(0 Unreachable!);
}
SDOperand Dummy;
- Result = ExpandLibCall(FnName, Node, false, Dummy);
+ Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
break;
}
case Promote:
@@ -3621,14 +3617,14 @@
SDOperand Dummy;
Tmp1 = ExpandLibCall(FnName1,
DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
- false, Dummy);
+ false /*sign irrelevant*/, Dummy);
Tmp2 = DAG.getConstant(0, MVT::i32);
CC = DAG.getCondCode(CC1);
if (FnName2) {
Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
LHS = ExpandLibCall(FnName2,
DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
-false, Dummy);
+false /*sign irrelevant*/, Dummy);
Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
DAG.getCondCode(CC2));
Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
@@ -4836,9 +4832,9 @@
}
if (Node-getOperand(0).getValueType() == MVT::f32)
- Lo = ExpandLibCall(__fixsfdi, Node, false, Hi);
+ Lo = ExpandLibCall(__fixsfdi, Node, false/*sign irrelevant*/, Hi);
else
- Lo = ExpandLibCall(__fixdfdi, Node, false, Hi);
+ Lo = ExpandLibCall(__fixdfdi, Node, false/*sign irrelevant*/, Hi);
break;
case ISD::FP_TO_UINT:
@@ -4860,9 +4856,9 @@
}
if (Node-getOperand(0).getValueType() == MVT::f32)
- Lo = ExpandLibCall(__fixunssfdi, Node, false, Hi);
+ Lo = ExpandLibCall(__fixunssfdi, Node, false/*sign irrelevant*/, Hi);
else
- Lo =
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.335 - 1.336
---
Log message:
Two changes:
1. Switch expression and cases are compared signed and are sign extended.
2. For function results needing extended, do SIGN_EXTEND if the SExtAttribute
is set and ZERO_EXTEND if the ZExtAttribute is set, otherwise just let
the Legalizer do ANY_EXTEND.
This fixes the recent regression in kimwitu++ and probably the llvm-gcc
bootstrap issue we had today.
---
Diffs of the changes: (+12 -5)
SelectionDAGISel.cpp | 17 -
1 files changed, 12 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.335
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.336
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.335Sat Dec 30
23:55:36 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Jan 2 22:25:33 2007
@@ -397,8 +397,8 @@
struct CaseCmp {
bool operator () (const Case C1, const Case C2) {
assert(isaConstantInt(C1.first) isaConstantInt(C2.first));
- return castconst ConstantInt(C1.first)-getZExtValue()
-castconst ConstantInt(C2.first)-getZExtValue();
+ return castconst ConstantInt(C1.first)-getSExtValue()
+castconst ConstantInt(C2.first)-getSExtValue();
}
};
@@ -766,10 +766,17 @@
else
TmpVT = MVT::i32;
const FunctionType *FTy = I.getParent()-getParent()-getFunctionType();
- ISD::NodeType ExtendKind = ISD::SIGN_EXTEND;
+ ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
+ if (FTy-paramHasAttr(0, FunctionType::SExtAttribute))
+ExtendKind = ISD::SIGN_EXTEND;
if (FTy-paramHasAttr(0, FunctionType::ZExtAttribute))
ExtendKind = ISD::ZERO_EXTEND;
- RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
+ if (ExtendKind == ISD::ANY_EXTEND)
+// There was no specification for extension in the parameter attributes
+// so we will just let the legalizer do the ANY_EXTEND
+;
+ else
+RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
}
NewValues.push_back(RetOp);
NewValues.push_back(DAG.getConstant(false, MVT::i32));
@@ -1378,7 +1385,7 @@
// Create a CaseBlock record representing a conditional branch to
// the LHS node if the value being switched on SV is less than C.
// Otherwise, branch to LHS.
- ISD::CondCode CC = ISD::SETULT;
+ ISD::CondCode CC = ISD::SETLT;
SelectionDAGISel::CaseBlock CB(CC, SV, C, TrueBB, FalseBB, CR.CaseBB);
if (CR.CaseBB == CurMBB)
___
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Re: [llvm-commits] [llvm-gcc] Cumulative PR950 Patch, Version 3 (Please Commit)
Hi Reid, I got this error when compiling: ../../llvm-gcc.src/gcc/llvm-convert.cpp: In member function 'bool TreeToLLVM::EmitFrontendExpandedBuiltinCall(tree_node*, tree_node*, llvm::Value*, llvm::Value*)': ../../llvm-gcc.src/gcc/llvm-convert.cpp:3128: error: 'const class llvm::Type' has no member named 'isSigned' ../../llvm-gcc.src/gcc/llvm-convert.cpp:3128: error: 'const class llvm::Type' has no member named 'isSigned' I should be working with TOT in the LLVM branch... -bw On Jan 2, 2007, at 9:29 PM, Reid Spencer wrote: All, The attached patch is a cumulative patch of changes to llvm-gcc since Dec 22nd. It should apply cleanly to the SVN Mirror's version 236. This contains the same changes as the last PR950 patch that I sent with the addition of @zext parameter attributes for bool types. The difference in this patch from the last one is only in the llvm-types.cpp file. If you're working with llvm-gcc HEAD version via the SVN repository, please note that a hardware failure has caused a delay in the mirror getting updated. It might take a few more days to get it restored. Until then, you'll need to apply this cumulative patches to rev 236 (current head) manually and rebuild in order for llvm-gcc to build with the current CVS head version of LLVM. If you've previously applied patches to llvm-gcc, I recommend you remove the affected files, update from the mirror to version 236 and then apply this patch. JIM: Yup, this needs to be committed. Reid. PR950-3.patch ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
