[llvm-commits] [llvm] r47056 - /llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
Author: evancheng Date: Wed Feb 13 02:41:08 2008 New Revision: 47056 URL: http://llvm.org/viewvc/llvm-project?rev=47056view=rev Log: * Cannot safely commute an instruction there are other defs which can reach its uses. * Ignore copy instructions which have already been coalesced. Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=47056r1=47055r2=47056view=diff == --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Wed Feb 13 02:41:08 2008 @@ -237,7 +237,9 @@ // AValNo is the value number in A that defines the copy, A3 in the example. LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1); VNInfo *AValNo = ALR-valno; - if (AValNo-def == ~0U || AValNo-def == ~1U) + // If other defs can reach uses of this def, then it's not safe to perform + // the optimization. + if (AValNo-def == ~0U || AValNo-def == ~1U || AValNo-hasPHIKill) return false; MachineInstr *DefMI = li_-getInstructionFromIndex(AValNo-def); const TargetInstrDesc TID = DefMI-getDesc(); @@ -312,6 +314,8 @@ MachineOperand UseMO = UI.getOperand(); ++UI; MachineInstr *UseMI = UseMO.getParent(); + if (JoinedCopies.count(UseMI)) +continue; unsigned UseIdx = li_-getInstructionIndex(UseMI); LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx); if (ULR-valno != AValNo) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47057 - /llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
Author: evancheng Date: Wed Feb 13 03:06:18 2008 New Revision: 47057 URL: http://llvm.org/viewvc/llvm-project?rev=47057view=rev Log: Fix a potential serious problem where kills belonging to the val# defined by a two-address instruction is also on the val# that defines the input. Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=47057r1=47056r2=47057view=diff == --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Feb 13 03:06:18 2008 @@ -315,7 +315,6 @@ const LiveRange *OldLR = interval.getLiveRangeContaining(RedefIndex-1); VNInfo *OldValNo = OldLR-valno; - unsigned OldEnd = OldLR-end; // Delete the initial value, which should be short and continuous, // because the 2-addr copy must be in the same MBB as the redef. @@ -328,7 +327,8 @@ // The new value number (#1) is defined by the instruction we claimed // defined value #0. VNInfo *ValNo = interval.getNextValue(0, 0, VNInfoAllocator); - interval.copyValNumInfo(ValNo, OldValNo); + ValNo-def = OldValNo-def; + ValNo-reg = OldValNo-reg; // Value#0 is now defined by the 2-addr instruction. OldValNo-def = RedefIndex; @@ -339,7 +339,6 @@ DOUT replace range with LR; interval.addRange(LR); interval.addKill(ValNo, RedefIndex); - interval.removeKills(ValNo, RedefIndex, OldEnd); // If this redefinition is dead, we need to add a dummy unit live // range covering the def slot. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r47043 - in /llvm/trunk/lib: CodeGen/TargetInstrInfoImpl.cpp Target/PowerPC/PPCInstrInfo.cpp Target/X86/X86InstrInfo.cpp
On Feb 12, 2008, at 9:59 PM, Chris Lattner wrote:
On Feb 12, 2008, at 6:46 PM, Evan Cheng wrote:
Author: evancheng
Date: Tue Feb 12 20:46:49 2008
New Revision: 47043
URL: http://llvm.org/viewvc/llvm-project?rev=47043view=rev
Log:
commuteInstr() can now commute non-ssa machine instrs.
Modified:
llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=47043r1=47042r2=47043view=diff
=
=
=
=
=
=
=
=
=
=
--- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Tue Feb 12
20:46:49 2008
@@ -23,8 +23,17 @@
This only knows how to commute register operands so far);
unsigned Reg1 = MI-getOperand(1).getReg();
unsigned Reg2 = MI-getOperand(2).getReg();
+ MachineOperand MO = MI-getOperand(0);
+ bool UpdateReg0 = MO.isReg() MO.getReg() == Reg1;
bool Reg1IsKill = MI-getOperand(1).isKill();
bool Reg2IsKill = MI-getOperand(2).isKill();
+ if (UpdateReg0) {
Why not just use:
if (MO.isReg() MO.getReg() == Reg1)
Further, does it even make sense for instructions to be marked
commutable if the first operand isn't a register? Why not just use:
if (MO.getReg() == Reg1)
Ok.
Bonus points for making tblgen reject instructions marked commutable
that don't start with three register operands.
That's too restrictive. It's entirely legal for target instruction
that don't start with 3 register operands to be commutable. That's why
we allow target specific code to commute certain instructions.
Evan
-Chris
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[llvm-commits] [llvm] r47058 - /llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
Author: evancheng
Date: Wed Feb 13 03:13:21 2008
New Revision: 47058
URL: http://llvm.org/viewvc/llvm-project?rev=47058view=rev
Log:
Simplify.
Modified:
llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=47058r1=47057r2=47058view=diff
==
--- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Wed Feb 13 03:13:21 2008
@@ -23,11 +23,9 @@
This only knows how to commute register operands so far);
unsigned Reg1 = MI-getOperand(1).getReg();
unsigned Reg2 = MI-getOperand(2).getReg();
- MachineOperand MO = MI-getOperand(0);
- bool UpdateReg0 = MO.isReg() MO.getReg() == Reg1;
bool Reg1IsKill = MI-getOperand(1).isKill();
bool Reg2IsKill = MI-getOperand(2).isKill();
- if (UpdateReg0) {
+ if (MI-getOperand(0).getReg() == Reg1) {
// Must be two address instruction!
assert(MI-getDesc().getOperandConstraint(0, TOI::TIED_TO)
Expecting a two-address instruction!);
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[llvm-commits] [llvm] r47059 - /llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h
Author: evancheng
Date: Wed Feb 13 03:18:16 2008
New Revision: 47059
URL: http://llvm.org/viewvc/llvm-project?rev=47059view=rev
Log:
Simplify.
Modified:
llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h
Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=47059r1=47058r2=47059view=diff
==
--- llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Wed Feb 13 03:18:16
2008
@@ -217,14 +217,14 @@
/// maps used by register allocator.
void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
- if (mi2i != mi2iMap_.end()) {
-i2miMap_[mi2i-second/InstrSlots::NUM] = NewMI;
-Mi2IndexMap::const_iterator it = mi2iMap_.find(MI);
-assert(it != mi2iMap_.end() Invalid instruction!);
-unsigned Index = it-second;
-mi2iMap_.erase(MI);
-mi2iMap_[NewMI] = Index;
- }
+ if (mi2i == mi2iMap_.end())
+return;
+ i2miMap_[mi2i-second/InstrSlots::NUM] = NewMI;
+ Mi2IndexMap::iterator it = mi2iMap_.find(MI);
+ assert(it != mi2iMap_.end() Invalid instruction!);
+ unsigned Index = it-second;
+ mi2iMap_.erase(it);
+ mi2iMap_[NewMI] = Index;
}
BumpPtrAllocator getVNInfoAllocator() { return VNInfoAllocator; }
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[llvm-commits] [llvm] r47060 - /llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
Author: evancheng
Date: Wed Feb 13 03:56:03 2008
New Revision: 47060
URL: http://llvm.org/viewvc/llvm-project?rev=47060view=rev
Log:
Some code clean up.
Modified:
llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=47060r1=47059r2=47060view=diff
==
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Wed Feb 13 03:56:03 2008
@@ -293,7 +293,8 @@
}
}
- // Commute def machine instr.
+ // At this point we have decided that it is legal to do this
+ // transformation. Start by commuting the instruction.
MachineBasicBlock *MBB = DefMI-getParent();
MachineInstr *NewMI = tii_-commuteInstruction(DefMI);
if (NewMI != DefMI) {
@@ -312,10 +313,10 @@
for (MachineRegisterInfo::use_iterator UI = mri_-use_begin(IntA.reg),
UE = mri_-use_end(); UI != UE;) {
MachineOperand UseMO = UI.getOperand();
+MachineInstr *UseMI = *UI;
++UI;
-MachineInstr *UseMI = UseMO.getParent();
- if (JoinedCopies.count(UseMI))
-continue;
+if (JoinedCopies.count(UseMI))
+ continue;
unsigned UseIdx = li_-getInstructionIndex(UseMI);
LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
if (ULR-valno != AValNo)
@@ -323,35 +324,35 @@
UseMO.setReg(NewReg);
if (UseMO.isKill())
BKills.push_back(li_-getUseIndex(UseIdx)+1);
-if (UseMI != CopyMI) {
- unsigned SrcReg, DstReg;
- if (!tii_-isMoveInstr(*UseMI, SrcReg, DstReg))
-continue;
- unsigned repDstReg = rep(DstReg);
- if (repDstReg != IntB.reg) {
-// Update dst register interval val# since its source register has
-// changed.
-LiveInterval DLI = li_-getInterval(repDstReg);
-LiveInterval::iterator DLR =
- DLI.FindLiveRangeContaining(li_-getDefIndex(UseIdx));
-DLR-valno-reg = NewReg;
-ChangedCopies.insert(UseMI);
- } else {
-// This copy will become a noop. If it's defining a new val#,
-// remove that val# as well. However this live range is being
-// extended to the end of the existing live range defined by the copy.
-unsigned DefIdx = li_-getDefIndex(UseIdx);
-LiveInterval::iterator DLR = IntB.FindLiveRangeContaining(DefIdx);
-BHasPHIKill |= DLR-valno-hasPHIKill;
-assert(DLR-valno-def == DefIdx);
-BDeadValNos.push_back(DLR-valno);
-BExtend[DLR-start] = DLR-end;
-JoinedCopies.insert(UseMI);
-// If this is a kill but it's going to be removed, the last use
-// of the same val# is the new kill.
-if (UseMO.isKill()) {
- BKills.pop_back();
-}
+if (UseMI == CopyMI)
+ continue;
+unsigned SrcReg, DstReg;
+if (!tii_-isMoveInstr(*UseMI, SrcReg, DstReg))
+ continue;
+unsigned repDstReg = rep(DstReg);
+if (repDstReg != IntB.reg) {
+ // Update dst register interval val# since its source register has
+ // changed.
+ LiveInterval DLI = li_-getInterval(repDstReg);
+ LiveInterval::iterator DLR =
+DLI.FindLiveRangeContaining(li_-getDefIndex(UseIdx));
+ DLR-valno-reg = NewReg;
+ ChangedCopies.insert(UseMI);
+} else {
+ // This copy will become a noop. If it's defining a new val#,
+ // remove that val# as well. However this live range is being
+ // extended to the end of the existing live range defined by the copy.
+ unsigned DefIdx = li_-getDefIndex(UseIdx);
+ LiveInterval::iterator DLR = IntB.FindLiveRangeContaining(DefIdx);
+ BHasPHIKill |= DLR-valno-hasPHIKill;
+ assert(DLR-valno-def == DefIdx);
+ BDeadValNos.push_back(DLR-valno);
+ BExtend[DLR-start] = DLR-end;
+ JoinedCopies.insert(UseMI);
+ // If this is a kill but it's going to be removed, the last use
+ // of the same val# is the new kill.
+ if (UseMO.isKill()) {
+BKills.pop_back();
}
}
}
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Re: [llvm-commits] [llvm] r47046 - in /llvm/trunk: include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/SimpleRegisterCoalescing.cpp lib/CodeGen/SimpleRegisterCoalescing.h
On Feb 12, 2008, at 9:56 PM, Chris Lattner wrote:
On Feb 12, 2008, at 7:01 PM, Evan Cheng wrote:
Author: evancheng
Date: Tue Feb 12 21:01:43 2008
New Revision: 47046
URL: http://llvm.org/viewvc/llvm-project?rev=47046view=rev
Log:
Initial support for copy elimination by commuting its definition MI.
Yay, thanks for tackling this Evan!
This speeds up FreeBench/neural by 29%, Olden/bh by 12%, oopack_v1p8
by 53%.
Very nice, does it also help shootout/fib?
bh speedup doesn't seem real. It doesn't help fib.
+ // Get the location that B is defined at. Two options: either
this value has
+ // an unknown definition point or it is defined at CopyIdx. If
unknown, we
+ // can't process it.
+ if (!BValNo-reg) return false;
+ assert(BValNo-def == CopyIdx Copy doesn't define the
value?);
+
+ // AValNo is the value number in A that defines the copy, A3 in
the example.
+ LiveInterval::iterator ALR =
IntA.FindLiveRangeContaining(CopyIdx-1);
+ VNInfo *AValNo = ALR-valno;
This idiom happens a lot in the preexisting code. Please use:
VNInfo *AValNo = IntA.FindLiveRangeContaining(CopyIdx-1)-valno;
ALR is also used below.
Or better yet, add a new method that returns valno directly.
+ int Idx = -1;
Idx is too generic of a name for a variable with this long of
lifetime, please name it something more descriptive. What type of idx
is it?
+ for (unsigned i = 0, e = DefMI-getNumOperands(); i != e; ++i) {
This loop needs a comment. What are you trying to find with this
loop? Maybe it should be moved out to its own function which just
returns idx? This would force you to name it, which would describe
what it does :)
There is a reason I said initial in the commit message. This is not
done. I need a target hook to tell me what is the new destination
register after commuting. Right now this is basically assuming x86
commutable instructions: A = A + B
Another random question unrelated to this code: now that we have
efficient RAUW, can we eliminate the 'rep' mapping stuff and just
RAUW vregs as they are coallesced?
Well, actually it's related. I think it's required for correctness.
See below.
+ MachineBasicBlock *MBB = DefMI-getParent();
+ MachineInstr *NewMI = tii_-commuteInstruction(DefMI);
+ if (NewMI != DefMI) {
+li_-ReplaceMachineInstrInMaps(DefMI, NewMI);
+MBB-insert(DefMI, NewMI);
+MBB-erase(DefMI);
+ }
+ unsigned OpIdx = NewMI-findRegisterUseOperandIdx(IntA.reg);
+ NewMI-getOperand(OpIdx).setIsKill();
+
+ // Update uses of IntA of the specific Val# with IntB.
+ bool BHasPHIKill = BValNo-hasPHIKill;
+ SmallVectorVNInfo*, 4 BDeadValNos;
+ SmallVectorunsigned, 4 BKills;
+ std::mapunsigned, unsigned BExtend;
+ for (MachineRegisterInfo::use_iterator UI = mri_-
use_begin(IntA.reg),
+ UE = mri_-use_end(); UI != UE;) {
Yay for use_iterators :)
Except I don't think this is quite right. Iterating through uses of
IntA.reg means we end up not updating other uses that have already
been coalesced to it.
+MachineOperand UseMO = UI.getOperand();
+++UI;
+MachineInstr *UseMI = UseMO.getParent();
It would be more clear to use (before the increment):
MachineInstr *UseMI = *UI;
Note that if an instruction uses a register multiple times,
incrementing the iterator could point into another operand of the same
instruction. This is rare, but the code needs to handle it
correctly. I'm concerned about cases like:
r1 = or r2, r2
(which is the copy operation on some targets).
Where the use iterator could point to the first r2, and incrementing
it could point to the next r2. This could be avoided by not zapping
instructions in this loop: move the copy zapping to a walk over a
smallset or something.
Nothing is being zapped in the loop. Copies that would be zapped are
put into a set JoinedCopies. In fact, all uses have to be updated to
the new register.
+unsigned UseIdx = li_-getInstructionIndex(UseMI);
+LiveInterval::iterator ULR =
IntA.FindLiveRangeContaining(UseIdx);
+if (ULR-valno != AValNo)
+ continue;
+UseMO.setReg(NewReg);
+if (UseMO.isKill())
+ BKills.push_back(li_-getUseIndex(UseIdx)+1);
+if (UseMI != CopyMI) {
if (UseMI == CopyMI) continue;
+ unsigned SrcReg, DstReg;
+ if (!tii_-isMoveInstr(*UseMI, SrcReg, DstReg))
+continue;
+ unsigned repDstReg = rep(DstReg);
+ if (repDstReg != IntB.reg) {
+// Update dst register interval val# since its source
register has
+// changed.
+LiveInterval DLI = li_-getInterval(repDstReg);
+LiveInterval::iterator DLR =
+ DLI.FindLiveRangeContaining(li_-getDefIndex(UseIdx));
+DLR-valno-reg = NewReg;
+ChangedCopies.insert(UseMI);
+ } else {
+// This copy will become a noop. If it's defining a new
val#,
+// remove that val# as well. However this live range is
Re: [llvm-commits] [llvm] r47007 - in /llvm/trunk: lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/2008-02-12-SMAXTripCount.ll
Chris Lattner wrote: Very nice, please add a comment above the code explaining what is going on though :) Done. Wojtek ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47061 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Author: wmat
Date: Wed Feb 13 05:51:34 2008
New Revision: 47061
URL: http://llvm.org/viewvc/llvm-project?rev=47061view=rev
Log:
Add comments as per review feedback.
Modified:
llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=47061r1=47060r2=47061view=diff
==
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Wed Feb 13 05:51:34 2008
@@ -2525,18 +2525,26 @@
return UnknownValue;
if (AddRec-isAffine()) {
-// The number of iterations for {n,+,1} m, is m-n. However, we don't
-// know that m is = n on input to the loop. If it is, the condition
-// returns true zero times. To handle both cases, we return SMAX(m, n)-n.
-
// FORNOW: We only support unit strides.
SCEVHandle One = SE.getIntegerSCEV(1, RHS-getType());
if (AddRec-getOperand(1) != One)
return UnknownValue;
+// We know the LHS is of the form {n,+,1} and the RHS is some
loop-invariant
+// m. So, we count the number of iterations in which {n,+,1} m is true.
+// Note that we cannot simply return max(m-n,0) because it's not safe to
+// treat m-n as signed nor unsinged due to overflow possibility.
+
+// First, we get the value of the LHS in the first iteration: n
SCEVHandle Start = AddRec-getOperand(0);
-SCEVHandle End = isSigned ? SE.getSMaxExpr(RHS, Start) : (SCEVHandle)RHS;
+// Then, we get the value of the LHS in the first iteration in which the
+// above condition doesn't hold. This equals to max(m,n).
+// FIXME (PR2003): we should have an umax operator as well.
+SCEVHandle End = isSigned ? SE.getSMaxExpr(RHS,Start) : (SCEVHandle)RHS;
+
+// Finally, we subtract these two values to get the number of times the
+// backedge is executed: max(m,n)-n.
return SE.getMinusSCEV(End, Start);
}
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Re: [llvm-commits] [llvm] r47061 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp
+// treat m-n as signed nor unsinged due to overflow possibility. unsinged - unsigned Ciao, D. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47062 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Author: wmat
Date: Wed Feb 13 06:21:32 2008
New Revision: 47062
URL: http://llvm.org/viewvc/llvm-project?rev=47062view=rev
Log:
Fix typo. Thanks to Duncan for noticing.
Modified:
llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=47062r1=47061r2=47062view=diff
==
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Wed Feb 13 06:21:32 2008
@@ -2533,7 +2533,7 @@
// We know the LHS is of the form {n,+,1} and the RHS is some
loop-invariant
// m. So, we count the number of iterations in which {n,+,1} m is true.
// Note that we cannot simply return max(m-n,0) because it's not safe to
-// treat m-n as signed nor unsinged due to overflow possibility.
+// treat m-n as signed nor unsigned due to overflow possibility.
// First, we get the value of the LHS in the first iteration: n
SCEVHandle Start = AddRec-getOperand(0);
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Re: [llvm-commits] [llvm] r47045 - /llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
Hi Nate,
Nate Begeman wrote:
Author: sampo
Date: Tue Feb 12 20:58:33 2008
New Revision: 47045
URL: http://llvm.org/viewvc/llvm-project?rev=47045view=rev
Log:
Make register scavenging happy by not using a reg (CR0) that isn't defined
I don't know about darwin, but this breaks linux/ppc32 JIT (llc works
fine). On a simple test case:
define i32 @main(i32 %argc) {
entry:
%tmp2 = add i32 2, %argc
ret i32 %tmp2
}
I get:
# Machine code for main():
Live Ins: r3 in VR#1024
Live Outs: r3
entry: 0x109cde80, LLVM BB @0x109c2640, ID#0:
Live Ins: %r3
%r3def = ADDI %r3kill, 2
BLR 20, %reg0, %r3imp-use,kill
# End machine code for main().
and the emission of the BLR instruction gives an error message:
Unhandled reg in PPCRegisterInfo::getRegisterNumbering!
It happens line 125 of PPCCodeEmitter.cpp. And the register number is zero.
Do you not get this on darwin?
Thanks,
Nicolas
Modified:
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=47045r1=47044r2=47045view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Tue Feb 12 20:58:33 2008
@@ -293,7 +293,7 @@
// PowerPC Predicate operand. 20 = (05)|20 = always, CR0 is a dummy reg
// that doesn't matter.
def pred : PredicateOperandOtherVT, (ops imm, CRRC),
- (ops (i32 20), CR0) {
+ (ops (i32 20), (i32 zero_reg)) {
let PrintMethod = printPredicateOperand;
}
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[llvm-commits] [llvm] r47063 - /llvm/trunk/docs/CFEBuildInstrs.html
Author: baldrick Date: Wed Feb 13 10:46:10 2008 New Revision: 47063 URL: http://llvm.org/viewvc/llvm-project?rev=47063view=rev Log: Add notes on Ada compilers that can be used for the build. Put all items that the user should specify in bold. Make it a debug build. Modified: llvm/trunk/docs/CFEBuildInstrs.html Modified: llvm/trunk/docs/CFEBuildInstrs.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CFEBuildInstrs.html?rev=47063r1=47062r2=47063view=diff == --- llvm/trunk/docs/CFEBuildInstrs.html (original) +++ llvm/trunk/docs/CFEBuildInstrs.html Wed Feb 13 10:46:10 2008 @@ -92,14 +92,22 @@ systems without some work./p/li lipThe build requires having a compiler that supports Ada, C and C++. The Ada front-end is written in Ada so an Ada compiler is needed to - build it. The LLVM parts of llvm-gcc are written in C++ so a C++ + build it. What is more, the Ada compiler must not be more recent + than what it is trying to compile, otherwise the build will fail. + This rules out gcc-4.3 (but not gcc-4.2) and also the + a href=http://libre.adacore.com/;2007 GNAT GPL Edition/a. + The LLVM parts of llvm-gcc are written in C++ so a C++ compiler is needed to build them. The rest of gcc is written in C. Some linux distributions provide a version of gcc that supports all three languages (the Ada part often comes as an add-on package to the rest of gcc). Otherwise it is possible to combine two versions - of gcc, one that supports Ada and C (such as - a href=http://libre.adacore.com/;GNAT GPL Edition/a) and another - which supports C++, see below./p/li + of gcc, one that supports Ada and C (such as the + a href=http://libre.adacore.com/;2006 GNAT GPL Edition/a) + and another which supports C++, see below./p/li + lipBecause the Ada front-end is experimental, it is wise to build the + compiler with checking enabled. This causes it to run slower, but + helps catch mistakes in the compiler (please report any problems using + a href=http://llvm.org/bugs;LLVM bugzilla/a)./p/li /ol pSupposing appropriate compilers are available, llvm-gcc with Ada support can @@ -153,21 +161,22 @@ lipConfigure LLVM (here it is configured to install into tt/usr/local/tt):/p div class=doc_code -pre../llvm/configure --prefix=/usr/local/pre +pre../llvm/configure --prefix=b/usr/local/b/pre /div pIf you have a multi-compiler setup and the C++ compiler is not the default, then you can configure like this:/p div class=doc_code -preCXX=bPATH_TO_C++_COMPILER/b ../llvm/configure --prefix=/usr/local/pre +preCXX=bPATH_TO_C++_COMPILER/b ../llvm/configure --prefix=b/usr/local/b/pre /div /li - lipBuild LLVM:/p + lipBuild LLVM with checking enabled (use ttENABLE_OPTIMIZED=1/tt to + build without checking):/p div class=doc_code -premake/pre +premake ENABLE_OPTIMIZED=0/pre /div /li @@ -190,11 +199,13 @@ /li lipConfigure llvm-gcc (here it is configured to install into tt/usr/local/tt). + The tt--enable-checking/tt flag turns on sanity checks inside the compiler. + If you omit it then LLVM must be built with ttmake ENABLE_OPTIMIZED=1/tt. Additional languages can be appended to the --enable-languages switch, for example tt--enable-languages=ada,c,c++/tt./p div class=doc_code -pre../llvm-gcc-4.2/configure --prefix=/usr/local --enable-languages=ada,c --enable-checking --enable-llvm=$PWD/../llvm-objects --disable-shared --disable-bootstrap --disable-multilib/pre +pre../llvm-gcc-4.2/configure --prefix=b/usr/local/b --enable-languages=ada,c --enable-checking --enable-llvm=$PWD/../llvm-objects --disable-shared --disable-bootstrap --disable-multilib/pre /div pIf you have a multi-compiler setup, then you can configure like this:/p @@ -203,7 +214,7 @@ pre export CC=bPATH_TO_C_AND_ADA_COMPILER/b export CXX=bPATH_TO_C++_COMPILER/b -../llvm-gcc-4.2/configure --prefix=/usr/local --enable-languages=ada,c --enable-checking --enable-llvm=$PWD/../llvm-objects --disable-shared --disable-bootstrap --disable-multilib/pre +../llvm-gcc-4.2/configure --prefix=b/usr/local/b --enable-languages=ada,c --enable-checking --enable-llvm=$PWD/../llvm-objects --disable-shared --disable-bootstrap --disable-multilib/pre /div /li ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r47007 - in /llvm/trunk: lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/2008-02-12-SMAXTripCount.ll
On Feb 13, 2008, at 3:51 AM, Wojciech Matyjewicz wrote: Chris Lattner wrote: Very nice, please add a comment above the code explaining what is going on though :) Done. Very nice, thanks! -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r47043 - in /llvm/trunk/lib: CodeGen/TargetInstrInfoImpl.cpp Target/PowerPC/PPCInstrInfo.cpp Target/X86/X86InstrInfo.cpp
Bonus points for making tblgen reject instructions marked commutable that don't start with three register operands. That's too restrictive. It's entirely legal for target instruction that don't start with 3 register operands to be commutable. That's why we allow target specific code to commute certain instructions. Ah right, good point! -chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r47045 - /llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
I don't know about darwin, but this breaks linux/ppc32 JIT (llc works
fine). On a simple test case:
define i32 @main(i32 %argc) {
entry:
%tmp2 = add i32 2, %argc
ret i32 %tmp2
}
Yep, this was broken on darwin as well. I just committed a fix which
makes it work for me, please verify.
-Chris
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[llvm-commits] [llvm] r47066 - /llvm/trunk/lib/Transforms/IPO/ConstantMerge.cpp
Author: lattner
Date: Wed Feb 13 11:18:26 2008
New Revision: 47066
URL: http://llvm.org/viewvc/llvm-project?rev=47066view=rev
Log:
remove some dead code.
Modified:
llvm/trunk/lib/Transforms/IPO/ConstantMerge.cpp
Modified: llvm/trunk/lib/Transforms/IPO/ConstantMerge.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/ConstantMerge.cpp?rev=47066r1=47065r2=47066view=diff
==
--- llvm/trunk/lib/Transforms/IPO/ConstantMerge.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/ConstantMerge.cpp Wed Feb 13 11:18:26 2008
@@ -87,10 +87,6 @@
} else if (GV-hasInternalLinkage()) {// Yup, this is a duplicate!
// Make all uses of the duplicate constant use the canonical version.
Replacements.push_back(std::make_pair(GV, Slot));
-} else if (GV-hasInternalLinkage()) {
- // Make all uses of the duplicate constant use the canonical version.
- Replacements.push_back(std::make_pair(Slot, GV));
- Slot = GV;
}
}
}
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[llvm-commits] [llvm] r47067 - /llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
Author: lattner
Date: Wed Feb 13 11:24:14 2008
New Revision: 47067
URL: http://llvm.org/viewvc/llvm-project?rev=47067view=rev
Log:
Fix the PPC JIT regressions by encoding zeroreg as 0 for BLR.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=47067r1=47066r2=47067view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed Feb 13 11:24:14 2008
@@ -46,6 +46,7 @@
unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
using namespace PPC;
switch (RegEnum) {
+ case 0: return 0;
case R0 : case X0 : case F0 : case V0 : case CR0: return 0;
case R1 : case X1 : case F1 : case V1 : case CR1: return 1;
case R2 : case X2 : case F2 : case V2 : case CR2: return 2;
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[llvm-commits] [llvm] r47073 - /llvm/trunk/docs/GettingStarted.html
Author: lattner Date: Wed Feb 13 11:50:24 2008 New Revision: 47073 URL: http://llvm.org/viewvc/llvm-project?rev=47073view=rev Log: gcc 3.2.3 is also bad. Modified: llvm/trunk/docs/GettingStarted.html Modified: llvm/trunk/docs/GettingStarted.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GettingStarted.html?rev=47073r1=47072r2=47073view=diff == --- llvm/trunk/docs/GettingStarted.html (original) +++ llvm/trunk/docs/GettingStarted.html Wed Feb 13 11:50:24 2008 @@ -510,7 +510,8 @@ problems in the STL that effectively prevent it from compiling LLVM. /p -pbGCC 3.2.2/b: This version of GCC fails to compile LLVM./p +pbGCC 3.2.2 and 3.2.3/b: These versions of GCC fails to compile LLVM with +a bogus template error. This was fixed in later GCCs./p pbGCC 3.3.2/b: This version of GCC suffered from a a href=http://gcc.gnu.org/PR13392;serious bug/a which causes it to crash in ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r47046 - in /llvm/trunk: include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/SimpleRegisterCoalescing.cpp lib/CodeGen/SimpleRegisterCoalescing.h
On Feb 13, 2008, at 1:47 AM, Evan Cheng wrote:
Very nice, does it also help shootout/fib?
bh speedup doesn't seem real. It doesn't help fib.
Ok, once things have settled, please take a look at the comments in
the bugzilla to see if there are other cases being missed.
This idiom happens a lot in the preexisting code. Please use:
VNInfo *AValNo = IntA.FindLiveRangeContaining(CopyIdx-1)-valno;
ALR is also used below.
Ok!
+ for (unsigned i = 0, e = DefMI-getNumOperands(); i != e; ++i) {
This loop needs a comment. What are you trying to find with this
loop? Maybe it should be moved out to its own function which just
returns idx? This would force you to name it, which would describe
what it does :)
There is a reason I said initial in the commit message. This is not
done. I need a target hook to tell me what is the new destination
register after commuting. Right now this is basically assuming x86
commutable instructions: A = A + B
Ok.
Another random question unrelated to this code: now that we have
efficient RAUW, can we eliminate the 'rep' mapping stuff and just
RAUW vregs as they are coallesced?
Well, actually it's related. I think it's required for correctness.
See below.
Ah, I see. Well this seems like an independently useful change that
will both speed up and simplify coalescing. Are you interested in
tackling it as part of this project?
Yay for use_iterators :)
Except I don't think this is quite right. Iterating through uses of
IntA.reg means we end up not updating other uses that have already
been coalesced to it.
Yeah, that's bad.
Where the use iterator could point to the first r2, and incrementing
it could point to the next r2. This could be avoided by not zapping
instructions in this loop: move the copy zapping to a walk over a
smallset or something.
Nothing is being zapped in the loop. Copies that would be zapped are
put into a set JoinedCopies. In fact, all uses have to be updated to
the new register.
Ok.
It isn't clear to me what this code is doing. It looks like it is
looking for the copy that has now becomes an identity copy. Is there
some way to factor this with other code that is coallescing copies
away? It seems duplicated from somewhere else. It would be nicer to
Not really. A number of things are happening here. We are trying to
determine which copies are now identity copies and make sure their
valno# will be eliminated. We also need to transfer the live ranges
defined by the (now dead) copies to the new val# defined by the
commuted definition MI. It's also tracking kill information.
Ok, please comment it a bit better. Is there any way to avoid this
work or factor this out into functions that can be shared with other
code?
just add all copies to a small vector and then zap them later or
something, to keep the logic simple.
That's essentially what's happening. This has gone through a number of
iterations already. Apart from some cosmetic changes, it's not going
to get much simpler than this.
ok.
Does this need to be an ivar? Can it just be passed by-ref between
the methods that need it?
This will be cleaned up later as part of RAUW change.
Ok. Thanks Evan!
-Chris
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Re: [llvm-commits] [llvm] r47048 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Does this mean some of the custom lowering in X86ISelLowering.cpp can
be eliminated?
Thanks,
Evan
On Feb 12, 2008, at 10:43 PM, Nate Begeman wrote:
Author: sampo
Date: Wed Feb 13 00:43:04 2008
New Revision: 47048
URL: http://llvm.org/viewvc/llvm-project?rev=47048view=rev
Log:
Support legalizing insert_vector_elt on targets where the element
type is not legal.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=47048r1=47047r2=47048view=diff
=
=
=
=
=
=
=
=
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Feb 13
00:43:04 2008
@@ -1263,8 +1263,16 @@
break;
case ISD::INSERT_VECTOR_ELT:
Tmp1 = LegalizeOp(Node-getOperand(0)); // InVec
-Tmp2 = LegalizeOp(Node-getOperand(1)); // InVal
Tmp3 = LegalizeOp(Node-getOperand(2)); // InEltNo
+
+// The type of the value to insert may not be legal, even
though the vector
+// type is legal. Legalize/Promote accordingly. We do not
handle Expand
+// here.
+switch (getTypeAction(Node-getOperand(1).getValueType())) {
+default: assert(0 Cannot expand insert element operand);
+case Legal: Tmp2 = LegalizeOp(Node-getOperand(1)); break;
+case Promote: Tmp2 = PromoteOp(Node-getOperand(1)); break;
+}
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
@@ -1283,30 +1291,35 @@
// If the insert index is a constant, codegen this as a
scalar_to_vector,
// then a shuffle that inserts it into the right position in
the vector.
if (ConstantSDNode *InsertPos =
dyn_castConstantSDNode(Tmp3)) {
-SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
- Tmp1.getValueType(), Tmp2);
-
-unsigned NumElts =
MVT::getVectorNumElements(Tmp1.getValueType());
-MVT::ValueType ShufMaskVT =
MVT::getIntVectorWithNumElements(NumElts);
-MVT::ValueType ShufMaskEltVT =
MVT::getVectorElementType(ShufMaskVT);
-
-// We generate a shuffle of InVec and ScVec, so the shuffle
mask should
-// be 0,1,2,3,4,5... with the appropriate element replaced
with elt 0 of
-// the RHS.
-SmallVectorSDOperand, 8 ShufOps;
-for (unsigned i = 0; i != NumElts; ++i) {
- if (i != InsertPos-getValue())
-ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
- else
-ShufOps.push_back(DAG.getConstant(NumElts,
ShufMaskEltVT));
+// SCALAR_TO_VECTOR requires that the type of the value
being inserted
+// match the element type of the vector being created.
+if (Tmp2.getValueType() ==
+MVT::getVectorElementType(Op.getValueType())) {
+ SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
+Tmp1.getValueType(), Tmp2);
+
+ unsigned NumElts =
MVT::getVectorNumElements(Tmp1.getValueType());
+ MVT::ValueType ShufMaskVT =
MVT::getIntVectorWithNumElements(NumElts);
+ MVT::ValueType ShufMaskEltVT =
MVT::getVectorElementType(ShufMaskVT);
+
+ // We generate a shuffle of InVec and ScVec, so the
shuffle mask
+ // should be 0,1,2,3,4,5... with the appropriate element
replaced with
+ // elt 0 of the RHS.
+ SmallVectorSDOperand, 8 ShufOps;
+ for (unsigned i = 0; i != NumElts; ++i) {
+if (i != InsertPos-getValue())
+ ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
+else
+ ShufOps.push_back(DAG.getConstant(NumElts,
ShufMaskEltVT));
+ }
+ SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR,
ShufMaskVT,
+ ShufOps[0],
ShufOps.size());
+
+ Result = DAG.getNode(ISD::VECTOR_SHUFFLE,
Tmp1.getValueType(),
+ Tmp1, ScVec, ShufMask);
+ Result = LegalizeOp(Result);
+ break;
}
-SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR,
ShufMaskVT,
- ShufOps[0],
ShufOps.size());
-
-Result = DAG.getNode(ISD::VECTOR_SHUFFLE,
Tmp1.getValueType(),
- Tmp1, ScVec, ShufMask);
-Result = LegalizeOp(Result);
-break;
}
// If the target doesn't support this, we have to spill the
input vector
@@ -1316,7 +1329,7 @@
// permute it into place, if the idx is a constant and if the
idx is
// supported by the target.
MVT::ValueType VT=
Re: [llvm-commits] [llvm] r47046 - in /llvm/trunk: include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/SimpleRegisterCoalescing.cpp lib/CodeGen/SimpleRegisterCoalescing.h
On Feb 13, 2008, at 9:31 AM, Chris Lattner wrote:
On Feb 13, 2008, at 1:47 AM, Evan Cheng wrote:
Very nice, does it also help shootout/fib?
bh speedup doesn't seem real. It doesn't help fib.
Ok, once things have settled, please take a look at the comments in
the bugzilla to see if there are other cases being missed.
This idiom happens a lot in the preexisting code. Please use:
VNInfo *AValNo = IntA.FindLiveRangeContaining(CopyIdx-1)-valno;
ALR is also used below.
Ok!
+ for (unsigned i = 0, e = DefMI-getNumOperands(); i != e; ++i) {
This loop needs a comment. What are you trying to find with this
loop? Maybe it should be moved out to its own function which just
returns idx? This would force you to name it, which would describe
what it does :)
There is a reason I said initial in the commit message. This is not
done. I need a target hook to tell me what is the new destination
register after commuting. Right now this is basically assuming x86
commutable instructions: A = A + B
Ok.
Another random question unrelated to this code: now that we have
efficient RAUW, can we eliminate the 'rep' mapping stuff and just
RAUW vregs as they are coallesced?
Well, actually it's related. I think it's required for correctness.
See below.
Ah, I see. Well this seems like an independently useful change that
will both speed up and simplify coalescing. Are you interested in
tackling it as part of this project?
That's the plan. Without RAUW change, I can't enable this optimization.
It's *shouldn't* take long.
Evan
Yay for use_iterators :)
Except I don't think this is quite right. Iterating through uses of
IntA.reg means we end up not updating other uses that have already
been coalesced to it.
Yeah, that's bad.
Where the use iterator could point to the first r2, and incrementing
it could point to the next r2. This could be avoided by not zapping
instructions in this loop: move the copy zapping to a walk over a
smallset or something.
Nothing is being zapped in the loop. Copies that would be zapped are
put into a set JoinedCopies. In fact, all uses have to be updated to
the new register.
Ok.
It isn't clear to me what this code is doing. It looks like it is
looking for the copy that has now becomes an identity copy. Is
there
some way to factor this with other code that is coallescing copies
away? It seems duplicated from somewhere else. It would be nicer
to
Not really. A number of things are happening here. We are trying to
determine which copies are now identity copies and make sure their
valno# will be eliminated. We also need to transfer the live ranges
defined by the (now dead) copies to the new val# defined by the
commuted definition MI. It's also tracking kill information.
Ok, please comment it a bit better. Is there any way to avoid this
work or factor this out into functions that can be shared with other
code?
just add all copies to a small vector and then zap them later or
something, to keep the logic simple.
That's essentially what's happening. This has gone through a number
of
iterations already. Apart from some cosmetic changes, it's not going
to get much simpler than this.
ok.
Does this need to be an ivar? Can it just be passed by-ref between
the methods that need it?
This will be cleaned up later as part of RAUW change.
Ok. Thanks Evan!
-Chris
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[llvm-commits] [llvm-gcc-4.2] r47077 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Author: johannes
Date: Wed Feb 13 12:36:09 2008
New Revision: 47077
URL: http://llvm.org/viewvc/llvm-project?rev=47077view=rev
Log:
Don't omit copying of PaddingElements; this causes
wrong code when structs are identical except that
one has padding in the same place another has a
real field. Look at the right node when looking
for MODIFY under RET.
Modified:
llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47077r1=47076r2=47077view=diff
==
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Feb 13 12:36:09 2008
@@ -1246,8 +1246,6 @@
const StructLayout *SL = getTargetData().getStructLayout(STy);
Constant *Zero = ConstantInt::get(Type::Int32Ty, 0);
for (unsigned i = 0, e = STy-getNumElements(); i != e; ++i) {
- if (isPaddingElement(STy, i))
-continue;
Constant *Idx = ConstantInt::get(Type::Int32Ty, i);
Value *Idxs[2] = { Zero, Idx };
Value *DElPtr = Builder.CreateGEP(DestLoc.Ptr, Idxs, Idxs + 2, tmp);
@@ -1721,7 +1719,8 @@
// operand is an aggregate value, create a temporary to evaluate it into.
MemRef DestLoc;
const Type *DestTy = ConvertType(TREE_TYPE(TREE_OPERAND(exp, 0)));
-if (!DestTy-isFirstClassType() TREE_CODE(exp) != MODIFY_EXPR)
+if (!DestTy-isFirstClassType()
+TREE_CODE(TREE_OPERAND(exp, 0)) != MODIFY_EXPR)
DestLoc = CreateTempLoc(DestTy);
Emit(TREE_OPERAND(exp, 0), DestLoc.Ptr ? DestLoc : NULL);
}
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[llvm-commits] [llvm] r47075 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeTypes.h lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp test/CodeGen/
Author: baldrick Date: Wed Feb 13 12:01:53 2008 New Revision: 47075 URL: http://llvm.org/viewvc/llvm-project?rev=47075view=rev Log: Teach LegalizeTypes how to expand and promote CTLZ, CTTZ and CTPOP. The expansion code differs from that in LegalizeDAG in that it chooses to take the CTLZ/CTTZ count from the Hi/Lo part depending on whether the Hi/Lo value is zero, not on whether CTLZ/CTTZ of Hi/Lo returned 32 (or whatever the width of the type is) for it. I made this change because the optimizers may well know that Hi/Lo is zero and exploit it. The promotion code for CTTZ also differs from that in LegalizeDAG: it uses an or to get the right result when the original value is zero, rather than using a compare and select. This also means the value doesn't need to be zero extended. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp llvm/trunk/test/CodeGen/Generic/2008-02-04-Ctlz.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=47075r1=47074r2=47075view=diff == --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Wed Feb 13 12:01:53 2008 @@ -159,23 +159,26 @@ // Result Promotion. void PromoteResult(SDNode *N, unsigned ResNo); - SDOperand PromoteResult_UNDEF(SDNode *N); SDOperand PromoteResult_Constant(SDNode *N); - SDOperand PromoteResult_TRUNCATE(SDNode *N); - SDOperand PromoteResult_INT_EXTEND(SDNode *N); + SDOperand PromoteResult_CTLZ(SDNode *N); + SDOperand PromoteResult_CTPOP(SDNode *N); + SDOperand PromoteResult_CTTZ(SDNode *N); SDOperand PromoteResult_FP_ROUND(SDNode *N); SDOperand PromoteResult_FP_TO_XINT(SDNode *N); - SDOperand PromoteResult_SETCC(SDNode *N); + SDOperand PromoteResult_INT_EXTEND(SDNode *N); SDOperand PromoteResult_LOAD(LoadSDNode *N); - SDOperand PromoteResult_SimpleIntBinOp(SDNode *N); SDOperand PromoteResult_SDIV(SDNode *N); - SDOperand PromoteResult_UDIV(SDNode *N); + SDOperand PromoteResult_SELECT (SDNode *N); + SDOperand PromoteResult_SELECT_CC(SDNode *N); + SDOperand PromoteResult_SETCC(SDNode *N); SDOperand PromoteResult_SHL(SDNode *N); + SDOperand PromoteResult_SimpleIntBinOp(SDNode *N); SDOperand PromoteResult_SRA(SDNode *N); SDOperand PromoteResult_SRL(SDNode *N); - SDOperand PromoteResult_SELECT (SDNode *N); - SDOperand PromoteResult_SELECT_CC(SDNode *N); - + SDOperand PromoteResult_TRUNCATE(SDNode *N); + SDOperand PromoteResult_UDIV(SDNode *N); + SDOperand PromoteResult_UNDEF(SDNode *N); + // Operand Promotion. bool PromoteOperand(SDNode *N, unsigned OperandNo); SDOperand PromoteOperand_ANY_EXTEND(SDNode *N); @@ -202,18 +205,21 @@ // Result Expansion. void ExpandResult(SDNode *N, unsigned ResNo); - void ExpandResult_UNDEF (SDNode *N, SDOperand Lo, SDOperand Hi); - void ExpandResult_Constant (SDNode *N, SDOperand Lo, SDOperand Hi); - void ExpandResult_BUILD_PAIR (SDNode *N, SDOperand Lo, SDOperand Hi); - void ExpandResult_MERGE_VALUES(SDNode *N, SDOperand Lo, SDOperand Hi); void ExpandResult_ANY_EXTEND (SDNode *N, SDOperand Lo, SDOperand Hi); - void ExpandResult_ZERO_EXTEND(SDNode *N, SDOperand Lo, SDOperand Hi); - void ExpandResult_SIGN_EXTEND(SDNode *N, SDOperand Lo, SDOperand Hi); void ExpandResult_AssertZext (SDNode *N, SDOperand Lo, SDOperand Hi); - void ExpandResult_TRUNCATE (SDNode *N, SDOperand Lo, SDOperand Hi); void ExpandResult_BIT_CONVERT(SDNode *N, SDOperand Lo, SDOperand Hi); - void ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand Lo, SDOperand Hi); + void ExpandResult_BUILD_PAIR (SDNode *N, SDOperand Lo, SDOperand Hi); + void ExpandResult_Constant (SDNode *N, SDOperand Lo, SDOperand Hi); + void ExpandResult_CTLZ (SDNode *N, SDOperand Lo, SDOperand Hi); + void ExpandResult_CTPOP (SDNode *N, SDOperand Lo, SDOperand Hi); + void ExpandResult_CTTZ (SDNode *N, SDOperand Lo, SDOperand Hi); void ExpandResult_LOAD (LoadSDNode *N, SDOperand Lo, SDOperand Hi); + void ExpandResult_MERGE_VALUES(SDNode *N, SDOperand Lo, SDOperand Hi); + void ExpandResult_SIGN_EXTEND(SDNode *N, SDOperand Lo, SDOperand Hi); + void ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand Lo, SDOperand Hi); + void ExpandResult_TRUNCATE (SDNode *N, SDOperand Lo, SDOperand Hi); + void ExpandResult_UNDEF (SDNode *N, SDOperand Lo, SDOperand Hi); + void ExpandResult_ZERO_EXTEND(SDNode *N, SDOperand Lo, SDOperand Hi); void ExpandResult_Logical(SDNode *N, SDOperand Lo, SDOperand Hi); void ExpandResult_BSWAP (SDNode *N, SDOperand Lo, SDOperand Hi); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp URL:
[llvm-commits] [llvm] r47078 - /llvm/trunk/test/C++Frontend/2008-02-13-sret.cpp
Author: johannes
Date: Wed Feb 13 12:36:48 2008
New Revision: 47078
URL: http://llvm.org/viewvc/llvm-project?rev=47078view=rev
Log:
New test, see comments.
Added:
llvm/trunk/test/C++Frontend/2008-02-13-sret.cpp
Added: llvm/trunk/test/C++Frontend/2008-02-13-sret.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/C%2B%2BFrontend/2008-02-13-sret.cpp?rev=47078view=auto
==
--- llvm/trunk/test/C++Frontend/2008-02-13-sret.cpp (added)
+++ llvm/trunk/test/C++Frontend/2008-02-13-sret.cpp Wed Feb 13 12:36:48 2008
@@ -0,0 +1,48 @@
+// RUN: %llvmgxx -S -O0 -emit-llvm %s -o - | grep retval | grep S242 | grep
{i32 1} | count 2
+
+// Test that all 8 bytes of ret in check242 are copied. llvm-gcc was
+// treating S242 as if it were S93, which does not need to have the
+// last 4 padding bytes copied.
+typedef __builtin_va_list va_list;
+typedef unsigned long size_t;
+void *memset(void *, int, size_t);
+struct S92 { int a:14; } ;
+ extern struct S92 s92;
+
+ struct S92 check92 () { struct S92 ret;
+ memset (ret, 0, sizeof (ret));
+ ret.a = s92.a;
+ return ret; }
+
+struct S93 { __attribute__((aligned (8))) void * a; } ;
+ extern struct S93 s93;
+ struct S93 check93 () {
+ struct S93 ret;
+ memset (ret, 0, sizeof (ret));
+ ret.a = s93.a;
+ return ret; }
+
+struct S242 { char * a;int b[1]; } ;
+ extern struct S242 s242;
+
+ struct S242 check242 () {
+ struct S242 ret;
+ memset (ret, 0, sizeof (ret));
+ ret.a = s242.a;
+ ret.b[0] = s242.b[0];
+ return ret; }
+
+void check93va (int z, ...) {
+ struct S93 arg;
+ va_list ap;
+ __builtin_va_start(ap,z);
+ arg = __builtin_va_arg(ap,struct S93);
+ __builtin_va_end(ap); }
+
+void check242va (int z, ...) {
+struct S242 arg;
+va_list ap;
+__builtin_va_start(ap,z);
+ arg = __builtin_va_arg(ap,struct S242);
+ __builtin_va_end(ap); }
+
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[llvm-commits] [llvm] r47079 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/ExecutionEngine/ lib/CodeGen/ lib/ExecutionEngine/ lib/ExecutionEngine/JIT/ lib/Target/PowerPC/ lib/Target/X86/
Author: geoffray
Date: Wed Feb 13 12:39:37 2008
New Revision: 47079
URL: http://llvm.org/viewvc/llvm-project?rev=47079view=rev
Log:
Enable exception handling int JIT
Added:
llvm/trunk/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp
llvm/trunk/lib/ExecutionEngine/JIT/JITDwarfEmitter.h
Modified:
llvm/trunk/include/llvm/CodeGen/MachineCodeEmitter.h
llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h
llvm/trunk/include/llvm/ExecutionEngine/JITMemoryManager.h
llvm/trunk/lib/CodeGen/ELFWriter.cpp
llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
llvm/trunk/lib/CodeGen/MachOWriter.cpp
llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp
llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp
llvm/trunk/lib/ExecutionEngine/JIT/JITMemoryManager.cpp
llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp
llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
Modified: llvm/trunk/include/llvm/CodeGen/MachineCodeEmitter.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineCodeEmitter.h?rev=47079r1=47078r2=47079view=diff
==
--- llvm/trunk/include/llvm/CodeGen/MachineCodeEmitter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineCodeEmitter.h Wed Feb 13 12:39:37
2008
@@ -26,6 +26,7 @@
class MachineConstantPool;
class MachineJumpTableInfo;
class MachineFunction;
+class MachineModuleInfo;
class MachineRelocation;
class Value;
class GlobalValue;
@@ -136,6 +137,72 @@
CurBufferPtr = BufferEnd;
}
+
+ /// emitULEB128Bytes - This callback is invoked when a ULEB128 needs to be
+ /// written to the output stream.
+ void emitULEB128Bytes(unsigned Value) {
+do {
+ unsigned char Byte = Value 0x7f;
+ Value = 7;
+ if (Value) Byte |= 0x80;
+ emitByte(Byte);
+} while (Value);
+ }
+
+ /// emitSLEB128Bytes - This callback is invoked when a SLEB128 needs to be
+ /// written to the output stream.
+ void emitSLEB128Bytes(int Value) {
+int Sign = Value (8 * sizeof(Value) - 1);
+bool IsMore;
+
+do {
+ unsigned char Byte = Value 0x7f;
+ Value = 7;
+ IsMore = Value != Sign || ((Byte ^ Sign) 0x40) != 0;
+ if (IsMore) Byte |= 0x80;
+ emitByte(Byte);
+} while (IsMore);
+ }
+
+ /// emitString - This callback is invoked when a String needs to be
+ /// written to the output stream.
+ void emitString(const std::string String) {
+for (unsigned i = 0, N = String.size(); i N; ++i) {
+ unsigned char C = String[i];
+ emitByte(C);
+}
+emitByte(0);
+ }
+
+ /// emitInt32 - Emit a int32 directive.
+ void emitInt32(int Value) {
+if (CurBufferPtr+4 = BufferEnd) {
+ *((uint32_t*)CurBufferPtr) = Value;
+ CurBufferPtr += 4;
+} else {
+ CurBufferPtr = BufferEnd;
+}
+ }
+
+ /// emitInt64 - Emit a int64 directive.
+ void emitInt64(uint64_t Value) {
+if (CurBufferPtr+8 = BufferEnd) {
+ *((uint64_t*)CurBufferPtr) = Value;
+ CurBufferPtr += 8;
+} else {
+ CurBufferPtr = BufferEnd;
+}
+ }
+
+ /// emitAt - Emit Value in Addr
+ void emitAt(uintptr_t *Addr, uintptr_t Value) {
+if (Addr = (uintptr_t*)BufferBegin Addr (uintptr_t*)BufferEnd)
+ (*Addr) = Value;
+ }
+
+ /// emitLabel - Emits a label
+ virtual void emitLabel(uint64_t LabelID) = 0;
+
/// allocateSpace - Allocate a block of space in the current output buffer,
/// returning null (and setting conditions to indicate buffer overflow) on
/// failure. Alignment is the alignment in bytes of the buffer desired.
@@ -194,6 +261,15 @@
/// emitted.
///
virtual intptr_t getMachineBasicBlockAddress(MachineBasicBlock *MBB) const=
0;
+
+ /// getLabelAddress - Return the address of the specified LabelID, only
usable
+ /// after the LabelID has been emitted.
+ ///
+ virtual intptr_t getLabelAddress(uint64_t LabelID) const = 0;
+
+ /// Specifies the MachineModuleInfo object. This is used for exception
handling
+ /// purposes.
+ virtual void setModuleInfo(MachineModuleInfo* Info) = 0;
};
} // End llvm namespace
Modified: llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h?rev=47079r1=47078r2=47079view=diff
==
--- llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h (original)
+++ llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h Wed Feb 13
12:39:37 2008
@@ -85,6 +85,11 @@
/// pointer is invoked to create it. If this returns null, the JIT will
abort.
void* (*LazyFunctionCreator)(const std::string );
+ /// ExceptionTableRegister - If Exception Handling is set, the JIT will
+ /// register dwarf tables with this function
+ typedef void (*EERegisterFn)(void*);
+ static EERegisterFn ExceptionTableRegister;
+
public:
/// lock - This lock is
Re: [llvm-commits] [llvm] r47045 - /llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
Thanks Chris, it works just fine now.
Chris Lattner wrote:
I don't know about darwin, but this breaks linux/ppc32 JIT (llc works
fine). On a simple test case:
define i32 @main(i32 %argc) {
entry:
%tmp2 = add i32 2, %argc
ret i32 %tmp2
}
Yep, this was broken on darwin as well. I just committed a fix which
makes it work for me, please verify.
-Chris
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Re: [llvm-commits] [llvm] r47054 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp test/CodeGen/X86/arg-cast.ll
Hi Chris, On Feb 12, 2008, at 11:39 PM, Chris Lattner wrote: URL: http://llvm.org/viewvc/llvm-project?rev=47054view=rev Log: In SDISel, for targets that support FORMAL_ARGUMENTS nodes, lower this node as soon as we create it in SDISel. Previously we would lower it in legalize. The problem with this is that it only exposes the argument loads implied by FORMAL_ARGUMENTs after legalize, so that only dag combine 2 can hack on them. This causes us to miss some optimizations because datatype expansion also happens here. Will this become redundant once LegalizeTypes is finished and DAGCombine can be run between it an legalizing operations? Dan ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc-4.2] r47081 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Author: johannes Date: Wed Feb 13 13:30:03 2008 New Revision: 47081 URL: http://llvm.org/viewvc/llvm-project?rev=47081view=rev Log: Whitespace change to have a place to put this comment, which belonged on 47077: Fixes t001 and t029 in struct-layout-1 in g++ testsuite. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47081r1=47080r2=47081view=diff == --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Feb 13 13:30:03 2008 @@ -1,4 +1,4 @@ -/* LLVM LOCAL begin (ENTIRE FILE!) */ +/* LLVM LOCAL begin (ENTIRE FILE!) */ /* High-level LLVM backend interface Copyright (C) 2005, 2006, 2007 Free Software Foundation, Inc. Contributed by Chris Lattner ([EMAIL PROTECTED]) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc-4.2] r47080 - in /llvm-gcc-4.2/trunk/gcc: common.opt llvm-backend.cpp
Author: dpatel
Date: Wed Feb 13 13:12:16 2008
New Revision: 47080
URL: http://llvm.org/viewvc/llvm-project?rev=47080view=rev
Log:
Add hook to dump .bc file before module level optimizer is run. This helps
investigate optimizer and code generator bugs which are not easily reproducible
using standalone 'opt' and 'llc' tools.
Modified:
llvm-gcc-4.2/trunk/gcc/common.opt
llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Modified: llvm-gcc-4.2/trunk/gcc/common.opt
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/common.opt?rev=47080r1=47079r2=47080view=diff
==
--- llvm-gcc-4.2/trunk/gcc/common.opt (original)
+++ llvm-gcc-4.2/trunk/gcc/common.opt Wed Feb 13 13:12:16 2008
@@ -233,6 +233,10 @@
fdebug-pass-arguments
Common Report Var(flag_debug_pass_arguments)
Print pass manager arguments
+
+fdebug-llvm-module-opt
+Common Report Var(flag_debug_llvm_module_opt)
+Help debug llvm module-level optimizer
; LLVM LOCAL end
; The version of the C++ ABI in use. The following values are allowed:
Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=47080r1=47079r2=47080view=diff
==
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Wed Feb 13 13:12:16 2008
@@ -79,6 +79,7 @@
TargetMachine *TheTarget = 0;
TypeConverter *TheTypeConverter = 0;
llvm::OStream *AsmOutFile = 0;
+llvm::OStream *AsmIntermediateOutFile = 0;
/// DisableLLVMOptimizations - Allow the user to specify:
/// -mllvm -disable-llvm-optzns on the llvm-gcc command line to force llvm
@@ -210,6 +211,7 @@
}
oFILEstream *AsmOutStream = 0;
+oFILEstream *AsmIntermediateOutStream = 0;
/// Read bytecode from PCH file. Initialize TheModule and setup
/// LTypes vector.
@@ -556,7 +558,31 @@
// Finish off the per-function pass.
if (PerFunctionPasses)
PerFunctionPasses-doFinalization();
+
+ // Emit intermediate .bc file before module level optimization passes are
run.
+ if (emit_llvm_bc flag_debug_llvm_module_opt) {
+static PassManager *IntermediatePM = new PassManager();
+IntermediatePM-add(new TargetData(*TheTarget-getTargetData()));
+
+ // Emit an LLVM .bc file to the output. This is used when passed
+ // -emit-llvm -c to the GCC driver.
+
+char asm_intermediate_out_filename[MAXPATHLEN];
+strcpy(asm_intermediate_out_filename[0], asm_file_name);
+strcat(asm_intermediate_out_filename[0],.0);
+FILE *asm_intermediate_out_file = fopen(asm_intermediate_out_filename,
w+b);
+AsmIntermediateOutStream = new oFILEstream(asm_intermediate_out_file);
+AsmIntermediateOutFile = new OStream(*AsmIntermediateOutStream);
+IntermediatePM-add(CreateBitcodeWriterPass(*AsmIntermediateOutStream));
+IntermediatePM-run(*TheModule);
+AsmIntermediateOutStream-flush();
+fflush(asm_intermediate_out_file);
+delete AsmIntermediateOutStream;
+AsmIntermediateOutStream = 0;
+delete AsmIntermediateOutFile;
+AsmIntermediateOutFile = 0;
+ }
// Run module-level optimizers, if any are present.
if (PerModulePasses)
PerModulePasses-run(*TheModule);
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[llvm-commits] [llvm] r47082 - in /llvm/trunk: lib/Transforms/Scalar/LoopIndexSplit.cpp test/Transforms/LoopIndexSplit/2008-02-13-ExitValueNum.ll
Author: dpatel
Date: Wed Feb 13 13:48:48 2008
New Revision: 47082
URL: http://llvm.org/viewvc/llvm-project?rev=47082view=rev
Log:
Keep track of exit value operand number when operands are swapped.
Added:
llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-13-ExitValueNum.ll
Modified:
llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp?rev=47082r1=47081r2=47082view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp Wed Feb 13 13:48:48 2008
@@ -1163,8 +1163,13 @@
if (ExitCondition-getPredicate() == ICmpInst::ICMP_SGT
|| ExitCondition-getPredicate() == ICmpInst::ICMP_UGT
|| ExitCondition-getPredicate() == ICmpInst::ICMP_SGE
- || ExitCondition-getPredicate() == ICmpInst::ICMP_UGE)
+ || ExitCondition-getPredicate() == ICmpInst::ICMP_UGE) {
ExitCondition-swapOperands();
+if (ExitValueNum)
+ ExitValueNum = 0;
+else
+ ExitValueNum = 1;
+ }
switch (ExitCondition-getPredicate()) {
case ICmpInst::ICMP_SGT:
Added: llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-13-ExitValueNum.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-13-ExitValueNum.ll?rev=47082view=auto
==
--- llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-13-ExitValueNum.ll (added)
+++ llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-13-ExitValueNum.ll Wed
Feb 13 13:48:48 2008
@@ -0,0 +1,67 @@
+; RUN: llvm-as %s | opt -disable-output -loop-index-split
+; PR 2011
+ %struct.CLAUSE_HELP = type { i32, i32, i32, i32, i32*, i32,
%struct.LIST_NODE*, %struct.LIST_NODE*, i32, i32, %struct.LITERAL_HELP**, i32,
i32, i32, i32 }
+ %struct.LIST_NODE = type { %struct.LIST_NODE*, i8* }
+ %struct.LITERAL_HELP = type { i32, i32, i32, %struct.CLAUSE_HELP*,
%struct.term* }
+ %struct.anon = type { %struct.LIST_NODE* }
+ %struct.st = type { %struct.subst*, %struct.LIST_NODE*,
%struct.LIST_NODE*, i16, i16 }
+ %struct.subst = type { %struct.subst*, i32, %struct.term* }
+ %struct.term = type { i32, %struct.anon, %struct.LIST_NODE*, i32, i32 }
+
+define fastcc %struct.LIST_NODE* @inf_HyperResolvents(%struct.CLAUSE_HELP*
%Clause, %struct.subst* %Subst, %struct.LIST_NODE* %Restlits, i32
%GlobalMaxVar, %struct.LIST_NODE* %FoundMap, i32 %StrictlyMaximal, {
%struct.st*, [3001 x %struct.term*], [4000 x %struct.term*], i32 }* %Index,
i32* %Flags, i32* %Precedence) nounwind {
+entry:
+ br i1 false, label %bb960, label %bb885
+
+bb885: ; preds = %entry
+ ret %struct.LIST_NODE* null
+
+bb960: ; preds = %entry
+ br i1 false, label %bb1097, label %bb1005.preheader
+
+bb1005.preheader: ; preds = %bb960
+ ret %struct.LIST_NODE* null
+
+bb1097:; preds = %bb960
+ br i1 false, label %bb1269.preheader, label %bb1141.preheader
+
+bb1141.preheader: ; preds = %bb1097
+ ret %struct.LIST_NODE* null
+
+bb1269.preheader: ; preds = %bb1097
+ br i1 false, label %bb1318, label %bb1281
+
+bb1281:; preds = %bb1269.preheader
+ ret %struct.LIST_NODE* null
+
+bb1318:; preds = %bb1269.preheader
+ br i1 false, label %bb1459, label %bb.nph52
+
+bb.nph52: ; preds = %bb1318
+ ret %struct.LIST_NODE* null
+
+bb1459:; preds = %bb1318
+ br i1 false, label %bb1553, label %bb.nph62
+
+bb.nph62: ; preds = %bb1459
+ ret %struct.LIST_NODE* null
+
+bb1553:; preds = %bb1669, %bb1459
+ %j295.0.reg2mem.0 = phi i32 [ %storemerge110, %bb1669 ], [ 0, %bb1459 ]
; i32 [#uses=2]
+ %tmp1629 = icmp sgt i32 %j295.0.reg2mem.0, 0; i1 [#uses=1]
+ br i1 %tmp1629, label %bb1649, label %bb1632
+
+bb1632:; preds = %bb1553
+ br label %bb1669
+
+bb1649:; preds = %bb1553
+ br label %bb1669
+
+bb1669:; preds = %bb1649, %bb1632
+ %storemerge110 = add i32 %j295.0.reg2mem.0, 1 ; i32
[#uses=2]
+ %tmp1672 = icmp sgt i32 %storemerge110, 0 ; i1 [#uses=1]
+ br i1 %tmp1672, label %bb1678, label %bb1553
+
+bb1678:; preds = %bb1669
+ ret %struct.LIST_NODE* null
+}
+
___
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Re: [llvm-commits] [llvm-gcc-4.2] r47080 - in /llvm-gcc-4.2/trunk/gcc: common.opt llvm-backend.cpp
Hi Devang, nice idea.
+ Â // Emit intermediate .bc file before module level optimization passes
are run. + Â if (emit_llvm_bc flag_debug_llvm_module_opt) {
Why condition this on emit_llvm_bc?
+static PassManager *IntermediatePM = new PassManager();
+IntermediatePM-add(new TargetData(*TheTarget-getTargetData()));
+
+ // Emit an LLVM .bc file to the output. This is used when passed
+ // -emit-llvm -c to the GCC driver.
This comment is not aligned properly. Also, it doesn't make much
sense: shouldn't it mention flag_debug_llvm_module_opt and not -c?
+AsmIntermediateOutFile = new OStream(*AsmIntermediateOutStream);
This doesn't seem to be used.
Best wishes,
Duncan.
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[llvm-commits] [llvm] r47084 - /llvm/trunk/include/llvm/Support/MathExtras.h
Author: djg
Date: Wed Feb 13 14:54:54 2008
New Revision: 47084
URL: http://llvm.org/viewvc/llvm-project?rev=47084view=rev
Log:
Add count{Leading,Trailing}Ones_{32,64} functions with simple implementations.
Modified:
llvm/trunk/include/llvm/Support/MathExtras.h
Modified: llvm/trunk/include/llvm/Support/MathExtras.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/MathExtras.h?rev=47084r1=47083r2=47084view=diff
==
--- llvm/trunk/include/llvm/Support/MathExtras.h (original)
+++ llvm/trunk/include/llvm/Support/MathExtras.h Wed Feb 13 14:54:54 2008
@@ -163,6 +163,14 @@
return Count;
}
+/// CountLeadingOnes_32 - this function performs the operation of
+/// counting the number of ones from the most significant bit to the first zero
+/// bit. Ex. CountLeadingOnes_32(0xFF0FFF00) == 8.
+/// Returns 32 if the word is all ones.
+inline unsigned CountLeadingOnes_32(uint32_t Value) {
+ return CountLeadingZeros_32(~Value);
+}
+
/// CountLeadingZeros_64 - This function performs the platform optimal form
/// of counting the number of zeros from the most significant bit to the first
/// one bit (64 bit edition.)
@@ -207,6 +215,14 @@
return Count;
}
+/// CountLeadingOnes_64 - This function performs the operation
+/// of counting the number of ones from the most significant bit to the first
+/// zero bit (64 bit edition.)
+/// Returns 64 if the word is all ones.
+inline unsigned CountLeadingOnes_64(uint64_t Value) {
+ return CountLeadingZeros_64(~Value);
+}
+
/// CountTrailingZeros_32 - this function performs the platform optimal form of
/// counting the number of zeros from the least significant bit to the first
one
/// bit. Ex. CountTrailingZeros_32(0xFF00FF00) == 8.
@@ -224,6 +240,14 @@
#endif
}
+/// CountTrailingOnes_32 - this function performs the operation of
+/// counting the number of ones from the least significant bit to the first
zero
+/// bit. Ex. CountTrailingOnes_32(0x00FF00FF) == 8.
+/// Returns 32 if the word is all ones.
+inline unsigned CountTrailingOnes_32(uint32_t Value) {
+ return CountTrailingZeros_32(~Value);
+}
+
/// CountTrailingZeros_64 - This function performs the platform optimal form
/// of counting the number of zeros from the least significant bit to the
first
/// one bit (64 bit edition.)
@@ -243,6 +267,14 @@
#endif
}
+/// CountTrailingOnes_64 - This function performs the operation
+/// of counting the number of ones from the least significant bit to the first
+/// zero bit (64 bit edition.)
+/// Returns 64 if the word is all ones.
+inline unsigned CountTrailingOnes_64(uint64_t Value) {
+ return CountTrailingZeros_64(~Value);
+}
+
/// CountPopulation_32 - this function counts the number of set bits in a
value.
/// Ex. CountPopulation(0xF000F000) = 8
/// Returns 0 if the word is zero.
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Re: [llvm-commits] [llvm-gcc-4.2] r47080 - in /llvm-gcc-4.2/trunk/gcc: common.opt llvm-backend.cpp
On Feb 13, 2008, at 11:52 AM, Duncan Sands wrote:
Hi Devang, nice idea.
+ // Emit intermediate .bc file before module level optimization
passes
are run. + if (emit_llvm_bc flag_debug_llvm_module_opt) {
Why condition this on emit_llvm_bc?
In the next patch I used emit_llvm_bc condition check to write bitcode
file and emit_llvm condition check to print llvm asm.
-
Devang
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[llvm-commits] [llvm-gcc-4.2] r47083 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Author: dpatel
Date: Wed Feb 13 14:47:35 2008
New Revision: 47083
URL: http://llvm.org/viewvc/llvm-project?rev=47083view=rev
Log:
Selectively print llvm asm file or write bit code file
as an intermediate file based on input command line options.
Modified:
llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=47083r1=47082r2=47083view=diff
==
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Wed Feb 13 14:47:35 2008
@@ -559,22 +559,22 @@
if (PerFunctionPasses)
PerFunctionPasses-doFinalization();
- // Emit intermediate .bc file before module level optimization passes are
run.
- if (emit_llvm_bc flag_debug_llvm_module_opt) {
+ // Emit intermediate file before module level optimization passes are run.
+ if (flag_debug_llvm_module_opt) {
static PassManager *IntermediatePM = new PassManager();
IntermediatePM-add(new TargetData(*TheTarget-getTargetData()));
- // Emit an LLVM .bc file to the output. This is used when passed
- // -emit-llvm -c to the GCC driver.
-
char asm_intermediate_out_filename[MAXPATHLEN];
strcpy(asm_intermediate_out_filename[0], asm_file_name);
strcat(asm_intermediate_out_filename[0],.0);
FILE *asm_intermediate_out_file = fopen(asm_intermediate_out_filename,
w+b);
AsmIntermediateOutStream = new oFILEstream(asm_intermediate_out_file);
AsmIntermediateOutFile = new OStream(*AsmIntermediateOutStream);
-IntermediatePM-add(CreateBitcodeWriterPass(*AsmIntermediateOutStream));
+if (emit_llvm_bc)
+ IntermediatePM-add(CreateBitcodeWriterPass(*AsmIntermediateOutStream));
+if (emit_llvm)
+ IntermediatePM-add(new PrintModulePass(AsmIntermediateOutFile));
IntermediatePM-run(*TheModule);
AsmIntermediateOutStream-flush();
fflush(asm_intermediate_out_file);
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[llvm-commits] [llvm] r47085 - /llvm/trunk/include/llvm/ADT/APInt.h
Author: djg
Date: Wed Feb 13 14:56:53 2008
New Revision: 47085
URL: http://llvm.org/viewvc/llvm-project?rev=47085view=rev
Log:
Fix a typo in a comment.
Modified:
llvm/trunk/include/llvm/ADT/APInt.h
Modified: llvm/trunk/include/llvm/ADT/APInt.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/APInt.h?rev=47085r1=47084r2=47085view=diff
==
--- llvm/trunk/include/llvm/ADT/APInt.h (original)
+++ llvm/trunk/include/llvm/ADT/APInt.h Wed Feb 13 14:56:53 2008
@@ -921,7 +921,7 @@
uint32_t countLeadingOnes() const;
/// countTrailingZeros - This function is an APInt version of the
- /// countTrailingZoers_{32,64} functions in MathExtras.h. It counts
+ /// countTrailingZeros_{32,64} functions in MathExtras.h. It counts
/// the number of zeros from the least significant bit to the first set bit.
/// @returns BitWidth if the value is zero.
/// @returns the number of zeros from the least significant bit to the first
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Re: [llvm-commits] [llvm] r47054 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp test/CodeGen/X86/arg-cast.ll
On Feb 13, 2008, at 10:16 AM, Dan Gohman wrote: Hi Chris, On Feb 12, 2008, at 11:39 PM, Chris Lattner wrote: URL: http://llvm.org/viewvc/llvm-project?rev=47054view=rev Log: In SDISel, for targets that support FORMAL_ARGUMENTS nodes, lower this node as soon as we create it in SDISel. Previously we would lower it in legalize. The problem with this is that it only exposes the argument loads implied by FORMAL_ARGUMENTs after legalize, so that only dag combine 2 can hack on them. This causes us to miss some optimizations because datatype expansion also happens here. Will this become redundant once LegalizeTypes is finished and DAGCombine can be run between it an legalizing operations? In this case, nope. The issue is that legalizedagtypes would expand the bitconvert on x86-32 because it is f64 - i64, and i64 isn't legal. -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r47046 - in /llvm/trunk: include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/SimpleRegisterCoalescing.cpp lib/CodeGen/SimpleRegisterCoalescing.h
On Feb 13, 2008, at 10:58 AM, Evan Cheng wrote: Ah, I see. Well this seems like an independently useful change that will both speed up and simplify coalescing. Are you interested in tackling it as part of this project? That's the plan. Without RAUW change, I can't enable this optimization. Awesome, thanks. It's *shouldn't* take long. *crosses fingers* :) -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47086 - in /llvm/trunk: include/llvm/ADT/APInt.h lib/Support/APInt.cpp
Author: djg
Date: Wed Feb 13 15:11:05 2008
New Revision: 47086
URL: http://llvm.org/viewvc/llvm-project?rev=47086view=rev
Log:
Add countTrailingOnes member functions to APInt.
Modified:
llvm/trunk/include/llvm/ADT/APInt.h
llvm/trunk/lib/Support/APInt.cpp
Modified: llvm/trunk/include/llvm/ADT/APInt.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/APInt.h?rev=47086r1=47085r2=47086view=diff
==
--- llvm/trunk/include/llvm/ADT/APInt.h (original)
+++ llvm/trunk/include/llvm/ADT/APInt.h Wed Feb 13 15:11:05 2008
@@ -913,8 +913,9 @@
/// one bits.
uint32_t countLeadingZeros() const;
- /// countLeadingOnes - This function counts the number of contiguous 1 bits
- /// in the high order bits. The count stops when the first 0 bit is reached.
+ /// countLeadingOnes - This function is an APInt version of the
+ /// countLeadingOnes_{32,64} functions in MathExtras.h. It counts the number
+ /// of ones from the most significant bit to the first zero bit.
/// @returns 0 if the high order bit is not set
/// @returns the number of 1 bits from the most significant to the least
/// @brief Count the number of leading one bits.
@@ -929,6 +930,15 @@
/// @brief Count the number of trailing zero bits.
uint32_t countTrailingZeros() const;
+ /// countTrailingOnes - This function is an APInt version of the
+ /// countTrailingOnes_{32,64} functions in MathExtras.h. It counts
+ /// the number of ones from the least significant bit to the first zero bit.
+ /// @returns BitWidth if the value is all ones.
+ /// @returns the number of ones from the least significant bit to the first
+ /// zero bit.
+ /// @brief Count the number of trailing one bits.
+ uint32_t countTrailingOnes() const;
+
/// countPopulation - This function is an APInt version of the
/// countPopulation_{32,64} functions in MathExtras.h. It counts the number
/// of 1 bits in the APInt value.
Modified: llvm/trunk/lib/Support/APInt.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/APInt.cpp?rev=47086r1=47085r2=47086view=diff
==
--- llvm/trunk/lib/Support/APInt.cpp (original)
+++ llvm/trunk/lib/Support/APInt.cpp Wed Feb 13 15:11:05 2008
@@ -813,6 +813,18 @@
return std::min(Count, BitWidth);
}
+uint32_t APInt::countTrailingOnes() const {
+ if (isSingleWord())
+return std::min(uint32_t(CountTrailingOnes_64(VAL)), BitWidth);
+ uint32_t Count = 0;
+ uint32_t i = 0;
+ for (; i getNumWords() pVal[i] == -1; ++i)
+Count += APINT_BITS_PER_WORD;
+ if (i getNumWords())
+Count += CountTrailingOnes_64(pVal[i]);
+ return std::min(Count, BitWidth);
+}
+
uint32_t APInt::countPopulation() const {
if (isSingleWord())
return CountPopulation_64(VAL);
___
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[llvm-commits] [poolalloc] r47092 - /poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
Author: criswell
Date: Wed Feb 13 16:22:22 2008
New Revision: 47092
URL: http://llvm.org/viewvc/llvm-project?rev=47092view=rev
Log:
Fix compilation when SAFECODE is defined.
Due to some strange errors when the C++ compiler tries to create a copy
constructor for struct FuncInfo, I cannot make ValueMap in struct FuncInfo a
DenseMap. I cannot change the DenseMap to a std::map either because the
CloneFunctionInto() function expects a DenseMap. For now, I have just copied
the data from the std::map into the DenseMap.
Modified:
poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
URL:
http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=47092r1=47091r2=47092view=diff
==
--- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Wed Feb 13 16:22:22 2008
@@ -410,10 +410,11 @@
// Map the existing arguments of the old function to the corresponding
// arguments of the new function, and copy over the names.
-#ifdef SAFECODE
- DenseMapconst Value*, Value* ValueMap = FI.ValueMap;
-#else
DenseMapconst Value*, Value* ValueMap;
+#ifdef SAFECODE
+ for (std::mapconst Value*, Value*::iterator I = FI.ValueMap.begin(),
+ E = FI.ValueMap.end(); I != E; ++I)
+ValueMap.insert(std::make_pair(I-first, I-second));
#endif
for (Function::arg_iterator I = F.arg_begin();
NI != New-arg_end(); ++I, ++NI) {
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[llvm-commits] [llvm] r47093 - in /llvm/trunk: lib/Transforms/Scalar/LoopIndexSplit.cpp test/Transforms/LoopIndexSplit/2008-02-13-LoopLatchPHI.ll
Author: dpatel
Date: Wed Feb 13 16:23:07 2008
New Revision: 47093
URL: http://llvm.org/viewvc/llvm-project?rev=47093view=rev
Log:
A loop latch phi node may have uses inside loop, not just in loop header.
Added:
llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-13-LoopLatchPHI.ll
Modified:
llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp?rev=47093r1=47092r2=47093view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp Wed Feb 13 16:23:07 2008
@@ -151,7 +151,7 @@
/// Update ExitBB PHINodes' to reflect this change.
void updatePHINodes(BasicBlock *ExitBB, BasicBlock *Latch,
BasicBlock *Header,
-PHINode *IV, Instruction *IVIncrement);
+PHINode *IV, Instruction *IVIncrement, Loop *LP);
/// moveExitCondition - Move exit condition EC into split condition block
CondBB.
void moveExitCondition(BasicBlock *CondBB, BasicBlock *ActiveBB,
@@ -1597,7 +1597,7 @@
new BranchInst(OrigDestBB, ExitingBB);
// Update PHINodes
- updatePHINodes(ExitBB, ExitingBB, CondBB, IV, IVAdd);
+ updatePHINodes(ExitBB, ExitingBB, CondBB, IV, IVAdd, LP);
// Fix dominator info.
// ExitBB is now dominated by CondBB
@@ -1637,7 +1637,8 @@
/// Update ExitBB PHINodes' to reflect this change.
void LoopIndexSplit::updatePHINodes(BasicBlock *ExitBB, BasicBlock *Latch,
BasicBlock *Header,
-PHINode *IV, Instruction *IVIncrement) {
+PHINode *IV, Instruction *IVIncrement,
+Loop *LP) {
for (BasicBlock::iterator BI = ExitBB-begin(), BE = ExitBB-end();
BI != BE; ++BI) {
@@ -1653,7 +1654,7 @@
for (Value::use_iterator UI = PHV-use_begin(), E = PHV-use_end();
UI != E; ++UI)
if (PHINode *U = dyn_castPHINode(*UI))
- if (U-getParent() == Header) {
+ if (LP-contains(U-getParent())) {
NewV = U;
break;
}
Added: llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-13-LoopLatchPHI.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-13-LoopLatchPHI.ll?rev=47093view=auto
==
--- llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-13-LoopLatchPHI.ll (added)
+++ llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-13-LoopLatchPHI.ll Wed
Feb 13 16:23:07 2008
@@ -0,0 +1,74 @@
+; RUN: llvm-as %s | opt -loop-index-split -disable-output
+; PR 2011
+ %struct.CLAUSE_HELP = type { i32, i32, i32, i32, i32*, i32,
%struct.LIST_NODE*, %struct.LIST_NODE*, i32, i32, %struct.LITERAL_HELP**, i32,
i32, i32, i32 }
+ %struct.LIST_NODE = type { %struct.LIST_NODE*, i8* }
+ %struct.LITERAL_HELP = type { i32, i32, i32, %struct.CLAUSE_HELP*,
%struct.term* }
+ %struct.anon = type { %struct.LIST_NODE* }
+ %struct.st = type { %struct.subst*, %struct.LIST_NODE*,
%struct.LIST_NODE*, i16, i16 }
+ %struct.subst = type { %struct.subst*, i32, %struct.term* }
+ %struct.term = type { i32, %struct.anon, %struct.LIST_NODE*, i32, i32 }
+
+define fastcc %struct.LIST_NODE* @inf_HyperResolvents(%struct.CLAUSE_HELP*
%Clause, %struct.subst* %Subst, %struct.LIST_NODE* %Restlits, i32
%GlobalMaxVar, %struct.LIST_NODE* %FoundMap, i32 %StrictlyMaximal, {
%struct.st*, [3001 x %struct.term*], [4000 x %struct.term*], i32 }* %Index,
i32* %Flags, i32* %Precedence) nounwind {
+entry:
+ br i1 false, label %bb960, label %bb885
+
+bb885: ; preds = %entry
+ ret %struct.LIST_NODE* null
+
+bb960: ; preds = %entry
+ br i1 false, label %bb1097, label %bb1005.preheader
+
+bb1005.preheader: ; preds = %bb960
+ ret %struct.LIST_NODE* null
+
+bb1097:; preds = %bb960
+ br i1 false, label %bb1269.preheader, label %bb1141.preheader
+
+bb1141.preheader: ; preds = %bb1097
+ ret %struct.LIST_NODE* null
+
+bb1269.preheader: ; preds = %bb1097
+ br i1 false, label %bb1318, label %bb1281
+
+bb1281:; preds = %bb1269.preheader
+ ret %struct.LIST_NODE* null
+
+bb1318:; preds = %bb1269.preheader
+ br i1 false, label %bb1459, label %bb.nph52
+
+bb.nph52: ; preds = %bb1318
+ ret %struct.LIST_NODE* null
+
+bb1459:; preds = %bb1318
+ br i1 false, label %bb1553, label %bb.nph62
+
+bb.nph62: ; preds = %bb1459
+ ret %struct.LIST_NODE* null
+
+bb1553:; preds = %bb1669, %bb1459
+
[llvm-commits] [poolalloc] r47094 - in /poolalloc/trunk: autoconf/aclocal.m4 autoconf/configure.ac configure
Author: criswell
Date: Wed Feb 13 16:23:55 2008
New Revision: 47094
URL: http://llvm.org/viewvc/llvm-project?rev=47094view=rev
Log:
Added the --with-safecodeobj option to configure the location of SAFECode's
object tree.
Fixed Makefiles so that they can now enable SAFECode builds properly.
Modified:
poolalloc/trunk/autoconf/aclocal.m4
poolalloc/trunk/autoconf/configure.ac
poolalloc/trunk/configure
Modified: poolalloc/trunk/autoconf/aclocal.m4
URL:
http://llvm.org/viewvc/llvm-project/poolalloc/trunk/autoconf/aclocal.m4?rev=47094r1=47093r2=47094view=diff
==
--- poolalloc/trunk/autoconf/aclocal.m4 (original)
+++ poolalloc/trunk/autoconf/aclocal.m4 Wed Feb 13 16:23:55 2008
@@ -1,7 +1,7 @@
-# generated automatically by aclocal 1.9.2 -*- Autoconf -*-
+# generated automatically by aclocal 1.9.6 -*- Autoconf -*-
-# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
-# Free Software Foundation, Inc.
+# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
+# 2005 Free Software Foundation, Inc.
# This file is free software; the Free Software Foundation
# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.
Modified: poolalloc/trunk/autoconf/configure.ac
URL:
http://llvm.org/viewvc/llvm-project/poolalloc/trunk/autoconf/configure.ac?rev=47094r1=47093r2=47094view=diff
==
--- poolalloc/trunk/autoconf/configure.ac (original)
+++ poolalloc/trunk/autoconf/configure.ac Wed Feb 13 16:23:55 2008
@@ -91,7 +91,8 @@
dnl **
dnl Location of SAFECode
-AC_ARG_WITH(safecodesrc,AS_HELP_STRING(--with-safecode,Location of SAFECode
Source Code),AC_SUBST(SAFECODESRC,[$withval]),AC_SUBST(SAFECODESRC,[`cd
../safecode; pwd`]))
+AC_ARG_WITH(safecodesrc,AS_HELP_STRING(--with-safecodesrc,Location of SAFECode
Source Code),AC_SUBST(SAFECODESRC,[$withval]),AC_SUBST(SAFECODESRC,[`cd
../safecode; pwd`]))
+AC_ARG_WITH(safecodeobj,AS_HELP_STRING(--with-safecodeobj,Location of SAFECode
Object Code),AC_SUBST(SAFECODEOBJ,[$withval]),AC_SUBST(SAFECODEOBJ,[`cd
../safecode; pwd`]))
dnl **
dnl * Create the output files
Modified: poolalloc/trunk/configure
URL:
http://llvm.org/viewvc/llvm-project/poolalloc/trunk/configure?rev=47094r1=47093r2=47094view=diff
==
--- poolalloc/trunk/configure (original)
+++ poolalloc/trunk/configure Wed Feb 13 16:23:55 2008
@@ -311,7 +311,7 @@
# include unistd.h
#endif
-ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME
PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix
program_transform_name bindir sbindir libexecdir datadir sysconfdir
sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir
build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS LLVM_SRC
LLVM_OBJ CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT CPP EGREP MMAP_FILE
SAFECODESRC LIBOBJS LTLIBOBJS'
+ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME
PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix
program_transform_name bindir sbindir libexecdir datadir sysconfdir
sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir
build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS LLVM_SRC
LLVM_OBJ CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT CPP EGREP MMAP_FILE
SAFECODESRC SAFECODEOBJ LIBOBJS LTLIBOBJS'
ac_subst_files=''
# Initialize some variables set by options.
@@ -854,7 +854,8 @@
--without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no)
--with-llvmsrc Location of LLVM Source Code
--with-llvmobj Location of LLVM Object Code
- --with-safecode Location of SAFECode Source Code
+ --with-safecodesrc Location of SAFECode Source Code
+ --with-safecodeobj Location of SAFECode Object Code
Some influential environment variables:
CC C compiler command
@@ -3675,6 +3676,16 @@
fi;
+# Check whether --with-safecodeobj or --without-safecodeobj was given.
+if test ${with_safecodeobj+set} = set; then
+ withval=$with_safecodeobj
+ SAFECODEOBJ=$withval
+
+else
+ SAFECODEOBJ=`cd ../safecode; pwd`
+
+fi;
+
ac_config_headers=$ac_config_headers
include/poolalloc/Config/config.h
@@ -4320,6 +4331,7 @@
s,@EGREP@,$EGREP,;t t
s,@MMAP_FILE@,$MMAP_FILE,;t t
s,@SAFECODESRC@,$SAFECODESRC,;t t
+s,@SAFECODEOBJ@,$SAFECODEOBJ,;t t
s,@LIBOBJS@,$LIBOBJS,;t t
s,@LTLIBOBJS@,$LTLIBOBJS,;t t
CEOF
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[llvm-commits] [poolalloc] r47095 - /poolalloc/trunk/Makefile.common.in
Author: criswell Date: Wed Feb 13 16:25:17 2008 New Revision: 47095 URL: http://llvm.org/viewvc/llvm-project?rev=47095view=rev Log: Enhanced Makefiles so that building with SAFECode works. Modified: poolalloc/trunk/Makefile.common.in Modified: poolalloc/trunk/Makefile.common.in URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/Makefile.common.in?rev=47095r1=47094r2=47095view=diff == --- poolalloc/trunk/Makefile.common.in (original) +++ poolalloc/trunk/Makefile.common.in Wed Feb 13 16:25:17 2008 @@ -19,6 +19,16 @@ # Set the root directory of this project's install prefix PROJ_INSTALL_ROOT := @prefix@ +# Location of SAFECode source tree +SAFECODE_SRC_ROOT := @SAFECODESRC@ +SAFECODE_OBJ_ROOT := @SAFECODEOBJ@ + +# All of the code should additionally look inside the pool allocation source +# code for include files +CFLAGS += -I$(SAFECODE_SRC_ROOT)/include -I$(SAFECODE_OBJ_ROOT)/include +CXXFLAGS += -I$(SAFECODE_SRC_ROOT)/include -I$(SAFECODE_OBJ_ROOT)/include +CPPFLAGS += -I$(SAFECODE_SRC_ROOT)/include -I$(SAFECODE_OBJ_ROOT)/include + # Include LLVM's Master Makefile. include $(LLVM_SRC_ROOT)/Makefile.common ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47096 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target
Author: djg
Date: Wed Feb 13 16:28:48 2008
New Revision: 47096
URL: http://llvm.org/viewvc/llvm-project?rev=47096view=rev
Log:
Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
to pass the mask APInt by value, not by reference.
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
llvm/trunk/include/llvm/Target/TargetLowering.h
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.h
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=47096r1=47095r2=47096view=diff
==
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Feb 13 16:28:48 2008
@@ -556,7 +556,7 @@
/// bitsets. This code only analyzes bits in Mask, in order to short-circuit
/// processing. Targets can implement the computeMaskedBitsForTargetNode
/// method in the TargetLowering class to allow target nodes to be
understood.
- void ComputeMaskedBits(SDOperand Op, APInt Mask, APInt KnownZero,
+ void ComputeMaskedBits(SDOperand Op, const APInt Mask, APInt KnownZero,
APInt KnownOne, unsigned Depth = 0) const;
/// ComputeMaskedBits - This is a wrapper around the APInt-using
Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=47096r1=47095r2=47096view=diff
==
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Wed Feb 13 16:28:48 2008
@@ -627,7 +627,7 @@
/// Mask are known to be either zero or one and return them in the
/// KnownZero/KnownOne bitsets.
virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
- APInt Mask,
+ const APInt Mask,
APInt KnownZero,
APInt KnownOne,
const SelectionDAG DAG,
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=47096r1=47095r2=47096view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Feb 13 16:28:48
2008
@@ -1130,7 +1130,7 @@
/// known to be either zero or one and return them in the KnownZero/KnownOne
/// bitsets. This code only analyzes bits in Mask, in order to short-circuit
/// processing.
-void SelectionDAG::ComputeMaskedBits(SDOperand Op, APInt Mask,
+void SelectionDAG::ComputeMaskedBits(SDOperand Op, const APInt Mask,
APInt KnownZero, APInt KnownOne,
unsigned Depth) const {
unsigned BitWidth = Mask.getBitWidth();
@@ -1153,8 +1153,8 @@
case ISD::AND:
// If either the LHS or the RHS are Zero, the result is zero.
ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
-Mask = ~KnownZero;
-ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
+ComputeMaskedBits(Op.getOperand(0), Mask ~KnownZero,
+ KnownZero2, KnownOne2, Depth+1);
assert((KnownZero KnownOne) == 0 Bits known to be one AND zero?);
assert((KnownZero2 KnownOne2) == 0 Bits known to be one AND zero?);
@@ -1165,8 +1165,8 @@
return;
case ISD::OR:
ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
-Mask = ~KnownOne;
-ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
+ComputeMaskedBits(Op.getOperand(0), Mask ~KnownOne,
+ KnownZero2, KnownOne2, Depth+1);
assert((KnownZero KnownOne) == 0 Bits known to be one AND zero?);
assert((KnownZero2 KnownOne2) == 0 Bits known to be one AND zero?);
@@ -1271,21 +1271,19 @@
return;
case ISD::SIGN_EXTEND_INREG: {
MVT::ValueType EVT = castVTSDNode(Op.getOperand(1))-getVT();
+unsigned EBits = MVT::getSizeInBits(EVT);
//
[llvm-commits] [llvm] r47090 - in /llvm/trunk: include/llvm/ADT/APInt.h lib/Transforms/Scalar/InstructionCombining.cpp
Author: djg
Date: Wed Feb 13 16:09:18 2008
New Revision: 47090
URL: http://llvm.org/viewvc/llvm-project?rev=47090view=rev
Log:
Rename APInt's isPositive to isNonNegative, to reflect what it
actually does.
Modified:
llvm/trunk/include/llvm/ADT/APInt.h
llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
Modified: llvm/trunk/include/llvm/ADT/APInt.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/APInt.h?rev=47090r1=47089r2=47090view=diff
==
--- llvm/trunk/include/llvm/ADT/APInt.h (original)
+++ llvm/trunk/include/llvm/ADT/APInt.h Wed Feb 13 16:09:18 2008
@@ -232,16 +232,17 @@
}
/// This tests the high bit of the APInt to determine if it is unset.
- /// @brief Determine if this APInt Value is positive (not negative).
- bool isPositive() const {
+ /// @brief Determine if this APInt Value is non-negative (= 0)
+ bool isNonNegative() const {
return !isNegative();
}
- /// This tests if the value of this APInt is strictly positive ( 0).
- /// @returns true if this APInt is Positive and not zero.
- /// @brief Determine if this APInt Value is strictly positive.
+ /// This tests if the value of this APInt is positive ( 0). Note
+ /// that 0 is not a positive value.
+ /// @returns true if this APInt is positive.
+ /// @brief Determine if this APInt Value is positive.
inline bool isStrictlyPositive() const {
-return isPositive() (*this) != 0;
+return isNonNegative() (*this) != 0;
}
/// This checks to see if the value has all bits of the APInt are set or not.
Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=47090r1=47089r2=47090view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Wed Feb 13
16:09:18 2008
@@ -5293,12 +5293,12 @@
HiOverflow = LoOverflow = ProdOV;
if (!HiOverflow)
HiOverflow = AddWithOverflow(HiBound, LoBound, DivRHS, false);
- } else if (DivRHS-getValue().isPositive()) { // Divisor is 0.
+ } else if (DivRHS-getValue().isStrictlyPositive()) { // Divisor is 0.
if (CmpRHSV == 0) { // (X / pos) op 0
// Can't overflow. e.g. X/2 op 0 -- [-1, 2)
LoBound = castConstantInt(ConstantExpr::getNeg(SubOne(DivRHS)));
HiBound = DivRHS;
-} else if (CmpRHSV.isPositive()) { // (X / pos) op pos
+} else if (CmpRHSV.isStrictlyPositive()) { // (X / pos) op pos
LoBound = Prod; // e.g. X/5 op 3 -- [15, 20)
HiOverflow = LoOverflow = ProdOV;
if (!HiOverflow)
@@ -5311,7 +5311,7 @@
HiBound = AddOne(Prod);
HiOverflow = ProdOV ? -1 : 0;
}
- } else { // Divisor is 0.
+ } else if (DivRHS-getValue().isNegative()) { // Divisor is 0.
if (CmpRHSV == 0) { // (X / neg) op 0
// e.g. X/-5 op 0 -- [-4, 5)
LoBound = AddOne(DivRHS);
@@ -5320,7 +5320,7 @@
HiOverflow = 1;// [INTMIN+1, overflow)
HiBound = 0; // e.g. X/INTMIN = 0 -- X INTMIN
}
-} else if (CmpRHSV.isPositive()) { // (X / neg) op pos
+} else if (CmpRHSV.isStrictlyPositive()) { // (X / neg) op pos
// e.g. X/-5 op 3 -- [-19, -14)
HiOverflow = LoOverflow = ProdOV ? -1 : 0;
if (!LoOverflow)
@@ -5434,8 +5434,8 @@
// Extending a relational comparison when we're checking the sign
// bit would not work.
if (Cast-hasOneUse()
-(ICI.isEquality() || AndCST-getValue().isPositive()
- RHSV.isPositive())) {
+(ICI.isEquality() || AndCST-getValue().isNonNegative()
+ RHSV.isNonNegative())) {
uint32_t BitWidth =
castIntegerType(Cast-getOperand(0)-getType())-getBitWidth();
APInt NewCST = AndCST-getValue();
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[llvm-commits] [llvm] r47089 - in /llvm/trunk: lib/Transforms/Scalar/LoopIndexSplit.cpp test/Transforms/LoopIndexSplit/2008-02-13-LoopLatch.ll
Author: dpatel
Date: Wed Feb 13 16:06:36 2008
New Revision: 47089
URL: http://llvm.org/viewvc/llvm-project?rev=47089view=rev
Log:
While moving exit condition, do not drop loop latch on the floor.
Added:
llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-13-LoopLatch.ll
Modified:
llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp?rev=47089r1=47088r2=47089view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp Wed Feb 13 16:06:36 2008
@@ -1579,17 +1579,22 @@
// destination.
BranchInst *ExitingBR = castBranchInst(ExitingBB-getTerminator());
ExitingBR-moveBefore(CurrentBR);
- if (ExitingBR-getSuccessor(0) == ExitBB)
+ BasicBlock *OrigDestBB = NULL;
+ if (ExitingBR-getSuccessor(0) == ExitBB) {
+OrigDestBB = ExitingBR-getSuccessor(1);
ExitingBR-setSuccessor(1, ActiveBB);
- else
+ }
+ else {
+OrigDestBB = ExitingBR-getSuccessor(0);
ExitingBR-setSuccessor(0, ActiveBB);
+ }
// Remove split condition and current split condition branch.
SC-eraseFromParent();
CurrentBR-eraseFromParent();
- // Connect exiting block to split condition block.
- new BranchInst(CondBB, ExitingBB);
+ // Connect exiting block to original destination.
+ new BranchInst(OrigDestBB, ExitingBB);
// Update PHINodes
updatePHINodes(ExitBB, ExitingBB, CondBB, IV, IVAdd);
Added: llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-13-LoopLatch.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-13-LoopLatch.ll?rev=47089view=auto
==
--- llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-13-LoopLatch.ll (added)
+++ llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-13-LoopLatch.ll Wed Feb
13 16:06:36 2008
@@ -0,0 +1,72 @@
+; RUN: llvm-as %s | opt -loop-index-split -disable-output
+; PR 2011
+ %struct.CLAUSE_HELP = type { i32, i32, i32, i32, i32*, i32,
%struct.LIST_NODE*, %struct.LIST_NODE*, i32, i32, %struct.LITERAL_HELP**, i32,
i32, i32, i32 }
+ %struct.LIST_NODE = type { %struct.LIST_NODE*, i8* }
+ %struct.LITERAL_HELP = type { i32, i32, i32, %struct.CLAUSE_HELP*,
%struct.term* }
+ %struct.anon = type { %struct.LIST_NODE* }
+ %struct.st = type { %struct.subst*, %struct.LIST_NODE*,
%struct.LIST_NODE*, i16, i16 }
+ %struct.subst = type { %struct.subst*, i32, %struct.term* }
+ %struct.term = type { i32, %struct.anon, %struct.LIST_NODE*, i32, i32 }
+
+define fastcc %struct.LIST_NODE* @inf_HyperResolvents(%struct.CLAUSE_HELP*
%Clause, %struct.subst* %Subst, %struct.LIST_NODE* %Restlits, i32
%GlobalMaxVar, %struct.LIST_NODE* %FoundMap, i32 %StrictlyMaximal, {
%struct.st*, [3001 x %struct.term*], [4000 x %struct.term*], i32 }* %Index,
i32* %Flags, i32* %Precedence) nounwind {
+entry:
+ br i1 false, label %bb960, label %bb885
+
+bb885: ; preds = %entry
+ ret %struct.LIST_NODE* null
+
+bb960: ; preds = %entry
+ br i1 false, label %bb1097, label %bb1005.preheader
+
+bb1005.preheader: ; preds = %bb960
+ ret %struct.LIST_NODE* null
+
+bb1097:; preds = %bb960
+ br i1 false, label %bb1269.preheader, label %bb1141.preheader
+
+bb1141.preheader: ; preds = %bb1097
+ ret %struct.LIST_NODE* null
+
+bb1269.preheader: ; preds = %bb1097
+ br i1 false, label %bb1318, label %bb1281
+
+bb1281:; preds = %bb1269.preheader
+ ret %struct.LIST_NODE* null
+
+bb1318:; preds = %bb1269.preheader
+ br i1 false, label %bb1459, label %bb.nph52
+
+bb.nph52: ; preds = %bb1318
+ ret %struct.LIST_NODE* null
+
+bb1459:; preds = %bb1318
+ br i1 false, label %bb1553, label %bb.nph62
+
+bb.nph62: ; preds = %bb1459
+ ret %struct.LIST_NODE* null
+
+bb1553:; preds = %bb1669, %bb1459
+ %j295.0.reg2mem.0 = phi i32 [ %storemerge110, %bb1669 ], [ 0, %bb1459 ]
; i32 [#uses=2]
+ br i1 false, label %bb1588, label %bb1616
+
+bb1588:; preds = %bb1553
+ br label %bb1616
+
+bb1616:; preds = %bb1588, %bb1553
+ %tmp1629 = icmp sgt i32 %j295.0.reg2mem.0, 0; i1 [#uses=1]
+ br i1 %tmp1629, label %bb1649, label %bb1632
+
+bb1632:; preds = %bb1616
+ br label %bb1669
+
+bb1649:; preds = %bb1616
+ br label %bb1669
+
+bb1669:; preds = %bb1649, %bb1632
+ %storemerge110 = add i32 %j295.0.reg2mem.0, 1 ; i32
[#uses=2]
+ %tmp1672 = icmp sgt i32 %storemerge110, 0 ; i1
[llvm-commits] [llvm] r47097 - /llvm/trunk/include/llvm/ADT/APInt.h
Author: djg Date: Wed Feb 13 16:32:12 2008 New Revision: 47097 URL: http://llvm.org/viewvc/llvm-project?rev=47097view=rev Log: Fix a typo in a comment. Modified: llvm/trunk/include/llvm/ADT/APInt.h Modified: llvm/trunk/include/llvm/ADT/APInt.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/APInt.h?rev=47097r1=47096r2=47097view=diff == --- llvm/trunk/include/llvm/ADT/APInt.h (original) +++ llvm/trunk/include/llvm/ADT/APInt.h Wed Feb 13 16:32:12 2008 @@ -123,7 +123,7 @@ uint32_t wordBits = BitWidth % APINT_BITS_PER_WORD; if (wordBits == 0) // If all bits are used, we want to leave the value alone. This also - // avoids the undefined behavior of when the shfit is the same size as + // avoids the undefined behavior of when the shift is the same size as // the word size (64). return *this; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47101 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Author: djg
Date: Wed Feb 13 17:13:32 2008
New Revision: 47101
URL: http://llvm.org/viewvc/llvm-project?rev=47101view=rev
Log:
Allow the APInt form of ComputeMaskedBits to operate on i128 types.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=47101r1=47100r2=47101view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Feb 13 17:13:32
2008
@@ -1134,14 +1134,13 @@
APInt KnownZero, APInt KnownOne,
unsigned Depth) const {
unsigned BitWidth = Mask.getBitWidth();
+ assert(BitWidth == MVT::getSizeInBits(Op.getValueType())
+ Mask size mismatches value type size!);
+
KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
if (Depth == 6 || Mask == 0)
return; // Limit search depth.
- // The masks are not wide enough to represent this type! Should use APInt.
- if (Op.getValueType() == MVT::i128)
-return;
-
APInt KnownZero2, KnownOne2;
switch (Op.getOpcode()) {
@@ -1477,6 +1476,10 @@
void SelectionDAG::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
uint64_t KnownZero, uint64_t KnownOne,
unsigned Depth) const {
+ // The masks are not wide enough to represent this type! Should use APInt.
+ if (Op.getValueType() == MVT::i128)
+return;
+
unsigned NumBits = MVT::getSizeInBits(Op.getValueType());
APInt APIntMask(NumBits, Mask);
APInt APIntKnownZero(NumBits, 0);
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Re: [llvm-commits] [llvm] r47096 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Ta
On Feb 13, 2008, at 2:28 PM, Dan Gohman wrote: Author: djg Date: Wed Feb 13 16:28:48 2008 New Revision: 47096 URL: http://llvm.org/viewvc/llvm-project?rev=47096view=rev Log: Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits to pass the mask APInt by value, not by reference. Thanks Dan! -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47099 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Author: djg
Date: Wed Feb 13 17:07:24 2008
New Revision: 47099
URL: http://llvm.org/viewvc/llvm-project?rev=47099view=rev
Log:
Assigning an APInt to 0 with plain assignment gives it a one-bit
size. Initialize these APInts to properly-sized zero values.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=47099r1=47098r2=47099view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Feb 13 17:07:24 2008
@@ -5653,7 +5653,7 @@
Should use MaskedValueIsZero if you don't know whether Op
is a target node!);
- KnownZero = KnownOne = 0; // Don't know anything.
+ KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know
anything.
switch (Opc) {
default: break;
case X86ISD::SETCC:
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Re: [llvm-commits] [llvm] r47086 - in /llvm/trunk: include/llvm/ADT/APInt.h lib/Support/APInt.cpp
Hi Dan,
+uint32_t APInt::countTrailingOnes() const {
+ if (isSingleWord())
+return std::min(uint32_t(CountTrailingOnes_64(VAL)), BitWidth);
+ uint32_t Count = 0;
+ uint32_t i = 0;
+ for (; i getNumWords() pVal[i] == -1; ++i)
This compare leads to this warning:
llvm[1]: Compiling APInt.cpp for Debug build
/Volumes/Gir/devel/llvm/llvm.src/lib/Support/APInt.cpp: In member
function 'uint32_t llvm::APInt::countTrailingOnes() const':
/Volumes/Gir/devel/llvm/llvm.src/lib/Support/APInt.cpp:821: warning:
comparison between signed and unsigned integer expressions
Could you take a look at it please?
-bw
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[llvm-commits] [llvm] r47102 - /llvm/trunk/test/CodeGen/X86/arg-cast.ll
Author: evancheng Date: Wed Feb 13 19:32:53 2008 New Revision: 47102 URL: http://llvm.org/viewvc/llvm-project?rev=47102view=rev Log: Fix test. Modified: llvm/trunk/test/CodeGen/X86/arg-cast.ll Modified: llvm/trunk/test/CodeGen/X86/arg-cast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/arg-cast.ll?rev=47102r1=47101r2=47102view=diff == --- llvm/trunk/test/CodeGen/X86/arg-cast.ll (original) +++ llvm/trunk/test/CodeGen/X86/arg-cast.ll Wed Feb 13 19:32:53 2008 @@ -1,7 +1,7 @@ ; This should compile to movl $2147483647, %eax + andl only. ; RUN: llvm-as %s | llc | grep andl ; RUN: llvm-as %s | llc | not grep movsd -; RUN: llvm-as %s | llc | not grep esp +; RUN: llvm-as %s | llc | grep esp | not grep add ; rdar://5736574 target datalayout = e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128 ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r47102 - /llvm/trunk/test/CodeGen/X86/arg-cast.ll
On Feb 13, 2008, at 5:32 PM, Evan Cheng wrote: Author: evancheng Date: Wed Feb 13 19:32:53 2008 New Revision: 47102 URL: http://llvm.org/viewvc/llvm-project?rev=47102view=rev Log: Fix test. Doh, thanks Evan. -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47105 - /llvm/trunk/tools/bugpoint/FindBugs.cpp
Author: nicholas
Date: Wed Feb 13 23:01:46 2008
New Revision: 47105
URL: http://llvm.org/viewvc/llvm-project?rev=47105view=rev
Log:
PR2027, Fix bugpoint's -find-bugs option, clean up the code.
Modified:
llvm/trunk/tools/bugpoint/FindBugs.cpp
Modified: llvm/trunk/tools/bugpoint/FindBugs.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/FindBugs.cpp?rev=47105r1=47104r2=47105view=diff
==
--- llvm/trunk/tools/bugpoint/FindBugs.cpp (original)
+++ llvm/trunk/tools/bugpoint/FindBugs.cpp Wed Feb 13 23:01:46 2008
@@ -30,8 +30,7 @@
/// recreate the failure. This returns true if a compiler error is found.
///
bool BugDriver::runManyPasses(const std::vectorconst PassInfo* AllPasses) {
- std::string Filename;
- std::vectorconst PassInfo* TempPass(AllPasses);
+ setPassesToRun(AllPasses);
std::cout Starting bug finding procedure...\n\n;
// Creating a reference output if necessary
@@ -45,26 +44,24 @@
}
srand(time(NULL));
- std::vectorconst PassInfo*::iterator I = TempPass.begin();
- std::vectorconst PassInfo*::iterator E = TempPass.end();
-
+
unsigned num = 1;
while(1) {
//
// Step 1: Randomize the order of the optimizer passes.
//
-std::random_shuffle(TempPass.begin(), TempPass.end());
+std::random_shuffle(PassesToRun.begin(), PassesToRun.end());
//
// Step 2: Run optimizer passes on the program and check for success.
//
std::cout Running selected passes on program to test for crash: ;
-for(int i = 0, e = TempPass.size(); i != e; i++) {
- std::cout - TempPass[i]-getPassArgument( ) ;
+for(int i = 0, e = PassesToRun.size(); i != e; i++) {
+ std::cout - PassesToRun[i]-getPassArgument( ) ;
}
std::string Filename;
-if(runPasses(TempPass, Filename, false)) {
+if(runPasses(PassesToRun, Filename, false)) {
std::cout \n;
std::cout Optimizer passes caused failure!\n\n;
debugOptimizerCrash();
@@ -72,7 +69,7 @@
} else {
std::cout Combination num optimized successfully!\n;
}
-
+
//
// Step 3: Compile the optimized code.
//
@@ -85,7 +82,7 @@
std::cout TEE.what();
return debugCodeGeneratorCrash();
}
-
+
//
// Step 4: Run the program and compare its output to the reference
// output (created above).
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[llvm-commits] [llvm] r47106 - in /llvm/trunk: lib/Target/X86/README-FPStack.txt test/CodeGen/X86/zero-remat.ll
Author: lattner
Date: Wed Feb 13 23:39:46 2008
New Revision: 47106
URL: http://llvm.org/viewvc/llvm-project?rev=47106view=rev
Log:
This readme entry is done, testcase here: CodeGen/X86/zero-remat.ll
Modified:
llvm/trunk/lib/Target/X86/README-FPStack.txt
llvm/trunk/test/CodeGen/X86/zero-remat.ll
Modified: llvm/trunk/lib/Target/X86/README-FPStack.txt
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-FPStack.txt?rev=47106r1=47105r2=47106view=diff
==
--- llvm/trunk/lib/Target/X86/README-FPStack.txt (original)
+++ llvm/trunk/lib/Target/X86/README-FPStack.txt Wed Feb 13 23:39:46 2008
@@ -9,20 +9,6 @@
//===-===//
-On darwin/x86, we should codegen:
-
-ret double 0.00e+00
-
-as fld0/ret, not as:
-
-movl $0, 4(%esp)
-movl $0, (%esp)
-fldl (%esp)
- ...
-ret
-
-//===-===//
-
This should use fiadd on chips where it is profitable:
double foo(double P, int *I) { return P+*I; }
Modified: llvm/trunk/test/CodeGen/X86/zero-remat.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/zero-remat.ll?rev=47106r1=47105r2=47106view=diff
==
--- llvm/trunk/test/CodeGen/X86/zero-remat.ll (original)
+++ llvm/trunk/test/CodeGen/X86/zero-remat.ll Wed Feb 13 23:39:46 2008
@@ -1,5 +1,7 @@
; RUN: llvm-as %s | llc -march=x86-64 | grep xor | count 4
; RUN: llvm-as %s | llc -march=x86-64 -stats -info-output-file - | grep
asm-printer | grep 12
+; RUN: llvm-as %s | llc -march=x86 | grep fldz
+; RUN: llvm-as %s | llc -march=x86 | not grep fldl
declare void @bar(double %x)
declare void @barf(float %x)
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[llvm-commits] [llvm] r47108 - /llvm/trunk/lib/Target/X86/README-MMX.txt
Author: lattner
Date: Wed Feb 13 23:43:18 2008
New Revision: 47108
URL: http://llvm.org/viewvc/llvm-project?rev=47108view=rev
Log:
the mid-level optimizer removes this stuff.
Modified:
llvm/trunk/lib/Target/X86/README-MMX.txt
Modified: llvm/trunk/lib/Target/X86/README-MMX.txt
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-MMX.txt?rev=47108r1=47107r2=47108view=diff
==
--- llvm/trunk/lib/Target/X86/README-MMX.txt (original)
+++ llvm/trunk/lib/Target/X86/README-MMX.txt Wed Feb 13 23:43:18 2008
@@ -41,29 +41,3 @@
addl$12, %esp
ret $4
-//===-===//
-
-int main() {
- __m64 A[1] = { _mm_cvtsi32_si64(1) };
- __m64 B[1] = { _mm_cvtsi32_si64(10) };
- __m64 sum = _mm_cvtsi32_si64(0);
-
- sum = __builtin_ia32_paddq(__builtin_ia32_paddq(A[0], B[0]), sum);
-
- printf(Sum = %d\n, _mm_cvtsi64_si32(sum));
- return 0;
-}
-
-Generates:
-
-movl $11, %eax
-### movd %eax, %mm0
-### movq %mm0, 8(%esp)
-### movl 8(%esp), %eax
-movl %eax, 4(%esp)
-movl $_str, (%esp)
-call L_printf$stub
-xorl %eax, %eax
-addl $28, %esp
-
-These instructions are unnecessary.
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[llvm-commits] [llvm] r47107 - /llvm/trunk/lib/Target/X86/README-FPStack.txt
Author: lattner Date: Wed Feb 13 23:41:38 2008 New Revision: 47107 URL: http://llvm.org/viewvc/llvm-project?rev=47107view=rev Log: this one is easy. Modified: llvm/trunk/lib/Target/X86/README-FPStack.txt Modified: llvm/trunk/lib/Target/X86/README-FPStack.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-FPStack.txt?rev=47107r1=47106r2=47107view=diff == --- llvm/trunk/lib/Target/X86/README-FPStack.txt (original) +++ llvm/trunk/lib/Target/X86/README-FPStack.txt Wed Feb 13 23:41:38 2008 @@ -80,6 +80,6 @@ addl $20, %esp ret -This will be solved when we go to a dynamic programming based isel. +This just requires being smarter when custom expanding fptoui. //===-===// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47109 - in /llvm/trunk/lib/Target/X86: README-SSE.txt README.txt
Author: lattner
Date: Thu Feb 14 00:19:02 2008
New Revision: 47109
URL: http://llvm.org/viewvc/llvm-project?rev=47109view=rev
Log:
upgrade some entries, remove stuff that is done.
Modified:
llvm/trunk/lib/Target/X86/README-SSE.txt
llvm/trunk/lib/Target/X86/README.txt
Modified: llvm/trunk/lib/Target/X86/README-SSE.txt
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-SSE.txt?rev=47109r1=47108r2=47109view=diff
==
--- llvm/trunk/lib/Target/X86/README-SSE.txt (original)
+++ llvm/trunk/lib/Target/X86/README-SSE.txt Thu Feb 14 00:19:02 2008
@@ -56,22 +56,23 @@
time, not at spiller time). *Note* however that this can only be done
if Y is dead. Here's a testcase:
-%.str_3 = external global [15 x sbyte] ; [15 x sbyte]* [#uses=0]
-implementation ; Functions:
-declare void %printf(int, ...)
-void %main() {
[EMAIL PROTECTED] = external global [15 x i8] ; [15 x i8]* [#uses=0]
+declare void @printf(i32, ...)
+define void @main() {
build_tree.exit:
-br label %no_exit.i7
-no_exit.i7: ; preds = %no_exit.i7, %build_tree.exit
-%tmp.0.1.0.i9 = phi double [ 0.00e+00, %build_tree.exit ], [
%tmp.34.i18, %no_exit.i7 ] ; double [#uses=1]
-%tmp.0.0.0.i10 = phi double [ 0.00e+00, %build_tree.exit ], [
%tmp.28.i16, %no_exit.i7 ] ; double [#uses=1]
-%tmp.28.i16 = add double %tmp.0.0.0.i10, 0.00e+00
-%tmp.34.i18 = add double %tmp.0.1.0.i9, 0.00e+00
-br bool false, label %Compute_Tree.exit23, label %no_exit.i7
-Compute_Tree.exit23:; preds = %no_exit.i7
-tail call void (int, ...)* %printf( int 0 )
-store double %tmp.34.i18, double* null
-ret void
+ br label %no_exit.i7
+
+no_exit.i7:; preds = %no_exit.i7, %build_tree.exit
+ %tmp.0.1.0.i9 = phi double [ 0.00e+00, %build_tree.exit ], [
%tmp.34.i18, %no_exit.i7 ] ; double [#uses=1]
+ %tmp.0.0.0.i10 = phi double [ 0.00e+00, %build_tree.exit ], [
%tmp.28.i16, %no_exit.i7 ]; double [#uses=1]
+ %tmp.28.i16 = add double %tmp.0.0.0.i10, 0.00e+00 ;
double [#uses=1]
+ %tmp.34.i18 = add double %tmp.0.1.0.i9, 0.00e+00;
double [#uses=2]
+ br i1 false, label %Compute_Tree.exit23, label %no_exit.i7
+
+Compute_Tree.exit23: ; preds = %no_exit.i7
+ tail call void (i32, ...)* @printf( i32 0 )
+ store double %tmp.34.i18, double* null
+ ret void
}
We currently emit:
@@ -125,25 +126,6 @@
//===-===//
-Currently the x86 codegen isn't very good at mixing SSE and FPStack
-code:
-
-unsigned int foo(double x) { return x; }
-
-foo:
- subl $20, %esp
- movsd 24(%esp), %xmm0
- movsd %xmm0, 8(%esp)
- fldl 8(%esp)
- fisttpll (%esp)
- movl (%esp), %eax
- addl $20, %esp
- ret
-
-This will be solved when we go to a dynamic programming based isel.
-
-//===-===//
-
Lower memcpy / memset to a series of SSE 128 bit move instructions when it's
feasible.
Modified: llvm/trunk/lib/Target/X86/README.txt
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README.txt?rev=47109r1=47108r2=47109view=diff
==
--- llvm/trunk/lib/Target/X86/README.txt (original)
+++ llvm/trunk/lib/Target/X86/README.txt Thu Feb 14 00:19:02 2008
@@ -435,44 +435,6 @@
//===-===//
-Consider this:
-
-typedef struct pair { float A, B; } pair;
-void pairtest(pair P, float *FP) {
-*FP = P.A+P.B;
-}
-
-We currently generate this code with llvmgcc4:
-
-_pairtest:
-movl 8(%esp), %eax
-movl 4(%esp), %ecx
-movd %eax, %xmm0
-movd %ecx, %xmm1
-addss %xmm0, %xmm1
-movl 12(%esp), %eax
-movss %xmm1, (%eax)
-ret
-
-we should be able to generate:
-_pairtest:
-movss 4(%esp), %xmm0
-movl 12(%esp), %eax
-addss 8(%esp), %xmm0
-movss %xmm0, (%eax)
-ret
-
-The issue is that llvmgcc4 is forcing the struct to memory, then passing it as
-integer chunks. It does this so that structs like {short,short} are passed in
-a single 32-bit integer stack slot. We should handle the safe cases above much
-nicer, while still handling the hard cases.
-
-While true in general, in this specific case we could do better by promoting
-load int + bitcast to float - load fload. This basically needs alignment
info,
-the code is already implemented (but disabled) in dag combine).
-
-//===-===//
-
Another instruction selector deficiency:
void %bar() {
@@ -551,25 +513,24
[llvm-commits] [llvm] r47111 - /llvm/trunk/lib/Transforms/Scalar/GVN.cpp
Author: nicholas Date: Thu Feb 14 01:11:24 2008 New Revision: 47111 URL: http://llvm.org/viewvc/llvm-project?rev=47111view=rev Log: Fix PR2032. Inform the alias analysis of changes to the underlying program. Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=47111r1=47110r2=47111view=diff == --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Thu Feb 14 01:11:24 2008 @@ -857,6 +857,8 @@ PN-addIncoming(val, *PI); } + AliasAnalysis AA = getAnalysisAliasAnalysis(); + AA.copyValue(orig, PN); // Attempt to collapse PHI nodes that are trivially redundant Value* v = CollapsePhi(PN); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47113 - /llvm/trunk/test/Transforms/GVN/2008-02-13-NewPHI.ll
Author: nicholas
Date: Thu Feb 14 01:15:11 2008
New Revision: 47113
URL: http://llvm.org/viewvc/llvm-project?rev=47113view=rev
Log:
Testcase for PR2032.
Added:
llvm/trunk/test/Transforms/GVN/2008-02-13-NewPHI.ll
Added: llvm/trunk/test/Transforms/GVN/2008-02-13-NewPHI.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/2008-02-13-NewPHI.ll?rev=47113view=auto
==
--- llvm/trunk/test/Transforms/GVN/2008-02-13-NewPHI.ll (added)
+++ llvm/trunk/test/Transforms/GVN/2008-02-13-NewPHI.ll Thu Feb 14 01:15:11 2008
@@ -0,0 +1,22 @@
+; RUN: llvm-as %s | opt -anders-aa -gvn
+; PR2032
+
+define i32 @sscal(i32 %n, double %sa1, float* %sx, i32 %incx) {
+entry:
+ %sx_addr = alloca float*; float** [#uses=3]
+ store float* %sx, float** %sx_addr, align 4
+ br label %bb33
+
+bb:; preds = %bb33
+ %tmp27 = load float** %sx_addr, align 4 ; float* [#uses=1]
+ store float 0.00e+00, float* %tmp27, align 4
+ store float* null, float** %sx_addr, align 4
+ br label %bb33
+
+bb33: ; preds = %bb, %entry
+ br i1 false, label %bb, label %return
+
+return:; preds = %bb33
+ %retval59 = load i32* null, align 4 ; i32 [#uses=1]
+ ret i32 %retval59
+}
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[llvm-commits] [llvm] r47114 - /llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
Author: sampo
Date: Thu Feb 14 01:23:11 2008
New Revision: 47114
URL: http://llvm.org/viewvc/llvm-project?rev=47114view=rev
Log:
Nuke dead comment
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=47114r1=47113r2=47114view=diff
==
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Feb 14 01:23:11 2008
@@ -1207,8 +1207,6 @@
class ConstantFPSDNode : public SDNode {
APFloat Value;
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
- // Longterm plan: replace all uses of getValue with getValueAPF, remove
- // getValue, rename getValueAPF to getValue.
protected:
friend class SelectionDAG;
ConstantFPSDNode(bool isTarget, const APFloat val, MVT::ValueType VT)
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[llvm-commits] [llvm] r47115 - in /llvm/trunk/lib/Target: CellSPU/SPUOperands.td Target.td
Author: sampo
Date: Thu Feb 14 01:25:46 2008
New Revision: 47115
URL: http://llvm.org/viewvc/llvm-project?rev=47115view=rev
Log:
Move some useful operands up into the all-targets .td
Modified:
llvm/trunk/lib/Target/CellSPU/SPUOperands.td
llvm/trunk/lib/Target/Target.td
Modified: llvm/trunk/lib/Target/CellSPU/SPUOperands.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUOperands.td?rev=47115r1=47114r2=47115view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUOperands.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUOperands.td Thu Feb 14 01:25:46 2008
@@ -538,9 +538,6 @@
let PrintMethod = printROTNeg7Imm;
}
-// Floating point immediate operands
-def f32imm : Operandf32;
-
def target : OperandOtherVT {
let PrintMethod = printBranchOperand;
}
Modified: llvm/trunk/lib/Target/Target.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Target.td?rev=47115r1=47114r2=47115view=diff
==
--- llvm/trunk/lib/Target/Target.td (original)
+++ llvm/trunk/lib/Target/Target.td Thu Feb 14 01:25:46 2008
@@ -277,6 +277,9 @@
def i32imm : Operandi32;
def i64imm : Operandi64;
+def f32imm : Operandf32;
+def f64imm : Operandf64;
+
/// zero_reg definition - Special node to stand for the zero register.
///
def zero_reg;
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[llvm-commits] [llvm] r47116 - /llvm/trunk/lib/Transforms/Scalar/SimplifyCFG.cpp
Author: lattner
Date: Thu Feb 14 01:39:01 2008
New Revision: 47116
URL: http://llvm.org/viewvc/llvm-project?rev=47116view=rev
Log:
simplify code, no functionality change.
Modified:
llvm/trunk/lib/Transforms/Scalar/SimplifyCFG.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyCFG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyCFG.cpp?rev=47116r1=47115r2=47116view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SimplifyCFG.cpp Thu Feb 14 01:39:01 2008
@@ -162,13 +162,15 @@
// Loop over all of the basic blocks that are not reachable, dropping all of
// their internal references...
- for (Function::iterator BB = ++F.begin(), E = F.end(); BB != E; ++BB)
-if (!Reachable.count(BB)) {
- for (succ_iterator SI = succ_begin(BB), SE = succ_end(BB); SI!=SE; ++SI)
-if (Reachable.count(*SI))
- (*SI)-removePredecessor(BB);
- BB-dropAllReferences();
-}
+ for (Function::iterator BB = ++F.begin(), E = F.end(); BB != E; ++BB) {
+if (Reachable.count(BB))
+ continue;
+
+for (succ_iterator SI = succ_begin(BB), SE = succ_end(BB); SI != SE; ++SI)
+ if (Reachable.count(*SI))
+(*SI)-removePredecessor(BB);
+BB-dropAllReferences();
+ }
for (Function::iterator I = ++F.begin(); I != F.end();)
if (!Reachable.count(I))
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[llvm-commits] [llvm] r47117 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
Author: sampo
Date: Thu Feb 14 01:39:30 2008
New Revision: 47117
URL: http://llvm.org/viewvc/llvm-project?rev=47117view=rev
Log:
Support a new type of MachineOperand, MO_FPImmediate, used for holding
FP Immediates, crazily enough
Modified:
llvm/trunk/include/llvm/CodeGen/MachineOperand.h
llvm/trunk/lib/CodeGen/MachineInstr.cpp
Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineOperand.h?rev=47117r1=47116r2=47117view=diff
==
--- llvm/trunk/include/llvm/CodeGen/MachineOperand.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineOperand.h Thu Feb 14 01:39:30 2008
@@ -21,6 +21,7 @@
namespace llvm {
+class ConstantFP;
class MachineBasicBlock;
class GlobalValue;
class MachineInstr;
@@ -34,6 +35,7 @@
enum MachineOperandType {
MO_Register,// Register operand.
MO_Immediate, // Immediate Operand
+MO_FPImmediate,
MO_MachineBasicBlock, // MachineBasicBlock reference
MO_FrameIndex, // Abstract Stack Frame Index
MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
@@ -77,6 +79,7 @@
/// Contents union - This contains the payload for the various operand types.
union {
MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
+ConstantFP *CFP; // For MO_FPImmediate.
int64_t ImmVal; // For MO_Immediate.
struct { // For MO_Register.
@@ -120,6 +123,7 @@
///
bool isRegister() const { return OpKind == MO_Register; }
bool isImmediate() const { return OpKind == MO_Immediate; }
+ bool isFPImmediate() const { return OpKind == MO_FPImmediate; }
bool isMachineBasicBlock() const { return OpKind == MO_MachineBasicBlock; }
bool isFrameIndex() const { return OpKind == MO_FrameIndex; }
bool isConstantPoolIndex() const { return OpKind == MO_ConstantPoolIndex; }
@@ -231,6 +235,11 @@
return Contents.ImmVal;
}
+ ConstantFP *getFPImm() const {
+assert(isFPImmediate() Wrong MachineOperand accessor);
+return Contents.CFP;
+ }
+
MachineBasicBlock *getMBB() const {
assert(isMachineBasicBlock() Wrong MachineOperand accessor);
return Contents.MBB;
@@ -313,6 +322,12 @@
return Op;
}
+ static MachineOperand CreateFPImm(ConstantFP *CFP) {
+MachineOperand Op(MachineOperand::MO_FPImmediate);
+Op.Contents.CFP = CFP;
+return Op;
+ }
+
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
bool isKill = false, bool isDead = false,
unsigned SubReg = 0) {
Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=47117r1=47116r2=47117view=diff
==
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Thu Feb 14 01:39:30 2008
@@ -11,6 +11,7 @@
//
//===--===//
+#include llvm/Constants.h
#include llvm/CodeGen/MachineInstr.h
#include llvm/Value.h
#include llvm/CodeGen/MachineFunction.h
@@ -138,6 +139,8 @@
getSubReg() == Other.getSubReg();
case MachineOperand::MO_Immediate:
return getImm() == Other.getImm();
+ case MachineOperand::MO_FPImmediate:
+return getFPImm() == Other.getFPImm();
case MachineOperand::MO_MachineBasicBlock:
return getMBB() == Other.getMBB();
case MachineOperand::MO_FrameIndex:
@@ -197,6 +200,13 @@
case MachineOperand::MO_Immediate:
OS getImm();
break;
+ case MachineOperand::MO_FPImmediate:
+if (getFPImm()-getType() == Type::FloatTy) {
+ OS getFPImm()-getValueAPF().convertToFloat();
+} else {
+ OS getFPImm()-getValueAPF().convertToDouble();
+}
+break;
case MachineOperand::MO_MachineBasicBlock:
OS mbb
((Value*)getMBB()-getBasicBlock())-getName()
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