Re: GitHub CI Jobs Failing During MacPorts Bootstrap

[Christopher Nielsen]

Thanks for clarifying Chris, that makes sense.

In the interim, what do we do for any open PRs which haven’t been validated by 
the CI process...?


> On 2021-04-26-M, at 12:39, Christopher Jones  wrote:
> 
> See the mail Ryan sent a few days back
> 
> The Bintray service will cease to exist on May 1. Our pull request CI checks 
> rely on being able to download certain assets from Bintray, so unless we do 
> something to fix this before then, our pull request CI checks will no longer 
> work as of May 1.
> 
> https://jfrog.com/blog/into-the-sunset-bintray-jcenter-gocenter-and-chartcenter/
>  
> 
> 
> looks like today is
> 
> "We will have some short service brown-outs to remind users about the 
> services that are going away on May 1st. (Specific hours will be advertised 
> in the Bintray status page.)”
> 
> Chris
> 
>> On 26 Apr 2021, at 5:35 pm, Christopher Nielsen > > wrote:
>> 
>> I’m seeing the following failures in the CI jobs, during the MacPorts 
>> Bootstrap phase:
>> 
>> Installing MacPorts
>> Fetching...
>> curl: (22) The requested URL returned error: 403 Forbidden
>> curl: (22) The requested URL returned error: 403 Forbidden
>> Error: Process completed with exit code 22.
>> 
>> Any thoughts/ideas…?

Re: M1 CPU features

[Georges Martin]

And this article describes SIMDe:


https://simd-everywhere.github.io/blog/2020/06/22/transitioning-to-arm-with-simde.html

SIMD Everywhere (SIMDe) provides fast, portable, permissively-licensed (MIT) 
implementations of the x86 APIs which allow you to run code designed for 
x86/x86_64 CPUs pretty much anywhere, including on Arm (using NEON if 
available). With almost no source code changes, you can recompile your x86 SIMD 
code for Arm (or POWER, or WebAssembly, etc.).

...that is not yet packaged for MacPorts ;-) ;-) ;-)

G.

> Le 26 avr. 2021 à 20:56, Georges Martin  a écrit :
> 
>> Aha, hw.optional! That's useful, thanks Georges!
> 
> You're welcome :-) You also have:
> 
>   hw.optional.amx_version: 2
>   hw.optional.arm64: 1
>   hw.targettype: J313
> 
> "amx" is the Neural Engine and I think "J313" is the code name for the M1.
> 
> You may find this article very interesting:
> 
>   
> https://levelup.gitconnected.com/armv9-what-is-the-big-deal-4528f20f78f3 
> 
> 
> It describes the new ARMv9 instruction set with SVE2 and how it compares to 
> Intel/AMD MMX/SSE/AVX and NEON/SVE.
> 
> Question is: would Apple adopt ARMv9 with SVE2 in a M2 for a future Mac Pro ? 
> ;-)
> 
> G.
> 
>> Le 26 avr. 2021 à 20:44, Jason Liu > > a écrit :
>> 
>> Aha, hw.optional! That's useful, thanks Georges!
>> 
>> -- 
>> Jason Liu
>> 
>> 
>> On Mon, Apr 26, 2021 at 2:16 PM Georges Martin > > wrote:
>> $ sysctl hw.optional | grep -E 'neon|armv8'
>> hw.optional.neon: 1
>> hw.optional.neon_hpfp: 1
>> hw.optional.neon_fp16: 1
>> hw.optional.armv8_1_atomics: 1
>> hw.optional.armv8_crc32: 1
>> hw.optional.armv8_2_fhm: 1
>> hw.optional.armv8_2_sha512: 1
>> hw.optional.armv8_2_sha3: 1
>> 
>>> Le 26 avr. 2021 à 19:55, Jason Liu >> > a écrit :
>>> 
>>> On Mon, Apr 26, 2021 at 1:42 PM Christopher Jones >> > wrote:
>>> Thats not at all surprising as those instruction sets are very much 
>>> specific to X86_64 systems.
>>> 
>>> RISC processors, Arm, do have their own sets of SIMD instructions (e.g. 
>>> Neon), but they are entirely different to those on X86_64 machines. 
>>> 
>>> Whether or these are supported on Apple’s M1 processors I have no idea.
>>> 
>>> It looks like the M1 supports Neon SIMD instructions, but not SVE SIMD 
>>> (which I guess is supposed to be similar to AVX?):
>>> 
>>> https://discussions.apple.com/thread/252073619 
>>> 
>>> 
>>> -- 
>>> Jason Liu
>>> 
>>> 
>>> On Mon, Apr 26, 2021 at 1:42 PM Christopher Jones >> > wrote:
>>> 
>>> 
 On 26 Apr 2021, at 6:28 pm, Jason Liu >>> > wrote:
 
 Thanks Arno :)
 
 I'm kind of surprised that the M1 doesn't seem to support any SSE or 
 AVX
>>> 
>>> 
>>> Thats not at all surprising as those instruction sets are very much 
>>> specific to X86_64 systems.
>>> 
>>> RISC processors, Arm, do have their own sets of SIMD instructions (e.g. 
>>> Neon), but they are entirely different to those on X86_64 machines. 
>>> 
>>> Whether or these are supported on Apple’s M1 processors I have no idea.
>>> 
>>> Chris
>>> 
>>> 
>>> 
 
 Does "sysctl machdep.cpu.features" return anything?
 
 -- 
 Jason Liu
 
 
 On Mon, Apr 26, 2021 at 1:23 PM Arno Hautala >>> > wrote:
 > On 26 Apr 2021, at 13:20, Jason Liu >>> > > wrote:
 > 
 > sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse”
 
 $ sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse”
 machdep.cpu.brand_string: Apple M1
 
 -- 
 arno  s  hautala/-|   a...@alum.wpi.edu 
 
 pgp b2c9d448
 
 
>>> 
>> 
> 

Re: M1 CPU features

[Georges Martin]

> Aha, hw.optional! That's useful, thanks Georges!

You're welcome :-) You also have:

hw.optional.amx_version: 2
hw.optional.arm64: 1
hw.targettype: J313

"amx" is the Neural Engine and I think "J313" is the code name for the M1.

You may find this article very interesting:

https://levelup.gitconnected.com/armv9-what-is-the-big-deal-4528f20f78f3

It describes the new ARMv9 instruction set with SVE2 and how it compares to 
Intel/AMD MMX/SSE/AVX and NEON/SVE.

Question is: would Apple adopt ARMv9 with SVE2 in a M2 for a future Mac Pro ? 
;-)

G.

> Le 26 avr. 2021 à 20:44, Jason Liu  a écrit :
> 
> Aha, hw.optional! That's useful, thanks Georges!
> 
> -- 
> Jason Liu
> 
> 
> On Mon, Apr 26, 2021 at 2:16 PM Georges Martin  > wrote:
> $ sysctl hw.optional | grep -E 'neon|armv8'
> hw.optional.neon: 1
> hw.optional.neon_hpfp: 1
> hw.optional.neon_fp16: 1
> hw.optional.armv8_1_atomics: 1
> hw.optional.armv8_crc32: 1
> hw.optional.armv8_2_fhm: 1
> hw.optional.armv8_2_sha512: 1
> hw.optional.armv8_2_sha3: 1
> 
>> Le 26 avr. 2021 à 19:55, Jason Liu > > a écrit :
>> 
>> On Mon, Apr 26, 2021 at 1:42 PM Christopher Jones > > wrote:
>> Thats not at all surprising as those instruction sets are very much specific 
>> to X86_64 systems.
>> 
>> RISC processors, Arm, do have their own sets of SIMD instructions (e.g. 
>> Neon), but they are entirely different to those on X86_64 machines. 
>> 
>> Whether or these are supported on Apple’s M1 processors I have no idea.
>> 
>> It looks like the M1 supports Neon SIMD instructions, but not SVE SIMD 
>> (which I guess is supposed to be similar to AVX?):
>> 
>> https://discussions.apple.com/thread/252073619 
>> 
>> 
>> -- 
>> Jason Liu
>> 
>> 
>> On Mon, Apr 26, 2021 at 1:42 PM Christopher Jones > > wrote:
>> 
>> 
>>> On 26 Apr 2021, at 6:28 pm, Jason Liu >> > wrote:
>>> 
>>> Thanks Arno :)
>>> 
>>> I'm kind of surprised that the M1 doesn't seem to support any SSE or AVX
>> 
>> 
>> Thats not at all surprising as those instruction sets are very much specific 
>> to X86_64 systems.
>> 
>> RISC processors, Arm, do have their own sets of SIMD instructions (e.g. 
>> Neon), but they are entirely different to those on X86_64 machines. 
>> 
>> Whether or these are supported on Apple’s M1 processors I have no idea.
>> 
>> Chris
>> 
>> 
>> 
>>> 
>>> Does "sysctl machdep.cpu.features" return anything?
>>> 
>>> -- 
>>> Jason Liu
>>> 
>>> 
>>> On Mon, Apr 26, 2021 at 1:23 PM Arno Hautala >> > wrote:
>>> > On 26 Apr 2021, at 13:20, Jason Liu >> > > wrote:
>>> > 
>>> > sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse”
>>> 
>>> $ sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse”
>>> machdep.cpu.brand_string: Apple M1
>>> 
>>> -- 
>>> arno  s  hautala/-|   a...@alum.wpi.edu 
>>> 
>>> pgp b2c9d448
>>> 
>>> 
>> 
> 

Re: M1 CPU features

[Georges Martin]

$ sysctl hw.optional | grep -E 'neon|armv8'
hw.optional.neon: 1
hw.optional.neon_hpfp: 1
hw.optional.neon_fp16: 1
hw.optional.armv8_1_atomics: 1
hw.optional.armv8_crc32: 1
hw.optional.armv8_2_fhm: 1
hw.optional.armv8_2_sha512: 1
hw.optional.armv8_2_sha3: 1

> Le 26 avr. 2021 à 19:55, Jason Liu  a écrit :
> 
> On Mon, Apr 26, 2021 at 1:42 PM Christopher Jones  > wrote:
> Thats not at all surprising as those instruction sets are very much specific 
> to X86_64 systems.
> 
> RISC processors, Arm, do have their own sets of SIMD instructions (e.g. 
> Neon), but they are entirely different to those on X86_64 machines. 
> 
> Whether or these are supported on Apple’s M1 processors I have no idea.
> 
> It looks like the M1 supports Neon SIMD instructions, but not SVE SIMD (which 
> I guess is supposed to be similar to AVX?):
> 
> https://discussions.apple.com/thread/252073619 
> 
> 
> -- 
> Jason Liu
> 
> 
> On Mon, Apr 26, 2021 at 1:42 PM Christopher Jones  > wrote:
> 
> 
>> On 26 Apr 2021, at 6:28 pm, Jason Liu > > wrote:
>> 
>> Thanks Arno :)
>> 
>> I'm kind of surprised that the M1 doesn't seem to support any SSE or AVX
> 
> 
> Thats not at all surprising as those instruction sets are very much specific 
> to X86_64 systems.
> 
> RISC processors, Arm, do have their own sets of SIMD instructions (e.g. 
> Neon), but they are entirely different to those on X86_64 machines. 
> 
> Whether or these are supported on Apple’s M1 processors I have no idea.
> 
> Chris
> 
> 
> 
>> 
>> Does "sysctl machdep.cpu.features" return anything?
>> 
>> -- 
>> Jason Liu
>> 
>> 
>> On Mon, Apr 26, 2021 at 1:23 PM Arno Hautala > > wrote:
>> > On 26 Apr 2021, at 13:20, Jason Liu > > > wrote:
>> > 
>> > sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse”
>> 
>> $ sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse”
>> machdep.cpu.brand_string: Apple M1
>> 
>> -- 
>> arno  s  hautala/-|   a...@alum.wpi.edu 
>> 
>> pgp b2c9d448
>> 
>> 
> 

Re: M1 CPU features

[Jason Liu]

On Mon, Apr 26, 2021 at 1:42 PM Christopher Jones 
wrote:

> Thats not at all surprising as those instruction sets are very much
> specific to X86_64 systems.
>
> RISC processors, Arm, do have their own sets of SIMD instructions (e.g.
> Neon), but they are entirely different to those on X86_64 machines.
>
> Whether or these are supported on Apple’s M1 processors I have no idea.
>

It looks like the M1 supports Neon SIMD instructions, but not SVE SIMD
(which I guess is supposed to be similar to AVX?):

https://discussions.apple.com/thread/252073619

-- 
Jason Liu


On Mon, Apr 26, 2021 at 1:42 PM Christopher Jones 
wrote:

>
>
> On 26 Apr 2021, at 6:28 pm, Jason Liu  wrote:
>
> Thanks Arno :)
>
> I'm kind of surprised that the M1 doesn't seem to support any SSE or
> AVX
>
>
>
> Thats not at all surprising as those instruction sets are very much
> specific to X86_64 systems.
>
> RISC processors, Arm, do have their own sets of SIMD instructions (e.g.
> Neon), but they are entirely different to those on X86_64 machines.
>
> Whether or these are supported on Apple’s M1 processors I have no idea.
>
> Chris
>
>
>
>
> Does "sysctl machdep.cpu.features" return anything?
>
> --
> Jason Liu
>
>
> On Mon, Apr 26, 2021 at 1:23 PM Arno Hautala  wrote:
>
>> > On 26 Apr 2021, at 13:20, Jason Liu  wrote:
>> >
>> > sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i
>> "avx\|sse”
>>
>> $ sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i
>> "avx\|sse”
>> machdep.cpu.brand_string: Apple M1
>>
>> --
>> arno  s  hautala/-|   a...@alum.wpi.edu
>>
>> pgp b2c9d448
>>
>>
>>
>

Re: M1 CPU features

[Christopher Jones]

> On 26 Apr 2021, at 6:28 pm, Jason Liu  wrote:
> 
> Thanks Arno :)
> 
> I'm kind of surprised that the M1 doesn't seem to support any SSE or AVX


Thats not at all surprising as those instruction sets are very much specific to 
X86_64 systems.

RISC processors, Arm, do have their own sets of SIMD instructions (e.g. Neon), 
but they are entirely different to those on X86_64 machines. 

Whether or these are supported on Apple’s M1 processors I have no idea.

Chris



> 
> Does "sysctl machdep.cpu.features" return anything?
> 
> -- 
> Jason Liu
> 
> 
> On Mon, Apr 26, 2021 at 1:23 PM Arno Hautala  > wrote:
> > On 26 Apr 2021, at 13:20, Jason Liu  > > wrote:
> > 
> > sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse”
> 
> $ sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse”
> machdep.cpu.brand_string: Apple M1
> 
> -- 
> arno  s  hautala/-|   a...@alum.wpi.edu 
> 
> pgp b2c9d448
> 
> 



smime.p7s
Description: S/MIME cryptographic signature

Re: M1 CPU features

[Arno Hautala]

> On 26 Apr 2021, at 13:20, Jason Liu  wrote:
> 
> sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse”

$ sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse”
machdep.cpu.brand_string: Apple M1

-- 
arno  s  hautala/-|   a...@alum.wpi.edu

pgp b2c9d448

Re: M1 CPU features

[Gary Palter]

Yes, that’s all it shows …

  - Gary


> On Apr 26, 2021, at 1:30 PM, Jason Liu  wrote:
> 
> That's it?! For all of machdep.cpu?! That's surprisingly minimal :/
> 
> -- 
> Jason Liu
> 
> 
> On Mon, Apr 26, 2021 at 1:25 PM Gary Palter  > wrote:
> [palter@miniMe ~/VLM/IssuesAndWiki.wiki](155)$ sysctl 
> machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse"
> machdep.cpu.brand_string: Apple M1
> [palter@miniMe ~/VLM/IssuesAndWiki.wiki](156)$ sysctl machdep.cpu
> machdep.cpu.cores_per_package: 8
> machdep.cpu.core_count: 8
> machdep.cpu.logical_per_package: 8
> machdep.cpu.thread_count: 8
> machdep.cpu.brand_string: Apple M1
> [palter@miniMe ~/VLM/IssuesAndWiki.wiki](157)$ 
> 
>   - Gary
> 
> 
>> On Apr 26, 2021, at 1:20 PM, Jason Liu > > wrote:
>> 
>> Can someone who owns an M1 Mac run the following command and let me know 
>> what the output is?
>> 
>> sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse"
>> 
>> -- 
>> Jason Liu
> 

Re: M1 CPU features

[Arno Hautala]

> On 26 Apr 2021, at 13:28, Jason Liu  wrote:
> 
> Thanks Arno :)
> 
> I'm kind of surprised that the M1 doesn't seem to support any SSE or AVX
> 
> Does "sysctl machdep.cpu.features" return anything?

Nope, nothing.

-- 
arno  s  hautala/-|   a...@alum.wpi.edu

pgp b2c9d448

Re: M1 CPU features

[Jason Liu]

That's it?! For all of machdep.cpu?! That's surprisingly minimal :/

-- 
Jason Liu


On Mon, Apr 26, 2021 at 1:25 PM Gary Palter  wrote:

> [palter@miniMe ~/VLM/IssuesAndWiki.wiki](155)$ sysctl
> machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse"
> machdep.cpu.brand_string: Apple M1
> [palter@miniMe ~/VLM/IssuesAndWiki.wiki](156)$ sysctl machdep.cpu
> machdep.cpu.cores_per_package: 8
> machdep.cpu.core_count: 8
> machdep.cpu.logical_per_package: 8
> machdep.cpu.thread_count: 8
> machdep.cpu.brand_string: Apple M1
> [palter@miniMe ~/VLM/IssuesAndWiki.wiki](157)$
>
>   - Gary
>
>
> On Apr 26, 2021, at 1:20 PM, Jason Liu  wrote:
>
> Can someone who owns an M1 Mac run the following command and let me know
> what the output is?
>
> sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse"
>
> --
> Jason Liu
>
>
>

Re: M1 CPU features

[Jason Liu]

Thanks Arno :)

I'm kind of surprised that the M1 doesn't seem to support any SSE or AVX

Does "sysctl machdep.cpu.features" return anything?

-- 
Jason Liu


On Mon, Apr 26, 2021 at 1:23 PM Arno Hautala  wrote:

> > On 26 Apr 2021, at 13:20, Jason Liu  wrote:
> >
> > sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse”
>
> $ sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse”
> machdep.cpu.brand_string: Apple M1
>
> --
> arno  s  hautala/-|   a...@alum.wpi.edu
>
> pgp b2c9d448
>
>
>

Re: M1 CPU features

[Gary Palter]

[palter@miniMe ~/VLM/IssuesAndWiki.wiki](155)$ sysctl machdep.cpu.brand_string 
; sysctl machdep.cpu | grep -i "avx\|sse"
machdep.cpu.brand_string: Apple M1
[palter@miniMe ~/VLM/IssuesAndWiki.wiki](156)$ sysctl machdep.cpu
machdep.cpu.cores_per_package: 8
machdep.cpu.core_count: 8
machdep.cpu.logical_per_package: 8
machdep.cpu.thread_count: 8
machdep.cpu.brand_string: Apple M1
[palter@miniMe ~/VLM/IssuesAndWiki.wiki](157)$ 

  - Gary


> On Apr 26, 2021, at 1:20 PM, Jason Liu  > wrote:
> 
> Can someone who owns an M1 Mac run the following command and let me know what 
> the output is?
> 
> sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse"
> 
> -- 
> Jason Liu

M1 CPU features

[Jason Liu]

Can someone who owns an M1 Mac run the following command and let me know
what the output is?

sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse"

-- 
Jason Liu

Re: GitHub CI Jobs Failing During MacPorts Bootstrap

[Christopher Jones]

See the mail Ryan sent a few days back

The Bintray service will cease to exist on May 1. Our pull request CI checks 
rely on being able to download certain assets from Bintray, so unless we do 
something to fix this before then, our pull request CI checks will no longer 
work as of May 1.

https://jfrog.com/blog/into-the-sunset-bintray-jcenter-gocenter-and-chartcenter/
 


looks like today is

"We will have some short service brown-outs to remind users about the services 
that are going away on May 1st. (Specific hours will be advertised in the 
Bintray status page.)”

Chris

> On 26 Apr 2021, at 5:35 pm, Christopher Nielsen  
> wrote:
> 
> I’m seeing the following failures in the CI jobs, during the MacPorts 
> Bootstrap phase:
> 
> Installing MacPorts
> Fetching...
> curl: (22) The requested URL returned error: 403 Forbidden
> curl: (22) The requested URL returned error: 403 Forbidden
> Error: Process completed with exit code 22.
> 
> Any thoughts/ideas…?



smime.p7s
Description: S/MIME cryptographic signature

GitHub CI Jobs Failing During MacPorts Bootstrap

[Christopher Nielsen]

I’m seeing the following failures in the CI jobs, during the MacPorts Bootstrap 
phase:

Installing MacPorts
Fetching...
curl: (22) The requested URL returned error: 403 Forbidden
curl: (22) The requested URL returned error: 403 Forbidden
Error: Process completed with exit code 22.

Any thoughts/ideas…?