Mesa (master): nouveau: avoid build failures since 0fc21ecf
Module: Mesa
Branch: master
Commit: c4cbaca327174135e28353c3438241b08bf96755
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c4cbaca327174135e28353c3438241b08bf96755
Author: Ilia Mirkin imir...@alum.mit.edu
Date: Wed Aug 26 14:04:03 2015 -0400
nouveau: avoid build failures since 0fc21ecf
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
src/gallium/drivers/nouveau/nv30/nv30_context.c |2 +-
src/gallium/drivers/nouveau/nv50/nv50_context.c |2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_context.c |2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_context.c
b/src/gallium/drivers/nouveau/nv30/nv30_context.c
index 46590ee..a36fd57 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_context.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_context.c
@@ -190,7 +190,7 @@ nv30_context_destroy(struct pipe_context *pipe)
} while(0)
struct pipe_context *
-nv30_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
+nv30_context_create(struct pipe_screen *pscreen, void *priv, unsigned ctxflags)
{
struct nv30_screen *screen = nv30_screen(pscreen);
struct nv30_context *nv30 = CALLOC_STRUCT(nv30_context);
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_context.c
b/src/gallium/drivers/nouveau/nv50/nv50_context.c
index 11638dd..4949459 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_context.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_context.c
@@ -240,7 +240,7 @@ nv50_context_get_sample_position(struct pipe_context *,
unsigned, unsigned,
float *);
struct pipe_context *
-nv50_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
+nv50_create(struct pipe_screen *pscreen, void *priv, unsigned ctxflags)
{
struct nv50_screen *screen = nv50_screen(pscreen);
struct nv50_context *nv50;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
index 613cad6..f7604f1 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
@@ -262,7 +262,7 @@ nvc0_context_get_sample_position(struct pipe_context *,
unsigned, unsigned,
float *);
struct pipe_context *
-nvc0_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
+nvc0_create(struct pipe_screen *pscreen, void *priv, unsigned ctxflags)
{
struct nvc0_screen *screen = nvc0_screen(pscreen);
struct nvc0_context *nvc0;
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Mesa (master): gallium: add flags parameter to pipe_screen::context_create
Module: Mesa
Branch: master
Commit: 0fc21ecfc0891d239f20bf7724e51bc75503570c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0fc21ecfc0891d239f20bf7724e51bc75503570c
Author: Marek Olšák marek.ol...@amd.com
Date: Sat Jul 25 18:40:59 2015 +0200
gallium: add flags parameter to pipe_screen::context_create
This allows creating compute-only and debug contexts.
Reviewed-by: Brian Paul bri...@vmware.com
Acked-by: Christian König christian.koe...@amd.com
Acked-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/auxiliary/util/u_tests.c |2 +-
src/gallium/auxiliary/vl/vl_mpeg12_decoder.c |2 +-
src/gallium/drivers/freedreno/a2xx/fd2_context.c |2 +-
src/gallium/drivers/freedreno/a2xx/fd2_context.h |2 +-
src/gallium/drivers/freedreno/a3xx/fd3_context.c |2 +-
src/gallium/drivers/freedreno/a3xx/fd3_context.h |2 +-
src/gallium/drivers/freedreno/a4xx/fd4_context.c |2 +-
src/gallium/drivers/freedreno/a4xx/fd4_context.h |2 +-
src/gallium/drivers/i915/i915_context.c |2 +-
src/gallium/drivers/i915/i915_context.h |2 +-
src/gallium/drivers/ilo/ilo_context.c |2 +-
src/gallium/drivers/llvmpipe/lp_context.c |3 ++-
src/gallium/drivers/llvmpipe/lp_context.h |3 ++-
src/gallium/drivers/noop/noop_pipe.c |3 ++-
src/gallium/drivers/nouveau/nv30/nv30_context.c |2 +-
src/gallium/drivers/nouveau/nv30/nv30_context.h |2 +-
src/gallium/drivers/nouveau/nv50/nv50_context.c |2 +-
src/gallium/drivers/nouveau/nv50/nv50_context.h |2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_context.c |2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_context.h |2 +-
src/gallium/drivers/r300/r300_context.c |2 +-
src/gallium/drivers/r300/r300_context.h |2 +-
src/gallium/drivers/r600/r600_pipe.c |5 +++--
src/gallium/drivers/radeonsi/si_pipe.c|5 +++--
src/gallium/drivers/rbug/rbug_screen.c|6 +++---
src/gallium/drivers/softpipe/sp_context.c |4 ++--
src/gallium/drivers/softpipe/sp_context.h |2 +-
src/gallium/drivers/svga/svga_context.c |4 ++--
src/gallium/drivers/svga/svga_context.h |2 +-
src/gallium/drivers/trace/tr_screen.c |7 +--
src/gallium/drivers/vc4/vc4_context.c |2 +-
src/gallium/drivers/vc4/vc4_context.h |2 +-
src/gallium/include/pipe/p_defines.h | 15 +++
src/gallium/include/pipe/p_screen.h | 11 +--
src/gallium/state_trackers/clover/core/queue.cpp |2 +-
src/gallium/state_trackers/glx/xlib/xm_st.c |2 +-
src/gallium/state_trackers/nine/device9.c |2 +-
src/gallium/state_trackers/omx/vid_dec.c |2 +-
src/gallium/state_trackers/omx/vid_enc.c |4 ++--
src/gallium/state_trackers/va/context.c |3 ++-
src/gallium/state_trackers/vdpau/device.c |2 +-
src/gallium/state_trackers/xa/xa_context.c|2 +-
src/gallium/state_trackers/xvmc/context.c |2 +-
src/gallium/tests/graw/clear.c|2 +-
src/gallium/tests/graw/fs-test.c |2 +-
src/gallium/tests/graw/graw_util.h|2 +-
src/gallium/tests/graw/gs-test.c |2 +-
src/gallium/tests/graw/quad-sample.c |2 +-
src/gallium/tests/graw/shader-leak.c |2 +-
src/gallium/tests/graw/tri-gs.c |2 +-
src/gallium/tests/graw/tri-instanced.c|2 +-
src/gallium/tests/graw/vs-test.c |2 +-
src/gallium/tests/trivial/compute.c |2 +-
src/gallium/tests/trivial/quad-tex.c |2 +-
src/gallium/tests/trivial/tri.c |2 +-
src/gallium/winsys/sw/wrapper/wrapper_sw_winsys.c |2 +-
src/mesa/state_tracker/st_manager.c |2 +-
57 files changed, 96 insertions(+), 65 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_tests.c
b/src/gallium/auxiliary/util/u_tests.c
index 6a489d6..a94e5cc 100644
--- a/src/gallium/auxiliary/util/u_tests.c
+++ b/src/gallium/auxiliary/util/u_tests.c
@@ -457,7 +457,7 @@ null_constant_buffer(struct pipe_context *ctx)
void
util_run_tests(struct pipe_screen *screen)
{
- struct pipe_context *ctx = screen-context_create(screen, NULL);
+ struct pipe_context *ctx = screen-context_create(screen, NULL, 0);
tgsi_vs_window_space_position(ctx);
null_sampler_view(ctx, TGSI_TEXTURE_2D);
diff --git a/src/gallium/auxiliary/vl/vl_mpeg12_decoder.c
b/src/gallium/auxiliary/vl/vl_mpeg12_decoder.c
index b700983..9d0e4a1 100644
--- a/src/gallium/auxiliary/vl/vl_mpeg12_decoder.c
+++ b/src/gallium/auxiliary/vl/vl_mpeg12_decoder.c
@@ -1120,7 +1120,7 @@ vl_create_mpeg12_decoder(struct pipe_context *context,
dec-base = *templat;
Mesa (master): radeonsi: generate register and packet tables for an IB parser from sid.h
Module: Mesa
Branch: master
Commit: a6a6c68955bb8526aac3c04af96fdfdee71bc8bc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a6a6c68955bb8526aac3c04af96fdfdee71bc8bc
Author: Marek Olšák marek.ol...@amd.com
Date: Sat Aug 15 23:44:04 2015 +0200
radeonsi: generate register and packet tables for an IB parser from sid.h
This makes writing a good IB parser a lot easier.
It generates 2 tables:
- packet3 table
- register table with all registers, fields, and named values
Acked-by: Christian König christian.koe...@amd.com
Acked-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/radeonsi/.gitignore |1 +
src/gallium/drivers/radeonsi/Makefile.am |9 ++
src/gallium/drivers/radeonsi/Makefile.sources |1 +
src/gallium/drivers/radeonsi/sid_tables.py| 179 +
4 files changed, 190 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/.gitignore
b/src/gallium/drivers/radeonsi/.gitignore
new file mode 100644
index 000..e0ee798
--- /dev/null
+++ b/src/gallium/drivers/radeonsi/.gitignore
@@ -0,0 +1 @@
+sid_tables.h
diff --git a/src/gallium/drivers/radeonsi/Makefile.am
b/src/gallium/drivers/radeonsi/Makefile.am
index aa79c5e..ae5035a 100644
--- a/src/gallium/drivers/radeonsi/Makefile.am
+++ b/src/gallium/drivers/radeonsi/Makefile.am
@@ -31,3 +31,12 @@ AM_CFLAGS = \
noinst_LTLIBRARIES = libradeonsi.la
libradeonsi_la_SOURCES = $(C_SOURCES)
+
+sid_tables.h: $(srcdir)/sid_tables.py $(srcdir)/sid.h
+ $(AM_V_GEN) $(PYTHON2) $(srcdir)/sid_tables.py $(srcdir)/sid.h $@
+
+EXTRA_DIST = \
+ sid_tables.py
+
+BUILT_SOURCES =\
+ sid_tables.h
diff --git a/src/gallium/drivers/radeonsi/Makefile.sources
b/src/gallium/drivers/radeonsi/Makefile.sources
index ae8fe59..fd44807 100644
--- a/src/gallium/drivers/radeonsi/Makefile.sources
+++ b/src/gallium/drivers/radeonsi/Makefile.sources
@@ -7,6 +7,7 @@ C_SOURCES := \
si_debug.c \
si_descriptors.c \
sid.h \
+ sid_tables.h \
si_dma.c \
si_hw_context.c \
si_pipe.c \
diff --git a/src/gallium/drivers/radeonsi/sid_tables.py
b/src/gallium/drivers/radeonsi/sid_tables.py
new file mode 100755
index 000..1fe5d3c
--- /dev/null
+++ b/src/gallium/drivers/radeonsi/sid_tables.py
@@ -0,0 +1,179 @@
+#!/usr/bin/env python
+
+CopyRight = '''
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+'''
+
+import sys
+import re
+
+
+class Field:
+def __init__(self, reg, s_name):
+self.s_name = s_name
+self.name = strip_prefix(s_name)
+self.values = []
+self.varname_values = '%s__%s__values' % (reg.r_name.lower(),
self.name.lower())
+
+class Reg:
+def __init__(self, r_name):
+self.r_name = r_name
+self.name = strip_prefix(r_name)
+self.fields = []
+self.varname_fields = '%s__fields' % self.r_name.lower()
+self.own_fields = True
+
+
+def strip_prefix(s):
+'''Strip prefix in the form ._.*_, e.g. R_001234_'''
+return s[s[2:].find('_')+3:]
+
+
+def parse(filename):
+stream = open(filename)
+regs = []
+packets = []
+
+for line in stream:
+if not line.startswith('#define '):
+continue
+
+line = line[8:].strip()
+
+if line.startswith('R_'):
+reg = Reg(line.split()[0])
+regs.append(reg)
+
+elif line.startswith('S_'):
+field = Field(reg, line[:line.find('(')])
+reg.fields.append(field)
+
+elif line.startswith('V_'):
+field.values.append(line.split()[0])
+
+elif line.startswith('PKT3_') and line.find('0x') != -1 and
line.find('(') == -1:
+packets.append(line.split()[0])
+
+# Copy fields to indexed registers which have their fields only defined
+# at register index 0.
+# For example, copy fields
Mesa (master): radeonsi: remove old CS tracing code
Module: Mesa
Branch: master
Commit: 189953ee13ad7d6b5d9d04ac21a230e8137a700d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=189953ee13ad7d6b5d9d04ac21a230e8137a700d
Author: Marek Olšák marek.ol...@amd.com
Date: Mon Aug 17 19:17:16 2015 +0200
radeonsi: remove old CS tracing code
Some of it is left there and it will be re-used in the next commit.
Acked-by: Christian König christian.koe...@amd.com
Acked-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/radeonsi/si_hw_context.c | 25 +
src/gallium/drivers/radeonsi/si_pipe.h |5 -
src/gallium/drivers/radeonsi/si_pm4.c| 12
src/gallium/drivers/radeonsi/si_state.h |1 +
src/gallium/drivers/radeonsi/si_state_draw.c |7 +--
5 files changed, 3 insertions(+), 47 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c
b/src/gallium/drivers/radeonsi/si_hw_context.c
index f848c64..b726eb3 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -88,11 +88,8 @@ void si_need_cs_space(struct si_context *ctx, unsigned
num_dw,
/* Count in framebuffer cache flushes at the end of CS. */
num_dw += ctx-atoms.s.cache_flush-num_dw;
-#if SI_TRACE_CS
- if (ctx-screen-b.trace_bo) {
+ if (ctx-screen-b.trace_bo)
num_dw += SI_TRACE_CS_DWORDS;
- }
-#endif
/* Flush if there's not enough space. */
if (num_dw cs-max_dw) {
@@ -146,26 +143,6 @@ void si_context_gfx_flush(void *context, unsigned flags,
if (fence)
ws-fence_reference(fence, ctx-last_gfx_fence);
-#if SI_TRACE_CS
- if (ctx-screen-b.trace_bo) {
- struct si_screen *sscreen = ctx-screen;
- unsigned i;
-
- for (i = 0; i 10; i++) {
- usleep(5);
- if (!ws-buffer_is_busy(sscreen-b.trace_bo-buf,
RADEON_USAGE_READWRITE)) {
- break;
- }
- }
- if (i == 10) {
- fprintf(stderr, timeout on cs lockup likely happen at
cs %d dw %d\n,
- sscreen-b.trace_ptr[1],
sscreen-b.trace_ptr[0]);
- } else {
- fprintf(stderr, cs %d executed in %dms\n,
sscreen-b.trace_ptr[1], i * 5);
- }
- }
-#endif
-
si_begin_new_cs(ctx);
}
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index 3672fec..09a21ce 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -43,7 +43,6 @@
#define SI_RESTART_INDEX_UNKNOWN INT_MIN
#define SI_NUM_SMOOTH_AA_SAMPLES 8
-#define SI_TRACE_CS 0
#define SI_TRACE_CS_DWORDS 6
#define SI_MAX_DRAW_CS_DWORDS \
@@ -298,10 +297,6 @@ void si_context_gfx_flush(void *context, unsigned flags,
void si_begin_new_cs(struct si_context *ctx);
void si_need_cs_space(struct si_context *ctx, unsigned num_dw, boolean
count_draw_in);
-#if SI_TRACE_CS
-void si_trace_emit(struct si_context *sctx);
-#endif
-
/* si_compute.c */
void si_init_compute_functions(struct si_context *sctx);
diff --git a/src/gallium/drivers/radeonsi/si_pm4.c
b/src/gallium/drivers/radeonsi/si_pm4.c
index e9b9a5f..036d90c 100644
--- a/src/gallium/drivers/radeonsi/si_pm4.c
+++ b/src/gallium/drivers/radeonsi/si_pm4.c
@@ -135,12 +135,6 @@ unsigned si_pm4_dirty_dw(struct si_context *sctx)
continue;
count += state-ndw;
-#if SI_TRACE_CS
- /* for tracing each states */
- if (sctx-screen-b.trace_bo) {
- count += SI_TRACE_CS_DWORDS;
- }
-#endif
}
return count;
@@ -161,12 +155,6 @@ void si_pm4_emit(struct si_context *sctx, struct
si_pm4_state *state)
}
cs-cdw += state-ndw;
-
-#if SI_TRACE_CS
- if (sctx-screen-b.trace_bo) {
- si_trace_emit(sctx);
- }
-#endif
}
void si_pm4_emit_dirty(struct si_context *sctx)
diff --git a/src/gallium/drivers/radeonsi/si_state.h
b/src/gallium/drivers/radeonsi/si_state.h
index b8f63c5..118c562 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -281,6 +281,7 @@ extern const struct r600_atom si_atom_msaa_sample_locs;
extern const struct r600_atom si_atom_msaa_config;
void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom
*atom);
void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
+void si_trace_emit(struct si_context *sctx);
/* si_commands.c */
void si_cmd_context_control(struct si_pm4_state *pm4);
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 4c21655..e56c9e7 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++
Mesa (master): radeonsi: save the contents of indirect buffers for debug contexts
Module: Mesa
Branch: master
Commit: be6dc8777662645958d4be6639ee2bb47c5054d8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=be6dc8777662645958d4be6639ee2bb47c5054d8
Author: Marek Olšák marek.ol...@amd.com
Date: Sat Aug 15 12:46:17 2015 +0200
radeonsi: save the contents of indirect buffers for debug contexts
This will be used by the IB parser.
Acked-by: Christian König christian.koe...@amd.com
Acked-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/radeonsi/si_hw_context.c |8
src/gallium/drivers/radeonsi/si_pipe.c |2 ++
src/gallium/drivers/radeonsi/si_pipe.h |5 +
3 files changed, 15 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c
b/src/gallium/drivers/radeonsi/si_hw_context.c
index 307dc39..f848c64 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -130,6 +130,14 @@ void si_context_gfx_flush(void *context, unsigned flags,
/* force to keep tiling flags */
flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
+ /* Save the IB for debug contexts. */
+ if (ctx-is_debug) {
+ free(ctx-last_ib);
+ ctx-last_ib_dw_size = cs-cdw;
+ ctx-last_ib = malloc(cs-cdw * 4);
+ memcpy(ctx-last_ib, cs-buf, cs-cdw * 4);
+ }
+
/* Flush the CS. */
ws-cs_flush(cs, flags, ctx-last_gfx_fence,
ctx-screen-b.cs_count++);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index f6d4a5a..e5900b7 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -81,6 +81,7 @@ static void si_destroy_context(struct pipe_context *context)
LLVMDisposeTargetMachine(sctx-tm);
#endif
+ free(sctx-last_ib);
FREE(sctx);
}
@@ -112,6 +113,7 @@ static struct pipe_context *si_create_context(struct
pipe_screen *screen,
sctx-b.b.destroy = si_destroy_context;
sctx-b.set_atom_dirty = (void *)si_set_atom_dirty;
sctx-screen = sscreen; /* Easy accessing of screen/winsys. */
+ sctx-is_debug = (flags PIPE_CONTEXT_DEBUG) != 0;
if (!r600_common_context_init(sctx-b, sscreen-b))
goto fail;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index 3ab9538..3672fec 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -243,6 +243,11 @@ struct si_context {
struct si_shader_selector *last_tcs;
int last_num_tcs_input_cp;
int last_tes_sh_base;
+
+ /* Debug state. */
+ boolis_debug;
+ uint32_t*last_ib;
+ unsignedlast_ib_dw_size;
};
/* cik_sdma.c */
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Mesa (master): gallium/radeon: read_registers should return bool meaning success or failure
Module: Mesa
Branch: master
Commit: 6924ecac77d1d041420c571de9d31cff1d30aecc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6924ecac77d1d041420c571de9d31cff1d30aecc
Author: Marek Olšák marek.ol...@amd.com
Date: Sat Aug 22 14:17:10 2015 +0200
gallium/radeon: read_registers should return bool meaning success or failure
Acked-by: Christian König christian.koe...@amd.com
Acked-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/radeon/radeon_winsys.h|2 +-
src/gallium/drivers/radeonsi/si_debug.c |4 ++--
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c |6 +++---
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |6 --
4 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index 7ab6e56..a4a2ae1 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -680,7 +680,7 @@ struct radeon_winsys {
uint64_t (*query_value)(struct radeon_winsys *ws,
enum radeon_value_id value);
-void (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
+bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
unsigned num_registers, uint32_t *out);
};
diff --git a/src/gallium/drivers/radeonsi/si_debug.c
b/src/gallium/drivers/radeonsi/si_debug.c
index 22d6f25..d3fd201 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -349,8 +349,8 @@ static void si_dump_mmapped_reg(struct si_context *sctx,
FILE *f,
struct radeon_winsys *ws = sctx-b.ws;
uint32_t value;
- ws-read_registers(ws, offset, 1, value);
- si_dump_reg(f, offset, value, ~0);
+ if (ws-read_registers(ws, offset, 1, value))
+ si_dump_reg(f, offset, value, ~0);
}
static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 012c900..875dcd0 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -350,14 +350,14 @@ static uint64_t amdgpu_query_value(struct radeon_winsys
*rws,
return 0;
}
-static void amdgpu_read_registers(struct radeon_winsys *rws,
+static bool amdgpu_read_registers(struct radeon_winsys *rws,
unsigned reg_offset,
unsigned num_registers, uint32_t *out)
{
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
- amdgpu_read_mm_registers(ws-dev, reg_offset / 4, num_registers,
-0x, 0, out);
+ return amdgpu_read_mm_registers(ws-dev, reg_offset / 4, num_registers,
+ 0x, 0, out) == 0;
}
static unsigned hash_dev(void *key)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index f7784fb..384d728 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -583,7 +583,7 @@ static uint64_t radeon_query_value(struct radeon_winsys
*rws,
return 0;
}
-static void radeon_read_registers(struct radeon_winsys *rws,
+static bool radeon_read_registers(struct radeon_winsys *rws,
unsigned reg_offset,
unsigned num_registers, uint32_t *out)
{
@@ -593,9 +593,11 @@ static void radeon_read_registers(struct radeon_winsys
*rws,
for (i = 0; i num_registers; i++) {
uint32_t reg = reg_offset + i*4;
-radeon_get_drm_value(ws-fd, RADEON_INFO_READ_REG, read-reg, reg);
+if (!radeon_get_drm_value(ws-fd, RADEON_INFO_READ_REG, NULL, reg))
+return false;
out[i] = reg;
}
+return true;
}
static unsigned hash_fd(void *key)
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Mesa (master): radeonsi: add an initial dump_debug_state implementation dumping shaders
Module: Mesa
Branch: master
Commit: 110873ed11342426584a75bf27e85b74035c3b4c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=110873ed11342426584a75bf27e85b74035c3b4c
Author: Marek Olšák marek.ol...@amd.com
Date: Sat Aug 15 23:56:22 2015 +0200
radeonsi: add an initial dump_debug_state implementation dumping shaders
This is usually called after a draw call.
Acked-by: Christian König christian.koe...@amd.com
Acked-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/radeonsi/Makefile.sources |1 +
src/gallium/drivers/radeonsi/si_debug.c | 59 +
src/gallium/drivers/radeonsi/si_pipe.c|1 +
src/gallium/drivers/radeonsi/si_pipe.h|3 ++
4 files changed, 64 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/Makefile.sources
b/src/gallium/drivers/radeonsi/Makefile.sources
index a0b1414..ae8fe59 100644
--- a/src/gallium/drivers/radeonsi/Makefile.sources
+++ b/src/gallium/drivers/radeonsi/Makefile.sources
@@ -4,6 +4,7 @@ C_SOURCES := \
si_commands.c \
si_compute.c \
si_cp_dma.c \
+ si_debug.c \
si_descriptors.c \
sid.h \
si_dma.c \
diff --git a/src/gallium/drivers/radeonsi/si_debug.c
b/src/gallium/drivers/radeonsi/si_debug.c
new file mode 100644
index 000..fa2ec03
--- /dev/null
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Marek Olšák mar...@gmail.com
+ */
+
+#include si_pipe.h
+#include si_shader.h
+#include sid.h
+
+
+static void si_dump_shader(struct si_shader_selector *sel, const char *name,
+ FILE *f)
+{
+ if (!sel || !sel-current)
+ return;
+
+ fprintf(f, %s shader disassembly:\n, name);
+ si_dump_shader_key(sel-type, sel-current-key, f);
+ fprintf(f, %s\n\n, sel-current-binary.disasm_string);
+}
+
+static void si_dump_debug_state(struct pipe_context *ctx, FILE *f,
+ unsigned flags)
+{
+ struct si_context *sctx = (struct si_context*)ctx;
+
+ si_dump_shader(sctx-vs_shader, Vertex, f);
+ si_dump_shader(sctx-tcs_shader, Tessellation control, f);
+ si_dump_shader(sctx-tes_shader, Tessellation evaluation, f);
+ si_dump_shader(sctx-gs_shader, Geometry, f);
+ si_dump_shader(sctx-ps_shader, Fragment, f);
+ fprintf(f, Done.\n);
+}
+
+void si_init_debug_functions(struct si_context *sctx)
+{
+ sctx-b.b.dump_debug_state = si_dump_debug_state;
+}
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 029b3cc..f6d4a5a 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -122,6 +122,7 @@ static struct pipe_context *si_create_context(struct
pipe_screen *screen,
si_init_blit_functions(sctx);
si_init_compute_functions(sctx);
si_init_cp_dma_functions(sctx);
+ si_init_debug_functions(sctx);
if (sscreen-b.info.has_uvd) {
sctx-b.b.create_video_codec = si_uvd_create_decoder;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index 553e1f3..3ab9538 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -275,6 +275,9 @@ void si_copy_buffer(struct si_context *sctx,
bool is_framebuffer);
void si_init_cp_dma_functions(struct si_context *sctx);
+/* si_debug.c */
+void si_init_debug_functions(struct si_context *sctx);
+
/* si_dma.c */
void si_dma_copy(struct pipe_context *ctx,
struct pipe_resource *dst,
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Mesa (master): mesa: remove pointless es31 checks, fix indirect to only be in es31
Module: Mesa
Branch: master
Commit: a3b617a25859ebbfe74b294b7e6bee7af1d24b8c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3b617a25859ebbfe74b294b7e6bee7af1d24b8c
Author: Ilia Mirkin imir...@alum.mit.edu
Date: Mon Aug 24 11:34:42 2015 -0400
mesa: remove pointless es31 checks, fix indirect to only be in es31
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
Reviewed-by: Tapani Pälli tapani.pa...@intel.com
---
src/mesa/main/get.c | 37 +
src/mesa/main/get_hash_params.py | 48 +++---
2 files changed, 25 insertions(+), 60 deletions(-)
diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index c691997..680576c 100644
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
@@ -361,48 +361,13 @@ static const int
extra_ARB_shader_image_load_store_and_tessellation[] = {
EXTRA_END
};
-static const int extra_ARB_draw_indirect_es31[] = {
- EXT(ARB_draw_indirect),
- EXTRA_API_ES31,
- EXTRA_END
-};
-
-static const int extra_ARB_shader_image_load_store_es31[] = {
- EXT(ARB_shader_image_load_store),
- EXTRA_API_ES31,
- EXTRA_END
-};
-
-static const int extra_ARB_shader_atomic_counters_es31[] = {
- EXT(ARB_shader_atomic_counters),
- EXTRA_API_ES31,
- EXTRA_END
-};
-
-static const int extra_ARB_texture_multisample_es31[] = {
- EXT(ARB_texture_multisample),
- EXTRA_API_ES31,
- EXTRA_END
-};
-
-static const int extra_ARB_texture_gather_es31[] = {
- EXT(ARB_texture_gather),
- EXTRA_API_ES31,
- EXTRA_END
-};
-
+/* HACK: remove when ARB_compute_shader is actually supported */
static const int extra_ARB_compute_shader_es31[] = {
EXT(ARB_compute_shader),
EXTRA_API_ES31,
EXTRA_END
};
-static const int extra_ARB_explicit_uniform_location_es31[] = {
- EXT(ARB_explicit_uniform_location),
- EXTRA_API_ES31,
- EXTRA_END
-};
-
EXTRA_EXT(ARB_texture_cube_map);
EXTRA_EXT(EXT_texture_array);
EXTRA_EXT(NV_fog_distance);
diff --git a/src/mesa/main/get_hash_params.py b/src/mesa/main/get_hash_params.py
index 517c391..73213f4 100644
--- a/src/mesa/main/get_hash_params.py
+++ b/src/mesa/main/get_hash_params.py
@@ -410,33 +410,33 @@ descriptor=[
# Enums in OpenGL and ES 3.1
{ apis: [GL, GL_CORE, GLES31], params: [
# GL_ARB_shader_image_load_store / GLES 3.1
- [ MAX_IMAGE_UNITS, CONTEXT_INT(Const.MaxImageUnits),
extra_ARB_shader_image_load_store_es31 ],
- [ MAX_VERTEX_IMAGE_UNIFORMS,
CONTEXT_INT(Const.Program[MESA_SHADER_VERTEX].MaxImageUniforms),
extra_ARB_shader_image_load_store_es31 ],
- [ MAX_FRAGMENT_IMAGE_UNIFORMS,
CONTEXT_INT(Const.Program[MESA_SHADER_FRAGMENT].MaxImageUniforms),
extra_ARB_shader_image_load_store_es31 ],
- [ MAX_COMBINED_IMAGE_UNIFORMS,
CONTEXT_INT(Const.MaxCombinedImageUniforms),
extra_ARB_shader_image_load_store_es31 ],
+ [ MAX_IMAGE_UNITS, CONTEXT_INT(Const.MaxImageUnits),
extra_ARB_shader_image_load_store ],
+ [ MAX_VERTEX_IMAGE_UNIFORMS,
CONTEXT_INT(Const.Program[MESA_SHADER_VERTEX].MaxImageUniforms),
extra_ARB_shader_image_load_store ],
+ [ MAX_FRAGMENT_IMAGE_UNIFORMS,
CONTEXT_INT(Const.Program[MESA_SHADER_FRAGMENT].MaxImageUniforms),
extra_ARB_shader_image_load_store ],
+ [ MAX_COMBINED_IMAGE_UNIFORMS,
CONTEXT_INT(Const.MaxCombinedImageUniforms),
extra_ARB_shader_image_load_store ],
# GL_ARB_shader_atomic_counters / GLES 3.1
- [ ATOMIC_COUNTER_BUFFER_BINDING, LOC_CUSTOM, TYPE_INT, 0,
extra_ARB_shader_atomic_counters_es31 ],
- [ MAX_ATOMIC_COUNTER_BUFFER_BINDINGS,
CONTEXT_INT(Const.MaxAtomicBufferBindings),
extra_ARB_shader_atomic_counters_es31 ],
- [ MAX_ATOMIC_COUNTER_BUFFER_SIZE, CONTEXT_INT(Const.MaxAtomicBufferSize),
extra_ARB_shader_atomic_counters_es31 ],
- [ MAX_VERTEX_ATOMIC_COUNTER_BUFFERS,
CONTEXT_INT(Const.Program[MESA_SHADER_VERTEX].MaxAtomicBuffers),
extra_ARB_shader_atomic_counters_es31 ],
- [ MAX_VERTEX_ATOMIC_COUNTERS,
CONTEXT_INT(Const.Program[MESA_SHADER_VERTEX].MaxAtomicCounters),
extra_ARB_shader_atomic_counters_es31 ],
- [ MAX_FRAGMENT_ATOMIC_COUNTER_BUFFERS,
CONTEXT_INT(Const.Program[MESA_SHADER_FRAGMENT].MaxAtomicBuffers),
extra_ARB_shader_atomic_counters_es31 ],
- [ MAX_FRAGMENT_ATOMIC_COUNTERS,
CONTEXT_INT(Const.Program[MESA_SHADER_FRAGMENT].MaxAtomicCounters),
extra_ARB_shader_atomic_counters_es31 ],
- [ MAX_COMBINED_ATOMIC_COUNTER_BUFFERS,
CONTEXT_INT(Const.MaxCombinedAtomicBuffers),
extra_ARB_shader_atomic_counters_es31 ],
- [ MAX_COMBINED_ATOMIC_COUNTERS,
CONTEXT_INT(Const.MaxCombinedAtomicCounters),
extra_ARB_shader_atomic_counters_es31 ],
+ [ ATOMIC_COUNTER_BUFFER_BINDING, LOC_CUSTOM, TYPE_INT, 0,
extra_ARB_shader_atomic_counters ],
+ [ MAX_ATOMIC_COUNTER_BUFFER_BINDINGS,
CONTEXT_INT(Const.MaxAtomicBufferBindings), extra_ARB_shader_atomic_counters
],
+ [ MAX_ATOMIC_COUNTER_BUFFER_SIZE, CONTEXT_INT(Const.MaxAtomicBufferSize),
extra_ARB_shader_atomic_counters ],
+ [ MAX_VERTEX_ATOMIC_COUNTER_BUFFERS,
CONTEXT_INT(Const.Program[MESA_SHADER_VERTEX].MaxAtomicBuffers),
Mesa (master): mesa: uncomment checks in es31 computation, add texture_ms
Module: Mesa Branch: master Commit: 332fb341dd100f167055d68871a240fd8d416a85 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=332fb341dd100f167055d68871a240fd8d416a85 Author: Ilia Mirkin imir...@alum.mit.edu Date: Mon Aug 24 09:35:04 2015 -0400 mesa: uncomment checks in es31 computation, add texture_ms Signed-off-by: Ilia Mirkin imir...@alum.mit.edu Reviewed-by: Martin Peres martin.pe...@linux.intel.com --- src/mesa/main/version.c |6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/main/version.c b/src/mesa/main/version.c index fd7ae53..f811c1a 100644 --- a/src/mesa/main/version.c +++ b/src/mesa/main/version.c @@ -450,13 +450,15 @@ compute_version_es2(const struct gl_extensions *extensions) extensions-ARB_arrays_of_arrays extensions-ARB_compute_shader extensions-ARB_draw_indirect + extensions-ARB_explicit_uniform_location false /*extensions-ARB_framebuffer_no_attachments*/ extensions-ARB_shader_atomic_counters extensions-ARB_shader_image_load_store - false /*extensions-ARB_shader_image_size*/ - false /*extensions-ARB_shader_storage_buffer_object*/ + extensions-ARB_shader_image_size + extensions-ARB_shader_storage_buffer_object extensions-ARB_shading_language_packing extensions-ARB_stencil_texturing + extensions-ARB_texture_multisample extensions-ARB_gpu_shader5 extensions-EXT_shader_integer_mix); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add IB tracing support for debug contexts
Module: Mesa
Branch: master
Commit: 2c14a6d3b1c53d5814414ce9e91fd8d24c90b787
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c14a6d3b1c53d5814414ce9e91fd8d24c90b787
Author: Marek Olšák marek.ol...@amd.com
Date: Wed Aug 19 11:53:25 2015 +0200
radeonsi: add IB tracing support for debug contexts
This adds trace points to all IBs and the parser prints them and also
prints which trace points were reached (executed) by the CP.
This can help pinpoint a problematic packet, draw call, etc.
Acked-by: Christian König christian.koe...@amd.com
Acked-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/radeonsi/si_debug.c | 67 --
src/gallium/drivers/radeonsi/si_hw_context.c | 24 -
src/gallium/drivers/radeonsi/si_pipe.c |2 +
src/gallium/drivers/radeonsi/si_pipe.h |9 +++-
src/gallium/drivers/radeonsi/si_state_draw.c | 19
5 files changed, 105 insertions(+), 16 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_debug.c
b/src/gallium/drivers/radeonsi/si_debug.c
index 72b7989..cf09686 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -142,7 +142,8 @@ static void si_parse_set_reg_packet(FILE *f, uint32_t *ib,
unsigned count,
si_dump_reg(f, reg + i*4, ib[2+i], ~0);
}
-static uint32_t *si_parse_packet3(FILE *f, uint32_t *ib, int *num_dw)
+static uint32_t *si_parse_packet3(FILE *f, uint32_t *ib, int *num_dw,
+ int trace_id)
{
unsigned count = PKT_COUNT_G(ib[0]);
unsigned op = PKT3_IT_OPCODE_G(ib[0]);
@@ -232,6 +233,36 @@ static uint32_t *si_parse_packet3(FILE *f, uint32_t *ib,
int *num_dw)
if (ib[0] == 0x1000) {
count = -1; /* One dword NOP. */
break;
+ } else if (count == 0 SI_IS_TRACE_POINT(ib[1])) {
+ unsigned packet_id = SI_GET_TRACE_POINT_ID(ib[1]);
+
+ print_spaces(f, INDENT_PKT);
+ fprintf(f, COLOR_RED Trace point ID: %u\n, packet_id);
+
+ if (trace_id == -1)
+ break; /* tracing was disabled */
+
+ print_spaces(f, INDENT_PKT);
+ if (packet_id trace_id)
+ fprintf(f, COLOR_RED
+ This trace point was reached by the
CP.
+ COLOR_RESET \n);
+ else if (packet_id == trace_id)
+ fprintf(f, COLOR_RED
+ ! This is the last trace point
that
+ was reached by the CP !
+ COLOR_RESET \n);
+ else if (packet_id+1 == trace_id)
+ fprintf(f, COLOR_RED
+ ! This is the first trace point
that
+ was NOT been reached by the CP !
+ COLOR_RESET \n);
+ else
+ fprintf(f, COLOR_RED
+ ! This trace point was NOT reached
+ by the CP !
+ COLOR_RESET \n);
+ break;
}
/* fall through, print all dwords */
default:
@@ -246,7 +277,17 @@ static uint32_t *si_parse_packet3(FILE *f, uint32_t *ib,
int *num_dw)
return ib;
}
-static void si_parse_ib(FILE *f, uint32_t *ib, int num_dw)
+/**
+ * Parse and print an IB into a file.
+ *
+ * \param ffile
+ * \param ib IB
+ * \param num_dw size of the IB
+ * \param chip_class chip class
+ * \param trace_id the last trace ID that is known to have been reached
+ * and executed by the CP, typically read from a buffer
+ */
+static void si_parse_ib(FILE *f, uint32_t *ib, int num_dw, int trace_id)
{
fprintf(f, -- IB begin --\n);
@@ -255,7 +296,7 @@ static void si_parse_ib(FILE *f, uint32_t *ib, int num_dw)
switch (type) {
case 3:
- ib = si_parse_packet3(f, ib, num_dw);
+ ib = si_parse_packet3(f, ib, num_dw, trace_id);
break;
case 2:
/* type-2 nop */
@@ -342,9 +383,27 @@ static void si_dump_debug_state(struct pipe_context *ctx,
FILE *f,
si_dump_shader(sctx-ps_shader, Fragment, f);
if (sctx-last_ib) {
- si_parse_ib(f, sctx-last_ib, sctx-last_ib_dw_size);
+ int last_trace_id = -1;
+
+ if (sctx-last_trace_buf) {
+ /* We are expecting that the
Mesa (master): radeonsi: parse and dump status registers on GPU hang
Module: Mesa
Branch: master
Commit: df6a5666b6398613e552f66cd092369b12cce9ed
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=df6a5666b6398613e552f66cd092369b12cce9ed
Author: Marek Olšák marek.ol...@amd.com
Date: Sun Aug 16 00:54:34 2015 +0200
radeonsi: parse and dump status registers on GPU hang
GPU hang detection must be enabled by setting: GALLIUM_DDEBUG=[timeout in ms]
This may print too much information that we might not understand yet,
but some of the bits are very useful.
Acked-by: Christian König christian.koe...@amd.com
Acked-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/radeonsi/si_debug.c | 52 +++
1 file changed, 52 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_debug.c
b/src/gallium/drivers/radeonsi/si_debug.c
index d692547..72b7989 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -278,11 +278,63 @@ static void si_parse_ib(FILE *f, uint32_t *ib, int num_dw)
}
}
+static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f,
+ unsigned offset)
+{
+ struct radeon_winsys *ws = sctx-b.ws;
+ uint32_t value;
+
+ ws-read_registers(ws, offset, 1, value);
+ si_dump_reg(f, offset, value, ~0);
+}
+
+static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
+{
+ if (sctx-screen-b.info.drm_major == 2
+ sctx-screen-b.info.drm_minor 42)
+ return; /* no radeon support */
+
+ fprintf(f, Memory-mapped registers:\n);
+ si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
+
+ /* No other registers can be read on DRM 3.1.0. */
+ if (sctx-screen-b.info.drm_major 3 ||
+ sctx-screen-b.info.drm_minor 1) {
+ fprintf(f, \n);
+ return;
+ }
+
+ si_dump_mmapped_reg(sctx, f, R_008008_GRBM_STATUS2);
+ si_dump_mmapped_reg(sctx, f, R_008014_GRBM_STATUS_SE0);
+ si_dump_mmapped_reg(sctx, f, R_008018_GRBM_STATUS_SE1);
+ si_dump_mmapped_reg(sctx, f, R_008038_GRBM_STATUS_SE2);
+ si_dump_mmapped_reg(sctx, f, R_00803C_GRBM_STATUS_SE3);
+ si_dump_mmapped_reg(sctx, f, R_00D034_SDMA0_STATUS_REG);
+ si_dump_mmapped_reg(sctx, f, R_00D834_SDMA1_STATUS_REG);
+ si_dump_mmapped_reg(sctx, f, R_000E50_SRBM_STATUS);
+ si_dump_mmapped_reg(sctx, f, R_000E4C_SRBM_STATUS2);
+ si_dump_mmapped_reg(sctx, f, R_000E54_SRBM_STATUS3);
+ si_dump_mmapped_reg(sctx, f, R_008680_CP_STAT);
+ si_dump_mmapped_reg(sctx, f, R_008674_CP_STALLED_STAT1);
+ si_dump_mmapped_reg(sctx, f, R_008678_CP_STALLED_STAT2);
+ si_dump_mmapped_reg(sctx, f, R_008670_CP_STALLED_STAT3);
+ si_dump_mmapped_reg(sctx, f, R_008210_CP_CPC_STATUS);
+ si_dump_mmapped_reg(sctx, f, R_008214_CP_CPC_BUSY_STAT);
+ si_dump_mmapped_reg(sctx, f, R_008218_CP_CPC_STALLED_STAT1);
+ si_dump_mmapped_reg(sctx, f, R_00821C_CP_CPF_STATUS);
+ si_dump_mmapped_reg(sctx, f, R_008220_CP_CPF_BUSY_STAT);
+ si_dump_mmapped_reg(sctx, f, R_008224_CP_CPF_STALLED_STAT1);
+ fprintf(f, \n);
+}
+
static void si_dump_debug_state(struct pipe_context *ctx, FILE *f,
unsigned flags)
{
struct si_context *sctx = (struct si_context*)ctx;
+ if (flags PIPE_DEBUG_DEVICE_IS_HUNG)
+ si_dump_debug_registers(sctx, f);
+
si_dump_shader(sctx-vs_shader, Vertex, f);
si_dump_shader(sctx-tcs_shader, Tessellation control, f);
si_dump_shader(sctx-tes_shader, Tessellation evaluation, f);
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Mesa (master): radeonsi: add IB parser support for CP DMA packets
Module: Mesa
Branch: master
Commit: 16e5d8ad388445c2e577406953a403608f1addc5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=16e5d8ad388445c2e577406953a403608f1addc5
Author: Marek Olšák marek.ol...@amd.com
Date: Wed Aug 19 18:45:11 2015 +0200
radeonsi: add IB parser support for CP DMA packets
If the packet encoding is defined in the same format as register definitions,
the python script can process them automatically and the parser support
becomes trivial.
Acked-by: Christian König christian.koe...@amd.com
Acked-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/radeonsi/si_cp_dma.c | 17 ++--
src/gallium/drivers/radeonsi/si_debug.c | 24 +
src/gallium/drivers/radeonsi/si_state_draw.c |6 +-
src/gallium/drivers/radeonsi/sid.h | 136 --
4 files changed, 122 insertions(+), 61 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c
b/src/gallium/drivers/radeonsi/si_cp_dma.c
index f8a9da4..7bdac97 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -47,10 +47,11 @@ static void si_emit_cp_dma_copy_buffer(struct si_context
*sctx,
unsigned size, unsigned flags)
{
struct radeon_winsys_cs *cs = sctx-b.rings.gfx.cs;
- uint32_t sync_flag = flags R600_CP_DMA_SYNC ? PKT3_CP_DMA_CP_SYNC : 0;
- uint32_t raw_wait = flags SI_CP_DMA_RAW_WAIT ?
PKT3_CP_DMA_CMD_RAW_WAIT : 0;
+ uint32_t sync_flag = flags R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
+ uint32_t raw_wait = flags SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
uint32_t sel = flags CIK_CP_DMA_USE_L2 ?
- PKT3_CP_DMA_SRC_SEL(3) | PKT3_CP_DMA_DST_SEL(3) : 0;
+ S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2) |
+ S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
assert(size);
assert((size ((121)-1)) == size);
@@ -79,16 +80,16 @@ static void si_emit_cp_dma_clear_buffer(struct si_context
*sctx,
uint32_t clear_value, unsigned flags)
{
struct radeon_winsys_cs *cs = sctx-b.rings.gfx.cs;
- uint32_t sync_flag = flags R600_CP_DMA_SYNC ? PKT3_CP_DMA_CP_SYNC : 0;
- uint32_t raw_wait = flags SI_CP_DMA_RAW_WAIT ?
PKT3_CP_DMA_CMD_RAW_WAIT : 0;
- uint32_t dst_sel = flags CIK_CP_DMA_USE_L2 ? PKT3_CP_DMA_DST_SEL(3) :
0;
+ uint32_t sync_flag = flags R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
+ uint32_t raw_wait = flags SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
+ uint32_t dst_sel = flags CIK_CP_DMA_USE_L2 ?
S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
assert(size);
assert((size ((121)-1)) == size);
if (sctx-b.chip_class = CIK) {
radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
- radeon_emit(cs, sync_flag | dst_sel | PKT3_CP_DMA_SRC_SEL(2));
/* CP_SYNC [31] | SRC_SEL[30:29] */
+ radeon_emit(cs, sync_flag | dst_sel |
S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
radeon_emit(cs, clear_value); /* DATA [31:0] */
radeon_emit(cs, 0);
radeon_emit(cs, dst_va);/* DST_ADDR_LO [31:0] */
@@ -97,7 +98,7 @@ static void si_emit_cp_dma_clear_buffer(struct si_context
*sctx,
} else {
radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
radeon_emit(cs, clear_value); /* DATA [31:0] */
- radeon_emit(cs, sync_flag | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC
[31] | SRC_SEL[30:29] */
+ radeon_emit(cs, sync_flag | S_411_SRC_SEL(V_411_DATA)); /*
CP_SYNC [31] | SRC_SEL[30:29] */
radeon_emit(cs, dst_va);/* DST_ADDR_LO
[31:0] */
radeon_emit(cs, (dst_va 32) 0x); /* DST_ADDR_HI
[15:0] */
radeon_emit(cs, size | raw_wait); /* COMMAND
[29:22] | BYTE_COUNT [20:0] */
diff --git a/src/gallium/drivers/radeonsi/si_debug.c
b/src/gallium/drivers/radeonsi/si_debug.c
index cf09686..22d6f25 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -229,6 +229,30 @@ static uint32_t *si_parse_packet3(FILE *f, uint32_t *ib,
int *num_dw,
case PKT3_NUM_INSTANCES:
si_dump_reg(f, R_030934_VGT_NUM_INSTANCES, ib[1], ~0);
break;
+ case PKT3_WRITE_DATA:
+ si_dump_reg(f, R_370_CONTROL, ib[1], ~0);
+ si_dump_reg(f, R_371_DST_ADDR_LO, ib[2], ~0);
+ si_dump_reg(f, R_372_DST_ADDR_HI, ib[3], ~0);
+ for (i = 2; i count; i++) {
+ print_spaces(f, INDENT_PKT);
+ fprintf(f, 0x%08x\n, ib[2+i]);
+ }
+ break;
+ case PKT3_CP_DMA:
+ si_dump_reg(f, R_410_CP_DMA_WORD0, ib[1], ~0);
+ si_dump_reg(f,
Mesa (master): radeonsi: allow si_dump_key to write to a file
Module: Mesa
Branch: master
Commit: 93d97db3492cc1af8fb401ed5eb6766e608f744e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=93d97db3492cc1af8fb401ed5eb6766e608f744e
Author: Marek Olšák marek.ol...@amd.com
Date: Sat Jul 11 13:13:07 2015 +0200
radeonsi: allow si_dump_key to write to a file
Acked-by: Christian König christian.koe...@amd.com
Acked-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/radeonsi/si_shader.c | 36 +++---
src/gallium/drivers/radeonsi/si_shader.h |1 +
2 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 6b70a8f..98b4289 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -3964,48 +3964,48 @@ static int si_generate_gs_copy_shader(struct si_screen
*sscreen,
return r;
}
-static void si_dump_key(unsigned shader, union si_shader_key *key)
+void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
{
int i;
- fprintf(stderr, SHADER KEY\n);
+ fprintf(f, SHADER KEY\n);
switch (shader) {
case PIPE_SHADER_VERTEX:
- fprintf(stderr, instance_divisors = {);
+ fprintf(f, instance_divisors = {);
for (i = 0; i Elements(key-vs.instance_divisors); i++)
- fprintf(stderr, !i ? %u : , %u,
+ fprintf(f, !i ? %u : , %u,
key-vs.instance_divisors[i]);
- fprintf(stderr, }\n);
+ fprintf(f, }\n);
if (key-vs.as_es)
- fprintf(stderr, es_enabled_outputs = 0x%PRIx64\n,
+ fprintf(f, es_enabled_outputs = 0x%PRIx64\n,
key-vs.es_enabled_outputs);
- fprintf(stderr, as_es = %u\n, key-vs.as_es);
- fprintf(stderr, as_ls = %u\n, key-vs.as_ls);
+ fprintf(f, as_es = %u\n, key-vs.as_es);
+ fprintf(f, as_ls = %u\n, key-vs.as_ls);
break;
case PIPE_SHADER_TESS_CTRL:
- fprintf(stderr, prim_mode = %u\n, key-tcs.prim_mode);
+ fprintf(f, prim_mode = %u\n, key-tcs.prim_mode);
break;
case PIPE_SHADER_TESS_EVAL:
if (key-tes.as_es)
- fprintf(stderr, es_enabled_outputs = 0x%PRIx64\n,
+ fprintf(f, es_enabled_outputs = 0x%PRIx64\n,
key-tes.es_enabled_outputs);
- fprintf(stderr, as_es = %u\n, key-tes.as_es);
+ fprintf(f, as_es = %u\n, key-tes.as_es);
break;
case PIPE_SHADER_GEOMETRY:
break;
case PIPE_SHADER_FRAGMENT:
- fprintf(stderr, export_16bpc = 0x%X\n,
key-ps.export_16bpc);
- fprintf(stderr, last_cbuf = %u\n, key-ps.last_cbuf);
- fprintf(stderr, color_two_side = %u\n,
key-ps.color_two_side);
- fprintf(stderr, alpha_func = %u\n, key-ps.alpha_func);
- fprintf(stderr, alpha_to_one = %u\n, key-ps.alpha_to_one);
- fprintf(stderr, poly_stipple = %u\n, key-ps.poly_stipple);
+ fprintf(f, export_16bpc = 0x%X\n, key-ps.export_16bpc);
+ fprintf(f, last_cbuf = %u\n, key-ps.last_cbuf);
+ fprintf(f, color_two_side = %u\n, key-ps.color_two_side);
+ fprintf(f, alpha_func = %u\n, key-ps.alpha_func);
+ fprintf(f, alpha_to_one = %u\n, key-ps.alpha_to_one);
+ fprintf(f, poly_stipple = %u\n, key-ps.poly_stipple);
break;
default:
@@ -4036,7 +4036,7 @@ int si_shader_create(struct si_screen *sscreen,
LLVMTargetMachineRef tm,
/* Dump TGSI code before doing TGSI-LLVM conversion in case the
* conversion fails. */
if (dump !(sscreen-b.debug_flags DBG_NO_TGSI)) {
- si_dump_key(sel-type, shader-key);
+ si_dump_shader_key(sel-type, shader-key, stderr);
tgsi_dump(tokens, 0);
si_dump_streamout(sel-so);
}
diff --git a/src/gallium/drivers/radeonsi/si_shader.h
b/src/gallium/drivers/radeonsi/si_shader.h
index cd845c1..423b849 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -304,6 +304,7 @@ static inline bool si_vs_exports_prim_id(struct si_shader
*shader)
/* radeonsi_shader.c */
int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
struct si_shader *shader);
+void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f);
int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
LLVMTargetMachineRef tm, LLVMModuleRef mod);
void si_shader_destroy(struct pipe_context
Mesa (master): gallium/ddebug: new pipe for hang detection and driver state dumping (v2)
Module: Mesa Branch: master Commit: 525921ed51176255474c73adacfc6801a7bf2783 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=525921ed51176255474c73adacfc6801a7bf2783 Author: Marek Olšák marek.ol...@amd.com Date: Sat Jul 4 14:10:21 2015 +0200 gallium/ddebug: new pipe for hang detection and driver state dumping (v2) v2: lots of improvements This is like identity or trace, but simpler. It doesn't wrap most states. Run with: GALLIUM_DDEBUG=1000 [executable] where executable is the app and 1000 is in miliseconds, meaning that the context will be considered hung if a fence fails to signal in 1000 ms. If that happens, all shaders, context states, bound resources, draw parameters, and driver debug information (if any) will be dumped into: /home/$username/dd_dumps/$processname_$pid_$index. Note that the context is flushed after every draw/clear/copy/blit operation and then waited for to find the exact call that hangs. You can also do: GALLIUM_DDEBUG=always to do the dumping after every draw/clear/copy/blit operation without flushing and waiting. Examples of driver states that can be dumped are: - Hardware status registers saying which hw block is busy (hung). - Disassembled shaders in a human-readable form. - The last submitted command buffer in a human-readable form. v2: drop pipe-loader changes, drop SConscript rename dd.h - dd_pipe.h Acked-by: Christian König christian.koe...@amd.com Acked-by: Alex Deucher alexander.deuc...@amd.com --- configure.ac |1 + src/gallium/Makefile.am|1 + .../auxiliary/target-helpers/inline_debug_helper.h |8 + src/gallium/drivers/ddebug/Makefile.am |9 + src/gallium/drivers/ddebug/Makefile.sources|6 + src/gallium/drivers/ddebug/dd_context.c| 771 +++ src/gallium/drivers/ddebug/dd_draw.c | 807 src/gallium/drivers/ddebug/dd_pipe.h | 141 src/gallium/drivers/ddebug/dd_public.h | 36 + src/gallium/drivers/ddebug/dd_screen.c | 353 + src/gallium/targets/dri/Makefile.am|2 + 11 files changed, 2135 insertions(+) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=525921ed51176255474c73adacfc6801a7bf2783 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: remove duplicated register definitions and instruction definitions
Module: Mesa Branch: master Commit: d15b71b4bd419f5bee0e7fcb21d4608edf70 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d15b71b4bd419f5bee0e7fcb21d4608edf70 Author: Marek Olšák marek.ol...@amd.com Date: Sat Aug 15 18:48:06 2015 +0200 radeonsi: remove duplicated register definitions and instruction definitions Instruction encoding isn't needed in Mesa. The border color address registers were duplicated. Acked-by: Christian König christian.koe...@amd.com Acked-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/radeonsi/sid.h | 3160 1 file changed, 3160 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=d15b71b4bd419f5bee0e7fcb21d4608edf70 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): gallium: add an interface for dumping debug driver state
Module: Mesa
Branch: master
Commit: 7b5c92391f15533ec02327d617c4e8639a2f8bb4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b5c92391f15533ec02327d617c4e8639a2f8bb4
Author: Marek Olšák marek.ol...@amd.com
Date: Sat Jul 11 12:34:46 2015 +0200
gallium: add an interface for dumping debug driver state
Reviewed-by: Brian Paul bri...@vmware.com
Acked-by: Christian König christian.koe...@amd.com
Acked-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/include/pipe/p_context.h | 12
src/gallium/include/pipe/p_defines.h |5 +
2 files changed, 17 insertions(+)
diff --git a/src/gallium/include/pipe/p_context.h
b/src/gallium/include/pipe/p_context.h
index f89dae9..9d8f5bd 100644
--- a/src/gallium/include/pipe/p_context.h
+++ b/src/gallium/include/pipe/p_context.h
@@ -32,6 +32,7 @@
#include p_format.h
#include p_video_enums.h
#include p_defines.h
+#include stdio.h
#ifdef __cplusplus
extern C {
@@ -617,6 +618,17 @@ struct pipe_context {
* Return information about unexpected device resets.
*/
enum pipe_reset_status (*get_device_reset_status)(struct pipe_context *ctx);
+
+ /**
+* Dump driver-specific debug information into a stream. This is
+* used by debugging tools.
+*
+* \param ctxpipe context
+* \param stream where the output should be written to
+* \param flags a mask of PIPE_DEBUG_* flags
+*/
+ void (*dump_debug_state)(struct pipe_context *ctx, FILE *stream,
+unsigned flags);
};
diff --git a/src/gallium/include/pipe/p_defines.h
b/src/gallium/include/pipe/p_defines.h
index 2ba56ea..4f2aa14 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -329,6 +329,11 @@ enum pipe_flush_flags
};
/**
+ * Flags for pipe_context::dump_debug_state.
+ */
+#define PIPE_DEBUG_DEVICE_IS_HUNG (1 0)
+
+/**
* Flags for pipe_context::memory_barrier.
*/
#define PIPE_BARRIER_MAPPED_BUFFER (1 0)
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Mesa (master): r600g,radeonsi: remove unused ill-formed register field definitions
Module: Mesa Branch: master Commit: c59ad265df655a19285d813144f6b76d7f49d7fd URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c59ad265df655a19285d813144f6b76d7f49d7fd Author: Marek Olšák marek.ol...@amd.com Date: Sat Aug 15 18:43:27 2015 +0200 r600g,radeonsi: remove unused ill-formed register field definitions Acked-by: Christian König christian.koe...@amd.com Acked-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/r600/r600d.h |1 - src/gallium/drivers/radeonsi/sid.h |1 - 2 files changed, 2 deletions(-) diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h index bce8b4e..3c08ba5 100644 --- a/src/gallium/drivers/r600/r600d.h +++ b/src/gallium/drivers/r600/r600d.h @@ -3428,7 +3428,6 @@ #define S_0085F0_SO3_DEST_BASE_ENA(x)(((x) 0x1) 5) #define G_0085F0_SO3_DEST_BASE_ENA(x)(((x) 5) 0x1) #define C_0085F0_SO3_DEST_BASE_ENA 0xFFDF -#define S_0085F0_CB0_DEST_BASE_ENA_SHIFT 6 #define S_0085F0_CB0_DEST_BASE_ENA(x)(((x) 0x1) 6) #define G_0085F0_CB0_DEST_BASE_ENA(x)(((x) 6) 0x1) #define C_0085F0_CB0_DEST_BASE_ENA 0xFFBF diff --git a/src/gallium/drivers/radeonsi/sid.h b/src/gallium/drivers/radeonsi/sid.h index 66fdf35..05d20db 100644 --- a/src/gallium/drivers/radeonsi/sid.h +++ b/src/gallium/drivers/radeonsi/sid.h @@ -614,7 +614,6 @@ #define S_0085F0_DEST_BASE_1_ENA(x) (((x) 0x1) 1) #define G_0085F0_DEST_BASE_1_ENA(x) (((x) 1) 0x1) #define C_0085F0_DEST_BASE_1_ENA 0xFFFD -#define S_0085F0_CB0_DEST_BASE_ENA_SHIFT 6 #define S_0085F0_CB0_DEST_BASE_ENA(x) (((x) 0x1) 6) #define G_0085F0_CB0_DEST_BASE_ENA(x) (((x) 6) 0x1) #define C_0085F0_CB0_DEST_BASE_ENA 0xFFBF ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add an IB parser
Module: Mesa
Branch: master
Commit: 61df4f0cd3f34ed11dd64932aeb7731d354f2bde
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=61df4f0cd3f34ed11dd64932aeb7731d354f2bde
Author: Marek Olšák marek.ol...@amd.com
Date: Sat Aug 15 23:57:22 2015 +0200
radeonsi: add an IB parser
Acked-by: Christian König christian.koe...@amd.com
Acked-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/radeonsi/si_debug.c | 245 +++
1 file changed, 245 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_debug.c
b/src/gallium/drivers/radeonsi/si_debug.c
index fa2ec03..d692547 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -27,6 +27,7 @@
#include si_pipe.h
#include si_shader.h
#include sid.h
+#include sid_tables.h
static void si_dump_shader(struct si_shader_selector *sel, const char *name,
@@ -40,6 +41,243 @@ static void si_dump_shader(struct si_shader_selector *sel,
const char *name,
fprintf(f, %s\n\n, sel-current-binary.disasm_string);
}
+/* Parsed IBs are difficult to read without colors. Use less -R file to
+ * read them, or use aha -b -f file to convert them to html.
+ */
+#define COLOR_RESET\033[0m
+#define COLOR_RED \033[31m
+#define COLOR_GREEN\033[1;32m
+#define COLOR_YELLOW \033[1;33m
+#define COLOR_CYAN \033[1;36m
+
+#define INDENT_PKT 8
+
+static void print_spaces(FILE *f, unsigned num)
+{
+ fprintf(f, %*s, num, );
+}
+
+static void print_value(FILE *file, uint32_t value, int bits)
+{
+ /* Guess if it's int or float */
+ if (value = (1 15))
+ fprintf(file, %u\n, value);
+ else {
+ float f = uif(value);
+
+ if (fabs(f) 10 f*10 == floor(f*10))
+ fprintf(file, %.1ff\n, f);
+ else
+ /* Don't print more leading zeros than there are bits.
*/
+ fprintf(file, 0x%0*x\n, bits / 4, value);
+ }
+}
+
+static void print_named_value(FILE *file, const char *name, uint32_t value,
+ int bits)
+{
+ print_spaces(file, INDENT_PKT);
+ fprintf(file, COLOR_YELLOW %s COLOR_RESET - , name);
+ print_value(file, value, bits);
+}
+
+static void si_dump_reg(FILE *file, unsigned offset, uint32_t value,
+ uint32_t field_mask)
+{
+ int r, f;
+
+ for (r = 0; r ARRAY_SIZE(reg_table); r++) {
+ const struct si_reg *reg = reg_table[r];
+
+ if (reg-offset == offset) {
+ bool first_field = true;
+
+ print_spaces(file, INDENT_PKT);
+ fprintf(file, COLOR_YELLOW %s COLOR_RESET - ,
+ reg-name);
+
+ if (!reg-num_fields) {
+ print_value(file, value, 32);
+ return;
+ }
+
+ for (f = 0; f reg-num_fields; f++) {
+ const struct si_field *field = reg-fields[f];
+ uint32_t val = (value field-mask)
+ (ffs(field-mask) - 1);
+
+ if (!(field-mask field_mask))
+ continue;
+
+ /* Indent the field. */
+ if (!first_field)
+ print_spaces(file,
+INDENT_PKT +
strlen(reg-name) + 4);
+
+ /* Print the field. */
+ fprintf(file, %s = , field-name);
+
+ if (val field-num_values
field-values[val])
+ fprintf(file, %s\n,
field-values[val]);
+ else
+ print_value(file, val,
+ util_bitcount(field-mask));
+
+ first_field = false;
+ }
+ return;
+ }
+ }
+
+ fprintf(file, COLOR_YELLOW 0x%05x COLOR_RESET = 0x%08x, offset,
value);
+}
+
+static void si_parse_set_reg_packet(FILE *f, uint32_t *ib, unsigned count,
+ unsigned reg_offset)
+{
+ unsigned reg = (ib[1] 2) + reg_offset;
+ int i;
+
+ for (i = 0; i count; i++)
+ si_dump_reg(f, reg + i*4, ib[2+i], ~0);
+}
+
+static uint32_t *si_parse_packet3(FILE *f, uint32_t *ib, int *num_dw)
+{
+ unsigned count = PKT_COUNT_G(ib[0]);
+ unsigned op = PKT3_IT_OPCODE_G(ib[0]);
+ const char *predicate = PKT3_PREDICATE(ib[0]) ? (predicate) : ;
+ int i;
+
+ /* Print the name first. */
+ for (i = 0; i ARRAY_SIZE(packet3_table); i++)
+ if
Mesa (master): mesa: return bool instead of GLboolean in compressedteximage_only_format()
Module: Mesa
Branch: master
Commit: 42ee16176dca797c395592b0245f370ea58ca3a8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=42ee16176dca797c395592b0245f370ea58ca3a8
Author: Nanley Chery nanley.g.ch...@intel.com
Date: Wed Jun 17 17:14:40 2015 -0700
mesa: return bool instead of GLboolean in compressedteximage_only_format()
In agreement with the coding style, functions that aren't directly visible
to the GL API should prefer the use of bool over GLboolean.
Suggested-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/teximage.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 0535db3..8d94903 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -1767,7 +1767,7 @@ _mesa_test_proxy_teximage(struct gl_context *ctx, GLenum
target, GLint level,
/**
* Return true if the format is only valid for glCompressedTexImage.
*/
-static GLboolean
+static bool
compressedteximage_only_format(const struct gl_context *ctx, GLenum format)
{
switch (format) {
@@ -1782,9 +1782,9 @@ compressedteximage_only_format(const struct gl_context
*ctx, GLenum format)
case GL_PALETTE8_R5_G6_B5_OES:
case GL_PALETTE8_RGBA4_OES:
case GL_PALETTE8_RGB5_A1_OES:
- return GL_TRUE;
+ return true;
default:
- return GL_FALSE;
+ return false;
}
}
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Mesa (master): swrast: add a new macro, FETCH_COMPRESSED
Module: Mesa
Branch: master
Commit: 9a759a6ee002203a045e9df1f91823204609fd4a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a759a6ee002203a045e9df1f91823204609fd4a
Author: Nanley Chery nanley.g.ch...@intel.com
Date: Sun May 31 13:29:41 2015 -0700
swrast: add a new macro, FETCH_COMPRESSED
This patch creates a new macro, FETCH_COMPRESSED - similar in nature
to the other FETCH_* macros. This reduces repetition in the code that
deals with compressed textures.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/swrast/s_texfetch.c | 239 --
1 file changed, 41 insertions(+), 198 deletions(-)
diff --git a/src/mesa/swrast/s_texfetch.c b/src/mesa/swrast/s_texfetch.c
index 754d982..acb06e6 100644
--- a/src/mesa/swrast/s_texfetch.c
+++ b/src/mesa/swrast/s_texfetch.c
@@ -116,6 +116,14 @@ static void fetch_null_texelf( const struct
swrast_texture_image *texImage,
NULL \
}
+#define FETCH_COMPRESSED(NAME) \
+ {\
+ MESA_FORMAT_ ## NAME, \
+ fetch_compressed, \
+ fetch_compressed, \
+ fetch_compressed \
+ }
+
/**
* Table to map MESA_FORMAT_ to texel fetch/store funcs.
*/
@@ -344,214 +352,49 @@ texfetch_funcs[] =
FETCH_NULL(RGBX_SINT32),
/* DXT compressed formats */
- {
- MESA_FORMAT_RGB_DXT1,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
- {
- MESA_FORMAT_RGBA_DXT1,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
- {
- MESA_FORMAT_RGBA_DXT3,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
- {
- MESA_FORMAT_RGBA_DXT5,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
+ FETCH_COMPRESSED(RGB_DXT1),
+ FETCH_COMPRESSED(RGBA_DXT1),
+ FETCH_COMPRESSED(RGBA_DXT3),
+ FETCH_COMPRESSED(RGBA_DXT5),
/* DXT sRGB compressed formats */
- {
- MESA_FORMAT_SRGB_DXT1,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
- {
- MESA_FORMAT_SRGBA_DXT1,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
- {
- MESA_FORMAT_SRGBA_DXT3,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
- {
- MESA_FORMAT_SRGBA_DXT5,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
+ FETCH_COMPRESSED(SRGB_DXT1),
+ FETCH_COMPRESSED(SRGBA_DXT1),
+ FETCH_COMPRESSED(SRGBA_DXT3),
+ FETCH_COMPRESSED(SRGBA_DXT5),
/* FXT1 compressed formats */
- {
- MESA_FORMAT_RGB_FXT1,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
- {
- MESA_FORMAT_RGBA_FXT1,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
+ FETCH_COMPRESSED(RGB_FXT1),
+ FETCH_COMPRESSED(RGBA_FXT1),
/* RGTC compressed formats */
- {
- MESA_FORMAT_R_RGTC1_UNORM,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
- {
- MESA_FORMAT_R_RGTC1_SNORM,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
- {
- MESA_FORMAT_RG_RGTC2_UNORM,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
- {
- MESA_FORMAT_RG_RGTC2_SNORM,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
+ FETCH_COMPRESSED(R_RGTC1_UNORM),
+ FETCH_COMPRESSED(R_RGTC1_SNORM),
+ FETCH_COMPRESSED(RG_RGTC2_UNORM),
+ FETCH_COMPRESSED(RG_RGTC2_SNORM),
/* LATC1/2 compressed formats */
- {
- MESA_FORMAT_L_LATC1_UNORM,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
- {
- MESA_FORMAT_L_LATC1_SNORM,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
- {
- MESA_FORMAT_LA_LATC2_UNORM,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
- {
- MESA_FORMAT_LA_LATC2_SNORM,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
+ FETCH_COMPRESSED(L_LATC1_UNORM),
+ FETCH_COMPRESSED(L_LATC1_SNORM),
+ FETCH_COMPRESSED(LA_LATC2_UNORM),
+ FETCH_COMPRESSED(LA_LATC2_SNORM),
/* ETC1/2 compressed formats */
- {
- MESA_FORMAT_ETC1_RGB8,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
- {
- MESA_FORMAT_ETC2_RGB8,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
- {
- MESA_FORMAT_ETC2_SRGB8,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
- {
- MESA_FORMAT_ETC2_RGBA8_EAC,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
- {
- MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC,
- fetch_compressed,
- fetch_compressed,
- fetch_compressed
- },
- {
-
Mesa (master): mesa: add ASTC extensions to the extensions table
Module: Mesa
Branch: master
Commit: 4143511b15e8f1d63176257ae8a83b4906e3204c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4143511b15e8f1d63176257ae8a83b4906e3204c
Author: Nanley Chery nanley.g.ch...@intel.com
Date: Tue May 19 15:41:28 2015 -0700
mesa: add ASTC extensions to the extensions table
v2: alphabetize the extensions.
remove OES ASTC extension.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/extensions.c |2 ++
src/mesa/main/mtypes.h |2 ++
2 files changed, 4 insertions(+)
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index 4a3c231..03303ac 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@ -342,6 +342,8 @@ static const struct extension extension_table[] = {
/* KHR extensions */
{ GL_KHR_debug, o(dummy_true),
GL, 2012 },
{ GL_KHR_context_flush_control, o(dummy_true),
GL | ES2, 2014 },
+ { GL_KHR_texture_compression_astc_hdr,
o(KHR_texture_compression_astc_hdr),GL | ES2, 2012 },
+ { GL_KHR_texture_compression_astc_ldr,
o(KHR_texture_compression_astc_ldr),GL | ES2, 2012 },
/* Vendor extensions */
{ GL_3DFX_texture_compression_FXT1,
o(TDFX_texture_compression_FXT1), GL, 1999 },
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 5031b08..a172952 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -3853,6 +3853,8 @@ struct gl_extensions
GLboolean ATI_fragment_shader;
GLboolean ATI_separate_stencil;
GLboolean INTEL_performance_query;
+ GLboolean KHR_texture_compression_astc_hdr;
+ GLboolean KHR_texture_compression_astc_ldr;
GLboolean MESA_pack_invert;
GLboolean MESA_ycbcr_texture;
GLboolean NV_conditional_render;
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Mesa (master): mesa/glformats: recognize ASTC formats as compressed
Module: Mesa Branch: master Commit: 692578ed134bacff1a315489ad47514450b3387f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=692578ed134bacff1a315489ad47514450b3387f Author: Nanley Chery nanley.g.ch...@intel.com Date: Tue May 19 15:41:56 2015 -0700 mesa/glformats: recognize ASTC formats as compressed Reviewed-by: Anuj Phogat anuj.pho...@gmail.com Signed-off-by: Nanley Chery nanley.g.ch...@intel.com --- src/mesa/main/glformats.c | 29 + 1 file changed, 29 insertions(+) diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c index fd8336c..ce66699 100644 --- a/src/mesa/main/glformats.c +++ b/src/mesa/main/glformats.c @@ -1303,6 +1303,35 @@ _mesa_is_compressed_format(const struct gl_context *ctx, GLenum format) case GL_COMPRESSED_RGB_BPTC_UNSIGNED_FLOAT: return _mesa_is_desktop_gl(ctx) ctx-Extensions.ARB_texture_compression_bptc; + case GL_COMPRESSED_RGBA_ASTC_4x4_KHR: + case GL_COMPRESSED_RGBA_ASTC_5x4_KHR: + case GL_COMPRESSED_RGBA_ASTC_5x5_KHR: + case GL_COMPRESSED_RGBA_ASTC_6x5_KHR: + case GL_COMPRESSED_RGBA_ASTC_6x6_KHR: + case GL_COMPRESSED_RGBA_ASTC_8x5_KHR: + case GL_COMPRESSED_RGBA_ASTC_8x6_KHR: + case GL_COMPRESSED_RGBA_ASTC_8x8_KHR: + case GL_COMPRESSED_RGBA_ASTC_10x5_KHR: + case GL_COMPRESSED_RGBA_ASTC_10x6_KHR: + case GL_COMPRESSED_RGBA_ASTC_10x8_KHR: + case GL_COMPRESSED_RGBA_ASTC_10x10_KHR: + case GL_COMPRESSED_RGBA_ASTC_12x10_KHR: + case GL_COMPRESSED_RGBA_ASTC_12x12_KHR: + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4_KHR: + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4_KHR: + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5_KHR: + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5_KHR: + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6_KHR: + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x5_KHR: + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x6_KHR: + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x8_KHR: + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x5_KHR: + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x6_KHR: + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x8_KHR: + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x10_KHR: + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x10_KHR: + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x12_KHR: + return ctx-Extensions.KHR_texture_compression_astc_ldr; case GL_PALETTE4_RGB8_OES: case GL_PALETTE4_RGBA8_OES: case GL_PALETTE4_R5_G6_B5_OES: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa/macros: add power-of-two assertions for alignment macros
Module: Mesa
Branch: master
Commit: 97f4efd573aed7ffc0ea9395f4e69ccdeb5041f6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=97f4efd573aed7ffc0ea9395f4e69ccdeb5041f6
Author: Nanley Chery nanley.g.ch...@intel.com
Date: Wed May 27 13:25:30 2015 -0700
mesa/macros: add power-of-two assertions for alignment macros
ALIGN and ROUND_DOWN_TO both require that the alignment value passed
into the macro be a power of two in the comments. Using software assertions
verifies this to be the case.
v2: use static inline functions instead of gcc-specific statement expressions
(Brian).
v3: fix indendation (Brian).
v4: add greater than zero requirement (Anuj).
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp |2 +-
src/mesa/main/macros.h | 14 --
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index a62dbb8..430efb3 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -131,7 +131,7 @@ fs_visitor::nir_setup_outputs(nir_shader *shader)
switch (stage) {
case MESA_SHADER_VERTEX:
- for (int i = 0; i ALIGN(type_size_scalar(var-type), 4) / 4; i++) {
+ for (unsigned int i = 0; i ALIGN(type_size_scalar(var-type), 4) /
4; i++) {
int output = var-data.location + i;
this-outputs[output] = offset(reg, bld, 4 * i);
this-output_components[output] = vector_elements;
diff --git a/src/mesa/main/macros.h b/src/mesa/main/macros.h
index 54df50c..c3ef42a 100644
--- a/src/mesa/main/macros.h
+++ b/src/mesa/main/macros.h
@@ -690,7 +690,12 @@ minify(unsigned value, unsigned levels)
*
* \sa ROUND_DOWN_TO()
*/
-#define ALIGN(value, alignment) (((value) + (alignment) - 1) ~((alignment)
- 1))
+static inline uintptr_t
+ALIGN(uintptr_t value, int32_t alignment)
+{
+ assert((alignment 0) _mesa_is_pow_two(alignment));
+ return (((value) + (alignment) - 1) ~((alignment) - 1));
+}
/**
* Align a value down to an alignment value
@@ -703,7 +708,12 @@ minify(unsigned value, unsigned levels)
*
* \sa ALIGN()
*/
-#define ROUND_DOWN_TO(value, alignment) ((value) ~(alignment - 1))
+static inline uintptr_t
+ROUND_DOWN_TO(uintptr_t value, int32_t alignment)
+{
+ assert((alignment 0) _mesa_is_pow_two(alignment));
+ return ((value) ~(alignment - 1));
+}
/** Cross product of two 3-element vectors */
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Mesa (master): i965: correct mt-align_h for 2D textures on Skylake
Module: Mesa
Branch: master
Commit: 1a9ceed4ba764cf73a643f8f2135b5b84cfe4581
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a9ceed4ba764cf73a643f8f2135b5b84cfe4581
Author: Nanley Chery nanley.g.ch...@intel.com
Date: Thu Jun 18 11:02:17 2015 -0700
i965: correct mt-align_h for 2D textures on Skylake
In agreement with commit 4ab8d59a23, vertical alignment values are equal to
four times the block height on Gen9+.
v2: add newlines to separate declarations, statments, and comments.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Reviewed-by: Neil Roberts n...@linux.intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 1d8eb09..e8a92dd 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -270,9 +270,14 @@ intel_vertical_texture_alignment_unit(struct brw_context
*brw,
* Where * means either VALIGN_2 or VALIGN_4 depending on the setting of
* the SURFACE_STATE Surface Vertical Alignment field.
*/
- if (_mesa_is_format_compressed(mt-format))
- /* See comment above for the horizontal alignment */
- return brw-gen = 9 ? 16 : 4;
+if (_mesa_is_format_compressed(mt-format)) {
+ unsigned int i, j;
+
+ _mesa_get_format_block_size(mt-format, i, j);
+
+ /* See comment above for the horizontal alignment */
+ return brw-gen = 9 ? j * 4 : 4;
+}
if (mt-format == MESA_FORMAT_S_UINT8)
return brw-gen = 7 ? 8 : 4;
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Mesa (master): radeonsi: mark unreachable paths to avoid warnings
Module: Mesa
Branch: master
Commit: f8b01ae47cc4760d5687e50f3315b5a89e19cd26
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f8b01ae47cc4760d5687e50f3315b5a89e19cd26
Author: Grazvydas Ignotas nota...@gmail.com
Date: Tue Aug 18 03:23:29 2015 +0300
radeonsi: mark unreachable paths to avoid warnings
Otherwise we get:
warning: 'num_user_sgprs' may be used uninitialized in this function
...
Reviewed-by: Michel Dänzer michel.daen...@amd.com
Signed-off-by: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeonsi/si_shader.c|2 +-
src/gallium/drivers/radeonsi/si_state_shaders.c |4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index fa6c15a..6b70a8f 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2418,7 +2418,7 @@ static void tex_fetch_args(
num_deriv_channels = 1;
break;
default:
- assert(0); /* no other targets are valid here */
+ unreachable(invalid target);
}
for (param = 0; param 2; param++)
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 0347014..a09f588 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -181,7 +181,7 @@ static void si_shader_es(struct si_shader *shader)
vgpr_comp_cnt = 3; /* all components are needed for TES */
num_user_sgprs = SI_TES_NUM_USER_SGPR;
} else
- assert(0);
+ unreachable(invalid shader selector type);
num_sgprs = shader-num_sgprs;
/* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
@@ -338,7 +338,7 @@ static void si_shader_vs(struct si_shader *shader)
vgpr_comp_cnt = 3; /* all components are needed for TES */
num_user_sgprs = SI_TES_NUM_USER_SGPR;
} else
- assert(0);
+ unreachable(invalid shader selector type);
num_sgprs = shader-num_sgprs;
if (num_user_sgprs num_sgprs) {
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Mesa (master): mesa: create multisample fallback textures like normal textures
Module: Mesa
Branch: master
Commit: f432ae899fb81468778dbeb17ac7615da3ed5c0d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f432ae899fb81468778dbeb17ac7615da3ed5c0d
Author: Marek Olšák marek.ol...@amd.com
Date: Mon Aug 24 00:22:37 2015 +0200
mesa: create multisample fallback textures like normal textures
This works if drivers upsample on upload (like all radeon ones do).
The alternative is an unexpected GL error from anything calling
_mesa_update_state and possibly other issues.
Cc: 10.6 11.0 mesa-sta...@lists.freedesktop.org
Reviewed-by: Dave Airlie airl...@redhat.com
---
src/mesa/main/texstore.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/main/texstore.c b/src/mesa/main/texstore.c
index fc83310..5394026 100644
--- a/src/mesa/main/texstore.c
+++ b/src/mesa/main/texstore.c
@@ -1004,6 +1004,7 @@ store_texsubimage(struct gl_context *ctx,
/* compute slice info (and do some sanity checks) */
switch (target) {
case GL_TEXTURE_2D:
+ case GL_TEXTURE_2D_MULTISAMPLE:
case GL_TEXTURE_RECTANGLE:
case GL_TEXTURE_CUBE_MAP:
case GL_TEXTURE_EXTERNAL_OES:
@@ -1025,6 +1026,7 @@ store_texsubimage(struct gl_context *ctx,
srcImageStride = _mesa_image_row_stride(packing, width, format, type);
break;
case GL_TEXTURE_2D_ARRAY:
+ case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
numSlices = depth;
sliceOffset = zoffset;
depth = 1;
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Mesa (master): i965: change the meaning of cpp for compressed textures
Module: Mesa
Branch: master
Commit: a6877341358e1534e74dd9e5fc72934a20b78228
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a6877341358e1534e74dd9e5fc72934a20b78228
Author: Nanley Chery nanley.g.ch...@intel.com
Date: Thu May 21 14:27:55 2015 -0700
i965: change the meaning of cpp for compressed textures
An ASTC block takes up 16 bytes for all block width and height configurations.
This size is not integrally divisible by all ASTC block widths. Therefore cpp
is changed to mean bytes per block if the texture is compressed.
Because the original definition was bytes per block divided by block width, all
references to the mipmap width must be divided the block width. This keeps the
address calculation formulas consistent. For example, the units for
miptree_level
x_offset and miptree total_width has changed from pixels to blocks.
v2: reuse preexisting ALIGN_NPOT macro located in an i965 driver file.
v3: move ALIGN_NPOT into seperate commit.
simplify cpp assignment in copy_image_with_blitter().
update miptree width and offset variables in: intel_miptree_copy_slice(),
intel_miptree_map_gtt(), and brw_miptree_layout_texture_3d().
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 15 +--
src/mesa/drivers/dri/i965/intel_copy_image.c | 19 +--
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 --
src/mesa/drivers/dri/i965/intel_mipmap_tree.h |2 +-
4 files changed, 15 insertions(+), 35 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index e8a92dd..a95ac95 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -395,6 +395,7 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
}
}
+ mt-total_width /= bw;
mt-total_height = 0;
for (unsigned level = mt-first_level; level = mt-last_level; level++) {
@@ -419,7 +420,7 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
/* Layout_below: step right after second mipmap.
*/
if (level == mt-first_level + 1) {
-x += ALIGN_NPOT(width, mt-align_w);
+x += ALIGN_NPOT(width, mt-align_w) / bw;
} else {
y += img_height;
}
@@ -579,12 +580,14 @@ static void
brw_miptree_layout_texture_3d(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
- unsigned yscale = mt-compressed ? 4 : 1;
-
mt-total_width = 0;
mt-total_height = 0;
unsigned ysum = 0;
+ unsigned bh, bw;
+
+ _mesa_get_format_block_size(mt-format, bw, bh);
+
for (unsigned level = mt-first_level; level = mt-last_level; level++) {
unsigned WL = MAX2(mt-physical_width0 level, 1);
unsigned HL = MAX2(mt-physical_height0 level, 1);
@@ -601,9 +604,9 @@ brw_miptree_layout_texture_3d(struct brw_context *brw,
unsigned x = (q % (1 level)) * wL;
unsigned y = ysum + (q level) * hL;
- intel_miptree_set_image_offset(mt, level, q, x, y / yscale);
- mt-total_width = MAX2(mt-total_width, x + wL);
- mt-total_height = MAX2(mt-total_height, (y + hL) / yscale);
+ intel_miptree_set_image_offset(mt, level, q, x / bw, y / bh);
+ mt-total_width = MAX2(mt-total_width, (x + wL) / bw);
+ mt-total_height = MAX2(mt-total_height, (y + hL) / bh);
}
ysum += ALIGN(DL, 1 level) / (1 level) * hL;
diff --git a/src/mesa/drivers/dri/i965/intel_copy_image.c
b/src/mesa/drivers/dri/i965/intel_copy_image.c
index 3706704..ac2738f 100644
--- a/src/mesa/drivers/dri/i965/intel_copy_image.c
+++ b/src/mesa/drivers/dri/i965/intel_copy_image.c
@@ -41,7 +41,6 @@ copy_image_with_blitter(struct brw_context *brw,
{
GLuint bw, bh;
uint32_t src_image_x, src_image_y, dst_image_x, dst_image_y;
- int cpp;
/* The blitter doesn't understand multisampling at all. */
if (src_mt-num_samples 0 || dst_mt-num_samples 0)
@@ -86,16 +85,6 @@ copy_image_with_blitter(struct brw_context *brw,
src_y /= (int)bh;
src_width /= (int)bw;
src_height /= (int)bh;
-
- /* Inside of the miptree, the x offsets are stored in pixels while
- * the y offsets are stored in blocks. We need to scale just the x
- * offset.
- */
- src_image_x /= bw;
-
- cpp = _mesa_get_format_bytes(src_mt-format);
- } else {
- cpp = src_mt-cpp;
}
src_x += src_image_x;
src_y += src_image_y;
@@ -111,18 +100,12 @@ copy_image_with_blitter(struct brw_context *brw,
dst_x /= (int)bw;
dst_y /= (int)bh;
-
- /* Inside of the miptree, the x offsets are stored in pixels while
- * the y offsets are stored in blocks. We need to scale just the x
- * offset.
- */
- dst_image_x /= bw;
}
dst_x += dst_image_x;
dst_y += dst_image_y;
return
Mesa (master): i965: refactor miptree alignment calculation code
Module: Mesa
Branch: master
Commit: 43d5b4db969930f9d85f605c75ef9ffe67e58ad3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=43d5b4db969930f9d85f605c75ef9ffe67e58ad3
Author: Nanley Chery nanley.g.ch...@intel.com
Date: Thu May 28 16:02:34 2015 -0700
i965: refactor miptree alignment calculation code
Remove redundant checks and comments by grouping our calculations for
align_w and align_h wherever possible.
v2: reintroduce brw.
don't include functional changes.
don't adjust function parameters or create a new function.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 85 ++--
1 file changed, 30 insertions(+), 55 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index a95ac95..268b995 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -123,12 +123,6 @@ intel_horizontal_texture_alignment_unit(struct brw_context
*brw,
return 16;
/**
-* From the Alignment Unit Size section of various specs, namely:
-* - Gen3 Spec: Memory Data Formats Volume, Section 1.20.1.4
-* - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
-* - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
-* - BSpec (for Ivybridge and slight variations in separate stencil)
-*
* +--+
* || alignment unit width (i) |
* | Surface Property |-|
@@ -146,32 +140,6 @@ intel_horizontal_texture_alignment_unit(struct brw_context
*brw,
* On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
* Surface Horizontal Alignment field to HALIGN_4 or HALIGN_8.
*/
-if (_mesa_is_format_compressed(mt-format)) {
- /* The hardware alignment requirements for compressed textures
-* happen to match the block boundaries.
-*/
- unsigned int i, j;
- _mesa_get_format_block_size(mt-format, i, j);
-
- /* On Gen9+ we can pick our own alignment for compressed textures but it
- * has to be a multiple of the block size. The minimum alignment we can
- * pick is 4 so we effectively have to align to 4 times the block
- * size
- */
- if (brw-gen = 9)
- return i * 4;
- else
- return i;
-}
-
- if (mt-format == MESA_FORMAT_S_UINT8)
- return 8;
-
- if (brw-gen = 9 mt-tr_mode != INTEL_MIPTREE_TRMODE_NONE) {
- uint32_t align = tr_mode_horizontal_texture_alignment(brw, mt);
- /* XY_FAST_COPY_BLT doesn't support horizontal alignment 32. */
- return align 32 ? 32 : align;
- }
if (brw-gen = 7 mt-format == MESA_FORMAT_Z_UNORM16)
return 8;
@@ -248,12 +216,6 @@ intel_vertical_texture_alignment_unit(struct brw_context
*brw,
const struct intel_mipmap_tree *mt)
{
/**
-* From the Alignment Unit Size section of various specs, namely:
-* - Gen3 Spec: Memory Data Formats Volume, Section 1.20.1.4
-* - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
-* - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
-* - BSpec (for Ivybridge and slight variations in separate stencil)
-*
* +--+
* || alignment unit height (j) |
* | Surface Property |-|
@@ -270,23 +232,6 @@ intel_vertical_texture_alignment_unit(struct brw_context
*brw,
* Where * means either VALIGN_2 or VALIGN_4 depending on the setting of
* the SURFACE_STATE Surface Vertical Alignment field.
*/
-if (_mesa_is_format_compressed(mt-format)) {
- unsigned int i, j;
-
- _mesa_get_format_block_size(mt-format, i, j);
-
- /* See comment above for the horizontal alignment */
- return brw-gen = 9 ? j * 4 : 4;
-}
-
- if (mt-format == MESA_FORMAT_S_UINT8)
- return brw-gen = 7 ? 8 : 4;
-
- if (mt-tr_mode != INTEL_MIPTREE_TRMODE_NONE) {
- uint32_t align = tr_mode_vertical_texture_alignment(brw, mt);
- /* XY_FAST_COPY_BLT doesn't support vertical alignment 64 */
- return align 64 ? 64 : align;
- }
/* Broadwell only supports VALIGN of 4, 8, and 16. The BSpec says 4
* should always be used, except for stencil buffers, which should be 8.
@@ -775,6 +720,13 @@ intel_miptree_set_alignment(struct brw_context *brw,
struct intel_mipmap_tree *mt,
uint32_t layout_flags)
{
+ /**
+* From the Alignment Unit Size section of various specs, namely:
+* - Gen3 Spec: Memory
Mesa (master): mesa/teximage: accept ASTC formats for 3D texture specification
Module: Mesa
Branch: master
Commit: 12b519b4571d27a45abd3266f35b126d00dcb926
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=12b519b4571d27a45abd3266f35b126d00dcb926
Author: Nanley Chery nanley.g.ch...@intel.com
Date: Mon Jul 27 16:09:09 2015 -0700
mesa/teximage: accept ASTC formats for 3D texture specification
The ASTC spec was revised as follows:
Revision 2, April 28, 2015 - added CompressedTex{Sub,}Image3D to
commands accepting ASTC format tokens in the New Tokens section [...].
Support only exists in the HDR submode:
Add a second new column 3D Tex. which is empty for all non-ASTC
formats. If only the LDR profile is supported by the implementation,
this column is also empty for all ASTC formats. If both the LDR and HDR
profiles are supported only, this column is checked for all ASTC
formats.
LDR-only systems should generate an INVALID_OPERATION error when
attempting to call CompressedTexImage3D with the TEXTURE_3D target.
v2. return the proper error for LDR-only systems.
v3. update is_astc_format().
v4. use _mesa_is_astc_format().
v5. place logic in _mesa_target_can_be_compressed.
v6. fix issues handling ASTC formats.
Reviewed-by: Chad Versace chad.vers...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/teximage.c | 63 --
1 file changed, 56 insertions(+), 7 deletions(-)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 0a641cf..56ae415 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -1854,19 +1854,68 @@ _mesa_target_can_be_compressed(const struct gl_context
*ctx, GLenum target,
return write_error(error, GL_INVALID_OPERATION);
target_can_be_compresed = ctx-Extensions.ARB_texture_cube_map_array;
- break;
- case GL_TEXTURE_3D:
- /* See ETC2/EAC comment in switch case GL_TEXTURE_CUBE_MAP_ARRAY. */
- if (layout == MESA_FORMAT_LAYOUT_ETC2 _mesa_is_gles3(ctx))
+ /* From the KHR_texture_compression_astc_hdr spec:
+ *
+ * Add a second new column 3D Tex. which is empty for all non-ASTC
+ * formats. If only the LDR profile is supported by the
+ * implementation, this column is also empty for all ASTC formats. If
+ * both the LDR and HDR profiles are supported only, this column is
+ * checked for all ASTC formats.
+ *
+ * Add a third new column Cube Map Array Tex. which is empty for
all
+ * non-ASTC formats, and checked for all ASTC formats.
+ *
+ * and,
+ *
+ * 'An INVALID_OPERATION error is generated by CompressedTexImage3D
+ * if internalformat is TEXTURE_CUBE_MAP_ARRAY and the
+ * Cube Map Array column of table 8.19 is *not* checked, or if
+ * internalformat is TEXTURE_3D and the 3D Tex. column of table
+ * 8.19 is *not* checked'
+ *
+ * The instances of internalformat above should say target.
+ */
+
+ /* Throw an INVALID_OPERATION error if the target is
+ * TEXTURE_CUBE_MAP_ARRAY and the format is not ASTC.
+ */
+ if (target_can_be_compresed
+ ctx-Extensions.KHR_texture_compression_astc_ldr
+ layout != MESA_FORMAT_LAYOUT_ASTC)
return write_error(error, GL_INVALID_OPERATION);
- if (layout == MESA_FORMAT_LAYOUT_BPTC) {
+ break;
+ case GL_TEXTURE_3D:
+ switch (layout) {
+ case MESA_FORMAT_LAYOUT_ETC2:
+ /* See ETC2/EAC comment in case GL_TEXTURE_CUBE_MAP_ARRAY. */
+ if (_mesa_is_gles3(ctx))
+return write_error(error, GL_INVALID_OPERATION);
+ break;
+ case MESA_FORMAT_LAYOUT_BPTC:
target_can_be_compresed =
ctx-Extensions.ARB_texture_compression_bptc;
break;
- }
+ case MESA_FORMAT_LAYOUT_ASTC:
+ target_can_be_compresed =
+ ctx-Extensions.KHR_texture_compression_astc_hdr;
- break;
+ /* Throw an INVALID_OPERATION error if the target is TEXTURE_3D and
+ * and the hdr extension is not supported.
+ * See comment in switch case GL_TEXTURE_CUBE_MAP_ARRAY for more info.
+ */
+ if (!target_can_be_compresed)
+return write_error(error, GL_INVALID_OPERATION);
+ break;
+ default:
+ /* Throw an INVALID_OPERATION error if the target is TEXTURE_3D and
+ * the format is not ASTC.
+ * See comment in switch case GL_TEXTURE_CUBE_MAP_ARRAY for more info.
+ */
+ if (ctx-Extensions.KHR_texture_compression_astc_ldr)
+return write_error(error, GL_INVALID_OPERATION);
+ break;
+ }
default:
break;
}
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Mesa (master): mesa/texcompress: enable translation between MESA and GL ASTC formats
Module: Mesa Branch: master Commit: 23c9cd5a9613ad07bdbe55708a56562ee23f25d5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=23c9cd5a9613ad07bdbe55708a56562ee23f25d5 Author: Nanley Chery nanley.g.ch...@intel.com Date: Tue Apr 28 15:08:32 2015 -0700 mesa/texcompress: enable translation between MESA and GL ASTC formats v3. conform the ASTC MESA_FORMAT enums to the existing naming convention. Reviewed-by: Anuj Phogat anuj.pho...@gmail.com Signed-off-by: Nanley Chery nanley.g.ch...@intel.com --- src/mesa/main/texcompress.c | 114 +++ 1 file changed, 114 insertions(+) diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c index c028daa..bb94137 100644 --- a/src/mesa/main/texcompress.c +++ b/src/mesa/main/texcompress.c @@ -471,6 +471,63 @@ _mesa_glenum_to_compressed_format(GLenum format) case GL_COMPRESSED_RGB_BPTC_UNSIGNED_FLOAT: return MESA_FORMAT_BPTC_RGB_UNSIGNED_FLOAT; + case GL_COMPRESSED_RGBA_ASTC_4x4_KHR: + return MESA_FORMAT_RGBA_ASTC_4x4; + case GL_COMPRESSED_RGBA_ASTC_5x4_KHR: + return MESA_FORMAT_RGBA_ASTC_5x4; + case GL_COMPRESSED_RGBA_ASTC_5x5_KHR: + return MESA_FORMAT_RGBA_ASTC_5x5; + case GL_COMPRESSED_RGBA_ASTC_6x5_KHR: + return MESA_FORMAT_RGBA_ASTC_6x5; + case GL_COMPRESSED_RGBA_ASTC_6x6_KHR: + return MESA_FORMAT_RGBA_ASTC_6x6; + case GL_COMPRESSED_RGBA_ASTC_8x5_KHR: + return MESA_FORMAT_RGBA_ASTC_8x5; + case GL_COMPRESSED_RGBA_ASTC_8x6_KHR: + return MESA_FORMAT_RGBA_ASTC_8x6; + case GL_COMPRESSED_RGBA_ASTC_8x8_KHR: + return MESA_FORMAT_RGBA_ASTC_8x8; + case GL_COMPRESSED_RGBA_ASTC_10x5_KHR: + return MESA_FORMAT_RGBA_ASTC_10x5; + case GL_COMPRESSED_RGBA_ASTC_10x6_KHR: + return MESA_FORMAT_RGBA_ASTC_10x6; + case GL_COMPRESSED_RGBA_ASTC_10x8_KHR: + return MESA_FORMAT_RGBA_ASTC_10x8; + case GL_COMPRESSED_RGBA_ASTC_10x10_KHR: + return MESA_FORMAT_RGBA_ASTC_10x10; + case GL_COMPRESSED_RGBA_ASTC_12x10_KHR: + return MESA_FORMAT_RGBA_ASTC_12x10; + case GL_COMPRESSED_RGBA_ASTC_12x12_KHR: + return MESA_FORMAT_RGBA_ASTC_12x12; + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4_KHR: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4; + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4_KHR: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4; + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5_KHR: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5; + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5_KHR: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5; + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6_KHR: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6; + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x5_KHR: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x5; + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x6_KHR: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x6; + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x8_KHR: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x8; + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x5_KHR: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x5; + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x6_KHR: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x6; + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x8_KHR: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x8; + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x10_KHR: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x10; + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x10_KHR: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x10; + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x12_KHR: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12; + default: return MESA_FORMAT_NONE; } @@ -561,6 +618,63 @@ _mesa_compressed_format_to_glenum(struct gl_context *ctx, mesa_format mesaFormat case MESA_FORMAT_BPTC_RGB_UNSIGNED_FLOAT: return GL_COMPRESSED_RGB_BPTC_UNSIGNED_FLOAT; + case MESA_FORMAT_RGBA_ASTC_4x4: + return GL_COMPRESSED_RGBA_ASTC_4x4_KHR; + case MESA_FORMAT_RGBA_ASTC_5x4: + return GL_COMPRESSED_RGBA_ASTC_5x4_KHR; + case MESA_FORMAT_RGBA_ASTC_5x5: + return GL_COMPRESSED_RGBA_ASTC_5x5_KHR; + case MESA_FORMAT_RGBA_ASTC_6x5: + return GL_COMPRESSED_RGBA_ASTC_6x5_KHR; + case MESA_FORMAT_RGBA_ASTC_6x6: + return GL_COMPRESSED_RGBA_ASTC_6x6_KHR; + case MESA_FORMAT_RGBA_ASTC_8x5: + return GL_COMPRESSED_RGBA_ASTC_8x5_KHR; + case MESA_FORMAT_RGBA_ASTC_8x6: + return GL_COMPRESSED_RGBA_ASTC_8x6_KHR; + case MESA_FORMAT_RGBA_ASTC_8x8: + return GL_COMPRESSED_RGBA_ASTC_8x8_KHR; + case MESA_FORMAT_RGBA_ASTC_10x5: + return GL_COMPRESSED_RGBA_ASTC_10x5_KHR; + case MESA_FORMAT_RGBA_ASTC_10x6: + return GL_COMPRESSED_RGBA_ASTC_10x6_KHR; + case MESA_FORMAT_RGBA_ASTC_10x8: + return GL_COMPRESSED_RGBA_ASTC_10x8_KHR; + case MESA_FORMAT_RGBA_ASTC_10x10: + return GL_COMPRESSED_RGBA_ASTC_10x10_KHR; + case MESA_FORMAT_RGBA_ASTC_12x10: + return GL_COMPRESSED_RGBA_ASTC_12x10_KHR; + case MESA_FORMAT_RGBA_ASTC_12x12: + return GL_COMPRESSED_RGBA_ASTC_12x12_KHR; +
Mesa (master): glapi: add support for KHR_texture_compression_astc_ldr
Module: Mesa Branch: master Commit: e9fd8e154fdb0394cbaed5e14ac52e689a020ebe URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9fd8e154fdb0394cbaed5e14ac52e689a020ebe Author: Nanley Chery nanley.g.ch...@intel.com Date: Tue Apr 28 14:41:49 2015 -0700 glapi: add support for KHR_texture_compression_astc_ldr v2: correct the spelling of the sRGB variants. remove spaces around = when setting the enum value. Reviewed-by: Anuj Phogat anuj.pho...@gmail.com Signed-off-by: Nanley Chery nanley.g.ch...@intel.com --- .../glapi/gen/KHR_texture_compression_astc.xml | 40 src/mapi/glapi/gen/Makefile.am |1 + src/mapi/glapi/gen/gl_API.xml |2 +- 3 files changed, 42 insertions(+), 1 deletion(-) diff --git a/src/mapi/glapi/gen/KHR_texture_compression_astc.xml b/src/mapi/glapi/gen/KHR_texture_compression_astc.xml new file mode 100644 index 000..7b5864d --- /dev/null +++ b/src/mapi/glapi/gen/KHR_texture_compression_astc.xml @@ -0,0 +1,40 @@ +?xml version=1.0? +!DOCTYPE OpenGLAPI SYSTEM gl_API.dtd + +OpenGLAPI + +category name=GL_KHR_texture_compression_astc_ldr number=118 + +enum name=COMPRESSED_RGBA_ASTC_4x4_KHR value=0x93B0/ +enum name=COMPRESSED_RGBA_ASTC_5x4_KHR value=0x93B1/ +enum name=COMPRESSED_RGBA_ASTC_5x5_KHR value=0x93B2/ +enum name=COMPRESSED_RGBA_ASTC_6x5_KHR value=0x93B3/ +enum name=COMPRESSED_RGBA_ASTC_6x6_KHR value=0x93B4/ +enum name=COMPRESSED_RGBA_ASTC_8x5_KHR value=0x93B5/ +enum name=COMPRESSED_RGBA_ASTC_8x6_KHR value=0x93B6/ +enum name=COMPRESSED_RGBA_ASTC_8x8_KHR value=0x93B7/ +enum name=COMPRESSED_RGBA_ASTC_10x5_KHR value=0x93B8/ +enum name=COMPRESSED_RGBA_ASTC_10x6_KHR value=0x93B9/ +enum name=COMPRESSED_RGBA_ASTC_10x8_KHR value=0x93BA/ +enum name=COMPRESSED_RGBA_ASTC_10x10_KHR value=0x93BB/ +enum name=COMPRESSED_RGBA_ASTC_12x10_KHR value=0x93BC/ +enum name=COMPRESSED_RGBA_ASTC_12x12_KHR value=0x93BD/ + +enum name=COMPRESSED_SRGB8_ALPHA8_ASTC_4x4_KHR value=0x93D0/ +enum name=COMPRESSED_SRGB8_ALPHA8_ASTC_5x4_KHR value=0x93D1/ +enum name=COMPRESSED_SRGB8_ALPHA8_ASTC_5x5_KHR value=0x93D2/ +enum name=COMPRESSED_SRGB8_ALPHA8_ASTC_6x5_KHR value=0x93D3/ +enum name=COMPRESSED_SRGB8_ALPHA8_ASTC_6x6_KHR value=0x93D4/ +enum name=COMPRESSED_SRGB8_ALPHA8_ASTC_8x5_KHR value=0x93D5/ +enum name=COMPRESSED_SRGB8_ALPHA8_ASTC_8x6_KHR value=0x93D6/ +enum name=COMPRESSED_SRGB8_ALPHA8_ASTC_8x8_KHR value=0x93D7/ +enum name=COMPRESSED_SRGB8_ALPHA8_ASTC_10x5_KHR value=0x93D8/ +enum name=COMPRESSED_SRGB8_ALPHA8_ASTC_10x6_KHR value=0x93D9/ +enum name=COMPRESSED_SRGB8_ALPHA8_ASTC_10x8_KHR value=0x93DA/ +enum name=COMPRESSED_SRGB8_ALPHA8_ASTC_10x10_KHR value=0x93DB/ +enum name=COMPRESSED_SRGB8_ALPHA8_ASTC_12x10_KHR value=0x93DC/ +enum name=COMPRESSED_SRGB8_ALPHA8_ASTC_12x12_KHR value=0x93DD/ + +/category + +/OpenGLAPI diff --git a/src/mapi/glapi/gen/Makefile.am b/src/mapi/glapi/gen/Makefile.am index 86a9243..9224de2 100644 --- a/src/mapi/glapi/gen/Makefile.am +++ b/src/mapi/glapi/gen/Makefile.am @@ -190,6 +190,7 @@ API_XML = \ INTEL_performance_query.xml \ KHR_debug.xml \ KHR_context_flush_control.xml \ + KHR_texture_compression_astc.xml \ NV_conditional_render.xml \ NV_primitive_restart.xml \ NV_texture_barrier.xml \ diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml index 658efa4..f0dcdca 100644 --- a/src/mapi/glapi/gen/gl_API.xml +++ b/src/mapi/glapi/gen/gl_API.xml @@ -8168,7 +8168,7 @@ xi:include href=ARB_texture_storage.xml xmlns:xi=http://www.w3.org/2001/XInclude/ -!-- ARB extension #118 -- +xi:include href=KHR_texture_compression_astc.xml xmlns:xi=http://www.w3.org/2001/XInclude/ xi:include href=KHR_debug.xml xmlns:xi=http://www.w3.org/2001/XInclude/ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: use ALIGN_NPOT for setting ASTC mipmap layouts
Module: Mesa
Branch: master
Commit: 10ff64fd3d19bc9da793fa43eb746c29608bfddd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=10ff64fd3d19bc9da793fa43eb746c29608bfddd
Author: Nanley Chery nanley.g.ch...@intel.com
Date: Thu May 21 14:27:55 2015 -0700
i965: use ALIGN_NPOT for setting ASTC mipmap layouts
ALIGN is changed to ALIGN_NPOT because alignment values are sometimes not
powers of two when working with ASTC.
v2: handle texture arrays and LDR-only systems.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 26 -
src/mesa/drivers/dri/i965/intel_mipmap_tree.c |4 ++--
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index e96732a..1d8eb09 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -367,7 +367,7 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
mt-total_width = mt-physical_width0;
if (mt-compressed)
- mt-total_width = ALIGN(mt-total_width, bw);
+ mt-total_width = ALIGN_NPOT(mt-total_width, bw);
/* May need to adjust width to accommodate the placement of
* the 2nd mipmap. This occurs when the alignment
@@ -378,10 +378,10 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
unsigned mip1_width;
if (mt-compressed) {
- mip1_width = ALIGN(minify(mt-physical_width0, 1), mt-align_w) +
- ALIGN(minify(mt-physical_width0, 2), bw);
+ mip1_width = ALIGN_NPOT(minify(mt-physical_width0, 1), mt-align_w)
+
+ ALIGN_NPOT(minify(mt-physical_width0, 2), bw);
} else {
- mip1_width = ALIGN(minify(mt-physical_width0, 1), mt-align_w) +
+ mip1_width = ALIGN_NPOT(minify(mt-physical_width0, 1), mt-align_w)
+
minify(mt-physical_width0, 2);
}
@@ -397,7 +397,7 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
intel_miptree_set_level_info(mt, level, x, y, depth);
- img_height = ALIGN(height, mt-align_h);
+ img_height = ALIGN_NPOT(height, mt-align_h);
if (mt-compressed)
img_height /= bh;
@@ -414,7 +414,7 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
/* Layout_below: step right after second mipmap.
*/
if (level == mt-first_level + 1) {
-x += ALIGN(width, mt-align_w);
+x += ALIGN_NPOT(width, mt-align_w);
} else {
y += img_height;
}
@@ -434,7 +434,7 @@ brw_miptree_get_horizontal_slice_pitch(const struct
brw_context *brw,
{
if ((brw-gen 9 mt-target == GL_TEXTURE_3D) ||
(brw-gen == 4 mt-target == GL_TEXTURE_CUBE_MAP)) {
- return ALIGN(minify(mt-physical_width0, level), mt-align_w);
+ return ALIGN_NPOT(minify(mt-physical_width0, level), mt-align_w);
} else {
return 0;
}
@@ -475,11 +475,11 @@ brw_miptree_get_vertical_slice_pitch(const struct
brw_context *brw,
} else if (mt-target == GL_TEXTURE_3D ||
(brw-gen == 4 mt-target == GL_TEXTURE_CUBE_MAP) ||
mt-array_layout == ALL_SLICES_AT_EACH_LOD) {
- return ALIGN(minify(mt-physical_height0, level), mt-align_h);
+ return ALIGN_NPOT(minify(mt-physical_height0, level), mt-align_h);
} else {
- const unsigned h0 = ALIGN(mt-physical_height0, mt-align_h);
- const unsigned h1 = ALIGN(minify(mt-physical_height0, 1), mt-align_h);
+ const unsigned h0 = ALIGN_NPOT(mt-physical_height0, mt-align_h);
+ const unsigned h1 = ALIGN_NPOT(minify(mt-physical_height0, 1),
mt-align_h);
return h0 + h1 + (brw-gen = 7 ? 12 : 11) * mt-align_h;
}
@@ -551,7 +551,7 @@ brw_miptree_layout_texture_array(struct brw_context *brw,
for (unsigned level = mt-first_level; level = mt-last_level; level++) {
unsigned img_height;
- img_height = ALIGN(height, mt-align_h);
+ img_height = ALIGN_NPOT(height, mt-align_h);
if (mt-compressed)
img_height /= mt-align_h;
@@ -584,8 +584,8 @@ brw_miptree_layout_texture_3d(struct brw_context *brw,
unsigned WL = MAX2(mt-physical_width0 level, 1);
unsigned HL = MAX2(mt-physical_height0 level, 1);
unsigned DL = MAX2(mt-physical_depth0 level, 1);
- unsigned wL = ALIGN(WL, mt-align_w);
- unsigned hL = ALIGN(HL, mt-align_h);
+ unsigned wL = ALIGN_NPOT(WL, mt-align_w);
+ unsigned hL = ALIGN_NPOT(HL, mt-align_h);
if (mt-target == GL_TEXTURE_CUBE_MAP)
DL = 6;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index e85c3f0..44eb913 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1272,8 +1272,8 @@ intel_miptree_copy_slice(struct brw_context *brw,
if (dst_mt-compressed) {
unsigned
Mesa (master): i965/surface_formats: add support for 2D ASTC surface formats
Module: Mesa
Branch: master
Commit: 8b1f008e9acf94645a28c27fa261f6450a3edb84
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b1f008e9acf94645a28c27fa261f6450a3edb84
Author: Nanley Chery nanley.g.ch...@intel.com
Date: Wed Apr 15 14:15:10 2015 -0700
i965/surface_formats: add support for 2D ASTC surface formats
Define two-thirds of the 2D Intel ASTC surface formats (LDR-only). This allows
a 1-to-1 mapping from the mesa format to the Intel format.
ASTC textures will default to being processed in LDR mode. If there is
hardware support for HDR/Full mode and the texture is not sRGB, add the
format bit necessary to process it in HDR/Full mode.
v2: remove extra newlines.
v3: follow existing coding style in translate_tex_format().
v4: expound on the GEN9_SURFACE_ASTC_HDR_FORMAT_BIT comment.
update SF table - ASTC is actually supported in Gen8.
v5: conform the ASTC MESA_FORMAT enums to the existing naming convention.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/brw_defines.h | 32 +
src/mesa/drivers/dri/i965/brw_surface_formats.c | 87 +++
2 files changed, 119 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 82a3635..cb5c82a 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -504,6 +504,38 @@
#define BRW_SURFACEFORMAT_R8G8B8_UINT0x1C8
#define BRW_SURFACEFORMAT_R8G8B8_SINT0x1C9
#define BRW_SURFACEFORMAT_RAW0x1FF
+
+#define GEN9_SURFACE_ASTC_HDR_FORMAT_BIT 0x100
+
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_4x4_U8sRGB 0x200
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_5x4_U8sRGB 0x208
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_5x5_U8sRGB 0x209
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_6x5_U8sRGB 0x211
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_6x6_U8sRGB 0x212
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_8x5_U8sRGB 0x221
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_8x6_U8sRGB 0x222
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_8x8_U8sRGB 0x224
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x5_U8sRGB0x231
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x6_U8sRGB0x232
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x8_U8sRGB0x234
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x10_U8sRGB 0x236
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_12x10_U8sRGB 0x23E
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_12x12_U8sRGB 0x23F
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_4x4_FLT16 0x240
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_5x4_FLT16 0x248
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_5x5_FLT16 0x249
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_6x5_FLT16 0x251
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_6x6_FLT16 0x252
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_8x5_FLT16 0x261
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_8x6_FLT16 0x262
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_8x8_FLT16 0x264
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x5_FLT16 0x271
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x6_FLT16 0x272
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x8_FLT16 0x274
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x10_FLT160x276
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_12x10_FLT160x27E
+#define BRW_SURFACEFORMAT_ASTC_LDR_2D_12x12_FLT160x27F
+
#define BRW_SURFACE_FORMAT_SHIFT 18
#define BRW_SURFACE_FORMAT_MASKINTEL_MASK(26, 18)
diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c
b/src/mesa/drivers/dri/i965/brw_surface_formats.c
index a33fd88..97fff60 100644
--- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
+++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
@@ -307,6 +307,34 @@ const struct surface_format_info surface_formats[] = {
SF( x, x, x, x, x, x, x, x, x, ETC2_EAC_SRGB8_A8)
SF( x, x, x, x, x, x, x, x, x, R8G8B8_UINT)
SF( x, x, x, x, x, x, x, x, x, R8G8B8_SINT)
+ SF(80, 80, x, x, x, x, x, x, x, ASTC_LDR_2D_4x4_FLT16)
+ SF(80, 80, x, x, x, x, x, x, x, ASTC_LDR_2D_5x4_FLT16)
+ SF(80, 80, x, x, x, x, x, x, x, ASTC_LDR_2D_5x5_FLT16)
+ SF(80, 80, x, x, x, x, x, x, x, ASTC_LDR_2D_6x5_FLT16)
+ SF(80, 80, x, x, x, x, x, x, x, ASTC_LDR_2D_6x6_FLT16)
+ SF(80, 80, x, x, x, x, x, x, x, ASTC_LDR_2D_8x5_FLT16)
+ SF(80, 80, x, x, x, x, x, x, x, ASTC_LDR_2D_8x6_FLT16)
+ SF(80, 80, x, x, x, x, x, x, x, ASTC_LDR_2D_8x8_FLT16)
+ SF(80, 80, x, x, x, x, x, x, x, ASTC_LDR_2D_10x5_FLT16)
+ SF(80, 80, x, x, x, x, x, x, x, ASTC_LDR_2D_10x6_FLT16)
+ SF(80, 80, x, x, x, x, x, x, x, ASTC_LDR_2D_10x8_FLT16)
+ SF(80, 80, x, x, x, x, x, x, x, ASTC_LDR_2D_10x10_FLT16)
+ SF(80, 80, x, x, x, x, x, x, x,
Mesa (master): mesa/macros: move ALIGN_NPOT to macros.h
Module: Mesa
Branch: master
Commit: 54d2aa4258f0bfcc669b2bc4e82332f7ff4876dd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=54d2aa4258f0bfcc669b2bc4e82332f7ff4876dd
Author: Nanley Chery nanley.g.ch...@intel.com
Date: Tue Jun 2 11:03:22 2015 -0700
mesa/macros: move ALIGN_NPOT to macros.h
Aligning with a non-power-of-two number is a general task that can be used in
various places. This commit is required for the next one.
v2: add greater than 0 assertion (Anuj).
convert the macro to a static inline function.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/intel_upload.c |6 --
src/mesa/main/macros.h | 10 ++
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_upload.c
b/src/mesa/drivers/dri/i965/intel_upload.c
index 870aabc..deaae6c 100644
--- a/src/mesa/drivers/dri/i965/intel_upload.c
+++ b/src/mesa/drivers/dri/i965/intel_upload.c
@@ -44,12 +44,6 @@
#define INTEL_UPLOAD_SIZE (64*1024)
-/**
- * Like ALIGN(), but works with a non-power-of-two alignment.
- */
-#define ALIGN_NPOT(value, alignment) \
- (((value) + (alignment) - 1) / (alignment) * (alignment))
-
void
intel_upload_finish(struct brw_context *brw)
{
diff --git a/src/mesa/main/macros.h b/src/mesa/main/macros.h
index c3ef42a..ed207d4 100644
--- a/src/mesa/main/macros.h
+++ b/src/mesa/main/macros.h
@@ -698,6 +698,16 @@ ALIGN(uintptr_t value, int32_t alignment)
}
/**
+ * Like ALIGN(), but works with a non-power-of-two alignment.
+ */
+static inline uintptr_t
+ALIGN_NPOT(uintptr_t value, int32_t alignment)
+{
+ assert(alignment 0);
+ return (value + alignment - 1) / alignment * alignment;
+}
+
+/**
* Align a value down to an alignment value
*
* If \c value is not already aligned to the requested alignment value, it
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Mesa (master): mesa: don't enable online compression for ASTC formats
Module: Mesa
Branch: master
Commit: 582ce1ea976a16aa8f32ff72cb2fecb00186e253
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=582ce1ea976a16aa8f32ff72cb2fecb00186e253
Author: Nanley Chery nanley.g.ch...@intel.com
Date: Mon May 18 16:30:30 2015 -0700
mesa: don't enable online compression for ASTC formats
In agreement with the ASTC spec, this makes calls to TexImage*D unsuccessful.
Implied by the spec, Generate[Texture]Mipmap and [Copy]Tex[Sub]Image*D calls
must be unsuccessful as well.
v2. actually force attempts to compress online to fail.
v3. indentation (Matt).
v4. update copytexture_error_check to account for CopyTexImage*D (Chad).
Reviewed-by: Chad Versace chad.vers...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/genmipmap.c |1 +
src/mesa/main/glformats.c | 41 +
src/mesa/main/glformats.h |3 +++
src/mesa/main/texcompress.c | 22 ++
src/mesa/main/teximage.c| 17 +
5 files changed, 80 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/genmipmap.c b/src/mesa/main/genmipmap.c
index c18f9d5..4ec8385 100644
--- a/src/mesa/main/genmipmap.c
+++ b/src/mesa/main/genmipmap.c
@@ -111,6 +111,7 @@ _mesa_generate_texture_mipmap(struct gl_context *ctx,
if (_mesa_is_enum_format_integer(srcImage-InternalFormat) ||
_mesa_is_depthstencil_format(srcImage-InternalFormat) ||
+ _mesa_is_astc_format(srcImage-InternalFormat) ||
_mesa_is_stencil_format(srcImage-InternalFormat)) {
_mesa_unlock_texture(ctx, texObj);
_mesa_error(ctx, GL_INVALID_OPERATION,
diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index 3eb66da..fd8336c 100644
--- a/src/mesa/main/glformats.c
+++ b/src/mesa/main/glformats.c
@@ -820,6 +820,47 @@ _mesa_is_enum_format_signed_int(GLenum format)
}
}
+/**
+ * Test if the given format is an ASTC format.
+ */
+GLboolean
+_mesa_is_astc_format(GLenum internalFormat)
+{
+ switch (internalFormat) {
+ case GL_COMPRESSED_RGBA_ASTC_4x4_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_5x4_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_5x5_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_6x5_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_6x6_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_8x5_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_8x6_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_8x8_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_10x5_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_10x6_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_10x8_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_10x10_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_12x10_KHR:
+ case GL_COMPRESSED_RGBA_ASTC_12x12_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x5_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x6_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_8x8_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x5_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x6_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x8_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x10_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x10_KHR:
+ case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x12_KHR:
+ return true;
+ default:
+ return false;
+ }
+}
+
/**
* Test if the given format is an integer (non-normalized) format.
diff --git a/src/mesa/main/glformats.h b/src/mesa/main/glformats.h
index 419955a..aec905d 100644
--- a/src/mesa/main/glformats.h
+++ b/src/mesa/main/glformats.h
@@ -57,6 +57,9 @@ extern GLint
_mesa_bytes_per_vertex_attrib(GLint comps, GLenum type);
extern GLboolean
+_mesa_is_astc_format(GLenum internalFormat);
+
+extern GLboolean
_mesa_is_type_unsigned(GLenum type);
extern GLboolean
diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index edfb036..c028daa 100644
--- a/src/mesa/main/texcompress.c
+++ b/src/mesa/main/texcompress.c
@@ -229,6 +229,28 @@ _mesa_gl_compressed_format_base_format(GLenum format)
*what GL_NUM_COMPRESSED_TEXTURE_FORMATS and
*GL_COMPRESSED_TEXTURE_FORMATS return.
*
+ * The KHR_texture_compression_astc_hdr spec says:
+ *
+ *Interactions with OpenGL 4.2
+ *
+ *OpenGL 4.2 supports the feature that compressed textures can be
+ *compressed online, by passing the compressed texture format enum as
+ *the internal format when uploading a texture using TexImage1D,
+ *TexImage2D or TexImage3D (see Section 3.9.3, Texture Image
+ *Specification, subsection Encoding of Special Internal Formats).
+ *
+ *Due to the complexity of the ASTC compression algorithm, it is not
+ *usually suitable for online use, and therefore ASTC support will be
+ *limited to pre-compressed textures only. Where on-device compression
+ *is required, a domain-specific limited
Mesa (master): mesa/teximage: return the base internal format of the ASTC formats
Module: Mesa
Branch: master
Commit: cd49b97a8a2c0dd8dc1d7f32b86f519e936571fd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd49b97a8a2c0dd8dc1d7f32b86f519e936571fd
Author: Nanley Chery nanley.g.ch...@intel.com
Date: Tue Apr 28 15:10:11 2015 -0700
mesa/teximage: return the base internal format of the ASTC formats
This is necesary to initialize the gl_texture_image struct.
From the KHR_texture_compression_astc_ldr spec:
Added to Section 3.8.6, Compressed Texture Images
Add the tokens specified above to Table 3.16, Compressed Internal Formats.
In all cases, the base internal format will be RGBA. The encoding allows
images to be encoded with fewer channels, but this is always presented as
RGBA to the sampler.
v2. use _mesa_is_astc_format().
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/teximage.c |4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 56ae415..0535db3 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -565,6 +565,10 @@ _mesa_base_tex_format( struct gl_context *ctx, GLint
internalFormat )
}
}
+ if (ctx-Extensions.KHR_texture_compression_astc_ldr
+ _mesa_is_astc_format(internalFormat))
+ return GL_RGBA;
+
if (_mesa_is_gles3(ctx) || ctx-Extensions.ARB_ES3_compatibility) {
switch (internalFormat) {
case GL_COMPRESSED_RGB8_ETC2:
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Mesa (master): mesa/formats: define the 2D ASTC formats
Module: Mesa
Branch: master
Commit: 8ae37365f30594498184fe5428f961a9c310fd8c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ae37365f30594498184fe5428f961a9c310fd8c
Author: Nanley Chery nanley.g.ch...@intel.com
Date: Tue May 19 10:35:39 2015 -0700
mesa/formats: define the 2D ASTC formats
Define the mesa formats and make changes necessary for compilation
without errors. Also add support for _mesa_get_srgb_format_linear().
v2. conform the ASTC MESA_FORMAT enums to the existing naming convention.
v3. remove ASTC cases for _mesa_get_uncompressed_format(). This function is
only used for generating mipmaps - something ASTC formats do not support
due to lack of online compression.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/format_info.py |3 +++
src/mesa/main/formats.c | 43 ++
src/mesa/main/formats.csv| 31 ++
src/mesa/main/formats.h | 31 ++
src/mesa/swrast/s_texfetch.c | 32 ++-
5 files changed, 139 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/format_info.py b/src/mesa/main/format_info.py
index 839d407..22eb5a7 100644
--- a/src/mesa/main/format_info.py
+++ b/src/mesa/main/format_info.py
@@ -122,6 +122,9 @@ def get_channel_bits(fmat, chan_name):
elif fmat.layout == 'bptc':
bits = 16 if fmat.name.endswith('_FLOAT') else 8
return bits if fmat.has_channel(chan_name) else 0
+ elif fmat.layout == 'astc':
+ bits = 16 if 'RGBA' in fmat.name else 8
+ return bits if fmat.has_channel(chan_name) else 0
else:
assert False
else:
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index 34a4434..587221c 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -197,6 +197,7 @@ _mesa_get_format_max_bits(mesa_format format)
*MESA_FORMAT_LAYOUT_ETC1
*MESA_FORMAT_LAYOUT_ETC2
*MESA_FORMAT_LAYOUT_BPTC
+ *MESA_FORMAT_LAYOUT_ASTC
*MESA_FORMAT_LAYOUT_OTHER
*/
extern enum mesa_format_layout
@@ -663,6 +664,48 @@ _mesa_get_srgb_format_linear(mesa_format format)
case MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM:
format = MESA_FORMAT_BPTC_RGBA_UNORM;
break;
+ case MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4:
+ format = MESA_FORMAT_RGBA_ASTC_4x4;
+ break;
+ case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4:
+ format = MESA_FORMAT_RGBA_ASTC_5x4;
+ break;
+ case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5:
+ format = MESA_FORMAT_RGBA_ASTC_5x5;
+ break;
+ case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5:
+ format = MESA_FORMAT_RGBA_ASTC_6x5;
+ break;
+ case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6:
+ format = MESA_FORMAT_RGBA_ASTC_6x6;
+ break;
+ case MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x5:
+ format = MESA_FORMAT_RGBA_ASTC_8x5;
+ break;
+ case MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x6:
+ format = MESA_FORMAT_RGBA_ASTC_8x6;
+ break;
+ case MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x8:
+ format = MESA_FORMAT_RGBA_ASTC_8x8;
+ break;
+ case MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x5:
+ format = MESA_FORMAT_RGBA_ASTC_10x5;
+ break;
+ case MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x6:
+ format = MESA_FORMAT_RGBA_ASTC_10x6;
+ break;
+ case MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x8:
+ format = MESA_FORMAT_RGBA_ASTC_10x8;
+ break;
+ case MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x10:
+ format = MESA_FORMAT_RGBA_ASTC_10x10;
+ break;
+ case MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x10:
+ format = MESA_FORMAT_RGBA_ASTC_12x10;
+ break;
+ case MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12:
+ format = MESA_FORMAT_RGBA_ASTC_12x12;
+ break;
case MESA_FORMAT_B8G8R8X8_SRGB:
format = MESA_FORMAT_B8G8R8X8_UNORM;
break;
diff --git a/src/mesa/main/formats.csv b/src/mesa/main/formats.csv
index e159e7d..80729d9 100644
--- a/src/mesa/main/formats.csv
+++ b/src/mesa/main/formats.csv
@@ -301,3 +301,34 @@ MESA_FORMAT_BPTC_RGBA_UNORM , bptc , 4, 4,
x128, , ,
MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM , bptc , 4, 4, x128, , ,
, xyzw, srgb
MESA_FORMAT_BPTC_RGB_SIGNED_FLOAT , bptc , 4, 4, x128, , ,
, xyz1, rgb
MESA_FORMAT_BPTC_RGB_UNSIGNED_FLOAT , bptc , 4, 4, x128, , ,
, xyz1, rgb
+
+# ASTC compressed formats
+MESA_FORMAT_RGBA_ASTC_4x4 , astc , 4, 4, x128, , ,
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_5x4 , astc , 5, 4, x128, , ,
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_5x5 , astc , 5, 5, x128, , ,
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_6x5 , astc , 6, 5, x128, , ,
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_6x6 , astc , 6, 6, x128, , ,
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_8x5 , astc , 8, 5, x128, , ,
