Mesa (master): dispatch: stop generating separate GLES1 API code.
Module: Mesa Branch: master Commit: a8ab7e335df4cd7841bbbe572d5494796bb4e398 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8ab7e335df4cd7841bbbe572d5494796bb4e398 Author: Paul Berry stereotype...@gmail.com Date: Tue Oct 23 13:24:17 2012 -0700 dispatch: stop generating separate GLES1 API code. This patch removes the generated files api_exec_es1.c, api_exec_es1_dispatch.h, and api_exec_es1_remap_helper.h (and the source files and build rules used to generate them), since they are no longer used. GLES1 now uses the same dispatch table layout as all the other APIs. Reviewed-by: Kenneth Graunke kenn...@whitecape.org --- src/mesa/Android.gen.mk | 33 +- src/mesa/Makefile.am | 15 - src/mesa/SConscript | 18 - src/mesa/main/.gitignore |3 - src/mesa/main/APIspec.py | 617 --- src/mesa/main/APIspec.xml | 2383 - src/mesa/main/APIspecutil.py | 272 - src/mesa/main/api_exec.h |6 - src/mesa/main/es_generator.py | 765 - src/mesa/sources.mak |1 - 10 files changed, 4 insertions(+), 4109 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=a8ab7e335df4cd7841bbbe572d5494796bb4e398 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): dispatch: stop using _mesa_create_exec_table_es1() for GLES1 .
Module: Mesa
Branch: master
Commit: 8386088e3dc6fbd223dca7cc966b86f9ab0652b5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8386088e3dc6fbd223dca7cc966b86f9ab0652b5
Author: Paul Berry stereotype...@gmail.com
Date: Tue Oct 23 14:48:39 2012 -0700
dispatch: stop using _mesa_create_exec_table_es1() for GLES1.
This patch modifies context creation code for GLES1 to use
_mesa_create_exec_table() (which is used for all other APIs) instead
of the GLES1-specific _mesa_create_exec_table_es1().
There is a slight change in functionality. As a result of a mistake
in the code generation of _mesa_create_exec_table_es1(), it does not
include glFlushMappedBufferRangeEXT or glMapBufferRangeEXT (this is
because when support for those two functions was added in commit
762d9ac, src/mesa/main/APIspec.xml wasn't updated). With this patch,
glFlushMappedBufferRangeEXT and glMapBufferRangeEXT are properly
included in the dispatch table. Accordingly, dispatch_sanity.cpp is
modified to expect these two functions to be present.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
v2: Leave GLES1.1 dispatch sanity test disabled when not building
GLES1 support.
---
src/mesa/main/context.c | 27 ++-
src/mesa/main/tests/dispatch_sanity.cpp | 20
2 files changed, 18 insertions(+), 29 deletions(-)
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index a510738..a4dedee 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -422,14 +422,7 @@ one_time_init( struct gl_context *ctx )
if (!(api_init_mask (1 ctx-API))) {
_mesa_init_get_hash(ctx);
- /*
- * This is fine as ES does not use the remap table, but it may not be
- * future-proof. We cannot always initialize the remap table because
- * when an app is linked to libGLES*, there are not enough dynamic
- * entries.
- */
- if (_mesa_is_desktop_gl(ctx) || ctx-API == API_OPENGLES2)
- _mesa_init_remap_table();
+ _mesa_init_remap_table();
}
api_init_mask |= 1 ctx-API;
@@ -943,23 +936,7 @@ _mesa_initialize_context(struct gl_context *ctx,
}
/* setup the API dispatch tables */
- switch (ctx-API) {
-#if FEATURE_GL || FEATURE_ES2
- case API_OPENGL:
- case API_OPENGL_CORE:
- case API_OPENGLES2:
- ctx-Exec = _mesa_create_exec_table(ctx);
- break;
-#endif
-#if FEATURE_ES1
- case API_OPENGLES:
- ctx-Exec = _mesa_create_exec_table_es1();
- break;
-#endif
- default:
- _mesa_problem(ctx, unknown or unsupported API);
- break;
- }
+ ctx-Exec = _mesa_create_exec_table(ctx);
if (!ctx-Exec) {
_mesa_reference_shared_state(ctx, ctx-Shared, NULL);
diff --git a/src/mesa/main/tests/dispatch_sanity.cpp
b/src/mesa/main/tests/dispatch_sanity.cpp
index 1195633..fadf295 100644
--- a/src/mesa/main/tests/dispatch_sanity.cpp
+++ b/src/mesa/main/tests/dispatch_sanity.cpp
@@ -76,7 +76,6 @@ extern const struct function gles2_functions_possible[];
extern const struct function gles3_functions_possible[];
#if FEATURE_ES1
-extern C _glapi_table *_mesa_create_exec_table_es1(void);
extern const struct function gles11_functions_possible[];
#endif /* FEATURE_ES1 */
@@ -147,9 +146,20 @@ validate_nops(const _glapi_proc *table)
#if FEATURE_ES1
TEST_F(DispatchSanity_test, GLES11)
{
- _glapi_proc *exec = (_glapi_proc *) _mesa_create_exec_table_es1();
- validate_functions(exec, gles11_functions_possible);
- validate_nops(exec);
+ ctx.Version = 11;
+ _mesa_initialize_context(ctx,
+API_OPENGLES,
+visual,
+NULL /* share_list */,
+driver_functions);
+
+ _swrast_CreateContext(ctx);
+ _vbo_CreateContext(ctx);
+ _tnl_CreateContext(ctx);
+ _swsetup_CreateContext(ctx);
+
+ validate_functions((_glapi_proc *) ctx.Exec, gles11_functions_possible);
+ validate_nops((_glapi_proc *) ctx.Exec);
}
#endif /* FEATURE_ES1 */
@@ -251,6 +261,7 @@ const struct function gles11_functions_possible[] = {
{ glEnableClientState, _gloffset_EnableClientState },
{ glFinish, _gloffset_Finish },
{ glFlush, _gloffset_Flush },
+ { glFlushMappedBufferRangeEXT, -1 },
{ glFogf, _gloffset_Fogf },
{ glFogfv, _gloffset_Fogfv },
{ glFogx, -1 },
@@ -312,6 +323,7 @@ const struct function gles11_functions_possible[] = {
{ glLoadMatrixx, -1 },
{ glLogicOp, _gloffset_LogicOp },
{ glMapBufferOES, -1 },
+ { glMapBufferRangeEXT, -1 },
{ glMaterialf, _gloffset_Materialf },
{ glMaterialfv, _gloffset_Materialfv },
{ glMaterialx, -1 },
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Mesa (master): shared-glapi: implement _glapi_get_proc_name().
Module: Mesa
Branch: master
Commit: 03984b26c4855efb64824cb42ea5bad579b48334
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=03984b26c4855efb64824cb42ea5bad579b48334
Author: Paul Berry stereotype...@gmail.com
Date: Tue Oct 23 10:49:33 2012 -0700
shared-glapi: implement _glapi_get_proc_name().
Previously this function was only implemented for non-shared-glapi
builds. Since the function is only intended for debugging purposes we
use a simple O(n) algorithm.
Acked-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Matt Turner matts...@gmail.com
---
src/mapi/mapi/mapi_glapi.c |4 ++--
src/mapi/mapi/stub.c | 22 ++
src/mapi/mapi/stub.h |3 +++
3 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/src/mapi/mapi/mapi_glapi.c b/src/mapi/mapi/mapi_glapi.c
index adfc0cb..4627c4d 100644
--- a/src/mapi/mapi/mapi_glapi.c
+++ b/src/mapi/mapi/mapi_glapi.c
@@ -219,8 +219,8 @@ _glapi_get_proc_address(const char *funcName)
const char *
_glapi_get_proc_name(unsigned int offset)
{
- /* not implemented */
- return NULL;
+ const struct mapi_stub *stub = stub_find_by_slot(offset);
+ return stub ? stub_get_name(stub) : NULL;
}
unsigned long
diff --git a/src/mapi/mapi/stub.c b/src/mapi/mapi/stub.c
index 6fb8556..688dc81 100644
--- a/src/mapi/mapi/stub.c
+++ b/src/mapi/mapi/stub.c
@@ -153,6 +153,28 @@ stub_find_dynamic(const char *name, int generate)
return stub;
}
+static const struct mapi_stub *
+search_table_by_slot(const struct mapi_stub *table, size_t num_entries,
+ int slot)
+{
+ size_t i;
+ for (i = 0; i num_entries; ++i) {
+ if (table[i].slot == slot)
+ return table[i];
+ }
+ return NULL;
+}
+
+const struct mapi_stub *
+stub_find_by_slot(int slot)
+{
+ const struct mapi_stub *stub =
+ search_table_by_slot(public_stubs, ARRAY_SIZE(public_stubs), slot);
+ if (stub)
+ return stub;
+ return search_table_by_slot(dynamic_stubs, num_dynamic_stubs, slot);
+}
+
void
stub_fix_dynamic(struct mapi_stub *stub, const struct mapi_stub *alias)
{
diff --git a/src/mapi/mapi/stub.h b/src/mapi/mapi/stub.h
index b2b6f18..98e2553 100644
--- a/src/mapi/mapi/stub.h
+++ b/src/mapi/mapi/stub.h
@@ -42,6 +42,9 @@ stub_find_public(const char *name);
struct mapi_stub *
stub_find_dynamic(const char *name, int generate);
+const struct mapi_stub *
+stub_find_by_slot(int slot);
+
void
stub_fix_dynamic(struct mapi_stub *stub, const struct mapi_stub *alias);
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Mesa (master): dispatch_sanity: print names of functions that shouldnt be in dispatch table.
Module: Mesa
Branch: master
Commit: 1cf6360f8955b4191c81be24c5b5fb950ff1b21f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1cf6360f8955b4191c81be24c5b5fb950ff1b21f
Author: Paul Berry stereotype...@gmail.com
Date: Tue Oct 23 10:59:44 2012 -0700
dispatch_sanity: print names of functions that shouldnt be in dispatch table.
Previously we just printed the dispatch table index and the user had
to convert it to a function name. That was a pain because when
FEATURE_remap_table is defined, the assignment of functions to
dispatch table entries is done at run time.
Acked-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Matt Turner matts...@gmail.com
---
src/mesa/main/tests/dispatch_sanity.cpp | 10 +-
1 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/src/mesa/main/tests/dispatch_sanity.cpp
b/src/mesa/main/tests/dispatch_sanity.cpp
index dbca581..ee53d2e 100644
--- a/src/mesa/main/tests/dispatch_sanity.cpp
+++ b/src/mesa/main/tests/dispatch_sanity.cpp
@@ -100,6 +100,13 @@ DispatchSanity_test::SetUp()
_mesa_init_driver_functions(driver_functions);
}
+static const char *
+offset_to_proc_name_safe(unsigned offset)
+{
+ const char *name = _glapi_get_proc_name(offset);
+ return name ? name : ???;
+}
+
static void
validate_functions(_glapi_proc *table, const struct function *function_table)
{
@@ -122,7 +129,8 @@ validate_functions(_glapi_proc *table, const struct
function *function_table)
const unsigned size = _glapi_get_dispatch_table_size();
for (unsigned i = 0; i size; i++) {
- EXPECT_EQ((_glapi_proc) _mesa_generic_nop, table[i]) i = i;
+ EXPECT_EQ((_glapi_proc) _mesa_generic_nop, table[i])
+ i = i ( offset_to_proc_name_safe(i) );
}
}
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Mesa (master): main: Fix warning ('struct gl_context' declared inside parameter list).
Module: Mesa
Branch: master
Commit: 992ed68ed65b99fd76213cb355404f9a18e26da1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=992ed68ed65b99fd76213cb355404f9a18e26da1
Author: Paul Berry stereotype...@gmail.com
Date: Sun Oct 21 11:16:07 2012 -0700
main: Fix warning ('struct gl_context' declared inside parameter list).
This eliminates a warning in GCC 4.7.1.
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/main/api_loopback.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/src/mesa/main/api_loopback.h b/src/mesa/main/api_loopback.h
index 3e43286..628d4f8 100644
--- a/src/mesa/main/api_loopback.h
+++ b/src/mesa/main/api_loopback.h
@@ -31,6 +31,7 @@
#include main/mfeatures.h
struct _glapi_table;
+struct gl_context;
extern void
_mesa_loopback_init_api_table(const struct gl_context *ctx,
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Mesa (master): glapi: Alias ClampColor and ClampColorARB.
Module: Mesa Branch: master Commit: bad96f6ada47ec8e2caea7246e31654b1c7c92bb URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bad96f6ada47ec8e2caea7246e31654b1c7c92bb Author: Paul Berry stereotype...@gmail.com Date: Thu Oct 18 22:13:02 2012 -0700 glapi: Alias ClampColor and ClampColorARB. There's no reason to have separate slots in the dispatch table for these two functions, since they are synonymous. Reviewed-by: Brian Paul bri...@vmware.com Reviewed-by: Jordan Justen jordan.l.jus...@intel.com Reviewed-by: Ian Romanick ian.d.roman...@intel.com --- src/mapi/glapi/gen/GL3x.xml |2 +- src/mesa/main/api_exec.c|1 - src/mesa/main/dlist.c |1 - 3 files changed, 1 insertions(+), 3 deletions(-) diff --git a/src/mapi/glapi/gen/GL3x.xml b/src/mapi/glapi/gen/GL3x.xml index 7642a27..db8bae5 100644 --- a/src/mapi/glapi/gen/GL3x.xml +++ b/src/mapi/glapi/gen/GL3x.xml @@ -150,7 +150,7 @@ return type=const GLubyte */ /function - function name=ClampColor offset=assign + function name=ClampColor alias=ClampColorARB param name=target type=GLenum/ param name=clamp type=GLenum/ /function diff --git a/src/mesa/main/api_exec.c b/src/mesa/main/api_exec.c index d2f14ce..e2a503d 100644 --- a/src/mesa/main/api_exec.c +++ b/src/mesa/main/api_exec.c @@ -768,7 +768,6 @@ _mesa_create_exec_table(struct gl_context *ctx) SET_ClearBufferfv(exec, _mesa_ClearBufferfv); SET_ClearBufferfi(exec, _mesa_ClearBufferfi); SET_GetStringi(exec, _mesa_GetStringi); - SET_ClampColor(exec, _mesa_ClampColorARB); } /* GL_ARB_instanced_arrays */ diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c index 28cd52a..1948bff 100644 --- a/src/mesa/main/dlist.c +++ b/src/mesa/main/dlist.c @@ -10143,7 +10143,6 @@ _mesa_create_save_table(const struct gl_context *ctx) /* GL_ARB_color_buffer_float */ SET_ClampColorARB(table, save_ClampColorARB); - SET_ClampColor(table, save_ClampColorARB); /* GL 3.0 */ SET_ClearBufferiv(table, save_ClearBufferiv); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glapi: Alias VertexAttribDivisor and VertexAttribDivisorARB.
Module: Mesa Branch: master Commit: e7dd2e5213ce1049767d889286a0b7e919c7eefd URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7dd2e5213ce1049767d889286a0b7e919c7eefd Author: Paul Berry stereotype...@gmail.com Date: Mon Oct 22 15:02:50 2012 -0700 glapi: Alias VertexAttribDivisor and VertexAttribDivisorARB. There's no reason to have separate slots in the dispatch table for these two functions, since they are synonymous. Note: previous to this patch, we never populated the dispatch table slot for VertexAttribDivisor, which was ok, since it is not required until 3.3. After this patch, both functions will be usable provided that the ARB_instanced_arrays extension is present. Reviewed-by: Jordan Justen jordan.l.jus...@intel.com Reviewed-by: Ian Romanick ian.d.roman...@intel.com --- src/mapi/glapi/gen/GL3x.xml |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/mapi/glapi/gen/GL3x.xml b/src/mapi/glapi/gen/GL3x.xml index db8bae5..82b977f 100644 --- a/src/mapi/glapi/gen/GL3x.xml +++ b/src/mapi/glapi/gen/GL3x.xml @@ -624,7 +624,8 @@ enum name=TEXTURE_SWIZZLE_Avalue=0x8E45/ enum name=TEXTURE_SWIZZLE_RGBA value=0x8E46/ - function name=VertexAttribDivisor offset=assign es2=3.0 + function name=VertexAttribDivisor offset=assign es2=3.0 +alias=VertexAttribDivisorARB param name=index type=GLuint/ param name=divisor type=GLuint/ /function ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): _mesa_create_exec_table: de-deprecate GetPointerv.
Module: Mesa
Branch: master
Commit: 893ddb068fcc74465f318582bebbee7e397067c4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=893ddb068fcc74465f318582bebbee7e397067c4
Author: Paul Berry stereotype...@gmail.com
Date: Fri Oct 19 06:01:42 2012 -0700
_mesa_create_exec_table: de-deprecate GetPointerv.
glGetPointerv was de-deprecated in GL 4.3, because GL 4.3 adds
functionality from KHR_debug and ARB_debug_output, which require
glGetPointerv.
This patch modifies _mesa_create_exec_table() to populate
glGetPointerv in the dispatch table for core contexts.
Technically this is not in compliance with the spec--what we really
ought to do for core contexts is expose glGetPointerv only when a GL
4.3 context is in use or one of the two extensions is present.
However, it seems silly to go to that extra work, since the only
client-visible effect would be for glGetPointerv to raise an
INVALID_OPERATION error instead of an INVALID_ENUM error. Besides,
the other functions set up by _mesa_create_exec_table() only depend on
the API in use, not on the GL version or extensions supported.
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/main/api_exec.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/src/mesa/main/api_exec.c b/src/mesa/main/api_exec.c
index e2a503d..9958496 100644
--- a/src/mesa/main/api_exec.c
+++ b/src/mesa/main/api_exec.c
@@ -322,10 +322,12 @@ _mesa_create_exec_table(struct gl_context *ctx)
SET_DisableClientState(exec, _mesa_DisableClientState);
SET_EdgeFlagPointer(exec, _mesa_EdgeFlagPointer);
SET_EnableClientState(exec, _mesa_EnableClientState);
- SET_GetPointerv(exec, _mesa_GetPointerv);
SET_IndexPointer(exec, _mesa_IndexPointer);
SET_InterleavedArrays(exec, _mesa_InterleavedArrays);
}
+ if (ctx-API != API_OPENGLES2) {
+ SET_GetPointerv(exec, _mesa_GetPointerv);
+ }
SET_IsTexture(exec, _mesa_IsTexture);
if (ctx-API != API_OPENGL_CORE ctx-API != API_OPENGLES2) {
SET_NormalPointer(exec, _mesa_NormalPointer);
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Mesa (master): _mesa_create_exec_table(): deprecate ProgramStringARB.
Module: Mesa
Branch: master
Commit: 5863e3d16e055f63f28e49fdec3b4a3d1c73fe62
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5863e3d16e055f63f28e49fdec3b4a3d1c73fe62
Author: Paul Berry stereotype...@gmail.com
Date: Fri Oct 19 06:09:04 2012 -0700
_mesa_create_exec_table(): deprecate ProgramStringARB.
This function is only useful for the ARB_{vertex,fragment}_program
extensions, which we don't expose in core contexts.
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/main/api_exec.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/src/mesa/main/api_exec.c b/src/mesa/main/api_exec.c
index 9958496..7a000e7 100644
--- a/src/mesa/main/api_exec.c
+++ b/src/mesa/main/api_exec.c
@@ -580,13 +580,15 @@ _mesa_create_exec_table(struct gl_context *ctx)
SET_EnableVertexAttribArrayARB(exec, _mesa_EnableVertexAttribArrayARB);
SET_DisableVertexAttribArrayARB(exec, _mesa_DisableVertexAttribArrayARB);
if (ctx-API != API_OPENGLES2) {
- SET_ProgramStringARB(exec, _mesa_ProgramStringARB);
/* glBindProgramARB aliases glBindProgramNV */
/* glDeleteProgramsARB aliases glDeleteProgramsNV */
/* glGenProgramsARB aliases glGenProgramsNV */
/* glIsProgramARB aliases glIsProgramNV */
SET_GetVertexAttribdvARB(exec, _mesa_GetVertexAttribdvARB);
}
+ if (ctx-API == API_OPENGL) {
+ SET_ProgramStringARB(exec, _mesa_ProgramStringARB);
+ }
SET_GetVertexAttribfvARB(exec, _mesa_GetVertexAttribfvARB);
SET_GetVertexAttribivARB(exec, _mesa_GetVertexAttribivARB);
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Mesa (master): _mesa_create_exec_table: GLES3 fixes.
Module: Mesa
Branch: master
Commit: 2e0de807513abdeb239ce02177ccbbd6b18af90c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e0de807513abdeb239ce02177ccbbd6b18af90c
Author: Paul Berry stereotype...@gmail.com
Date: Fri Oct 19 06:37:09 2012 -0700
_mesa_create_exec_table: GLES3 fixes.
This patch sets up the dispatch table for the following GLES3
functions when a GLES3 context is in use:
- BeginQuery
- BeginTransformFeedback
- BindSampler
- BindTransformFeedback
- BlitFramebuffer
- ClearBufferfi
- ClearBufferfv
- ClearBufferiv
- ClearBufferuiv
- ClientWaitSync
- CopyBufferSubData
- DeleteQueries
- DeleteSamplers
- DeleteSync
- DeleteTransformFeedbacks
- EndQuery
- EndTransformFeedback
- FenceSync
- FramebufferTextureLayer
- GenQueries
- GenSamplers
- GenTransformFeedbacks
- GetInteger64v
- GetQueryObjectuiv
- GetQueryiv
- GetSamplerParameterfv
- GetSamplerParameteriv
- GetStringi
- GetSynciv
- GetTransformFeedbackVarying
- GetVertexAttribIiv
- GetVertexAttribIuiv
- IsQuery
- IsSampler
- IsSync
- IsTransformFeedback
- PauseTransformFeedback
- RenderbufferStorageMultisample
- ResumeTransformFeedback
- SamplerParameterf
- SamplerParameterfv
- SamplerParameteri
- SamplerParameteriv
- TransformFeedbackVaryings
- VertexAttribDivisor
- VertexAttribIPointer
- WaitSync
And it avoids setting up the dispatch table for these non-GLES3
functions:
- ColorMaski
- GetBooleani_v
- Enablei
- Disablei
- IsEnabledi
- ClearColorIiEXT
- ClearColorIuiEXT
- TextureStorage2DEXT
- TextureStorage3DEXT
- GetActiveUniformName
- GetnUniformdv
- GetnUniformfv
- GetnUniformiv
- GetnUniformuiv
Reviewed-by: Brian Paul bri...@vmware.com
v2: Make the ctx argument to _mesa_init_transform_feedback_dispatch()
a const pointer. Add a comment to remind us to add
GetBufferParameteri64v once tests exist for it. Also add
VertexAttribDivisor for GLES3, and remove GetActiveUniformName and
GetnUniform{dv,fv,iv,uiv} for GLES3.
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/main/api_exec.c | 36
src/mesa/main/bufferobj.c |3 +++
src/mesa/main/dlist.c |4 ++--
src/mesa/main/queryobj.c | 20
src/mesa/main/queryobj.h |3 ++-
src/mesa/main/samplerobj.c| 14 +-
src/mesa/main/samplerobj.h|3 ++-
src/mesa/main/transformfeedback.c |7 +--
src/mesa/main/transformfeedback.h |3 ++-
src/mesa/main/uniforms.c | 18 +++---
10 files changed, 68 insertions(+), 43 deletions(-)
diff --git a/src/mesa/main/api_exec.c b/src/mesa/main/api_exec.c
index 7a000e7..a670fba 100644
--- a/src/mesa/main/api_exec.c
+++ b/src/mesa/main/api_exec.c
@@ -492,8 +492,8 @@ _mesa_create_exec_table(struct gl_context *ctx)
/* 352. GL_EXT_transform_feedback */
/* ARB 93. GL_ARB_transform_feedback2 */
- if (ctx-API != API_OPENGLES2) {
- _mesa_init_transform_feedback_dispatch(exec);
+ if (ctx-API != API_OPENGLES2 || _mesa_is_gles3(ctx)) {
+ _mesa_init_transform_feedback_dispatch(ctx, exec);
}
/* 364. GL_EXT_provoking_vertex */
@@ -614,15 +614,15 @@ _mesa_create_exec_table(struct gl_context *ctx)
_mesa_init_bufferobj_dispatch(ctx, exec);
/* ARB 29. GL_ARB_occlusion_query */
- if (ctx-API != API_OPENGLES2) {
- _mesa_init_queryobj_dispatch(exec);
+ if (ctx-API != API_OPENGLES2 || _mesa_is_gles3(ctx)) {
+ _mesa_init_queryobj_dispatch(ctx, exec);
}
/* ARB 37. GL_ARB_draw_buffers */
SET_DrawBuffersARB(exec, _mesa_DrawBuffersARB);
/* ARB 66. GL_ARB_sync */
- if (ctx-API != API_OPENGLES2) {
+ if (ctx-API != API_OPENGLES2 || _mesa_is_gles3(ctx)) {
_mesa_init_sync_dispatch(exec);
}
@@ -672,7 +672,7 @@ _mesa_create_exec_table(struct gl_context *ctx)
SET_GetFramebufferAttachmentParameterivEXT(exec,
_mesa_GetFramebufferAttachmentParameterivEXT);
SET_GenerateMipmapEXT(exec, _mesa_GenerateMipmapEXT);
- if (ctx-API != API_OPENGLES2) {
+ if (ctx-API != API_OPENGLES2 || _mesa_is_gles3(ctx)) {
SET_BlitFramebufferEXT(exec, _mesa_BlitFramebufferEXT);
}
@@ -683,7 +683,7 @@ _mesa_create_exec_table(struct gl_context *ctx)
}
/* GL_MESA_texture_array / GL_EXT_texture_array */
- if (ctx-API != API_OPENGLES2) {
+ if (ctx-API != API_OPENGLES2 || _mesa_is_gles3(ctx)) {
SET_FramebufferTextureLayerEXT(exec, _mesa_FramebufferTextureLayerEXT);
}
@@ -695,7 +695,7 @@ _mesa_create_exec_table(struct gl_context *ctx)
/* The ARB_fbo functions are the union of
* GL_EXT_fbo, GL_EXT_framebuffer_blit, GL_EXT_texture_array
*/
- if (ctx-API != API_OPENGLES2) {
+ if (ctx-API != API_OPENGLES2 || _mesa_is_gles3(ctx)) {
SET_RenderbufferStorageMultisample(exec,
_mesa_RenderbufferStorageMultisample);
}
@@ -704,7 +704,7 @@ _mesa_create_exec_table(struct gl_context *ctx
Mesa (master): glapi: use new-style Python classes.
Module: Mesa
Branch: master
Commit: 7dc052b12bb8341a57151e1f3cefb8f9d15d5192
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7dc052b12bb8341a57151e1f3cefb8f9d15d5192
Author: Paul Berry stereotype...@gmail.com
Date: Wed Oct 10 11:01:35 2012 -0700
glapi: use new-style Python classes.
An unfortunate quirk of Python 2 is that there are two types of
classes: classic classes (which are backward compatible with some
unfortunate design decisions made early in Python's history), and
new-style classes. Classic classes have a number of limitations
(for example they don't support super()) and are unavailable in Python
3. There's really no reason to use classic classes, except in
unmaintained legacy code. For more information see
http://www.python.org/download/releases/2.2.3/descrintro/.
This patch upgrades the Python code in src/mapi/glapi/gen to use
exclusively new-style classes.
Tested-by: Matt Turner matts...@gmail.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mapi/glapi/gen/glX_XML.py|2 +-
src/mapi/glapi/gen/glX_proto_size.py |2 +-
src/mapi/glapi/gen/gl_XML.py | 10 +-
src/mapi/glapi/gen/typeexpr.py |6 +++---
4 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/mapi/glapi/gen/glX_XML.py b/src/mapi/glapi/gen/glX_XML.py
index 975321a..03a35b7 100644
--- a/src/mapi/glapi/gen/glX_XML.py
+++ b/src/mapi/glapi/gen/glX_XML.py
@@ -543,7 +543,7 @@ class glx_function(gl_XML.gl_function):
return not self.ignore and (self.offset != -1) and (self.glx_rop or
self.glx_sop or self.glx_vendorpriv or self.vectorequiv or self.client_handcode)
-class glx_function_iterator:
+class glx_function_iterator(object):
Class to iterate over a list of glXFunctions
def __init__(self, context):
diff --git a/src/mapi/glapi/gen/glX_proto_size.py
b/src/mapi/glapi/gen/glX_proto_size.py
index 7db816b..fdb355d 100644
--- a/src/mapi/glapi/gen/glX_proto_size.py
+++ b/src/mapi/glapi/gen/glX_proto_size.py
@@ -30,7 +30,7 @@ import license
import sys, getopt, copy, string
-class glx_enum_function:
+class glx_enum_function(object):
def __init__(self, func_name, enum_dict):
self.name = func_name
self.mode = 1
diff --git a/src/mapi/glapi/gen/gl_XML.py b/src/mapi/glapi/gen/gl_XML.py
index ce14a41..f956730 100644
--- a/src/mapi/glapi/gen/gl_XML.py
+++ b/src/mapi/glapi/gen/gl_XML.py
@@ -72,7 +72,7 @@ def is_attr_true( element, name ):
raise RuntimeError('Invalid value %s for boolean %s.' % (value,
name))
-class gl_print_base:
+class gl_print_base(object):
Base class of all API pretty-printers.
In the model-view-controller pattern, this is the view. Any derived
@@ -322,7 +322,7 @@ def create_parameter_string(parameters, include_names):
return string.join(list, , )
-class gl_item:
+class gl_item(object):
def __init__(self, element, context):
self.context = context
self.name = element.nsProp( name, None )
@@ -401,7 +401,7 @@ class gl_enum( gl_item ):
-class gl_parameter:
+class gl_parameter(object):
def __init__(self, element, context):
self.name = element.nsProp( name, None )
@@ -780,7 +780,7 @@ class gl_function( gl_item ):
return _dispatch_stub_%u % (self.offset)
-class gl_item_factory:
+class gl_item_factory(object):
Factory to create objects derived from gl_item.
def create_item(self, item_name, element, context):
@@ -798,7 +798,7 @@ class gl_item_factory:
return None
-class gl_api:
+class gl_api(object):
def __init__(self, factory):
self.functions_by_name = {}
self.enums_by_name = {}
diff --git a/src/mapi/glapi/gen/typeexpr.py b/src/mapi/glapi/gen/typeexpr.py
index 6cc71cb..ed23d23 100644
--- a/src/mapi/glapi/gen/typeexpr.py
+++ b/src/mapi/glapi/gen/typeexpr.py
@@ -27,7 +27,7 @@
import string, copy
-class type_node:
+class type_node(object):
def __init__(self):
self.pointer = 0 # bool
self.const = 0# bool
@@ -65,7 +65,7 @@ class type_node:
return s
-class type_table:
+class type_table(object):
def __init__(self):
self.types_by_name = {}
return
@@ -109,7 +109,7 @@ def create_initial_types():
return
-class type_expression:
+class type_expression(object):
built_in_types = None
def __init__(self, type_string, extra_types = None):
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Mesa (master): glapi: Add es1 and es2 attributes to XML.
Module: Mesa Branch: master Commit: 81a7f5078130c66855c56afc6c9803c89bf05ee8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=81a7f5078130c66855c56afc6c9803c89bf05ee8 Author: Paul Berry stereotype...@gmail.com Date: Wed Oct 10 16:28:42 2012 -0700 glapi: Add es1 and es2 attributes to XML. Currently, the set of functions which exist in GLES1 or GLES2 is determined by hardcoded lists of function names in gles_api.py. This patch encodes that information into the XML files using new attributes, es1 and es2. The es1 attribute denotes the first version of GLES 1 in which the function exists (e.g. es1=1.1 means the function exists in GLES 1.1 but not GLES 1.0). none (the default) means the function is not available in any version of GLES 1. The es2 attribute denotes the first version of GLES 2/3 in which the function exists (e.g. es2=2.0 means the function exists in both GLES 2.0 and GLES 3.0). none (the default) means the function is not available in any version of GLES 2 or GLES 3. Note that since GLES 3 is a strict superset of GLES 2, there is no need for a separate attribute for it; instead, 'es2=3.0' should be used to denote functions that are present in GLES 3 but not GLES 2. This patch only adds information about GLES versions 1.0, 1.1, and 2.0. Later patches will modify the python code generation scripts to use this information rather than the hardcoded lists in gles_api.py. Tested-by: Matt Turner matts...@gmail.com Reviewed-by: Ian Romanick ian.d.roman...@intel.com --- src/mapi/glapi/gen/ARB_ES2_compatibility.xml | 10 +- src/mapi/glapi/gen/ARB_framebuffer_object.xml | 38 ++- src/mapi/glapi/gen/OES_EGL_image.xml |6 +- src/mapi/glapi/gen/OES_fixed_point.xml| 125 ++--- src/mapi/glapi/gen/OES_single_precision.xml | 18 +- src/mapi/glapi/gen/es_EXT.xml | 159 src/mapi/glapi/gen/gl_API.dtd |4 +- src/mapi/glapi/gen/gl_API.xml | 349 + src/mapi/glapi/gen/gl_and_es_API.xml | 127 ++--- 9 files changed, 502 insertions(+), 334 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=81a7f5078130c66855c56afc6c9803c89bf05ee8 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glapi: Read GLES information from XML.
Module: Mesa
Branch: master
Commit: cd4ce16c450d2cf99fb508d1be1a111a2b1f9423
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd4ce16c450d2cf99fb508d1be1a111a2b1f9423
Author: Paul Berry stereotype...@gmail.com
Date: Wed Oct 10 16:48:08 2012 -0700
glapi: Read GLES information from XML.
Tested-by: Matt Turner matts...@gmail.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mapi/glapi/gen/gl_XML.py | 48 ++
1 files changed, 48 insertions(+), 0 deletions(-)
diff --git a/src/mapi/glapi/gen/gl_XML.py b/src/mapi/glapi/gen/gl_XML.py
index f956730..ef7ed51 100644
--- a/src/mapi/glapi/gen/gl_XML.py
+++ b/src/mapi/glapi/gen/gl_XML.py
@@ -25,6 +25,7 @@
# Authors:
#Ian Romanick i...@us.ibm.com
+from decimal import Decimal
import libxml2
import re, sys, string
import typeexpr
@@ -606,6 +607,16 @@ class gl_function( gl_item ):
self.initialized = 0
self.images = []
+# self.entry_point_api_map[name][api] is a decimal value
+# indicating the earliest version of the given API in which
+# each entry point exists. Every entry point is included in
+# the first level of the map; the second level of the map only
+# lists APIs which contain the entry point in at least one
+# version. For example,
+# self.entry_point_gles_map['ClipPlanex'] == { 'es1':
+# Decimal('1.1') }.
+self.entry_point_api_map = {}
+
self.assign_offset = 0
self.static_entry_points = []
@@ -634,6 +645,14 @@ class gl_function( gl_item ):
self.static_entry_points.append(name)
self.entry_points.append( name )
+
+self.entry_point_api_map[name] = {}
+for api in ('es1', 'es2'):
+version_str = element.nsProp(api, None)
+assert version_str is not None
+if version_str != 'none':
+self.entry_point_api_map[name][api] = Decimal(version_str)
+
if alias:
true_name = alias
else:
@@ -779,6 +798,22 @@ class gl_function( gl_item ):
else:
return _dispatch_stub_%u % (self.offset)
+def entry_points_for_api_version(self, api, version = None):
+Return a list of the entry point names for this function
+which are supported in the given API (and optionally, version).
+
+Use the decimal.Decimal type to precisely express non-integer
+versions.
+
+result = []
+for entry_point, api_to_ver in self.entry_point_api_map.iteritems():
+if api not in api_to_ver:
+continue
+if version is not None and version api_to_ver[api]:
+continue
+result.append(entry_point)
+return result
+
class gl_item_factory(object):
Factory to create objects derived from gl_item.
@@ -825,6 +860,19 @@ class gl_api(object):
self.functions_by_name = functions_by_name
+def filter_functions_by_api(self, api, version = None):
+Filter out entry points not in the given API (or
+optionally, not in the given version of the given API).
+
+functions_by_name = {}
+for func in self.functions_by_name.itervalues():
+entry_points = func.entry_points_for_api_version(api, version)
+if entry_points:
+func.filter_entry_points(entry_points)
+functions_by_name[func.name] = func
+
+self.functions_by_name = functions_by_name
+
def process_element(self, doc):
element = doc.children
while element.type != element or element.name != OpenGLAPI:
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Mesa (master): glapi: Use GLES information from XML rather than gles_api.py .
Module: Mesa
Branch: master
Commit: e378cd77bc63ebeaec42030da8f5ceb1d9c4be10
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e378cd77bc63ebeaec42030da8f5ceb1d9c4be10
Author: Paul Berry stereotype...@gmail.com
Date: Wed Oct 10 16:48:08 2012 -0700
glapi: Use GLES information from XML rather than gles_api.py.
Tested-by: Matt Turner matts...@gmail.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mapi/glapi/gen/gl_table.py |9 +
src/mapi/glapi/gen/remap_helper.py |9 +
2 files changed, 2 insertions(+), 16 deletions(-)
diff --git a/src/mapi/glapi/gen/gl_table.py b/src/mapi/glapi/gen/gl_table.py
index 856aedb..382eaaf 100644
--- a/src/mapi/glapi/gen/gl_table.py
+++ b/src/mapi/glapi/gen/gl_table.py
@@ -254,13 +254,6 @@ if __name__ == '__main__':
api = gl_XML.parse_GL_API( file_name )
if es is not None:
-import gles_api
-
-api_map = {
-'es1': gles_api.es1_api,
-'es2': gles_api.es2_api,
-}
-
-api.filter_functions(api_map[es])
+api.filter_functions_by_api(es)
printer.Print( api )
diff --git a/src/mapi/glapi/gen/remap_helper.py
b/src/mapi/glapi/gen/remap_helper.py
index eae1cf3..e1a13d0 100644
--- a/src/mapi/glapi/gen/remap_helper.py
+++ b/src/mapi/glapi/gen/remap_helper.py
@@ -186,14 +186,7 @@ if __name__ == '__main__':
api = gl_XML.parse_GL_API( file_name )
if es is not None:
-import gles_api
-
-api_map = {
-'es1': gles_api.es1_api,
-'es2': gles_api.es2_api,
-}
-
-api.filter_functions(api_map[es])
+api.filter_functions_by_api(es)
printer = PrintGlRemap()
printer.Print( api )
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Mesa (master): mapi_abi: Collect all imports at top of file.
Module: Mesa
Branch: master
Commit: 155eff56b1c0a3a6119952db97f2fc5cb5f19e46
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=155eff56b1c0a3a6119952db97f2fc5cb5f19e46
Author: Paul Berry stereotype...@gmail.com
Date: Wed Oct 10 14:52:48 2012 -0700
mapi_abi: Collect all imports at top of file.
Tested-by: Matt Turner matts...@gmail.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mapi/mapi/mapi_abi.py | 13 +
1 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/src/mapi/mapi/mapi_abi.py b/src/mapi/mapi/mapi_abi.py
index c18dd82..4fd1582 100644
--- a/src/mapi/mapi/mapi_abi.py
+++ b/src/mapi/mapi/mapi_abi.py
@@ -34,6 +34,11 @@ sys.path.append(GLAPI)
import re
from optparse import OptionParser
+import gl_XML
+import glX_XML
+import copy
+from gles_api import es1_api, es2_api
+
# number of dynamic entries
ABI_NUM_DYNAMIC_ENTRIES = 256
@@ -133,8 +138,6 @@ class ABIEntry(object):
def abi_parse_xml(xml):
Parse a GLAPI XML file for ABI entries.
-import gl_XML, glX_XML
-
api = gl_XML.parse_GL_API(xml, glX_XML.glx_item_factory())
entry_dict = {}
@@ -711,8 +714,6 @@ class GLAPIPrinter(ABIPrinter):
def _get_api_entries(self, entries, api):
Override the entry attributes according to API.
-import copy
-
# no override
if api is None:
return entries
@@ -760,8 +761,6 @@ class ES1APIPrinter(GLAPIPrinter):
OpenGL ES 1.x API Printer
def __init__(self, entries):
-from gles_api import es1_api
-
super(ES1APIPrinter, self).__init__(entries, es1_api)
self.prefix_lib = 'gl'
self.prefix_warn = 'gl'
@@ -779,8 +778,6 @@ class ES2APIPrinter(GLAPIPrinter):
OpenGL ES 2.x API Printer
def __init__(self, entries):
-from gles_api import es2_api
-
super(ES2APIPrinter, self).__init__(entries, es2_api)
self.prefix_lib = 'gl'
self.prefix_warn = 'gl'
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Mesa (master): mapi_abi: Remove sanity check that all GLES functions are present.
Module: Mesa
Branch: master
Commit: 77ed171f27de5c4f50720263b419e26d6715e621
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=77ed171f27de5c4f50720263b419e26d6715e621
Author: Paul Berry stereotype...@gmail.com
Date: Wed Oct 10 15:07:00 2012 -0700
mapi_abi: Remove sanity check that all GLES functions are present.
Currently mapi_abi.py uses hardcoded lists of function names (in
gles_api.py) to determine which functions need to be included in the
GLES 1 or GLES 2 API. This patch removes a sanity check which
verified that all GLES functions listed in the hardcoded lists were
actually present in the XML.
Later patches in this series will modify mapi_abi.py to determine
which functions need to be included in the GLES 1 or GLES 2 API based
directly on the XML. Once that is done, the sanity check will be
redundant. Removing the sanity check now will simplify the patches to
come.
Tested-by: Matt Turner matts...@gmail.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mapi/mapi/mapi_abi.py |5 -
1 files changed, 0 insertions(+), 5 deletions(-)
diff --git a/src/mapi/mapi/mapi_abi.py b/src/mapi/mapi/mapi_abi.py
index 4fd1582..ce4e047 100644
--- a/src/mapi/mapi/mapi_abi.py
+++ b/src/mapi/mapi/mapi_abi.py
@@ -730,11 +730,6 @@ class GLAPIPrinter(ABIPrinter):
api_entries[ent.name] = ent
-# sanity check
-missed = [name for name in api if name not in api_entries]
-if missed:
-raise Exception('%s is missing' % str(missed))
-
entries = api_entries.values()
entries.sort()
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Mesa (master): mapi_abi: Get rid of unnecessary copy.
Module: Mesa
Branch: master
Commit: 4f6fc905c68fc1f7deab27d0b931f58e0558630e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f6fc905c68fc1f7deab27d0b931f58e0558630e
Author: Paul Berry stereotype...@gmail.com
Date: Wed Oct 10 15:10:00 2012 -0700
mapi_abi: Get rid of unnecessary copy.
Previously, _get_api_entries() would make a deep copy of each element
in the entries table before modifying the 'hidden' and 'handcode'
attributes. This was unnecessary, since the entries aren't used again
after this function. Removing the copy simplifies the code, because
it is no longer necessary to adjust the alias pointers to point to the
copied entries.
Tested-by: Matt Turner matts...@gmail.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mapi/mapi/mapi_abi.py | 19 +++
1 files changed, 3 insertions(+), 16 deletions(-)
diff --git a/src/mapi/mapi/mapi_abi.py b/src/mapi/mapi/mapi_abi.py
index ce4e047..c2d9085 100644
--- a/src/mapi/mapi/mapi_abi.py
+++ b/src/mapi/mapi/mapi_abi.py
@@ -36,7 +36,6 @@ import re
from optparse import OptionParser
import gl_XML
import glX_XML
-import copy
from gles_api import es1_api, es2_api
@@ -690,8 +689,8 @@ class GLAPIPrinter(ABIPrinter):
OpenGL API Printer
def __init__(self, entries, api=None):
-api_entries = self._get_api_entries(entries, api)
-super(GLAPIPrinter, self).__init__(api_entries)
+self._override_for_api(entries, api)
+super(GLAPIPrinter, self).__init__(entries)
self.api_defines = ['GL_GLEXT_PROTOTYPES']
self.api_headers = ['GL/gl.h', 'GL/glext.h']
@@ -712,28 +711,16 @@ class GLAPIPrinter(ABIPrinter):
self.c_header = self._get_c_header()
-def _get_api_entries(self, entries, api):
+def _override_for_api(self, entries, api):
Override the entry attributes according to API.
# no override
if api is None:
return entries
-api_entries = {}
for ent in entries:
-ent = copy.copy(ent)
-
# override 'hidden' and 'handcode'
ent.hidden = ent.name not in api
ent.handcode = False
-if ent.alias:
-ent.alias = api_entries[ent.alias.name]
-
-api_entries[ent.name] = ent
-
-entries = api_entries.values()
-entries.sort()
-
-return entries
def _get_c_header(self):
header = #ifndef _GLAPI_TMP_H_
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Mesa (master): mapi_abi: Override 'hidden' and 'handcode' attributes using polymorphism.
Module: Mesa Branch: master Commit: 137f8ef2258cda926074d1c4708b4925f7da71a8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=137f8ef2258cda926074d1c4708b4925f7da71a8 Author: Paul Berry stereotype...@gmail.com Date: Wed Oct 10 15:19:21 2012 -0700 mapi_abi: Override 'hidden' and 'handcode' attributes using polymorphism. Previously, the ES1, ES2, and shared GLAPI printers passed a list of function names to the base class constructor, which was used by the _override_for_api() function to loop over all the API functions and adjust their 'hidden' and 'handcode' attributes as appropriate for the API flavour being code-generated. This patch lifts the loop from _override_for_api() into its caller, and makes it into a polymorphic function, so that the derived classes can customize its behaviour directly. In a future patch, this will allow us to override the 'hidden' and 'handcode' attributes based on information from the XML rather than a list of functions. Tested-by: Matt Turner matts...@gmail.com Reviewed-by: Ian Romanick ian.d.roman...@intel.com --- src/mapi/mapi/mapi_abi.py | 38 +++--- 1 files changed, 23 insertions(+), 15 deletions(-) diff --git a/src/mapi/mapi/mapi_abi.py b/src/mapi/mapi/mapi_abi.py index c2d9085..b1b08a2 100644 --- a/src/mapi/mapi/mapi_abi.py +++ b/src/mapi/mapi/mapi_abi.py @@ -688,8 +688,9 @@ class ABIPrinter(object): class GLAPIPrinter(ABIPrinter): OpenGL API Printer -def __init__(self, entries, api=None): -self._override_for_api(entries, api) +def __init__(self, entries): +for ent in entries: +self._override_for_api(ent) super(GLAPIPrinter, self).__init__(entries) self.api_defines = ['GL_GLEXT_PROTOTYPES'] @@ -711,16 +712,11 @@ class GLAPIPrinter(ABIPrinter): self.c_header = self._get_c_header() -def _override_for_api(self, entries, api): -Override the entry attributes according to API. -# no override -if api is None: -return entries - -for ent in entries: -# override 'hidden' and 'handcode' -ent.hidden = ent.name not in api -ent.handcode = False +def _override_for_api(self, ent): +Override attributes of an entry if necessary for this +printer. +# By default, no override is necessary. +pass def _get_c_header(self): header = #ifndef _GLAPI_TMP_H_ @@ -743,10 +739,14 @@ class ES1APIPrinter(GLAPIPrinter): OpenGL ES 1.x API Printer def __init__(self, entries): -super(ES1APIPrinter, self).__init__(entries, es1_api) +super(ES1APIPrinter, self).__init__(entries) self.prefix_lib = 'gl' self.prefix_warn = 'gl' +def _override_for_api(self, ent): +ent.hidden = ent.name not in es1_api +ent.handcode = False + def _get_c_header(self): header = #ifndef _GLAPI_TMP_H_ #define _GLAPI_TMP_H_ @@ -760,10 +760,14 @@ class ES2APIPrinter(GLAPIPrinter): OpenGL ES 2.x API Printer def __init__(self, entries): -super(ES2APIPrinter, self).__init__(entries, es2_api) +super(ES2APIPrinter, self).__init__(entries) self.prefix_lib = 'gl' self.prefix_warn = 'gl' +def _override_for_api(self, ent): +ent.hidden = ent.name not in es2_api +ent.handcode = False + def _get_c_header(self): header = #ifndef _GLAPI_TMP_H_ #define _GLAPI_TMP_H_ @@ -777,7 +781,7 @@ class SharedGLAPIPrinter(GLAPIPrinter): Shared GLAPI API Printer def __init__(self, entries): -super(SharedGLAPIPrinter, self).__init__(entries, []) +super(SharedGLAPIPrinter, self).__init__(entries) self.lib_need_table_size = True self.lib_need_noop_array = True @@ -788,6 +792,10 @@ class SharedGLAPIPrinter(GLAPIPrinter): self.prefix_lib = 'shared' self.prefix_warn = 'gl' +def _override_for_api(self, ent): +ent.hidden = True +ent.handcode = False + def _get_c_header(self): header = #ifndef _GLAPI_TMP_H_ #define _GLAPI_TMP_H_ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glapi: Delete gles_api.py, since it is no longer used.
Module: Mesa Branch: master Commit: 381186dbf8e0dcf9f84564968eec4872122af9b4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=381186dbf8e0dcf9f84564968eec4872122af9b4 Author: Paul Berry stereotype...@gmail.com Date: Wed Oct 10 16:59:20 2012 -0700 glapi: Delete gles_api.py, since it is no longer used. Tested-by: Matt Turner matts...@gmail.com Reviewed-by: Ian Romanick ian.d.roman...@intel.com --- src/mapi/glapi/gen/gl_and_es_API.xml |5 - src/mapi/glapi/gen/gles_api.py | 467 -- 2 files changed, 0 insertions(+), 472 deletions(-) diff --git a/src/mapi/glapi/gen/gl_and_es_API.xml b/src/mapi/glapi/gen/gl_and_es_API.xml index 5271041..8e000a8 100644 --- a/src/mapi/glapi/gen/gl_and_es_API.xml +++ b/src/mapi/glapi/gen/gl_and_es_API.xml @@ -3,11 +3,6 @@ !-- OpenGL + OpenGL ES -- -!-- IMPORTANT - Remember to update gles_api.py when new OpenGL ES specific entry points - are added. Otherwise, they will be filtered out. --- - OpenGLAPI xi:include href=gl_API.xml xmlns:xi=http://www.w3.org/2001/XInclude/ diff --git a/src/mapi/glapi/gen/gles_api.py b/src/mapi/glapi/gen/gles_api.py deleted file mode 100644 index 3bee1a6..000 --- a/src/mapi/glapi/gen/gles_api.py +++ /dev/null @@ -1,467 +0,0 @@ -#!/usr/bin/env python - -# Mesa 3-D graphics library -# Version: 7.12 -# -# Copyright (C) 2011 LunarG Inc. -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the Software), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included -# in all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -# DEALINGS IN THE SOFTWARE. -# -# Authors: -#Chia-I Wu o...@lunarg.com - -# These info should be part of GLAPI XML. Until that is possible, scripts have -# to use tables here to filter gl_api. - -es1_core = ( -# OpenGL ES 1.1 -'ActiveTexture', -'AlphaFunc', -'AlphaFuncx', -'BindBuffer', -'BindTexture', -'BlendFunc', -'BufferData', -'BufferSubData', -'Clear', -'ClearColor', -'ClearColorx', -'ClearDepthf', -'ClearDepthx', -'ClearStencil', -'ClientActiveTexture', -'ClipPlanef', -'ClipPlanex', -'Color4f', -'Color4ub', -'Color4x', -'ColorMask', -'ColorPointer', -'CompressedTexImage2D', -'CompressedTexSubImage2D', -'CopyTexImage2D', -'CopyTexSubImage2D', -'CullFace', -'DeleteBuffers', -'DeleteTextures', -'DepthFunc', -'DepthMask', -'DepthRangef', -'DepthRangex', -'Disable', -'DisableClientState', -'DrawArrays', -'DrawElements', -'Enable', -'EnableClientState', -'Finish', -'Flush', -'Fogf', -'Fogfv', -'Fogx', -'Fogxv', -'FrontFace', -'Frustumf', -'Frustumx', -'GenBuffers', -'GenTextures', -'GetBooleanv', -'GetBufferParameteriv', -'GetClipPlanef', -'GetClipPlanex', -'GetError', -'GetFixedv', -'GetFloatv', -'GetIntegerv', -'GetLightfv', -'GetLightxv', -'GetMaterialfv', -'GetMaterialxv', -'GetPointerv', -'GetString', -'GetTexEnvfv', -'GetTexEnviv', -'GetTexEnvxv', -'GetTexParameterfv', -'GetTexParameteriv', -'GetTexParameterxv', -'Hint', -'IsBuffer', -'IsEnabled', -'IsTexture', -'Lightf', -'Lightfv', -'LightModelf', -'LightModelfv', -'LightModelx', -'LightModelxv', -'Lightx', -'Lightxv', -'LineWidth', -'LineWidthx', -'LoadIdentity', -'LoadMatrixf', -'LoadMatrixx', -'LogicOp', -'Materialf', -'Materialfv', -'Materialx', -'Materialxv', -'MatrixMode', -'MultiTexCoord4f', -'MultiTexCoord4x', -'MultMatrixf', -'MultMatrixx', -'Normal3f
Mesa (master): mapi_abi: Use GLES information from XML rather than gles_api .py.
Module: Mesa
Branch: master
Commit: c8ad6ef1c616795baa1fb14eb78205972967af76
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c8ad6ef1c616795baa1fb14eb78205972967af76
Author: Paul Berry stereotype...@gmail.com
Date: Wed Oct 10 16:31:01 2012 -0700
mapi_abi: Use GLES information from XML rather than gles_api.py.
Note: mapi_abi can consume API information from either XML or a .csv
file. A side effect of this change is that the ES1 and ES2 API
printers can only be used with XML input now. That's ok, since the
.csv input format is only used for the OpenVG API.
Tested-by: Matt Turner matts...@gmail.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mapi/mapi/mapi_abi.py | 16 +++-
1 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/src/mapi/mapi/mapi_abi.py b/src/mapi/mapi/mapi_abi.py
index b1b08a2..30ffe7b 100644
--- a/src/mapi/mapi/mapi_abi.py
+++ b/src/mapi/mapi/mapi_abi.py
@@ -36,7 +36,6 @@ import re
from optparse import OptionParser
import gl_XML
import glX_XML
-from gles_api import es1_api, es2_api
# number of dynamic entries
@@ -48,13 +47,14 @@ class ABIEntry(object):
_match_c_param = re.compile(
'^(?Ptype[\w\s*]+?)(?Pname\w+)(\[(?Parray\d+)\])?$')
-def __init__(self, cols, attrs):
+def __init__(self, cols, attrs, xml_data = None):
self._parse(cols)
self.slot = attrs['slot']
self.hidden = attrs['hidden']
self.alias = attrs['alias']
self.handcode = attrs['handcode']
+self.xml_data = xml_data
def c_prototype(self):
return '%s %s(%s)' % (self.c_return(), self.name, self.c_params())
@@ -177,7 +177,7 @@ def abi_parse_xml(xml):
params = func.get_parameter_string(name)
cols.extend([p.strip() for p in params.split(',')])
-ent = ABIEntry(cols, attrs)
+ent = ABIEntry(cols, attrs, func)
entry_dict[ent.name] = ent
entries = entry_dict.values()
@@ -744,7 +744,10 @@ class ES1APIPrinter(GLAPIPrinter):
self.prefix_warn = 'gl'
def _override_for_api(self, ent):
-ent.hidden = ent.name not in es1_api
+if ent.xml_data is None:
+raise Exception('ES2 API printer requires XML input')
+ent.hidden = ent.name not in \
+ent.xml_data.entry_points_for_api_version('es1')
ent.handcode = False
def _get_c_header(self):
@@ -765,7 +768,10 @@ class ES2APIPrinter(GLAPIPrinter):
self.prefix_warn = 'gl'
def _override_for_api(self, ent):
-ent.hidden = ent.name not in es2_api
+if ent.xml_data is None:
+raise Exception('ES2 API printer requires XML input')
+ent.hidden = ent.name not in \
+ent.xml_data.entry_points_for_api_version('es2')
ent.handcode = False
def _get_c_header(self):
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Mesa (master): glapi: Reformat python code generation scripts to use 4-space indentation.
Module: Mesa Branch: master Commit: 99802519b47983be8301a0283f2946a44a9656a5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=99802519b47983be8301a0283f2946a44a9656a5 Author: Paul Berry stereotype...@gmail.com Date: Wed Oct 10 07:20:57 2012 -0700 glapi: Reformat python code generation scripts to use 4-space indentation. This brings us into accordance with the official Python style guide (http://www.python.org/dev/peps/pep-0008/#indentation). To preserve the indentation of the c code that is generated by these scripts, I've avoided re-indenting triple-quoted strings (unless those strings appear to be docstrings). Acked-by: Kenneth Graunke kenn...@whitecape.org Reviewed-by: Ian Romanick ian.d.roman...@intel.com --- src/mapi/glapi/gen/extension_helper.py | 330 src/mapi/glapi/gen/glX_XML.py | 1026 +++--- src/mapi/glapi/gen/glX_doc.py | 472 +- src/mapi/glapi/gen/glX_proto_common.py | 88 +- src/mapi/glapi/gen/glX_proto_recv.py | 1018 +++--- src/mapi/glapi/gen/glX_proto_send.py | 1532 src/mapi/glapi/gen/glX_proto_size.py | 1218 +- src/mapi/glapi/gen/glX_server_table.py | 712 src/mapi/glapi/gen/gl_SPARC_asm.py | 440 +- src/mapi/glapi/gen/gl_XML.py | 1376 ++-- src/mapi/glapi/gen/gl_apitemp.py | 418 +- src/mapi/glapi/gen/gl_enums.py | 192 ++-- src/mapi/glapi/gen/gl_gentable.py | 76 +- src/mapi/glapi/gen/gl_offsets.py | 138 ++-- src/mapi/glapi/gen/gl_procs.py | 300 src/mapi/glapi/gen/gl_table.py | 392 src/mapi/glapi/gen/gl_x86-64_asm.py| 546 ++-- src/mapi/glapi/gen/gl_x86_asm.py | 412 +- src/mapi/glapi/gen/mesadef.py | 306 src/mapi/glapi/gen/remap_helper.py | 308 src/mapi/glapi/gen/typeexpr.py | 378 21 files changed, 5839 insertions(+), 5839 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=99802519b47983be8301a0283f2946a44a9656a5 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa: don't enable glVertexPointer() when using API_OPENGLES2.
Module: Mesa
Branch: master
Commit: 8f0b81bf7ddcdf5715a3e00af67395b91f27a243
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f0b81bf7ddcdf5715a3e00af67395b91f27a243
Author: Paul Berry stereotype...@gmail.com
Date: Wed Oct 3 14:20:17 2012 -0700
mesa: don't enable glVertexPointer() when using API_OPENGLES2.
This function is only present in GLES1 and in the OpenGL compatibility
profile.
Fixes the following make check failure:
[--] 1 test from DispatchSanity_test
[ RUN ] DispatchSanity_test.GLES2
Mesa warning: couldn't open libtxc_dxtn.so, software DXTn
compression/decompression unavailable
dispatch_sanity.cpp:122: Failure
Value of: table[i]
Actual: 0x4de54e
Expected: (_glapi_proc) _mesa_generic_nop
Which is: 0x41af72
i = 321
[ FAILED ] DispatchSanity_test.GLES2 (4 ms)
[--] 1 test from DispatchSanity_test (4 ms total)
NOTE: This is a candidate for stable release branches.
Reviewed-by: Oliver McFadden oliver.mcfad...@linux.intel.com
Tested-by: Oliver McFadden oliver.mcfad...@linux.intel.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/main/api_exec.c |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/api_exec.c b/src/mesa/main/api_exec.c
index ddf7c7f..f42da94 100644
--- a/src/mesa/main/api_exec.c
+++ b/src/mesa/main/api_exec.c
@@ -335,8 +335,6 @@ _mesa_create_exec_table(struct gl_context *ctx)
SET_NormalPointer(exec, _mesa_NormalPointer);
SET_PrioritizeTextures(exec, _mesa_PrioritizeTextures);
SET_TexCoordPointer(exec, _mesa_TexCoordPointer);
- }
- if (ctx-API != API_OPENGL_CORE) {
SET_VertexPointer(exec, _mesa_VertexPointer);
}
#endif
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Mesa (master): register_allocate: don' t consider trivially colorable registers for spilling.
Module: Mesa
Branch: master
Commit: 551c991606e543c3a264a762026f11348b37947e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=551c991606e543c3a264a762026f11348b37947e
Author: Paul Berry stereotype...@gmail.com
Date: Fri Sep 28 14:21:38 2012 -0700
register_allocate: don't consider trivially colorable registers for spilling.
Previously, we considered all registers as candidates for spilling.
This was counterproductive--for any registers that have already been
removed from the interference graph, there is no benefit to spilling
them, since they don't contribute to register pressure.
This patch ensures that we will only try to spill registers that are
still in the interference graph after register allocation has failed.
This is consistent with the recommendations of the paper Retargetable
Graph-Coloring Register Allocation for Irregular Architectures, on
which our register allocator is based.
Reviewed-by: Matt Turner matts...@gmail.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/program/register_allocate.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/mesa/program/register_allocate.c
b/src/mesa/program/register_allocate.c
index 97d4e33..88793db 100644
--- a/src/mesa/program/register_allocate.c
+++ b/src/mesa/program/register_allocate.c
@@ -555,6 +555,13 @@ ra_get_best_spill_node(struct ra_graph *g)
if (cost = 0.0)
continue;
+ /* Only consider registers for spilling if they are still in the
+ * interference graph (those on the stack have already been proven to be
+ * allocatable without spilling).
+ */
+ if (g-nodes[n].in_stack)
+ continue;
+
benefit = ra_get_spill_benefit(g, n);
if (benefit / cost best_benefit) {
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Mesa (9.0): i965/gen6+: Adjust stencil buffer size after computing miptree layout.
Module: Mesa
Branch: 9.0
Commit: 5db1deab5118a986167ea6e8f8c7c196c74457c1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5db1deab5118a986167ea6e8f8c7c196c74457c1
Author: Paul Berry stereotype...@gmail.com
Date: Tue Sep 4 07:57:37 2012 -0700
i965/gen6+: Adjust stencil buffer size after computing miptree layout.
Since Gen6+ stencil buffers use W-tiling (a tiling arrangement which
drm and the kernel are not aware of) we need to round up the width and
height of a stencil buffer to multiples of the W-tile size (64x64)
before allocating a stencil buffer. Previously, we rounded up the
size of the base miplevel, and then computed the miptree layout based
on the rounded up size. This was incorrect, because it meant that the
total size of the miptree would not be properly W-tile aligned, and
therefore we would not always allocate enough pages.
(Note: even though the GL API doesn't allow creation of mipmapped
stencil textures, it does allow mipmapping of a combined depth/stencil
texture, and on Gen6+, a combined depth/stencil texture is internally
implemented as a pair of separate depth and stencil buffers.)
For example, on Sandy Bridge, when allocating a mipmapped stencil
texture of size 128x128, we would first round up to the nearest
multiple of 64x64 (causing no change to the size), and then compute
the miptree layout (whose size worked out to 128x196). Then we would
request an allocation of 128*196 bytes (6.125 pages), causing 7 pages
to be allocated to the texture. However, the texture needs 8 pages,
since each W-tile occupies a page, and it takes 2 W-tiles to cover a
width of 128 and 4 W-tiles to cover a height of 196.
This patch changes the order of operations so that the miptree layout
is computed first and then the total size of the miptree is rounded up
to be W-tile aligned.
NOTE: This is a candidate for the 8.0 release branch.
Reviewed-by: Eric Anholt e...@anholt.net
(cherry picked from commit bde833c9d014ad8aebfab0d2285184d7e6d5896d)
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 28 +--
1 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 24cd9e9..dbfddc8 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -200,6 +200,7 @@ intel_miptree_create(struct intel_context *intel,
uint32_t tiling = I915_TILING_NONE;
GLenum base_format;
bool wraps_etc1 = false;
+ GLuint total_width, total_height;
if (format == MESA_FORMAT_ETC1_RGB8) {
format = MESA_FORMAT_RGBX_REV;
@@ -231,16 +232,6 @@ intel_miptree_create(struct intel_context *intel,
tiling = I915_TILING_X;
}
- if (format == MESA_FORMAT_S8) {
- /* The stencil buffer is W tiled. However, we request from the kernel a
- * non-tiled buffer because the GTT is incapable of W fencing. So round
- * up the width and height to match the size of W tiles (64x64).
- */
- tiling = I915_TILING_NONE;
- width0 = ALIGN(width0, 64);
- height0 = ALIGN(height0, 64);
- }
-
mt = intel_miptree_create_internal(intel, target, format,
first_level, last_level, width0,
height0, depth0,
@@ -253,12 +244,25 @@ intel_miptree_create(struct intel_context *intel,
return NULL;
}
+ total_width = mt-total_width;
+ total_height = mt-total_height;
+
+ if (format == MESA_FORMAT_S8) {
+ /* The stencil buffer is W tiled. However, we request from the kernel a
+ * non-tiled buffer because the GTT is incapable of W fencing. So round
+ * up the width and height to match the size of W tiles (64x64).
+ */
+ tiling = I915_TILING_NONE;
+ total_width = ALIGN(total_width, 64);
+ total_height = ALIGN(total_height, 64);
+ }
+
mt-wraps_etc1 = wraps_etc1;
mt-region = intel_region_alloc(intel-intelScreen,
tiling,
mt-cpp,
- mt-total_width,
- mt-total_height,
+ total_width,
+ total_height,
expect_accelerated_upload);
mt-offset = 0;
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Mesa (9.0): i965/blorp: Clarify why width/ height must be adjusted for Gen6 IMS surfaces.
Module: Mesa
Branch: 9.0
Commit: cb9765ca94b5a73eaafe0468ed40052dce55fdc8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb9765ca94b5a73eaafe0468ed40052dce55fdc8
Author: Paul Berry stereotype...@gmail.com
Date: Wed Aug 29 12:04:30 2012 -0700
i965/blorp: Clarify why width/height must be adjusted for Gen6 IMS surfaces.
Also add a clarifying comment for why the width/height doesn't need
adjustment for Gen7.
Reviewed-by: Eric Anholt e...@anholt.net
(cherry picked from commit 32c7b2769cbe80ff56d1c73c4f9b62f13f577c8d)
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp |6 +-
src/mesa/drivers/dri/i965/gen7_blorp.cpp |5 +
2 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 995b507..8a22fe3 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -415,7 +415,11 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
uint32_t wm_surf_offset;
uint32_t width, height;
surface-get_miplevel_dims(width, height);
- if (surface-num_samples 1) { /* TODO: seems clumsy */
+ if (surface-num_samples 1) {
+ /* Since gen6 uses INTEL_MSAA_LAYOUT_IMS, width and height are measured
+ * in samples. But SURFACE_STATE wants them in pixels, so we need to
+ * divide them each by 2.
+ */
width /= 2;
height /= 2;
}
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index a65a975..e23868d 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -144,6 +144,11 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
uint32_t wm_surf_offset;
uint32_t width, height;
surface-get_miplevel_dims(width, height);
+ /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
+* color surfaces, width and height are measured in pixels; we don't need
+* to divide them by 2 as we do for Gen6 (see
+* gen6_blorp_emit_surface_state).
+*/
if (surface-map_stencil_as_y_tiled) {
width *= 2;
height /= 2;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (9.0): i965/blorp: Change gl_renderbuffer* params to intel_renderbuffer*.
Module: Mesa
Branch: 9.0
Commit: 5c66640ac7c271a96f66f4cb49adad54eb58cc47
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c66640ac7c271a96f66f4cb49adad54eb58cc47
Author: Paul Berry stereotype...@gmail.com
Date: Wed Aug 15 14:51:56 2012 -0700
i965/blorp: Change gl_renderbuffer* params to intel_renderbuffer*.
This makes it more convenient for blorp functions to get access to
Intel-specific data inside the renderbuffer objects.
Reviewed-by: Eric Anholt e...@anholt.net
(cherry picked from commit e14b1288ef5b5b6091facaecd42e86f0a8157f28)
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 60 ++
1 files changed, 32 insertions(+), 28 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 1e49ac5..0b2dbe3 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -112,9 +112,8 @@ clip_or_scissor(bool mirror, GLint src_x0, GLint src_x1,
GLint dst_x0,
static struct intel_mipmap_tree *
-find_miptree(GLbitfield buffer_bit, struct gl_renderbuffer *rb)
+find_miptree(GLbitfield buffer_bit, struct intel_renderbuffer *irb)
{
- struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_mipmap_tree *mt = irb-mt;
if (buffer_bit == GL_STENCIL_BUFFER_BIT mt-stencil_mt)
mt = mt-stencil_mt;
@@ -141,42 +140,43 @@ brw_blorp_blit_miptrees(struct intel_context *intel,
static void
do_blorp_blit(struct intel_context *intel, GLbitfield buffer_bit,
- struct gl_renderbuffer *src_rb, struct gl_renderbuffer *dst_rb,
+ struct intel_renderbuffer *src_irb,
+ struct intel_renderbuffer *dst_irb,
GLint srcX0, GLint srcY0,
GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
bool mirror_x, bool mirror_y)
{
/* Find source/dst miptrees */
- struct intel_mipmap_tree *src_mt = find_miptree(buffer_bit, src_rb);
- struct intel_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_rb);
+ struct intel_mipmap_tree *src_mt = find_miptree(buffer_bit, src_irb);
+ struct intel_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_irb);
/* Get ready to blit. This includes depth resolving the src and dst
* buffers if necessary.
*/
- intel_renderbuffer_resolve_depth(intel, intel_renderbuffer(src_rb));
- intel_renderbuffer_resolve_depth(intel, intel_renderbuffer(dst_rb));
+ intel_renderbuffer_resolve_depth(intel, src_irb);
+ intel_renderbuffer_resolve_depth(intel, dst_irb);
/* Do the blit */
brw_blorp_blit_miptrees(intel, src_mt, dst_mt,
srcX0, srcY0, dstX0, dstY0, dstX1, dstY1,
mirror_x, mirror_y);
- intel_renderbuffer_set_needs_hiz_resolve(intel_renderbuffer(dst_rb));
- intel_renderbuffer_set_needs_downsample(intel_renderbuffer(dst_rb));
+ intel_renderbuffer_set_needs_hiz_resolve(dst_irb);
+ intel_renderbuffer_set_needs_downsample(dst_irb);
}
static bool
-formats_match(GLbitfield buffer_bit, struct gl_renderbuffer *src_rb,
- struct gl_renderbuffer *dst_rb)
+formats_match(GLbitfield buffer_bit, struct intel_renderbuffer *src_irb,
+ struct intel_renderbuffer *dst_irb)
{
/* Note: don't just check gl_renderbuffer::Format, because in some cases
* multiple gl_formats resolve to the same native type in the miptree (for
* example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit
* between those formats.
*/
- return find_miptree(buffer_bit, src_rb)-format ==
- find_miptree(buffer_bit, dst_rb)-format;
+ return find_miptree(buffer_bit, src_irb)-format ==
+ find_miptree(buffer_bit, dst_irb)-format;
}
@@ -243,36 +243,40 @@ try_blorp_blit(struct intel_context *intel,
}
/* Find buffers */
- struct gl_renderbuffer *src_rb;
- struct gl_renderbuffer *dst_rb;
+ struct intel_renderbuffer *src_irb;
+ struct intel_renderbuffer *dst_irb;
switch (buffer_bit) {
case GL_COLOR_BUFFER_BIT:
- src_rb = read_fb-_ColorReadBuffer;
+ src_irb = intel_renderbuffer(read_fb-_ColorReadBuffer);
for (unsigned i = 0; i ctx-DrawBuffer-_NumColorDrawBuffers; ++i) {
- dst_rb = ctx-DrawBuffer-_ColorDrawBuffers[i];
- if (dst_rb !formats_match(buffer_bit, src_rb, dst_rb))
+ dst_irb = intel_renderbuffer(ctx-DrawBuffer-_ColorDrawBuffers[i]);
+ if (dst_irb !formats_match(buffer_bit, src_irb, dst_irb))
return false;
}
for (unsigned i = 0; i ctx-DrawBuffer-_NumColorDrawBuffers; ++i) {
- dst_rb = ctx-DrawBuffer-_ColorDrawBuffers[i];
- do_blorp_blit(intel, buffer_bit, src_rb, dst_rb, srcX0, srcY0,
+ dst_irb = intel_renderbuffer(ctx-DrawBuffer-_ColorDrawBuffers[i]);
+ do_blorp_blit(intel, buffer_bit, src_irb, dst_irb, srcX0, srcY0,
dstX0, dstY0, dstX1, dstY1, mirror_x, mirror_y
Mesa (9.0): i965/blorp: store surface width/height in brw_blorp_mip_info.
Module: Mesa
Branch: 9.0
Commit: 602e9a0f3727b036caf3a7b228fe90d36d832ea7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=602e9a0f3727b036caf3a7b228fe90d36d832ea7
Author: Paul Berry stereotype...@gmail.com
Date: Wed Aug 29 11:51:14 2012 -0700
i965/blorp: store surface width/height in brw_blorp_mip_info.
Previously, gen{6,7}_blorp_emit_surface_state would look up the width
and height of the surface at the time they set up the surface state,
and then tweak it if necessary (it's necessary when a W-tiled surface
is being mapped as Y-tiled). With this patch, we look up the width
and height when setting up the blit, and store them in
brw_blorp_mip_info. This allows us to do the necessary tweak in the
brw_blorp_blit_params constructor (where it makes more sense). It
also reduces the need to keep track of level and layer in
brw_blorp_mip_info, so that a future patch can eliminate them
entirely.
For consistency, this patch makes a similar change to the handling of
depth buffers when doing HiZ operations.
Reviewed-by: Eric Anholt e...@anholt.net
(cherry picked from commit 09b0fa8499d8035fa31ccb2b550056305fbd149b)
---
src/mesa/drivers/dri/i965/brw_blorp.cpp |9 ++-
src/mesa/drivers/dri/i965/brw_blorp.h| 18 +++-
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 28 +++--
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 15 +++--
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 15 +++--
5 files changed, 48 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 9017e4d..7322a04 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -31,7 +31,9 @@
brw_blorp_mip_info::brw_blorp_mip_info()
: mt(NULL),
level(0),
- layer(0)
+ layer(0),
+ width(0),
+ height(0)
{
}
@@ -50,6 +52,8 @@ brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
this-mt = mt;
this-level = level;
this-layer = layer;
+ this-width = mt-level[level].width;
+ this-height = mt-level[level].height;
}
void
@@ -164,7 +168,8 @@ brw_hiz_op_params::brw_hiz_op_params(struct
intel_mipmap_tree *mt,
this-hiz_op = op;
depth.set(mt, level, layer);
- depth.get_miplevel_dims(x1, y1);
+ x1 = depth.width;
+ y1 = depth.height;
assert(mt-hiz_mt != NULL);
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 8d05543..a19d283 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -65,15 +65,21 @@ public:
unsigned int level, unsigned int layer);
void get_draw_offsets(uint32_t *draw_x, uint32_t *draw_y) const;
- void get_miplevel_dims(uint32_t *width, uint32_t *height) const
- {
- *width = mt-level[level].width;
- *height = mt-level[level].height;
- }
-
struct intel_mipmap_tree *mt;
unsigned int level;
unsigned int layer;
+
+ /**
+* Width of the miplevel to be used. For surfaces using
+* INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
+*/
+ uint32_t width;
+
+ /**
+* Height of the miplevel to be used. For surfaces using
+* INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
+*/
+ uint32_t height;
};
class brw_blorp_surface_info : public brw_blorp_mip_info
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 0b2dbe3..d92f674 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1770,18 +1770,20 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
}
if (dst.map_stencil_as_y_tiled) {
- /* We must modify the rectangle we send through the rendering pipeline,
- * to account for the fact that we are mapping it as Y-tiled when it is
- * in fact W-tiled. Y tiles have dimensions 128x32 whereas W tiles have
- * dimensions 64x64. We must also align it to a multiple of the tile
- * size, because the differences between W and Y tiling formats will
- * mean that pixels are scrambled within the tile.
+ /* We must modify the rectangle we send through the rendering pipeline
+ * (and the size of the destination surface), to account for the fact
+ * that we are mapping it as Y-tiled when it is in fact W-tiled. Y
+ * tiles have dimensions 128x32 whereas W tiles have dimensions 64x64.
+ * We must also align it to a multiple of the tile size, because the
+ * differences between W and Y tiling formats will mean that pixels are
+ * scrambled within the tile.
*
* Note: if the destination surface configured to use IMS layout, then
* the effective tile size we need to align it to is smaller, because
* each pixel covers a 2x2 or a 4x2 block of samples
Mesa (9.0): i965/blorp: store x and y offsets in brw_blorp_mip_info.
Module: Mesa
Branch: 9.0
Commit: 127dc6d136db64fcf9448d66cb4c86db3bb11226
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=127dc6d136db64fcf9448d66cb4c86db3bb11226
Author: Paul Berry stereotype...@gmail.com
Date: Wed Aug 29 12:16:06 2012 -0700
i965/blorp: store x and y offsets in brw_blorp_mip_info.
Currently, gen{6,7}_blorp_emit_surface_state assumes that the src and
dst surfaces are mapped to miplevel 0 and layer 0 (thus no surface
offset is required). This is a bug, since the user might try to blit
to and from levels/layers other than 0.
To fix this bug, it will not be sufficient to have
gen6_{6,7}_blorp_emit_surface_state look up the surface offset at the
time they set up the surface state, since these offsets will need to
be tweaked when blitting stencil buffers (due to the fact that stencil
buffer blits have to swizzle between W and Y tiling formats).
So, to pave the way for the bug fix, this patch causes the x and y
offsets to be computed during blit setup and stored in
brw_blorp_mip_info.
As a result of this change, brw_blorp_mip_info doesn't need to store
the level and layer anymore.
For consistency, this patch makes a similar change to the handling of
depth buffers when doing HiZ operations.
Reviewed-by: Eric Anholt e...@anholt.net
(cherry picked from commit c130ce7b2b26b4b67d4bf2b6dd1044a200efe25d)
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 30 --
src/mesa/drivers/dri/i965/brw_blorp.h| 17 ++---
src/mesa/drivers/dri/i965/gen6_blorp.cpp |4 ++--
src/mesa/drivers/dri/i965/gen7_blorp.cpp |8 +++-
4 files changed, 31 insertions(+), 28 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 7322a04..6acc591 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -30,10 +30,10 @@
brw_blorp_mip_info::brw_blorp_mip_info()
: mt(NULL),
- level(0),
- layer(0),
width(0),
- height(0)
+ height(0),
+ x_offset(0),
+ y_offset(0)
{
}
@@ -50,10 +50,17 @@ brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
intel_miptree_check_level_layer(mt, level, layer);
this-mt = mt;
- this-level = level;
- this-layer = layer;
this-width = mt-level[level].width;
this-height = mt-level[level].height;
+
+ /* Construct a dummy renderbuffer just to extract tile offsets. */
+ struct intel_renderbuffer rb;
+ rb.mt = mt;
+ rb.mt_level = level;
+ rb.mt_layer = layer;
+ intel_renderbuffer_set_draw_offset(rb);
+ x_offset = rb.draw_x;
+ y_offset = rb.draw_y;
}
void
@@ -107,19 +114,6 @@ brw_blorp_surface_info::set(struct brw_context *brw,
}
}
-void
-brw_blorp_mip_info::get_draw_offsets(uint32_t *draw_x, uint32_t *draw_y) const
-{
- /* Construct a dummy renderbuffer just to extract tile offsets. */
- struct intel_renderbuffer rb;
- rb.mt = mt;
- rb.mt_level = level;
- rb.mt_layer = layer;
- intel_renderbuffer_set_draw_offset(rb);
- *draw_x = rb.draw_x;
- *draw_y = rb.draw_y;
-}
-
brw_blorp_params::brw_blorp_params()
: x0(0),
y0(0),
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index a19d283..d6239b4 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -63,11 +63,8 @@ public:
void set(struct intel_mipmap_tree *mt,
unsigned int level, unsigned int layer);
- void get_draw_offsets(uint32_t *draw_x, uint32_t *draw_y) const;
struct intel_mipmap_tree *mt;
- unsigned int level;
- unsigned int layer;
/**
* Width of the miplevel to be used. For surfaces using
@@ -80,6 +77,20 @@ public:
* INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
*/
uint32_t height;
+
+ /**
+* X offset within the surface to texture from (or render to). For
+* surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
+* pixels.
+*/
+ uint32_t x_offset;
+
+ /**
+* Y offset within the surface to texture from (or render to). For
+* surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
+* pixels.
+*/
+ uint32_t y_offset;
};
class brw_blorp_surface_info : public brw_blorp_mip_info
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 14e8563..d5d65c6 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -823,11 +823,11 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context
*brw,
const brw_blorp_params *params)
{
struct intel_context *intel = brw-intel;
- uint32_t draw_x, draw_y;
+ uint32_t draw_x = params-depth.x_offset;
+ uint32_t draw_y = params-depth.y_offset;
uint32_t tile_mask_x, tile_mask_y;
gen6_blorp_compute_tile_masks(params, tile_mask_x, tile_mask_y);
- params
Mesa (9.0): i965/blorp: Thread level and layer through brw_blorp_blit_miptrees().
Module: Mesa
Branch: 9.0
Commit: e87174cf4b499c8e9558438e70b0da5f0f38f54a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e87174cf4b499c8e9558438e70b0da5f0f38f54a
Author: Paul Berry stereotype...@gmail.com
Date: Thu Aug 16 10:06:08 2012 -0700
i965/blorp: Thread level and layer through brw_blorp_blit_miptrees().
Previously, when performing a blit using the blorp engine, we failed
to account for the level and layer of the source and destination. As
a result, all blits would occur between miplevel 0 and layer 0 of the
corresponding textures, regardless of which level/layer was bound to
the framebuffer.
This patch passes the correct level and layer through
brw_blorp_miptrees() into the brw_blorp_blit_params data structure.
Further patches in the series will adapt
gen{6,7}_blorp_emit_surface_state to make use of these parameters.
Reviewed-by: Eric Anholt e...@anholt.net
(cherry picked from commit 3123f0621561549c4566248100661ef77cab2834)
---
src/mesa/drivers/dri/i965/brw_blorp.h |4
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 15 +++
src/mesa/drivers/dri/intel/intel_mipmap_tree.c |6 --
3 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index d6239b4..f9e03d3 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -37,7 +37,9 @@ extern C {
void
brw_blorp_blit_miptrees(struct intel_context *intel,
struct intel_mipmap_tree *src_mt,
+unsigned src_level, unsigned src_layer,
struct intel_mipmap_tree *dst_mt,
+unsigned dst_level, unsigned dst_layer,
int src_x0, int src_y0,
int dst_x0, int dst_y0,
int dst_x1, int dst_y1,
@@ -295,7 +297,9 @@ class brw_blorp_blit_params : public brw_blorp_params
public:
brw_blorp_blit_params(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
+ unsigned src_level, unsigned src_layer,
struct intel_mipmap_tree *dst_mt,
+ unsigned dst_level, unsigned dst_layer,
GLuint src_x0, GLuint src_y0,
GLuint dst_x0, GLuint dst_y0,
GLuint width, GLuint height,
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index d92f674..ede78cc 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -123,14 +123,17 @@ find_miptree(GLbitfield buffer_bit, struct
intel_renderbuffer *irb)
void
brw_blorp_blit_miptrees(struct intel_context *intel,
struct intel_mipmap_tree *src_mt,
+unsigned src_level, unsigned src_layer,
struct intel_mipmap_tree *dst_mt,
+unsigned dst_level, unsigned dst_layer,
int src_x0, int src_y0,
int dst_x0, int dst_y0,
int dst_x1, int dst_y1,
bool mirror_x, bool mirror_y)
{
brw_blorp_blit_params params(brw_context(intel-ctx),
-src_mt, dst_mt,
+src_mt, src_level, src_layer,
+dst_mt, dst_level, dst_layer,
src_x0, src_y0,
dst_x0, dst_y0,
dst_x1, dst_y1,
@@ -157,7 +160,9 @@ do_blorp_blit(struct intel_context *intel, GLbitfield
buffer_bit,
intel_renderbuffer_resolve_depth(intel, dst_irb);
/* Do the blit */
- brw_blorp_blit_miptrees(intel, src_mt, dst_mt,
+ brw_blorp_blit_miptrees(intel,
+ src_mt, src_irb-mt_level, src_irb-mt_layer,
+ dst_mt, dst_irb-mt_level, dst_irb-mt_layer,
srcX0, srcY0, dstX0, dstY0, dstX1, dstY1,
mirror_x, mirror_y);
@@ -1622,14 +1627,16 @@ compute_msaa_layout_for_pipeline(struct brw_context
*brw, unsigned num_samples,
brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
+ unsigned src_level, unsigned
src_layer,
struct intel_mipmap_tree *dst_mt,
+ unsigned dst_level, unsigned
dst_layer,
GLuint src_x0, GLuint src_y0,
GLuint dst_x0, GLuint dst_y0,
GLuint dst_x1, GLuint dst_y1,
bool
Mesa (9.0): i965/blorp: Account for offsets when emitting SURFACE_STATE.
Module: Mesa
Branch: 9.0
Commit: 239e9bef92bd4602bc30e05177fa85a6e5b69fe0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=239e9bef92bd4602bc30e05177fa85a6e5b69fe0
Author: Paul Berry stereotype...@gmail.com
Date: Wed Aug 29 16:04:15 2012 -0700
i965/blorp: Account for offsets when emitting SURFACE_STATE.
Fixes piglit tests framebuffer-blit-levels {read,draw} depth.
Reviewed-by: Eric Anholt e...@anholt.net
(cherry picked from commit f04f219906e40a6647a10fd9c1928509fe25fb84)
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 25 +
src/mesa/drivers/dri/i965/brw_blorp.h|2 ++
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 13 ++---
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 12 +++-
4 files changed, 48 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 6acc591..1c83aad 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -114,6 +114,31 @@ brw_blorp_surface_info::set(struct brw_context *brw,
}
}
+
+/**
+ * Split x_offset and y_offset into a base offset (in bytes) and a remaining
+ * x/y offset (in pixels). Note: we can't do this by calling
+ * intel_renderbuffer_tile_offsets(), because the offsets may have been
+ * adjusted to account for Y vs. W tiling differences. So we compute it
+ * directly from the adjusted offsets.
+ */
+uint32_t
+brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
+ uint32_t *tile_y) const
+{
+ struct intel_region *region = mt-region;
+ uint32_t mask_x, mask_y;
+
+ intel_region_get_tile_masks(region, mask_x, mask_y);
+
+ *tile_x = x_offset mask_x;
+ *tile_y = y_offset mask_y;
+
+ return intel_region_get_aligned_offset(region, x_offset ~mask_x,
+ y_offset ~mask_y);
+}
+
+
brw_blorp_params::brw_blorp_params()
: x0(0),
y0(0),
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index f9e03d3..017628e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -104,6 +104,8 @@ void set(struct brw_context *brw,
struct intel_mipmap_tree *mt,
unsigned int level, unsigned int layer);
+ uint32_t compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const;
+
/* Setting this flag indicates that the buffer's contents are W-tiled
* stencil data, but the surface state should be set up for Y tiled
* MESA_FORMAT_R8 data (this is necessary because surface states don't
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index d5d65c6..baf3fa4 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -424,6 +424,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
height /= 2;
}
struct intel_region *region = surface-mt-region;
+ uint32_t tile_x, tile_y;
uint32_t *surf = (uint32_t *)
brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
@@ -435,7 +436,8 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
surface-brw_surfaceformat BRW_SURFACE_FORMAT_SHIFT);
/* reloc */
- surf[1] = region-bo-offset; /* No tile offsets needed */
+ surf[1] = (surface-compute_tile_offsets(tile_x, tile_y) +
+ region-bo-offset);
surf[2] = (0 BRW_SURFACE_LOD_SHIFT |
(width - 1) BRW_SURFACE_WIDTH_SHIFT |
@@ -453,8 +455,13 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
surf[4] = brw_get_surface_num_multisamples(surface-num_samples);
- surf[5] = (0 BRW_SURFACE_X_OFFSET_SHIFT |
- 0 BRW_SURFACE_Y_OFFSET_SHIFT |
+ /* Note that the low bits of these fields are missing, so
+* there's the possibility of getting in trouble.
+*/
+ assert(tile_x % 4 == 0);
+ assert(tile_y % 2 == 0);
+ surf[5] = ((tile_x / 4) BRW_SURFACE_X_OFFSET_SHIFT |
+ (tile_y / 2) BRW_SURFACE_Y_OFFSET_SHIFT |
(surface-mt-align_h == 4 ?
BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 3520ff6..00f13a5 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -150,6 +150,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
* gen6_blorp_emit_surface_state).
*/
struct intel_region *region = surface-mt-region;
+ uint32_t tile_x, tile_y;
struct gen7_surface_state *surf = (struct gen7_surface_state *)
brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, sizeof(*surf), 32,
@@ -167,7 +168,16 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
GEN7_SURFACE_ARYSPC_LOD0 : GEN7_SURFACE_ARYSPC_FULL;
/* reloc */
- surf-ss1.base_addr = region-bo-offset; /* No tile
Mesa (9.0): intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks.
Module: Mesa
Branch: 9.0
Commit: 96fd94ba9421c7c3072988f999ee869534f2bc2a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=96fd94ba9421c7c3072988f999ee869534f2bc2a
Author: Paul Berry stereotype...@gmail.com
Date: Thu Aug 30 10:57:03 2012 -0700
intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks.
When the blorp engine is performing a blit from one stencil buffer to
another, it sets up the surface state for these buffers as Y-tiled, so
it needs to be able to force intel_region_get_tile_masks() to return
the appropriate masks for a Y-tiled region.
Acked-by: Eric Anholt e...@anholt.net
(cherry picked from commit 50dec7fc2d5ba813aaa822596d124098a22db301)
---
src/mesa/drivers/dri/i965/brw_blorp.cpp |3 ++-
src/mesa/drivers/dri/i965/brw_misc_state.c |6 +++---
src/mesa/drivers/dri/i965/gen6_blorp.cpp|4 ++--
src/mesa/drivers/dri/i965/gen7_misc_state.c |5 +++--
src/mesa/drivers/dri/intel/intel_fbo.c |2 +-
src/mesa/drivers/dri/intel/intel_regions.c |9 +++--
src/mesa/drivers/dri/intel/intel_regions.h |3 ++-
src/mesa/drivers/dri/intel/intel_screen.c |2 +-
8 files changed, 21 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 1c83aad..e81194e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -129,7 +129,8 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t
*tile_x,
struct intel_region *region = mt-region;
uint32_t mask_x, mask_y;
- intel_region_get_tile_masks(region, mask_x, mask_y);
+ intel_region_get_tile_masks(region, mask_x, mask_y,
+ map_stencil_as_y_tiled);
*tile_x = x_offset mask_x;
*tile_y = y_offset mask_y;
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 3f186f5..52926fb 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -288,7 +288,7 @@ static void emit_depthbuffer(struct brw_context *brw)
if (depth_irb) {
intel_region_get_tile_masks(depth_irb-mt-region,
- tile_mask_x, tile_mask_y);
+ tile_mask_x, tile_mask_y, false);
}
if (depth_irb
@@ -298,7 +298,7 @@ static void emit_depthbuffer(struct brw_context *brw)
uint32_t hiz_tile_mask_x, hiz_tile_mask_y;
intel_region_get_tile_masks(hiz_region,
- hiz_tile_mask_x, hiz_tile_mask_y);
+ hiz_tile_mask_x, hiz_tile_mask_y, false);
/* Each HiZ row represents 2 rows of pixels */
hiz_tile_mask_y = hiz_tile_mask_y 1 | 1;
@@ -331,7 +331,7 @@ static void emit_depthbuffer(struct brw_context *brw)
uint32_t stencil_tile_mask_x, stencil_tile_mask_y;
intel_region_get_tile_masks(stencil_mt-region,
stencil_tile_mask_x,
- stencil_tile_mask_y);
+ stencil_tile_mask_y, false);
tile_mask_x |= stencil_tile_mask_x;
tile_mask_y |= stencil_tile_mask_y;
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index baf3fa4..3e0b80e 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -58,9 +58,9 @@ gen6_blorp_compute_tile_masks(const brw_blorp_params *params,
{
uint32_t depth_mask_x, depth_mask_y, hiz_mask_x, hiz_mask_y;
intel_region_get_tile_masks(params-depth.mt-region,
- depth_mask_x, depth_mask_y);
+ depth_mask_x, depth_mask_y, false);
intel_region_get_tile_masks(params-depth.mt-hiz_mt-region,
- hiz_mask_x, hiz_mask_y);
+ hiz_mask_x, hiz_mask_y, false);
/* Each HiZ row represents 2 rows of pixels */
hiz_mask_y = hiz_mask_y 1 | 1;
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index a0d2460..9709b8e 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -69,12 +69,13 @@ static void emit_depthbuffer(struct brw_context *brw)
hiz_mt = depth_mt-hiz_mt;
intel_region_get_tile_masks(depth_mt-region,
- tile_mask_x, tile_mask_y);
+ tile_mask_x, tile_mask_y, false);
if (hiz_mt) {
uint32_t hiz_tile_mask_x, hiz_tile_mask_y;
intel_region_get_tile_masks(hiz_mt-region,
- hiz_tile_mask_x, hiz_tile_mask_y);
+ hiz_tile_mask_x, hiz_tile_mask_y,
+ false);
/* Each HiZ row represents 2 rows of pixels
Mesa (9.0): intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset.
Module: Mesa Branch: 9.0 Commit: 68da5dfc2c2e9c0aca47431076be0cd43406d4aa URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=68da5dfc2c2e9c0aca47431076be0cd43406d4aa Author: Paul Berry stereotype...@gmail.com Date: Thu Aug 30 11:16:44 2012 -0700 intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset. This patch modifies intel_region_get_aligned_offset() to make the appropriate calculation when the blorp engine sets up a W-tiled stencil buffer using a Y-tiled SURFACE_STATE. Acked-by: Eric Anholt e...@anholt.net (cherry picked from commit b760c9913dcff848a2aa0e60abeb48e596ae8fee) --- src/mesa/drivers/dri/i965/brw_blorp.cpp |3 ++- src/mesa/drivers/dri/i965/brw_misc_state.c |5 +++-- src/mesa/drivers/dri/i965/gen6_blorp.cpp|4 ++-- src/mesa/drivers/dri/i965/gen7_blorp.cpp|4 ++-- src/mesa/drivers/dri/i965/gen7_misc_state.c |6 -- src/mesa/drivers/dri/intel/intel_fbo.c |2 +- src/mesa/drivers/dri/intel/intel_regions.c | 18 -- src/mesa/drivers/dri/intel/intel_regions.h |2 +- 8 files changed, 31 insertions(+), 13 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index e81194e..b08ce07 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -136,7 +136,8 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x, *tile_y = y_offset mask_y; return intel_region_get_aligned_offset(region, x_offset ~mask_x, - y_offset ~mask_y); + y_offset ~mask_y, + map_stencil_as_y_tiled); } diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 52926fb..6dfa08e 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -474,7 +474,7 @@ static void emit_depthbuffer(struct brw_context *brw) offset = intel_region_get_aligned_offset(region, draw_x ~tile_mask_x, - draw_y ~tile_mask_y); + draw_y ~tile_mask_y, false); BEGIN_BATCH(len); OUT_BATCH(_3DSTATE_DEPTH_BUFFER 16 | (len - 2)); @@ -518,7 +518,8 @@ static void emit_depthbuffer(struct brw_context *brw) uint32_t hiz_offset = intel_region_get_aligned_offset(hiz_region, draw_x ~tile_mask_x, -(draw_y ~tile_mask_y) / 2); +(draw_y ~tile_mask_y) / 2, +false); BEGIN_BATCH(3); OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER 16) | (3 - 2)); diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index 3e0b80e..1f536bf 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -843,7 +843,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw, uint32_t offset = intel_region_get_aligned_offset(params-depth.mt-region, draw_x ~tile_mask_x, - draw_y ~tile_mask_y); + draw_y ~tile_mask_y, false); /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for Depth @@ -896,7 +896,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw, uint32_t hiz_offset = intel_region_get_aligned_offset(hiz_region, draw_x ~tile_mask_x, - (draw_y ~tile_mask_y) / 2); + (draw_y ~tile_mask_y) / 2, false); BEGIN_BATCH(3); OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER 16) | (3 - 2)); diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 00f13a5..abe 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -591,7 +591,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw, uint32_t offset = intel_region_get_aligned_offset(params-depth.mt-region, draw_x ~tile_mask_x, - draw_y ~tile_mask_y); + draw_y ~tile_mask_y, false); /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for Depth @@ -640,7 +640,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw, uint32_t hiz_offset
Mesa (9.0): i965/blorp: don' t reduce stencil alignment restrictions when multisampling.
Module: Mesa
Branch: 9.0
Commit: 62bc4af0e18f76dd30a4d5ae6d45a365a1fa226f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=62bc4af0e18f76dd30a4d5ae6d45a365a1fa226f
Author: Paul Berry stereotype...@gmail.com
Date: Wed Aug 29 15:11:49 2012 -0700
i965/blorp: don't reduce stencil alignment restrictions when multisampling.
When blitting to a stencil buffer, we need to align the rectangle we
send down the rendering pipeline, to account for the fact that the
stencil buffer uses a W-tiled layout, but we are configuring its
surface state as Y-tiled.
Previously, when the stencil buffer was multisampled, we assumed that
we could reduce the amount of alignment that was necessary, since each
pixel occupies a block of 2x2 or 4x2 samples in the stencil buffer.
That would have been correct if the coordinates we were adjusting were
measured in pixels. However, the conversion from pixel coordinates to
coordinates within the interleaved buffer has already been done;
therefore the full alignment restriction applies.
Note: the reason this mistake wasn't previously uncovered by piglit
tests is because it is being masked by another mistake: the blorp
engine is using overly conservative alignment restrictions when doing
stencil blits. The overly conservative alignment restrictions will be
removed in the patch that follows. Doing this fix now will prevent
the subsequent patch from introducing regressions.
Acked-by: Eric Anholt e...@anholt.net
(cherry picked from commit 1a75063d5f829547b75b60ae64bddf3905b4cb8f)
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 10 +-
1 files changed, 1 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index ede78cc..67274dc 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1785,18 +1785,10 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
* differences between W and Y tiling formats will mean that pixels are
* scrambled within the tile.
*
- * Note: if the destination surface configured to use IMS layout, then
- * the effective tile size we need to align it to is smaller, because
- * each pixel covers a 2x2 or a 4x2 block of samples.
- *
* TODO: what if this makes the coordinates (or the texture size) too
* large?
*/
- unsigned x_align = 64, y_align = 64;
- if (dst_mt-msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
- x_align /= (dst_mt-num_samples == 4 ? 2 : 4);
- y_align /= 2;
- }
+ const unsigned x_align = 64, y_align = 64;
x0 = ROUND_DOWN_TO(x0, x_align) * 2;
y0 = ROUND_DOWN_TO(y0, y_align) / 2;
x1 = ALIGN(x1, x_align) * 2;
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Mesa (9.0): i965/blorp: Reduce alignment restrictions for stencil blits.
Module: Mesa
Branch: 9.0
Commit: 21e9850d5369f9757b5005df4c8af38668a3053b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=21e9850d5369f9757b5005df4c8af38668a3053b
Author: Paul Berry stereotype...@gmail.com
Date: Wed Aug 29 14:26:48 2012 -0700
i965/blorp: Reduce alignment restrictions for stencil blits.
Previously, we aligned all stencil blit operations to multiples of the
size of a tile, since stencil buffers use W-tiling, and blorp has to
approximate this by configuring the 3D pipeline for Y-tiling and
swizzling coordinates.
However, this was unnecessarily conservative; it turns out that the
differences between W-tiling and Y-tiling are confined to 32-byte
sub-tiles within the 4k tiling pattern; the layout of these 32-byte
sub-tiles within the larger 4k tile is the same (8 sub-tiles across by
16 sub-tiles down, in column-major order). Therefore we only need to
align stencil blit operations to multiples of the sub-tile size.
Note: although the performance improvement of this change is probably
quite small, the fact that W-tiling and Y-tiling formats only differ
within 32-byte sub-tiles will be essential in a future patch to ensure
that stencil blits work correctly between parts of the miptree other
than level/layer 0. Making this change provides handy documentation
(and validation) of this fact.
Acked-by: Eric Anholt e...@anholt.net
(cherry picked from commit 5fd67fac14d7f35c311eb5c671be8d4ae9b2ea37)
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 23 +--
1 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 67274dc..6bf37b8 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1779,16 +1779,27 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
if (dst.map_stencil_as_y_tiled) {
/* We must modify the rectangle we send through the rendering pipeline
* (and the size of the destination surface), to account for the fact
- * that we are mapping it as Y-tiled when it is in fact W-tiled. Y
- * tiles have dimensions 128x32 whereas W tiles have dimensions 64x64.
- * We must also align it to a multiple of the tile size, because the
- * differences between W and Y tiling formats will mean that pixels are
- * scrambled within the tile.
+ * that we are mapping it as Y-tiled when it is in fact W-tiled.
+ *
+ * Both Y tiling and W tiling can be understood as organizations of
+ * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
+ * is different, but the layout of the 32-byte sub-tiles within the 4k
+ * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
+ * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
+ * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
+ *
+ * Therefore, to account for the layout differences within the 32-byte
+ * sub-tiles, we must expand the rectangle so the X coordinates of its
+ * edges are multiples of 8 (the W sub-tile width), and its Y
+ * coordinates of its edges are multiples of 4 (the W sub-tile height).
+ * Then we need to scale the X and Y coordinates of the rectangle to
+ * account for the differences in aspect ratio between the Y and W
+ * sub-tiles.
*
* TODO: what if this makes the coordinates (or the texture size) too
* large?
*/
- const unsigned x_align = 64, y_align = 64;
+ const unsigned x_align = 8, y_align = 4;
x0 = ROUND_DOWN_TO(x0, x_align) * 2;
y0 = ROUND_DOWN_TO(y0, y_align) / 2;
x1 = ALIGN(x1, x_align) * 2;
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Mesa (9.0): i965/blorp: Fix offsets and width/height for stencil blits.
Module: Mesa
Branch: 9.0
Commit: 76c1c34c4aa2fa48126aee8d16e943bf0e3ff750
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=76c1c34c4aa2fa48126aee8d16e943bf0e3ff750
Author: Paul Berry stereotype...@gmail.com
Date: Thu Aug 30 08:01:54 2012 -0700
i965/blorp: Fix offsets and width/height for stencil blits.
Fixes piglit test framebuffer-blit-levels draw stencil.
Acked-by: Eric Anholt e...@anholt.net
(cherry picked from commit 1a5d4f7cb2367c7863b28efbd78e9169114baf42)
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 46 +-
1 files changed, 37 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 6bf37b8..656a497 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1778,8 +1778,9 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
if (dst.map_stencil_as_y_tiled) {
/* We must modify the rectangle we send through the rendering pipeline
- * (and the size of the destination surface), to account for the fact
- * that we are mapping it as Y-tiled when it is in fact W-tiled.
+ * (and the size and x/y offset of the destination surface), to account
+ * for the fact that we are mapping it as Y-tiled when it is in fact
+ * W-tiled.
*
* Both Y tiling and W tiling can be understood as organizations of
* 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
@@ -1794,7 +1795,25 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
* coordinates of its edges are multiples of 4 (the W sub-tile height).
* Then we need to scale the X and Y coordinates of the rectangle to
* account for the differences in aspect ratio between the Y and W
- * sub-tiles.
+ * sub-tiles. We need to modify the layer width and height similarly.
+ *
+ * Note: Since the x/y offset of the surface will be applied using the
+ * SURFACE_STATE command packet, it will be invisible to the swizzling
+ * code in the shader; therefore it needs to be in a multiple of the
+ * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
+ * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
+ * buffer), and the miplevel alignment used for stencil buffers is 8
+ * pixels horizontally and either 4 or 8 pixels vertically (see
+ * intel_horizontal_texture_alignment_unit() and
+ * intel_vertical_texture_alignment_unit()).
+ *
+ * Note: Also, since the SURFACE_STATE command packet can only apply
+ * offsets that are multiples of 4 pixels horizontally and 2 pixels
+ * vertically, it is important that the offsets will be multiples of
+ * these sizes after they are converted into Y-tiled coordinates.
+ * Fortunately they will be, since we know from above that the offsets
+ * are a multiple of the 32-byte sub-tile size, and in Y-tiled
+ * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
*
* TODO: what if this makes the coordinates (or the texture size) too
* large?
@@ -1804,19 +1823,28 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
y0 = ROUND_DOWN_TO(y0, y_align) / 2;
x1 = ALIGN(x1, x_align) * 2;
y1 = ALIGN(y1, y_align) / 2;
- dst.width *= 2;
- dst.height /= 2;
+ dst.width = ALIGN(dst.width, x_align) * 2;
+ dst.height = ALIGN(dst.height, y_align) / 2;
+ dst.x_offset *= 2;
+ dst.y_offset /= 2;
wm_prog_key.use_kill = true;
}
if (src.map_stencil_as_y_tiled) {
- /* We must modify the size of the source surface to account for the fact
- * that we are mapping it as Y-tiled when it is in fact W tiled.
+ /* We must modify the size and x/y offset of the source surface to
+ * account for the fact that we are mapping it as Y-tiled when it is in
+ * fact W tiled.
+ *
+ * See the comments above concerning x/y offset alignment for the
+ * destination surface.
*
* TODO: what if this makes the texture size too large?
*/
- src.width *= 2;
- src.height /= 2;
+ const unsigned x_align = 8, y_align = 4;
+ src.width = ALIGN(src.width, x_align) * 2;
+ src.height = ALIGN(src.height, y_align) / 2;
+ src.x_offset *= 2;
+ src.y_offset /= 2;
}
}
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Mesa (9.0): i965/blorp: Increase Y alignment for multisampled stencil blits .
Module: Mesa
Branch: 9.0
Commit: 36bc0fe4f2e90ea9efa19940f477472dad6fb18f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=36bc0fe4f2e90ea9efa19940f477472dad6fb18f
Author: Paul Berry stereotype...@gmail.com
Date: Wed Sep 12 11:13:49 2012 -0700
i965/blorp: Increase Y alignment for multisampled stencil blits.
This patch is a band-aid fix for a bug in commit 5fd67fa (i965/blorp:
Reduce alignment restrictions for stencil blits), which causes
multisampled stencil blits to work incorrectly on Sandy Bridge.
When blitting to or from a normal stencil buffer, we have to use a
coordinate transformation that swizzles coordinates to account for the
fact that stencil buffers use W tiling, but the most similar tiling
format available for textures and render targets is Y tiling. The
differences between W and Y tiling cause pixels to be scrambled within
a block of size 8x4 (width x height) as measured relative to a W tile,
or 16x2 as measured relative to a Y tile. So in order to make sure
that pixels at the edges of the blit aren't lost, we need to align the
rendering rectangle (and the buffer sizes) to multiples of the 8x4
block size. This alignment happens in the brw_blorp_blit_params
constructor, whereas the determination of how to swizzle the
coordinates happens during code generation, in the
brw_blorp_blit_program class.
When blitting to or from a multisampled stencil buffer, the coordinate
swizzling is more complex, because it has to account for the
interleaving pattern of samples, which uses 4x4 blocks for 4x MSAA and
8x4 blocks for 8x MSAA. The end result is that if multisampling is in
use, the 16x2 block size (relative so a Y tile) needs to be expanded
to 16x4, and the corresponding size relative to a W tile expands to
8x8.
The problem doesn't affect Ivy Bridge severely enough to crop up in
Piglit tests because on Ivy Bridge we have to disable multisampling
when blitting *to* a multisampled stencil buffer (the blorp compiler
generates code to compensate for the fact that multisampling is
disabled). However I suspect a bug is still present because we don't
disable multisampling when blitting *from* a multisampled stencil
buffer.
This patch fixes the problem by doubling the vertical alignment
requirement when blitting to or from a multisampled stencil buffer,
and multisampling has not been disabled.
In the long run I would like to rework the brw_blorp_blit_params
constructor--it's difficult to follow and has had several subtle bugs
like this one. However this band-aid fix should be suitable for
cherry-picking to release branches.
Fixes Piglit tests unaligned-blit {2,4} stencil {msaa,upsample} on
Sandy Bridge.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
(cherry picked from commit a33ce665a5827c598b85bb04d94b33e6a5e41c28)
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 656a497..2207230 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1797,6 +1797,11 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
* account for the differences in aspect ratio between the Y and W
* sub-tiles. We need to modify the layer width and height similarly.
*
+ * A correction needs to be applied when MSAA is in use: since
+ * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
+ * we need to align the Y coordinates to multiples of 8, so that when
+ * they are divided by two they are still multiples of 4.
+ *
* Note: Since the x/y offset of the surface will be applied using the
* SURFACE_STATE command packet, it will be invisible to the swizzling
* code in the shader; therefore it needs to be in a multiple of the
@@ -1818,7 +1823,7 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
* TODO: what if this makes the coordinates (or the texture size) too
* large?
*/
- const unsigned x_align = 8, y_align = 4;
+ const unsigned x_align = 8, y_align = dst.num_samples != 0 ? 8 : 4;
x0 = ROUND_DOWN_TO(x0, x_align) * 2;
y0 = ROUND_DOWN_TO(y0, y_align) / 2;
x1 = ALIGN(x1, x_align) * 2;
@@ -1840,7 +1845,7 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
*
* TODO: what if this makes the texture size too large?
*/
- const unsigned x_align = 8, y_align = 4;
+ const unsigned x_align = 8, y_align = src.num_samples != 0 ? 8 : 4;
src.width = ALIGN(src.width, x_align) * 2;
src.height = ALIGN(src.height, y_align) / 2;
src.x_offset *= 2;
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Mesa (9.0): i965: Don't spill smeared registers.
Module: Mesa
Branch: 9.0
Commit: 849a3d243d8a0d951202515c06d9b17daf59d2f2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=849a3d243d8a0d951202515c06d9b17daf59d2f2
Author: Paul Berry stereotype...@gmail.com
Date: Wed Sep 19 13:28:00 2012 -0700
i965: Don't spill smeared registers.
Fixes an assertion failure when compiling certain shaders that need both
pull constants and register spilling:
brw_eu_emit.c:204: validate_reg: Assertion `execsize = width' failed.
NOTE: This is a candidate for the 8.0 release branch.
Signed-off-by: Paul Berry stereotype...@gmail.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
(cherry picked from commit ab5ce2789fe9e5f2789ee22fdb02bcfed42a7125)
---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index e7f11ae..82a7ee9 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -317,11 +317,26 @@ fs_visitor::choose_spill_reg(struct ra_graph *g)
for (unsigned int i = 0; i 3; i++) {
if (inst-src[i].file == GRF) {
spill_costs[inst-src[i].reg] += loop_scale;
+
+/* Register spilling logic assumes full-width registers; smeared
+ * registers have a width of 1 so if we try to spill them we'll
+ * generate invalid assembly. This shouldn't be a problem because
+ * smeared registers are only used as short-term temporaries when
+ * loading pull constants, so spilling them is unlikely to reduce
+ * register pressure anyhow.
+ */
+if (inst-src[i].smear = 0) {
+ no_spill[inst-src[i].reg] = true;
+}
}
}
if (inst-dst.file == GRF) {
spill_costs[inst-dst.reg] += inst-regs_written() * loop_scale;
+
+ if (inst-dst.smear = 0) {
+no_spill[inst-dst.reg] = true;
+ }
}
switch (inst-opcode) {
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Mesa (9.0): i965/blorp: Add support for blits between SRGB and linear formats (fixed).
Module: Mesa Branch: 9.0 Commit: 8c1c18769ef4838b11065b353f6f62bfd1de1cd2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c1c18769ef4838b11065b353f6f62bfd1de1cd2 Author: Kenneth Graunke kenn...@whitecape.org Date: Tue Sep 11 16:20:43 2012 -0700 i965/blorp: Add support for blits between SRGB and linear formats (fixed). This is a squash of 2 commits from master. The first commit is: i965/blorp: Add support for blits between SRGB and linear formats. Fixes colorspace issues in L4D2 when multisampling is enabled (the scene was far too dark, but the flashlight area was way too bright). The nVidia and AMD binary drivers both allow this kind of blit. Reviewed-by: Paul Berry stereotype...@gmail.com Signed-off-by: Kenneth Graunke kenn...@whitecape.org (cherry picked from commit e2249e8c4d06a85d6389ba1689e15d7e29aa4dff) The second commit is: i965/blorp: Fix sRGB MSAA resolves. Commit e2249e8c4d06a85d6389ba1689e15d7e29aa4dff (i965/blorp: Add support for blits between SRGB and linear formats) changed blorp to always configure surface states for in linear format (even if the underlying surface is sRGB). This allowed sRGB-to-linear and linear-to-sRGB blits to occur without causing the image to be inappropriately brightened or darkened. However, it broke sRGB MSAA resolves, since they rely on the destination buffer format being sRGB in order to ensure that samples are averaged together in sRGB-correct fashion. This patch fixes the problem by instead configuring the source buffer to use the *same* format as the destination buffer. This ensures that the image won't be brightened or darkened, but preserves proper sRGB averaging. Fixes piglit tests EXT_framebuffer_multisample/accuracy srgb. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55265 Reviewed-by: Eric Anholt e...@anholt.net Reviewed-and-tested-by: Kenneth Graunke kenn...@whitecape.org (cherry picked from commit 124b214f094fa63ff1ddb7e9f0a1c2e0ba8214fb) --- src/mesa/drivers/dri/i965/brw_blorp.cpp |9 - src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 20 ++-- 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index b08ce07..b847980 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -102,11 +102,10 @@ brw_blorp_surface_info::set(struct brw_context *brw, this-brw_surfaceformat = BRW_SURFACEFORMAT_R8G8_UNORM; break; default: - /* Blorp blits don't support any sort of format conversion, so we can - * safely assume that the same format is being used for the source and - * destination. Therefore the format must be supported as a render - * target, even if this is the source image. So we can convert to a - * surface format using brw-render_target_format. + /* Blorp blits don't support any sort of format conversion (except + * between sRGB and linear), so we can safely assume that the format is + * supported as a render target, even if this is the source image. So + * we can convert to a surface format using brw-render_target_format. */ assert(brw-format_supported_as_render_target[mt-format]); this-brw_surfaceformat = brw-render_target_format[mt-format]; diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp index 2207230..e8604e7 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp @@ -180,8 +180,11 @@ formats_match(GLbitfield buffer_bit, struct intel_renderbuffer *src_irb, * example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit * between those formats. */ - return find_miptree(buffer_bit, src_irb)-format == - find_miptree(buffer_bit, dst_irb)-format; + gl_format src_format = find_miptree(buffer_bit, src_irb)-format; + gl_format dst_format = find_miptree(buffer_bit, dst_irb)-format; + + return _mesa_get_srgb_format_linear(src_format) == + _mesa_get_srgb_format_linear(dst_format); } @@ -1638,6 +1641,19 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw, src.set(brw, src_mt, src_level, src_layer); dst.set(brw, dst_mt, dst_level, dst_layer); + /* If we are blitting from sRGB to linear or vice versa, we still want the +* blit to be a direct copy, so we need source and destination to use the +* same format. However, we want the destination sRGB/linear state to be +* correct (so that sRGB blending is used when doing an MSAA resolve to an +* sRGB surface, and linear blending is used when doing an MSAA resolve to +* a linear surface). Since blorp blits don't support any format +* conversion (except between sRGB and linear), we can accomplish this by +* simply setting up the source to use the same format as the destination. +*/ + assert
Mesa (master): meta: Properly save/restore GL_FRAMEBUFFER_SRGB in Meta.
Module: Mesa
Branch: master
Commit: 414f69aaad442abfce506323d0f0640139928898
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=414f69aaad442abfce506323d0f0640139928898
Author: Paul Berry stereotype...@gmail.com
Date: Mon Sep 24 14:38:19 2012 -0700
meta: Properly save/restore GL_FRAMEBUFFER_SRGB in Meta.
Previously, meta logic was saving and restoring the value of
GL_FRAMEBUFFER_SRGB in an ad-hoc fashion. As a result, it was not
properly disabled and/or restored for some meta operations.
This patch causes GL_FRAMEBUFFER_SRGB to be saved/restored in the
conventional way of meta-ops (using _mesa_meta_begin() and
_mesa_meta_end()). It is now reliably saved/restored for
_mesa_meta_BlitFramebuffer, _mesa_meta_GenerateMipmap, and
decompress_texture_image, and preserved for all other meta ops.
Fixes piglit tests ARB_framebuffer_sRGB/blit renderbuffer
{linear_to_srgb,srgb} scaled {disabled,enabled}.
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/common/meta.c | 47 +---
src/mesa/drivers/common/meta.h |1 +
2 files changed, 21 insertions(+), 27 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 28a79b0..6689337 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -187,6 +187,9 @@ struct save_state
/** MESA_META_MULTISAMPLE */
GLboolean MultisampleEnabled;
+ /** MESA_META_FRAMEBUFFER_SRGB */
+ GLboolean sRGBEnabled;
+
/** Miscellaneous (always disabled) */
GLboolean Lighting;
GLboolean RasterDiscard;
@@ -773,6 +776,12 @@ _mesa_meta_begin(struct gl_context *ctx, GLbitfield state)
_mesa_set_multisample(ctx, GL_FALSE);
}
+ if (state MESA_META_FRAMEBUFFER_SRGB) {
+ save-sRGBEnabled = ctx-Color.sRGBEnabled;
+ if (ctx-Color.sRGBEnabled)
+ _mesa_set_framebuffer_srgb(ctx, GL_FALSE);
+ }
+
/* misc */
{
save-Lighting = ctx-Light.Enabled;
@@ -1075,6 +1084,11 @@ _mesa_meta_end(struct gl_context *ctx)
_mesa_set_multisample(ctx, save-MultisampleEnabled);
}
+ if (state MESA_META_FRAMEBUFFER_SRGB) {
+ if (ctx-Color.sRGBEnabled != save-sRGBEnabled)
+ _mesa_set_framebuffer_srgb(ctx, save-sRGBEnabled);
+ }
+
/* misc */
if (save-Lighting) {
_mesa_set_enable(ctx, GL_LIGHTING, GL_TRUE);
@@ -1394,7 +1408,6 @@ blitframebuffer_texture(struct gl_context *ctx,
const GLuint srcLevel = readAtt-TextureLevel;
const GLint baseLevelSave = texObj-BaseLevel;
const GLint maxLevelSave = texObj-MaxLevel;
- const GLenum fbo_srgb_save = ctx-Color.sRGBEnabled;
const GLenum target = texObj-Target;
GLuint sampler, samplerSave =
ctx-Texture.Unit[ctx-Texture.CurrentUnit].Sampler ?
@@ -1433,15 +1446,14 @@ blitframebuffer_texture(struct gl_context *ctx,
_mesa_SamplerParameteri(sampler, GL_TEXTURE_WRAP_S, GL_CLAMP_TO_EDGE);
_mesa_SamplerParameteri(sampler, GL_TEXTURE_WRAP_T, GL_CLAMP_TO_EDGE);
-/* Always do our blits with no sRGB decode or encode.*/
+/* Always do our blits with no sRGB decode or encode. Note that
+ * GL_FRAMEBUFFER_SRGB has already been disabled by
+ * _mesa_meta_begin().
+ */
if (ctx-Extensions.EXT_texture_sRGB_decode) {
_mesa_SamplerParameteri(sampler, GL_TEXTURE_SRGB_DECODE_EXT,
GL_SKIP_DECODE_EXT);
}
- if ((_mesa_is_desktop_gl(ctx) ctx-Extensions.EXT_framebuffer_sRGB)
- || _mesa_is_gles3(ctx)) {
-_mesa_set_enable(ctx, GL_FRAMEBUFFER_SRGB_EXT, GL_FALSE);
- }
_mesa_TexEnvi(GL_TEXTURE_ENV, GL_TEXTURE_ENV_MODE, GL_REPLACE);
_mesa_set_enable(ctx, target, GL_TRUE);
@@ -1500,9 +1512,6 @@ blitframebuffer_texture(struct gl_context *ctx,
_mesa_TexParameteri(target, GL_TEXTURE_BASE_LEVEL, baseLevelSave);
_mesa_TexParameteri(target, GL_TEXTURE_MAX_LEVEL, maxLevelSave);
}
-if (ctx-Extensions.EXT_framebuffer_sRGB fbo_srgb_save) {
- _mesa_set_enable(ctx, GL_FRAMEBUFFER_SRGB_EXT, GL_TRUE);
-}
_mesa_BindSampler(ctx-Texture.CurrentUnit, samplerSave);
_mesa_DeleteSamplers(1, sampler);
@@ -1713,7 +1722,8 @@ _mesa_meta_Clear(struct gl_context *ctx, GLbitfield
buffers)
GLbitfield metaSave = (MESA_META_ALL -
MESA_META_SCISSOR -
MESA_META_PIXEL_STORE -
- MESA_META_CONDITIONAL_RENDER);
+ MESA_META_CONDITIONAL_RENDER -
+ MESA_META_FRAMEBUFFER_SRGB);
const GLuint stencilMax = (1 ctx-DrawBuffer-Visual.stencilBits) - 1;
if (buffers BUFFER_BITS_COLOR) {
@@ -3236,7 +3246,6 @@ _mesa_meta_GenerateMipmap(struct
Mesa (master): enable: Create _mesa_set_framebuffer_srgb() function for use by meta ops.
Module: Mesa
Branch: master
Commit: 8faa79764c394ce5ec87c5376afb5643f99c53e7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8faa79764c394ce5ec87c5376afb5643f99c53e7
Author: Paul Berry stereotype...@gmail.com
Date: Mon Sep 24 14:24:28 2012 -0700
enable: Create _mesa_set_framebuffer_srgb() function for use by meta ops.
GLES3 supports sRGB formats, but it does not support the
GL_FRAMEBUFFER_SRGB enable/disable flag (instead it behaves as if this
flag is always enabled). Therefore, meta ops that need to disable
GL_FRAMEBUFFER_SRGB will need a backdoor mechanism to do so when the
API is GLES3.
We were already doing a similar thing for GL_MULTISAMPLE, which has
the same constraints.
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/main/enable.c | 22 +++---
src/mesa/main/enable.h |3 +++
2 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/src/mesa/main/enable.c b/src/mesa/main/enable.c
index 3643cfb..676cd9b 100644
--- a/src/mesa/main/enable.c
+++ b/src/mesa/main/enable.c
@@ -264,6 +264,23 @@ _mesa_set_multisample(struct gl_context *ctx, GLboolean
state)
}
/**
+ * Helper function to enable or disable GL_FRAMEBUFFER_SRGB, skipping the
+ * check for whether the API supports it (GLES doesn't).
+ */
+void
+_mesa_set_framebuffer_srgb(struct gl_context *ctx, GLboolean state)
+{
+ if (ctx-Color.sRGBEnabled == state)
+ return;
+ FLUSH_VERTICES(ctx, _NEW_BUFFERS);
+ ctx-Color.sRGBEnabled = state;
+
+ if (ctx-Driver.Enable) {
+ ctx-Driver.Enable(ctx, GL_FRAMEBUFFER_SRGB, state);
+ }
+}
+
+/**
* Helper function to enable or disable state.
*
* \param ctx GL context.
@@ -1047,9 +1064,8 @@ _mesa_set_enable(struct gl_context *ctx, GLenum cap,
GLboolean state)
if (!_mesa_is_desktop_gl(ctx) !_mesa_is_gles3(ctx))
goto invalid_enum_error;
CHECK_EXTENSION(EXT_framebuffer_sRGB, cap);
- FLUSH_VERTICES(ctx, _NEW_BUFFERS);
- ctx-Color.sRGBEnabled = state;
- break;
+ _mesa_set_framebuffer_srgb(ctx, state);
+ return;
/* GL_OES_EGL_image_external */
case GL_TEXTURE_EXTERNAL_OES:
diff --git a/src/mesa/main/enable.h b/src/mesa/main/enable.h
index c49b494..be79094 100644
--- a/src/mesa/main/enable.h
+++ b/src/mesa/main/enable.h
@@ -70,6 +70,9 @@ _mesa_DisableClientState( GLenum cap );
extern void
_mesa_set_multisample(struct gl_context *ctx, GLboolean state);
+extern void
+_mesa_set_framebuffer_srgb(struct gl_context *ctx, GLboolean state);
+
#endif
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Mesa (master): gles3: Prohibit set/get of GL_FRAMEBUFFER_SRGB.
Module: Mesa
Branch: master
Commit: 112caa853d53467a9c0ef171f272505db0278c6a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=112caa853d53467a9c0ef171f272505db0278c6a
Author: Paul Berry stereotype...@gmail.com
Date: Mon Sep 24 14:47:12 2012 -0700
gles3: Prohibit set/get of GL_FRAMEBUFFER_SRGB.
GLES 3 supports sRGB functionality, but it does not expose the
GL_FRAMEBUFFER_SRGB enable/disable bit. Instead the implementation
is expected to behave as though that bit is always enabled.
This patch ensures that ctx-Color.sRGBEnabled (the internal variable
tracking GL_FRAMEBUFFER_SRGB) is initially true in GLES 2/3 contexts,
and that it cannot be modified through the GLES 3 API.
This is safe for GLES 2, since ctx-Color.sRGBEnabled has no effect on
non-sRGB formats, and GLES 2 doesn't support any sRGB formats.
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/main/blend.c |7 +++
src/mesa/main/enable.c |4 ++--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/blend.c b/src/mesa/main/blend.c
index de871a9..5d55311 100644
--- a/src/mesa/main/blend.c
+++ b/src/mesa/main/blend.c
@@ -858,6 +858,13 @@ void _mesa_init_color( struct gl_context * ctx )
ctx-Color._ClampFragmentColor = GL_TRUE;
ctx-Color.ClampReadColor = GL_FIXED_ONLY_ARB;
ctx-Color._ClampReadColor = GL_TRUE;
+
+ if (ctx-API == API_OPENGLES2) {
+ /* GLES 3 behaves as though GL_FRAMEBUFFER_SRGB is always enabled. */
+ ctx-Color.sRGBEnabled = GL_TRUE;
+ } else {
+ ctx-Color.sRGBEnabled = GL_FALSE;
+ }
}
/*@}*/
diff --git a/src/mesa/main/enable.c b/src/mesa/main/enable.c
index 676cd9b..a607bdc 100644
--- a/src/mesa/main/enable.c
+++ b/src/mesa/main/enable.c
@@ -1061,7 +1061,7 @@ _mesa_set_enable(struct gl_context *ctx, GLenum cap,
GLboolean state)
/* GL3.0 - GL_framebuffer_sRGB */
case GL_FRAMEBUFFER_SRGB_EXT:
- if (!_mesa_is_desktop_gl(ctx) !_mesa_is_gles3(ctx))
+ if (!_mesa_is_desktop_gl(ctx))
goto invalid_enum_error;
CHECK_EXTENSION(EXT_framebuffer_sRGB, cap);
_mesa_set_framebuffer_srgb(ctx, state);
@@ -1715,7 +1715,7 @@ _mesa_IsEnabled( GLenum cap )
/* GL3.0 - GL_framebuffer_sRGB */
case GL_FRAMEBUFFER_SRGB_EXT:
- if (!_mesa_is_desktop_gl(ctx) !_mesa_is_gles3(ctx))
+ if (!_mesa_is_desktop_gl(ctx))
goto invalid_enum_error;
CHECK_EXTENSION(EXT_framebuffer_sRGB);
return ctx-Color.sRGBEnabled;
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Mesa (master): i965/blorp: Increase Y alignment for multisampled stencil blits.
Module: Mesa
Branch: master
Commit: a33ce665a5827c598b85bb04d94b33e6a5e41c28
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a33ce665a5827c598b85bb04d94b33e6a5e41c28
Author: Paul Berry stereotype...@gmail.com
Date: Wed Sep 12 11:13:49 2012 -0700
i965/blorp: Increase Y alignment for multisampled stencil blits.
This patch is a band-aid fix for a bug in commit 5fd67fa (i965/blorp:
Reduce alignment restrictions for stencil blits), which causes
multisampled stencil blits to work incorrectly on Sandy Bridge.
When blitting to or from a normal stencil buffer, we have to use a
coordinate transformation that swizzles coordinates to account for the
fact that stencil buffers use W tiling, but the most similar tiling
format available for textures and render targets is Y tiling. The
differences between W and Y tiling cause pixels to be scrambled within
a block of size 8x4 (width x height) as measured relative to a W tile,
or 16x2 as measured relative to a Y tile. So in order to make sure
that pixels at the edges of the blit aren't lost, we need to align the
rendering rectangle (and the buffer sizes) to multiples of the 8x4
block size. This alignment happens in the brw_blorp_blit_params
constructor, whereas the determination of how to swizzle the
coordinates happens during code generation, in the
brw_blorp_blit_program class.
When blitting to or from a multisampled stencil buffer, the coordinate
swizzling is more complex, because it has to account for the
interleaving pattern of samples, which uses 4x4 blocks for 4x MSAA and
8x4 blocks for 8x MSAA. The end result is that if multisampling is in
use, the 16x2 block size (relative so a Y tile) needs to be expanded
to 16x4, and the corresponding size relative to a W tile expands to
8x8.
The problem doesn't affect Ivy Bridge severely enough to crop up in
Piglit tests because on Ivy Bridge we have to disable multisampling
when blitting *to* a multisampled stencil buffer (the blorp compiler
generates code to compensate for the fact that multisampling is
disabled). However I suspect a bug is still present because we don't
disable multisampling when blitting *from* a multisampled stencil
buffer.
This patch fixes the problem by doubling the vertical alignment
requirement when blitting to or from a multisampled stencil buffer,
and multisampling has not been disabled.
In the long run I would like to rework the brw_blorp_blit_params
constructor--it's difficult to follow and has had several subtle bugs
like this one. However this band-aid fix should be suitable for
cherry-picking to release branches.
Fixes Piglit tests unaligned-blit {2,4} stencil {msaa,upsample} on
Sandy Bridge.
NOTE: This is a candidate for stable release branches.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 6e156d0..034c701 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1800,6 +1800,11 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
* account for the differences in aspect ratio between the Y and W
* sub-tiles. We need to modify the layer width and height similarly.
*
+ * A correction needs to be applied when MSAA is in use: since
+ * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
+ * we need to align the Y coordinates to multiples of 8, so that when
+ * they are divided by two they are still multiples of 4.
+ *
* Note: Since the x/y offset of the surface will be applied using the
* SURFACE_STATE command packet, it will be invisible to the swizzling
* code in the shader; therefore it needs to be in a multiple of the
@@ -1821,7 +1826,7 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
* TODO: what if this makes the coordinates (or the texture size) too
* large?
*/
- const unsigned x_align = 8, y_align = 4;
+ const unsigned x_align = 8, y_align = dst.num_samples != 0 ? 8 : 4;
x0 = ROUND_DOWN_TO(x0, x_align) * 2;
y0 = ROUND_DOWN_TO(y0, y_align) / 2;
x1 = ALIGN(x1, x_align) * 2;
@@ -1843,7 +1848,7 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
*
* TODO: what if this makes the texture size too large?
*/
- const unsigned x_align = 8, y_align = 4;
+ const unsigned x_align = 8, y_align = src.num_samples != 0 ? 8 : 4;
src.width = ALIGN(src.width, x_align) * 2;
src.height = ALIGN(src.height, y_align) / 2;
src.x_offset *= 2;
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Mesa (master): i965/blorp: Fix sRGB MSAA resolves.
Module: Mesa Branch: master Commit: 124b214f094fa63ff1ddb7e9f0a1c2e0ba8214fb URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=124b214f094fa63ff1ddb7e9f0a1c2e0ba8214fb Author: Paul Berry stereotype...@gmail.com Date: Mon Sep 24 05:38:32 2012 -0700 i965/blorp: Fix sRGB MSAA resolves. Commit e2249e8c4d06a85d6389ba1689e15d7e29aa4dff (i965/blorp: Add support for blits between SRGB and linear formats) changed blorp to always configure surface states for in linear format (even if the underlying surface is sRGB). This allowed sRGB-to-linear and linear-to-sRGB blits to occur without causing the image to be inappropriately brightened or darkened. However, it broke sRGB MSAA resolves, since they rely on the destination buffer format being sRGB in order to ensure that samples are averaged together in sRGB-correct fashion. This patch fixes the problem by instead configuring the source buffer to use the *same* format as the destination buffer. This ensures that the image won't be brightened or darkened, but preserves proper sRGB averaging. Fixes piglit tests EXT_framebuffer_multisample/accuracy srgb. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55265 NOTE: This is a candidate for stable release branches. Reviewed-by: Eric Anholt e...@anholt.net Reviewed-and-tested-by: Kenneth Graunke kenn...@whitecape.org --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 14 ++ src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 13 + 2 files changed, 19 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index 54b3ceb..77b9f8f 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -95,15 +95,13 @@ brw_blorp_surface_info::set(struct brw_context *brw, this-brw_surfaceformat = BRW_SURFACEFORMAT_R8G8_UNORM; break; default: - /* Blorp blits don't support any sort of format conversion, so we can - * safely assume that the same format is being used for the source and - * destination. Therefore the format must be supported as a render - * target, even if this is the source image. So we can convert to a - * surface format using brw-render_target_format. + /* Blorp blits don't support any sort of format conversion (except + * between sRGB and linear), so we can safely assume that the format is + * supported as a render target, even if this is the source image. So + * we can convert to a surface format using brw-render_target_format. */ - gl_format linear_format = _mesa_get_srgb_format_linear(mt-format); - assert(brw-format_supported_as_render_target[linear_format]); - this-brw_surfaceformat = brw-render_target_format[linear_format]; + assert(brw-format_supported_as_render_target[mt-format]); + this-brw_surfaceformat = brw-render_target_format[mt-format]; break; } } diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp index 034c701..e8604e7 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp @@ -1641,6 +1641,19 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw, src.set(brw, src_mt, src_level, src_layer); dst.set(brw, dst_mt, dst_level, dst_layer); + /* If we are blitting from sRGB to linear or vice versa, we still want the +* blit to be a direct copy, so we need source and destination to use the +* same format. However, we want the destination sRGB/linear state to be +* correct (so that sRGB blending is used when doing an MSAA resolve to an +* sRGB surface, and linear blending is used when doing an MSAA resolve to +* a linear surface). Since blorp blits don't support any format +* conversion (except between sRGB and linear), we can accomplish this by +* simply setting up the source to use the same format as the destination. +*/ + assert(_mesa_get_srgb_format_linear(src_mt-format) == + _mesa_get_srgb_format_linear(dst_mt-format)); + src.brw_surfaceformat = dst.brw_surfaceformat; + use_wm_prog = true; memset(wm_prog_key, 0, sizeof(wm_prog_key)); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): meta: Refactor handling of GL_MULTISAMPLE.
Module: Mesa
Branch: master
Commit: a29a4566354af53e3bdc4a925eddc0d7af2bf384
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a29a4566354af53e3bdc4a925eddc0d7af2bf384
Author: Paul Berry stereotype...@gmail.com
Date: Thu Sep 13 10:20:07 2012 -0700
meta: Refactor handling of GL_MULTISAMPLE.
In commit 055093e (meta: remove call to _meta_in_progress(), fix
multisample enable/disable), we created a meta_set_enable() function
that could be used by meta ops to enable and disable GL_MULTISAMPLE
even when the GLES API was in use (the GLES API doesn't support
GL_MULTISAMPLE; it behaves as if it is always enabled). This created
some unfortunate code duplication between meta_set_enable() and the
existing _mesa_set_enable() function.
This patch eliminates the duplication by creating a
_mesa_set_multisample() function, which is used by both meta ops and
_mesa_set_enable() to enable/disable GL_MULTISAMPLE.
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/common/meta.c | 33 ++---
src/mesa/main/enable.c | 24 +++-
src/mesa/main/enable.h |4
3 files changed, 25 insertions(+), 36 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 3d8e138..677548e 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -448,35 +448,6 @@ _mesa_meta_free(struct gl_context *ctx)
/**
- * This is an alternative to _mesa_set_enable() to handle some special cases.
- * See comments inside.
- */
-static void
-meta_set_enable(struct gl_context *ctx, GLenum cap, GLboolean state)
-{
- switch (cap) {
- case GL_MULTISAMPLE:
- /* We need to enable/disable multisample when using GLES but this enum
- * is not supported there.
- */
- if (ctx-Multisample.Enabled == state)
- return;
- FLUSH_VERTICES(ctx, _NEW_MULTISAMPLE);
- ctx-Multisample.Enabled = state;
- break;
- default:
- _mesa_problem(ctx, Unexpected cap in _meta_set_enable());
- return;
- }
-
- if (ctx-Driver.Enable) {
- ctx-Driver.Enable(ctx, cap, state);
- }
-}
-
-
-
-/**
* Enter meta state. This is like a light-weight version of glPushAttrib
* but it also resets most GL state back to default values.
*
@@ -796,7 +767,7 @@ _mesa_meta_begin(struct gl_context *ctx, GLbitfield state)
if (state MESA_META_MULTISAMPLE) {
save-MultisampleEnabled = ctx-Multisample.Enabled;
if (ctx-Multisample.Enabled)
- meta_set_enable(ctx, GL_MULTISAMPLE, GL_FALSE);
+ _mesa_set_multisample(ctx, GL_FALSE);
}
/* misc */
@@ -1100,7 +1071,7 @@ _mesa_meta_end(struct gl_context *ctx)
if (state MESA_META_MULTISAMPLE) {
if (ctx-Multisample.Enabled != save-MultisampleEnabled)
- meta_set_enable(ctx, GL_MULTISAMPLE, save-MultisampleEnabled);
+ _mesa_set_multisample(ctx, save-MultisampleEnabled);
}
/* misc */
diff --git a/src/mesa/main/enable.c b/src/mesa/main/enable.c
index 14eea53..5dd8833 100644
--- a/src/mesa/main/enable.c
+++ b/src/mesa/main/enable.c
@@ -251,6 +251,23 @@ enable_texture(struct gl_context *ctx, GLboolean state,
GLbitfield texBit)
/**
+ * Helper function to enable or disable GL_MULTISAMPLE, skipping the check for
+ * whether the API supports it (GLES doesn't).
+ */
+void
+_mesa_set_multisample(struct gl_context *ctx, GLboolean state)
+{
+ if (ctx-Multisample.Enabled == state)
+ return;
+ FLUSH_VERTICES(ctx, _NEW_MULTISAMPLE);
+ ctx-Multisample.Enabled = state;
+
+ if (ctx-Driver.Enable) {
+ ctx-Driver.Enable(ctx, GL_MULTISAMPLE, state);
+ }
+}
+
+/**
* Helper function to enable or disable state.
*
* \param ctx GL context.
@@ -767,11 +784,8 @@ _mesa_set_enable(struct gl_context *ctx, GLenum cap,
GLboolean state)
case GL_MULTISAMPLE_ARB:
if (!_mesa_is_desktop_gl(ctx) ctx-API != API_OPENGLES)
goto invalid_enum_error;
- if (ctx-Multisample.Enabled == state)
-return;
- FLUSH_VERTICES(ctx, _NEW_MULTISAMPLE);
- ctx-Multisample.Enabled = state;
- break;
+ _mesa_set_multisample(ctx, state);
+ return;
case GL_SAMPLE_ALPHA_TO_COVERAGE_ARB:
if (ctx-Multisample.SampleAlphaToCoverage == state)
return;
diff --git a/src/mesa/main/enable.h b/src/mesa/main/enable.h
index 6d90c17..c49b494 100644
--- a/src/mesa/main/enable.h
+++ b/src/mesa/main/enable.h
@@ -67,5 +67,9 @@ _mesa_EnableClientState( GLenum cap );
extern void GLAPIENTRY
_mesa_DisableClientState( GLenum cap );
+extern void
+_mesa_set_multisample(struct gl_context *ctx, GLboolean state);
+
+
#endif
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Mesa (master): i965/gen6+: Adjust stencil buffer size after computing miptree layout.
Module: Mesa
Branch: master
Commit: bde833c9d014ad8aebfab0d2285184d7e6d5896d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bde833c9d014ad8aebfab0d2285184d7e6d5896d
Author: Paul Berry stereotype...@gmail.com
Date: Tue Sep 4 07:57:37 2012 -0700
i965/gen6+: Adjust stencil buffer size after computing miptree layout.
Since Gen6+ stencil buffers use W-tiling (a tiling arrangement which
drm and the kernel are not aware of) we need to round up the width and
height of a stencil buffer to multiples of the W-tile size (64x64)
before allocating a stencil buffer. Previously, we rounded up the
size of the base miplevel, and then computed the miptree layout based
on the rounded up size. This was incorrect, because it meant that the
total size of the miptree would not be properly W-tile aligned, and
therefore we would not always allocate enough pages.
(Note: even though the GL API doesn't allow creation of mipmapped
stencil textures, it does allow mipmapping of a combined depth/stencil
texture, and on Gen6+, a combined depth/stencil texture is internally
implemented as a pair of separate depth and stencil buffers.)
For example, on Sandy Bridge, when allocating a mipmapped stencil
texture of size 128x128, we would first round up to the nearest
multiple of 64x64 (causing no change to the size), and then compute
the miptree layout (whose size worked out to 128x196). Then we would
request an allocation of 128*196 bytes (6.125 pages), causing 7 pages
to be allocated to the texture. However, the texture needs 8 pages,
since each W-tile occupies a page, and it takes 2 W-tiles to cover a
width of 128 and 4 W-tiles to cover a height of 196.
This patch changes the order of operations so that the miptree layout
is computed first and then the total size of the miptree is rounded up
to be W-tile aligned.
NOTE: This is a candidate for stable release branches.
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 28 +--
1 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 24cd9e9..dbfddc8 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -200,6 +200,7 @@ intel_miptree_create(struct intel_context *intel,
uint32_t tiling = I915_TILING_NONE;
GLenum base_format;
bool wraps_etc1 = false;
+ GLuint total_width, total_height;
if (format == MESA_FORMAT_ETC1_RGB8) {
format = MESA_FORMAT_RGBX_REV;
@@ -231,16 +232,6 @@ intel_miptree_create(struct intel_context *intel,
tiling = I915_TILING_X;
}
- if (format == MESA_FORMAT_S8) {
- /* The stencil buffer is W tiled. However, we request from the kernel a
- * non-tiled buffer because the GTT is incapable of W fencing. So round
- * up the width and height to match the size of W tiles (64x64).
- */
- tiling = I915_TILING_NONE;
- width0 = ALIGN(width0, 64);
- height0 = ALIGN(height0, 64);
- }
-
mt = intel_miptree_create_internal(intel, target, format,
first_level, last_level, width0,
height0, depth0,
@@ -253,12 +244,25 @@ intel_miptree_create(struct intel_context *intel,
return NULL;
}
+ total_width = mt-total_width;
+ total_height = mt-total_height;
+
+ if (format == MESA_FORMAT_S8) {
+ /* The stencil buffer is W tiled. However, we request from the kernel a
+ * non-tiled buffer because the GTT is incapable of W fencing. So round
+ * up the width and height to match the size of W tiles (64x64).
+ */
+ tiling = I915_TILING_NONE;
+ total_width = ALIGN(total_width, 64);
+ total_height = ALIGN(total_height, 64);
+ }
+
mt-wraps_etc1 = wraps_etc1;
mt-region = intel_region_alloc(intel-intelScreen,
tiling,
mt-cpp,
- mt-total_width,
- mt-total_height,
+ total_width,
+ total_height,
expect_accelerated_upload);
mt-offset = 0;
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Mesa (master): i965/blorp: Clarify why width/ height must be adjusted for Gen6 IMS surfaces.
Module: Mesa
Branch: master
Commit: 32c7b2769cbe80ff56d1c73c4f9b62f13f577c8d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=32c7b2769cbe80ff56d1c73c4f9b62f13f577c8d
Author: Paul Berry stereotype...@gmail.com
Date: Wed Aug 29 12:04:30 2012 -0700
i965/blorp: Clarify why width/height must be adjusted for Gen6 IMS surfaces.
Also add a clarifying comment for why the width/height doesn't need
adjustment for Gen7.
NOTE: This is a candidate for stable release branches.
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp |6 +-
src/mesa/drivers/dri/i965/gen7_blorp.cpp |5 +
2 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 995b507..8a22fe3 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -415,7 +415,11 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
uint32_t wm_surf_offset;
uint32_t width, height;
surface-get_miplevel_dims(width, height);
- if (surface-num_samples 1) { /* TODO: seems clumsy */
+ if (surface-num_samples 1) {
+ /* Since gen6 uses INTEL_MSAA_LAYOUT_IMS, width and height are measured
+ * in samples. But SURFACE_STATE wants them in pixels, so we need to
+ * divide them each by 2.
+ */
width /= 2;
height /= 2;
}
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index a65a975..e23868d 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -144,6 +144,11 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
uint32_t wm_surf_offset;
uint32_t width, height;
surface-get_miplevel_dims(width, height);
+ /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
+* color surfaces, width and height are measured in pixels; we don't need
+* to divide them by 2 as we do for Gen6 (see
+* gen6_blorp_emit_surface_state).
+*/
if (surface-map_stencil_as_y_tiled) {
width *= 2;
height /= 2;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/blorp: Change gl_renderbuffer* params to intel_renderbuffer*.
Module: Mesa
Branch: master
Commit: e14b1288ef5b5b6091facaecd42e86f0a8157f28
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e14b1288ef5b5b6091facaecd42e86f0a8157f28
Author: Paul Berry stereotype...@gmail.com
Date: Wed Aug 15 14:51:56 2012 -0700
i965/blorp: Change gl_renderbuffer* params to intel_renderbuffer*.
This makes it more convenient for blorp functions to get access to
Intel-specific data inside the renderbuffer objects.
NOTE: This is a candidate for stable release branches.
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 60 ++
1 files changed, 32 insertions(+), 28 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 1e49ac5..0b2dbe3 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -112,9 +112,8 @@ clip_or_scissor(bool mirror, GLint src_x0, GLint src_x1,
GLint dst_x0,
static struct intel_mipmap_tree *
-find_miptree(GLbitfield buffer_bit, struct gl_renderbuffer *rb)
+find_miptree(GLbitfield buffer_bit, struct intel_renderbuffer *irb)
{
- struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_mipmap_tree *mt = irb-mt;
if (buffer_bit == GL_STENCIL_BUFFER_BIT mt-stencil_mt)
mt = mt-stencil_mt;
@@ -141,42 +140,43 @@ brw_blorp_blit_miptrees(struct intel_context *intel,
static void
do_blorp_blit(struct intel_context *intel, GLbitfield buffer_bit,
- struct gl_renderbuffer *src_rb, struct gl_renderbuffer *dst_rb,
+ struct intel_renderbuffer *src_irb,
+ struct intel_renderbuffer *dst_irb,
GLint srcX0, GLint srcY0,
GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
bool mirror_x, bool mirror_y)
{
/* Find source/dst miptrees */
- struct intel_mipmap_tree *src_mt = find_miptree(buffer_bit, src_rb);
- struct intel_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_rb);
+ struct intel_mipmap_tree *src_mt = find_miptree(buffer_bit, src_irb);
+ struct intel_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_irb);
/* Get ready to blit. This includes depth resolving the src and dst
* buffers if necessary.
*/
- intel_renderbuffer_resolve_depth(intel, intel_renderbuffer(src_rb));
- intel_renderbuffer_resolve_depth(intel, intel_renderbuffer(dst_rb));
+ intel_renderbuffer_resolve_depth(intel, src_irb);
+ intel_renderbuffer_resolve_depth(intel, dst_irb);
/* Do the blit */
brw_blorp_blit_miptrees(intel, src_mt, dst_mt,
srcX0, srcY0, dstX0, dstY0, dstX1, dstY1,
mirror_x, mirror_y);
- intel_renderbuffer_set_needs_hiz_resolve(intel_renderbuffer(dst_rb));
- intel_renderbuffer_set_needs_downsample(intel_renderbuffer(dst_rb));
+ intel_renderbuffer_set_needs_hiz_resolve(dst_irb);
+ intel_renderbuffer_set_needs_downsample(dst_irb);
}
static bool
-formats_match(GLbitfield buffer_bit, struct gl_renderbuffer *src_rb,
- struct gl_renderbuffer *dst_rb)
+formats_match(GLbitfield buffer_bit, struct intel_renderbuffer *src_irb,
+ struct intel_renderbuffer *dst_irb)
{
/* Note: don't just check gl_renderbuffer::Format, because in some cases
* multiple gl_formats resolve to the same native type in the miptree (for
* example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit
* between those formats.
*/
- return find_miptree(buffer_bit, src_rb)-format ==
- find_miptree(buffer_bit, dst_rb)-format;
+ return find_miptree(buffer_bit, src_irb)-format ==
+ find_miptree(buffer_bit, dst_irb)-format;
}
@@ -243,36 +243,40 @@ try_blorp_blit(struct intel_context *intel,
}
/* Find buffers */
- struct gl_renderbuffer *src_rb;
- struct gl_renderbuffer *dst_rb;
+ struct intel_renderbuffer *src_irb;
+ struct intel_renderbuffer *dst_irb;
switch (buffer_bit) {
case GL_COLOR_BUFFER_BIT:
- src_rb = read_fb-_ColorReadBuffer;
+ src_irb = intel_renderbuffer(read_fb-_ColorReadBuffer);
for (unsigned i = 0; i ctx-DrawBuffer-_NumColorDrawBuffers; ++i) {
- dst_rb = ctx-DrawBuffer-_ColorDrawBuffers[i];
- if (dst_rb !formats_match(buffer_bit, src_rb, dst_rb))
+ dst_irb = intel_renderbuffer(ctx-DrawBuffer-_ColorDrawBuffers[i]);
+ if (dst_irb !formats_match(buffer_bit, src_irb, dst_irb))
return false;
}
for (unsigned i = 0; i ctx-DrawBuffer-_NumColorDrawBuffers; ++i) {
- dst_rb = ctx-DrawBuffer-_ColorDrawBuffers[i];
- do_blorp_blit(intel, buffer_bit, src_rb, dst_rb, srcX0, srcY0,
+ dst_irb = intel_renderbuffer(ctx-DrawBuffer-_ColorDrawBuffers[i]);
+ do_blorp_blit(intel, buffer_bit, src_irb, dst_irb, srcX0, srcY0,
dstX0, dstY0, dstX1, dstY1, mirror_x, mirror_y
Mesa (master): i965/blorp: store surface width/height in brw_blorp_mip_info .
Module: Mesa
Branch: master
Commit: 09b0fa8499d8035fa31ccb2b550056305fbd149b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=09b0fa8499d8035fa31ccb2b550056305fbd149b
Author: Paul Berry stereotype...@gmail.com
Date: Wed Aug 29 11:51:14 2012 -0700
i965/blorp: store surface width/height in brw_blorp_mip_info.
Previously, gen{6,7}_blorp_emit_surface_state would look up the width
and height of the surface at the time they set up the surface state,
and then tweak it if necessary (it's necessary when a W-tiled surface
is being mapped as Y-tiled). With this patch, we look up the width
and height when setting up the blit, and store them in
brw_blorp_mip_info. This allows us to do the necessary tweak in the
brw_blorp_blit_params constructor (where it makes more sense). It
also reduces the need to keep track of level and layer in
brw_blorp_mip_info, so that a future patch can eliminate them
entirely.
For consistency, this patch makes a similar change to the handling of
depth buffers when doing HiZ operations.
NOTE: This is a candidate for stable release branches.
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/i965/brw_blorp.cpp |9 ++-
src/mesa/drivers/dri/i965/brw_blorp.h| 18 +++-
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 28 +++--
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 15 +++--
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 15 +++--
5 files changed, 48 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 9017e4d..7322a04 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -31,7 +31,9 @@
brw_blorp_mip_info::brw_blorp_mip_info()
: mt(NULL),
level(0),
- layer(0)
+ layer(0),
+ width(0),
+ height(0)
{
}
@@ -50,6 +52,8 @@ brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
this-mt = mt;
this-level = level;
this-layer = layer;
+ this-width = mt-level[level].width;
+ this-height = mt-level[level].height;
}
void
@@ -164,7 +168,8 @@ brw_hiz_op_params::brw_hiz_op_params(struct
intel_mipmap_tree *mt,
this-hiz_op = op;
depth.set(mt, level, layer);
- depth.get_miplevel_dims(x1, y1);
+ x1 = depth.width;
+ y1 = depth.height;
assert(mt-hiz_mt != NULL);
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index dbbd508..d53fca2 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -65,15 +65,21 @@ public:
unsigned int level, unsigned int layer);
void get_draw_offsets(uint32_t *draw_x, uint32_t *draw_y) const;
- void get_miplevel_dims(uint32_t *width, uint32_t *height) const
- {
- *width = mt-level[level].width;
- *height = mt-level[level].height;
- }
-
struct intel_mipmap_tree *mt;
unsigned int level;
unsigned int layer;
+
+ /**
+* Width of the miplevel to be used. For surfaces using
+* INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
+*/
+ uint32_t width;
+
+ /**
+* Height of the miplevel to be used. For surfaces using
+* INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
+*/
+ uint32_t height;
};
class brw_blorp_surface_info : public brw_blorp_mip_info
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 0b2dbe3..d92f674 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1770,18 +1770,20 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
}
if (dst.map_stencil_as_y_tiled) {
- /* We must modify the rectangle we send through the rendering pipeline,
- * to account for the fact that we are mapping it as Y-tiled when it is
- * in fact W-tiled. Y tiles have dimensions 128x32 whereas W tiles have
- * dimensions 64x64. We must also align it to a multiple of the tile
- * size, because the differences between W and Y tiling formats will
- * mean that pixels are scrambled within the tile.
+ /* We must modify the rectangle we send through the rendering pipeline
+ * (and the size of the destination surface), to account for the fact
+ * that we are mapping it as Y-tiled when it is in fact W-tiled. Y
+ * tiles have dimensions 128x32 whereas W tiles have dimensions 64x64.
+ * We must also align it to a multiple of the tile size, because the
+ * differences between W and Y tiling formats will mean that pixels are
+ * scrambled within the tile.
*
* Note: if the destination surface configured to use IMS layout, then
* the effective tile size we need to align it to is smaller, because
* each pixel covers a 2x2 or a 4x2 block of samples
Mesa (master): i965/blorp: store x and y offsets in brw_blorp_mip_info.
Module: Mesa
Branch: master
Commit: c130ce7b2b26b4b67d4bf2b6dd1044a200efe25d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c130ce7b2b26b4b67d4bf2b6dd1044a200efe25d
Author: Paul Berry stereotype...@gmail.com
Date: Wed Aug 29 12:16:06 2012 -0700
i965/blorp: store x and y offsets in brw_blorp_mip_info.
Currently, gen{6,7}_blorp_emit_surface_state assumes that the src and
dst surfaces are mapped to miplevel 0 and layer 0 (thus no surface
offset is required). This is a bug, since the user might try to blit
to and from levels/layers other than 0.
To fix this bug, it will not be sufficient to have
gen6_{6,7}_blorp_emit_surface_state look up the surface offset at the
time they set up the surface state, since these offsets will need to
be tweaked when blitting stencil buffers (due to the fact that stencil
buffer blits have to swizzle between W and Y tiling formats).
So, to pave the way for the bug fix, this patch causes the x and y
offsets to be computed during blit setup and stored in
brw_blorp_mip_info.
As a result of this change, brw_blorp_mip_info doesn't need to store
the level and layer anymore.
For consistency, this patch makes a similar change to the handling of
depth buffers when doing HiZ operations.
NOTE: This is a candidate for stable release branches.
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 30 --
src/mesa/drivers/dri/i965/brw_blorp.h| 17 ++---
src/mesa/drivers/dri/i965/gen6_blorp.cpp |4 ++--
src/mesa/drivers/dri/i965/gen7_blorp.cpp |8 +++-
4 files changed, 31 insertions(+), 28 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 7322a04..6acc591 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -30,10 +30,10 @@
brw_blorp_mip_info::brw_blorp_mip_info()
: mt(NULL),
- level(0),
- layer(0),
width(0),
- height(0)
+ height(0),
+ x_offset(0),
+ y_offset(0)
{
}
@@ -50,10 +50,17 @@ brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
intel_miptree_check_level_layer(mt, level, layer);
this-mt = mt;
- this-level = level;
- this-layer = layer;
this-width = mt-level[level].width;
this-height = mt-level[level].height;
+
+ /* Construct a dummy renderbuffer just to extract tile offsets. */
+ struct intel_renderbuffer rb;
+ rb.mt = mt;
+ rb.mt_level = level;
+ rb.mt_layer = layer;
+ intel_renderbuffer_set_draw_offset(rb);
+ x_offset = rb.draw_x;
+ y_offset = rb.draw_y;
}
void
@@ -107,19 +114,6 @@ brw_blorp_surface_info::set(struct brw_context *brw,
}
}
-void
-brw_blorp_mip_info::get_draw_offsets(uint32_t *draw_x, uint32_t *draw_y) const
-{
- /* Construct a dummy renderbuffer just to extract tile offsets. */
- struct intel_renderbuffer rb;
- rb.mt = mt;
- rb.mt_level = level;
- rb.mt_layer = layer;
- intel_renderbuffer_set_draw_offset(rb);
- *draw_x = rb.draw_x;
- *draw_y = rb.draw_y;
-}
-
brw_blorp_params::brw_blorp_params()
: x0(0),
y0(0),
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index d53fca2..023b966 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -63,11 +63,8 @@ public:
void set(struct intel_mipmap_tree *mt,
unsigned int level, unsigned int layer);
- void get_draw_offsets(uint32_t *draw_x, uint32_t *draw_y) const;
struct intel_mipmap_tree *mt;
- unsigned int level;
- unsigned int layer;
/**
* Width of the miplevel to be used. For surfaces using
@@ -80,6 +77,20 @@ public:
* INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
*/
uint32_t height;
+
+ /**
+* X offset within the surface to texture from (or render to). For
+* surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
+* pixels.
+*/
+ uint32_t x_offset;
+
+ /**
+* Y offset within the surface to texture from (or render to). For
+* surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
+* pixels.
+*/
+ uint32_t y_offset;
};
class brw_blorp_surface_info : public brw_blorp_mip_info
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 14e8563..d5d65c6 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -823,11 +823,11 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context
*brw,
const brw_blorp_params *params)
{
struct intel_context *intel = brw-intel;
- uint32_t draw_x, draw_y;
+ uint32_t draw_x = params-depth.x_offset;
+ uint32_t draw_y = params-depth.y_offset;
uint32_t tile_mask_x, tile_mask_y;
gen6_blorp_compute_tile_masks(params, tile_mask_x, tile_mask_y);
- params
Mesa (master): i965/blorp: Don' t create a dummy renderbuffer just to fetch image offsets.
Module: Mesa Branch: master Commit: bc6cafa045d8de839090fe2d82716b3afbd54701 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bc6cafa045d8de839090fe2d82716b3afbd54701 Author: Paul Berry stereotype...@gmail.com Date: Mon Sep 10 11:30:14 2012 -0700 i965/blorp: Don't create a dummy renderbuffer just to fetch image offsets. This is unnecessary--the image offsets can be read directly out of the miptree using intel_miptree_get_image_offset. --- src/mesa/drivers/dri/i965/brw_blorp.cpp |9 + 1 files changed, 1 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index 6acc591..af1156c 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -53,14 +53,7 @@ brw_blorp_mip_info::set(struct intel_mipmap_tree *mt, this-width = mt-level[level].width; this-height = mt-level[level].height; - /* Construct a dummy renderbuffer just to extract tile offsets. */ - struct intel_renderbuffer rb; - rb.mt = mt; - rb.mt_level = level; - rb.mt_layer = layer; - intel_renderbuffer_set_draw_offset(rb); - x_offset = rb.draw_x; - y_offset = rb.draw_y; + intel_miptree_get_image_offset(mt, level, 0, layer, x_offset, y_offset); } void ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/blorp: Thread level and layer through brw_blorp_blit_miptrees().
Module: Mesa
Branch: master
Commit: 3123f0621561549c4566248100661ef77cab2834
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3123f0621561549c4566248100661ef77cab2834
Author: Paul Berry stereotype...@gmail.com
Date: Thu Aug 16 10:06:08 2012 -0700
i965/blorp: Thread level and layer through brw_blorp_blit_miptrees().
Previously, when performing a blit using the blorp engine, we failed
to account for the level and layer of the source and destination. As
a result, all blits would occur between miplevel 0 and layer 0 of the
corresponding textures, regardless of which level/layer was bound to
the framebuffer.
This patch passes the correct level and layer through
brw_blorp_miptrees() into the brw_blorp_blit_params data structure.
Further patches in the series will adapt
gen{6,7}_blorp_emit_surface_state to make use of these parameters.
NOTE: This is a candidate for stable release branches.
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/i965/brw_blorp.h |4
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 15 +++
src/mesa/drivers/dri/intel/intel_mipmap_tree.c |6 --
3 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 023b966..ef0c274 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -37,7 +37,9 @@ extern C {
void
brw_blorp_blit_miptrees(struct intel_context *intel,
struct intel_mipmap_tree *src_mt,
+unsigned src_level, unsigned src_layer,
struct intel_mipmap_tree *dst_mt,
+unsigned dst_level, unsigned dst_layer,
int src_x0, int src_y0,
int dst_x0, int dst_y0,
int dst_x1, int dst_y1,
@@ -295,7 +297,9 @@ class brw_blorp_blit_params : public brw_blorp_params
public:
brw_blorp_blit_params(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
+ unsigned src_level, unsigned src_layer,
struct intel_mipmap_tree *dst_mt,
+ unsigned dst_level, unsigned dst_layer,
GLuint src_x0, GLuint src_y0,
GLuint dst_x0, GLuint dst_y0,
GLuint width, GLuint height,
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index d92f674..ede78cc 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -123,14 +123,17 @@ find_miptree(GLbitfield buffer_bit, struct
intel_renderbuffer *irb)
void
brw_blorp_blit_miptrees(struct intel_context *intel,
struct intel_mipmap_tree *src_mt,
+unsigned src_level, unsigned src_layer,
struct intel_mipmap_tree *dst_mt,
+unsigned dst_level, unsigned dst_layer,
int src_x0, int src_y0,
int dst_x0, int dst_y0,
int dst_x1, int dst_y1,
bool mirror_x, bool mirror_y)
{
brw_blorp_blit_params params(brw_context(intel-ctx),
-src_mt, dst_mt,
+src_mt, src_level, src_layer,
+dst_mt, dst_level, dst_layer,
src_x0, src_y0,
dst_x0, dst_y0,
dst_x1, dst_y1,
@@ -157,7 +160,9 @@ do_blorp_blit(struct intel_context *intel, GLbitfield
buffer_bit,
intel_renderbuffer_resolve_depth(intel, dst_irb);
/* Do the blit */
- brw_blorp_blit_miptrees(intel, src_mt, dst_mt,
+ brw_blorp_blit_miptrees(intel,
+ src_mt, src_irb-mt_level, src_irb-mt_layer,
+ dst_mt, dst_irb-mt_level, dst_irb-mt_layer,
srcX0, srcY0, dstX0, dstY0, dstX1, dstY1,
mirror_x, mirror_y);
@@ -1622,14 +1627,16 @@ compute_msaa_layout_for_pipeline(struct brw_context
*brw, unsigned num_samples,
brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
+ unsigned src_level, unsigned
src_layer,
struct intel_mipmap_tree *dst_mt,
+ unsigned dst_level, unsigned
dst_layer,
GLuint src_x0, GLuint src_y0,
GLuint dst_x0, GLuint dst_y0,
GLuint dst_x1, GLuint dst_y1,
bool mirror_x, bool
Mesa (master): i965/blorp: Account for offsets when emitting SURFACE_STATE.
Module: Mesa
Branch: master
Commit: f04f219906e40a6647a10fd9c1928509fe25fb84
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f04f219906e40a6647a10fd9c1928509fe25fb84
Author: Paul Berry stereotype...@gmail.com
Date: Wed Aug 29 16:04:15 2012 -0700
i965/blorp: Account for offsets when emitting SURFACE_STATE.
Fixes piglit tests framebuffer-blit-levels {read,draw} depth.
NOTE: This is a candidate for stable release branches.
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 25 +
src/mesa/drivers/dri/i965/brw_blorp.h|2 ++
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 13 ++---
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 12 +++-
4 files changed, 48 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index af1156c..3368907 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -107,6 +107,31 @@ brw_blorp_surface_info::set(struct brw_context *brw,
}
}
+
+/**
+ * Split x_offset and y_offset into a base offset (in bytes) and a remaining
+ * x/y offset (in pixels). Note: we can't do this by calling
+ * intel_renderbuffer_tile_offsets(), because the offsets may have been
+ * adjusted to account for Y vs. W tiling differences. So we compute it
+ * directly from the adjusted offsets.
+ */
+uint32_t
+brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
+ uint32_t *tile_y) const
+{
+ struct intel_region *region = mt-region;
+ uint32_t mask_x, mask_y;
+
+ intel_region_get_tile_masks(region, mask_x, mask_y);
+
+ *tile_x = x_offset mask_x;
+ *tile_y = y_offset mask_y;
+
+ return intel_region_get_aligned_offset(region, x_offset ~mask_x,
+ y_offset ~mask_y);
+}
+
+
brw_blorp_params::brw_blorp_params()
: x0(0),
y0(0),
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index ef0c274..0ad7c1b 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -104,6 +104,8 @@ public:
struct intel_mipmap_tree *mt,
unsigned int level, unsigned int layer);
+ uint32_t compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const;
+
/* Setting this flag indicates that the buffer's contents are W-tiled
* stencil data, but the surface state should be set up for Y tiled
* MESA_FORMAT_R8 data (this is necessary because surface states don't
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index d5d65c6..baf3fa4 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -424,6 +424,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
height /= 2;
}
struct intel_region *region = surface-mt-region;
+ uint32_t tile_x, tile_y;
uint32_t *surf = (uint32_t *)
brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
@@ -435,7 +436,8 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
surface-brw_surfaceformat BRW_SURFACE_FORMAT_SHIFT);
/* reloc */
- surf[1] = region-bo-offset; /* No tile offsets needed */
+ surf[1] = (surface-compute_tile_offsets(tile_x, tile_y) +
+ region-bo-offset);
surf[2] = (0 BRW_SURFACE_LOD_SHIFT |
(width - 1) BRW_SURFACE_WIDTH_SHIFT |
@@ -453,8 +455,13 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
surf[4] = brw_get_surface_num_multisamples(surface-num_samples);
- surf[5] = (0 BRW_SURFACE_X_OFFSET_SHIFT |
- 0 BRW_SURFACE_Y_OFFSET_SHIFT |
+ /* Note that the low bits of these fields are missing, so
+* there's the possibility of getting in trouble.
+*/
+ assert(tile_x % 4 == 0);
+ assert(tile_y % 2 == 0);
+ surf[5] = ((tile_x / 4) BRW_SURFACE_X_OFFSET_SHIFT |
+ (tile_y / 2) BRW_SURFACE_Y_OFFSET_SHIFT |
(surface-mt-align_h == 4 ?
BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 3520ff6..00f13a5 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -150,6 +150,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
* gen6_blorp_emit_surface_state).
*/
struct intel_region *region = surface-mt-region;
+ uint32_t tile_x, tile_y;
struct gen7_surface_state *surf = (struct gen7_surface_state *)
brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, sizeof(*surf), 32,
@@ -167,7 +168,16 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
GEN7_SURFACE_ARYSPC_LOD0 : GEN7_SURFACE_ARYSPC_FULL;
/* reloc */
- surf-ss1.base_addr = region-bo-offset; /* No tile offsets needed */
+ surf-ss1
Mesa (master): intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks.
Module: Mesa
Branch: master
Commit: 50dec7fc2d5ba813aaa822596d124098a22db301
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=50dec7fc2d5ba813aaa822596d124098a22db301
Author: Paul Berry stereotype...@gmail.com
Date: Thu Aug 30 10:57:03 2012 -0700
intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks.
When the blorp engine is performing a blit from one stencil buffer to
another, it sets up the surface state for these buffers as Y-tiled, so
it needs to be able to force intel_region_get_tile_masks() to return
the appropriate masks for a Y-tiled region.
NOTE: This is a candidate for stable release branches.
Acked-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/i965/brw_blorp.cpp |3 ++-
src/mesa/drivers/dri/i965/brw_misc_state.c |6 +++---
src/mesa/drivers/dri/i965/gen6_blorp.cpp|4 ++--
src/mesa/drivers/dri/i965/gen7_misc_state.c |5 +++--
src/mesa/drivers/dri/intel/intel_fbo.c |2 +-
src/mesa/drivers/dri/intel/intel_regions.c |9 +++--
src/mesa/drivers/dri/intel/intel_regions.h |3 ++-
src/mesa/drivers/dri/intel/intel_screen.c |2 +-
8 files changed, 21 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 3368907..7e45191 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -122,7 +122,8 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t
*tile_x,
struct intel_region *region = mt-region;
uint32_t mask_x, mask_y;
- intel_region_get_tile_masks(region, mask_x, mask_y);
+ intel_region_get_tile_masks(region, mask_x, mask_y,
+ map_stencil_as_y_tiled);
*tile_x = x_offset mask_x;
*tile_y = y_offset mask_y;
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 3f186f5..52926fb 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -288,7 +288,7 @@ static void emit_depthbuffer(struct brw_context *brw)
if (depth_irb) {
intel_region_get_tile_masks(depth_irb-mt-region,
- tile_mask_x, tile_mask_y);
+ tile_mask_x, tile_mask_y, false);
}
if (depth_irb
@@ -298,7 +298,7 @@ static void emit_depthbuffer(struct brw_context *brw)
uint32_t hiz_tile_mask_x, hiz_tile_mask_y;
intel_region_get_tile_masks(hiz_region,
- hiz_tile_mask_x, hiz_tile_mask_y);
+ hiz_tile_mask_x, hiz_tile_mask_y, false);
/* Each HiZ row represents 2 rows of pixels */
hiz_tile_mask_y = hiz_tile_mask_y 1 | 1;
@@ -331,7 +331,7 @@ static void emit_depthbuffer(struct brw_context *brw)
uint32_t stencil_tile_mask_x, stencil_tile_mask_y;
intel_region_get_tile_masks(stencil_mt-region,
stencil_tile_mask_x,
- stencil_tile_mask_y);
+ stencil_tile_mask_y, false);
tile_mask_x |= stencil_tile_mask_x;
tile_mask_y |= stencil_tile_mask_y;
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index baf3fa4..3e0b80e 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -58,9 +58,9 @@ gen6_blorp_compute_tile_masks(const brw_blorp_params *params,
{
uint32_t depth_mask_x, depth_mask_y, hiz_mask_x, hiz_mask_y;
intel_region_get_tile_masks(params-depth.mt-region,
- depth_mask_x, depth_mask_y);
+ depth_mask_x, depth_mask_y, false);
intel_region_get_tile_masks(params-depth.mt-hiz_mt-region,
- hiz_mask_x, hiz_mask_y);
+ hiz_mask_x, hiz_mask_y, false);
/* Each HiZ row represents 2 rows of pixels */
hiz_mask_y = hiz_mask_y 1 | 1;
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index a0d2460..9709b8e 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -69,12 +69,13 @@ static void emit_depthbuffer(struct brw_context *brw)
hiz_mt = depth_mt-hiz_mt;
intel_region_get_tile_masks(depth_mt-region,
- tile_mask_x, tile_mask_y);
+ tile_mask_x, tile_mask_y, false);
if (hiz_mt) {
uint32_t hiz_tile_mask_x, hiz_tile_mask_y;
intel_region_get_tile_masks(hiz_mt-region,
- hiz_tile_mask_x, hiz_tile_mask_y);
+ hiz_tile_mask_x, hiz_tile_mask_y,
+ false);
/* Each HiZ row represents 2 rows of pixels
Mesa (master): intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset.
Module: Mesa Branch: master Commit: b760c9913dcff848a2aa0e60abeb48e596ae8fee URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b760c9913dcff848a2aa0e60abeb48e596ae8fee Author: Paul Berry stereotype...@gmail.com Date: Thu Aug 30 11:16:44 2012 -0700 intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset. This patch modifies intel_region_get_aligned_offset() to make the appropriate calculation when the blorp engine sets up a W-tiled stencil buffer using a Y-tiled SURFACE_STATE. NOTE: This is a candidate for stable release branches. Acked-by: Eric Anholt e...@anholt.net --- src/mesa/drivers/dri/i965/brw_blorp.cpp |3 ++- src/mesa/drivers/dri/i965/brw_misc_state.c |5 +++-- src/mesa/drivers/dri/i965/gen6_blorp.cpp|4 ++-- src/mesa/drivers/dri/i965/gen7_blorp.cpp|4 ++-- src/mesa/drivers/dri/i965/gen7_misc_state.c |6 -- src/mesa/drivers/dri/intel/intel_fbo.c |2 +- src/mesa/drivers/dri/intel/intel_regions.c | 18 -- src/mesa/drivers/dri/intel/intel_regions.h |2 +- 8 files changed, 31 insertions(+), 13 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index 7e45191..fa7fee7 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -129,7 +129,8 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x, *tile_y = y_offset mask_y; return intel_region_get_aligned_offset(region, x_offset ~mask_x, - y_offset ~mask_y); + y_offset ~mask_y, + map_stencil_as_y_tiled); } diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 52926fb..6dfa08e 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -474,7 +474,7 @@ static void emit_depthbuffer(struct brw_context *brw) offset = intel_region_get_aligned_offset(region, draw_x ~tile_mask_x, - draw_y ~tile_mask_y); + draw_y ~tile_mask_y, false); BEGIN_BATCH(len); OUT_BATCH(_3DSTATE_DEPTH_BUFFER 16 | (len - 2)); @@ -518,7 +518,8 @@ static void emit_depthbuffer(struct brw_context *brw) uint32_t hiz_offset = intel_region_get_aligned_offset(hiz_region, draw_x ~tile_mask_x, -(draw_y ~tile_mask_y) / 2); +(draw_y ~tile_mask_y) / 2, +false); BEGIN_BATCH(3); OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER 16) | (3 - 2)); diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index 3e0b80e..1f536bf 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -843,7 +843,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw, uint32_t offset = intel_region_get_aligned_offset(params-depth.mt-region, draw_x ~tile_mask_x, - draw_y ~tile_mask_y); + draw_y ~tile_mask_y, false); /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for Depth @@ -896,7 +896,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw, uint32_t hiz_offset = intel_region_get_aligned_offset(hiz_region, draw_x ~tile_mask_x, - (draw_y ~tile_mask_y) / 2); + (draw_y ~tile_mask_y) / 2, false); BEGIN_BATCH(3); OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER 16) | (3 - 2)); diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 00f13a5..abe 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -591,7 +591,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw, uint32_t offset = intel_region_get_aligned_offset(params-depth.mt-region, draw_x ~tile_mask_x, - draw_y ~tile_mask_y); + draw_y ~tile_mask_y, false); /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for Depth @@ -640,7 +640,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw, uint32_t hiz_offset
Mesa (master): i965/blorp: don' t reduce stencil alignment restrictions when multisampling.
Module: Mesa
Branch: master
Commit: 1a75063d5f829547b75b60ae64bddf3905b4cb8f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a75063d5f829547b75b60ae64bddf3905b4cb8f
Author: Paul Berry stereotype...@gmail.com
Date: Wed Aug 29 15:11:49 2012 -0700
i965/blorp: don't reduce stencil alignment restrictions when multisampling.
When blitting to a stencil buffer, we need to align the rectangle we
send down the rendering pipeline, to account for the fact that the
stencil buffer uses a W-tiled layout, but we are configuring its
surface state as Y-tiled.
Previously, when the stencil buffer was multisampled, we assumed that
we could reduce the amount of alignment that was necessary, since each
pixel occupies a block of 2x2 or 4x2 samples in the stencil buffer.
That would have been correct if the coordinates we were adjusting were
measured in pixels. However, the conversion from pixel coordinates to
coordinates within the interleaved buffer has already been done;
therefore the full alignment restriction applies.
Note: the reason this mistake wasn't previously uncovered by piglit
tests is because it is being masked by another mistake: the blorp
engine is using overly conservative alignment restrictions when doing
stencil blits. The overly conservative alignment restrictions will be
removed in the patch that follows. Doing this fix now will prevent
the subsequent patch from introducing regressions.
NOTE: This is a candidate for stable release branches.
Acked-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 10 +-
1 files changed, 1 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index ede78cc..67274dc 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1785,18 +1785,10 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
* differences between W and Y tiling formats will mean that pixels are
* scrambled within the tile.
*
- * Note: if the destination surface configured to use IMS layout, then
- * the effective tile size we need to align it to is smaller, because
- * each pixel covers a 2x2 or a 4x2 block of samples.
- *
* TODO: what if this makes the coordinates (or the texture size) too
* large?
*/
- unsigned x_align = 64, y_align = 64;
- if (dst_mt-msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
- x_align /= (dst_mt-num_samples == 4 ? 2 : 4);
- y_align /= 2;
- }
+ const unsigned x_align = 64, y_align = 64;
x0 = ROUND_DOWN_TO(x0, x_align) * 2;
y0 = ROUND_DOWN_TO(y0, y_align) / 2;
x1 = ALIGN(x1, x_align) * 2;
___
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Mesa (master): i965/blorp: Reduce alignment restrictions for stencil blits.
Module: Mesa
Branch: master
Commit: 5fd67fac14d7f35c311eb5c671be8d4ae9b2ea37
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5fd67fac14d7f35c311eb5c671be8d4ae9b2ea37
Author: Paul Berry stereotype...@gmail.com
Date: Wed Aug 29 14:26:48 2012 -0700
i965/blorp: Reduce alignment restrictions for stencil blits.
Previously, we aligned all stencil blit operations to multiples of the
size of a tile, since stencil buffers use W-tiling, and blorp has to
approximate this by configuring the 3D pipeline for Y-tiling and
swizzling coordinates.
However, this was unnecessarily conservative; it turns out that the
differences between W-tiling and Y-tiling are confined to 32-byte
sub-tiles within the 4k tiling pattern; the layout of these 32-byte
sub-tiles within the larger 4k tile is the same (8 sub-tiles across by
16 sub-tiles down, in column-major order). Therefore we only need to
align stencil blit operations to multiples of the sub-tile size.
Note: although the performance improvement of this change is probably
quite small, the fact that W-tiling and Y-tiling formats only differ
within 32-byte sub-tiles will be essential in a future patch to ensure
that stencil blits work correctly between parts of the miptree other
than level/layer 0. Making this change provides handy documentation
(and validation) of this fact.
NOTE: This is a candidate for stable release branches.
Acked-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 23 +--
1 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 67274dc..6bf37b8 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1779,16 +1779,27 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
if (dst.map_stencil_as_y_tiled) {
/* We must modify the rectangle we send through the rendering pipeline
* (and the size of the destination surface), to account for the fact
- * that we are mapping it as Y-tiled when it is in fact W-tiled. Y
- * tiles have dimensions 128x32 whereas W tiles have dimensions 64x64.
- * We must also align it to a multiple of the tile size, because the
- * differences between W and Y tiling formats will mean that pixels are
- * scrambled within the tile.
+ * that we are mapping it as Y-tiled when it is in fact W-tiled.
+ *
+ * Both Y tiling and W tiling can be understood as organizations of
+ * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
+ * is different, but the layout of the 32-byte sub-tiles within the 4k
+ * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
+ * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
+ * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
+ *
+ * Therefore, to account for the layout differences within the 32-byte
+ * sub-tiles, we must expand the rectangle so the X coordinates of its
+ * edges are multiples of 8 (the W sub-tile width), and its Y
+ * coordinates of its edges are multiples of 4 (the W sub-tile height).
+ * Then we need to scale the X and Y coordinates of the rectangle to
+ * account for the differences in aspect ratio between the Y and W
+ * sub-tiles.
*
* TODO: what if this makes the coordinates (or the texture size) too
* large?
*/
- const unsigned x_align = 64, y_align = 64;
+ const unsigned x_align = 8, y_align = 4;
x0 = ROUND_DOWN_TO(x0, x_align) * 2;
y0 = ROUND_DOWN_TO(y0, y_align) / 2;
x1 = ALIGN(x1, x_align) * 2;
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Mesa (master): i965/blorp: Fix offsets and width/height for stencil blits.
Module: Mesa
Branch: master
Commit: 1a5d4f7cb2367c7863b28efbd78e9169114baf42
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a5d4f7cb2367c7863b28efbd78e9169114baf42
Author: Paul Berry stereotype...@gmail.com
Date: Thu Aug 30 08:01:54 2012 -0700
i965/blorp: Fix offsets and width/height for stencil blits.
Fixes piglit test framebuffer-blit-levels draw stencil.
NOTE: This is a candidate for stable release branches.
Acked-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 46 +-
1 files changed, 37 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 6bf37b8..656a497 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1778,8 +1778,9 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
if (dst.map_stencil_as_y_tiled) {
/* We must modify the rectangle we send through the rendering pipeline
- * (and the size of the destination surface), to account for the fact
- * that we are mapping it as Y-tiled when it is in fact W-tiled.
+ * (and the size and x/y offset of the destination surface), to account
+ * for the fact that we are mapping it as Y-tiled when it is in fact
+ * W-tiled.
*
* Both Y tiling and W tiling can be understood as organizations of
* 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
@@ -1794,7 +1795,25 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
* coordinates of its edges are multiples of 4 (the W sub-tile height).
* Then we need to scale the X and Y coordinates of the rectangle to
* account for the differences in aspect ratio between the Y and W
- * sub-tiles.
+ * sub-tiles. We need to modify the layer width and height similarly.
+ *
+ * Note: Since the x/y offset of the surface will be applied using the
+ * SURFACE_STATE command packet, it will be invisible to the swizzling
+ * code in the shader; therefore it needs to be in a multiple of the
+ * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
+ * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
+ * buffer), and the miplevel alignment used for stencil buffers is 8
+ * pixels horizontally and either 4 or 8 pixels vertically (see
+ * intel_horizontal_texture_alignment_unit() and
+ * intel_vertical_texture_alignment_unit()).
+ *
+ * Note: Also, since the SURFACE_STATE command packet can only apply
+ * offsets that are multiples of 4 pixels horizontally and 2 pixels
+ * vertically, it is important that the offsets will be multiples of
+ * these sizes after they are converted into Y-tiled coordinates.
+ * Fortunately they will be, since we know from above that the offsets
+ * are a multiple of the 32-byte sub-tile size, and in Y-tiled
+ * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
*
* TODO: what if this makes the coordinates (or the texture size) too
* large?
@@ -1804,19 +1823,28 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
y0 = ROUND_DOWN_TO(y0, y_align) / 2;
x1 = ALIGN(x1, x_align) * 2;
y1 = ALIGN(y1, y_align) / 2;
- dst.width *= 2;
- dst.height /= 2;
+ dst.width = ALIGN(dst.width, x_align) * 2;
+ dst.height = ALIGN(dst.height, y_align) / 2;
+ dst.x_offset *= 2;
+ dst.y_offset /= 2;
wm_prog_key.use_kill = true;
}
if (src.map_stencil_as_y_tiled) {
- /* We must modify the size of the source surface to account for the fact
- * that we are mapping it as Y-tiled when it is in fact W tiled.
+ /* We must modify the size and x/y offset of the source surface to
+ * account for the fact that we are mapping it as Y-tiled when it is in
+ * fact W tiled.
+ *
+ * See the comments above concerning x/y offset alignment for the
+ * destination surface.
*
* TODO: what if this makes the texture size too large?
*/
- src.width *= 2;
- src.height /= 2;
+ const unsigned x_align = 8, y_align = 4;
+ src.width = ALIGN(src.width, x_align) * 2;
+ src.height = ALIGN(src.height, y_align) / 2;
+ src.x_offset *= 2;
+ src.y_offset /= 2;
}
}
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Mesa (master): mesa/msaa: Allow X and Y flips in multisampled blits.
Module: Mesa
Branch: master
Commit: 5d5f0f349135786cdd76b6004f38b12e50d7f8f9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d5f0f349135786cdd76b6004f38b12e50d7f8f9
Author: Paul Berry stereotype...@gmail.com
Date: Wed Sep 5 16:07:16 2012 -0700
mesa/msaa: Allow X and Y flips in multisampled blits.
From the GL 4.3 spec, section 18.3.1 Blitting Pixel Rectangles:
If SAMPLE_BUFFERS for either the read framebuffer or draw
framebuffer is greater than zero, no copy is performed and an
INVALID_OPERATION error is generated if the dimensions of the
source and destination rectangles provided to BlitFramebuffer are
not identical, or if the formats of the read and draw framebuffers
are not identical.
It is not clear from the spec whether dimensions should mean both
sign and magnitude, or just magnitude.
Previously, Mesa interpreted dimensions as meaning both sign and
magnitude, so any multisampled blit that attempted to flip the image
in the X and/or Y direction would fail.
However, Y flips are likely to be commonplace in OpenGL applications
that have been ported from DirectX applications, as a result of the
fact that DirectX and OpenGL differ in their orientation of the Y
axis. Furthermore, at least one commercial driver (nVidia) permits Y
filps, and L4D2 relies on them being permitted. So it seems prudent
for Mesa to permit them.
This patch changes Mesa to allow both X and Y flips, since there is no
language in the spec to indicate that X and Y flips should be treated
differently.
NOTE: This is a candidate for stable release branches.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/main/fbobject.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index 59a5ec3..abc9d83 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -2979,8 +2979,8 @@ _mesa_BlitFramebufferEXT(GLint srcX0, GLint srcY0, GLint
srcX1, GLint srcY1,
/* extra checks for multisample copies... */
if (readFb-Visual.samples 0 || drawFb-Visual.samples 0) {
/* src and dest region sizes must be the same */
- if (srcX1 - srcX0 != dstX1 - dstX0 ||
- srcY1 - srcY0 != dstY1 - dstY0) {
+ if (abs(srcX1 - srcX0) != abs(dstX1 - dstX0) ||
+ abs(srcY1 - srcY0) != abs(dstY1 - dstY0)) {
_mesa_error(ctx, GL_INVALID_OPERATION,
glBlitFramebufferEXT(bad src/dst multisample region sizes));
return;
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Mesa (master): intel: avoid undefined variable warnings in intel_screen.c
Module: Mesa
Branch: master
Commit: 78a34d868d3c8704a57aa2fb934233ca6c880a5f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=78a34d868d3c8704a57aa2fb934233ca6c880a5f
Author: Paul Berry stereotype...@gmail.com
Date: Thu Aug 30 17:22:29 2012 -0700
intel: avoid undefined variable warnings in intel_screen.c
Reviewed-by: Matt Turner matts...@gmail.com
---
src/mesa/drivers/dri/intel/intel_screen.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
index 3470db6..ca6ac34 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -778,11 +778,12 @@ intelCreateContext(gl_api api,
unsigned *error,
void *sharedContextPrivate)
{
- __DRIscreen *sPriv = driContextPriv-driScreenPriv;
- struct intel_screen *intelScreen = sPriv-driverPrivate;
bool success = false;
#ifdef I915
+ __DRIscreen *sPriv = driContextPriv-driScreenPriv;
+ struct intel_screen *intelScreen = sPriv-driverPrivate;
+
if (IS_9XX(intelScreen-deviceID)) {
success = i915CreateContext(api, mesaVis, driContextPriv,
major_version, minor_version, error,
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Mesa (master): mapi: Add shared-glapi-test to .gitignore
Module: Mesa Branch: master Commit: 772ea84b357c8bf10346d02909c75d85110488e8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=772ea84b357c8bf10346d02909c75d85110488e8 Author: Paul Berry stereotype...@gmail.com Date: Thu Aug 30 12:15:29 2012 -0700 mapi: Add shared-glapi-test to .gitignore --- src/mapi/shared-glapi/tests/.gitignore |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/mapi/shared-glapi/tests/.gitignore b/src/mapi/shared-glapi/tests/.gitignore index 6e92e45..b525d7d 100644 --- a/src/mapi/shared-glapi/tests/.gitignore +++ b/src/mapi/shared-glapi/tests/.gitignore @@ -1,2 +1,3 @@ /Makefile /glapi-test +/shared-glapi-test ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/blorp: Fix incorrect indentation.
Module: Mesa Branch: master Commit: e42f16c19222dfbc093972e79bd1f7d23778c77e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e42f16c19222dfbc093972e79bd1f7d23778c77e Author: Paul Berry stereotype...@gmail.com Date: Thu Aug 30 11:03:33 2012 -0700 i965/blorp: Fix incorrect indentation. --- src/mesa/drivers/dri/i965/brw_blorp.h |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h index 8d05543..dbbd508 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.h +++ b/src/mesa/drivers/dri/i965/brw_blorp.h @@ -81,8 +81,8 @@ class brw_blorp_surface_info : public brw_blorp_mip_info public: brw_blorp_surface_info(); -void set(struct brw_context *brw, - struct intel_mipmap_tree *mt, + void set(struct brw_context *brw, +struct intel_mipmap_tree *mt, unsigned int level, unsigned int layer); /* Setting this flag indicates that the buffer's contents are W-tiled ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): meta: remove call to _meta_in_progress(), fix multisample enable/disable
Module: Mesa
Branch: master
Commit: 055093e33fc90705c429e948caefedf0e0fb82af
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=055093e33fc90705c429e948caefedf0e0fb82af
Author: Brian Paul bri...@vmware.com
Date: Thu Aug 30 08:45:13 2012 -0600
meta: remove call to _meta_in_progress(), fix multisample enable/disable
This partially reverts d638da23d2ec2e9c52655b1ea138249e7f8bcccb.
With gallium the meta code is not always built so the call to
_meta_in_progress() was unresolved. Simply special-case the
GL_MULTISAMPLE case in the meta code. There might be other special
cases in the future given all the differences between legacy GL,
core GL, GLES, etc.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=54234
and https://bugs.freedesktop.org/show_bug.cgi?id=54239
v2 (Paul Berry stereotype...@gmail.com): keep _meta_in_progress
function, since it's needed by the i965 driver, but don't call it from
core mesa.
Signed-off-by: Brian Paul bri...@vmware.com
---
src/mesa/drivers/common/meta.c | 33 +++--
src/mesa/main/enable.c |7 +--
2 files changed, 32 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 3a34b1e..4b448fe 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -438,6 +438,35 @@ _mesa_meta_free(struct gl_context *ctx)
/**
+ * This is an alternative to _mesa_set_enable() to handle some special cases.
+ * See comments inside.
+ */
+static void
+meta_set_enable(struct gl_context *ctx, GLenum cap, GLboolean state)
+{
+ switch (cap) {
+ case GL_MULTISAMPLE:
+ /* We need to enable/disable multisample when using GLES but this enum
+ * is not supported there.
+ */
+ if (ctx-Multisample.Enabled == state)
+ return;
+ FLUSH_VERTICES(ctx, _NEW_MULTISAMPLE);
+ ctx-Multisample.Enabled = state;
+ break;
+ default:
+ _mesa_problem(ctx, Unexpected cap in _meta_set_enable());
+ return;
+ }
+
+ if (ctx-Driver.Enable) {
+ ctx-Driver.Enable(ctx, cap, state);
+ }
+}
+
+
+
+/**
* Enter meta state. This is like a light-weight version of glPushAttrib
* but it also resets most GL state back to default values.
*
@@ -755,7 +784,7 @@ _mesa_meta_begin(struct gl_context *ctx, GLbitfield state)
if (state MESA_META_MULTISAMPLE) {
save-MultisampleEnabled = ctx-Multisample.Enabled;
if (ctx-Multisample.Enabled)
- _mesa_set_enable(ctx, GL_MULTISAMPLE, GL_FALSE);
+ meta_set_enable(ctx, GL_MULTISAMPLE, GL_FALSE);
}
/* misc */
@@ -1057,7 +1086,7 @@ _mesa_meta_end(struct gl_context *ctx)
if (state MESA_META_MULTISAMPLE) {
if (ctx-Multisample.Enabled != save-MultisampleEnabled)
- _mesa_set_enable(ctx, GL_MULTISAMPLE, save-MultisampleEnabled);
+ meta_set_enable(ctx, GL_MULTISAMPLE, save-MultisampleEnabled);
}
/* misc */
diff --git a/src/mesa/main/enable.c b/src/mesa/main/enable.c
index b713f5f..14eea53 100644
--- a/src/mesa/main/enable.c
+++ b/src/mesa/main/enable.c
@@ -765,13 +765,8 @@ _mesa_set_enable(struct gl_context *ctx, GLenum cap,
GLboolean state)
/* GL_ARB_multisample */
case GL_MULTISAMPLE_ARB:
- /* Technically speaking, this should not be allowed for OpenGL ES 2.0
- * or 3.0. However, meta really needs it.
- */
- if (!_mesa_meta_in_progress(ctx) !_mesa_is_desktop_gl(ctx)
- ctx-API != API_OPENGLES)
+ if (!_mesa_is_desktop_gl(ctx) ctx-API != API_OPENGLES)
goto invalid_enum_error;
-
if (ctx-Multisample.Enabled == state)
return;
FLUSH_VERTICES(ctx, _NEW_MULTISAMPLE);
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Mesa (master): i965/HiZ: remove assertion from intel_resolve_map_set().
Module: Mesa
Branch: master
Commit: 4b8b6f385e855ecb6da0b7dea56e70e69d1517b9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4b8b6f385e855ecb6da0b7dea56e70e69d1517b9
Author: Paul Berry stereotype...@gmail.com
Date: Wed Aug 22 08:01:58 2012 -0700
i965/HiZ: remove assertion from intel_resolve_map_set().
There are three possible resolve map states for each (level, layer) of
a depth miptree: needs HiZ resolve, needs depth resolve, and
needs neither. When HiZ was first implemented on i965, any attempt
to directly transition between needs HiZ resolve and needs depth
resolve without passing through the needs neither state would have
been a bug indicating that a necessary resolve hadn't been performed.
Accordingly, intel_resolve_map_set() contained an assertion to verify
that no such direct transition happened.
However, now that we support fast depth clears, there is a valid
transition from the needs HiZ resolve to the needs depth resolve
state. When doing a fast depth clear, the old state of the buffer is
irrelevant, since we are completely replacing it with the clear value,
so it is not necessary to do any resolves before clearing--we can
transition, if necessary, directly from the needs HiZ resolve state
to the needs depth resolve state.
To avoid spurious assertions in this valid case, this patch just
removes the assertion.
Reviewed-by: Eric Anholt e...@anholt.net
Reviewed-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_resolve_map.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_resolve_map.c
b/src/mesa/drivers/dri/intel/intel_resolve_map.c
index 471988d..04b5c94 100644
--- a/src/mesa/drivers/dri/intel/intel_resolve_map.c
+++ b/src/mesa/drivers/dri/intel/intel_resolve_map.c
@@ -29,8 +29,8 @@
/**
* \brief Set that the miptree slice at (level, layer) needs a resolve.
*
- * \pre If a map element already exists with the given key, then
- * the new and existing element value must be identical.
+ * If a map element already exists with the given key, then the value is
+ * changed to the given value of \c need.
*/
void
intel_resolve_map_set(struct intel_resolve_map *head,
@@ -43,7 +43,7 @@ intel_resolve_map_set(struct intel_resolve_map *head,
while (*tail) {
if ((*tail)-level == level (*tail)-layer == layer) {
-assert((*tail)-need == need);
+ (*tail)-need = need;
return;
}
prev = *tail;
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Mesa (master): i965: don't clear resolve map when doing fast depth clears.
Module: Mesa Branch: master Commit: 5133bd6585552a5708b294180fa9a561bf7564a6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5133bd6585552a5708b294180fa9a561bf7564a6 Author: Paul Berry stereotype...@gmail.com Date: Wed Aug 22 08:02:39 2012 -0700 i965: don't clear resolve map when doing fast depth clears. Previously, when performing a fast depth clear, we would also clear the miptree's resolve map. This destroyed important information, since the resolve map contains information about needed resolves for all levels and layers of the miptree, whereas a depth clear only applies to a single level/layer combination at a time. As a result, resolves would sometimes fail to occur, leading to incorrect rendering. Fixes rendering artifacts with shadow maps in Unigine Heaven and Unigine Sanctuary. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50270 Reviewed-by: Eric Anholt e...@anholt.net Reviewed-by: Chad Versace chad.vers...@linux.intel.com --- src/mesa/drivers/dri/i965/brw_clear.c |6 ++ 1 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index e56a26a..ce40e52 100644 --- a/src/mesa/drivers/dri/i965/brw_clear.c +++ b/src/mesa/drivers/dri/i965/brw_clear.c @@ -193,11 +193,9 @@ brw_fast_clear_depth(struct gl_context *ctx) intel_batchbuffer_emit_mi_flush(intel); } - /* Now, the entire HiZ buffer contains data that needs to be resolved to the -* entire depth buffer (so any previous resolve records should get tossed -* out). + /* Now, the HiZ buffer contains data that needs to be resolved to the depth +* buffer. */ - intel_resolve_map_clear(mt-hiz_map); intel_renderbuffer_set_needs_depth_resolve(depth_irb); return true; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (8.0): i965/Gen6: Work around GPU hangs due to misaligned depth coordinate offsets.
Module: Mesa
Branch: 8.0
Commit: 24db6d63dab7cc8d3e5d4482b95d58e46113ba44
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=24db6d63dab7cc8d3e5d4482b95d58e46113ba44
Author: Paul Berry stereotype...@gmail.com
Date: Thu Apr 26 06:35:56 2012 -0700
i965/Gen6: Work around GPU hangs due to misaligned depth coordinate offsets.
In i965 Gen6, Mesa has for a long time used the depth coordinate
offset X/Y settings (in 3DSTATE_DEPTH_BUFFER) to cause the GPU to
render to miplevels other than 0. Unfortunately, this doesn't work,
because these offsets must be aligned to multiples of 8, and miplevels
in the depth buffer are only guaranteed to be aligned to multiples of
4. When the offsets aren't aligned to a multiple of 8, the GPU
sometimes hangs.
As a temporary measure, to avoid GPU hangs, this patch smashes the 3
LSB's of depth coordinate offset X/Y to 0. This results in
incorrect rendering to mipmapped depth textures, but that seems like a
reasonable stopgap while we figure out a better solution.
(Note that we have only ever observed this GPU hang on Gen6 when HiZ
is enabled, so another possible stopgap would be to disable HiZ).
Avoids GPU hangs in piglit test depthstencil-render-miplevels at
texture sizes that are not powers of 2.
Reviewed-by: Chad Verace chad.vers...@linux.intel.com
Cherry-picked from a683012a80a3408b3b71f22b2a97d9eaaac11a46
Conflicts:
src/mesa/drivers/dri/i965/brw_misc_state.c
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50271
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 18 ++
src/mesa/drivers/dri/i965/gen6_hiz.c | 18 ++
2 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index efe2f0f..d2c9246 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -378,6 +378,24 @@ static void emit_depthbuffer(struct brw_context *brw)
assert(intel-gen 6 || region-tiling == I915_TILING_Y);
assert(!hiz_region || region-tiling == I915_TILING_Y);
+ /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
+ * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for Depth
+ * Coordinate Offset X/Y:
+ *
+ * The 3 LSBs of both offsets must be zero to ensure correct
+ * alignment
+ *
+ * We have no guarantee that tile_x and tile_y are correctly aligned,
+ * since they are determined by the mipmap layout, which is only aligned
+ * to multiples of 4.
+ *
+ * So, to avoid hanging the GPU, just smash the low order 3 bits of
+ * tile_x and tile_y to 0. This is a temporary workaround until we come
+ * up with a better solution.
+ */
+ tile_x = ~7;
+ tile_y = ~7;
+
BEGIN_BATCH(len);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER 16 | (len - 2));
OUT_BATCH(((region-pitch * region-cpp) - 1) |
diff --git a/src/mesa/drivers/dri/i965/gen6_hiz.c
b/src/mesa/drivers/dri/i965/gen6_hiz.c
index a86c147..92cf1d4 100644
--- a/src/mesa/drivers/dri/i965/gen6_hiz.c
+++ b/src/mesa/drivers/dri/i965/gen6_hiz.c
@@ -489,6 +489,24 @@ gen6_hiz_exec(struct intel_context *intel,
offset = intel_renderbuffer_tile_offsets(rb, tile_x, tile_y);
}
+ /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
+ * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for Depth
+ * Coordinate Offset X/Y:
+ *
+ * The 3 LSBs of both offsets must be zero to ensure correct
+ * alignment
+ *
+ * We have no guarantee that tile_x and tile_y are correctly aligned,
+ * since they are determined by the mipmap layout, which is only aligned
+ * to multiples of 4.
+ *
+ * So, to avoid hanging the GPU, just smash the low order 3 bits of
+ * tile_x and tile_y to 0. This is a temporary workaround until we come
+ * up with a better solution.
+ */
+ tile_x = ~7;
+ tile_y = ~7;
+
uint32_t format;
switch (mt-format) {
case MESA_FORMAT_Z16: format = BRW_DEPTHFORMAT_D16_UNORM; break;
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Mesa (8.0): i965/Gen7: Work around GPU hangs due to misaligned depth coordinate offsets.
Module: Mesa Branch: 8.0 Commit: 889cc4d9225084e15b9e8d010e30b31a87dbfd2d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=889cc4d9225084e15b9e8d010e30b31a87dbfd2d Author: Paul Berry stereotype...@gmail.com Date: Thu Apr 26 06:35:56 2012 -0700 i965/Gen7: Work around GPU hangs due to misaligned depth coordinate offsets. In i965 Gen7, Mesa has for a long time used the depth coordinate offset X/Y settings (in 3DSTATE_DEPTH_BUFFER) to cause the GPU to render to miplevels other than 0. Unfortunately, this doesn't work, because these offsets must be aligned to multiples of 8, and miplevels in the depth buffer are only guaranteed to be aligned to multiples of 4. When the offsets aren't aligned to a multiple of 8, the GPU sometimes hangs. As a temporary measure, to avoid GPU hangs, this patch smashes the 3 LSB's of depth coordinate offset X/Y to 0. This results in incorrect rendering to mipmapped depth textures, but that seems like a reasonable stopgap while we figure out a better solution. Avoids GPU hangs in piglit test depthstencil-render-miplevels at texture sizes that are not powers of 2. Reviewed-by: Chad Verace chad.vers...@linux.intel.com Cherry-picked from 714b4f6184db84a738cf2d063980f0e19ab03b4b Conflicts: src/mesa/drivers/dri/i965/gen7_misc_state.c Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50271 --- src/mesa/drivers/dri/i965/gen7_hiz.c| 18 ++ src/mesa/drivers/dri/i965/gen7_misc_state.c | 18 ++ 2 files changed, 36 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_hiz.c b/src/mesa/drivers/dri/i965/gen7_hiz.c index 34e51ab..962079e 100644 --- a/src/mesa/drivers/dri/i965/gen7_hiz.c +++ b/src/mesa/drivers/dri/i965/gen7_hiz.c @@ -349,6 +349,24 @@ gen7_hiz_exec(struct intel_context *intel, offset = intel_renderbuffer_tile_offsets(rb, tile_x, tile_y); } + /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327 + * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for Depth + * Coordinate Offset X/Y: + * + * The 3 LSBs of both offsets must be zero to ensure correct + * alignment + * + * We have no guarantee that tile_x and tile_y are correctly aligned, + * since they are determined by the mipmap layout, which is only aligned + * to multiples of 4. + * + * So, to avoid hanging the GPU, just smash the low order 3 bits of + * tile_x and tile_y to 0. This is a temporary workaround until we come + * up with a better solution. + */ + tile_x = ~7; + tile_y = ~7; + intel_emit_depth_stall_flushes(intel); BEGIN_BATCH(7); diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c index d0ce542..870702f 100644 --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c @@ -93,6 +93,24 @@ static void emit_depthbuffer(struct brw_context *brw) offset = intel_renderbuffer_tile_offsets(drb, tile_x, tile_y); + /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327 + * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for Depth + * Coordinate Offset X/Y: + * + * The 3 LSBs of both offsets must be zero to ensure correct + * alignment + * + * We have no guarantee that tile_x and tile_y are correctly aligned, + * since they are determined by the mipmap layout, which is only aligned + * to multiples of 4. + * + * So, to avoid hanging the GPU, just smash the low order 3 bits of + * tile_x and tile_y to 0. This is a temporary workaround until we come + * up with a better solution. + */ + tile_x = ~7; + tile_y = ~7; + assert(region-tiling == I915_TILING_Y); /* _NEW_DEPTH, _NEW_STENCIL */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (gles3): egl_dri2: Remove swrast version = 2 checks
Module: Mesa
Branch: gles3
Commit: 0d0af45bb6f2eb3f07e63e89e940d101e88817dc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d0af45bb6f2eb3f07e63e89e940d101e88817dc
Author: Ian Romanick ian.d.roman...@intel.com
Date: Wed Jul 18 10:08:49 2012 -0700
egl_dri2: Remove swrast version = 2 checks
Since support for swrast version 2 was added (f55d027a), it has also been
required. In swrast_driver_extensions, version 2 is set for __DRI_SWRAST
extension. Remove the spurious version checks sprinked through the code.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
---
src/egl/drivers/dri2/egl_dri2.c | 38 +++---
1 files changed, 11 insertions(+), 27 deletions(-)
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index f86ed0b..480268f 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -470,10 +470,7 @@ dri2_setup_screen(_EGLDisplay *disp)
api_mask = 1 __DRI_API_OPENGL;
} else {
assert(dri2_dpy-swrast);
- if (dri2_dpy-swrast-base.version = 2)
- api_mask = 1 __DRI_API_OPENGL | 1 __DRI_API_GLES | 1
__DRI_API_GLES2;
- else
- api_mask = 1 __DRI_API_OPENGL;
+ api_mask = 1 __DRI_API_OPENGL | 1 __DRI_API_GLES | 1
__DRI_API_GLES2;
}
disp-ClientAPIs = 0;
@@ -492,11 +489,9 @@ dri2_setup_screen(_EGLDisplay *disp)
}
} else {
assert(dri2_dpy-swrast);
- if (dri2_dpy-swrast-base.version = 2) {
- disp-Extensions.KHR_surfaceless_gles1 = EGL_TRUE;
- disp-Extensions.KHR_surfaceless_gles2 = EGL_TRUE;
- disp-Extensions.KHR_surfaceless_opengl = EGL_TRUE;
- }
+ disp-Extensions.KHR_surfaceless_gles1 = EGL_TRUE;
+ disp-Extensions.KHR_surfaceless_gles2 = EGL_TRUE;
+ disp-Extensions.KHR_surfaceless_opengl = EGL_TRUE;
}
if (dri2_dpy-image) {
@@ -733,24 +728,13 @@ dri2_create_context(_EGLDriver *drv, _EGLDisplay *disp,
_EGLConfig *conf,
}
} else {
assert(dri2_dpy-swrast);
- if (dri2_dpy-swrast-base.version = 2) {
-dri2_ctx-dri_context =
- dri2_dpy-swrast-createNewContextForAPI(dri2_dpy-dri_screen,
-api,
-dri_config,
-dri2_ctx_shared ?
-
dri2_ctx_shared-dri_context : NULL,
-dri2_ctx);
- } else if (api == __DRI_API_OPENGL) {
-dri2_ctx-dri_context =
- dri2_dpy-core-createNewContext(dri2_dpy-dri_screen,
-dri_config,
-dri2_ctx_shared ?
-dri2_ctx_shared-dri_context :
NULL,
-dri2_ctx);
- } else {
-/* fail */
- }
+ dri2_ctx-dri_context =
+ dri2_dpy-swrast-createNewContextForAPI(dri2_dpy-dri_screen,
+ api,
+ dri_config,
+ dri2_ctx_shared ?
+ dri2_ctx_shared-dri_context
: NULL,
+ dri2_ctx);
}
if (!dri2_ctx-dri_context)
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Mesa (gles3): egl_dri2: Require DRI2 version 2
Module: Mesa
Branch: gles3
Commit: 3067c56990d0d6935ef19572c26f4c79f5c7a88b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3067c56990d0d6935ef19572c26f4c79f5c7a88b
Author: Ian Romanick ian.d.roman...@intel.com
Date: Wed Jul 18 13:17:50 2012 -0700
egl_dri2: Require DRI2 version 2
The extra block in dri2_create_context is to prevent extra white space noise
in the next patch.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
---
src/egl/drivers/dri2/egl_dri2.c | 33 +++--
1 files changed, 7 insertions(+), 26 deletions(-)
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 90956a1..65fc088 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -308,7 +308,7 @@ struct dri2_extension_match {
static struct dri2_extension_match dri2_driver_extensions[] = {
{ __DRI_CORE, 1, offsetof(struct dri2_egl_display, core) },
- { __DRI_DRI2, 1, offsetof(struct dri2_egl_display, dri2) },
+ { __DRI_DRI2, 2, offsetof(struct dri2_egl_display, dri2) },
{ NULL, 0, 0 }
};
@@ -464,10 +464,7 @@ dri2_setup_screen(_EGLDisplay *disp)
unsigned int api_mask;
if (dri2_dpy-dri2) {
- if (dri2_dpy-dri2-base.version = 2)
- api_mask = dri2_dpy-dri2-getAPIMask(dri2_dpy-dri_screen);
- else
- api_mask = 1 __DRI_API_OPENGL;
+ api_mask = dri2_dpy-dri2-getAPIMask(dri2_dpy-dri_screen);
} else {
assert(dri2_dpy-swrast);
api_mask = 1 __DRI_API_OPENGL | 1 __DRI_API_GLES | 1
__DRI_API_GLES2;
@@ -481,18 +478,10 @@ dri2_setup_screen(_EGLDisplay *disp)
if (api_mask (1 __DRI_API_GLES2))
disp-ClientAPIs |= EGL_OPENGL_ES2_BIT;
- if (dri2_dpy-dri2) {
- if (dri2_dpy-dri2-base.version = 2) {
- disp-Extensions.KHR_surfaceless_gles1 = EGL_TRUE;
- disp-Extensions.KHR_surfaceless_gles2 = EGL_TRUE;
- disp-Extensions.KHR_surfaceless_opengl = EGL_TRUE;
- }
- } else {
- assert(dri2_dpy-swrast);
- disp-Extensions.KHR_surfaceless_gles1 = EGL_TRUE;
- disp-Extensions.KHR_surfaceless_gles2 = EGL_TRUE;
- disp-Extensions.KHR_surfaceless_opengl = EGL_TRUE;
- }
+ assert(dri2_dpy-dri2 || dri2_dpy-swrast);
+ disp-Extensions.KHR_surfaceless_gles1 = EGL_TRUE;
+ disp-Extensions.KHR_surfaceless_gles2 = EGL_TRUE;
+ disp-Extensions.KHR_surfaceless_opengl = EGL_TRUE;
if (dri2_dpy-image) {
disp-Extensions.MESA_drm_image = EGL_TRUE;
@@ -710,21 +699,13 @@ dri2_create_context(_EGLDriver *drv, _EGLDisplay *disp,
_EGLConfig *conf,
dri_config = NULL;
if (dri2_dpy-dri2) {
- if (dri2_dpy-dri2-base.version = 2) {
+ {
dri2_ctx-dri_context =
dri2_dpy-dri2-createNewContextForAPI(dri2_dpy-dri_screen,
api,
dri_config,
shared,
dri2_ctx);
- } else if (api == __DRI_API_OPENGL) {
-dri2_ctx-dri_context =
- dri2_dpy-dri2-createNewContext(dri2_dpy-dri_screen,
-dri_config,
- shared,
-dri2_ctx);
- } else {
-/* fail */
}
} else {
assert(dri2_dpy-swrast);
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Mesa (gles3): egl_dri2: Refactor dereference of dri2_ctx_shared
Module: Mesa
Branch: gles3
Commit: 592cab75f5a849f478eeedf230d7f97b62886219
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=592cab75f5a849f478eeedf230d7f97b62886219
Author: Ian Romanick ian.d.roman...@intel.com
Date: Wed Jul 18 14:37:28 2012 -0700
egl_dri2: Refactor dereference of dri2_ctx_shared
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
---
src/egl/drivers/dri2/egl_dri2.c | 11 +--
1 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 480268f..90956a1 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -648,6 +648,8 @@ dri2_create_context(_EGLDriver *drv, _EGLDisplay *disp,
_EGLConfig *conf,
struct dri2_egl_context *dri2_ctx;
struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
struct dri2_egl_context *dri2_ctx_shared = dri2_egl_context(share_list);
+ __DRIcontext *const shared =
+ dri2_ctx_shared ? dri2_ctx_shared-dri_context : NULL;
struct dri2_egl_config *dri2_config = dri2_egl_config(conf);
const __DRIconfig *dri_config;
int api;
@@ -713,15 +715,13 @@ dri2_create_context(_EGLDriver *drv, _EGLDisplay *disp,
_EGLConfig *conf,
dri2_dpy-dri2-createNewContextForAPI(dri2_dpy-dri_screen,
api,
dri_config,
- dri2_ctx_shared ?
- dri2_ctx_shared-dri_context
: NULL,
+ shared,
dri2_ctx);
} else if (api == __DRI_API_OPENGL) {
dri2_ctx-dri_context =
dri2_dpy-dri2-createNewContext(dri2_dpy-dri_screen,
dri_config,
-dri2_ctx_shared ?
-dri2_ctx_shared-dri_context :
NULL,
+ shared,
dri2_ctx);
} else {
/* fail */
@@ -732,8 +732,7 @@ dri2_create_context(_EGLDriver *drv, _EGLDisplay *disp,
_EGLConfig *conf,
dri2_dpy-swrast-createNewContextForAPI(dri2_dpy-dri_screen,
api,
dri_config,
- dri2_ctx_shared ?
- dri2_ctx_shared-dri_context
: NULL,
+ shared,
dri2_ctx);
}
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Mesa (gles3): egl_dri2: Use createContextAttribs if DRI2 version = 3
Module: Mesa
Branch: gles3
Commit: 74844c6cbe6242ce58963186dbf0e805fc8cafbd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=74844c6cbe6242ce58963186dbf0e805fc8cafbd
Author: Ian Romanick ian.d.roman...@intel.com
Date: Wed Jul 18 14:41:28 2012 -0700
egl_dri2: Use createContextAttribs if DRI2 version = 3
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
---
src/egl/drivers/dri2/egl_dri2.c | 18 +-
1 files changed, 17 insertions(+), 1 deletions(-)
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 65fc088..cde4d4f 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -699,7 +699,23 @@ dri2_create_context(_EGLDriver *drv, _EGLDisplay *disp,
_EGLConfig *conf,
dri_config = NULL;
if (dri2_dpy-dri2) {
- {
+ if (dri2_dpy-dri2-base.version = 3) {
+ unsigned error;
+ const uint32_t ctx_attribs[2] = {
+__DRI_CTX_ATTRIB_MAJOR_VERSION,
+dri2_ctx-base.ClientVersion
+ };
+
+dri2_ctx-dri_context =
+ dri2_dpy-dri2-createContextAttribs(dri2_dpy-dri_screen,
+ api,
+ dri_config,
+ shared,
+ 1,
+ ctx_attribs,
+ error,
+ dri2_ctx);
+ } else {
dri2_ctx-dri_context =
dri2_dpy-dri2-createNewContextForAPI(dri2_dpy-dri_screen,
api,
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Mesa (gles3): egl: Rename ClientVersion to ClientMajorVersion, add ClientMinorVersion
Module: Mesa
Branch: gles3
Commit: 83fcc669aa6afaa7ad053ab31e4c6c60ab8c44e9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=83fcc669aa6afaa7ad053ab31e4c6c60ab8c44e9
Author: Ian Romanick ian.d.roman...@intel.com
Date: Wed Jul 18 15:59:15 2012 -0700
egl: Rename ClientVersion to ClientMajorVersion, add ClientMinorVersion
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
---
src/egl/drivers/dri2/egl_dri2.c |4 ++--
src/egl/main/eglcontext.c |9 +
src/egl/main/eglcontext.h |3 ++-
3 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index cde4d4f..a73f163 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -656,7 +656,7 @@ dri2_create_context(_EGLDriver *drv, _EGLDisplay *disp,
_EGLConfig *conf,
switch (dri2_ctx-base.ClientAPI) {
case EGL_OPENGL_ES_API:
- switch (dri2_ctx-base.ClientVersion) {
+ switch (dri2_ctx-base.ClientMajorVersion) {
case 1:
api = __DRI_API_GLES;
break;
@@ -703,7 +703,7 @@ dri2_create_context(_EGLDriver *drv, _EGLDisplay *disp,
_EGLConfig *conf,
unsigned error;
const uint32_t ctx_attribs[2] = {
__DRI_CTX_ATTRIB_MAJOR_VERSION,
-dri2_ctx-base.ClientVersion
+dri2_ctx-base.ClientMajorVersion
};
dri2_ctx-dri_context =
diff --git a/src/egl/main/eglcontext.c b/src/egl/main/eglcontext.c
index 17cb037..5595baf 100644
--- a/src/egl/main/eglcontext.c
+++ b/src/egl/main/eglcontext.c
@@ -49,7 +49,7 @@ _eglGetContextAPIBit(_EGLContext *ctx)
switch (ctx-ClientAPI) {
case EGL_OPENGL_ES_API:
- switch (ctx-ClientVersion) {
+ switch (ctx-ClientMajorVersion) {
case 1:
bit = EGL_OPENGL_ES_BIT;
break;
@@ -100,7 +100,7 @@ _eglParseContextAttribList(_EGLContext *ctx, const EGLint
*attrib_list)
err = EGL_BAD_ATTRIBUTE;
break;
}
- ctx-ClientVersion = val;
+ ctx-ClientMajorVersion = val;
break;
default:
err = EGL_BAD_ATTRIBUTE;
@@ -138,7 +138,8 @@ _eglInitContext(_EGLContext *ctx, _EGLDisplay *dpy,
_EGLConfig *conf,
ctx-Config = conf;
ctx-WindowRenderBuffer = EGL_NONE;
- ctx-ClientVersion = 1; /* the default, per EGL spec */
+ ctx-ClientMajorVersion = 1; /* the default, per EGL spec */
+ ctx-ClientMinorVersion = 0;
err = _eglParseContextAttribList(ctx, attrib_list);
if (err == EGL_SUCCESS ctx-Config) {
@@ -191,7 +192,7 @@ _eglQueryContext(_EGLDriver *drv, _EGLDisplay *dpy,
_EGLContext *c,
*value = c-Config-ConfigID;
break;
case EGL_CONTEXT_CLIENT_VERSION:
- *value = c-ClientVersion;
+ *value = c-ClientMajorVersion;
break;
case EGL_CONTEXT_CLIENT_TYPE:
*value = c-ClientAPI;
diff --git a/src/egl/main/eglcontext.h b/src/egl/main/eglcontext.h
index 0ac8462..5e86cec 100644
--- a/src/egl/main/eglcontext.h
+++ b/src/egl/main/eglcontext.h
@@ -52,7 +52,8 @@ struct _egl_context
_EGLConfig *Config;
EGLint ClientAPI; /** EGL_OPENGL_ES_API, EGL_OPENGL_API, EGL_OPENVG_API */
- EGLint ClientVersion; /** 1 = OpenGLES 1.x, 2 = OpenGLES 2.x */
+ EGLint ClientMajorVersion;
+ EGLint ClientMinorVersion;
/* The real render buffer when a window surface is bound */
EGLint WindowRenderBuffer;
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Mesa (gles3): egl: Import eglext.h version 13
Module: Mesa
Branch: gles3
Commit: ae546207303993a13931a0c60a398cf4fb5caa11
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae546207303993a13931a0c60a398cf4fb5caa11
Author: Ian Romanick ian.d.roman...@intel.com
Date: Thu Jul 19 10:59:49 2012 -0700
egl: Import eglext.h version 13
This is necessary for EGL_KHR_create_context work.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
---
include/EGL/eglext.h | 137 -
1 files changed, 123 insertions(+), 14 deletions(-)
diff --git a/include/EGL/eglext.h b/include/EGL/eglext.h
index a7ea2ea..c38b72d 100644
--- a/include/EGL/eglext.h
+++ b/include/EGL/eglext.h
@@ -6,7 +6,7 @@ extern C {
#endif
/*
-** Copyright (c) 2007-2010 The Khronos Group Inc.
+** Copyright (c) 2007-2012 The Khronos Group Inc.
**
** Permission is hereby granted, free of charge, to any person obtaining a
** copy of this software and/or associated documentation files (the
@@ -34,8 +34,8 @@ extern C {
/* Header file version number */
/* Current version at http://www.khronos.org/registry/egl/ */
-/* $Revision: 15052 $ on $Date: 2011-07-06 17:43:46 -0700 (Wed, 06 Jul 2011) $
*/
-#define EGL_EGLEXT_VERSION 10
+/* $Revision: 18175 $ on $Date: 2012-06-13 11:26:12 -0700 (Wed, 13 Jun 2012) $
*/
+#define EGL_EGLEXT_VERSION 13
#ifndef EGL_KHR_config_attribs
#define EGL_KHR_config_attribs 1
@@ -178,15 +178,15 @@ typedef EGLBoolean (EGLAPIENTRYP
PFNEGLGETSYNCATTRIBKHRPROC) (EGLDisplay dpy, EG
#ifndef EGL_NV_coverage_sample
#define EGL_NV_coverage_sample 1
-#define EGL_COVERAGE_BUFFERS_NV 0x30E0
-#define EGL_COVERAGE_SAMPLES_NV 0x30E1
+#define EGL_COVERAGE_BUFFERS_NV0x30E0
+#define EGL_COVERAGE_SAMPLES_NV0x30E1
#endif
#ifndef EGL_NV_depth_nonlinear
#define EGL_NV_depth_nonlinear 1
-#define EGL_DEPTH_ENCODING_NV 0x30E2
+#define EGL_DEPTH_ENCODING_NV 0x30E2
#define EGL_DEPTH_ENCODING_NONE_NV 0
-#define EGL_DEPTH_ENCODING_NONLINEAR_NV 0x30E3
+#define EGL_DEPTH_ENCODING_NONLINEAR_NV0x30E3
#endif
#if KHRONOS_SUPPORT_INT64 /* EGLTimeNV requires 64-bit uint support */
@@ -208,12 +208,12 @@ typedef EGLBoolean (EGLAPIENTRYP
PFNEGLGETSYNCATTRIBKHRPROC) (EGLDisplay dpy, EG
typedef void* EGLSyncNV;
typedef khronos_utime_nanoseconds_t EGLTimeNV;
#ifdef EGL_EGLEXT_PROTOTYPES
-EGLSyncNV eglCreateFenceSyncNV (EGLDisplay dpy, EGLenum condition, const
EGLint *attrib_list);
-EGLBoolean eglDestroySyncNV (EGLSyncNV sync);
-EGLBoolean eglFenceNV (EGLSyncNV sync);
-EGLint eglClientWaitSyncNV (EGLSyncNV sync, EGLint flags, EGLTimeNV timeout);
-EGLBoolean eglSignalSyncNV (EGLSyncNV sync, EGLenum mode);
-EGLBoolean eglGetSyncAttribNV (EGLSyncNV sync, EGLint attribute, EGLint
*value);
+EGLAPI EGLSyncNV EGLAPIENTRY eglCreateFenceSyncNV (EGLDisplay dpy, EGLenum
condition, const EGLint *attrib_list);
+EGLAPI EGLBoolean EGLAPIENTRY eglDestroySyncNV (EGLSyncNV sync);
+EGLAPI EGLBoolean EGLAPIENTRY eglFenceNV (EGLSyncNV sync);
+EGLAPI EGLint EGLAPIENTRY eglClientWaitSyncNV (EGLSyncNV sync, EGLint flags,
EGLTimeNV timeout);
+EGLAPI EGLBoolean EGLAPIENTRY eglSignalSyncNV (EGLSyncNV sync, EGLenum mode);
+EGLAPI EGLBoolean EGLAPIENTRY eglGetSyncAttribNV (EGLSyncNV sync, EGLint
attribute, EGLint *value);
#endif /* EGL_EGLEXT_PROTOTYPES */
typedef EGLSyncNV (EGLAPIENTRYP PFNEGLCREATEFENCESYNCNVPROC) (EGLDisplay dpy,
EGLenum condition, const EGLint *attrib_list);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLDESTROYSYNCNVPROC) (EGLSyncNV sync);
@@ -313,7 +313,7 @@ typedef EGLBoolean (EGLAPIENTRYP
PFNEGLQUERYSURFACEPOINTERANGLEPROC) (EGLDisplay
#define EGL_COVERAGE_SAMPLE_RESOLVE_NONE_NV0x3133
#endif
-#if KHRONOS_SUPPORT_INT64 /* EGLTimeKHR requires 64-bit uint support */
+#if KHRONOS_SUPPORT_INT64 /* EGLuint64NV requires 64-bit uint support */
#ifndef EGL_NV_system_time
#define EGL_NV_system_time 1
@@ -328,6 +328,115 @@ typedef EGLuint64NV (EGLAPIENTRYP
PFNEGLGETSYSTEMTIMENVPROC) (void);
#endif
#endif
+#if KHRONOS_SUPPORT_INT64 /* EGLuint64KHR requires 64-bit uint support */
+#ifndef EGL_KHR_stream
+#define EGL_KHR_stream 1
+typedef void* EGLStreamKHR;
+typedef khronos_uint64_t EGLuint64KHR;
+#define EGL_NO_STREAM_KHR ((EGLStreamKHR)0)
+#define EGL_CONSUMER_LATENCY_USEC_KHR 0x3210
+#define EGL_PRODUCER_FRAME_KHR 0x3212
+#define EGL_CONSUMER_FRAME_KHR 0x3213
+#define EGL_STREAM_STATE_KHR 0x3214
+#define EGL_STREAM_STATE_CREATED_KHR 0x3215
+#define EGL_STREAM_STATE_CONNECTING_KHR0x3216
+#define EGL_STREAM_STATE_EMPTY_KHR 0x3217
+#define EGL_STREAM_STATE_NEW_FRAME_AVAILABLE_KHR0x3218
+#define EGL_STREAM_STATE_OLD_FRAME_AVAILABLE_KHR0x3219
+#define EGL_STREAM_STATE_DISCONNECTED_KHR 0x321A
+#define EGL_BAD_STREAM_KHR 0x321B
+#define EGL_BAD_STATE_KHR
Mesa (gles3): egl_dri2: Silence warnings about missing initializers
Module: Mesa
Branch: gles3
Commit: 27913f38745165ec014f4d937a47040df412aa54
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=27913f38745165ec014f4d937a47040df412aa54
Author: Ian Romanick ian.d.roman...@intel.com
Date: Thu Jul 19 11:08:02 2012 -0700
egl_dri2: Silence warnings about missing initializers
egl_dri2.c: At top level:
egl_dri2.c:325:4: warning: missing initializer [-Wmissing-field-initializers]
egl_dri2.c:325:4: warning: (near initialization for
'swrast_driver_extensions[2].version') [-Wmissing-field-initializers]
egl_dri2.c:330:4: warning: missing initializer [-Wmissing-field-initializers]
egl_dri2.c:330:4: warning: (near initialization for
'swrast_core_extensions[1].version') [-Wmissing-field-initializers]
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
---
src/egl/drivers/dri2/egl_dri2.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index a73f163..a2f9a8b 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -322,12 +322,12 @@ static struct dri2_extension_match dri2_core_extensions[]
= {
static struct dri2_extension_match swrast_driver_extensions[] = {
{ __DRI_CORE, 1, offsetof(struct dri2_egl_display, core) },
{ __DRI_SWRAST, 2, offsetof(struct dri2_egl_display, swrast) },
- { NULL }
+ { NULL, 0, 0 }
};
static struct dri2_extension_match swrast_core_extensions[] = {
{ __DRI_TEX_BUFFER, 2, offsetof(struct dri2_egl_display, tex_buffer) },
- { NULL }
+ { NULL, 0, 0 }
};
static EGLBoolean
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Mesa (gles3): egl: Implement front-end support for EGL_KHR_create_context
Module: Mesa
Branch: gles3
Commit: bf6da1fd5b2e52bf46098d7e9ad0e2dcd60bc0d6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf6da1fd5b2e52bf46098d7e9ad0e2dcd60bc0d6
Author: Ian Romanick ian.d.roman...@intel.com
Date: Thu Jul 19 11:10:15 2012 -0700
egl: Implement front-end support for EGL_KHR_create_context
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
---
src/egl/main/eglcontext.c | 217 +++-
src/egl/main/eglcontext.h |3 +
src/egl/main/egldisplay.h |1 +
src/egl/main/eglmisc.c|1 +
4 files changed, 217 insertions(+), 5 deletions(-)
diff --git a/src/egl/main/eglcontext.c b/src/egl/main/eglcontext.c
index 5595baf..f0620aa 100644
--- a/src/egl/main/eglcontext.c
+++ b/src/egl/main/eglcontext.c
@@ -78,7 +78,8 @@ _eglGetContextAPIBit(_EGLContext *ctx)
* Parse the list of context attributes and return the proper error code.
*/
static EGLint
-_eglParseContextAttribList(_EGLContext *ctx, const EGLint *attrib_list)
+_eglParseContextAttribList(_EGLContext *ctx, _EGLDisplay *dpy,
+ const EGLint *attrib_list)
{
EGLenum api = ctx-ClientAPI;
EGLint i, err = EGL_SUCCESS;
@@ -86,22 +87,88 @@ _eglParseContextAttribList(_EGLContext *ctx, const EGLint
*attrib_list)
if (!attrib_list)
return EGL_SUCCESS;
+ if (api == EGL_OPENVG_API attrib_list[0] != EGL_NONE) {
+ _eglLog(_EGL_DEBUG, bad context attribute 0x%04x, attrib_list[0]);
+ return EGL_BAD_ATTRIBUTE;
+ }
+
for (i = 0; attrib_list[i] != EGL_NONE; i++) {
EGLint attr = attrib_list[i++];
EGLint val = attrib_list[i];
switch (attr) {
case EGL_CONTEXT_CLIENT_VERSION:
- if (api != EGL_OPENGL_ES_API) {
+ ctx-ClientMajorVersion = val;
+ break;
+
+ case EGL_CONTEXT_MINOR_VERSION_KHR:
+ if (!dpy-Extensions.KHR_create_context) {
err = EGL_BAD_ATTRIBUTE;
break;
}
- if (val != 1 val != 2) {
+
+ ctx-ClientMinorVersion = val;
+ break;
+
+ case EGL_CONTEXT_FLAGS_KHR:
+ if (!dpy-Extensions.KHR_create_context) {
err = EGL_BAD_ATTRIBUTE;
break;
}
- ctx-ClientMajorVersion = val;
+
+ /* The EGL_KHR_create_context spec says:
+ *
+ * Flags are only defined for OpenGL context creation, and
+ * specifying a flags value other than zero for other types of
+ * contexts, including OpenGL ES contexts, will generate an
+ * error.
+ */
+ if (api != EGL_OPENGL_API val != 0) {
+err = EGL_BAD_ATTRIBUTE;
+break;
+ }
+
+ ctx-Flags = val;
break;
+
+ case EGL_CONTEXT_OPENGL_PROFILE_MASK_KHR:
+ if (!dpy-Extensions.KHR_create_context) {
+err = EGL_BAD_ATTRIBUTE;
+break;
+ }
+
+ /* The EGL_KHR_create_context spec says:
+ *
+ * [EGL_CONTEXT_OPENGL_PROFILE_MASK_KHR] is only meaningful for
+ * OpenGL contexts, and specifying it for other types of
+ * contexts, including OpenGL ES contexts, will generate an
+ * error.
+ */
+ if (api != EGL_OPENGL_API) {
+err = EGL_BAD_ATTRIBUTE;
+break;
+ }
+
+ ctx-Profile = val;
+ break;
+
+ case EGL_CONTEXT_OPENGL_RESET_NOTIFICATION_STRATEGY_KHR:
+ /* The EGL_KHR_create_context spec says:
+ *
+ * [EGL_CONTEXT_OPENGL_RESET_NOTIFICATION_STRATEGY_KHR] is only
+ * meaningful for OpenGL contexts, and specifying it for other
+ * types of contexts, including OpenGL ES contexts, will generate
+ * an error.
+ */
+ if (!dpy-Extensions.KHR_create_context
+ || api != EGL_OPENGL_API) {
+err = EGL_BAD_ATTRIBUTE;
+break;
+ }
+
+ ctx-ResetNotificationStrategy = val;
+ break;
+
default:
err = EGL_BAD_ATTRIBUTE;
break;
@@ -113,6 +180,142 @@ _eglParseContextAttribList(_EGLContext *ctx, const EGLint
*attrib_list)
}
}
+ if (api == EGL_OPENGL_API) {
+ /* The EGL_KHR_create_context spec says:
+ *
+ * If the requested OpenGL version is less than 3.2,
+ * EGL_CONTEXT_OPENGL_PROFILE_MASK_KHR is ignored and the
+ * functionality of the context is determined solely by the
+ * requested version.
+ *
+ * Since the value is ignored, only validate the setting if the version
+ * is = 3.2.
+ */
+ if (ctx-ClientMajorVersion = 4
+ || (ctx-ClientMajorVersion == 3 ctx-ClientMinorVersion = 2)) {
+ switch (ctx-Profile) {
+ case EGL_CONTEXT_OPENGL_CORE_PROFILE_BIT_KHR:
+ case EGL_CONTEXT_OPENGL_COMPATIBILITY_PROFILE_BIT_KHR:
+break;
+
+ default:
+
Mesa (gles3): egl: Implement front-end support for EGL_EXT_create_context_robustness
Module: Mesa
Branch: gles3
Commit: 54a75ab732194a8348ed5d546bba5586a33375c4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=54a75ab732194a8348ed5d546bba5586a33375c4
Author: Ian Romanick ian.d.roman...@intel.com
Date: Thu Jul 19 15:08:06 2012 -0700
egl: Implement front-end support for EGL_EXT_create_context_robustness
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
---
src/egl/main/eglcontext.c | 25 +
src/egl/main/egldisplay.h |2 ++
src/egl/main/eglmisc.c|2 ++
3 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/src/egl/main/eglcontext.c b/src/egl/main/eglcontext.c
index f0620aa..ecb5d50 100644
--- a/src/egl/main/eglcontext.c
+++ b/src/egl/main/eglcontext.c
@@ -169,6 +169,31 @@ _eglParseContextAttribList(_EGLContext *ctx, _EGLDisplay
*dpy,
ctx-ResetNotificationStrategy = val;
break;
+ case EGL_CONTEXT_OPENGL_RESET_NOTIFICATION_STRATEGY_EXT:
+ /* The EGL_EXT_create_context_robustness spec says:
+ *
+ * [EGL_CONTEXT_OPENGL_RESET_NOTIFICATION_STRATEGY_EXT] is only
+ * meaningful for OpenGL ES contexts, and specifying it for other
+ * types of contexts will generate an EGL_BAD_ATTRIBUTE error.
+ */
+ if (!dpy-Extensions.EXT_create_context_robustness
+ || api != EGL_OPENGL_ES_API) {
+err = EGL_BAD_ATTRIBUTE;
+break;
+ }
+
+ ctx-ResetNotificationStrategy = val;
+ break;
+
+ case EGL_CONTEXT_OPENGL_ROBUST_ACCESS_EXT:
+ if (!dpy-Extensions.EXT_create_context_robustness) {
+err = EGL_BAD_ATTRIBUTE;
+break;
+ }
+
+ ctx-Flags = EGL_CONTEXT_OPENGL_ROBUST_ACCESS_BIT_KHR;
+ break;
+
default:
err = EGL_BAD_ATTRIBUTE;
break;
diff --git a/src/egl/main/egldisplay.h b/src/egl/main/egldisplay.h
index 09096f7..3a6f361 100644
--- a/src/egl/main/egldisplay.h
+++ b/src/egl/main/egldisplay.h
@@ -114,6 +114,8 @@ struct _egl_extensions
EGLBoolean ANDROID_image_native_buffer;
EGLBoolean NV_post_sub_buffer;
+
+ EGLBoolean EXT_create_context_robustness;
};
diff --git a/src/egl/main/eglmisc.c b/src/egl/main/eglmisc.c
index 31c3f75..c681bcf 100644
--- a/src/egl/main/eglmisc.c
+++ b/src/egl/main/eglmisc.c
@@ -117,6 +117,8 @@ _eglUpdateExtensionsString(_EGLDisplay *dpy)
_EGL_CHECK_EXTENSION(ANDROID_image_native_buffer);
+ _EGL_CHECK_EXTENSION(EXT_create_context_robustness);
+
_EGL_CHECK_EXTENSION(NV_post_sub_buffer);
#undef _EGL_CHECK_EXTENSION
}
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Mesa (gles3): egl_dri2: Add support for EGL_KHR_create_context and EGL_EXT_create_context_robustness
Module: Mesa
Branch: gles3
Commit: 254a2ffc8e6782a858d0414ba317ed42f4035549
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=254a2ffc8e6782a858d0414ba317ed42f4035549
Author: Ian Romanick ian.d.roman...@intel.com
Date: Thu Jul 19 16:04:01 2012 -0700
egl_dri2: Add support for EGL_KHR_create_context and
EGL_EXT_create_context_robustness
Just like in GLX, EGL_KHR_create_context requires DRI2 version = 3, and
EGL_EXT_create_context_robustness requires both DRI2 version = 3 and the
__DRI2_ROBUSTNESS extension.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
---
src/egl/drivers/dri2/egl_dri2.c | 67 +++---
src/egl/drivers/dri2/egl_dri2.h |1 +
2 files changed, 62 insertions(+), 6 deletions(-)
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index a2f9a8b..3613694 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -483,6 +483,13 @@ dri2_setup_screen(_EGLDisplay *disp)
disp-Extensions.KHR_surfaceless_gles2 = EGL_TRUE;
disp-Extensions.KHR_surfaceless_opengl = EGL_TRUE;
+ if (dri2_dpy-dri2-base.version = 3) {
+ disp-Extensions.KHR_create_context = EGL_TRUE;
+
+ if (dri2_dpy-robustness)
+ disp-Extensions.EXT_create_context_robustness = EGL_TRUE;
+ }
+
if (dri2_dpy-image) {
disp-Extensions.MESA_drm_image = EGL_TRUE;
disp-Extensions.KHR_image_base = EGL_TRUE;
@@ -519,8 +526,16 @@ dri2_create_screen(_EGLDisplay *disp)
extensions = dri2_dpy-core-getExtensions(dri2_dpy-dri_screen);
if (dri2_dpy-dri2) {
+ unsigned i;
+
if (!dri2_bind_extensions(dri2_dpy, dri2_core_extensions, extensions))
goto cleanup_dri_screen;
+
+ for (i = 0; extensions[i]; i++) {
+if (strcmp(extensions[i]-name, __DRI2_ROBUSTNESS) == 0) {
+dri2_dpy-robustness = (__DRIrobustnessExtension *) extensions[i];
+}
+ }
} else {
assert(dri2_dpy-swrast);
if (!dri2_bind_extensions(dri2_dpy, swrast_core_extensions, extensions))
@@ -669,7 +684,13 @@ dri2_create_context(_EGLDriver *drv, _EGLDisplay *disp,
_EGLConfig *conf,
}
break;
case EGL_OPENGL_API:
- api = __DRI_API_OPENGL;
+ if ((dri2_ctx-base.ClientMajorVersion = 4
+ || (dri2_ctx-base.ClientMajorVersion == 3
+dri2_ctx-base.ClientMinorVersion = 2))
+ dri2_ctx-base.Profile == EGL_CONTEXT_OPENGL_CORE_PROFILE_BIT_KHR)
+ api = __DRI_API_OPENGL_CORE;
+ else
+ api = __DRI_API_OPENGL;
break;
default:
_eglError(EGL_BAD_PARAMETER, eglCreateContext);
@@ -701,17 +722,51 @@ dri2_create_context(_EGLDriver *drv, _EGLDisplay *disp,
_EGLConfig *conf,
if (dri2_dpy-dri2) {
if (dri2_dpy-dri2-base.version = 3) {
unsigned error;
- const uint32_t ctx_attribs[2] = {
-__DRI_CTX_ATTRIB_MAJOR_VERSION,
-dri2_ctx-base.ClientMajorVersion
- };
+ unsigned num_attribs = 0;
+ uint32_t ctx_attribs[8];
+
+ ctx_attribs[num_attribs++] = __DRI_CTX_ATTRIB_MAJOR_VERSION;
+ ctx_attribs[num_attribs++] = dri2_ctx-base.ClientMajorVersion;
+ ctx_attribs[num_attribs++] = __DRI_CTX_ATTRIB_MINOR_VERSION;
+ ctx_attribs[num_attribs++] = dri2_ctx-base.ClientMinorVersion;
+
+ if (dri2_ctx-base.Flags != 0) {
+/* If the implementation doesn't support the __DRI2_ROBUSTNESS
+ * extension, don't even try to send it the robust-access flag.
+ * It may explode. Instead, generate the required EGL error here.
+ */
+if ((dri2_ctx-base.Flags
EGL_CONTEXT_OPENGL_ROBUST_ACCESS_BIT_KHR) != 0
+ !dri2_dpy-robustness) {
+ _eglError(EGL_BAD_MATCH, eglCreateContext);
+ goto cleanup;
+}
+
+ctx_attribs[num_attribs++] = __DRI_CTX_ATTRIB_FLAGS;
+ctx_attribs[num_attribs++] = dri2_ctx-base.Flags;
+ }
+
+ if (dri2_ctx-base.ResetNotificationStrategy !=
EGL_NO_RESET_NOTIFICATION_KHR) {
+/* If the implementation doesn't support the __DRI2_ROBUSTNESS
+ * extension, don't even try to send it a reset strategy. It may
+ * explode. Instead, generate the required EGL error here.
+ */
+if (!dri2_dpy-robustness) {
+ _eglError(EGL_BAD_CONFIG, eglCreateContext);
+ goto cleanup;
+}
+
+ctx_attribs[num_attribs++] = __DRI_CTX_ATTRIB_RESET_STRATEGY;
+ctx_attribs[num_attribs++] = __DRI_CTX_RESET_LOSE_CONTEXT;
+ }
+
+ assert(num_attribs = ARRAY_SIZE(ctx_attribs));
dri2_ctx-dri_context =
dri2_dpy-dri2-createContextAttribs(dri2_dpy-dri_screen,
api,
dri_config,
Mesa (gles3): egl: Replace KHR_surfaceless_* extensions with KHR_surfaceless_context
Module: Mesa
Branch: gles3
Commit: 26850fe2fafb00583e8f4b216e2cf38464c89a90
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=26850fe2fafb00583e8f4b216e2cf38464c89a90
Author: Ian Romanick ian.d.roman...@intel.com
Date: Wed Jul 18 09:38:34 2012 -0700
egl: Replace KHR_surfaceless_* extensions with KHR_surfaceless_context
KHR extension name is reserved for Khronos ratified extensions, and there is
no such thing as EGL_KHR_surfaceless_{gles1,gles2,opengl}. Replace these
three extensions with EGL_KHR_surfaceless_context since that extension
actually exists.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
---
src/egl/drivers/dri2/egl_dri2.c |4 +---
src/egl/main/eglapi.c |8 ++--
src/egl/main/eglcontext.c | 19 ++-
src/egl/main/egldisplay.h |4 +---
src/egl/main/eglmisc.c |4 +---
src/gallium/state_trackers/egl/common/egl_g3d.c |4 +---
6 files changed, 8 insertions(+), 35 deletions(-)
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 3613694..29aceff 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -479,9 +479,7 @@ dri2_setup_screen(_EGLDisplay *disp)
disp-ClientAPIs |= EGL_OPENGL_ES2_BIT;
assert(dri2_dpy-dri2 || dri2_dpy-swrast);
- disp-Extensions.KHR_surfaceless_gles1 = EGL_TRUE;
- disp-Extensions.KHR_surfaceless_gles2 = EGL_TRUE;
- disp-Extensions.KHR_surfaceless_opengl = EGL_TRUE;
+ disp-Extensions.KHR_surfaceless_context = EGL_TRUE;
if (dri2_dpy-dri2-base.version = 3) {
disp-Extensions.KHR_create_context = EGL_TRUE;
diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index ffc404c..bcc5465 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -427,9 +427,7 @@ eglCreateContext(EGLDisplay dpy, EGLConfig config,
EGLContext share_list,
if (!config) {
/* config may be NULL if surfaceless */
- if (!disp-Extensions.KHR_surfaceless_gles1
- !disp-Extensions.KHR_surfaceless_gles2
- !disp-Extensions.KHR_surfaceless_opengl)
+ if (!disp-Extensions.KHR_surfaceless_context)
RETURN_EGL_ERROR(disp, EGL_BAD_CONFIG, EGL_NO_CONTEXT);
}
@@ -487,9 +485,7 @@ eglMakeCurrent(EGLDisplay dpy, EGLSurface draw, EGLSurface
read,
RETURN_EGL_ERROR(disp, EGL_BAD_CONTEXT, EGL_FALSE);
if (!draw_surf || !read_surf) {
/* surfaces may be NULL if surfaceless */
- if (!disp-Extensions.KHR_surfaceless_gles1
- !disp-Extensions.KHR_surfaceless_gles2
- !disp-Extensions.KHR_surfaceless_opengl)
+ if (!disp-Extensions.KHR_surfaceless_context)
RETURN_EGL_ERROR(disp, EGL_BAD_SURFACE, EGL_FALSE);
if ((!draw_surf draw != EGL_NO_SURFACE) ||
diff --git a/src/egl/main/eglcontext.c b/src/egl/main/eglcontext.c
index ecb5d50..cb50de7 100644
--- a/src/egl/main/eglcontext.c
+++ b/src/egl/main/eglcontext.c
@@ -477,7 +477,6 @@ _eglCheckMakeCurrent(_EGLContext *ctx, _EGLSurface *draw,
_EGLSurface *read)
_EGLThreadInfo *t = _eglGetCurrentThread();
_EGLDisplay *dpy;
EGLint conflict_api;
- EGLBoolean surfaceless;
if (_eglIsCurrentThreadDummy())
return _eglError(EGL_BAD_ALLOC, eglMakeCurrent);
@@ -490,22 +489,8 @@ _eglCheckMakeCurrent(_EGLContext *ctx, _EGLSurface *draw,
_EGLSurface *read)
}
dpy = ctx-Resource.Display;
- switch (_eglGetContextAPIBit(ctx)) {
- case EGL_OPENGL_ES_BIT:
- surfaceless = dpy-Extensions.KHR_surfaceless_gles1;
- break;
- case EGL_OPENGL_ES2_BIT:
- surfaceless = dpy-Extensions.KHR_surfaceless_gles2;
- break;
- case EGL_OPENGL_BIT:
- surfaceless = dpy-Extensions.KHR_surfaceless_opengl;
- break;
- default:
- surfaceless = EGL_FALSE;
- break;
- }
-
- if (!surfaceless (draw == NULL || read == NULL))
+ if (!dpy-Extensions.KHR_surfaceless_context
+(draw == NULL || read == NULL))
return _eglError(EGL_BAD_MATCH, eglMakeCurrent);
/*
diff --git a/src/egl/main/egldisplay.h b/src/egl/main/egldisplay.h
index 3a6f361..ccb1fbc 100644
--- a/src/egl/main/egldisplay.h
+++ b/src/egl/main/egldisplay.h
@@ -103,9 +103,7 @@ struct _egl_extensions
EGLBoolean KHR_reusable_sync;
EGLBoolean KHR_fence_sync;
- EGLBoolean KHR_surfaceless_gles1;
- EGLBoolean KHR_surfaceless_gles2;
- EGLBoolean KHR_surfaceless_opengl;
+ EGLBoolean KHR_surfaceless_context;
EGLBoolean KHR_create_context;
EGLBoolean NOK_swap_region;
diff --git a/src/egl/main/eglmisc.c b/src/egl/main/eglmisc.c
index c681bcf..b7599d0 100644
--- a/src/egl/main/eglmisc.c
+++ b/src/egl/main/eglmisc.c
@@ -107,9 +107,7 @@ _eglUpdateExtensionsString(_EGLDisplay *dpy)
_EGL_CHECK_EXTENSION(KHR_reusable_sync);
_EGL_CHECK_EXTENSION(KHR_fence_sync);
- _EGL_CHECK_EXTENSION(KHR_surfaceless_gles1);
- _EGL_CHECK_EXTENSION(KHR_surfaceless_gles2);
-
Mesa (gles3): dri2: Note that __DRI_API_GLES2 is also used for OpenGL ES 3.
Module: Mesa
Branch: gles3
Commit: 11d0c35d575567f15846d4671ba8a2a3ddd56c40
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=11d0c35d575567f15846d4671ba8a2a3ddd56c40
Author: Ian Romanick ian.d.roman...@intel.com
Date: Wed Jul 18 14:29:29 2012 -0700
dri2: Note that __DRI_API_GLES2 is also used for OpenGL ES 3.0
Unlike 1.x to 2.0, OpenGL ES 3.0 is backwards compatible with 2.0. Use the
same API flag for both. Applications that specifically want 3.0 will specify
this using the major / minor version attributes.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
---
include/GL/internal/dri_interface.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/GL/internal/dri_interface.h
b/include/GL/internal/dri_interface.h
index d3a66c5..97e1a1a 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -800,8 +800,8 @@ struct __DRIdri2LoaderExtensionRec {
#define __DRI_DRI2_VERSION 3
#define __DRI_API_OPENGL 0 /** OpenGL compatibility profile */
-#define __DRI_API_GLES 1
-#define __DRI_API_GLES22
+#define __DRI_API_GLES 1 /** OpenGL ES 1.x */
+#define __DRI_API_GLES22 /** OpenGL ES 2.0 or 3.0 */
#define __DRI_API_OPENGL_CORE 3 /** OpenGL 3.2+ core profile */
#define __DRI_CTX_ATTRIB_MAJOR_VERSION 0
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (gles3): egl: Allow OpenGL ES 3.0 as a version
Module: Mesa Branch: gles3 Commit: dcb7fe6fb2bc11fa6193060517b263d09ab38cc3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dcb7fe6fb2bc11fa6193060517b263d09ab38cc3 Author: Ian Romanick ian.d.roman...@intel.com Date: Thu Jul 19 16:12:13 2012 -0700 egl: Allow OpenGL ES 3.0 as a version In the DRI2 back-end this will get the same API as GLES 2.0. Signed-off-by: Ian Romanick ian.d.roman...@intel.com --- src/egl/drivers/dri2/egl_dri2.c |1 + src/egl/main/eglcontext.c |8 +++- 2 files changed, 8 insertions(+), 1 deletions(-) diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c index 29aceff..11e12d5 100644 --- a/src/egl/drivers/dri2/egl_dri2.c +++ b/src/egl/drivers/dri2/egl_dri2.c @@ -674,6 +674,7 @@ dri2_create_context(_EGLDriver *drv, _EGLDisplay *disp, _EGLConfig *conf, api = __DRI_API_GLES; break; case 2: + case 3: api = __DRI_API_GLES2; break; default: diff --git a/src/egl/main/eglcontext.c b/src/egl/main/eglcontext.c index cb50de7..829050d 100644 --- a/src/egl/main/eglcontext.c +++ b/src/egl/main/eglcontext.c @@ -54,6 +54,7 @@ _eglGetContextAPIBit(_EGLContext *ctx) bit = EGL_OPENGL_ES_BIT; break; case 2: + case 3: bit = EGL_OPENGL_ES2_BIT; break; default: @@ -317,9 +318,14 @@ _eglParseContextAttribList(_EGLContext *ctx, _EGLDisplay *dpy, break; case 2: + if (ctx-ClientMinorVersion 0) +err = EGL_BAD_MATCH; + break; + + case 3: default: /* Don't put additional version checks here. We don't know that - * there won't be versions 2.0. + * there won't be versions 3.0. */ break; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (gles3): Merge branch 'master' into gles3
Module: Mesa Branch: gles3 Commit: 23c5b3193f3afee0288740f1a1cc16b2c020f4e4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=23c5b3193f3afee0288740f1a1cc16b2c020f4e4 Author: Paul Berry stereotype...@gmail.com Date: Thu Aug 2 10:51:50 2012 -0700 Merge branch 'master' into gles3 --- ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/msaa: Treat GL_SAMPLES=1 as equivalent to GL_SAMPLES=0.
Module: Mesa
Branch: master
Commit: 97fc89c6cbaa3b5ef7f678d2dc2c7d5bbba05315
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=97fc89c6cbaa3b5ef7f678d2dc2c7d5bbba05315
Author: Paul Berry stereotype...@gmail.com
Date: Thu Jul 26 18:01:28 2012 -0700
i965/msaa: Treat GL_SAMPLES=1 as equivalent to GL_SAMPLES=0.
EXT_framebuffer_multisample is a required subpart of
ARB_framebuffer_object, which means that we must support it even on
platforms that don't support MSAA. Fortunately
EXT_framebuffer_multisample allows for this by allowing GL_MAX_SAMPLES
to be set to 1.
This leads to a tricky quirk in the GL spec: since
GlRenderbufferStorageMultisamples() accepts any value for its
samples parameter up to and including GL_MAX_SAMPLES, that means
that on platforms that don't support MSAA, GL_SAMPLES is allowed to be
set to either 0 or 1. On platforms that do support MSAA, GL_SAMPLES=1
is not used; 0 means no MSAA, and 2 or higher means MSAA.
In other words, GL_SAMPLES needs to be interpreted as follows:
=0 no MSAA (possible on all platforms)
=1 no MSAA (only possible on platforms where MSAA unsupported)
1 MSAA (only possible on platforms where MSAA supported)
This patch modifies all MSAA-related code to choose between
multisampling and single-sampling based on the condition (GL_SAMPLES
1) instead of (GL_SAMPLES 0) so that GL_SAMPLES=1 will be treated as
no MSAA.
Note that since GL_SAMPLES=1 implies GL_SAMPLE_BUFFERS=1, we can no
longer use GL_SAMPLE_BUFFERS to distinguish between MSAA and non-MSAA
rendering.
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 10 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c |4 ++--
src/mesa/drivers/dri/i965/gen6_blorp.cpp |6 +++---
src/mesa/drivers/dri/i965/gen6_multisample_state.c |3 ++-
src/mesa/drivers/dri/i965/gen6_sf_state.c |2 +-
src/mesa/drivers/dri/i965/gen6_wm_state.c |2 +-
src/mesa/drivers/dri/i965/gen7_blorp.cpp |4 ++--
src/mesa/drivers/dri/i965/gen7_sf_state.c |2 +-
src/mesa/drivers/dri/i965/gen7_wm_state.c |2 +-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |4 ++--
src/mesa/drivers/dri/intel/intel_mipmap_tree.c |6 +++---
11 files changed, 23 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 296b99f..1206237 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1582,7 +1582,7 @@ inline intel_msaa_layout
compute_msaa_layout_for_pipeline(struct brw_context *brw, unsigned num_samples,
intel_msaa_layout true_layout)
{
- if (num_samples == 0) {
+ if (num_samples = 1) {
/* When configuring the GPU for non-MSAA, we can still accommodate IMS
* format buffers, by transforming coordinates appropriately.
*/
@@ -1652,7 +1652,7 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
dst.num_samples = 0;
}
- if (dst.map_stencil_as_y_tiled dst.num_samples 0) {
+ if (dst.map_stencil_as_y_tiled dst.num_samples 1) {
/* If the destination surface is a W-tiled multisampled stencil buffer
* that we're mapping as Y tiled, then we need to arrange for the WM
* program to run once per sample rather than once per pixel, because
@@ -1662,7 +1662,7 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
wm_prog_key.persample_msaa_dispatch = true;
}
- if (src.num_samples 0 dst.num_samples 0) {
+ if (src.num_samples 0 dst.num_samples 1) {
/* We are blitting from a multisample buffer to a multisample buffer, so
* we must preserve samples within a pixel. This means we have to
* arrange for the WM program to run once per sample rather than once
@@ -1679,7 +1679,7 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
GLenum base_format = _mesa_get_format_base_format(src_mt-format);
if (base_format != GL_DEPTH_COMPONENT /* TODO: what about depth/stencil?
*/
base_format != GL_STENCIL_INDEX
- src_mt-num_samples 0 dst_mt-num_samples == 0) {
+ src_mt-num_samples 1 dst_mt-num_samples = 1) {
/* We are downsampling a color buffer, so blend. */
wm_prog_key.blend = true;
}
@@ -1717,7 +1717,7 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
wm_push_consts.x_transform.setup(src_x0, dst_x0, dst_x1, mirror_x);
wm_push_consts.y_transform.setup(src_y0, dst_y0, dst_y1, mirror_y);
- if (dst.num_samples == 0 dst_mt-num_samples 0) {
+ if (dst.num_samples = 1 dst_mt-num_samples 1) {
/* We must expand the rectangle we send through the rendering pipeline,
* to account for the fact that we
Mesa (master): i965/msaa: Allow GL_SAMPLES to be set to 1 prior to Gen6.
Module: Mesa Branch: master Commit: c18806cebf107d03751b11cc8866062c3822a56f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c18806cebf107d03751b11cc8866062c3822a56f Author: Paul Berry stereotype...@gmail.com Date: Thu Jul 26 18:02:20 2012 -0700 i965/msaa: Allow GL_SAMPLES to be set to 1 prior to Gen6. This patch allows GL_SAMPLES to be set to either 0 or 1 on i965 platforms that don't support MSAA (those prior to Gen6). Setting GL_SAMPLES=1 has the same effect as setting it to 0 on these platforms (because MSAA is unsupported), but is distinguishable via the GL API. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50165 Reviewed-by: Jordan Justen jordan.l.jus...@intel.com Reviewed-by: Ian Romanick ian.d.roman...@intel.com --- src/mesa/drivers/dri/intel/intel_fbo.c | 10 +- 1 files changed, 9 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index a53985b..613287f 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -202,7 +202,15 @@ quantize_num_samples(struct intel_context *intel, unsigned num_samples) return 0; return 0; default: - /* MSAA unsupported */ + /* MSAA unsupported. However, a careful reading of + * EXT_framebuffer_multisample reveals that we need to permit + * num_samples to be 1 (since num_samples is permitted to be as high as + * GL_MAX_SAMPLES, and GL_MAX_SAMPLES must be at least 1). Since + * platforms before Gen6 don't support MSAA, this is safe, because + * multisampling won't happen anyhow. + */ + if (num_samples 0) + return 1; return 0; } } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/msaa: Use MESA_FORMAT_R8 for MCS buffer.
Module: Mesa Branch: master Commit: ee9f6a34ccf7f5b21bba8d8f9d03cc0a2c74 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee9f6a34ccf7f5b21bba8d8f9d03cc0a2c74 Author: Paul Berry stereotype...@gmail.com Date: Thu Jul 26 14:13:35 2012 -0700 i965/msaa: Use MESA_FORMAT_R8 for MCS buffer. No functional change. This patch modifies intel_miptree_alloc_mcs to allocate the 4x MCS buffer using MESA_FORMAT_R8 instead of MESA_FORMAT_A8. In principle it doesn't matter, since we only access the buffer using MCS-specific hardware mechanisms, so all that's important is to use a format with the correct size. However, MESA_FORMAT_A8 has enough unusual behaviours that it seems prudent to avoid it. Acked-by: Kenneth Graunke kenn...@whitecape.org --- src/mesa/drivers/dri/intel/intel_mipmap_tree.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index 3d15a8d..53bc23f 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -684,7 +684,7 @@ intel_miptree_alloc_mcs(struct intel_context *intel, /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for * each sample). */ - format = MESA_FORMAT_A8; + format = MESA_FORMAT_R8; break; case 8: /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa: Make more consistent use of _mesa_is_{user, winsys}_fbo ()
Module: Mesa
Branch: master
Commit: 284ad9c3b29a6d6f0bade050ea9e949d67967983
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=284ad9c3b29a6d6f0bade050ea9e949d67967983
Author: Paul Berry stereotype...@gmail.com
Date: Wed Jul 18 12:54:48 2012 -0700
mesa: Make more consistent use of _mesa_is_{user,winsys}_fbo()
A lot of code was still differentiating between between winsys and
user fbos by testing the fbo's name against zero. This converts
everything in core mesa, the state tracker, and src/mesa/program over
to use _mesa_is_user_fbo() and _mesa_is_winsys_fbo().
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/main/context.c |8
src/mesa/main/drawpix.c |4 +++-
src/mesa/main/framebuffer.c |6 +++---
src/mesa/main/readpix.c |4 +++-
src/mesa/program/prog_statevars.c |3 ++-
src/mesa/state_tracker/st_cb_viewport.c |4 +++-
src/mesa/state_tracker/st_context.h |3 ++-
src/mesa/state_tracker/st_manager.c |4 +++-
8 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index 41550f9..243053e 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -1456,8 +1456,8 @@ _mesa_make_current( struct gl_context *newCtx,
_glapi_set_dispatch(newCtx-CurrentDispatch);
if (drawBuffer readBuffer) {
- ASSERT(drawBuffer-Name == 0);
- ASSERT(readBuffer-Name == 0);
+ ASSERT(_mesa_is_winsys_fbo(drawBuffer));
+ ASSERT(_mesa_is_winsys_fbo(readBuffer));
_mesa_reference_framebuffer(newCtx-WinSysDrawBuffer, drawBuffer);
_mesa_reference_framebuffer(newCtx-WinSysReadBuffer, readBuffer);
@@ -1465,7 +1465,7 @@ _mesa_make_current( struct gl_context *newCtx,
* Only set the context's Draw/ReadBuffer fields if they're NULL
* or not bound to a user-created FBO.
*/
- if (!newCtx-DrawBuffer || newCtx-DrawBuffer-Name == 0) {
+ if (!newCtx-DrawBuffer || _mesa_is_winsys_fbo(newCtx-DrawBuffer)) {
_mesa_reference_framebuffer(newCtx-DrawBuffer, drawBuffer);
/* Update the FBO's list of drawbuffers/renderbuffers.
* For winsys FBOs this comes from the GL state (which may have
@@ -1473,7 +1473,7 @@ _mesa_make_current( struct gl_context *newCtx,
*/
_mesa_update_draw_buffers(newCtx);
}
- if (!newCtx-ReadBuffer || newCtx-ReadBuffer-Name == 0) {
+ if (!newCtx-ReadBuffer || _mesa_is_winsys_fbo(newCtx-ReadBuffer)) {
_mesa_reference_framebuffer(newCtx-ReadBuffer, readBuffer);
}
diff --git a/src/mesa/main/drawpix.c b/src/mesa/main/drawpix.c
index 49b0782..bd9837f 100644
--- a/src/mesa/main/drawpix.c
+++ b/src/mesa/main/drawpix.c
@@ -36,6 +36,7 @@
#include state.h
#include dispatch.h
#include glformats.h
+#include fbobject.h
#if FEATURE_drawpix
@@ -240,7 +241,8 @@ _mesa_CopyPixels( GLint srcx, GLint srcy, GLsizei width,
GLsizei height,
goto end;
}
- if (ctx-ReadBuffer-Name != 0 ctx-ReadBuffer-Visual.samples 0) {
+ if (_mesa_is_user_fbo(ctx-ReadBuffer)
+ ctx-ReadBuffer-Visual.samples 0) {
_mesa_error(ctx, GL_INVALID_OPERATION,
glCopyPixels(multisample FBO));
goto end;
diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
index f45ece6..13887f8 100644
--- a/src/mesa/main/framebuffer.c
+++ b/src/mesa/main/framebuffer.c
@@ -347,7 +347,7 @@ _mesa_resizebuffers( struct gl_context *ctx )
GLuint newWidth, newHeight;
struct gl_framebuffer *buffer = ctx-WinSysDrawBuffer;
- assert(buffer-Name == 0);
+ assert(_mesa_is_winsys_fbo(buffer));
/* ask device driver for size of output buffer */
ctx-Driver.GetBufferSize( buffer, newWidth, newHeight );
@@ -364,7 +364,7 @@ _mesa_resizebuffers( struct gl_context *ctx )
GLuint newWidth, newHeight;
struct gl_framebuffer *buffer = ctx-WinSysReadBuffer;
- assert(buffer-Name == 0);
+ assert(_mesa_is_winsys_fbo(buffer));
/* ask device driver for size of read buffer */
ctx-Driver.GetBufferSize( buffer, newWidth, newHeight );
@@ -444,7 +444,7 @@ _mesa_update_draw_buffer_bounds(struct gl_context *ctx)
if (!buffer)
return;
- if (buffer-Name) {
+ if (_mesa_is_user_fbo(buffer)) {
/* user-created framebuffer size depends on the renderbuffers */
update_framebuffer_size(ctx, buffer);
}
diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c
index 82d99fd..7ac8774 100644
--- a/src/mesa/main/readpix.c
+++ b/src/mesa/main/readpix.c
@@ -37,6 +37,7 @@
#include pbo.h
#include state.h
#include glformats.h
+#include fbobject.h
/**
@@ -722,7 +723,8 @@ _mesa_ReadnPixelsARB( GLint x, GLint y, GLsizei width,
GLsizei height,
}
}
- if (ctx
Mesa (master): intel: Make more consistent use of _mesa_is_{user, winsys}_fbo()
Module: Mesa
Branch: master
Commit: c738ea1191cd1b5a0dc60b0e6d05fd918083e961
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c738ea1191cd1b5a0dc60b0e6d05fd918083e961
Author: Paul Berry stereotype...@gmail.com
Date: Wed Jul 18 12:54:48 2012 -0700
intel: Make more consistent use of _mesa_is_{user,winsys}_fbo()
A lot of code was still differentiating between between winsys and
user fbos by testing the fbo's name against zero. This converts
everything in the i915 and 965 drivers over to use _mesa_is_user_fbo()
and _mesa_is_winsys_fbo().
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i915/i830_vtbl.c |3 ++-
src/mesa/drivers/dri/i915/intel_tris.c |3 ++-
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp|5 +++--
src/mesa/drivers/dri/intel/intel_blit.c |3 ++-
src/mesa/drivers/dri/intel/intel_buffers.c |2 +-
src/mesa/drivers/dri/intel/intel_fbo.c |2 +-
src/mesa/drivers/dri/intel/intel_pixel_bitmap.c |5 +++--
src/mesa/drivers/dri/intel/intel_pixel_copy.c |5 +++--
src/mesa/drivers/dri/intel/intel_tex_copy.c |3 ++-
9 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c
b/src/mesa/drivers/dri/i915/i830_vtbl.c
index 28e95d9..6019852 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -39,6 +39,7 @@
#include swrast_setup/swrast_setup.h
#include main/renderbuffer.h
#include main/framebuffer.h
+#include main/fbobject.h
#define FILE_DEBUG_FLAG DEBUG_STATE
@@ -769,7 +770,7 @@ i830_update_draw_buffer(struct intel_context *intel)
/* Get the intel_renderbuffer for the single colorbuffer we're drawing
* into.
*/
- if (fb-Name == 0) {
+ if (_mesa_is_winsys_fbo(fb)) {
/* drawing to window system buffer */
if (fb-_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT)
colorRegions[0] = intel_get_rb_region(fb, BUFFER_FRONT_LEFT);
diff --git a/src/mesa/drivers/dri/i915/intel_tris.c
b/src/mesa/drivers/dri/i915/intel_tris.c
index cf67d74..5954b24 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.c
+++ b/src/mesa/drivers/dri/i915/intel_tris.c
@@ -38,6 +38,7 @@
#include main/texobj.h
#include main/state.h
#include main/dd.h
+#include main/fbobject.h
#include swrast/swrast.h
#include swrast_setup/swrast_setup.h
@@ -503,7 +504,7 @@ intel_emit_fragcoord(struct intel_context *intel,
intelVertexPtr v)
fragcoord[0] = vertex_position[0];
- if (fb-Name)
+ if (_mesa_is_user_fbo(fb))
fragcoord[1] = vertex_position[1];
else
fragcoord[1] = fb-Height - vertex_position[1];
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index f8b7e4a..bd15632 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -22,6 +22,7 @@
*/
#include main/teximage.h
+#include main/fbobject.h
#include glsl/ralloc.h
@@ -214,13 +215,13 @@ try_blorp_blit(struct intel_context *intel,
/* Account for the fact that in the system framebuffer, the origin is at
* the lower left.
*/
- if (read_fb-Name == 0) {
+ if (_mesa_is_winsys_fbo(read_fb)) {
GLint tmp = read_fb-Height - srcY0;
srcY0 = read_fb-Height - srcY1;
srcY1 = tmp;
mirror_y = !mirror_y;
}
- if (draw_fb-Name == 0) {
+ if (_mesa_is_winsys_fbo(draw_fb)) {
GLint tmp = draw_fb-Height - dstY0;
dstY0 = draw_fb-Height - dstY1;
dstY1 = tmp;
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c
b/src/mesa/drivers/dri/intel/intel_blit.c
index fd4a86c..36a2c6a 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -30,6 +30,7 @@
#include main/context.h
#include main/enums.h
#include main/colormac.h
+#include main/fbobject.h
#include intel_blit.h
#include intel_buffers.h
@@ -248,7 +249,7 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
}
cx = fb-_Xmin;
- if (fb-Name == 0)
+ if (_mesa_is_winsys_fbo(fb))
cy = ctx-DrawBuffer-Height - fb-_Ymax;
else
cy = fb-_Ymin;
diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c
b/src/mesa/drivers/dri/intel/intel_buffers.c
index 2b02763..9a9a259 100644
--- a/src/mesa/drivers/dri/intel/intel_buffers.c
+++ b/src/mesa/drivers/dri/intel/intel_buffers.c
@@ -70,7 +70,7 @@ void
intel_check_front_buffer_rendering(struct intel_context *intel)
{
const struct gl_framebuffer *fb = intel-ctx.DrawBuffer;
- if (fb-Name == 0) {
+ if (_mesa_is_winsys_fbo(fb)) {
/* drawing to window system buffer */
if (fb-_NumColorDrawBuffers 0) {
if (fb-_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) {
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index ac7d6c1..a53985b 100644
--- a/src
Mesa (master): i965/msaa: Remove TODO comments that are no longer relevant.
Module: Mesa Branch: master Commit: 8f37ea414fca66d03f6f4460d6b7730411abb2a2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f37ea414fca66d03f6f4460d6b7730411abb2a2 Author: Paul Berry stereotype...@gmail.com Date: Wed Jul 18 09:54:04 2012 -0700 i965/msaa: Remove TODO comments that are no longer relevant. Reviewed-by: Kenneth Graunke kenn...@whitecape.org --- src/mesa/drivers/dri/i965/brw_state_upload.c |4 ++-- src/mesa/drivers/dri/i965/gen6_blorp.cpp |1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 551fa6a..12535ed 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -153,7 +153,7 @@ static const struct brw_tracked_state *gen6_atoms[] = brw_samplers, gen6_sampler_state, - gen6_multisample_state, /* TODO: is this the right spot? */ + gen6_multisample_state, gen6_vs_state, gen6_gs_state, @@ -222,7 +222,7 @@ const struct brw_tracked_state *gen7_atoms[] = brw_wm_binding_table, gen7_samplers, - gen6_multisample_state, /* TODO: is this the right spot? */ + gen6_multisample_state, gen7_disable_stages, gen7_vs_state, diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index b2cafdb..b134ab4 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -299,7 +299,6 @@ gen6_blorp_emit_blend_state(struct brw_context *brw, memset(blend, 0, sizeof(*blend)); - // TODO: handle other formats. blend-blend1.pre_blend_clamp_enable = 1; blend-blend1.post_blend_clamp_enable = 1; blend-blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Use sendc for all render target writes on Gen6+.
Module: Mesa
Branch: master
Commit: 148c8e639da7ee10fc9e002e3c6d60e17d218b21
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=148c8e639da7ee10fc9e002e3c6d60e17d218b21
Author: Paul Berry stereotype...@gmail.com
Date: Thu Jul 19 07:58:30 2012 -0700
i965: Use sendc for all render target writes on Gen6+.
The sendc instruction causes the fragment shader thread to wait for
any dependent threads (i.e. threads rendering to overlapping pixels)
to complete before sending the message. We need to use sendc on the
first render target write in order to guarantee that fragment shader
outputs are written to the render target in the correct order.
Previously, we only used the sendc instruction when writing to
binding table index 0. This did the right thing for fragment shaders,
because our fragment shader back-ends always issue their first render
target write to binding table index 0. However, it did the wrong
thing for blorp, which performs its render target writes to binding
table index 1.
A more robust solution is to use sendc for all render target writes.
This should not produce any performance penalty, since after the first
sendc, all of the dependent threads will have completed.
For more information about sendc, see the Ivy Bridge PRM, Vol4 Part3
p218 (sendc - Conditional Send Message), and p54 (TDR Registers).
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/i965/brw_eu_emit.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 93e84ae..25bf91b 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -2259,7 +2259,7 @@ void brw_fb_WRITE(struct brw_compile *p,
else
dest = retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW);
- if (intel-gen = 6 binding_table_index == 0) {
+ if (intel-gen = 6) {
insn = next_insn(p, BRW_OPCODE_SENDC);
} else {
insn = next_insn(p, BRW_OPCODE_SEND);
___
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Mesa (master): i965/msaa: use ROUND_DOWN_TO macro.
Module: Mesa
Branch: master
Commit: 4df2848786d4778a2ce7dbf2e046e191036ccb56
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4df2848786d4778a2ce7dbf2e046e191036ccb56
Author: Paul Berry stereotype...@gmail.com
Date: Tue Jul 24 14:48:51 2012 -0700
i965/msaa: use ROUND_DOWN_TO macro.
No functional change. This patch modifies brw_blorp_blit.cpp to use
the ROUND_DOWN_TO macro instead of open-coded bit manipulations, for
clarity.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index bd15632..296b99f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1733,14 +1733,14 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
assert(dst_mt-msaa_layout == INTEL_MSAA_LAYOUT_IMS);
switch (dst_mt-num_samples) {
case 4:
- x0 = (x0 * 2) ~3;
- y0 = (y0 * 2) ~3;
+ x0 = ROUND_DOWN_TO(x0 * 2, 4);
+ y0 = ROUND_DOWN_TO(y0 * 2, 4);
x1 = ALIGN(x1 * 2, 4);
y1 = ALIGN(y1 * 2, 4);
break;
case 8:
- x0 = (x0 * 4) ~7;
- y0 = (y0 * 2) ~3;
+ x0 = ROUND_DOWN_TO(x0 * 4, 8);
+ y0 = ROUND_DOWN_TO(y0 * 2, 4);
x1 = ALIGN(x1 * 4, 8);
y1 = ALIGN(y1 * 2, 4);
break;
@@ -1770,8 +1770,8 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
x_align /= (dst_mt-num_samples == 4 ? 2 : 4);
y_align /= 2;
}
- x0 = (x0 ~(x_align - 1)) * 2;
- y0 = (y0 ~(y_align - 1)) / 2;
+ x0 = ROUND_DOWN_TO(x0, x_align) * 2;
+ y0 = ROUND_DOWN_TO(y0, y_align) / 2;
x1 = ALIGN(x1, x_align) * 2;
y1 = ALIGN(y1, y_align) / 2;
wm_prog_key.use_kill = true;
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Mesa (master): msaa: Compute visual samples/sampleBuffers from all buffers.
Module: Mesa
Branch: master
Commit: 48fdfbcb58929f1c20cb21190846faa388b1abba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=48fdfbcb58929f1c20cb21190846faa388b1abba
Author: Paul Berry stereotype...@gmail.com
Date: Mon Jul 9 20:06:19 2012 -0700
msaa: Compute visual samples/sampleBuffers from all buffers.
This patch ensures that Visual.samples and Visual.sampleBuffers are
set correctly even in the case where there is no color buffer.
Previously, these values would retain their default value of 0 in this
circumstance, even if the depth or stencil buffer was multisampled.
Reviewed-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/main/framebuffer.c |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
index ea14148..f45ece6 100644
--- a/src/mesa/main/framebuffer.c
+++ b/src/mesa/main/framebuffer.c
@@ -517,6 +517,13 @@ _mesa_update_framebuffer_visual(struct gl_context *ctx,
const GLenum baseFormat = _mesa_get_format_base_format(rb-Format);
const gl_format fmt = rb-Format;
+ /* Grab samples and sampleBuffers from any attachment point (assuming
+ * the framebuffer is complete, we'll get the same answer from all
+ * attachments).
+ */
+ fb-Visual.samples = rb-NumSamples;
+ fb-Visual.sampleBuffers = rb-NumSamples 0 ? 1 : 0;
+
if (_mesa_is_legal_color_format(ctx, baseFormat)) {
fb-Visual.redBits = _mesa_get_format_bits(fmt, GL_RED_BITS);
fb-Visual.greenBits = _mesa_get_format_bits(fmt, GL_GREEN_BITS);
@@ -524,8 +531,6 @@ _mesa_update_framebuffer_visual(struct gl_context *ctx,
fb-Visual.alphaBits = _mesa_get_format_bits(fmt, GL_ALPHA_BITS);
fb-Visual.rgbBits = fb-Visual.redBits
+ fb-Visual.greenBits + fb-Visual.blueBits;
-fb-Visual.samples = rb-NumSamples;
-fb-Visual.sampleBuffers = rb-NumSamples 0 ? 1 : 0;
if (_mesa_get_format_color_encoding(fmt) == GL_SRGB)
fb-Visual.sRGBCapable = ctx-Extensions.EXT_framebuffer_sRGB;
break;
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Mesa (master): i965/msaa: Control multisampling behaviour via the visual.
Module: Mesa
Branch: master
Commit: 691c55f3560e5b8b9db9ecd2c089f13b41ec684f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=691c55f3560e5b8b9db9ecd2c089f13b41ec684f
Author: Paul Berry stereotype...@gmail.com
Date: Mon Jul 9 20:05:41 2012 -0700
i965/msaa: Control multisampling behaviour via the visual.
Previously, we used the number of samples in draw buffer 0 to
determine whether to set up the 3D pipeline for multisampling. Using
the visual is cleaner, and has the benefit of working properly when
there is no color buffer.
Fixes all piglit tests EXT_framebuffer_multisample/no-color on Gen7.
On Gen6, the depth-computed variants of these tests still fail; this
will be addresed in a later patch.
Reviewed-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen6_multisample_state.c |8 +++-
src/mesa/drivers/dri/i965/gen6_sf_state.c |4 +---
src/mesa/drivers/dri/i965/gen6_wm_state.c |4 +---
src/mesa/drivers/dri/i965/gen7_sf_state.c |4 +---
src/mesa/drivers/dri/i965/gen7_wm_state.c |4 +---
5 files changed, 7 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
index f0648c3..336e7c5 100644
--- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
@@ -83,20 +83,18 @@ static void upload_multisample_state(struct brw_context
*brw)
{
struct intel_context *intel = brw-intel;
struct gl_context *ctx = intel-ctx;
- unsigned num_samples = 0;
float coverage = 1.0;
float coverage_invert = false;
+ /* _NEW_BUFFERS */
+ unsigned num_samples = ctx-DrawBuffer-Visual.samples;
+
/* _NEW_MULTISAMPLE */
if (ctx-Multisample._Enabled ctx-Multisample.SampleCoverage) {
coverage = ctx-Multisample.SampleCoverageValue;
coverage_invert = ctx-Multisample.SampleCoverageInvert;
}
- /* _NEW_BUFFERS */
- if (ctx-DrawBuffer-_ColorDrawBuffers[0])
- num_samples = ctx-DrawBuffer-_ColorDrawBuffers[0]-NumSamples;
-
/* 3DSTATE_MULTISAMPLE is nonpipelined. */
intel_emit_post_sync_nonzero_flush(intel);
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index aeed369..736e83a 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -122,9 +122,7 @@ upload_sf_state(struct brw_context *brw)
int i;
/* _NEW_BUFFER */
bool render_to_fbo = _mesa_is_user_fbo(brw-intel.ctx.DrawBuffer);
- bool multisampled_fbo = false;
- if (ctx-DrawBuffer-_ColorDrawBuffers[0])
- multisampled_fbo = ctx-DrawBuffer-_ColorDrawBuffers[0]-NumSamples 0;
+ bool multisampled_fbo = ctx-DrawBuffer-Visual.sampleBuffers;
int attr = 0, input_index = 0;
int urb_entry_read_offset = 1;
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c
b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index fa83ece..05f4ab9 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -98,11 +98,9 @@ upload_wm_state(struct brw_context *brw)
const struct brw_fragment_program *fp =
brw_fragment_program_const(brw-fragment_program);
uint32_t dw2, dw4, dw5, dw6;
- bool multisampled_fbo = false;
/* _NEW_BUFFERS */
- if (ctx-DrawBuffer-_ColorDrawBuffers[0])
- multisampled_fbo = ctx-DrawBuffer-_ColorDrawBuffers[0]-NumSamples 0;
+ bool multisampled_fbo = ctx-DrawBuffer-Visual.sampleBuffers;
/* CACHE_NEW_WM_PROG */
if (brw-wm.prog_data-nr_params == 0) {
diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c
b/src/mesa/drivers/dri/i965/gen7_sf_state.c
index b1fe654..2d258d2 100644
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c
@@ -161,9 +161,7 @@ upload_sf_state(struct brw_context *brw)
float point_size;
/* _NEW_BUFFERS */
bool render_to_fbo = _mesa_is_user_fbo(brw-intel.ctx.DrawBuffer);
- bool multisampled_fbo = false;
- if (ctx-DrawBuffer-_ColorDrawBuffers[0])
- multisampled_fbo = ctx-DrawBuffer-_ColorDrawBuffers[0]-NumSamples 0;
+ bool multisampled_fbo = ctx-DrawBuffer-Visual.sampleBuffers;
dw1 = GEN6_SF_STATISTICS_ENABLE |
GEN6_SF_VIEWPORT_TRANSFORM_ENABLE;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 8e4417e..e60027a 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -39,12 +39,10 @@ upload_wm_state(struct brw_context *brw)
const struct brw_fragment_program *fp =
brw_fragment_program_const(brw-fragment_program);
bool writes_depth = false;
- bool multisampled_fbo = false;
uint32_t dw1, dw2;
/* _NEW_BUFFERS */
- if (ctx-DrawBuffer-_ColorDrawBuffers[0])
- multisampled_fbo = ctx-DrawBuffer-_ColorDrawBuffers[0]-NumSamples 0;
+ bool
Mesa (master): i965: Set width, height, and tiling properly for null render targets.
Module: Mesa
Branch: master
Commit: 0aeb87023e64807734aee323e76f81796d525a36
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0aeb87023e64807734aee323e76f81796d525a36
Author: Paul Berry stereotype...@gmail.com
Date: Fri Jul 13 07:25:12 2012 -0700
i965: Set width, height, and tiling properly for null render targets.
The HW docs say that the width and height of null render targets need
to match the width and height of the corresponding depth and/or
stencil buffers, and that they need to be marked as Y-tiled. Although
leaving these values at 0 doesn't seem to cause any ill effects, it
seems wise to follow the documented requirements.
Reviewed-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 33 +++-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 29 ++
2 files changed, 60 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 82e44f9..c2e629c 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -961,9 +961,31 @@ const struct brw_tracked_state brw_wm_pull_constants = {
static void
brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int
unit)
{
+ /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
+* Notes):
+*
+* A null surface will be used in instances where an actual surface is
+* not bound. When a write message is generated to a null surface, no
+* actual surface is written to. When a read message (including any
+* sampling engine message) is generated to a null surface, the result
+* is all zeros. Note that a null surface type is allowed to be used
+* with all messages, even if it is not specificially indicated as
+* supported. All of the remaining fields in surface state are ignored
+* for null surfaces, with the following exceptions:
+*
+* - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
+* depth buffer’s corresponding state for all render target surfaces,
+* including null.
+*
+* - Surface Format must be R8G8B8A8_UNORM.
+*/
struct intel_context *intel = brw-intel;
+ struct gl_context *ctx = intel-ctx;
uint32_t *surf;
+ /* _NEW_BUFFERS */
+ const struct gl_framebuffer *fb = ctx-DrawBuffer;
+
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
6 * 4, 32, brw-wm.surf_offset[unit]);
@@ -976,8 +998,15 @@ brw_update_null_renderbuffer_surface(struct brw_context
*brw, unsigned int unit)
1 BRW_SURFACE_WRITEDISABLE_A_SHIFT);
}
surf[1] = 0;
- surf[2] = 0;
- surf[3] = 0;
+ surf[2] = ((fb-Width - 1) BRW_SURFACE_WIDTH_SHIFT |
+ (fb-Height - 1) BRW_SURFACE_HEIGHT_SHIFT);
+
+ /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
+* Notes):
+*
+* If Surface Type is SURFTYPE_NULL, this field must be TRUE
+*/
+ surf[3] = BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
surf[4] = 0;
surf[5] = 0;
}
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 869f943..2522276 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -409,8 +409,28 @@ gen7_create_constant_surface(struct brw_context *brw,
static void
gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
{
+ /* From the Ivy bridge PRM, Vol4 Part1 p62 (Surface Type: Programming
+* Notes):
+*
+* A null surface is used in instances where an actual surface is not
+* bound. When a write message is generated to a null surface, no
+* actual surface is written to. When a read message (including any
+* sampling engine message) is generated to a null surface, the result
+* is all zeros. Note that a null surface type is allowed to be used
+* with all messages, even if it is not specificially indicated as
+* supported. All of the remaining fields in surface state are ignored
+* for null surfaces, with the following exceptions: Width, Height,
+* Depth, LOD, and Render Target View Extent fields must match the
+* depth buffer’s corresponding state for all render target surfaces,
+* including null.
+*/
+ struct intel_context *intel = brw-intel;
+ struct gl_context *ctx = intel-ctx;
struct gen7_surface_state *surf;
+ /* _NEW_BUFFERS */
+ const struct gl_framebuffer *fb = ctx-DrawBuffer;
+
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
sizeof(*surf), 32, brw-wm.surf_offset[unit]);
memset(surf, 0, sizeof(*surf));
@@ -418,6 +438,15 @@ gen7_update_null_renderbuffer_surface(struct brw_context
Mesa (master): i965/msaa: Work around problems with null render targets on Gen6.
Module: Mesa
Branch: master
Commit: bac43b8bb7ace5401a2cc0d92f416340344df1bd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bac43b8bb7ace5401a2cc0d92f416340344df1bd
Author: Paul Berry stereotype...@gmail.com
Date: Tue Jul 10 11:23:25 2012 -0700
i965/msaa: Work around problems with null render targets on Gen6.
On Gen6, multisampled null render targets don't seem to work
properly--they cause the GPU to hang. So, as a workaround, we render
into a dummy color buffer.
Fortunately this situation (multisampled rendering without a color
buffer) is rare, and we don't have to waste too much memory, because
we can give the workaround buffer a very small pitch.
Fixes piglit test EXT_framebuffer_multisample/no-color {2,4}
depth-computed * on Gen6.
Reviewed-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_context.h |6 +++
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 47 --
2 files changed, 49 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index b4868fe..c179c69 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -971,6 +971,12 @@ struct brw_context
drm_intel_bo *scratch_bo;
+ /**
+ * Buffer object used in place of multisampled null render targets on
+ * Gen6. See brw_update_null_renderbuffer_surface().
+ */
+ drm_intel_bo *multisampled_null_render_target_bo;
+
/** Offset in the program cache to the WM program */
uint32_t prog_offset;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index c2e629c..9607828 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -982,6 +982,10 @@ brw_update_null_renderbuffer_surface(struct brw_context
*brw, unsigned int unit)
struct intel_context *intel = brw-intel;
struct gl_context *ctx = intel-ctx;
uint32_t *surf;
+ unsigned surface_type = BRW_SURFACE_NULL;
+ drm_intel_bo *bo = NULL;
+ unsigned pitch_minus_1 = 0;
+ uint32_t multisampling_state = 0;
/* _NEW_BUFFERS */
const struct gl_framebuffer *fb = ctx-DrawBuffer;
@@ -989,7 +993,34 @@ brw_update_null_renderbuffer_surface(struct brw_context
*brw, unsigned int unit)
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
6 * 4, 32, brw-wm.surf_offset[unit]);
- surf[0] = (BRW_SURFACE_NULL BRW_SURFACE_TYPE_SHIFT |
+ if (fb-Visual.samples 0) {
+ /* On Gen6, null render targets seem to cause GPU hangs when
+ * multisampling. So work around this problem by rendering into dummy
+ * color buffer.
+ *
+ * To decrease the amount of memory needed by the workaround buffer, we
+ * set its pitch to 128 bytes (the width of a Y tile). This means that
+ * the amount of memory needed for the workaround buffer is
+ * (width_in_tiles + height_in_tiles - 1) tiles.
+ *
+ * Note that since the workaround buffer will be interpreted by the
+ * hardware as an interleaved multisampled buffer, we need to compute
+ * width_in_tiles and height_in_tiles by dividing the width and height
+ * by 16 rather than the normal Y-tile size of 32.
+ */
+ unsigned width_in_tiles = ALIGN(fb-Width, 16) / 16;
+ unsigned height_in_tiles = ALIGN(fb-Height, 16) / 16;
+ unsigned size_needed = (width_in_tiles + height_in_tiles - 1) * 4096;
+ brw_get_scratch_bo(intel, brw-wm.multisampled_null_render_target_bo,
+ size_needed);
+ bo = brw-wm.multisampled_null_render_target_bo;
+ surface_type = BRW_SURFACE_2D;
+ pitch_minus_1 = 127;
+ multisampling_state =
+ brw_get_surface_num_multisamples(fb-Visual.samples);
+ }
+
+ surf[0] = (surface_type BRW_SURFACE_TYPE_SHIFT |
BRW_SURFACEFORMAT_B8G8R8A8_UNORM BRW_SURFACE_FORMAT_SHIFT);
if (intel-gen 6) {
surf[0] |= (1 BRW_SURFACE_WRITEDISABLE_R_SHIFT |
@@ -997,7 +1028,7 @@ brw_update_null_renderbuffer_surface(struct brw_context
*brw, unsigned int unit)
1 BRW_SURFACE_WRITEDISABLE_B_SHIFT |
1 BRW_SURFACE_WRITEDISABLE_A_SHIFT);
}
- surf[1] = 0;
+ surf[1] = bo ? bo-offset : 0;
surf[2] = ((fb-Width - 1) BRW_SURFACE_WIDTH_SHIFT |
(fb-Height - 1) BRW_SURFACE_HEIGHT_SHIFT);
@@ -1006,9 +1037,17 @@ brw_update_null_renderbuffer_surface(struct brw_context
*brw, unsigned int unit)
*
* If Surface Type is SURFTYPE_NULL, this field must be TRUE
*/
- surf[3] = BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
- surf[4] = 0;
+ surf[3] = (BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y |
+ pitch_minus_1 BRW_SURFACE_PITCH_SHIFT);
+ surf[4] = multisampling_state;
surf[5] = 0;
+
+ if (bo
Mesa (master): i965/blorp: Simplify check that src/dst width/height match.
Module: Mesa Branch: master Commit: da54d2e576426122009be083ecbfb9eefd8a3799 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=da54d2e576426122009be083ecbfb9eefd8a3799 Author: Paul Berry stereotype...@gmail.com Date: Fri Jul 13 18:30:55 2012 -0700 i965/blorp: Simplify check that src/dst width/height match. When checking that the source and destination dimensions match, we don't need to store the width and height in variables; doing so just risks confusion since right after the check, we do clipping and scissoring, which may alter the width and height. No functional change. Reviewed-by: Chad Versace chad.vers...@linux.intel.com --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp |6 ++ 1 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp index f72145f..eb79359 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp @@ -191,10 +191,8 @@ try_blorp_blit(struct intel_context *intel, fixup_mirroring(mirror_y, dstY0, dstY1); /* Make sure width and height match */ - GLsizei width = srcX1 - srcX0; - GLsizei height = srcY1 - srcY0; - if (width != dstX1 - dstX0) return false; - if (height != dstY1 - dstY0) return false; + if (srcX1 - srcX0 != dstX1 - dstX0) return false; + if (srcY1 - srcY0 != dstY1 - dstY0) return false; /* If the destination rectangle needs to be clipped or scissored, do so. */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/blorp: Fixup scissoring of blits to window system buffers.
Module: Mesa
Branch: master
Commit: 0dbec6ae07e7b3d566cc397ab09caa413e412846
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0dbec6ae07e7b3d566cc397ab09caa413e412846
Author: Paul Berry stereotype...@gmail.com
Date: Fri Jul 13 18:30:55 2012 -0700
i965/blorp: Fixup scissoring of blits to window system buffers.
This patch modifies the order of operations in the blorp engine so
that clipping and scissoring are performed before adjusting the
coordinates to account for the difference in origin convention between
window system buffers and framebuffer objects. Previously, we would
do clipping and scissoring after adjusting for origin conventions, so
we would get scissoring wrong in window system buffers.
Fixes Piglit test fbo-scissor-blit window.
Reviewed-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 28 ++---
1 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index eb79359..038489f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -171,18 +171,6 @@ try_blorp_blit(struct intel_context *intel,
if (src_mt-format != dst_mt-format)
return false;
- /* Account for the fact that in the system framebuffer, the origin is at
-* the lower left.
-*/
- if (read_fb-Name == 0) {
- srcY0 = read_fb-Height - srcY0;
- srcY1 = read_fb-Height - srcY1;
- }
- if (draw_fb-Name == 0) {
- dstY0 = draw_fb-Height - dstY0;
- dstY1 = draw_fb-Height - dstY1;
- }
-
/* Detect if the blit needs to be mirrored */
bool mirror_x = false, mirror_y = false;
fixup_mirroring(mirror_x, srcX0, srcX1);
@@ -213,6 +201,22 @@ try_blorp_blit(struct intel_context *intel,
return true;
}
+ /* Account for the fact that in the system framebuffer, the origin is at
+* the lower left.
+*/
+ if (read_fb-Name == 0) {
+ GLint tmp = read_fb-Height - srcY0;
+ srcY0 = read_fb-Height - srcY1;
+ srcY1 = tmp;
+ mirror_y = !mirror_y;
+ }
+ if (draw_fb-Name == 0) {
+ GLint tmp = draw_fb-Height - dstY0;
+ dstY0 = draw_fb-Height - dstY1;
+ dstY1 = tmp;
+ mirror_y = !mirror_y;
+ }
+
/* Get ready to blit. This includes depth resolving the src and dst
* buffers if necessary.
*/
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Mesa (master): i965/blorp: Don't fall back to swrast when miptrees absent.
Module: Mesa Branch: master Commit: eac4f1a70772c1480778bae2563199c12634893e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=eac4f1a70772c1480778bae2563199c12634893e Author: Paul Berry stereotype...@gmail.com Date: Fri Jul 13 13:59:41 2012 -0700 i965/blorp: Don't fall back to swrast when miptrees absent. Previously, the blorp engine would fall back to swrast if the source or destination of a blit had no associated miptree. This was unnecessary, since _mesa_BlitFramebufferEXT() already takes care of making the blit silently succeed if there are no buffers bound, so the fallback paths could never actually happen in practice. Removing these fallback paths will simplify the implementation of correct DrawBuffers support in blorp. Reviewed-by: Chad Versace chad.vers...@linux.intel.com --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp |8 ++-- 1 files changed, 2 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp index 038489f..eb78fe1 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp @@ -147,19 +147,15 @@ try_blorp_blit(struct intel_context *intel, assert(false); } - /* Validate source */ - if (!src_rb) return false; + /* Find source miptree */ struct intel_renderbuffer *src_irb = intel_renderbuffer(src_rb); struct intel_mipmap_tree *src_mt = src_irb-mt; - if (!src_mt) return false; if (buffer_bit == GL_STENCIL_BUFFER_BIT src_mt-stencil_mt) src_mt = src_mt-stencil_mt; - /* Validate destination */ - if (!dst_rb) return false; + /* Find destination miptree */ struct intel_renderbuffer *dst_irb = intel_renderbuffer(dst_rb); struct intel_mipmap_tree *dst_mt = dst_irb-mt; - if (!dst_mt) return false; if (buffer_bit == GL_STENCIL_BUFFER_BIT dst_mt-stencil_mt) dst_mt = dst_mt-stencil_mt; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/blorp: Rearrange order of blit validation and preparation steps.
Module: Mesa
Branch: master
Commit: fa1d267beb4adb542ea90b805306599f602c38d2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa1d267beb4adb542ea90b805306599f602c38d2
Author: Paul Berry stereotype...@gmail.com
Date: Fri Jul 13 14:21:27 2012 -0700
i965/blorp: Rearrange order of blit validation and preparation steps.
This patch rearranges the order of steps performed by a blorp blit
from this:
- Sync up state of window system buffers.
- Find buffers.
- Find miptrees.
- Make sure buffer formats match.
- Handle mirroring.
- Make sure width and height match.
- Handle clipping/scissoring.
- Account for window system origin conventions.
- Do depth resolves, if applicable.
- Do the blit.
- Record the need for a future HiZ resolve, if applicable.
To this:
- Sync up state of window system buffers.
- Handle mirroring.
- Make sure width and height match.
- Handle clipping/scissoring.
- Account for window system origin conventions.
- Find buffers.
- Make sure buffer formats match.
- Find miptrees.
- Do depth resolves, if applicable.
- Do the blit.
- Record the need for a future HiZ resolve, if applicable.
The steps are the same, but they are now performed in an order that
will make it possible to implement correct DrawBuffers support. Note
that the last four steps are now in a separate function
(do_blorp_blit), since they will need to be executed repeatedly when
DrawBuffers support is added.
Reviewed-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 143 --
1 files changed, 88 insertions(+), 55 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index eb78fe1..0c42e85 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -110,6 +110,61 @@ clip_or_scissor(bool mirror, GLint src_x0, GLint src_x1,
GLint dst_x0,
}
+static struct intel_mipmap_tree *
+find_miptree(GLbitfield buffer_bit, struct gl_renderbuffer *rb)
+{
+ struct intel_renderbuffer *irb = intel_renderbuffer(rb);
+ struct intel_mipmap_tree *mt = irb-mt;
+ if (buffer_bit == GL_STENCIL_BUFFER_BIT mt-stencil_mt)
+ mt = mt-stencil_mt;
+ return mt;
+}
+
+
+static void
+do_blorp_blit(struct intel_context *intel, GLbitfield buffer_bit,
+ struct gl_renderbuffer *src_rb, struct gl_renderbuffer *dst_rb,
+ GLint srcX0, GLint srcY0,
+ GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
+ bool mirror_x, bool mirror_y)
+{
+ struct gl_context *ctx = intel-ctx;
+
+ /* Find source/dst miptrees */
+ struct intel_mipmap_tree *src_mt = find_miptree(buffer_bit, src_rb);
+ struct intel_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_rb);
+
+ /* Get ready to blit. This includes depth resolving the src and dst
+* buffers if necessary.
+*/
+ intel_renderbuffer_resolve_depth(intel, intel_renderbuffer(src_rb));
+ intel_renderbuffer_resolve_depth(intel, intel_renderbuffer(dst_rb));
+
+ /* Do the blit */
+ brw_blorp_blit_params params(brw_context(ctx), src_mt, dst_mt,
+srcX0, srcY0, dstX0, dstY0, dstX1, dstY1,
+mirror_x, mirror_y);
+ brw_blorp_exec(intel, params);
+
+ /* Mark the dst buffer as needing a HiZ resolve if necessary. */
+ intel_renderbuffer_set_needs_hiz_resolve(intel_renderbuffer(dst_rb));
+}
+
+
+static bool
+formats_match(GLbitfield buffer_bit, struct gl_renderbuffer *src_rb,
+ struct gl_renderbuffer *dst_rb)
+{
+ /* Note: don't just check gl_renderbuffer::Format, because in some cases
+* multiple gl_formats resolve to the same native type in the miptree (for
+* example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit
+* between those formats.
+*/
+ return find_miptree(buffer_bit, src_rb)-format ==
+ find_miptree(buffer_bit, dst_rb)-format;
+}
+
+
static bool
try_blorp_blit(struct intel_context *intel,
GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
@@ -123,49 +178,8 @@ try_blorp_blit(struct intel_context *intel,
*/
intel_prepare_render(intel);
- /* Find buffers */
const struct gl_framebuffer *read_fb = ctx-ReadBuffer;
const struct gl_framebuffer *draw_fb = ctx-DrawBuffer;
- struct gl_renderbuffer *src_rb;
- struct gl_renderbuffer *dst_rb;
- switch (buffer_bit) {
- case GL_COLOR_BUFFER_BIT:
- src_rb = read_fb-_ColorReadBuffer;
- dst_rb =
- draw_fb-Attachment[
-draw_fb-_ColorDrawBufferIndexes[0]].Renderbuffer;
- break;
- case GL_DEPTH_BUFFER_BIT:
- src_rb = read_fb-Attachment[BUFFER_DEPTH].Renderbuffer;
- dst_rb = draw_fb-Attachment[BUFFER_DEPTH].Renderbuffer;
- break;
- case GL_STENCIL_BUFFER_BIT:
- src_rb = read_fb-Attachment[BUFFER_STENCIL].Renderbuffer;
- dst_rb = draw_fb-Attachment[BUFFER_STENCIL].Renderbuffer;
- break
Mesa (master): i965/blorp: Handle DrawBuffers properly.
Module: Mesa
Branch: master
Commit: ff9313fac70fa85d051dd4d2b9d3402d39f67cea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff9313fac70fa85d051dd4d2b9d3402d39f67cea
Author: Paul Berry stereotype...@gmail.com
Date: Fri Jul 13 14:59:13 2012 -0700
i965/blorp: Handle DrawBuffers properly.
When the client program uses glDrawBuffer() or glDrawBuffers() to
select more than one color buffer for drawing into, and then performs
a blit, we need to blit into every single enabled draw buffer.
+2 oglconforms.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50407
Reviewed-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 17 ++---
1 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 0c42e85..fbda7b0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -233,13 +233,16 @@ try_blorp_blit(struct intel_context *intel,
switch (buffer_bit) {
case GL_COLOR_BUFFER_BIT:
src_rb = read_fb-_ColorReadBuffer;
- dst_rb =
- draw_fb-Attachment[
-draw_fb-_ColorDrawBufferIndexes[0]].Renderbuffer;
- if (!formats_match(buffer_bit, src_rb, dst_rb))
- return false;
- do_blorp_blit(intel, buffer_bit, src_rb, dst_rb, srcX0, srcY0,
-dstX0, dstY0, dstX1, dstY1, mirror_x, mirror_y);
+ for (unsigned i = 0; i ctx-DrawBuffer-_NumColorDrawBuffers; ++i) {
+ dst_rb = ctx-DrawBuffer-_ColorDrawBuffers[i];
+ if (dst_rb !formats_match(buffer_bit, src_rb, dst_rb))
+return false;
+ }
+ for (unsigned i = 0; i ctx-DrawBuffer-_NumColorDrawBuffers; ++i) {
+ dst_rb = ctx-DrawBuffer-_ColorDrawBuffers[i];
+ do_blorp_blit(intel, buffer_bit, src_rb, dst_rb, srcX0, srcY0,
+ dstX0, dstY0, dstX1, dstY1, mirror_x, mirror_y);
+ }
break;
case GL_DEPTH_BUFFER_BIT:
src_rb = read_fb-Attachment[BUFFER_DEPTH].Renderbuffer;
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Mesa (master): i965/msaa: Remove comment about falsely claiming to support MSAA.
Module: Mesa Branch: master Commit: 4afee38a2f2f9d0aedc02f1d7ba9b780914fce27 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4afee38a2f2f9d0aedc02f1d7ba9b780914fce27 Author: Paul Berry stereotype...@gmail.com Date: Mon Jul 9 16:23:26 2012 -0700 i965/msaa: Remove comment about falsely claiming to support MSAA. Gen6+ hardware now supports MSAA properly. Reviewed-by: Chad Versace chad.vers...@linux.intel.com --- src/mesa/drivers/dri/i965/brw_context.c |5 - 1 files changed, 0 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 5a109e3..62b28be 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -154,11 +154,6 @@ brwCreateContext(int api, ctx-Const.MaxTransformFeedbackSeparateComponents = BRW_MAX_SOL_BINDINGS / BRW_MAX_SOL_BUFFERS; - /* Claim to support 4 multisamples, even though we don't. This is a -* requirement for GL 3.0 that we missed until the last minute. Go ahead and -* claim the limit, so that usage of the 4 multisample-based API that is -* guaranteed in 3.0 succeeds, even though we only rasterize a single sample. -*/ if (intel-gen = 6) ctx-Const.MaxSamples = 4; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/blorp: Properly adjust primitive size for 8x MSAA.
Module: Mesa
Branch: master
Commit: 082874e3891e588f674508be6578f600b35852c4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=082874e3891e588f674508be6578f600b35852c4
Author: Paul Berry stereotype...@gmail.com
Date: Tue Jul 17 21:06:01 2012 -0700
i965/blorp: Properly adjust primitive size for 8x MSAA.
When rendering to an IMS MSAA surface on Gen7, blorp sets up the
rendering pipeline as though it were rendering to a single-sampled
surface; accordingly it must adjust the size of the primitive it sends
down the pipeline to account for the interleaving of samples in an IMS
surface.
This patch modifies the size adjustment code to properly handle 8x
MSAA, which makes room for the extra samples by using an interleaving
pattern that is twice as wide as 4x MSAA.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 21 +
1 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index ae60ae2..f77008d 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1633,10 +1633,23 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
* pipeline as multisampled.
*/
assert(dst_mt-msaa_layout == INTEL_MSAA_LAYOUT_IMS);
- x0 = (x0 * 2) ~3;
- y0 = (y0 * 2) ~3;
- x1 = ALIGN(x1 * 2, 4);
- y1 = ALIGN(y1 * 2, 4);
+ switch (dst_mt-num_samples) {
+ case 4:
+ x0 = (x0 * 2) ~3;
+ y0 = (y0 * 2) ~3;
+ x1 = ALIGN(x1 * 2, 4);
+ y1 = ALIGN(y1 * 2, 4);
+ break;
+ case 8:
+ x0 = (x0 * 4) ~7;
+ y0 = (y0 * 2) ~3;
+ x1 = ALIGN(x1 * 4, 8);
+ y1 = ALIGN(y1 * 2, 4);
+ break;
+ default:
+ assert(!Unrecognized sample count in brw_blorp_blit_params ctor);
+ break;
+ }
wm_prog_key.use_kill = true;
}
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Mesa (master): i965/blorp: Compute sample number correctly for 8x MSAA.
Module: Mesa
Branch: master
Commit: 619471dc322de80942f7dbb29a437890e48155c6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=619471dc322de80942f7dbb29a437890e48155c6
Author: Paul Berry stereotype...@gmail.com
Date: Tue Jul 17 21:06:01 2012 -0700
i965/blorp: Compute sample number correctly for 8x MSAA.
When operating in persample dispatch mode, the blorp engine would
previously assume that subspan N always represented sample N (this is
correct assuming 4x MSAA and a 16-wide dispatch). In order to support
8x MSAA, we must compute which sample is associated with each subspan,
using the Starting Sample Pair Index field in the thread payload.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 55 +++--
1 files changed, 42 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index f77008d..3051d75 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -816,19 +816,48 @@ brw_blorp_blit_program::compute_frag_coords()
brw_ADD(func, Y, stride(suboffset(R1, 5), 2, 4, 0), brw_imm_v(0x11001100));
if (key-persample_msaa_dispatch) {
- /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples 0.
- * Therefore, subspan 0 will represent sample 0, subspan 1 will
- * represent sample 1, and so on.
- *
- * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1, 1,
- * 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to populate a
- * temporary variable with the sequence (0, 1, 2, 3), and then copy from
- * it using vstride=1, width=4, hstride=0.
- *
- * TODO: implement the necessary calculation for 8x multisampling.
- */
- brw_MOV(func, t1, brw_imm_v(0x3210));
- brw_MOV(func, S, stride(t1, 1, 4, 0));
+ switch (key-rt_samples) {
+ case 4:
+ /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
+ * Therefore, subspan 0 will represent sample 0, subspan 1 will
+ * represent sample 1, and so on.
+ *
+ * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
+ * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
+ * populate a temporary variable with the sequence (0, 1, 2, 3), and
+ * then copy from it using vstride=1, width=4, hstride=0.
+ */
+ brw_MOV(func, t1, brw_imm_v(0x3210));
+ brw_MOV(func, S, stride(t1, 1, 4, 0));
+ break;
+ case 8: {
+ /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
+ * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
+ * subspan 1 will represent sample 1, and so on. We can find the
+ * value of N by looking at R0.0 bits 7:6 (Starting Sample Pair
+ * Index) and multiplying by two (since samples are always delivered
+ * in pairs). That is, we compute 2*((R0.0 0xc0) 6) == (R0.0
+ * 0xc0) 5.
+ *
+ * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
+ * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
+ * variable with the sequence (0, 1, 2, 3), and then reading from it
+ * using vstride=1, width=4, hstride=0.
+ */
+ struct brw_reg t1_ud1 = vec1(retype(t1, BRW_REGISTER_TYPE_UD));
+ struct brw_reg r0_ud1 = vec1(retype(R0, BRW_REGISTER_TYPE_UD));
+ brw_AND(func, t1_ud1, r0_ud1, brw_imm_ud(0xc0));
+ brw_SHR(func, t1_ud1, t1_ud1, brw_imm_ud(5));
+ brw_MOV(func, t2, brw_imm_v(0x3210));
+ brw_ADD(func, S, retype(t1_ud1, BRW_REGISTER_TYPE_UW),
+ stride(t2, 1, 4, 0));
+ break;
+ }
+ default:
+ assert(!Unrecognized sample count in
+brw_blorp_blit_program::compute_frag_coords());
+ break;
+ }
s_is_zero = false;
} else {
/* Either the destination surface is single-sampled, or the WM will be
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