Mesa (master): 28 new commits

[GitLab Mirror]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fd265bb4f1fb6770a296ec6c2bf22692bd3054f6
Author: Alyssa Rosenzweig 
Date:   Fri Aug 14 16:13:33 2020 -0400

panfrost: Update CI expectations

The GenXML approach is more stable, so somehow some failing tests
disappeared.

Signed-off-by: Alyssa Rosenzweig 
Reviewed-by: Tomeu Vizoso 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a13351234cae688ef5ed2aeb6c42d719c76c5cd
Author: Alyssa Rosenzweig 
Date:   Fri Aug 14 16:04:47 2020 -0400

panfrost: Drop union mali_attr

Now replaced by the XML translation. I left the comment explaining
instancing since this is still very good information about how to
calculate these fields.

Signed-off-by: Alyssa Rosenzweig 
Reviewed-by: Tomeu Vizoso 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e3fe54e2e01a562f285eb98910b7f4d8ba475f9
Author: Alyssa Rosenzweig 
Date:   Fri Aug 14 16:03:12 2020 -0400

panfrost: Drop hand-rolled pandecode for attribute buffers

Sadly, we lose some of the validation, but indeed, much of the
validation has turend out to be wrong after enough development so... meh

Signed-off-by: Alyssa Rosenzweig 
Reviewed-by: Tomeu Vizoso 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec58cda5da0b7d43b5ff71db4f4f3b85629e6739
Author: Alyssa Rosenzweig 
Date:   Fri Aug 14 15:50:13 2020 -0400

panfrost: Use packs for varying buffers

In addition to better aesthetics, this automatically fixed multiple
instances of accidental CPU readback of GPU buffers -- in a hot path,
too!

Signed-off-by: Alyssa Rosenzweig 
Reviewed-by: Tomeu Vizoso 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9732b64862f57b214e96ce01dba4674808987a22
Author: Alyssa Rosenzweig 
Date:   Fri Aug 14 15:25:04 2020 -0400

panfrost: Remove mali_attr_meta

Signed-off-by: Alyssa Rosenzweig 
Reviewed-by: Tomeu Vizoso 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb2762a837d8da9727a20ee17a86d8609f093e49
Author: Alyssa Rosenzweig 
Date:   Fri Aug 14 15:27:40 2020 -0400

pan/bit: Use packs for Bifrost unit tests

Signed-off-by: Alyssa Rosenzweig 
Reviewed-by: Tomeu Vizoso 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ef205dabd4909c6768f2181fff95fe3f9b451cf
Author: Alyssa Rosenzweig 
Date:   Fri Aug 14 15:23:51 2020 -0400

panfrost: Use MALI_ATTRIBUTE_LENGTH

Removes an unwanted reference to mali_attr_meta.

Signed-off-by: Alyssa Rosenzweig 
Reviewed-by: Tomeu Vizoso 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=59fa26902d56e068de1769a62d8329e6777bba92
Author: Alyssa Rosenzweig 
Date:   Fri Aug 14 15:23:10 2020 -0400

panfrost: Use pack for general varying

Signed-off-by: Alyssa Rosenzweig 
Reviewed-by: Tomeu Vizoso 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c850637f5a988ce92c1dd22809229a1d2c22d37
Author: Alyssa Rosenzweig 
Date:   Fri Aug 14 15:21:20 2020 -0400

panfrost: Use pack for XFB varying

Signed-off-by: Alyssa Rosenzweig 
Reviewed-by: Tomeu Vizoso 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=40b4ee9426f7b2e73e79e68da8c600cc8b4d643a
Author: Alyssa Rosenzweig 
Date:   Fri Aug 14 15:19:25 2020 -0400

panfrost: Factor out general varying case

To avoid hard-to-follow control flow now that we return void.

Signed-off-by: Alyssa Rosenzweig 
Reviewed-by: Tomeu Vizoso 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b805cf9b1f4eaf91bf21ff9d0fe9b86ce7e73041
Author: Alyssa Rosenzweig 
Date:   Fri Aug 14 15:12:39 2020 -0400

panfrost: Pass varying descriptors by reference

Instead of returning by value, as a stepping stone to packing directly.

Signed-off-by: Alyssa Rosenzweig 
Reviewed-by: Tomeu Vizoso 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5a264facfda518bb854737a563242cb36626c22
Author: Alyssa Rosenzweig 
Date:   Fri Aug 14 15:24:35 2020 -0400

panfrost: Reword comment

Avoid referencing 

Mesa (master): 28 new commits

[GitLab Mirror]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed0bea4495aef3dd50fc0c9b8b05836b58a3cfc1
Author: Marek Olšák 
Date:   Mon Feb 24 20:52:06 2020 -0500

glthread: fall back if a param size is non-zero and a pointer param is NULL

So that we don't crash. This is a GL error anyway.

Reviewed-by: Timothy Arceri 
Tested-by: Marge Bot 

Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=57a9c1ee478c5af8cc2f9ffe78b24917deebb1b3
Author: Marek Olšák 
Date:   Mon Feb 24 20:46:02 2020 -0500

glthread: fix a crash with incorrect glShaderSource parameters

Reviewed-by: Timothy Arceri 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c5825b7b6e734c991c65246aff59c04ea8cde102
Author: Marek Olšák 
Date:   Mon Feb 24 20:30:23 2020 -0500

glthread: add custom marshalling for glNamedBuffer(Sub)DataEXT

Reviewed-by: Timothy Arceri 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b8aa5edfc5632e7c7a164566b61c21a6658025b3
Author: Marek Olšák 
Date:   Mon Feb 24 19:58:38 2020 -0500

glthread: merge glBufferSubData and glNamedBufferSubData into 1 set of 
functions

This is a big cleanup.
GL_EXTERNAL_VIRTUAL_MEMORY_BUFFER_AMD also doesn't sync anymore.

Reviewed-by: Timothy Arceri 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8eb03327497f3f0c0147ceea5c22213c4dfd1b13
Author: Marek Olšák 
Date:   Mon Feb 24 19:58:38 2020 -0500

glthread: merge glBufferData and glNamedBufferData into 1 set of functions

This is a big cleanup.
GL_EXTERNAL_VIRTUAL_MEMORY_BUFFER_AMD also doesn't sync anymore.

Reviewed-by: Timothy Arceri 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=93b2ee18a1c00f8b60a60e34cee3743dca45bd47
Author: Marek Olšák 
Date:   Mon Feb 24 19:26:12 2020 -0500

glthread: replace custom glBindBuffer marshalling with generated one

Reviewed-by: Timothy Arceri 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=85276e2c1b8dfdf090a656a7fa1b5613d373515e
Author: Marek Olšák 
Date:   Thu Feb 20 20:40:31 2020 -0500

glthread: sync instead of disabling glthread for non-VBO pointers

Reviewed-by: Timothy Arceri 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=28a2ad7ddf76702a5de56a7bc0d8754b7dbd66a0
Author: Marek Olšák 
Date:   Thu Feb 20 19:28:56 2020 -0500

glthread: track for each VAO whether the user has set a user pointer

This commit mainly adds basic infrastructure for tracking vertex array
state.

If glthread gets a non-VBO pointer, this commit delays disabling
glthread until glDraw is called. The next will change that to "sync"
instead of "disable".

Reviewed-by: Timothy Arceri 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d510e652d46f471a93eae5a07f7e7508633d1040
Author: Marek Olšák 
Date:   Thu Feb 20 18:15:42 2020 -0500

glthread: add marshal_call_after and remove custom glFlush and glEnable code

Instead of implementing marshalling manually, this XML property allows us
to insert additional code into code-generated functions.

Reviewed-by: Timothy Arceri 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4970199d11907833858bbb2700ba313ae12f3a95
Author: Marek Olšák 
Date:   Thu Feb 20 18:10:37 2020 -0500

glthread: don't insert an empty line after (void) cmd;

Reviewed-by: Timothy Arceri 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9eef27920ca7b670225cdc529f200b30140dc39
Author: Marek Olšák 
Date:   Wed Feb 19 22:15:51 2020 -0500

glthread: add support for glMemoryObjectParameteriv, 
glSemaphoreParameterui64v

Reviewed-by: Timothy Arceri 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5c58bbf6ce49199eca076225a7985f3e149ffd3
Author: Marek Olšák 
Date:   Wed Feb 19 22:06:53 2020 -0500

glthread: add support for glCallLists, glPatchParameterfv

Reviewed-by: Timothy Arceri 
Part-of: 

URL:

Mesa (master): 28 new commits

[GitLab Mirror]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa75be05af5cd261c96eddb8a42efa85bbb1ba89
Author: Timur Kristóf 
Date:   Wed Oct 9 10:40:24 2019 +0200

aco: Clean up usages of PhysReg::reg from aco_assembler.

These are not needed anymore, since PhyReg has an implicit
conversion operator that can convert it to unsigned int,
which is equivalent to accessing this field.

Signed-off-by: Timur Kristóf 
Reviewed-by: Daniel Schürmann 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d729d8f1dcc26f39e4b57a093f80a75f8a6f02e7
Author: Timur Kristóf 
Date:   Thu Oct 3 19:32:48 2019 +0200

aco: Add extra assertion for number of FS input VGPRs.

Signed-off-by: Timur Kristóf 
Reviewed-by: Daniel Schürmann 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a89153d03815dfe56d5521276eaad8cd9087ee0d
Author: Timur Kristóf 
Date:   Tue Sep 17 19:59:17 2019 +0200

aco: Fix s_dcache_wb on GFX10.

Signed-off-by: Timur Kristóf 
Reviewed-by: Daniel Schürmann 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=68c9554732d5ea7c2edd6282d6d0b3ba3b7303bb
Author: Rhys Perry 
Date:   Thu Sep 12 15:28:49 2019 +0100

aco: Have s_waitcnt_vscnt write to NULL.

Not sure if this instruction actually writes anything, but LLVM
disassembles a destination and sets it to NULL.

Signed-off-by: Rhys Perry 
Reviewed-By: Timur Kristóf 
Reviewed-by: Daniel Schürmann 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=619f0a71ccdb079ee0ea77a130e92f2ac4d5a75f
Author: Rhys Perry 
Date:   Thu Sep 12 13:25:18 2019 +0100

aco: Use the VOP3-only add/sub GFX10 instructions if needed.

Signed-off-by: Rhys Perry 
Reviewed-By: Timur Kristóf 
Reviewed-by: Daniel Schürmann 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a6bef59b0dd13d790ff0f94745bf02e06b5bb37
Author: Rhys Perry 
Date:   Thu Sep 12 17:42:17 2019 +0200

aco: Initial work to avoid GFX10 hazards.

Currently just breaks up SMEM groups and fixes
FeatureVMEMtoScalarWriteHazard (name from LLVM).

Signed-off-by: Rhys Perry 
Reviewed-By: Timur Kristóf 
Reviewed-by: Daniel Schürmann 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d63c175897e31e2a78eb346362a7c90a2fec5f13
Author: Rhys Perry 
Date:   Tue Oct 8 14:47:00 2019 +0200

aco: pad code with s_code_end on GFX10

Signed-off-by: Rhys Perry 
Reviewed-By: Timur Kristóf 
Reviewed-by: Daniel Schürmann 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=83993f535eb90874ca2256ddbd35bce4e407c13a
Author: Rhys Perry 
Date:   Tue Sep 10 18:11:13 2019 +0100

aco: workaround GFX10 0x3f branch bug

According to LLVM, branches with an offset of 0x3f are buggy.

v2: (by Timur Kristóf)
- extract the GFX10 specific part to its own function

Signed-off-by: Rhys Perry 
Signed-off-by: Timur Kristóf 
Reviewed-by: Daniel Schürmann 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0be1dd856445cf30acc0a7ca74b662f6c21512b8
Author: Timur Kristóf 
Date:   Tue Aug 27 16:27:41 2019 +0200

aco: Fix VS input VGPRs on GFX10.

Signed-off-by: Timur Kristóf 
Reviewed-by: Daniel Schürmann 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c24cd975159b7053aaf51ca3b684f23890a6b07e
Author: Rhys Perry 
Date:   Thu Sep 12 19:55:12 2019 +0100

aco: Assemble opsel in VOP3 instructions.

Signed-off-by: Rhys Perry 
Reviewed-By: Timur Kristóf 
Reviewed-by: Daniel Schürmann 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=818bdab796772da77a363f0a96e8895736591aac
Author: Rhys Perry 
Date:   Thu Sep 12 19:55:36 2019 +0100

aco: Allow literals on VOP3 instructions.

Signed-off-by: Rhys Perry 
Reviewed-by: Daniel Schürmann 
Reviewed-By: Timur Kristóf 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7cf1dcf22db7a0b23a02f5ed42f917ba19d0013f
Author: Timur Kristóf 
Date:   Tue Oct 8 14:43:43 2019 +0200

aco: Support subvector loops in aco_assembler.

These are currently not used, but could be useful later.

Signed-off-by: Timur Kristóf 
Reviewed-by: Daniel Schürmann 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=21f1953383eecf793b2625ddb80cb406e104e24c
Author: Timur Kristóf 
Date:   Tue Oct 8 14:42:52 2019 +0200

aco: Set GFX10 dimensionality on the instructions that need it.

Signed-off-by: Timur Kristóf 
Reviewed-by: Daniel Schürmann 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eaa2a7cdf6655fa163e3ceccbb6052d3755cbd1f
Author: Timur Kristóf 
Date:   Fri Oct 4 15:12:21 2019 +0200

aco: Use ac_get_sampler_dim, delete duplicate code.

Signed-off-by: Timur Kristóf 
Reviewed-by: Daniel Schürmann 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1de9ef9c96c1933b20ba1877cad799794e10359d
Author: Timur Kristóf 
Date:   Thu Sep 26 17:53:17 2019 +0200

 

Mesa (master): 28 new commits

[GitLab Mirror]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b225f1892a677d9b735782c9d6aac4ee5d33c56
Author: Alyssa Rosenzweig 
Date:   Fri Aug 30 13:49:33 2019 -0700

pan/midgard: Remove mir_opt_post_move_eliminate

This optimization depended on RA running before scheduling. It therefore
no longer applies and is now unused.

Signed-off-by: Alyssa Rosenzweig 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d699a17475b5d123e6a22778e8ac6e005774ce92
Author: Alyssa Rosenzweig 
Date:   Fri Aug 30 12:56:55 2019 -0700

pan/midgard: Schedule before RA

This is a tradeoff.

Scheduling before RA means we don't do RA on what-will-become pipeline
registers. Importantly, it means the scheduler is able to reorder
instructions, as registers have not been decided yet.

Unfortunately, it also complicates register spilling, since the spills
themselves won't get bundled optimally and we can only spill twice per
ALU bundle (only one spill per bundle allowed here). It also prevents us
from eliminating dead moves introduced by register allocation, as they
are not dead before RA. The shader-db regressions are from poor spilling
choices introduced by the new bundling requirements. These could be
solved by the combination of a post-scheduler (to combine adjacent
spills into bundles) with a VLIW-aware spill cost calculation.
Nevertheless, the change is small enough that I feel it's worth it to
eat a tiny shader-db regression for the sake of flexibility.

Signed-off-by: Alyssa Rosenzweig 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e06d90c4510eb3a8c42b0e0d1a3ebfd19830069
Author: Alyssa Rosenzweig 
Date:   Fri Aug 30 11:06:33 2019 -0700

pan/midgard: Handle fragment writeout in RA

Rather than using a pile of hacks and awkward constructs in MIR to
ensure the writeout parameter gets written into r0, let's add a
dedicated shadow register class for writeout (interfering with work
register r0) so we can express the writeout condition succintly and
directly.

Signed-off-by: Alyssa Rosenzweig 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=116b17d2d191892aeccf8fd5044a20f5a2d0c64f
Author: Alyssa Rosenzweig 
Date:   Fri Aug 30 14:35:01 2019 -0700

pan/midgard: Do not propagate swizzles into writeout

There's no slot for it; you'll end up writing into the void and
clobbering stuff. Don't. do it.

Signed-off-by: Alyssa Rosenzweig 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb3cc20f42feb4a79c35ca717d4bda2430223d78
Author: Alyssa Rosenzweig 
Date:   Fri Aug 30 11:04:52 2019 -0700

pan/midgard: Fix misc. RA issues

When running the register allocator after scheduling, the MIR looks a
little different, so we need to extend the RA to handle a few of these
extra cases correctly.

Signed-off-by: Alyssa Rosenzweig 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5ba016d3ab1abb9f97e7864fbe5ab96e3877ee7
Author: Alyssa Rosenzweig 
Date:   Fri Aug 30 11:03:44 2019 -0700

pan/midgard: Print MIR by the bundle

After scheduling, we still have valid MIR, but we have additional
bundling annotations which we would like to keep debug, so print these.

Signed-off-by: Alyssa Rosenzweig 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f42cebdd8424d3e0896bd0ddc214b2996bd07a73
Author: Alyssa Rosenzweig 
Date:   Fri Aug 30 11:02:52 2019 -0700

pan/midgard: Print branches in MIR

Rather than a vague "br.??" line, annotate the branch with its target
type (useful for disambiguating discards) and whether it was inverted.

Signed-off-by: Alyssa Rosenzweig 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=59f2cfcbc7d9da9b9e7c45ccc58c5cdaecbe92e8
Author: Alyssa Rosenzweig 
Date:   Fri Aug 30 11:01:57 2019 -0700

pan/midgard: Remove texture_index

This is deadcode.

Signed-off-by: Alyssa Rosenzweig 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=76529836ecf53c977762283cf944a5c123c2b6db
Author: Alyssa Rosenzweig 
Date:   Fri Aug 30 11:01:15 2019 -0700

pan/midgard: Cleanup fragment writeout branch

I'm not sure if this is strictly necessary but it makes debugging easier
and minimizes the diff with the experimental scheduler.

Signed-off-by: Alyssa Rosenzweig 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc2ba8efe96f2b44a6dc3d1e0b06c3a1ee9b8f50
Author: Alyssa Rosenzweig 
Date:   Fri Aug 30 10:53:13 2019 -0700

pan/midgard: Add scheduling barriers

Scheduling occurs on a per-block basis, strongly assuming that a given
block contains at most a single branch. This does not always map to the
source NIR control flow, particularly when discard intrinsics are
involved. The solution is to allow scheduling barriers, which will
terminate a block early in code generation 

Mesa (master): 28 new commits

[Jason Ekstrand]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=561348caa14a849dd50ed1df1d8f7abba7de66f7
Author: Jason Ekstrand 
Date:   Fri Jan 26 11:43:24 2018 -0800

intel/isl: Allow CCS_E on 1010102 formats

On CNL and above, CCS_E supports 1010102 formats and R11G11B10F.  We had
shut them off during early enabling because blorp_copy couldn't handle
them.  Now it can handle 1010102 formats so we can turn them back on.

Reviewed-by: Topi Pohjolainen 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ccb44b8a94654fc827eda784653e607062de3ca1
Author: Jason Ekstrand 
Date:   Fri Jan 26 11:42:35 2018 -0800

intel/blorp: Allow CCS copies of 1010102 formats

Reviewed-by: Topi Pohjolainen 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1978de66f7160b5af8eac8041dfa8c4e0ec3bb83
Author: Jason Ekstrand 
Date:   Fri Jan 26 11:41:02 2018 -0800

intel/blorp: Add support for more format bitcasting

nir_format_bitcast_uint_vec_unmasked can only be used to cast between
formats with uniform channel sizes.  In particular, it cannot handle
10_10_10_2 formats.  By making use of the NIR helper for uint vector
casts, we should now be able to bitcast between any two uint formats so
long as their channels are in RGBA order (possibly with channels
missing).  In order to do this we need to rework the key a bit to pass
the actual formats instead of just the number of bits in each.

Reviewed-by: Topi Pohjolainen 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7998fe268e727c49388aeed854bc0d6ff1ef6a89
Author: Jason Ekstrand 
Date:   Fri Jan 26 11:35:04 2018 -0800

intel/blorp: Use nir_format_bitcast_uint_vec_unmasked

Reviewed-by: Topi Pohjolainen 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=047e68389f0aa56213503e99d31d5357284acdde
Author: Jason Ekstrand 
Date:   Fri Jan 26 11:34:04 2018 -0800

nir/format_convert: Add code for bitcasting vectors

This is a fairly direct port from blorp.  The only real change is that
the nir_format_convert version doesn't assume that everything is a vec4.

Reviewed-by: Topi Pohjolainen 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a6b66a7b26ae1cc01355d3ccfaa604a5c8e1dae5
Author: Jason Ekstrand 
Date:   Fri Jan 26 10:44:51 2018 -0800

intel/blorp: Use ISL instead of bitcast_color_value_to_uint

Reviewed-by: Topi Pohjolainen 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=09ced6542049986f7fe52af8087aec9fc23d9f16
Author: Jason Ekstrand 
Date:   Thu Jun 22 18:45:24 2017 -0700

intel/isl: Add format conversion code

This adds helpers to ISL to convert an isl_color_value to and from
binary data encoded with a given isl_format.  The conversion is done
using ISL's built-in format introspection so it's fairly slow as format
conversions go but it should be fine for a single pixel value.  In
particular, we can use this to convert clear colors.

As a side-effect, we now rely on the sRGB helpers in libmesautil so we
need to tweak the build system a bit.  All prior uses of src/util in ISL
were header-only.

Reviewed-by: Topi Pohjolainen 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8152c60e012605df2ac3a3522974e17c2362b770
Author: Jason Ekstrand 
Date:   Thu Jun 22 23:18:06 2017 -0700

intel/isl/format: Get rid of the ALPHA colorspace

Alpha-only formats are just linear.  There's no need to specially
deliminate them as being in their own colorspace.

Reviewed-by: Topi Pohjolainen 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ab73790efbce705c84c5fd6e598d91ffe02b579
Author: Jason Ekstrand 
Date:   Thu Jun 22 17:12:36 2017 -0700

intel/isl/format: Add field locations informations to channel_layout

Reviewed-by: Topi Pohjolainen 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=96598fbc02d2277a923d10aad168a7a3be0fb08b
Author: Jason Ekstrand 
Date:   Thu Jun 22 16:52:56 2017 -0700

intel/isl/format: Add a column for channel order to the table

Reviewed-by: Topi Pohjolainen 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d08d6a3da88aa3a07e0c867428c93ab7be23c9e4
Author: Jason Ekstrand 
Date:   Fri Jan 20 22:36:30 2017 -0800

i965/blorp: Remove a pile of blorp_blit restrictions

Previously, blorp could only blit 

Mesa (master): 28 new commits

[Jason Ekstrand]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f1ba51b940216b4cb235c869d1636ac42bb0c857
Author: Jason Ekstrand 
Date:   Fri May 26 12:18:49 2017 -0700

i965: Delete intel_resolve_map

Now that we've moved over to the new array mechanism, it's no longer
needed.

Reviewed-by: Topi Pohjolainen 
Acked-by: Chad Versace 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=641405f7970536d7705e39e8c9bb09e3b0b6b165
Author: Jason Ekstrand 
Date:   Fri May 26 12:12:06 2017 -0700

i965: Use the new tracking mechanism for HiZ

This is similar to the previous commit only for HiZ.  For HiZ, apart
from everything looking different, there is really only one functional
change:  We now track the ISL_AUX_STATE_COMPRESSED_NO_CLEAR state.
Previously, if you rendered to a resolved slice of the miptree and then
did a fast-clear with a different clear color, that slice would get
resolved even though it hadn't been fast-cleared.  Now that we can track
COMPRESSED_NO_CLEAR, we know that it doesn't have any blocks in the
"clear" state so we can skip the resolve.

Reviewed-by: Topi Pohjolainen 
Acked-by: Chad Versace 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6c69264edab14c3eadff658835c11938b7339aa
Author: Jason Ekstrand 
Date:   Wed May 31 11:50:24 2017 -0700

i965/miptree: Make level_has_hiz take a const miptree

Acked-by: Chad Versace 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b2c6290b0140797d0e12dd5b358292289d43edc4
Author: Jason Ekstrand 
Date:   Thu May 25 17:18:30 2017 -0700

i965: Wholesale replace the color resolve tracking code

This commit reworks the resolve tracking for CCS and MCS to use the new
isl_aux_state enum.  This should provide much more accurate and easy to
reason about tracking.  In order to understand, for instance, the
intel_miptree_prepare_ccs_access function, one only has to go look at
the giant comment for the isl_aux_state enum and follow the arrows.
Unfortunately, there's no good way to split this up without making a
real mess so there are a bunch of changes in here:

 1) We now do partial resolves.  I really have no idea how this ever
worked before.  So far as I can tell, the only time the old code
ever did a partial resolve was when it was using CCS_D where a
partial resolve and a full resolve are the same thing.

 2) We are now tracking 4 states instead of 3 for CCS_E.  In particular,
we distinguish between compressed with clear and compressed without
clear.  The end result is that you will never get two partial
resolves in a row.

 3) The texture view rules are now more correct.  Previously, we would
only bail if compression was not supported by the destination
format.  However, this is not actually correct.  Not all format
pairs are supported for texture views with CCS even if both support
CCS individually.  Fortunately, ISL has a helper for this.

 4) We are no longer using intel_resolve_map for tracking aux state but
are instead using a simple array of enum isl_aux_state indexed by
level and layer.  This is because, now that we're tracking 4
different states, it's no longer clear which should be the "default"
and array lookups are faster than linked list searches.

 5) The new code is very assert-happy.  Incorrect transitions will now
get caught by assertions rather than by rendering corruption.

Reviewed-by: Topi Pohjolainen 
Acked-by: Chad Versace 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=46fd9248990b1bb596321866cac9e299a310a87c
Author: Jason Ekstrand 
Date:   Thu May 25 15:02:23 2017 -0700

i965: Delete most of the old resolve interface

Reviewed-by: Topi Pohjolainen 
Acked-by: Chad Versace 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f296c22989ff0b6d5c58f2aad89300a4a1a4d64c
Author: Jason Ekstrand 
Date:   Thu May 25 16:09:04 2017 -0700

i965: Use the new get/set_aux_state functions for color clears

Reviewed-by: Topi Pohjolainen 
Acked-by: Chad Versace 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=38563e95d514661a02e4f58f4edb3a699907d92c
Author: Jason Ekstrand 
Date:   Thu May 25 14:50:26 2017 -0700

i965: Move blorp to the new resolve functions

Reviewed-by: Topi Pohjolainen 

Mesa (master): 28 new commits

[Dave Airlie]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c011fe7452f5a0c90e1839e3549efc4c2ac665c1
Author: Dave Airlie 
Date:   Thu Mar 30 08:48:49 2017 +0100

radv: enable tessellation shaders.

This enables tessellation shaders and sets some values for
the maximums.

Reviewed-by: Bas Nieuwenhuizen 
Signed-off-by: Dave Airlie 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb1518e96be44714c3925066379d8394adcc161e
Author: Dave Airlie 
Date:   Thu Mar 30 20:15:23 2017 +0100

radv/ac: setup lds for tessellation

This seems to get lost in the rebases, should fix
the tessellation demos, crash in llvm.

Reviewed-by: Bas Nieuwenhuizen 
Signed-off-by: Dave Airlie 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f0d69af20e881846742d6f25454a17bf332a241
Author: Dave Airlie 
Date:   Thu Mar 30 08:10:06 2017 +0100

radv: add ia_multi_vgt_param tessellation support.

This just ports the relevant radeonsi pieces.

Reviewed-by: Bas Nieuwenhuizen 
Signed-off-by: Dave Airlie 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b4495b71c66700475888142cafcacab626ea7ca4
Author: Dave Airlie 
Date:   Thu Mar 30 08:47:38 2017 +0100

radv/cmd: emit tessellation state.

This emits the tessellation shaders and state to the command stream.

It contains the logic to emit the LS/HS shaders.

Reviewed-by: Bas Nieuwenhuizen 
Signed-off-by: Dave Airlie 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=60fc0544e085bae1d19fa75f9d7806de50c38cef
Author: Dave Airlie 
Date:   Thu Mar 30 08:45:42 2017 +0100

radv/pipeline: handle tessellation shader compilation

So tess shaders have some circular dependencies,

TCS needs the TES primitive mode
TES needs the TCS vertices out

This builds the nir for each shader first to get the
info, executes a tes specific nir pass, then builds
the LLVM shaders.

Reviewed-by: Bas Nieuwenhuizen 
Signed-off-by: Dave Airlie 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aaabdd6bc6ac6e7edf218c473cf2a7a9a02c116e
Author: Dave Airlie 
Date:   Thu Mar 30 08:44:26 2017 +0100

radv/ac: handle writing out tess factors.

This ports the code from radeonsi to build the if/endif,
and ports the tess factor emission code. This code has
an optimisation TODO that we can deal with later.

Reviewed-by: Bas Nieuwenhuizen 
Signed-off-by: Dave Airlie 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=94f9591995f3e682a570400c7b6e6237b89ad113
Author: Dave Airlie 
Date:   Thu Mar 30 08:28:46 2017 +0100

radv/ac: add support for TCS/TES inputs/outputs.

This adds support for the tessellation inputs/outputs to the
shader compiler, this is one of the main pieces of the patch.

It is very similiar to the radeonsi code (post merge we should
consider if there are better sharing opportunities). The main
differences from radeonsi, is that we can have "compact" varyings
for clip/cull/tess factors, and we have to add special handling
for these.

This consists of treating the const index from the deref different
depending on the compactness.

Reviewed-by: Bas Nieuwenhuizen 
Signed-off-by: Dave Airlie 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ab1289b485b660fbf21cddae9e28d0358072a70
Author: Dave Airlie 
Date:   Thu Mar 30 08:26:28 2017 +0100

radv/ac: add clip support for tess eval shader.

As this may be the last shader to emit clip distances.

Reviewed-by: Bas Nieuwenhuizen 
Signed-off-by: Dave Airlie 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=326b9bc6dc43b1fe58ee95ad0022c1005cb756ea
Author: Dave Airlie 
Date:   Thu Mar 30 08:25:18 2017 +0100

radv/ac: hook up tessellation intrinsics.

This just adds support for the nir intrinsics that tessellation uses.

Reviewed-by: Bas Nieuwenhuizen 
Signed-off-by: Dave Airlie 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8ab71b207138439f23d377b07e7c4678426b62b
Author: Dave Airlie 
Date:   Thu Mar 30 08:23:36 2017 +0100

radv/ac: hook up shader information handling for tessellation

This hooks up the tessellation shader info to the nir values
and ctx generated ones.

Mesa (master): 28 new commits

[Timothy Arceri]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3ab09f90f83e09578985fbac39e39121d084b75
Author: Timothy Arceri 
Date:   Tue Feb 7 12:10:19 2017 +1100

util/disk_cache: check cache exists before calling munmap()

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=512c046eddc16bec9c309a3c7b4205d94ffc4ef3
Author: Timothy Arceri 
Date:   Tue Feb 7 09:49:47 2017 +1100

util/disk_cache: add support for removing old versions of the cache

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3342ce452cf33dc70ffad03b676579e0631182b3
Author: Timothy Arceri 
Date:   Mon Feb 6 12:56:08 2017 +1100

util/disk_cache: allow drivers to pass a directory structure

In order to avoid costly fallback recompiles when cache items are
created with an old version of Mesa or for a different gpu on the
same system we want to create directories that look like this:

./{TIMESTAMP}_{LLVM_TIMESTAMP}/{GPU_ID}

Note: The disk cache util will take a single timestamp string, it is
up to the backend to concatenate the llvm string with the mesa string
if applicable.

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=87009681a53436700a477c45cb13272fa4a881fd
Author: Timothy Arceri 
Date:   Mon Feb 6 21:23:31 2017 +1100

mesa: remove cache creation from _mesa_initialize_context()

We will change the way we create the cache directory in the following
patches.

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6602d0401c23211af122f4ef5a86acf5dd9665e7
Author: Timothy Arceri 
Date:   Fri Feb 17 10:16:16 2017 +1100

st/mesa/glsl: build string of dri options and use as input to building sha 
for shaders

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed6153012167fc7176a23f23ee4e9cbaee4a
Author: Timothy Arceri 
Date:   Wed Jun 8 10:18:33 2016 +1000

glsl: reserve parameter storage on cache restore

Since we know how big the list will be we can allocate the storage
upfront.

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1183eb487f65cc8f101578866c404026d6b6dfaa
Author: Timothy Arceri 
Date:   Thu Jun 2 14:13:26 2016 +1000

glsl: don't try to load/store buffer object values in the cache

Also add an assert to catch buffer overflows.

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cad1a9bfde61b634d95041d02f527093fd590677
Author: Timothy Arceri 
Date:   Mon Jun 20 11:09:34 2016 +1000

glsl: don't reprocess or clear UBOs on cache fallback

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=01d1e5a7ad4883d3f3aa7675711a5acd38736325
Author: Timothy Arceri 
Date:   Sat Apr 23 22:34:38 2016 +1000

glsl: skip more uniform initialisation when doing fallback linking

We already pull these values from the metadata cache so no need to
recreate them.

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=794f7326bcc3ffb7ab473d2c10a8c81ff4958167
Author: Timothy Arceri 
Date:   Wed Apr 27 15:41:19 2016 +1000

glsl: don't lose uniform values when falling back to full compile

Here we skip the recreation of uniform storage if we are relinking
after a cache miss. This is improtant because uniform values may
have already been set by the application and we don't want to reset
them.

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e9991f957e296f46cfff40a94ffba0adf2a58e1
Author: Timothy Arceri 
Date:   Sun Nov 20 17:48:27 2016 +1100

glsl: don't reference shader prog data during cache fallback

We already have a reference.

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f19accc5ecdff29c9300f0eceb420c0b1538b24
Author: Timothy Arceri 
Date:   Sun Nov 20 12:47:00 2016 +1100

mesa/glsl: add cache_fallback flag to gl_shader_program_data

This will allow us to skip certain things when falling back to
a full recompile on a cache miss such as avoiding reinitialising
uniforms.

In this change we 

Mesa (master): 28 new commits

[Jordan Justen]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=83e8e07a2b1d15285b35adab6634eeba64371103
Author: Jordan Justen 
Date:   Sat Sep 26 23:50:55 2015 -0700

docs: Add ARB_compute_shader to 11.2.0 release notes

Signed-off-by: Jordan Justen 
Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Kristian Høgsberg 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c0d059c02b58fb2539d992e5143f700c94dc9fb
Author: Jordan Justen 
Date:   Sat Sep 26 23:49:52 2015 -0700

docs: Mark ARB_compute_shader as done for i965

Signed-off-by: Jordan Justen 
Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Kristian Høgsberg 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d04612b60d98ff785646affaffc3d7243deecb74
Author: Jordan Justen 
Date:   Wed Sep 2 15:47:33 2015 -0700

i965: Enable ARB_compute_shader extension on supported hardware

Enable ARB_compute_shader on gen7+, on hardware that supports the
OpenGL 4.3 requirements of a local group size of 1024.

With SIMD16 support, this is limited to Ivy Bridge and Haswell.

Broadwell will work with a local group size up to 896 on SIMD16
meaning programs that use this size or lower should run when setting
MESA_EXTENSION_OVERRIDE=GL_ARB_compute_shader.

Signed-off-by: Jordan Justen 
Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Kristian Høgsberg 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e288b4a133f1ea8208cd219545a72805ed5a91c6
Author: Jordan Justen 
Date:   Sat Oct 10 13:01:03 2015 -0700

i965/nir: Implement shared variable atomic operations

v3:
 * Update based on latest SSBO code (Iago)

Signed-off-by: Jordan Justen 
Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Kristian Høgsberg 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d584b2313e9ab992d4d9a8f966cf547b52d48efc
Author: Jordan Justen 
Date:   Sat Oct 10 12:25:39 2015 -0700

nir: Add nir intrinsics for shared variable atomic operations

v3:
 * Update min/max based on latest SSBO code (Iago)

Signed-off-by: Jordan Justen 
Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Kristian Høgsberg 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc21a7c26ea7b49031e4f33dcac5e2a297d2a6f3
Author: Jordan Justen 
Date:   Sat Oct 10 11:30:33 2015 -0700

glsl: Disable several optimizations on shared variables

Shared variables can be accessed by other threads within the same
local workgroup. This prevents us from performing certain
optimizations with shared variables.

Signed-off-by: Jordan Justen 
Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Kristian Høgsberg 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f821a3ec4f8dda55722f326f26855c2b24ca186c
Author: Jordan Justen 
Date:   Sat Oct 10 09:36:22 2015 -0700

glsl: Buffer atomics are supported for compute shaders

Signed-off-by: Jordan Justen 
Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Kristian Høgsberg 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7333593cf3141e61610f25f86e8b5282c8db099e
Author: Jordan Justen 
Date:   Sat Oct 10 07:55:42 2015 -0700

glsl: Translate atomic intrinsic functions on shared variables

When an intrinsic atomic operation is used on a shared variable, we
translate it to a new 'shared variable' specific intrinsic function
call.

For example, a call to __intrinsic_atomic_add when used on a shared
variable will be translated to a call to
__intrinsic_atomic_add_shared.

v3:
 * Fix stale comments copied from SSBOs (Iago)

Signed-off-by: Jordan Justen 
Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Kristian Høgsberg 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=614ad9b40b9412e243f4d86bcd7cb0952c42c46f
Author: Jordan Justen 
Date:   Tue Nov 17 10:55:26 2015 -0800

glsl: Check for SSBO variable in check_for_ssbo_store

The compiler probably already blocks this earlier on, but we should be
checking for an SSBO here.

Signed-off-by: Jordan Justen 
Reviewed-by: Iago Toral Quiroga 

Mesa (master): 28 new commits

[Francisco Jerez]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b224290fbf8f4f4ccf933a6281276931ccec9b8
Author: Francisco Jerez curroje...@riseup.net
Date:   Fri Nov 22 18:35:46 2013 -0800

i965/gen7-8: Implement glMemoryBarrier().

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=46b03d5400794736e04eee5d373673309ba286ad
Author: Francisco Jerez curroje...@riseup.net
Date:   Tue Feb 10 15:53:14 2015 +0200

i965: Generalize the update_null_renderbuffer_surface vtbl hook to 
non-renderbuffers.

Null surfaces are going to be useful to have something to point
unbound image units to, as the ARB_shader_image_load_store extension
requires us to behave deterministically in cases where some shader
tries to access an unbound image unit: Invalid stores and atomics are
supposed to be discarded and invalid loads are supposed to return
zero, which is precisely what the null surface does.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=342b7ce7d4383db3f956e207f189376a94b359fe
Author: Francisco Jerez curroje...@riseup.net
Date:   Fri Nov 22 16:08:12 2013 -0800

i965: Allocate binding table space for shader images.

v2: Bump the number of supported image uniforms to 32 (Ken).

Reviewed-by: Paul Berry stereotype...@gmail.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=36a17f0f991323410778392bc2d00f9d911d501b
Author: Francisco Jerez curroje...@riseup.net
Date:   Fri Nov 14 20:30:46 2014 +0200

i965: Don't tile 1D miptrees.

It doesn't really improve locality of texture fetches, quite the
opposite it's a waste of memory bandwidth and space due to tile
alignment.

v2: Check mt-logical_height0 instead of mt-target (Ken).  Add short
comment explaining why they shouldn't be tiled.

Reviewed-by: Neil Roberts n...@linux.intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b40bcd24e0c86fb02c226261c1fe46fb362be217
Author: Francisco Jerez curroje...@riseup.net
Date:   Wed Feb 4 18:37:46 2015 +0200

i965/vec4: Don't set any dependency control bits for F32TO16 on Gen8.

It's expanded to several instructions.

Reviewed-by: Matt Turner matts...@gmail.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aef83957e1e13ecb96df436d53373ecc4cedeb08
Author: Francisco Jerez curroje...@riseup.net
Date:   Fri Feb 6 14:38:20 2015 +0200

i965: Handle negated unsigned immediate values in constant propagation.

Negation of UD/UW sources behaves the same as for D/W sources, taking
the two's complement of the source, except for bitwise logical
operations on Gen8 and up which take the one's complement.  Fixes
crash in a GLSL shader with subtraction of two unsigned values.

Reviewed-by: Matt Turner matts...@gmail.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=64fde7b31c419685aa8ef6060828e21b9a11ef51
Author: Francisco Jerez curroje...@riseup.net
Date:   Tue Feb 3 22:50:06 2015 +0200

i965/vec4: Take into account non-zero reg_offset during register allocation.

Reviewed-by: Matt Turner matts...@gmail.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=78e9043475d4bed8b50f7e413963c960fa0935bb
Author: Francisco Jerez curroje...@riseup.net
Date:   Tue Feb 3 20:34:39 2015 +0200

i965/vec4: Add register classes up to MAX_VGRF_SIZE.

In preparation for some send from GRF instructions that will require
larger payloads.

Reviewed-by: Matt Turner matts...@gmail.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=530445330b403d835a4027b41388b5eea8c2e1ab
Author: Francisco Jerez curroje...@riseup.net
Date:   Tue Feb 3 22:52:37 2015 +0200

i965/vec4: Init mlen for several send from GRF instructions.

Reviewed-by: Matt Turner matts...@gmail.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f878d1b470e5307ec18ca409e73b1a81e8361fa
Author: Francisco Jerez curroje...@riseup.net
Date:   Tue Feb 3 22:42:23 2015 +0200

i965/vec4: Don't infer MRF dependencies for send from GRF instructions.

Reviewed-by: Matt Turner matts...@gmail.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=de666fc102b805707c7033b203c5b76ccbbcef8d
Author: Francisco Jerez curroje...@riseup.net
Date:   Thu Feb 5 22:39:33 2015 +0200

i965/vec4: Fix the scheduler to take into account reads and writes of 
multiple registers.

v2: Avoid nested ternary operators in vec4_instruction::regs_read(). (Matt)

Reviewed-by: Matt Turner matts...@gmail.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ad486077e122c19b603750e19dd678bb7793d5b
Author: Francisco Jerez curroje...@riseup.net
Date:   Thu Feb 5 22:58:03 2015 +0200

i965/vec4: 

Mesa (master): 28 new commits

[Marek Olšák]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1829f9c928836940fa13b12a8b073f09c26dc782
Author: Marek Olšák marek.ol...@amd.com
Date:   Sun Jan 4 17:08:57 2015 +0100

radeonsi: enable LLVM optimizations that assume no NaNs for non-compute 
shaders

v2: complete rewrite

Reviewed-by: Alex Deucher alexander.deuc...@amd.com
Reviewed-by: Tom Stellard thomas.stell...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8185aa9a8e3588fe014faef8afaeae56d45e90b
Author: Marek Olšák marek.ol...@amd.com
Date:   Tue Dec 30 18:41:25 2014 +0100

radeonsi: emit SURFACE_SYNC last

This fixes a case where a transform feedback buffer is fed back as an index
buffer, because SURFACE_SYNC must be after VS_PARTIAL_FLUSH.

Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c9ec6ca7ee30109f0bcf0f3f4bcee6fb30dac81
Author: Marek Olšák marek.ol...@amd.com
Date:   Mon Dec 29 15:09:22 2014 +0100

radeonsi: flush all CB/DB caches unconditionally when changing the 
framebuffer

This is easier to read and will work better with shader image stores.

Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1bbccf5214f95d8e23d6da88f51aae6032cbfe9
Author: Marek Olšák marek.ol...@amd.com
Date:   Mon Dec 29 01:25:48 2014 +0100

radeonsi: change TC cache flushing strategy for textures

Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca9c5b2be5ed6aa34032264432bb5465d37641ed
Author: Marek Olšák marek.ol...@amd.com
Date:   Tue Dec 30 16:45:51 2014 +0100

radeonsi: improve and fix streamout flushing

- we don't usually need to flush TC L2
- we should flush KCACHE
  (not really an issue now since we always flush KCACHE when updating
   descriptors, but it could be a problem if we used CE, which doesn't
   require flushing KCACHE)
- add an explicit VS_PARTIAL_FLUSH flag

Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=18a30c97780bef9c498db915ba5e7debe832f576
Author: Marek Olšák marek.ol...@amd.com
Date:   Mon Dec 29 14:53:11 2014 +0100

radeonsi: use TC L2 for CP DMA operations with shader resources on CIK

So that TC L2 doesn't need to be flushed.

The only problem is with index buffers, which don't use TC.
A simple solution is added that flushes TC L2 before a draw call 
(TC_L2_dirty).

Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=11b76369f53e064bef1bad629f957373c0e93b6c
Author: Marek Olšák marek.ol...@amd.com
Date:   Mon Dec 29 13:22:00 2014 +0100

radeonsi: use TC L2 for updating descriptors on CIK

This allows not flushing TC L2 on CIK later.

Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=02ba7334d35cf8182048c17a149b16f18104c6bf
Author: Marek Olšák marek.ol...@amd.com
Date:   Sun Jan 4 22:16:53 2015 +0100

radeonsi: don't use TC L2 for updating descriptors on SI

It's causing problems, because we mix uncached CP DMA with cached WRITE_DATA
when updating the same memory.

The solution for SI is to use uncached access here, because CP DMA doesn't
support cached access.

CIK will be handled in the next patch.

Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=edf18da85dd3b1865c4faaba650a8fa371b7103c
Author: Marek Olšák marek.ol...@amd.com
Date:   Mon Dec 29 14:45:49 2014 +0100

radeonsi: only flush the right set of caches for CP DMA operations

That's either framebuffer caches or caches for shader resources.
The motivation is that framebuffer caches need to be flushed very rarely
here.

Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=73c2b0d18c51459697d8ec194ecfc4438c98c139
Author: Marek Olšák marek.ol...@amd.com
Date:   Sun Dec 28 23:11:38 2014 +0100

radeonsi: implement separate ICACHE and KCACHE flush for SI

Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0aecf9e2d18804d83473a5cc142297c1bbae04f8
Author: Marek Olšák marek.ol...@amd.com
Date:   Tue Dec 30 13:08:32 2014 +0100

radeonsi: add a combined flag for flushing a framebuffer

Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2bfe9d4538693ebad3c0330a92e432c6c4c5afd3
Author: Marek Olšák marek.ol...@amd.com
Date:   Mon Dec 29 14:02:46 2014 +0100

radeonsi: rename flush flags, split the TC flag into L1 and L2

Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:

Mesa (master): 28 new commits

[Marek Olšák]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f7714e0717250c6737accc6c8259c6d9107fd6e
Author: Marek Olšák marek.ol...@amd.com
Date:   Mon Sep 22 22:12:43 2014 +0200

gallium/rbug: correctly unreference a sampler view

This fixes heap corruption. The sampler view can be bound in the context,
so we cannot call destroy directly.

Reviewed-by: Brian Paul bri...@vmware.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=91ddf49c874829aa5f9d561d1e321651992ca127
Author: Marek Olšák marek.ol...@amd.com
Date:   Mon Sep 22 22:12:10 2014 +0200

gallium/rbug: unlock a mutex in rbug_create_query

Reviewed-by: Brian Paul bri...@vmware.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c94486670805be0f12ade6a7a2e5c324db4cb798
Author: Marek Olšák marek.ol...@amd.com
Date:   Sat Sep 20 12:02:59 2014 +0200

radeonsi: remove old cache flushing code

Reviewed-by: Alex Deucher alexander.deuc...@amd.com
Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd53d53dc664946a445bcb9e26b1819f4b92a32c
Author: Marek Olšák marek.ol...@amd.com
Date:   Sat Sep 20 11:54:46 2014 +0200

radeonsi/compute: do CS partial flush with si_emit_cache_flush

Reviewed-by: Alex Deucher alexander.deuc...@amd.com
Reviewed-by: Tom Stellard thomas.stell...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=604b58b554f00ab9eb06eff47bfd4f859424c0ae
Author: Marek Olšák marek.ol...@amd.com
Date:   Sat Sep 20 11:48:58 2014 +0200

radeonsi/compute: flush caches with si_emit_cache_flush

Reviewed-by: Alex Deucher alexander.deuc...@amd.com
Reviewed-by: Tom Stellard thomas.stell...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=628f8ee1d9dac7d88f6826242b8fb1f271b98efa
Author: Marek Olšák marek.ol...@amd.com
Date:   Sat Sep 20 11:33:06 2014 +0200

radeonsi/compute: directly emit CONTEXT_CONTROL

Reviewed-by: Alex Deucher alexander.deuc...@amd.com
Reviewed-by: Tom Stellard thomas.stell...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc05a9e4e089d66a2ffe8919857ad9660e108c28
Author: Marek Olšák marek.ol...@amd.com
Date:   Thu Sep 18 23:48:04 2014 +0200

radeonsi: properly destroy the GS copy shader and scratch_bo for compute

Cc: 10.2 10.3 mesa-sta...@lists.freedesktop.org
Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=711623f7c8113d43f2d54ebfe5cbed3d406a3c79
Author: Marek Olšák marek.ol...@amd.com
Date:   Thu Sep 18 21:40:02 2014 +0200

radeonsi: release GS rings at context destruction

Cc: 10.2 10.3 mesa-sta...@lists.freedesktop.org
Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2833dc4e4596948b2669a0a7261ba9338395835c
Author: Marek Olšák marek.ol...@amd.com
Date:   Thu Sep 18 21:30:58 2014 +0200

radeonsi: don't use pipe_constant_buffer for GS rings

Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1abb1a97b0559b103c4a458def317c6440491a76
Author: Marek Olšák marek.ol...@amd.com
Date:   Wed Sep 17 22:44:22 2014 +0200

radeonsi: don't pass the context to the shader translator

This should prevent accessing context state there.

Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e29353ff20a2761a5a1caeaed78398557797207c
Author: Marek Olšák marek.ol...@amd.com
Date:   Wed Sep 17 22:17:02 2014 +0200

radeonsi: don't snoop currently-bound GS shader when compiling ES

Instead, pass the layout of GS inputs in memory to the ES using the shader
key. Only 64 bits are needed to represent the layout in the key.

Mixing and matching different VS and GS shaders should now always work.

Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2774abd4cec70d95cb73f83c2c150e9f5171c50d
Author: Marek Olšák marek.ol...@amd.com
Date:   Tue Sep 16 18:45:33 2014 +0200

radeonsi: shorten si_pipe_* prefixes to si_*

This was the original naming convention in r600g and it somehow crept
into radeonsi.

Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c37c16cbc4fd84bbb648cac2189b02633e3f806
Author: Marek Olšák marek.ol...@amd.com
Date:   Tue Sep 16 18:40:07 2014 +0200

radeonsi: merge si_pipe_shader into si_shader

One is part of the other anyway.

Reviewed-by: Michel Dänzer michel.daen...@amd.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=07c0b4d9b779dd43fcd3cfc119b1dc0150ab07d2
Author: Marek Olšák marek.ol...@amd.com
Date:   Fri Sep 19 18:00:49 2014 +0200

radeonsi: disable gl_SampleMask fragment shader output if MSAA is disabled

Mesa (master): 28 new commits

[Marek Olšák]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7435c043988dd83b430f3d3a7ca5a5a1b2f30d61
Merge: bb4c5d72d7c7cb1d9e7016e2c07c36875f30011a 
4d11a6a0c798301863d5b202703dcca37dc24e7c
Author: Marek Olšák mar...@gmail.com
Date:   Fri May 11 16:42:20 2012 +0200

Merge branch 'master' of ssh://git.freedesktop.org/git/mesa/mesa

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb4c5d72d7c7cb1d9e7016e2c07c36875f30011a
Merge: 96956dc5076fc03b9290368ca90e3f3b870ee613 
8dd3e341b337ca2d22bcc0e7548a78a6c36ca77d
Author: Marek Olšák mar...@gmail.com
Date:   Fri May 11 16:38:13 2012 +0200

Merge branch 'gallium-userbuf'

Conflicts:
src/gallium/docs/source/screen.rst
src/gallium/drivers/nv50/nv50_state.c
src/gallium/include/pipe/p_defines.h
src/mesa/state_tracker/st_draw.c

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8dd3e341b337ca2d22bcc0e7548a78a6c36ca77d
Author: Brian Paul bri...@vmware.com
Date:   Mon Apr 30 14:44:26 2012 -0600

svga: check for and skip null vertex buffer pointers

Fixes regressions with google earth and other things.

Reviewed-by: José Fonseca jfons...@vmware.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5752e16e82d4375171d157cb116a81ea025ea7b
Author: Brian Paul bri...@vmware.com
Date:   Mon Apr 30 14:37:12 2012 -0600

softpipe: cast away const to silence warning

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e588dff57a7a1f8c4d4f243cdf0580121fa9843
Author: Brian Paul bri...@vmware.com
Date:   Mon Apr 30 14:36:50 2012 -0600

svga: cast away const to silence warning

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=96863baa42564ce2daa5f4651f1c52f1d281d9a5
Author: Marek Olšák mar...@gmail.com
Date:   Tue May 1 00:11:25 2012 +0200

u_vbuf: set user buffer pointer for drivers which support user buffers

It's not common to end up in u_vbuf and at the same time support user 
buffers
in a driver, but such a combination should work.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c5ff5a41fa63634e2cc8037a0a601c60d233537
Author: Marek Olšák mar...@gmail.com
Date:   Mon Apr 30 20:56:25 2012 +0200

st/mesa: unmap upload buffer after uploading indices and constants

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ed72dd31d45b66e54724dcd20b6875313c3
Author: Marek Olšák mar...@gmail.com
Date:   Sun Apr 29 21:34:43 2012 +0200

st/xorg: don't use user_buffer_create

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=889c9a566c1b0e1d3ef269c53900e5cfbd6d7b45
Author: Marek Olšák mar...@gmail.com
Date:   Sun Apr 29 21:34:18 2012 +0200

st/xa: don't use user_buffer_create

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa20733a622770eaaa941f64d570d7b63d8f37b6
Author: Marek Olšák mar...@gmail.com
Date:   Sun Apr 29 21:33:37 2012 +0200

st/vega: don't use user_buffer_create

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0279d15c990d831c7cc4e76cbe7caeba1347b689
Author: Marek Olšák mar...@gmail.com
Date:   Sun Apr 29 21:32:52 2012 +0200

st/vega: use cso_draw_arrays

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=46fe17930ec71be3489fbb844de2bf16d877437e
Author: Marek Olšák mar...@gmail.com
Date:   Sun Apr 29 21:24:39 2012 +0200

cso: cso_context should install u_vbuf by itself and not st/mesa

so that it's installed in the other state trackers too

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f656607c35c80250f0217b6c03b9312987450f13
Author: Marek Olšák mar...@gmail.com
Date:   Sun Apr 29 20:43:12 2012 +0200

st/xorg: fix compilation - wrong libkms include file

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b5f4b173b2703b7f72dcf33ad4cb00347712733
Author: Marek Olšák mar...@gmail.com
Date:   Thu Apr 26 13:45:29 2012 +0200

gallium/util: stop using user buffers in util_draw_texquad

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ac0683d632347347c2fdbd546da0c7c2effb08a
Author: Marek Olšák mar...@gmail.com
Date:   Thu Apr 26 13:41:33 2012 +0200

gallium: remove pipe_resource::user_ptr

It's unused now.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=65d451d9fa1192c386301ca0b84b6c5cd369f92d
Author: Marek Olšák mar...@gmail.com
Date:   Thu Apr 26 13:39:19 2012 +0200

radeonsi: don't create temporary user buffer for r600_upload_const_buffer

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b7d48cbad86eaac21fce3793da41b46db8be3b4
Author: Marek Olšák mar...@gmail.com
Date:   Tue Apr 24 22:53:05 2012 +0200

gallium: add void *user_buffer to pipe_constant_buffer

This reduces CPU overhead when updating constants.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=01bf5569c44389c1127bbb9e873c8a234ac92ff7
Author: Marek Olšák mar...@gmail.com
Date:   Thu Apr 26 11:19:35 2012 +0200

st/mesa: reorder code in draw_vbo

URL:

Mesa (master): 28 new commits

[Brian Paul]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea0cedce6a199a08b062d6ed5451c79b793e8598
Author: Brian Paul bri...@vmware.com
Date:   Thu Sep 22 17:30:34 2011 -0600

svga: indentation/formatting fixes

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c308c66e2c35f4df25f3ec546ffd21dc37df89a
Author: Brian Paul bri...@vmware.com
Date:   Thu Sep 22 17:19:47 2011 -0600

svga: remove emit_consts() offset parameter

It was always zero.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c6a5134bac6976fff8aa7bb5408bfbea9be9389
Author: Brian Paul bri...@vmware.com
Date:   Thu Sep 22 17:17:34 2011 -0600

svga: s/int/unsigned/ in svga_state_constants.c

Be consistent with other functions in the file.  And add some comments.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c27f24f6f00d632110667a34cb0b213e4fd7f762
Author: Brian Paul bri...@vmware.com
Date:   Thu Sep 22 17:10:24 2011 -0600

svga: s/unit/shader/ and related clean-ups

'shader' is more intuitive.  Also s/int/unsigned/ and add assertions.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f053bf4ae092df9e5ff6ab38caf9867e6fe46bf
Author: Brian Paul bri...@vmware.com
Date:   Thu Sep 22 17:02:59 2011 -0600

svga: clean up return values and error codes

Previously we were using a hodge podge of int vs. pipe_enum and
0 vs. PIPE_OK.  Some functions that always returned PIPE_OK were
made void.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=681f92140c2f4170ec222a8213e0895c7fa8483a
Author: Brian Paul bri...@vmware.com
Date:   Wed Jul 27 16:12:25 2011 -0600

svga: add format translation for DXT/sRGB formats

Without this, apps/tests that tried to use a DXT/sRGB format would die on
a failed assertion (st_texture.c:80).

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b2a69e088416a18e3bb119ea1edb594b06e06fe
Author: Brian Paul bri...@vmware.com
Date:   Wed Jul 27 09:13:32 2011 -0600

svga: test register W component in emit_kil()

Only the XYZ components are checked to be negative by SVGA3DOP_TEXKILL.
GL_ARB_fp requires all four components be checked.  Emit a second texkill
for W if needed.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7d09df0cbc7e4524919a025cdd506b29e2d8b4f1
Author: Brian Paul bri...@vmware.com
Date:   Tue Jul 26 09:19:40 2011 -0600

svga: fix depth/shadow compare for non-projected texcoords

We only need to do the divide by Q step for TXP instructions.
This fixes the incorrectly rendered soft shadow test in Lightsmark.
Along with the previous texture swizzle commit, this also fixes all
the piglit glsl-fs-shadow2d-XX.shader_test failures.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9bd15aef865352b9234fedae76617fc51c71e6d5
Author: Brian Paul bri...@vmware.com
Date:   Mon Jul 25 16:06:45 2011 -0600

svga: implement texture swizzling

This exposes the GL_EXT_texture_swizzle extension and allows the various
depth texture modes to be implemented properly.  This, plus a follow-on
texture/shadow change fixes quite a few piglit GLSL shadow sampler test
failures.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=49a6f5e68eeb6b23bb040cfc1f93befc2f1eb35a
Author: Brian Paul bri...@vmware.com
Date:   Tue Jul 19 14:52:54 2011 -0600

svga: check that we don't exceed input/ouput register limits

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f40e4aac7ab79deb06ff6ab9ae03a896d7a9169
Author: Brian Paul bri...@vmware.com
Date:   Wed Jul 13 10:58:01 2011 -0600

svga: implement point sprite suppport

Emit the SVGA3D_RS_POINTSPRITEENABLE render state.
When sprite_coord_mode=PIPE_SPRITE_COORD_LOWER_LEFT emit extra frag
shader code to invert the Y coordinate of the incoming texcoord.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a41ecab2f371e207901ae4d86918049c5aa
Author: Brian Paul bri...@vmware.com
Date:   Mon Jul 11 10:30:56 2011 -0600

svga: add translation for float formats

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=73e840ab7d5d4f42dabe498b194b388713fdc43b
Author: Brian Paul bri...@vmware.com
Date:   Mon Jun 20 11:07:57 2011 -0600

svga: check to avoid writing beyond end of constant buffer

See bug 688394

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=974b6413f4540d73c21c092cc0a62abb6d546e21
Author: José Fonseca jfons...@vmware.com
Date:   Wed Apr 27 12:02:08 2011 +0100

svga: Cleanup format capability checking.

Accurately describe what operations are supported when a format caps
entry is not advertised by the host, and which formats are never
supported, instead of making ad-hoc and often incorrect assumptions.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ffeed5da6e568836867f09f1acb7ce660d091d4a
Author: José Fonseca jfons...@vmware.com
Date:   Thu Apr 14 13:28:10 2011 +0100

svga: Don't use 

Mesa (master): 28 new commits

[Brian Paul]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b22427911ad27efc1f36faee9462c6082d0417c
Merge: 7e7f8815fbfa21ab2397e673fa19c36603bc7a51 
6749310d3f60df70ad8f82db986871ab9496793b
Author: Brian Paul bri...@vmware.com
Date:   Mon Jan 25 14:46:17 2010 -0700

Merge branch 'mesa_7_7_branch'

Conflicts:

src/mesa/drivers/dri/intel/intel_screen.c
src/mesa/drivers/dri/intel/intel_swapbuffers.c
src/mesa/drivers/dri/r300/r300_emit.c
src/mesa/drivers/dri/r300/r300_ioctl.c
src/mesa/drivers/dri/r300/r300_tex.c
src/mesa/drivers/dri/r300/r300_texstate.c

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6749310d3f60df70ad8f82db986871ab9496793b
Author: Jakob Bornecrantz ja...@vmware.com
Date:   Mon Jan 25 20:07:43 2010 +0100

st/xorg: Fix crash on resize with libkms

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d051af6127d206d165a1034ca0795ce8fdcd389
Author: Igor Oliveira igor.olive...@openbossa.org
Date:   Mon Jan 25 09:53:53 2010 -0700

vega: fix incorrect samplers, textures indexes in blend_bind_samplers()

Fixes fd.o bug 25863.

Signed-off-by: Brian Paul bri...@vmware.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6877c5de3c3ff39da514a74928ea270138cddff9
Author: Jakob Bornecrantz ja...@vmware.com
Date:   Mon Jan 25 12:27:47 2010 +0100

vmware/xorg: Do buffer round-robin logic differently

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b482c4fbe69a807bb69bf92f37e362f818c664d
Author: Jakob Bornecrantz ja...@vmware.com
Date:   Fri Jan 22 18:28:40 2010 +0100

st/xorg: Improve options and print them to log

Set 2D acceleration to off by default
Get fallback debugging from the Xorg config
Also print if 3D acceleration is enabled

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3b783ea294f348bf3424eeb4170dd7f0741519a
Author: Jakob Bornecrantz ja...@vmware.com
Date:   Thu Jan 21 21:32:28 2010 +0100

vmware/xorg: Export pci_probe function for ugly chain-loading

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=36fd55f9f03b00263ee1ccf22bbb50e5ba048e80
Author: Jakob Bornecrantz ja...@vmware.com
Date:   Thu Jan 21 21:23:22 2010 +0100

st/xorg: Export helper function for detecting modesetting

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=16cf7e14a6dee85fadc0ab4e7c066288c3362352
Author: Jakob Bornecrantz ja...@vmware.com
Date:   Thu Jan 21 21:28:14 2010 +0100

st/xorg: Fix warning

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=47d30b0c2c36f952cc14deefb9f937f1b0a9b531
Author: Brian Paul bri...@vmware.com
Date:   Sun Jan 24 18:18:17 2010 -0700

st/mesa: fix int-uint conversion for negative scissor bound values

Based on a patch by Xavier Chantry chantry.xav...@gmail.com:

If x+width or y+height is negative, then maxx or maxy will get a bogus value
when converting that to unsigned. Fix this by setting 0 as minimal value.

This was also triggered by teeworlds, but only with some combination of
resolution and map section. For example upper part of dm2 at 1280x1024.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e88d6fe299cb43eedfae7f0fa3bb14c8086a8cd4
Author: Brian Paul bri...@vmware.com
Date:   Sun Jan 24 17:54:44 2010 -0700

mesa: move _mesa_debug() call earlier in _mesa_Scissor

Part of a patch from Xavier Chantry chantry.xav...@gmail.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fdfa4c85297d5d25e7256bf73e35309b358af86c
Author: Xavier Chantry chantry.xav...@gmail.com
Date:   Sat Jan 23 17:27:21 2010 +0100

st/mesa: fix unsigned/signed breakage in scissor

commit 53174afeeb introduced a portability change that converted GLint x,y
to GLuint. That breaks when x and y are negative, which seems to be allowed,
and which at least one game uses : teeworlds.

Rather than simply reverting the change, it seems possible to convert the
16bit unsigned to GLint so that comparisons are made between signed integers
instead.  This hopefully does not break anything while keeping MSVC happy.

Signed-off-by: Xavier Chantry chantry.xav...@gmail.com
Signed-off-by: Brian Paul bri...@vmware.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e85cb98a169f83e1a1ad7f17cbbedaee0ea47fe1
Author: Vinson Lee v...@vmware.com
Date:   Sun Jan 24 00:17:00 2010 -0800

r200: Silence fprintf format warning.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e02dc139520fab9f7189e0ae390f72ed674bb7d7
Author: Vinson Lee v...@vmware.com
Date:   Sat Jan 23 23:18:33 2010 -0800

x86: Do not build read_rgba_span_x86.S on Mac OS X.

read_rgba_span_x86.S uses the pseudo-ops .hidden and .type which are
not recognized on Mac OS X.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f429b80fffc57a6165b76e9345cf5b9383edd650
Author: Vinson Lee v...@vmware.com
Date:   Sat Jan 23 23:12:34 2010 

Mesa (master): 28 new commits

[Brian Paul]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c9f7a23ef05adfd2ebae56ee9f1b19897a589831
Merge: 6be2bc56af5c0d281d07e427863789e949904db1 
7549a8397b310acf672f97a08c8e7d866cdf492c
Author: Brian Paul bri...@vmware.com
Date:   Thu Sep 24 11:03:16 2009 -0600

Merge branch 'mesa_7_6_branch'

Conflicts:

src/mesa/drivers/dri/r600/r700_assembler.c
src/mesa/drivers/dri/r600/r700_chip.c
src/mesa/drivers/dri/r600/r700_render.c
src/mesa/drivers/dri/r600/r700_vertprog.c
src/mesa/drivers/dri/r600/r700_vertprog.h
src/mesa/drivers/dri/radeon/radeon_span.c

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7549a8397b310acf672f97a08c8e7d866cdf492c
Merge: a64d4516a0d6219dec0b5b0622215918469faecc 
2acd5de22651a3461c0576107c8e8fab1f01469a
Author: Brian Paul bri...@vmware.com
Date:   Thu Sep 24 10:52:15 2009 -0600

Merge branch 'mesa_7_5_branch' into mesa_7_6_branch

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a64d4516a0d6219dec0b5b0622215918469faecc
Author: Brian Paul bri...@vmware.com
Date:   Thu Sep 24 10:26:56 2009 -0600

tgsi/sse: Pass the lodbias, not zero.  More comments.

This fixes the glean/glsl1 texture2D(), with bias test when using SSE.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a491e25b1fa8683f538ed0d67a6389f2cdf7e4bc
Author: Brian Paul bri...@vmware.com
Date:   Wed Sep 23 15:44:37 2009 -0600

mesa: added default case return to silence warning

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=00ddd4f9e9680132872f98f2d18b52dfc30c6f2f
Author: Brian Paul bri...@vmware.com
Date:   Wed Sep 23 15:44:18 2009 -0600

glsl: init var to silence warning

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e44c084be536c021985a8908db4300c764c63bbc
Author: Brian Paul bri...@vmware.com
Date:   Wed Sep 23 15:44:02 2009 -0600

glsl: fix missing initializers warning

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2058dfaa47704abc62aa5aa9719013624f26764d
Author: Andre Maasikas amaasi...@gmail.com
Date:   Wed Sep 23 14:20:59 2009 +0300

r600: add support for CUBE textures, also TXP

seems to work here ...

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=639fb1472d09281a8df3792c9bcbc59cd4424688
Author: Alex Deucher alexdeuc...@gmail.com
Date:   Mon Sep 21 16:48:55 2009 -0400

r600: fix typo in the last commit

128 gprs, 256 reg-based consts

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=28308c92605229129a12a2273dda47c6a2ca4790
Author: Alex Deucher alexdeuc...@gmail.com
Date:   Mon Sep 21 16:30:14 2009 -0400

r600: various cleanups

- max texture size is 8k, but mesa doesn't support
that at the moment.
- attempt to set shader limits to what the hw actually
supports
- clean up some old r300 cruft
- no need to explicitly disable irqs.  This is fixed
in the drm now.

Signed-off-by: Alex Deucher alexdeuc...@gmail.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed91d103477d563f73be3555d1022ec9af073467
Author: Andre Maasikas amaasi...@gmail.com
Date:   Mon Sep 21 10:14:25 2009 -0400

r600: fix some issues with LIT instruction

- MUL_LIT is ALU.Trans instruction
- some Trans instructions can take 3 arguments
- don't clobber dst.x, use dst.z as temp, it'll get written correct
  value in last insn
- respect source swizzles

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=48559c76056e09ca4f9e4f39e9008f6d32ecd5b0
Author: Alex Deucher alexdeuc...@gmail.com
Date:   Sat Sep 19 15:18:42 2009 -0400

r600: fix point sizes

registers takes radius

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=095db818c6c7ed5706b5f31d17d0cb19c03cb67a
Author: Alex Deucher alexdeuc...@gmail.com
Date:   Sat Sep 19 14:46:06 2009 -0400

r600: fix polygon offset

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec14d59afa952b4e53ad268971098584686a6fca
Author: Alex Deucher alexdeuc...@gmail.com
Date:   Tue Sep 15 17:12:03 2009 -0400

radeon: don't build non-r600 span code on r600

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dbec27be856584bc5205c7eeeca2b7e98299d4cb
Author: Alex Deucher alexdeuc...@gmail.com
Date:   Tue Sep 15 16:58:37 2009 -0400

r600: minor span cleanups

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2cd2dc34ac93dd929ec8f01cf1f7f8dfa6b34d0d
Author: Andre Maasikas amaasi...@gmail.com
Date:   Tue Sep 15 11:27:51 2009 -0400

r600: support position_invariant programs

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9437ac9bccd294bd5a8b838e7ca7597e5dc6d5b0
Author: Alex Deucher alexdeuc...@gmail.com
Date:   Mon Sep 14 18:05:15 2009 -0400

r600: add span support for 1D tiles

1D tile span support for depth/stencil/color/textures

Z and stencil buffers are always tiled, so this fixes
sw access to Z and stencil buffers.  color and textures
are currently