Mesa (master): i965: Check CCS_E compatibility for texture view rendering
Module: Mesa
Branch: master
Commit: 9e849eb8bb97259136b40dc2b06f42a81cfd3dae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e849eb8bb97259136b40dc2b06f42a81cfd3dae
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Thu Oct 26 16:05:52 2017 -0700
i965: Check CCS_E compatibility for texture view rendering
Only use CCS_E to render to a texture that is CCS_E-compatible with the
original texture's miptree (linear) format. This prevents render
operations from writing data that can't be decoded with the original
miptree format.
On Gen10, with the new CCS_E-enabled formats handled, this enables the
driver to pass the arb_texture_view-rendering-formats piglit test.
v2. Add a TODO for texturing. (Jason)
Cc: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.ch...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 29 +--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index a850f4d17b..82f5a814a1 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -241,6 +241,27 @@ intel_miptree_supports_hiz(const struct brw_context *brw,
}
}
+/**
+ * Return true if the format that will be used to access the miptree is
+ * CCS_E-compatible with the miptree's linear/non-sRGB format.
+ *
+ * Why use the linear format? Well, although the miptree may be specified with
+ * an sRGB format, the usage of that color space/format can be toggled. Since
+ * our HW tends to support more linear formats than sRGB ones, we use this
+ * format variant for check for CCS_E compatibility.
+ */
+static bool
+format_ccs_e_compat_with_miptree(const struct gen_device_info *devinfo,
+ const struct intel_mipmap_tree *mt,
+ enum isl_format access_format)
+{
+ assert(mt->aux_usage == ISL_AUX_USAGE_CCS_E);
+
+ mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
+ enum isl_format isl_format = brw_isl_format_for_mesa_format(linear_format);
+ return isl_formats_are_ccs_e_compatible(devinfo, isl_format, access_format);
+}
+
static bool
intel_miptree_supports_ccs_e(struct brw_context *brw,
const struct intel_mipmap_tree *mt)
@@ -2545,6 +2566,7 @@ can_texture_with_ccs(struct brw_context *brw,
if (mt->aux_usage != ISL_AUX_USAGE_CCS_E)
return false;
+ /* TODO: Replace with format_ccs_e_compat_with_miptree for better perf. */
if (!isl_formats_are_ccs_e_compatible(>screen->devinfo,
mt->surf.format, view_format)) {
perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
@@ -2662,8 +2684,11 @@ intel_miptree_render_aux_usage(struct brw_context *brw,
return mt->mcs_buf ? ISL_AUX_USAGE_CCS_D : ISL_AUX_USAGE_NONE;
case ISL_AUX_USAGE_CCS_E: {
- /* If the format supports CCS_E, then we can just use it */
- if (isl_format_supports_ccs_e(>screen->devinfo, render_format))
+ /* If the format supports CCS_E and is compatible with the miptree,
+ * then we can use it.
+ */
+ if (format_ccs_e_compat_with_miptree(>screen->devinfo,
+ mt, render_format))
return ISL_AUX_USAGE_CCS_E;
/* Otherwise, we have to fall back to CCS_D */
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Mesa (master): intel/isl: Disable some gen10 CCS_E formats for now
Module: Mesa
Branch: master
Commit: c7baaafe543ee5d4756fdd034a89fdcc47429a7e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c7baaafe543ee5d4756fdd034a89fdcc47429a7e
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Wed Aug 23 10:51:28 2017 -0700
intel/isl: Disable some gen10 CCS_E formats for now
CannonLake additionally supports R11G11B10_FLOAT and four 10-10-10-2
formats with CCS_E. None of these formats fit within the current
blorp_copy framework so disable them until support is added.
Signed-off-by: Nanley Chery <nanley.g.ch...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/intel/isl/isl_format.c | 24
1 file changed, 24 insertions(+)
diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
index fba3ac5e1a..03c591071b 100644
--- a/src/intel/isl/isl_format.c
+++ b/src/intel/isl/isl_format.c
@@ -536,6 +536,30 @@ isl_format_supports_ccs_e(const struct gen_device_info
*devinfo,
if (!format_info[format].exists)
return false;
+ /* For simplicity, only report that a format supports CCS_E if blorp can
+* perform bit-for-bit copies with an image of that format while compressed.
+* This allows ISL users to avoid having to resolve the image before
+* performing such a copy. We may want to change this behavior in the
+* future.
+*
+* R11G11B10_FLOAT has no equivalent UINT format. Given how blorp_copy
+* currently works, bit-for-bit copy operations are not possible without an
+* intermediate resolve.
+*/
+ if (format == ISL_FORMAT_R11G11B10_FLOAT)
+ return false;
+
+ /* blorp_copy currently doesn't support formats with different bit-widths
+* per-channel. Until that support is added, report that these formats don't
+* support CCS_E. FIXME: Add support for these formats.
+*/
+ if (format == ISL_FORMAT_B10G10R10A2_UNORM ||
+ format == ISL_FORMAT_B10G10R10A2_UNORM_SRGB ||
+ format == ISL_FORMAT_R10G10B10A2_UNORM ||
+ format == ISL_FORMAT_R10G10B10A2_UINT) {
+ return false;
+ }
+
return format_gen(devinfo) >= format_info[format].ccs_e;
}
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Mesa (master): i965/miptree: Zero-initialize CCS_D buffers
Module: Mesa
Branch: master
Commit: 8a9491058da72ee2df75da25bb147010a451fb68
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a9491058da72ee2df75da25bb147010a451fb68
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Wed May 2 09:38:47 2018 -0700
i965/miptree: Zero-initialize CCS_D buffers
Before this patch, the aux_state was actually AUX_INVALID because the BO
was never defined. This was fine on single slice miptrees because we
would fast-clear the resource right after creation. For multi-slice
miptrees on SKL+ however, this results in undefined behavior when
accessing a non-base slice. Here's a specific example:
1) Fast clear level 0
* Undefined CCS_D buffer allocated in "PASS_THROUGH" state.
* Level 0 transitions to the CLEAR state.
2) Render to level 1
* Level 1 may have a 2-bit pattern of 2's.
* Rendering with a 2 in the CCS is undefined.
Cc: <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index dd851ff9b5..c01a71d445 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1801,13 +1801,11 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* A CCS value of 0 indicates that the corresponding block is in the
* pass-through state which is what we want.
*
-* For CCS_D, on the other hand, we don't care as we're about to perform a
-* fast-clear operation. In that case, being hot in caches more useful.
+* For CCS_D, do the same thing. On gen9+, this avoids having any undefined
+* bits in the aux buffer.
*/
- const uint32_t alloc_flags = mt->aux_usage == ISL_AUX_USAGE_CCS_E ?
-BO_ALLOC_ZEROED : BO_ALLOC_BUSY;
- mt->aux_buf = intel_alloc_aux_buffer(brw, "ccs-miptree",
-_ccs_surf, alloc_flags, mt);
+ mt->aux_buf = intel_alloc_aux_buffer(brw, "ccs-miptree", _ccs_surf,
+BO_ALLOC_ZEROED, mt);
if (!mt->aux_buf) {
free(aux_state);
return false;
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Mesa (master): intel/blorp: Add a NO_UPDATE_CLEAR_COLOR batch flag
Module: Mesa
Branch: master
Commit: 02f5512fed2e6fc2b92a32623fb979117d41239b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=02f5512fed2e6fc2b92a32623fb979117d41239b
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Thu Apr 26 17:09:29 2018 -0700
intel/blorp: Add a NO_UPDATE_CLEAR_COLOR batch flag
Allow callers to handle updating the indirect clear color buffer
themselves. This can reduce the number of clear color updates in the
case where a caller performs multiple fast clears with the same clear
color.
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/intel/blorp/blorp.h | 5 +
src/intel/blorp/blorp_genX_exec.h | 6 --
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index 4626f2f83c..f22110bc84 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -72,6 +72,11 @@ enum blorp_batch_flags {
/* This flag indicates that the blorp call should be predicated. */
BLORP_BATCH_PREDICATE_ENABLE = (1 << 1),
+
+ /* This flag indicates that blorp should *not* update the indirect clear
+* color buffer.
+*/
+ BLORP_BATCH_NO_UPDATE_CLEAR_COLOR = (1 << 2),
};
struct blorp_batch {
diff --git a/src/intel/blorp/blorp_genX_exec.h
b/src/intel/blorp/blorp_genX_exec.h
index 593521b95c..446743b591 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1700,8 +1700,10 @@ blorp_update_clear_color(struct blorp_batch *batch,
static void
blorp_exec(struct blorp_batch *batch, const struct blorp_params *params)
{
- blorp_update_clear_color(batch, >dst, params->fast_clear_op);
- blorp_update_clear_color(batch, >depth, params->hiz_op);
+ if (!(batch->flags & BLORP_BATCH_NO_UPDATE_CLEAR_COLOR)) {
+ blorp_update_clear_color(batch, >dst, params->fast_clear_op);
+ blorp_update_clear_color(batch, >depth, params->hiz_op);
+ }
#if GEN_GEN >= 8
if (params->hiz_op != ISL_AUX_OP_NONE) {
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Mesa (master): i965/miptree: Drop the mt param from alloc_aux_buffer
Module: Mesa
Branch: master
Commit: beed9c4550c1c65fed97c539ade023a66a679d15
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=beed9c4550c1c65fed97c539ade023a66a679d15
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Wed May 2 14:30:17 2018 -0700
i965/miptree: Drop the mt param from alloc_aux_buffer
Drop an unused parameter.
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index d9a8c0f848..ccde5beb3c 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1659,8 +1659,7 @@ static struct intel_miptree_aux_buffer *
intel_alloc_aux_buffer(struct brw_context *brw,
const struct isl_surf *aux_surf,
bool wants_memset,
- uint8_t memset_value,
- struct intel_mipmap_tree *mt)
+ uint8_t memset_value)
{
struct intel_miptree_aux_buffer *buf = calloc(sizeof(*buf), 1);
if (!buf)
@@ -1766,7 +1765,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
*
* Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
*/
- mt->aux_buf = intel_alloc_aux_buffer(brw, _mcs_surf, true, 0xFF, mt);
+ mt->aux_buf = intel_alloc_aux_buffer(brw, _mcs_surf, true, 0xFF);
if (!mt->aux_buf) {
free(aux_state);
return false;
@@ -1810,7 +1809,7 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* For CCS_D, do the same thing. On gen9+, this avoids having any undefined
* bits in the aux buffer.
*/
- mt->aux_buf = intel_alloc_aux_buffer(brw, _ccs_surf, true, 0, mt);
+ mt->aux_buf = intel_alloc_aux_buffer(brw, _ccs_surf, true, 0);
if (!mt->aux_buf) {
free(aux_state);
return false;
@@ -1875,7 +1874,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
isl_surf_get_hiz_surf(>isl_dev, >surf, _hiz_surf);
assert(ok);
- mt->aux_buf = intel_alloc_aux_buffer(brw, _hiz_surf, false, 0, mt);
+ mt->aux_buf = intel_alloc_aux_buffer(brw, _hiz_surf, false, 0);
if (!mt->aux_buf) {
free(aux_state);
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Mesa (master): i965/miptree: Drop the name param from alloc_aux_buffer
Module: Mesa
Branch: master
Commit: 3dd7f600e04a3dd758e57b8ff70ba242b491580a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3dd7f600e04a3dd758e57b8ff70ba242b491580a
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Tue May 1 14:35:35 2018 -0700
i965/miptree: Drop the name param from alloc_aux_buffer
A name of "aux-miptree" should be sufficient.
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index bf0731f1f3..931f71f6d9 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1657,7 +1657,6 @@ intel_miptree_copy_teximage(struct brw_context *brw,
static struct intel_miptree_aux_buffer *
intel_alloc_aux_buffer(struct brw_context *brw,
- const char *name,
const struct isl_surf *aux_surf,
uint32_t alloc_flags,
bool wants_memset,
@@ -1684,7 +1683,7 @@ intel_alloc_aux_buffer(struct brw_context *brw,
* Therefore one can pass the ISL dimensions in terms of bytes instead of
* trying to recalculate based on different format block sizes.
*/
- buf->bo = brw_bo_alloc_tiled(brw->bufmgr, name, size,
+ buf->bo = brw_bo_alloc_tiled(brw->bufmgr, "aux-miptree", size,
I915_TILING_Y, aux_surf->row_pitch,
alloc_flags);
if (!buf->bo) {
@@ -1764,7 +1763,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
*
* Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
*/
- mt->aux_buf = intel_alloc_aux_buffer(brw, "mcs-miptree", _mcs_surf,
+ mt->aux_buf = intel_alloc_aux_buffer(brw, _mcs_surf,
alloc_flags, true, 0xFF, mt);
if (!mt->aux_buf) {
free(aux_state);
@@ -1809,7 +1808,7 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* For CCS_D, do the same thing. On gen9+, this avoids having any undefined
* bits in the aux buffer.
*/
- mt->aux_buf = intel_alloc_aux_buffer(brw, "ccs-miptree", _ccs_surf,
+ mt->aux_buf = intel_alloc_aux_buffer(brw, _ccs_surf,
BO_ALLOC_ZEROED, false, 0, mt);
if (!mt->aux_buf) {
free(aux_state);
@@ -1876,7 +1875,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
assert(ok);
const uint32_t alloc_flags = 0;
- mt->aux_buf = intel_alloc_aux_buffer(brw, "hiz-miptree", _hiz_surf,
+ mt->aux_buf = intel_alloc_aux_buffer(brw, _hiz_surf,
alloc_flags, false, 0, mt);
if (!mt->aux_buf) {
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Mesa (master): i965/miptree: Initialize the indirect clear color to zero
Module: Mesa
Branch: master
Commit: 58d99a21f125b4a834dd7af58b4f05a3a601f7c7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=58d99a21f125b4a834dd7af58b4f05a3a601f7c7
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Mon Apr 30 11:30:32 2018 -0700
i965/miptree: Initialize the indirect clear color to zero
The indirect clear color isn't correctly tracked in
intel_miptree::fast_clear_color. The initial value of ::fast_clear_color
is zero, while that of the indirect clear color is undefined.
Topi Pohjolainen discovered this issue with MCS buffers. This issue is
apparent when fast-clearing an MCS buffer for the first time with
glClearColor = {0.0,}. Although the indirect clear color is undefined,
the initial aux state of the MCS is CLEAR and the tracked clear color is
zero, so we avoid updating the indirect clear color with {0.0,}.
Make the indirect clear color match the initial value of
::fast_clear_color.
Note: although we only have to drop HiZ's BO_ALLOC_BUSY flag for gen10+,
we also drop it pre-gen10 to keep things simple. We add this flag back
for pre-gen10 in a later patch.
v2: Add a note about dropping HiZ's BO_ALLOC_BUSY flag (Topi).
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 33 ++-
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index d132b20abe..bf0731f1f3 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -978,11 +978,11 @@ create_ccs_buf_for_image(struct brw_context *brw,
* system with CCS, we don't have the extra space at the end of the aux
* buffer. So create a new bo here that will store that clear color.
*/
- const struct gen_device_info *devinfo = >screen->devinfo;
- if (devinfo->gen >= 10) {
+ if (brw->isl_dev.ss.clear_color_state_size > 0) {
mt->aux_buf->clear_color_bo =
- brw_bo_alloc(brw->bufmgr, "clear_color_bo",
- brw->isl_dev.ss.clear_color_state_size);
+ brw_bo_alloc_tiled(brw->bufmgr, "clear_color_bo",
+brw->isl_dev.ss.clear_color_state_size,
+I915_TILING_NONE, 0, BO_ALLOC_ZEROED);
if (!mt->aux_buf->clear_color_bo) {
free(mt->aux_buf);
mt->aux_buf = NULL;
@@ -1670,9 +1670,9 @@ intel_alloc_aux_buffer(struct brw_context *brw,
uint64_t size = aux_surf->size;
- const struct gen_device_info *devinfo = >screen->devinfo;
- if (devinfo->gen >= 10) {
- /* On CNL, instead of setting the clear color in the SURFACE_STATE, we
+ const bool has_indirect_clear = brw->isl_dev.ss.clear_color_state_size > 0;
+ if (has_indirect_clear) {
+ /* On CNL+, instead of setting the clear color in the SURFACE_STATE, we
* will set a pointer to a dword somewhere that contains the color. So,
* allocate the space for the clear color value here on the aux buffer.
*/
@@ -1693,7 +1693,8 @@ intel_alloc_aux_buffer(struct brw_context *brw,
}
/* Initialize the bo to the desired value */
- if (wants_memset) {
+ const bool needs_memset = wants_memset || has_indirect_clear;
+ if (needs_memset) {
assert(!(alloc_flags & BO_ALLOC_BUSY));
void *map = brw_bo_map(brw, buf->bo, MAP_WRITE | MAP_RAW);
@@ -1701,11 +1702,21 @@ intel_alloc_aux_buffer(struct brw_context *brw,
intel_miptree_aux_buffer_free(buf);
return NULL;
}
- memset(map, memset_value, aux_surf->size);
+
+ /* Memset the aux_surf portion of the BO. */
+ if (wants_memset)
+ memset(map, memset_value, aux_surf->size);
+
+ /* Zero the indirect clear color to match ::fast_clear_color. */
+ if (has_indirect_clear) {
+ memset((char *)map + buf->clear_color_offset, 0,
+brw->isl_dev.ss.clear_color_state_size);
+ }
+
brw_bo_unmap(buf->bo);
}
- if (devinfo->gen >= 10) {
+ if (has_indirect_clear) {
buf->clear_color_bo = buf->bo;
brw_bo_reference(buf->clear_color_bo);
}
@@ -1864,7 +1875,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
isl_surf_get_hiz_surf(>isl_dev, >surf, _hiz_surf);
assert(ok);
- const uint32_t alloc_flags = BO_ALLOC_BUSY;
+ const uint32_t alloc_flags = 0;
mt->aux_buf = intel_alloc_aux_buffer(brw, "hiz-miptree", _hiz_surf,
alloc_flags, false, 0, mt);
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Mesa (master): i965/clear: Drop a stale comment in fast_clear_depth
Module: Mesa
Branch: master
Commit: 43616404be311e787f043f49d0a8341ef54459cb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=43616404be311e787f043f49d0a8341ef54459cb
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Sun Apr 8 14:00:30 2018 -0700
i965/clear: Drop a stale comment in fast_clear_depth
This comment made more sense when it was above the calls to
intel_miptree_slice_set_needs_depth_resolve(). We stopped using these
functions at commit 554f7d6d02931ea45653c8872565d21c1678a6da
("i965: Move depth to the new resolve functions").
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_clear.c | 4
1 file changed, 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
b/src/mesa/drivers/dri/i965/brw_clear.c
index a65839a0a0..24c8b24244 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -228,13 +228,9 @@ brw_fast_clear_depth(struct gl_context *ctx)
}
}
- /* Now, the HiZ buffer contains data that needs to be resolved to the depth
-* buffer.
-*/
intel_miptree_set_aux_state(brw, mt, depth_irb->mt_level,
depth_irb->mt_layer, num_layers,
ISL_AUX_STATE_CLEAR);
-
return true;
}
___
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Mesa (master): i965/blorp: Also skip the fast clear if the clear color differs
Module: Mesa
Branch: master
Commit: f8ac11d69f1a05378896023577d6455764b5cdf2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f8ac11d69f1a05378896023577d6455764b5cdf2
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Tue Mar 27 15:08:53 2018 -0700
i965/blorp: Also skip the fast clear if the clear color differs
If the aux state is CLEAR and clear color value has changed, only the
surface state must be updated. The bit-pattern in the aux buffer is
exactly the same.
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 04155b7d4c..9d57745cc5 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1229,13 +1229,12 @@ do_single_blorp_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
brw_meta_convert_fast_clear_color(brw, irb->mt,
>Color.ClearColor);
- bool same_clear_color =
- !intel_miptree_set_clear_color(brw, irb->mt, clear_color);
+ intel_miptree_set_clear_color(brw, irb->mt, clear_color);
- /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
+ /* If the buffer is already in ISL_AUX_STATE_CLEAR, the clear
* is redundant and can be skipped.
*/
- if (aux_state == ISL_AUX_STATE_CLEAR && same_clear_color)
+ if (aux_state == ISL_AUX_STATE_CLEAR)
return;
DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__,
___
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Mesa (master): i965/blorp: Disable BLORP clear color updates
Module: Mesa Branch: master Commit: edfb57c0a0adacad4ccb42a49c19c14314a09565 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=edfb57c0a0adacad4ccb42a49c19c14314a09565 Author: Nanley Chery <nanley.g.ch...@intel.com> Date: Thu Apr 26 17:13:36 2018 -0700 i965/blorp: Disable BLORP clear color updates With the previous patches, we now update the indirect clear color buffer every time the clear color changes. Avoid redundant updates. Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/mesa/drivers/dri/i965/brw_blorp.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 9d57745cc5..636591c0b7 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -1261,7 +1261,8 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb, brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); struct blorp_batch batch; - blorp_batch_init(>blorp, , brw, 0); + blorp_batch_init(>blorp, , brw, + BLORP_BATCH_NO_UPDATE_CLEAR_COLOR); blorp_fast_clear(, , isl_format, level, irb->mt_layer, num_layers, x0, y0, x1, y1); @@ -1615,7 +1616,8 @@ intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, , start_layer, num_layers, isl_tmp); struct blorp_batch batch; - blorp_batch_init(>blorp, , brw, 0); + blorp_batch_init(>blorp, , brw, +BLORP_BATCH_NO_UPDATE_CLEAR_COLOR); blorp_hiz_op(, , level, start_layer, num_layers, op); blorp_batch_finish(); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Prepare to delete intel_miptree_alloc_ccs()
Module: Mesa
Branch: master
Commit: 6c41a2ef3b72f9465646fea7ac941e8deb1b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c41a2ef3b72f9465646fea7ac941e8deb1b
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Wed May 2 20:05:08 2018 -0700
i965: Prepare to delete intel_miptree_alloc_ccs()
We're going to delete intel_miptree_alloc_ccs() in the next commit. With
that in mind, replace the use of this function in
do_single_blorp_clear() with intel_miptree_alloc_aux() and move the
delayed allocation logic to it's callers.
v2: Duplicate the delayed allocation comment (Topi Pohjolainen).
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 27 ++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +-
3 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index f538cd03bc..2ea13bb743 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1208,7 +1208,7 @@ do_single_blorp_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
*/
if (can_fast_clear && !irb->mt->aux_buf) {
assert(irb->mt->aux_usage == ISL_AUX_USAGE_CCS_D);
- if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
+ if (!intel_miptree_alloc_aux(brw, irb->mt)) {
/* There are a few reasons in addition to out-of-memory, that can
* cause intel_miptree_alloc_non_msrt_mcs to fail. Try to recover by
* falling back to non-fast clear.
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index ccde5beb3c..a1834fe911 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -60,10 +60,6 @@ static void *intel_miptree_map_raw(struct brw_context *brw,
static void intel_miptree_unmap_raw(struct intel_mipmap_tree *mt);
static bool
-intel_miptree_alloc_aux(struct brw_context *brw,
-struct intel_mipmap_tree *mt);
-
-static bool
intel_miptree_supports_mcs(struct brw_context *brw,
const struct intel_mipmap_tree *mt)
{
@@ -791,7 +787,12 @@ intel_miptree_create(struct brw_context *brw,
mt->offset = 0;
- if (!intel_miptree_alloc_aux(brw, mt)) {
+ /* Create the auxiliary surface up-front. CCS_D, on the other hand, can only
+* compress clear color so we wait until an actual fast-clear to allocate
+* it.
+*/
+ if (mt->aux_usage != ISL_AUX_USAGE_CCS_D &&
+ !intel_miptree_alloc_aux(brw, mt)) {
intel_miptree_release();
return NULL;
}
@@ -882,7 +883,12 @@ intel_miptree_create_for_bo(struct brw_context *brw,
if (!(flags & MIPTREE_CREATE_NO_AUX)) {
intel_miptree_choose_aux_usage(brw, mt);
- if (!intel_miptree_alloc_aux(brw, mt)) {
+ /* Create the auxiliary surface up-front. CCS_D, on the other hand, can
+ * only compress clear color so we wait until an actual fast-clear to
+ * allocate it.
+ */
+ if (mt->aux_usage != ISL_AUX_USAGE_CCS_D &&
+ !intel_miptree_alloc_aux(brw, mt)) {
intel_miptree_release();
return NULL;
}
@@ -1776,7 +1782,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
return true;
}
-bool
+static bool
intel_miptree_alloc_ccs(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
@@ -1897,7 +1903,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
* create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
* compress clear color so we wait until an actual fast-clear to allocate it.
*/
-static bool
+bool
intel_miptree_alloc_aux(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
@@ -1919,11 +1925,6 @@ intel_miptree_alloc_aux(struct brw_context *brw,
return true;
case ISL_AUX_USAGE_CCS_D:
- /* Since CCS_D can only compress clear color so we wait until an actual
- * fast-clear to allocate it.
- */
- return true;
-
case ISL_AUX_USAGE_CCS_E:
assert(_mesa_is_format_color_format(mt->format));
assert(mt->surf.samples == 1);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 9adcc5ab0c..aa360fcb35 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -354,7 +354,7 @@ struct intel_mipmap_tree
};
bool
-intel_miptree_alloc_ccs(struct brw_context *brw,
+intel_miptree_alloc_aux(struct brw_context *brw,
struct intel_mipmap_tree *mt);
enum intel_miptree_create_flags {
_
Mesa (master): i965/miptree: Add and use a memset option in alloc_aux_buffer
Module: Mesa
Branch: master
Commit: b58675e93f03eee46de63bb596d4b97561fdaf42
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b58675e93f03eee46de63bb596d4b97561fdaf42
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Mon Apr 30 10:44:01 2018 -0700
i965/miptree: Add and use a memset option in alloc_aux_buffer
Add infrastructure for initializing the clear color BO.
intel_miptree_init_mcs is no longer needed with change.
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 68 ---
1 file changed, 31 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index c01a71d445..d132b20abe 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1655,41 +1655,13 @@ intel_miptree_copy_teximage(struct brw_context *brw,
intel_obj->needs_validate = true;
}
-static bool
-intel_miptree_init_mcs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- int init_value)
-{
- assert(mt->aux_buf != NULL);
-
- /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
-*
-* When MCS buffer is enabled and bound to MSRT, it is required that it
-* is cleared prior to any rendering.
-*
-* Since we don't use the MCS buffer for any purpose other than rendering,
-* it makes sense to just clear it immediately upon allocation.
-*
-* Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
-*/
- void *map = brw_bo_map(brw, mt->aux_buf->bo, MAP_WRITE | MAP_RAW);
- if (unlikely(map == NULL)) {
- fprintf(stderr, "Failed to map mcs buffer into GTT\n");
- intel_miptree_aux_buffer_free(mt->aux_buf);
- mt->aux_buf = NULL;
- return false;
- }
- void *data = map;
- memset(data, init_value, mt->aux_buf->surf.size);
- brw_bo_unmap(mt->aux_buf->bo);
- return true;
-}
-
static struct intel_miptree_aux_buffer *
intel_alloc_aux_buffer(struct brw_context *brw,
const char *name,
const struct isl_surf *aux_surf,
uint32_t alloc_flags,
+ bool wants_memset,
+ uint8_t memset_value,
struct intel_mipmap_tree *mt)
{
struct intel_miptree_aux_buffer *buf = calloc(sizeof(*buf), 1);
@@ -1720,6 +1692,19 @@ intel_alloc_aux_buffer(struct brw_context *brw,
return NULL;
}
+ /* Initialize the bo to the desired value */
+ if (wants_memset) {
+ assert(!(alloc_flags & BO_ALLOC_BUSY));
+
+ void *map = brw_bo_map(brw, buf->bo, MAP_WRITE | MAP_RAW);
+ if (map == NULL) {
+ intel_miptree_aux_buffer_free(buf);
+ return NULL;
+ }
+ memset(map, memset_value, aux_surf->size);
+ brw_bo_unmap(buf->bo);
+ }
+
if (devinfo->gen >= 10) {
buf->clear_color_bo = buf->bo;
brw_bo_reference(buf->clear_color_bo);
@@ -1758,10 +1743,19 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
* to be just used by the GPU.
*/
const uint32_t alloc_flags = 0;
- mt->aux_buf = intel_alloc_aux_buffer(brw, "mcs-miptree",
-_mcs_surf, alloc_flags, mt);
- if (!mt->aux_buf ||
- !intel_miptree_init_mcs(brw, mt, 0xFF)) {
+ /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
+*
+* When MCS buffer is enabled and bound to MSRT, it is required that it
+* is cleared prior to any rendering.
+*
+* Since we don't use the MCS buffer for any purpose other than rendering,
+* it makes sense to just clear it immediately upon allocation.
+*
+* Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
+*/
+ mt->aux_buf = intel_alloc_aux_buffer(brw, "mcs-miptree", _mcs_surf,
+alloc_flags, true, 0xFF, mt);
+ if (!mt->aux_buf) {
free(aux_state);
return false;
}
@@ -1805,7 +1799,7 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* bits in the aux buffer.
*/
mt->aux_buf = intel_alloc_aux_buffer(brw, "ccs-miptree", _ccs_surf,
-BO_ALLOC_ZEROED, mt);
+BO_ALLOC_ZEROED, false, 0, mt);
if (!mt->aux_buf) {
free(aux_state);
return false;
@@ -1871,8 +1865,8 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
assert(ok);
const uint32_t alloc_flags = BO_ALLOC_BUSY;
- mt->aux_buf = intel_alloc_aux_buffer(brw, "hiz-miptree",
-_hiz_surf, alloc_flags, mt);
+ mt->aux_buf = intel_alloc_aux_buff
Mesa (master): i965: Update the indirect buffer in set_clear_color
Module: Mesa
Branch: master
Commit: 82849fb6d54629a0c7c5a118ed8780a3ae573b25
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=82849fb6d54629a0c7c5a118ed8780a3ae573b25
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Sun Apr 8 14:00:30 2018 -0700
i965: Update the indirect buffer in set_clear_color
For depth buffers, we avoid fast-clearing if the aux_state is already
CLEAR. We do the same for color buffers only if the clear color
doesn't change. We require that the clear colors match because, in
that case, we don't update the indirect clear color outside of BLORP.
Update the indirect clear color for color buffers as well. We'll
enable the same depth buffer optimization for color buffers in a
later patch.
Note that we're now actually updating the indirect clear color twice
in the case where we use BLORP to perform the fast-clear. This is
only temporary. In later patches, we'll prevent BLORP from performing
the update.
v2: Add more context to the commit message (Topi).
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_clear.c | 37 ---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 13 ++
2 files changed, 13 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
b/src/mesa/drivers/dri/i965/brw_clear.c
index ba79447fc8..a65839a0a0 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -108,7 +108,6 @@ brw_fast_clear_depth(struct gl_context *ctx)
struct intel_mipmap_tree *mt = depth_irb->mt;
struct gl_renderbuffer_attachment *depth_att =
>Attachment[BUFFER_DEPTH];
const struct gen_device_info *devinfo = >screen->devinfo;
- bool same_clear_value = true;
if (devinfo->gen < 6)
return false;
@@ -215,42 +214,6 @@ brw_fast_clear_depth(struct gl_context *ctx)
const union isl_color_value clear_color = { .f32 = {clear_value, } };
intel_miptree_set_clear_color(brw, mt, clear_color);
- same_clear_value = false;
- }
-
- bool need_clear = false;
- for (unsigned a = 0; a < num_layers; a++) {
- enum isl_aux_state aux_state =
- intel_miptree_get_aux_state(mt, depth_irb->mt_level,
- depth_irb->mt_layer + a);
-
- if (aux_state != ISL_AUX_STATE_CLEAR) {
- need_clear = true;
- break;
- }
- }
-
- if (!need_clear) {
- if (devinfo->gen >= 10 && !same_clear_value) {
- /* Before gen10, it was enough to just update the clear value in the
- * miptree. But on gen10+, we let blorp update the clear value state
- * buffer when doing a fast clear. Since we are skipping the fast
- * clear here, we need to update the clear color ourselves.
- */
- uint32_t clear_offset = mt->aux_buf->clear_color_offset;
- union isl_color_value clear_color = { .f32 = { clear_value, } };
-
- /* We can't update the clear color while the hardware is still using
- * the previous one for a resolve or sampling from it. So make sure
- * that there's no pending commands at this point.
- */
- brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
- for (int i = 0; i < 4; i++) {
-brw_store_data_imm32(brw, mt->aux_buf->clear_color_bo,
- clear_offset + i * 4, clear_color.u32[i]);
- }
- brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
- }
}
for (unsigned a = 0; a < num_layers; a++) {
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 88db0fc80b..0c7c89a9ac 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3728,6 +3728,19 @@ intel_miptree_set_clear_color(struct brw_context *brw,
{
if (memcmp(>fast_clear_color, _color, sizeof(clear_color)) != 0) {
mt->fast_clear_color = clear_color;
+ if (mt->aux_buf->clear_color_bo) {
+ /* We can't update the clear color while the hardware is still using
+ * the previous one for a resolve or sampling from it. Make sure that
+ * there are no pending commands at this point.
+ */
+ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
+ for (int i = 0; i < 4; i++) {
+brw_store_data_imm32(brw, mt->aux_buf->clear_color_bo,
+ mt->aux_buf->clear_color_offset + i * 4,
+ mt->fast_clear_color.u32[i]);
+ }
+ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
+ }
brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
return true;
}
__
Mesa (master): i965: Use set_clear_color for depth miptrees
Module: Mesa
Branch: master
Commit: 6f609ca609f3011b756bb920a7b06946a8a8c0b7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f609ca609f3011b756bb920a7b06946a8a8c0b7
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Thu Apr 26 18:49:19 2018 -0700
i965: Use set_clear_color for depth miptrees
Reduce code duplication now and prevent it in the following commits.
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_clear.c | 3 ++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 13 -
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 -
3 files changed, 2 insertions(+), 19 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
b/src/mesa/drivers/dri/i965/brw_clear.c
index 3d540d6d90..2f61ea8ef1 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -213,7 +213,8 @@ brw_fast_clear_depth(struct gl_context *ctx)
}
}
- intel_miptree_set_depth_clear_value(brw, mt, clear_value);
+ const union isl_color_value clear_color = { .f32 = {clear_value, } };
+ intel_miptree_set_clear_color(brw, mt, clear_color);
same_clear_value = false;
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 506cf73e62..88db0fc80b 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3734,19 +3734,6 @@ intel_miptree_set_clear_color(struct brw_context *brw,
return false;
}
-bool
-intel_miptree_set_depth_clear_value(struct brw_context *brw,
-struct intel_mipmap_tree *mt,
-float clear_value)
-{
- if (mt->fast_clear_color.f32[0] != clear_value) {
- mt->fast_clear_color.f32[0] = clear_value;
- brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
- return true;
- }
- return false;
-}
-
union isl_color_value
intel_miptree_get_clear_color(const struct gen_device_info *devinfo,
const struct intel_mipmap_tree *mt,
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 2d827afa53..42f73ba1f9 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -716,11 +716,6 @@ intel_miptree_get_clear_color(const struct gen_device_info
*devinfo,
struct brw_bo **clear_color_bo,
uint32_t *clear_color_offset);
-bool
-intel_miptree_set_depth_clear_value(struct brw_context *brw,
-struct intel_mipmap_tree *mt,
-float clear_value);
-
#ifdef __cplusplus
}
#endif
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Mesa (master): i965/clear: Remove an early return in fast_clear_depth
Module: Mesa
Branch: master
Commit: 5b315f3ad1451b7c24e29f534cd1c7ed0de0fa77
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b315f3ad1451b7c24e29f534cd1c7ed0de0fa77
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Tue Apr 24 17:16:50 2018 -0700
i965/clear: Remove an early return in fast_clear_depth
Reduce complexity and allow the next patch to delete some code. With
this change, clear operations will still be skipped and setting the
aux_state will cause no side-effects.
Remove the associated comment which implies an early return.
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_clear.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
b/src/mesa/drivers/dri/i965/brw_clear.c
index 2f61ea8ef1..ba79447fc8 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -231,10 +231,6 @@ brw_fast_clear_depth(struct gl_context *ctx)
}
if (!need_clear) {
- /* If all of the layers we intend to clear are already in the clear
- * state then simply updating the miptree fast clear value is sufficient
- * to change their clear value.
- */
if (devinfo->gen >= 10 && !same_clear_value) {
/* Before gen10, it was enough to just update the clear value in the
* miptree. But on gen10+, we let blorp update the clear value state
@@ -255,7 +251,6 @@ brw_fast_clear_depth(struct gl_context *ctx)
}
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
}
- return true;
}
for (unsigned a = 0; a < num_layers; a++) {
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Mesa (master): i965/miptree: Unify aux buffer allocation
Module: Mesa
Branch: master
Commit: bb18af82c30f702788108e67270b3f473dfaec80
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb18af82c30f702788108e67270b3f473dfaec80
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Mon Apr 30 17:00:32 2018 -0700
i965/miptree: Unify aux buffer allocation
There isn't much that changes between the aux allocation functions.
Remove the duplicated code.
v2: Inline the switch statement (Jason).
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 215 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 9 --
2 files changed, 82 insertions(+), 142 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index a1834fe911..b5d7d691ec 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1739,95 +1739,9 @@ intel_alloc_aux_buffer(struct brw_context *brw,
return buf;
}
-static bool
-intel_miptree_alloc_mcs(struct brw_context *brw,
-struct intel_mipmap_tree *mt,
-GLuint num_samples)
-{
- assert(brw->screen->devinfo.gen >= 7); /* MCS only used on Gen7+ */
- assert(mt->aux_buf == NULL);
- assert(mt->aux_usage == ISL_AUX_USAGE_MCS);
-
- /* Multisampled miptrees are only supported for single level. */
- assert(mt->first_level == 0);
- enum isl_aux_state **aux_state =
- create_aux_state_map(mt, ISL_AUX_STATE_CLEAR);
- if (!aux_state)
- return false;
-
- struct isl_surf temp_mcs_surf;
-
- MAYBE_UNUSED bool ok =
- isl_surf_get_mcs_surf(>isl_dev, >surf, _mcs_surf);
- assert(ok);
-
- /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
-*
-* When MCS buffer is enabled and bound to MSRT, it is required that it
-* is cleared prior to any rendering.
-*
-* Since we don't use the MCS buffer for any purpose other than rendering,
-* it makes sense to just clear it immediately upon allocation.
-*
-* Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
-*/
- mt->aux_buf = intel_alloc_aux_buffer(brw, _mcs_surf, true, 0xFF);
- if (!mt->aux_buf) {
- free(aux_state);
- return false;
- }
-
- mt->aux_state = aux_state;
-
- return true;
-}
-
-static bool
-intel_miptree_alloc_ccs(struct brw_context *brw,
-struct intel_mipmap_tree *mt)
-{
- assert(mt->aux_buf == NULL);
- assert(mt->aux_usage == ISL_AUX_USAGE_CCS_E ||
- mt->aux_usage == ISL_AUX_USAGE_CCS_D);
-
- struct isl_surf temp_ccs_surf;
-
- if (!isl_surf_get_ccs_surf(>isl_dev, >surf, _ccs_surf, 0))
- return false;
-
- assert(temp_ccs_surf.size &&
- (temp_ccs_surf.size % temp_ccs_surf.row_pitch == 0));
-
- enum isl_aux_state **aux_state =
- create_aux_state_map(mt, ISL_AUX_STATE_PASS_THROUGH);
- if (!aux_state)
- return false;
-
- /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
-* state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
-*
-*"If Software wants to enable Color Compression without Fast clear,
-*Software needs to initialize MCS with zeros."
-*
-* A CCS value of 0 indicates that the corresponding block is in the
-* pass-through state which is what we want.
-*
-* For CCS_D, do the same thing. On gen9+, this avoids having any undefined
-* bits in the aux buffer.
-*/
- mt->aux_buf = intel_alloc_aux_buffer(brw, _ccs_surf, true, 0);
- if (!mt->aux_buf) {
- free(aux_state);
- return false;
- }
-
- mt->aux_state = aux_state;
-
- return true;
-}
/**
- * Helper for intel_miptree_alloc_hiz() that sets
+ * Helper for intel_miptree_alloc_aux() that sets
* \c mt->level[level].has_hiz. Return true if and only if
* \c has_hiz was set.
*/
@@ -1862,39 +1776,6 @@ intel_miptree_level_enable_hiz(struct brw_context *brw,
return true;
}
-bool
-intel_miptree_alloc_hiz(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
-{
- assert(mt->aux_buf == NULL);
- assert(mt->aux_usage == ISL_AUX_USAGE_HIZ);
-
- enum isl_aux_state **aux_state =
- create_aux_state_map(mt, ISL_AUX_STATE_AUX_INVALID);
- if (!aux_state)
- return false;
-
- struct isl_surf temp_hiz_surf;
-
- MAYBE_UNUSED bool ok =
- isl_surf_get_hiz_surf(>isl_dev, >surf, _hiz_surf);
- assert(ok);
-
- mt->aux_buf = intel_alloc_aux_buffer(brw, _hiz_surf, false, 0);
-
- if (!mt->aux_buf) {
- free(aux_state);
- return false;
- }
-
- for (unsigned level = mt->first_level; level <= mt->last_level; ++level)
- intel_miptree_level_enable_hiz(brw, mt, level);
-
- mt->aux
Mesa (master): i965/miptree: Drop the alloc_flags param from alloc_aux_buffer
Module: Mesa
Branch: master
Commit: 6b1836aabeab3cd4d7d318214d7d2c59386ba7ee
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b1836aabeab3cd4d7d318214d7d2c59386ba7ee
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Wed May 2 12:46:54 2018 -0700
i965/miptree: Drop the alloc_flags param from alloc_aux_buffer
We have enough information to determine the optimal flags internally.
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 29 +--
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 931f71f6d9..d9a8c0f848 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1658,7 +1658,6 @@ intel_miptree_copy_teximage(struct brw_context *brw,
static struct intel_miptree_aux_buffer *
intel_alloc_aux_buffer(struct brw_context *brw,
const struct isl_surf *aux_surf,
- uint32_t alloc_flags,
bool wants_memset,
uint8_t memset_value,
struct intel_mipmap_tree *mt)
@@ -1679,6 +1678,17 @@ intel_alloc_aux_buffer(struct brw_context *brw,
size += brw->isl_dev.ss.clear_color_state_size;
}
+ /* If the buffer needs to be initialised (requiring the buffer to be
+* immediately mapped to cpu space for writing), do not use the gpu access
+* flag which can cause an unnecessary delay if the backing pages happened
+* to be just used by the GPU.
+*/
+ const bool alloc_zeroed = wants_memset && memset_value == 0;
+ const bool needs_memset =
+ !alloc_zeroed && (wants_memset || has_indirect_clear);
+ const uint32_t alloc_flags =
+ alloc_zeroed ? BO_ALLOC_ZEROED : (needs_memset ? 0 : BO_ALLOC_BUSY);
+
/* ISL has stricter set of alignment rules then the drm allocator.
* Therefore one can pass the ISL dimensions in terms of bytes instead of
* trying to recalculate based on different format block sizes.
@@ -1692,7 +1702,6 @@ intel_alloc_aux_buffer(struct brw_context *brw,
}
/* Initialize the bo to the desired value */
- const bool needs_memset = wants_memset || has_indirect_clear;
if (needs_memset) {
assert(!(alloc_flags & BO_ALLOC_BUSY));
@@ -1747,12 +1756,6 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
isl_surf_get_mcs_surf(>isl_dev, >surf, _mcs_surf);
assert(ok);
- /* Buffer needs to be initialised requiring the buffer to be immediately
-* mapped to cpu space for writing. Therefore do not use the gpu access
-* flag which can cause an unnecessary delay if the backing pages happened
-* to be just used by the GPU.
-*/
- const uint32_t alloc_flags = 0;
/* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
*
* When MCS buffer is enabled and bound to MSRT, it is required that it
@@ -1763,8 +1766,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
*
* Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
*/
- mt->aux_buf = intel_alloc_aux_buffer(brw, _mcs_surf,
-alloc_flags, true, 0xFF, mt);
+ mt->aux_buf = intel_alloc_aux_buffer(brw, _mcs_surf, true, 0xFF, mt);
if (!mt->aux_buf) {
free(aux_state);
return false;
@@ -1808,8 +1810,7 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* For CCS_D, do the same thing. On gen9+, this avoids having any undefined
* bits in the aux buffer.
*/
- mt->aux_buf = intel_alloc_aux_buffer(brw, _ccs_surf,
-BO_ALLOC_ZEROED, false, 0, mt);
+ mt->aux_buf = intel_alloc_aux_buffer(brw, _ccs_surf, true, 0, mt);
if (!mt->aux_buf) {
free(aux_state);
return false;
@@ -1874,9 +1875,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
isl_surf_get_hiz_surf(>isl_dev, >surf, _hiz_surf);
assert(ok);
- const uint32_t alloc_flags = 0;
- mt->aux_buf = intel_alloc_aux_buffer(brw, _hiz_surf,
-alloc_flags, false, 0, mt);
+ mt->aux_buf = intel_alloc_aux_buffer(brw, _hiz_surf, false, 0, mt);
if (!mt->aux_buf) {
free(aux_state);
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Mesa (master): Revert "i965: Make the miptree clear color setter take a gl_color_union"
Module: Mesa
Branch: master
Commit: 92a0a87b6f78b316f47132bb8f67c1ba28d3c020
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=92a0a87b6f78b316f47132bb8f67c1ba28d3c020
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Fri Apr 27 12:27:07 2018 -0700
Revert "i965: Make the miptree clear color setter take a gl_color_union"
This reverts commit 1d94aa19877fb702ffacacde28ad7253cce72c97.
The next patch will make depth miptrees use the clear color setter that
was originally being used for color miptrees. Go back to using the
isl_color_value parameter because it's the same type as the
fast_clear_color field used by color and depth miptrees.
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 5 -
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +-
3 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 2ea13bb743..04155b7d4c 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1225,9 +1225,12 @@ do_single_blorp_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
if (can_fast_clear) {
const enum isl_aux_state aux_state =
intel_miptree_get_aux_state(irb->mt, irb->mt_level, irb->mt_layer);
+ union isl_color_value clear_color =
+ brw_meta_convert_fast_clear_color(brw, irb->mt,
+ >Color.ClearColor);
bool same_clear_color =
- !intel_miptree_set_clear_color(brw, irb->mt, >Color.ClearColor);
+ !intel_miptree_set_clear_color(brw, irb->mt, clear_color);
/* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
* is redundant and can be skipped.
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index b5d7d691ec..506cf73e62 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -36,7 +36,6 @@
#include "brw_blorp.h"
#include "brw_context.h"
-#include "brw_meta_util.h"
#include "brw_state.h"
#include "main/enums.h"
@@ -3725,11 +3724,8 @@ get_isl_dim_layout(const struct gen_device_info *devinfo,
bool
intel_miptree_set_clear_color(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- const union gl_color_union *color)
+ union isl_color_value clear_color)
{
- const union isl_color_value clear_color =
- brw_meta_convert_fast_clear_color(brw, mt, color);
-
if (memcmp(>fast_clear_color, _color, sizeof(clear_color)) != 0) {
mt->fast_clear_color = clear_color;
brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 903d99137f..2d827afa53 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -706,7 +706,7 @@ intel_miptree_sample_with_hiz(struct brw_context *brw,
bool
intel_miptree_set_clear_color(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- const union gl_color_union *color);
+ union isl_color_value clear_color);
/* Get a clear color suitable for filling out an ISL surface state. */
union isl_color_value
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Mesa (master): i965/miptree: Fix handling of uninitialized MCS buffers
Module: Mesa
Branch: master
Commit: 816f2dc67da72be8993e724aeda4c2ec2f5a2978
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=816f2dc67da72be8993e724aeda4c2ec2f5a2978
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Mon Apr 30 10:40:18 2018 -0700
i965/miptree: Fix handling of uninitialized MCS buffers
Before this patch, if we failed to initialize an MCS buffer, we'd
end up in a state in which the miptree thinks it has an MCS buffer,
but doesn't. We also leaked the clear_color_bo if it existed.
With this patch, we now free the miptree aux buffer resources and let
intel_miptree_alloc_mcs() know that the MCS buffer no longer exists.
Cc: <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 67086ee6c0..dd851ff9b5 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1655,7 +1655,7 @@ intel_miptree_copy_teximage(struct brw_context *brw,
intel_obj->needs_validate = true;
}
-static void
+static bool
intel_miptree_init_mcs(struct brw_context *brw,
struct intel_mipmap_tree *mt,
int init_value)
@@ -1675,13 +1675,14 @@ intel_miptree_init_mcs(struct brw_context *brw,
void *map = brw_bo_map(brw, mt->aux_buf->bo, MAP_WRITE | MAP_RAW);
if (unlikely(map == NULL)) {
fprintf(stderr, "Failed to map mcs buffer into GTT\n");
- brw_bo_unreference(mt->aux_buf->bo);
- free(mt->aux_buf);
- return;
+ intel_miptree_aux_buffer_free(mt->aux_buf);
+ mt->aux_buf = NULL;
+ return false;
}
void *data = map;
memset(data, init_value, mt->aux_buf->surf.size);
brw_bo_unmap(mt->aux_buf->bo);
+ return true;
}
static struct intel_miptree_aux_buffer *
@@ -1759,15 +1760,14 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
const uint32_t alloc_flags = 0;
mt->aux_buf = intel_alloc_aux_buffer(brw, "mcs-miptree",
_mcs_surf, alloc_flags, mt);
- if (!mt->aux_buf) {
+ if (!mt->aux_buf ||
+ !intel_miptree_init_mcs(brw, mt, 0xFF)) {
free(aux_state);
return false;
}
mt->aux_state = aux_state;
- intel_miptree_init_mcs(brw, mt, 0xFF);
-
return true;
}
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Mesa (master): i965/miptree: Remove format assertion in alloc_aux
Module: Mesa
Branch: master
Commit: f88caf2321bbe809b9882fbc86f5aff718f68a75
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f88caf2321bbe809b9882fbc86f5aff718f68a75
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Wed May 16 11:03:24 2018 -0700
i965/miptree: Remove format assertion in alloc_aux
intel_miptree_supports_{ccs,mcs,hiz} ensures the format is valid for the
color or depth miptree before the miptree is assigned an aux_usage.
alloc_aux switches on the aux_usage so don't assert that the format is
valid.
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 1a797326a8..b783cf3abf 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1804,13 +1804,10 @@ intel_miptree_alloc_aux(struct brw_context *brw,
aux_surf_ok = true;
break;
case ISL_AUX_USAGE_HIZ:
- assert(!_mesa_is_format_color_format(mt->format));
-
initial_state = ISL_AUX_STATE_AUX_INVALID;
aux_surf_ok = isl_surf_get_hiz_surf(>isl_dev, >surf, _surf);
break;
case ISL_AUX_USAGE_MCS:
- assert(_mesa_is_format_color_format(mt->format));
assert(brw->screen->devinfo.gen >= 7); /* MCS only used on Gen7+ */
/* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
@@ -1831,8 +1828,6 @@ intel_miptree_alloc_aux(struct brw_context *brw,
break;
case ISL_AUX_USAGE_CCS_D:
case ISL_AUX_USAGE_CCS_E:
- assert(_mesa_is_format_color_format(mt->format));
-
/* When CCS_E is used, we need to ensure that the CCS starts off in a
* valid state. From the Sky Lake PRM, "MCS Buffer for Render
* Target(s)":
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Mesa (master): i965: isl: Move the MCS gen7+ assertion into ISL
Module: Mesa
Branch: master
Commit: 0ab25f05ab046532f57d683d460de5c35b74a78a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ab25f05ab046532f57d683d460de5c35b74a78a
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Wed May 16 11:11:04 2018 -0700
i965: isl: Move the MCS gen7+ assertion into ISL
This is useful for every user of ISL. Drop the comment along the way to
match similar functions in ISL.
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/intel/isl/isl.c | 2 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 --
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 7dfead00dc..f39d8a7999 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1642,6 +1642,8 @@ isl_surf_get_mcs_surf(const struct isl_device *dev,
const struct isl_surf *surf,
struct isl_surf *mcs_surf)
{
+ assert(ISL_DEV_GEN(dev) >= 7);
+
/* It must be multisampled with an array layout */
assert(surf->samples > 1 && surf->msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index b783cf3abf..5f19e23b01 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1808,8 +1808,6 @@ intel_miptree_alloc_aux(struct brw_context *brw,
aux_surf_ok = isl_surf_get_hiz_surf(>isl_dev, >surf, _surf);
break;
case ISL_AUX_USAGE_MCS:
- assert(brw->screen->devinfo.gen >= 7); /* MCS only used on Gen7+ */
-
/* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
*
* When MCS buffer is enabled and bound to MSRT, it is required that
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Mesa (master): i965: Make get_ccs_surf succeed in alloc_aux
Module: Mesa
Branch: master
Commit: da98441fefd051d681b2834b496567285a8836d3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=da98441fefd051d681b2834b496567285a8836d3
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Wed May 16 10:10:35 2018 -0700
i965: Make get_ccs_surf succeed in alloc_aux
Synchronize the requirements listed in isl_surf_get_ccs_surf with
intel_miptree_supports_ccs by importing a restriction from ISL. Some
implications:
* We successfully create every aux_surf in alloc_aux
* We only return false from alloc_aux if we run out of memory
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 5 +
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 16 ++--
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 636591c0b7..70c8e0d581 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1209,10 +1209,7 @@ do_single_blorp_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
if (can_fast_clear && !irb->mt->aux_buf) {
assert(irb->mt->aux_usage == ISL_AUX_USAGE_CCS_D);
if (!intel_miptree_alloc_aux(brw, irb->mt)) {
- /* There are a few reasons in addition to out-of-memory, that can
- * cause intel_miptree_alloc_non_msrt_mcs to fail. Try to recover by
- * falling back to non-fast clear.
- */
+ /* We're out of memory. Fall back to a non-fast clear. */
can_fast_clear = false;
}
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0c7c89a9ac..0289f4f7e4 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -204,6 +204,13 @@ intel_miptree_supports_ccs(struct brw_context *brw,
if (devinfo->gen < 8 && (mip_mapped || arrayed))
return false;
+ /* The PRM doesn't say this explicitly, but fast-clears don't appear to
+* work for 3D textures until gen9 where the layout of 3D textures changes
+* to match 2D array textures.
+*/
+ if (devinfo->gen <= 8 && mt->surf.dim != ISL_SURF_DIM_2D)
+ return false;
+
/* There's no point in using an MCS buffer if the surface isn't in a
* renderable format.
*/
@@ -1793,7 +1800,7 @@ intel_miptree_alloc_aux(struct brw_context *brw,
enum isl_aux_state initial_state;
uint8_t memset_value;
struct isl_surf aux_surf;
- bool aux_surf_ok;
+ MAYBE_UNUSED bool aux_surf_ok;
switch (mt->aux_usage) {
case ISL_AUX_USAGE_NONE:
@@ -1805,7 +1812,6 @@ intel_miptree_alloc_aux(struct brw_context *brw,
initial_state = ISL_AUX_STATE_AUX_INVALID;
aux_surf_ok = isl_surf_get_hiz_surf(>isl_dev, >surf, _surf);
- assert(aux_surf_ok);
break;
case ISL_AUX_USAGE_MCS:
assert(_mesa_is_format_color_format(mt->format));
@@ -1826,7 +1832,6 @@ intel_miptree_alloc_aux(struct brw_context *brw,
initial_state = ISL_AUX_STATE_CLEAR;
memset_value = 0xFF;
aux_surf_ok = isl_surf_get_mcs_surf(>isl_dev, >surf, _surf);
- assert(aux_surf_ok);
break;
case ISL_AUX_USAGE_CCS_D:
case ISL_AUX_USAGE_CCS_E:
@@ -1852,9 +1857,8 @@ intel_miptree_alloc_aux(struct brw_context *brw,
break;
}
- /* Ensure we have a valid aux_surf. */
- if (aux_surf_ok == false)
- return false;
+ /* We should have a valid aux_surf. */
+ assert(aux_surf_ok);
/* No work is needed for a zero-sized auxiliary buffer. */
if (aux_surf.size == 0)
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Mesa (master): i965/miptree: Simplify the switch in supports_ccs
Module: Mesa
Branch: master
Commit: 8007b2d78b42a6eaf90dfdb5f59f71bedd9f268c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8007b2d78b42a6eaf90dfdb5f59f71bedd9f268c
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Wed May 16 11:07:41 2018 -0700
i965/miptree: Simplify the switch in supports_ccs
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0289f4f7e4..1a797326a8 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -159,12 +159,8 @@ intel_miptree_supports_ccs(struct brw_context *brw,
return false;
/* MCS is only supported for color buffers */
- switch (_mesa_get_format_base_format(mt->format)) {
- case GL_DEPTH_COMPONENT:
- case GL_DEPTH_STENCIL:
- case GL_STENCIL_INDEX:
+ if (!_mesa_is_format_color_format(mt->format))
return false;
- }
if (mt->cpp != 4 && mt->cpp != 8 && mt->cpp != 16)
return false;
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Mesa (master): i965/tex_image: Avoid the ASTC LDR workaround on gen9lp
Module: Mesa Branch: master Commit: 3e56e4642fb5875b3f5c4eb34798ba9f3d827705 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e56e4642fb5875b3f5c4eb34798ba9f3d827705 Author: Nanley Chery <nanley.g.ch...@intel.com> Date: Sat Feb 24 01:26:20 2018 -0800 i965/tex_image: Avoid the ASTC LDR workaround on gen9lp Both the internal documentation and the results of testing this in the CI suggest that this is unnecessary. Add the fixes tag because this reduces an internal benchmark's startup time by about 17 seconds (reported by Eero). Fixes: 710b1d2e665 "i965/tex_image: Flush certain subnormal ASTC channel values" Tested-by: Eero Tamminen <eero.t.tammi...@intel.com> Acked-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/intel_tex_image.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c index 3fd227ad05..856216ecf9 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_image.c +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c @@ -927,7 +927,7 @@ intelCompressedTexSubImage(struct gl_context *ctx, GLuint dims, !_mesa_is_srgb_format(gl_format); struct brw_context *brw = (struct brw_context*) ctx; const struct gen_device_info *devinfo = >screen->devinfo; - if (devinfo->gen == 9 && is_linear_astc) + if (devinfo->gen == 9 && !gen_device_info_is_9lp(devinfo) && is_linear_astc) flush_astc_denorms(ctx, dims, texImage, xoffset, yoffset, zoffset, width, height, depth); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): blorp: Silence unused function warnings
Module: Mesa
Branch: master
Commit: 377da9eb785d52904735cd62c0c7b205404c39d2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=377da9eb785d52904735cd62c0c7b205404c39d2
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Tue Apr 10 15:05:31 2018 -0700
blorp: Silence unused function warnings
vulkan/genX_blorp_exec.c:69:1: warning: ‘blorp_get_surface_base_address’
defined but not used [-Wunused-function]
blorp_get_surface_base_address(struct blorp_batch *batch)
^~
In file included from vulkan/genX_blorp_exec.c:35:0:
./blorp/blorp_genX_exec.h:1249:1: warning: ‘blorp_emit_memcpy’ defined but not
used [-Wunused-function]
blorp_emit_memcpy(struct blorp_batch *batch,
^
genX_blorp_exec.c:99:1: warning: ‘blorp_get_surface_base_address’ defined but
not used [-Wunused-function]
blorp_get_surface_base_address(struct blorp_batch *batch)
^~
In file included from genX_blorp_exec.c:33:0:
../../../../../src/intel/blorp/blorp_genX_exec.h:1249:1: warning:
‘blorp_emit_memcpy’ defined but not used [-Wunused-function]
blorp_emit_memcpy(struct blorp_batch *batch,
^
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
src/intel/blorp/blorp_genX_exec.h | 4 ++--
src/intel/vulkan/genX_blorp_exec.c | 2 +-
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/intel/blorp/blorp_genX_exec.h
b/src/intel/blorp/blorp_genX_exec.h
index 7851228d8d..593521b95c 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -78,7 +78,7 @@ static void
blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
struct blorp_address address, uint32_t delta);
-#if GEN_GEN >= 7 && GEN_GEN <= 10
+#if GEN_GEN >= 7 && GEN_GEN < 10
static struct blorp_address
blorp_get_surface_base_address(struct blorp_batch *batch);
#endif
@@ -1244,7 +1244,7 @@ blorp_emit_pipeline(struct blorp_batch *batch,
#endif /* GEN_GEN >= 6 */
-#if GEN_GEN >= 7 && GEN_GEN <= 10
+#if GEN_GEN >= 7 && GEN_GEN < 10
static void
blorp_emit_memcpy(struct blorp_batch *batch,
struct blorp_address dst,
diff --git a/src/intel/vulkan/genX_blorp_exec.c
b/src/intel/vulkan/genX_blorp_exec.c
index 1ecec19984..b423046d61 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -64,7 +64,7 @@ blorp_surface_reloc(struct blorp_batch *batch, uint32_t
ss_offset,
anv_batch_set_error(_buffer->batch, result);
}
-#if GEN_GEN >= 7 && GEN_GEN <= 10
+#if GEN_GEN >= 7 && GEN_GEN < 10
static struct blorp_address
blorp_get_surface_base_address(struct blorp_batch *batch)
{
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 3406a6fdec..b72ca9c515 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -94,7 +94,7 @@ blorp_surface_reloc(struct blorp_batch *batch, uint32_t
ss_offset,
#endif
}
-#if GEN_GEN >= 7 && GEN_GEN <= 10
+#if GEN_GEN >= 7 && GEN_GEN < 10
static struct blorp_address
blorp_get_surface_base_address(struct blorp_batch *batch)
{
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Mesa (master): i965/miptree: Move the clear color and value setter implementations
Module: Mesa
Branch: master
Commit: 3dbb49a97809cd3a9911d2782bb7b03f8ae1a7d8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3dbb49a97809cd3a9911d2782bb7b03f8ae1a7d8
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Tue Mar 27 15:46:49 2018 -0700
i965/miptree: Move the clear color and value setter implementations
These will get more complex in later commits.
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 26 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 25 -
2 files changed, 30 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 89074a6493..32be4b033e 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3804,3 +3804,29 @@ intel_miptree_get_aux_isl_usage(const struct brw_context
*brw,
return mt->aux_usage;
}
+
+bool
+intel_miptree_set_clear_color(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ union isl_color_value clear_color)
+{
+ if (memcmp(>fast_clear_color, _color, sizeof(clear_color)) != 0) {
+ mt->fast_clear_color = clear_color;
+ brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
+ return true;
+ }
+ return false;
+}
+
+bool
+intel_miptree_set_depth_clear_value(struct brw_context *brw,
+struct intel_mipmap_tree *mt,
+float clear_value)
+{
+ if (mt->fast_clear_color.f32[0] != clear_value) {
+ mt->fast_clear_color.f32[0] = clear_value;
+ brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
+ return true;
+ }
+ return false;
+}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index df9b76892a..ff6ce4ecf9 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -731,32 +731,15 @@ bool
intel_miptree_sample_with_hiz(struct brw_context *brw,
struct intel_mipmap_tree *mt);
-
-static inline bool
+bool
intel_miptree_set_clear_color(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- union isl_color_value clear_color)
-{
- if (memcmp(>fast_clear_color, _color, sizeof(clear_color)) != 0) {
- mt->fast_clear_color = clear_color;
- brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
- return true;
- }
- return false;
-}
+ union isl_color_value clear_color);
-static inline bool
+bool
intel_miptree_set_depth_clear_value(struct brw_context *brw,
struct intel_mipmap_tree *mt,
-float clear_value)
-{
- if (mt->fast_clear_color.f32[0] != clear_value) {
- mt->fast_clear_color.f32[0] = clear_value;
- brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
- return true;
- }
- return false;
-}
+float clear_value);
#ifdef __cplusplus
}
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Mesa (master): i965: Use the brw_context for the clear color and value setters
Module: Mesa
Branch: master
Commit: 1ce7ae391e8a41b2ee4dab568cd77faa072a0fe2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ce7ae391e8a41b2ee4dab568cd77faa072a0fe2
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Wed Mar 28 17:53:13 2018 -0700
i965: Use the brw_context for the clear color and value setters
Do what all the other functions in the miptree API do.
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
src/mesa/drivers/dri/i965/brw_clear.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 8
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index d91d03609a..0ccfa21254 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1240,7 +1240,7 @@ do_single_blorp_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
>Color.ClearColor);
bool same_clear_color =
- !intel_miptree_set_clear_color(ctx, irb->mt, clear_color);
+ !intel_miptree_set_clear_color(brw, irb->mt, clear_color);
/* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
* is redundant and can be skipped.
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
b/src/mesa/drivers/dri/i965/brw_clear.c
index 63c0b24189..487de9b899 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -213,7 +213,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
}
}
- intel_miptree_set_depth_clear_value(ctx, mt, clear_value);
+ intel_miptree_set_depth_clear_value(brw, mt, clear_value);
same_clear_value = false;
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 54d3640075..df9b76892a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -733,26 +733,26 @@ intel_miptree_sample_with_hiz(struct brw_context *brw,
static inline bool
-intel_miptree_set_clear_color(struct gl_context *ctx,
+intel_miptree_set_clear_color(struct brw_context *brw,
struct intel_mipmap_tree *mt,
union isl_color_value clear_color)
{
if (memcmp(>fast_clear_color, _color, sizeof(clear_color)) != 0) {
mt->fast_clear_color = clear_color;
- ctx->NewDriverState |= BRW_NEW_AUX_STATE;
+ brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
return true;
}
return false;
}
static inline bool
-intel_miptree_set_depth_clear_value(struct gl_context *ctx,
+intel_miptree_set_depth_clear_value(struct brw_context *brw,
struct intel_mipmap_tree *mt,
float clear_value)
{
if (mt->fast_clear_color.f32[0] != clear_value) {
mt->fast_clear_color.f32[0] = clear_value;
- ctx->NewDriverState |= BRW_NEW_AUX_STATE;
+ brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
return true;
}
return false;
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Mesa (master): i965: Make the miptree clear color setter take a gl_color_union
Module: Mesa
Branch: master
Commit: 1d94aa19877fb702ffacacde28ad7253cce72c97
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d94aa19877fb702ffacacde28ad7253cce72c97
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Wed Mar 28 18:06:58 2018 -0700
i965: Make the miptree clear color setter take a gl_color_union
We want to hide the internal details of how the miptree's clear color
is calculated.
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 5 +
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +-
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 0ccfa21254..5dcd95e9f4 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1235,12 +1235,9 @@ do_single_blorp_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
if (can_fast_clear) {
const enum isl_aux_state aux_state =
intel_miptree_get_aux_state(irb->mt, irb->mt_level, irb->mt_layer);
- union isl_color_value clear_color =
- brw_meta_convert_fast_clear_color(brw, irb->mt,
- >Color.ClearColor);
bool same_clear_color =
- !intel_miptree_set_clear_color(brw, irb->mt, clear_color);
+ !intel_miptree_set_clear_color(brw, irb->mt, >Color.ClearColor);
/* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
* is redundant and can be skipped.
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 32be4b033e..8d3ddd5654 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -36,6 +36,7 @@
#include "brw_blorp.h"
#include "brw_context.h"
+#include "brw_meta_util.h"
#include "brw_state.h"
#include "main/enums.h"
@@ -3808,8 +3809,11 @@ intel_miptree_get_aux_isl_usage(const struct brw_context
*brw,
bool
intel_miptree_set_clear_color(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- union isl_color_value clear_color)
+ const union gl_color_union *color)
{
+ const union isl_color_value clear_color =
+ brw_meta_convert_fast_clear_color(brw, mt, color);
+
if (memcmp(>fast_clear_color, _color, sizeof(clear_color)) != 0) {
mt->fast_clear_color = clear_color;
brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index ff6ce4ecf9..4136c6586b 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -734,7 +734,7 @@ intel_miptree_sample_with_hiz(struct brw_context *brw,
bool
intel_miptree_set_clear_color(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- union isl_color_value clear_color);
+ const union gl_color_union *color);
bool
intel_miptree_set_depth_clear_value(struct brw_context *brw,
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Mesa (master): i965/miptree: Don't leak the clear_color_bo
Module: Mesa
Branch: master
Commit: 010abacc95207f600bc750f01d690b1c899e112c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=010abacc95207f600bc750f01d690b1c899e112c
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Mon Apr 9 11:27:08 2018 -0700
i965/miptree: Don't leak the clear_color_bo
Free the clear_color_bo in addition to freeing the
intel_miptree_aux_buffer which holds the reference to it.
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 8d3ddd5654..0580cc0534 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2877,8 +2877,7 @@ intel_miptree_make_shareable(struct brw_context *brw,
ISL_AUX_USAGE_NONE, false);
if (mt->mcs_buf) {
- brw_bo_unreference(mt->mcs_buf->bo);
- free(mt->mcs_buf);
+ intel_miptree_aux_buffer_free(mt->mcs_buf);
mt->mcs_buf = NULL;
/* Any pending MCS/CCS operations are no longer needed. Trying to
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Mesa (master): i965/miptree: Delete an unused function
Module: Mesa
Branch: master
Commit: 7b2032910761a7e36ceeb498eee4e77c7a916f38
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b2032910761a7e36ceeb498eee4e77c7a916f38
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Mon Apr 9 11:20:27 2018 -0700
i965/miptree: Delete an unused function
We're going to combine ::mcs_buf and ::hiz_buf in later commits. Once
that happens, this function no longer make sense.
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 13 -
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4
2 files changed, 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0580cc0534..d95128de11 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3792,19 +3792,6 @@ get_isl_dim_layout(const struct gen_device_info *devinfo,
unreachable("Invalid texture target");
}
-enum isl_aux_usage
-intel_miptree_get_aux_isl_usage(const struct brw_context *brw,
-const struct intel_mipmap_tree *mt)
-{
- if (mt->hiz_buf)
- return ISL_AUX_USAGE_HIZ;
-
- if (!mt->mcs_buf)
- return ISL_AUX_USAGE_NONE;
-
- return mt->aux_usage;
-}
-
bool
intel_miptree_set_clear_color(struct brw_context *brw,
struct intel_mipmap_tree *mt,
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 4136c6586b..2f754427fc 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -485,10 +485,6 @@ enum isl_dim_layout
get_isl_dim_layout(const struct gen_device_info *devinfo,
enum isl_tiling tiling, GLenum target);
-enum isl_aux_usage
-intel_miptree_get_aux_isl_usage(const struct brw_context *brw,
-const struct intel_mipmap_tree *mt);
-
void
intel_get_image_dims(struct gl_texture_image *image,
int *width, int *height, int *depth);
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Mesa (master): i965/meta_util: Re-enable sRGB-encoded fast-clears on CNL
Module: Mesa
Branch: master
Commit: 0e8b16e0a239cc4a4758b62fb6787158180a74fd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e8b16e0a239cc4a4758b62fb6787158180a74fd
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Thu Mar 22 17:05:34 2018 -0700
i965/meta_util: Re-enable sRGB-encoded fast-clears on CNL
The paths which sample with the clear color are now using a getter which
performs the sRGB decode needed to enable this fast clear.
This path can be exercised by fast-clearing a texture, then performing
an operation which requires sRGB decoding. Test coverage for this
feature is provided with the following tests:
* Shader texture calls:
- spec@ext_texture_srgb@tex-srgb
* Shader texelfetch calls:
- spec@arb_framebuffer_srgb@fbo-fast-clear
- spec@arb_framebuffer_srgb@msaa-fast-clear
* Blending:
- spec@arb_framebuffer_srgb@arb_framebuffer_srgb-fast-clear-blend
* Blitting:
- spec@arb_framebuffer_srgb@blit texture srgb msaa enabled clear
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_meta_util.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c
b/src/mesa/drivers/dri/i965/brw_meta_util.c
index b31181521c..d292f5a8e2 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -293,18 +293,7 @@ brw_is_color_fast_clear_compatible(struct brw_context *brw,
brw->mesa_to_isl_render_format[mt->format])
return false;
- const bool srgb_rb = _mesa_get_srgb_format_linear(mt->format) != mt->format;
- /* Gen10 doesn't automatically decode the clear color of sRGB buffers. Since
- * we currently don't perform this decode in software, avoid a fast-clear
- * altogether. TODO: Do this in software.
- */
const mesa_format format = _mesa_get_render_format(ctx, mt->format);
- if (devinfo->gen >= 10 && srgb_rb) {
- perf_debug("sRGB fast clear not enabled for (%s)",
- _mesa_get_format_name(format));
- return false;
- }
-
if (_mesa_is_format_integer_color(format)) {
if (devinfo->gen >= 8) {
perf_debug("Integer fast clear not enabled for (%s)",
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Mesa (master): i965: Add and use a getter for the miptree aux buffer
Module: Mesa
Branch: master
Commit: 5503b65103b6a93dabe609cbedbbc999dd63bff5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5503b65103b6a93dabe609cbedbbc999dd63bff5
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Mon Apr 9 11:11:46 2018 -0700
i965: Add and use a getter for the miptree aux buffer
Make the next patch easier to read by eliminating most of the would-be
duplicate field accesses now.
v2: Update the HiZ comment instead of deleting it (Rafael).
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp.c| 8 ++--
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 16 +--
src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 25 +---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h| 17
4 files changed, 25 insertions(+), 41 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 5dcd95e9f4..962a316c5c 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -154,12 +154,6 @@ blorp_surf_for_miptree(struct brw_context *brw,
.aux_usage = aux_usage,
};
- struct intel_miptree_aux_buffer *aux_buf = NULL;
- if (mt->mcs_buf)
- aux_buf = mt->mcs_buf;
- else if (mt->hiz_buf)
- aux_buf = mt->hiz_buf;
-
if (mt->format == MESA_FORMAT_S_UINT8 && is_render_target &&
devinfo->gen <= 7)
mt->r8stencil_needs_update = true;
@@ -174,6 +168,8 @@ blorp_surf_for_miptree(struct brw_context *brw,
*/
surf->clear_color = mt->fast_clear_color;
+ struct intel_miptree_aux_buffer *aux_buf =
+ intel_miptree_get_aux_buffer(mt);
surf->aux_surf = _buf->surf;
surf->aux_addr = (struct blorp_address) {
.reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 3fb101bf68..06f739faf6 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -155,21 +155,7 @@ brw_emit_surface_state(struct brw_context *brw,
struct brw_bo *aux_bo = NULL;
struct isl_surf *aux_surf = NULL;
uint64_t aux_offset = 0;
- struct intel_miptree_aux_buffer *aux_buf = NULL;
- switch (aux_usage) {
- case ISL_AUX_USAGE_MCS:
- case ISL_AUX_USAGE_CCS_D:
- case ISL_AUX_USAGE_CCS_E:
- aux_buf = mt->mcs_buf;
- break;
-
- case ISL_AUX_USAGE_HIZ:
- aux_buf = mt->hiz_buf;
- break;
-
- case ISL_AUX_USAGE_NONE:
- break;
- }
+ struct intel_miptree_aux_buffer *aux_buf = intel_miptree_get_aux_buffer(mt);
if (aux_usage != ISL_AUX_USAGE_NONE) {
aux_surf = _buf->surf;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index d95128de11..3cb6f70a6c 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1249,8 +1249,7 @@ intel_miptree_release(struct intel_mipmap_tree **mt)
brw_bo_unreference((*mt)->bo);
intel_miptree_release(&(*mt)->stencil_mt);
intel_miptree_release(&(*mt)->r8stencil_mt);
- intel_miptree_aux_buffer_free((*mt)->hiz_buf);
- intel_miptree_aux_buffer_free((*mt)->mcs_buf);
+ intel_miptree_aux_buffer_free(intel_miptree_get_aux_buffer(*mt));
free_aux_state_map((*mt)->aux_state);
intel_miptree_release(&(*mt)->plane[0]);
@@ -2876,31 +2875,17 @@ intel_miptree_make_shareable(struct brw_context *brw,
0, INTEL_REMAINING_LAYERS,
ISL_AUX_USAGE_NONE, false);
- if (mt->mcs_buf) {
- intel_miptree_aux_buffer_free(mt->mcs_buf);
+ struct intel_miptree_aux_buffer *aux_buf = intel_miptree_get_aux_buffer(mt);
+ if (aux_buf) {
+ intel_miptree_aux_buffer_free(aux_buf);
mt->mcs_buf = NULL;
-
- /* Any pending MCS/CCS operations are no longer needed. Trying to
- * execute any will likely crash due to the missing aux buffer. So let's
- * delete all pending ops.
- */
- free(mt->aux_state);
- mt->aux_state = NULL;
- brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
- }
-
- if (mt->hiz_buf) {
- intel_miptree_aux_buffer_free(mt->hiz_buf);
mt->hiz_buf = NULL;
+ /* Make future calls of intel_miptree_level_has_hiz() return false. */
for (uint32_t l = mt->first_level; l <= mt->last_level; ++l) {
mt->level[l].has_hiz = false;
}
- /* Any pending HiZ operations are no longer needed. Trying to execute
- * any will likely crash due to the missing aux buffer. So let's delete
- * all pending ops.
- */
free(mt->aux_state);
mt
Mesa (master): i965: Add and use a single miptree aux_buf field
Module: Mesa
Branch: master
Commit: af4e9295febe966ace7793e43ba35705521749e8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=af4e9295febe966ace7793e43ba35705521749e8
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Fri Apr 6 09:54:31 2018 -0700
i965: Add and use a single miptree aux_buf field
We want to add and use a function that accesses the auxiliary buffer's
clear_color_bo and doesn't care if it has an MCS or HiZ buffer
specifically.
v2 (Jason Ekstrand):
* Drop intel_miptree_get_aux_buffer().
* Mention CCS in the aux_buf field.
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com> (v1)
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_blorp.c| 16 ++--
src/mesa/drivers/dri/i965/brw_clear.c| 4 +-
src/mesa/drivers/dri/i965/brw_wm.c | 2 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 11 ++-
src/mesa/drivers/dri/i965/gen6_depth_state.c | 6 +-
src/mesa/drivers/dri/i965/gen7_misc_state.c | 4 +-
src/mesa/drivers/dri/i965/gen8_depth_state.c | 6 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 106 +++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h| 53 +---
src/mesa/drivers/dri/i965/intel_tex_image.c | 2 +-
10 files changed, 96 insertions(+), 114 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 962a316c5c..37fca5e9d3 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -168,21 +168,19 @@ blorp_surf_for_miptree(struct brw_context *brw,
*/
surf->clear_color = mt->fast_clear_color;
- struct intel_miptree_aux_buffer *aux_buf =
- intel_miptree_get_aux_buffer(mt);
- surf->aux_surf = _buf->surf;
+ surf->aux_surf = >aux_buf->surf;
surf->aux_addr = (struct blorp_address) {
.reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
.mocs = surf->addr.mocs,
};
- surf->aux_addr.buffer = aux_buf->bo;
- surf->aux_addr.offset = aux_buf->offset;
+ surf->aux_addr.buffer = mt->aux_buf->bo;
+ surf->aux_addr.offset = mt->aux_buf->offset;
if (devinfo->gen >= 10) {
surf->clear_color_addr = (struct blorp_address) {
-.buffer = aux_buf->clear_color_bo,
-.offset = aux_buf->clear_color_offset,
+.buffer = mt->aux_buf->clear_color_bo,
+.offset = mt->aux_buf->clear_color_offset,
};
}
} else {
@@ -1212,7 +1210,7 @@ do_single_blorp_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
/* If the MCS buffer hasn't been allocated yet, we need to allocate it now.
*/
- if (can_fast_clear && !irb->mt->mcs_buf) {
+ if (can_fast_clear && !irb->mt->aux_buf) {
assert(irb->mt->aux_usage == ISL_AUX_USAGE_CCS_D);
if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
/* There are a few reasons in addition to out-of-memory, that can
@@ -1611,7 +1609,7 @@ intel_hiz_exec(struct brw_context *brw, struct
intel_mipmap_tree *mt,
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
}
- assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->hiz_buf);
+ assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->aux_buf);
struct isl_surf isl_tmp[2];
struct blorp_surf surf;
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
b/src/mesa/drivers/dri/i965/brw_clear.c
index 487de9b899..3d540d6d90 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -240,7 +240,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
* buffer when doing a fast clear. Since we are skipping the fast
* clear here, we need to update the clear color ourselves.
*/
- uint32_t clear_offset = mt->hiz_buf->clear_color_offset;
+ uint32_t clear_offset = mt->aux_buf->clear_color_offset;
union isl_color_value clear_color = { .f32 = { clear_value, } };
/* We can't update the clear color while the hardware is still using
@@ -249,7 +249,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
*/
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
for (int i = 0; i < 4; i++) {
-brw_store_data_imm32(brw, mt->hiz_buf->clear_color_bo,
+brw_store_data_imm32(brw, mt->aux_buf->clear_color_bo,
clear_offset + i * 4, clear_color.u32[i]);
}
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c
b/src/mesa/drivers/dri/i965/brw_wm.c
index 68d4ab88d7..94048cd758 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/d
Mesa (master): i965: Add and use a getter for the clear color
Module: Mesa
Branch: master
Commit: 7ea013c6d3b515701df8a4d2a50578ee9b691272
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ea013c6d3b515701df8a4d2a50578ee9b691272
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Mon Mar 26 14:32:18 2018 -0700
i965: Add and use a getter for the clear color
It returns both the inline clear color and a clear address which points
to the indirect clear color buffer (or NULL if unused/non-existent).
This getter allows CNL to sample from fast-cleared sRGB textures
correctly by doing the needed sRGB-decode on the clear color (inline)
and making the indirect clear color buffer unused.
v2 (Rafael):
* Have a more detailed commit message.
* Add a comment on the sRGB conversion process.
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_blorp.c| 13 -
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 7 ++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 34
src/mesa/drivers/dri/i965/intel_mipmap_tree.h| 8 ++
4 files changed, 51 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 37fca5e9d3..ba14136edc 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -166,7 +166,11 @@ blorp_surf_for_miptree(struct brw_context *brw,
/* We only really need a clear color if we also have an auxiliary
* surface. Without one, it does nothing.
*/
- surf->clear_color = mt->fast_clear_color;
+ surf->clear_color =
+ intel_miptree_get_clear_color(devinfo, mt, mt->surf.format,
+ !is_render_target, (struct brw_bo **)
+ >clear_color_addr.buffer,
+ >clear_color_addr.offset);
surf->aux_surf = >aux_buf->surf;
surf->aux_addr = (struct blorp_address) {
@@ -176,13 +180,6 @@ blorp_surf_for_miptree(struct brw_context *brw,
surf->aux_addr.buffer = mt->aux_buf->bo;
surf->aux_addr.offset = mt->aux_buf->offset;
-
- if (devinfo->gen >= 10) {
- surf->clear_color_addr = (struct blorp_address) {
-.buffer = mt->aux_buf->clear_color_bo,
-.offset = mt->aux_buf->clear_color_offset,
- };
- }
} else {
surf->aux_addr = (struct blorp_address) {
.buffer = NULL,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 7cbd2d42ae..96c93a7e5b 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -166,9 +166,10 @@ brw_emit_surface_state(struct brw_context *brw,
/* We only really need a clear color if we also have an auxiliary
* surface. Without one, it does nothing.
*/
- clear_bo = mt->aux_buf->clear_color_bo;
- clear_offset = mt->aux_buf->clear_color_offset;
- clear_color = mt->fast_clear_color;
+ clear_color =
+ intel_miptree_get_clear_color(devinfo, mt, view.format,
+ view.usage & ISL_SURF_USAGE_TEXTURE_BIT,
+ _bo, _offset);
}
void *state = brw_state_batch(brw,
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 139f3f0c19..b00368f8f9 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -46,6 +46,9 @@
#include "main/texcompress_etc.h"
#include "main/teximage.h"
#include "main/streaming-load-memcpy.h"
+
+#include "util/format_srgb.h"
+
#include "x86/common_x86_asm.h"
#define FILE_DEBUG_FLAG DEBUG_MIPTREE
@@ -3803,3 +3806,34 @@ intel_miptree_set_depth_clear_value(struct brw_context
*brw,
}
return false;
}
+
+union isl_color_value
+intel_miptree_get_clear_color(const struct gen_device_info *devinfo,
+ const struct intel_mipmap_tree *mt,
+ enum isl_format view_format, bool sampling,
+ struct brw_bo **clear_color_bo,
+ uint32_t *clear_color_offset)
+{
+ assert(mt->aux_buf);
+
+ if (devinfo->gen == 10 && isl_format_is_srgb(view_format) && sampling) {
+ /* The gen10 sampler doesn't gamma-correct the clear color. In this case,
+ * we switch to using the inline clear color and do the sRGB color
+ * conversion process defined in the OpenGL spec. The red, green, and
+ * blue channels take part in gamma correction, while the alpha channel
+
Mesa (master): i965/wm_surface_state: Use the clear address if clear_bo is non-NULL
Module: Mesa
Branch: master
Commit: cd5ce363e3fcf975c05a5f325292e95df8322cfb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd5ce363e3fcf975c05a5f325292e95df8322cfb
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Tue Apr 10 13:56:18 2018 -0700
i965/wm_surface_state: Use the clear address if clear_bo is non-NULL
We want to add and use a getter that turns off the indirect path by
returning zero for the clear color bo and offset.
v2: Fix usage of "clear address" in commit message (Jason).
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 8025ec128b..7cbd2d42ae 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -155,6 +155,8 @@ brw_emit_surface_state(struct brw_context *brw,
struct brw_bo *aux_bo = NULL;
struct isl_surf *aux_surf = NULL;
uint64_t aux_offset = 0;
+ struct brw_bo *clear_bo = NULL;
+ uint32_t clear_offset = 0;
if (aux_usage != ISL_AUX_USAGE_NONE) {
aux_surf = >aux_buf->surf;
@@ -164,6 +166,8 @@ brw_emit_surface_state(struct brw_context *brw,
/* We only really need a clear color if we also have an auxiliary
* surface. Without one, it does nothing.
*/
+ clear_bo = mt->aux_buf->clear_color_bo;
+ clear_offset = mt->aux_buf->clear_color_offset;
clear_color = mt->fast_clear_color;
}
@@ -172,15 +176,6 @@ brw_emit_surface_state(struct brw_context *brw,
brw->isl_dev.ss.align,
surf_offset);
- bool use_clear_address = devinfo->gen >= 10 && aux_surf;
-
- struct brw_bo *clear_bo = NULL;
- uint32_t clear_offset = 0;
- if (use_clear_address) {
- clear_bo = mt->aux_buf->clear_color_bo;
- clear_offset = mt->aux_buf->clear_color_offset;
- }
-
isl_surf_fill_state(>isl_dev, state, .surf = , .view = ,
.address = brw_state_reloc(>batch,
*surf_offset +
brw->isl_dev.ss.addr_offset,
@@ -189,7 +184,7 @@ brw_emit_surface_state(struct brw_context *brw,
.aux_address = aux_offset,
.mocs = brw_get_bo_mocs(devinfo, mt->bo),
.clear_color = clear_color,
- .use_clear_address = use_clear_address,
+ .use_clear_address = clear_bo != NULL,
.clear_address = clear_offset,
.x_offset_sa = tile_x, .y_offset_sa = tile_y);
if (aux_surf) {
@@ -221,7 +216,7 @@ brw_emit_surface_state(struct brw_context *brw,
}
}
- if (use_clear_address) {
+ if (clear_bo != NULL) {
/* Make sure the offset is aligned with a cacheline. */
assert((clear_offset & 0x3f) == 0);
uint32_t *clear_address =
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Mesa (master): i965/miptree: Extend the sRGB-blending WA to future platforms
Module: Mesa Branch: master Commit: 129ad66dd5332159f154b3714a87e5f8d65214fa URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=129ad66dd5332159f154b3714a87e5f8d65214fa Author: Nanley Chery <nanley.g.ch...@intel.com> Date: Thu Mar 29 22:14:09 2018 -0700 i965/miptree: Extend the sRGB-blending WA to future platforms The blending issue seems to be present on CNL as well. Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index b00368f8f9..93a91fd808 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -2737,11 +2737,11 @@ intel_miptree_render_aux_usage(struct brw_context *brw, return ISL_AUX_USAGE_NONE; } - /* gen9 hardware technically supports non-0/1 clear colors with sRGB + /* gen9+ hardware technically supports non-0/1 clear colors with sRGB * formats. However, there are issues with blending where it doesn't * properly apply the sRGB curve to the clear color when blending. */ - if (devinfo->gen == 9 && blend_enabled && + if (devinfo->gen >= 9 && blend_enabled && isl_format_is_srgb(render_format) && !isl_color_value_is_zero_one(mt->fast_clear_color, render_format)) return ISL_AUX_USAGE_NONE; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): util/srgb: Add a float sRGB -> linear helper
Module: Mesa
Branch: master
Commit: b55077a8bc1e85400b43141f9ed4a1f4a322b420
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b55077a8bc1e85400b43141f9ed4a1f4a322b420
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Thu Jun 22 20:00:47 2017 -0700
util/srgb: Add a float sRGB -> linear helper
Reviewed-by: Nanley Chery <nanley.g.ch...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/util/format_srgb.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/util/format_srgb.h b/src/util/format_srgb.h
index 34b50afe3d..596af56f4c 100644
--- a/src/util/format_srgb.h
+++ b/src/util/format_srgb.h
@@ -55,6 +55,20 @@ util_format_linear_to_srgb_helper_table[104];
static inline float
+util_format_srgb_to_linear_float(float cs)
+{
+ if (cs <= 0.0f)
+ return 0.0f;
+ else if (cs <= 0.04045f)
+ return cs / 12.92f;
+ else if (cs < 1.0f)
+ return powf((cs + 0.055) / 1.055f, 2.4f);
+ else
+ return 1.0f;
+}
+
+
+static inline float
util_format_linear_to_srgb_float(float cl)
{
if (cl <= 0.0f)
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