[Mesa-dev] [PATCH v5] i965/aa: fixing anti-aliasing bug for thinnest width lines - GEN6
On SNB and IVB hw, for 1 pixel line thickness or less,
the general anti-aliasing algorithm give up - garbage line is generated.
Setting a Line Width of 0.0 specifies the rasterization of
the “thinnest” (one-pixel-wide), non-antialiased lines.
Lines rendered with zero Line Width are rasterized using
Grid Intersection Quantization rules as specified
by bspec section 6.3.12.1 Zero-Width (Cosmetic) Line Rasterization.
v2: Daniel Stone: Fix = used instead of == in an if-statement.
v3: Ian Romanick: Use ._Enabled flag insteed .Enabled.
Add code comments. re-word wrap the commit message.
Add a complete bugzillia list.
Improve the hardcoded values to produce better results.
v4: Matt Turner: typo fixes and adjust = 1.49 to become 1.5
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28832
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=9951
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27007
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60797
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=15006
Signed-off-by: Marius Predut marius.pre...@intel.com
---
src/mesa/drivers/dri/i965/gen6_sf_state.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index ea5c47a..e445ce2 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -367,9 +367,25 @@ upload_sf_state(struct brw_context *brw)
float line_width =
roundf(CLAMP(ctx-Line.Width, 0.0, ctx-Const.MaxLineWidth));
uint32_t line_width_u3_7 = U_FIXED(line_width, 7);
- /* TODO: line width of 0 is not allowed when MSAA enabled */
- if (line_width_u3_7 == 0)
- line_width_u3_7 = 1;
+
+ /* Line width of 0 is not allowed when MSAA enabled */
+ if (ctx-Multisample._Enabled) {
+ if (line_width_u3_7 == 0)
+ line_width_u3_7 = 1;
+ } else if (ctx-Line.SmoothFlag ctx-Line.Width 1.5) {
+ /* For 1 pixel line thickness or less, the general
+ * anti-aliasing algorithm gives up, and a garbage line is
+ * generated. Setting a Line Width of 0.0 specifies the
+ * rasterization of the thinnest (one-pixel-wide),
+ * non-antialiased lines.
+ *
+ * Lines rendered with zero Line Width are rasterized using
+ * Grid Intersection Quantization rules as specified by
+ * bspec section 6.3.12.1 Zero-Width (Cosmetic) Line
+ * Rasterization.
+ */
+ line_width_u3_7 = 0;
+ }
dw3 |= line_width_u3_7 GEN6_SF_LINE_WIDTH_SHIFT;
}
if (ctx-Line.SmoothFlag) {
--
1.9.1
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[Mesa-dev] [PATCH] mesa: add support for exposing up to GL4.2
Add the 4.0/4.1/4.2 extensions lists to compute_version. A coule of
extensions aren't in mesa yet, so those are marked with 0 until they
become supported.
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
I wasn't 100% sure about shading_language_packing -- it includes a
couple of functions that don't appear until GL 4.2. However since it's
enabled for all the drivers that matter in mesa, wtvr.
I'm planning on making an integration branch for nvc0 that includes
Dave's work on subroutines and 64-bit attribs along with Chris and my
tess patches, to be able to expose GL4.1. Having this in tree would be
convenient. [And GL4.2 was easy enough to include, so I went ahead with it.]
src/mesa/main/version.c | 46 +-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/version.c b/src/mesa/main/version.c
index 7c6d994..738b406 100644
--- a/src/mesa/main/version.c
+++ b/src/mesa/main/version.c
@@ -295,7 +295,51 @@ compute_version(const struct gl_extensions *extensions,
extensions-EXT_texture_swizzle);
/* ARB_sampler_objects is always enabled in mesa
*/
- if (ver_3_3) {
+ const GLboolean ver_4_0 = (ver_3_3
+ consts-GLSLVersion = 400
+ extensions-ARB_draw_buffers_blend
+ extensions-ARB_draw_indirect
+ extensions-ARB_gpu_shader5
+ extensions-ARB_gpu_shader_fp64
+ extensions-ARB_sample_shading
+ extensions-ARB_shading_language_packing
+ 0/*extensions-ARB_shader_subroutine*/
+ extensions-ARB_tessellation_shader
+ extensions-ARB_texture_buffer_object_rgb32
+ extensions-ARB_texture_cube_map_array
+ extensions-ARB_texture_query_lod
+ extensions-ARB_transform_feedback2
+ extensions-ARB_transform_feedback3);
+ const GLboolean ver_4_1 = (ver_4_0
+ consts-GLSLVersion = 410
+ extensions-ARB_ES2_compatibility
+ extensions-ARB_shader_precision
+ 0/*extensions-ARB_vertex_attrib_64bit*/
+ extensions-ARB_viewport_array);
+ const GLboolean ver_4_2 = (ver_4_1
+ consts-GLSLVersion = 420
+ extensions-ARB_base_instance
+ extensions-ARB_conservative_depth
+ extensions-ARB_internalformat_query
+ extensions-ARB_shader_atomic_counters
+ extensions-ARB_shader_image_load_store
+ extensions-ARB_shading_language_420pack
+ extensions-ARB_texture_compression_bptc
+ extensions-ARB_transform_feedback_instanced);
+
+ if (ver_4_2) {
+ major = 4;
+ minor = 2;
+ }
+ else if (ver_4_1) {
+ major = 4;
+ minor = 1;
+ }
+ else if (ver_4_0) {
+ major = 4;
+ minor = 0;
+ }
+ else if (ver_3_3) {
major = 3;
minor = 3;
}
--
2.0.5
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[Mesa-dev] [PATCH v2] mesa: add support for exposing up to GL4.2
Add the 4.0/4.1/4.2 extensions lists to compute_version. A coule of
extensions aren't in mesa yet, so those are marked with 0 until they
become supported.
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
v1 - v2:
move shading_language_packing to 4.2 list
src/mesa/main/version.c | 46 +-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/version.c b/src/mesa/main/version.c
index 7c6d994..a65ace0 100644
--- a/src/mesa/main/version.c
+++ b/src/mesa/main/version.c
@@ -295,7 +295,51 @@ compute_version(const struct gl_extensions *extensions,
extensions-EXT_texture_swizzle);
/* ARB_sampler_objects is always enabled in mesa
*/
- if (ver_3_3) {
+ const GLboolean ver_4_0 = (ver_3_3
+ consts-GLSLVersion = 400
+ extensions-ARB_draw_buffers_blend
+ extensions-ARB_draw_indirect
+ extensions-ARB_gpu_shader5
+ extensions-ARB_gpu_shader_fp64
+ extensions-ARB_sample_shading
+ 0/*extensions-ARB_shader_subroutine*/
+ extensions-ARB_tessellation_shader
+ extensions-ARB_texture_buffer_object_rgb32
+ extensions-ARB_texture_cube_map_array
+ extensions-ARB_texture_query_lod
+ extensions-ARB_transform_feedback2
+ extensions-ARB_transform_feedback3);
+ const GLboolean ver_4_1 = (ver_4_0
+ consts-GLSLVersion = 410
+ extensions-ARB_ES2_compatibility
+ extensions-ARB_shader_precision
+ 0/*extensions-ARB_vertex_attrib_64bit*/
+ extensions-ARB_viewport_array);
+ const GLboolean ver_4_2 = (ver_4_1
+ consts-GLSLVersion = 420
+ extensions-ARB_base_instance
+ extensions-ARB_conservative_depth
+ extensions-ARB_internalformat_query
+ extensions-ARB_shader_atomic_counters
+ extensions-ARB_shader_image_load_store
+ extensions-ARB_shading_language_420pack
+ extensions-ARB_shading_language_packing
+ extensions-ARB_texture_compression_bptc
+ extensions-ARB_transform_feedback_instanced);
+
+ if (ver_4_2) {
+ major = 4;
+ minor = 2;
+ }
+ else if (ver_4_1) {
+ major = 4;
+ minor = 1;
+ }
+ else if (ver_4_0) {
+ major = 4;
+ minor = 0;
+ }
+ else if (ver_3_3) {
major = 3;
minor = 3;
}
--
2.0.5
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Re: [Mesa-dev] [PATCH v4] i965/aa: fixing anti-aliasing bug for thinnest width lines - GEN7
-Original Message-
From: Matt Turner [mailto:matts...@gmail.com]
Sent: Thursday, April 23, 2015 12:55 AM
To: Predut, Marius
Cc: mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] [PATCH v4] i965/aa: fixing anti-aliasing bug for
thinnest width lines - GEN7
On Thu, Apr 2, 2015 at 4:30 AM, Predut, Marius marius.pre...@intel.com
wrote:
Please review by feedback please :-)
-Original Message-
From: Predut, Marius
Sent: Thursday, March 19, 2015 9:34 PM
To: mesa-dev@lists.freedesktop.org
Cc: Predut, Marius
Subject: [Mesa-dev][PATCH v4] i965/aa: fixing anti-aliasing bug for thinnest
width lines - GEN7
I was confused by the fact that there were separate Gen6 and Gen7
patches. That's fine, though I probably wouldn't bother doing it
myself, but if that's what you want you definitely should send them as
a 2 patch series.
Having just two nearly identically named patches is prone to confusion.
I had prepared ,developed and tests the patches on the 2 different machines(SNB
and IVB) this is the reason for.
Also the patches can be applied independently , only the fix is identical.
On SNB and IVB hw, for 1 pixel line thickness or less, the general anti-
aliasing algorithm give up - garbage line is generated.
Setting a Line Width of 0.0 specifies the rasterization of the “thinnest”
(one-pixel-wide), non-antialiased lines.
Lines rendered with zero Line Width are rasterized using Grid Intersection
Quantization rules as specified by bspec section 6.3.12.1 Zero-Width
(Cosmetic) Line Rasterization.
v2: Daniel Stone: Fix = used instead of == in an if-statement.
v3: Ian Romanick: Use ._Enabled flag insteed .Enabled.
Add code comments. re-word wrap the commit message.
Add a complete bugzillia list.
Improve the hardcoded values to produce better results.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28832
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=9951
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27007
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60797
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=15006
Signed-off-by: Marius Predut marius.pre...@intel.com
---
src/mesa/drivers/dri/i965/gen7_sf_state.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c
b/src/mesa/drivers/dri/i965/gen7_sf_state.c
index c9815b0..e33cb79 100644
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c
@@ -198,9 +198,24 @@ upload_sf_state(struct brw_context *brw)
float line_width =
roundf(CLAMP(ctx-Line.Width, 0.0, ctx-Const.MaxLineWidth));
uint32_t line_width_u3_7 = U_FIXED(line_width, 7);
- /* TODO: line width of 0 is not allowed when MSAA enabled */
- if (line_width_u3_7 == 0)
- line_width_u3_7 = 1;
+ /* Line width of 0 is not allowed when MSAA enabled */
+ if (ctx-Multisample._Enabled) {
+ if (line_width_u3_7 == 0)
+ line_width_u3_7 = 1;
+ } else if (ctx-Line.SmoothFlag ctx-Line.Width = 1.49) {
I don't know what 1.49 is. Presumably you're checking for values that
line widths that round-to-nearest to 1.0? If so, shouldn't that be
ctx-Line.Width 1.5?
Yep, I use your version.( I supposed nobody thinking for lines width with the 3
decimals value :-)
+ /* For lines less than 1 pixel thick, the general
But then the comment says less than 1 pixel thick, so I don't
understand -- and it's not helping that I don't really know anything
about this code to begin with. :)
Presumably the comment in the commit message saying for 1 pixel line
thickness or less is more correct.
For what it's worth, I did confirm that this patch makes the
line-aa-width test in piglit go from fail - pass on my Haswell.
Typo fixed.
+ * anti-aliasing algorithm gives up, and a garbage line is
+ * generated. Setting a Line Width of 0.0 specifies the
+ * rasterization of the thinnest (one-pixel-wide),
+ * non-antialiased lines.
+ *
+ * Lines rendered with zero Line Width are rasterized using
+ * Grid Intersection Quantization rules as specified by
+ * bspec section 6.3.12.1 Zero-Width (Cosmetic) Line
+ * Rasterization.
+ */
+ line_width_u3_7 = 0;
+ }
dw2 |= line_width_u3_7 GEN6_SF_LINE_WIDTH_SHIFT;
}
if (ctx-Line.SmoothFlag) {
--
1.7.9.5
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Re: [Mesa-dev] [PATCH] mesa: add support for exposing up to GL4.2
On Thu, Apr 23, 2015 at 11:08 AM, Matt Turner matts...@gmail.com wrote: On Thu, Apr 23, 2015 at 7:53 AM, Ilia Mirkin imir...@alum.mit.edu wrote: Add the 4.0/4.1/4.2 extensions lists to compute_version. A coule of extensions aren't in mesa yet, so those are marked with 0 until they become supported. Signed-off-by: Ilia Mirkin imir...@alum.mit.edu --- I wasn't 100% sure about shading_language_packing -- it includes a couple of functions that don't appear until GL 4.2. However since it's enabled for all the drivers that matter in mesa, wtvr. What makes you think that? I actually fixed something recently where we were exposing some shading_language_packing functions as GLSL 4.0 instead of 4.2. As far as I'm aware, it's part of 4.2. commit 8d3aa5926b73c67c7dbd4477b7177aaa00c533e5 Author: Matt Turner matts...@gmail.com Date: Wed Mar 11 18:14:28 2015 -0700 glsl: Expose built-in packing functions under GLSL 4.2. ARB_shading_language_packing is part of GLSL 4.2, not 4.0 as I mistakenly believed. The following functions are available only with ARB_shading_language_packing, GLSL 4.2 (not GLSL 4.0), or ES 3.0: - packSnorm2x16 - unpackSnorm2x16 - packHalf2x16 - unpackHalf2x16 Reviewed-by: Carl Worth cwo...@cworth.org Reviewed-by: Marek Olšák marek.ol...@amd.com Right. Those were the functions from shading_language_packing that don't appear until GL 4.2. But other ones it includes are in GL 4.0 (packUnorm*, packSnorm4x8). In a theoretical world where we wanted to support every possibility, we'd have a separate packing_400 internal enable which would imply that only the 4.0 ones are there. But in practice, it's all-or-nothing, so who cares. So I included it in the 4.0 list. Buuut... oops. Looks like those actually come in via ARB_gpu_shader5 as well. And shading_language_packing has those *and* the extra ones (for GPUs that don't do gs5). OK. I'll move it to the 4.2 list. -ilia ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 09/12] nir: Add a simple growing array data structure
On 13/04/15 01:51, Matt Turner wrote:
On Sun, Apr 12, 2015 at 6:38 PM, Jason Ekstrand ja...@jlekstrand.net wrote:
On Apr 12, 2015 3:24 PM, Thomas Helland thomashellan...@gmail.com wrote:
Hi,
This looks correct as far as I can tell.
I have some comments inline, but I don't feel strongly about
either of them, so do as you please.
Also, maybe this is a candidate for /src/util ?
Maybe. If so I'm OK leaving it here until there are other users.
2015-04-11 2:48 GMT+02:00 Jason Ekstrand ja...@jlekstrand.net:
---
src/glsl/nir/nir_array.h | 96
1 file changed, 96 insertions(+)
create mode 100644 src/glsl/nir/nir_array.h
diff --git a/src/glsl/nir/nir_array.h b/src/glsl/nir/nir_array.h
new file mode 100644
index 000..1db4e8c
--- /dev/null
+++ b/src/glsl/nir/nir_array.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person
obtaining a
+ * copy of this software and associated documentation files (the
Software),
+ * to deal in the Software without restriction, including without
limitation
+ * the rights to use, copy, modify, merge, publish, distribute,
sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom
the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
next
+ * paragraph) shall be included in all copies or substantial portions
of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *Jason Ekstrand (ja...@jlekstrand.net)
+ *
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern C {
+#endif
+
+typedef struct {
+ void *mem_ctx;
+ size_t size;
+ size_t alloc;
Maybe alloced or alloced_mem instead?
I was a bit puzzled initially about its purpose.
Sure
FWIW, I use length and size for these two things.
There are also the std::vector names - capacity and size, if anyone
is keen on them :-)
Jason,
Can you squash the following hunk before pushing.
diff --git a/src/glsl/Makefile.sources b/src/glsl/Makefile.sources
index c471eca..d784a81 100644
--- a/src/glsl/Makefile.sources
+++ b/src/glsl/Makefile.sources
@@ -22,6 +22,7 @@ NIR_FILES = \
nir/glsl_to_nir.h \
nir/nir.c \
nir/nir.h \
+ nir/nir_array.h \
nir/nir_builder.h \
nir/nir_constant_expressions.h \
nir/nir_dominance.c \
Thanks
Emil
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[Mesa-dev] [PATCH 10/16] i965/blorp: Use virtual function for wm/ps configuration
instead of resolving the program offset and data. Different flavours
of blorp programs (blit, clear, hiz) each have its own parameter type.
The decision making on how state is configured will be moved for the
parameter type to make instead of branching explicitly in the main
body of batch submission (gen6/7_blorp_exec()).
This will be exploited even further in the subsequent patches when one
more program type is added - the one representing programs compiled
from real glsl-sources.
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 7 ---
src/mesa/drivers/dri/i965/brw_blorp.h| 20 ---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 13 ++---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 17
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 29
5 files changed, 57 insertions(+), 29 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index b404869..300cafe 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -335,10 +335,3 @@ brw_hiz_op_params::brw_hiz_op_params(struct
intel_mipmap_tree *mt,
default:unreachable(not reached);
}
}
-
-uint32_t
-brw_hiz_op_params::get_wm_prog(struct brw_context *brw,
- brw_blorp_prog_data **prog_data) const
-{
- return 0;
-}
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 695414a..a2682da 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -215,8 +215,10 @@ public:
unsigned num_draw_buffers = 1,
unsigned num_layers = 1);
- virtual uint32_t get_wm_prog(struct brw_context *brw,
-brw_blorp_prog_data **prog_data) const = 0;
+ virtual void gen6_emit_wm_config(struct brw_context *brw) const;
+ virtual void gen7_emit_wm_config(struct brw_context *brw) const;
+
+ virtual void gen7_emit_ps_config(struct brw_context *brw) const;
uint32_t x0;
uint32_t y0;
@@ -254,9 +256,6 @@ public:
brw_hiz_op_params(struct intel_mipmap_tree *mt,
unsigned int level, unsigned int layer,
gen6_hiz_op op);
-
- virtual uint32_t get_wm_prog(struct brw_context *brw,
-brw_blorp_prog_data **prog_data) const;
};
struct brw_blorp_blit_prog_key
@@ -354,11 +353,18 @@ public:
GLfloat dst_x1, GLfloat dst_y1,
GLenum filter, bool mirror_x, bool mirror_y);
- virtual uint32_t get_wm_prog(struct brw_context *brw,
-brw_blorp_prog_data **prog_data) const;
+ virtual void gen6_emit_wm_config(struct brw_context *brw) const;
+ virtual void gen7_emit_wm_config(struct brw_context *brw) const;
+
+ virtual void gen7_emit_ps_config(struct brw_context *brw) const;
private:
+ void set_wm_prog(struct brw_context *brw);
+
brw_blorp_blit_prog_key wm_prog_key;
+
+ brw_blorp_prog_data *prog_data;
+ uint32_t prog_offset;
};
/**
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 1561b59..947f3b0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -2115,16 +2115,16 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
src.x_offset *= 2;
src.y_offset /= 2;
}
+
+ set_wm_prog(brw);
}
-uint32_t
-brw_blorp_blit_params::get_wm_prog(struct brw_context *brw,
- brw_blorp_prog_data **prog_data) const
+void
+brw_blorp_blit_params::set_wm_prog(struct brw_context *brw)
{
- uint32_t prog_offset = 0;
if (!brw_search_cache(brw-cache, BRW_CACHE_BLORP_BLIT_PROG,
this-wm_prog_key, sizeof(this-wm_prog_key),
- prog_offset, prog_data)) {
+ prog_offset, prog_data)) {
brw_blorp_blit_program prog(brw, this-wm_prog_key,
INTEL_DEBUG DEBUG_BLORP);
GLuint program_size;
@@ -2133,7 +2133,6 @@ brw_blorp_blit_params::get_wm_prog(struct brw_context
*brw,
this-wm_prog_key, sizeof(this-wm_prog_key),
program, program_size,
prog.prog_data, sizeof(prog.prog_data),
- prog_offset, prog_data);
+ prog_offset, prog_data);
}
- return prog_offset;
}
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 21c8423..39fbb24 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -998,6 +998,18 @@ gen6_blorp_emit_primitive(struct brw_context *brw,
ADVANCE_BATCH();
}
[Mesa-dev] [PATCH 03/16] i965/blorp: Allow caller to provide sampler settings
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.h| 4 +++-
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 15 +--
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 3 ++-
3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 59aecab..63dfe5b 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -415,7 +415,9 @@ gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
uint32_t
gen6_blorp_emit_sampler_state(struct brw_context *brw,
- const brw_blorp_params *params);
+ unsigned tex_filter, unsigned max_lod,
+ bool use_unorm_coords);
+
/** \} */
#endif /* __cplusplus */
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 6c139ec..ae4f34d 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -455,7 +455,8 @@ gen6_blorp_emit_binding_table(struct brw_context *brw,
*/
uint32_t
gen6_blorp_emit_sampler_state(struct brw_context *brw,
- const brw_blorp_params *params)
+ unsigned tex_filter, unsigned max_lod,
+ bool use_unorm_coords)
{
uint32_t sampler_offset;
uint32_t *sampler_state = (uint32_t *)
@@ -476,8 +477,8 @@ gen6_blorp_emit_sampler_state(struct brw_context *brw,
brw_emit_sampler_state(brw,
sampler_state,
sampler_offset,
- BRW_MAPFILTER_LINEAR, /* min filter */
- BRW_MAPFILTER_LINEAR, /* mag filter */
+ tex_filter, /* min filter */
+ tex_filter, /* mag filter */
BRW_MIPFILTER_NONE,
BRW_ANISORATIO_2,
address_rounding,
@@ -485,11 +486,11 @@ gen6_blorp_emit_sampler_state(struct brw_context *brw,
BRW_TEXCOORDMODE_CLAMP,
BRW_TEXCOORDMODE_CLAMP,
0, /* min LOD */
- 0, /* max LOD */
+ max_lod,
0, /* LOD bias */
0, /* base miplevel */
0, /* shadow function */
- true, /* non-normalized coordinates */
+ use_unorm_coords,
0); /* border color offset - unused */
return sampler_offset;
@@ -1059,7 +1060,9 @@ gen6_blorp_exec(struct brw_context *brw,
gen6_blorp_emit_binding_table(brw, params,
wm_surf_offset_renderbuffer,
wm_surf_offset_texture);
- sampler_offset = gen6_blorp_emit_sampler_state(brw, params);
+ sampler_offset =
+ gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
+
gen6_blorp_emit_sampler_state_pointers(brw, params, sampler_offset);
}
gen6_blorp_emit_vs_disable(brw, params);
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 8215fe9..d841346 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -830,7 +830,8 @@ gen7_blorp_exec(struct brw_context *brw,
gen6_blorp_emit_binding_table(brw, params,
wm_surf_offset_renderbuffer,
wm_surf_offset_texture);
- sampler_offset = gen6_blorp_emit_sampler_state(brw, params);
+ sampler_offset =
+ gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
}
gen7_blorp_emit_vs_disable(brw, params);
gen7_blorp_emit_hs_disable(brw, params);
--
1.9.3
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[Mesa-dev] [PATCH 09/16] i965/blorp: Prepare drawing rectangle for flipped coordinates
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com --- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index 4f4d752..21c8423 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -950,8 +950,8 @@ gen6_blorp_emit_drawing_rectangle(struct brw_context *brw, BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE 16 | (4 - 2)); OUT_BATCH(0); - OUT_BATCH(((params-x1 - 1) 0x) | - ((params-y1 - 1) 16)); + OUT_BATCH(((MAX2(params-x1, params-x0) - 1) 0x) | + ((MAX2(params-y1, params-y0) - 1) 16)); OUT_BATCH(0); ADVANCE_BATCH(); } -- 1.9.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 16/16] i965/blorp: Move multisample setup for parameter type to handle
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.h| 2 ++
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 14 ++
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 5 +
3 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index c005bdf..2abe654 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -225,6 +225,8 @@ public:
virtual void gen6_emit_sampler_state(struct brw_context *brw) const;
+ virtual void gen6_emit_multisample_state(struct brw_context *brw) const;
+
virtual void gen7_emit_ps_config(struct brw_context *brw) const;
virtual void gen6_emit_vertices(struct brw_context *brw) const;
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 3b18001..77de474 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -1021,6 +1021,15 @@ brw_blorp_params::gen6_emit_sampler_state(struct
brw_context *brw) const
}
void
+brw_blorp_params::gen6_emit_multisample_state(struct brw_context *brw) const
+{
+ gen6_emit_3dstate_multisample(brw, dst.num_samples);
+ gen6_emit_3dstate_sample_mask(brw,
+ dst.num_samples 1 ?
+(1 dst.num_samples) - 1 : 1);
+}
+
+void
brw_blorp_blit_params::gen6_emit_wm_constants(struct brw_context *brw)
{
wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, this);
@@ -1092,10 +1101,7 @@ gen6_blorp_exec(struct brw_context *brw,
/* Emit workaround flushes when we switch from drawing to blorping. */
intel_emit_post_sync_nonzero_flush(brw);
- gen6_emit_3dstate_multisample(brw, params-dst.num_samples);
- gen6_emit_3dstate_sample_mask(brw,
- params-dst.num_samples 1 ?
- (1 params-dst.num_samples) - 1 : 1);
+ params-gen6_emit_multisample_state(brw);
gen6_blorp_emit_state_base_address(brw, params);
params-gen6_emit_vertices(brw);
gen6_blorp_emit_urb_config(brw, params);
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index feb31d5..f430fa0 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -818,10 +818,7 @@ gen7_blorp_exec(struct brw_context *brw,
uint32_t cc_state_offset = 0;
uint32_t depthstencil_offset;
- gen6_emit_3dstate_multisample(brw, params-dst.num_samples);
- gen6_emit_3dstate_sample_mask(brw,
- params-dst.num_samples 1 ?
- (1 params-dst.num_samples) - 1 : 1);
+ params-gen6_emit_multisample_state(brw);
gen6_blorp_emit_state_base_address(brw, params);
params-gen6_emit_vertices(brw);
gen7_blorp_emit_urb_config(brw);
--
1.9.3
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[Mesa-dev] [PATCH 15/16] i965/blorp: Move vertex uploading for parameter type to handle
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.h| 6 ++
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 11 +--
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 2 +-
3 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 238a966..c005bdf 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -227,6 +227,8 @@ public:
virtual void gen7_emit_ps_config(struct brw_context *brw) const;
+ virtual void gen6_emit_vertices(struct brw_context *brw) const;
+
uint32_t x0;
uint32_t y0;
uint32_t x1;
@@ -398,10 +400,6 @@ void
gen6_blorp_emit_state_base_address(struct brw_context *brw,
const brw_blorp_params *params);
-void
-gen6_blorp_emit_vertices(struct brw_context *brw,
- const brw_blorp_params *params);
-
uint32_t
gen6_blorp_emit_blend_state(struct brw_context *brw,
const brw_blorp_params *params);
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 612a06d..3b18001 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -126,8 +126,7 @@ gen6_blorp_emit_vertex_buffer_state(struct brw_context *brw,
}
void
-gen6_blorp_emit_vertices(struct brw_context *brw,
- const brw_blorp_params *params)
+brw_blorp_params::gen6_emit_vertices(struct brw_context *brw) const
{
uint32_t vertex_offset;
@@ -164,9 +163,9 @@ gen6_blorp_emit_vertices(struct brw_context *brw,
float *vertex_data;
const float vertices[GEN6_BLORP_VBO_SIZE] = {
- /* v0 */ 0, 0, 0, 0, (float) params-x0, (float) params-y1, 0, 1,
- /* v1 */ 0, 0, 0, 0, (float) params-x1, (float) params-y1, 0, 1,
- /* v2 */ 0, 0, 0, 0, (float) params-x0, (float) params-y0, 0, 1,
+ /* v0 */ 0, 0, 0, 0, (float) x0, (float) y1, 0, 1,
+ /* v1 */ 0, 0, 0, 0, (float) x1, (float) y1, 0, 1,
+ /* v2 */ 0, 0, 0, 0, (float) x0, (float) y0, 0, 1,
};
vertex_data = (float *) brw_state_batch(brw, AUB_TRACE_VERTEX_BUFFER,
@@ -1098,7 +1097,7 @@ gen6_blorp_exec(struct brw_context *brw,
params-dst.num_samples 1 ?
(1 params-dst.num_samples) - 1 : 1);
gen6_blorp_emit_state_base_address(brw, params);
- gen6_blorp_emit_vertices(brw, params);
+ params-gen6_emit_vertices(brw);
gen6_blorp_emit_urb_config(brw, params);
if (params-use_wm_prog) {
cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 4c07820..feb31d5 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -823,7 +823,7 @@ gen7_blorp_exec(struct brw_context *brw,
params-dst.num_samples 1 ?
(1 params-dst.num_samples) - 1 : 1);
gen6_blorp_emit_state_base_address(brw, params);
- gen6_blorp_emit_vertices(brw, params);
+ params-gen6_emit_vertices(brw);
gen7_blorp_emit_urb_config(brw);
if (params-use_wm_prog) {
cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
--
1.9.3
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[Mesa-dev] [PATCH 14/16] i965/blorp/gen7: Move surface setup for the parameter type to handle
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.h| 3 ++
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 55 ++--
2 files changed, 34 insertions(+), 24 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index d07d3c0..238a966 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -218,6 +218,7 @@ public:
virtual void gen6_emit_wm_constants(struct brw_context *brw);
virtual void gen6_emit_surface_states(struct brw_context *brw);
+ virtual void gen7_emit_surface_states(struct brw_context *brw);
virtual void gen6_emit_wm_config(struct brw_context *brw) const;
virtual void gen7_emit_wm_config(struct brw_context *brw) const;
@@ -362,6 +363,7 @@ public:
virtual void gen6_emit_wm_constants(struct brw_context *brw);
virtual void gen6_emit_surface_states(struct brw_context *brw);
+ virtual void gen7_emit_surface_states(struct brw_context *brw);
virtual void gen6_emit_wm_config(struct brw_context *brw) const;
virtual void gen7_emit_wm_config(struct brw_context *brw) const;
@@ -379,6 +381,7 @@ private:
uint32_t prog_offset;
uint32_t wm_push_const_offset;
uint32_t wm_bind_bo_offset;
+ uint32_t sampler_offset;
};
/**
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index ce4e46d..4c07820 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -755,6 +755,11 @@ brw_blorp_params::gen7_emit_wm_config(struct brw_context
*brw) const
}
void
+brw_blorp_params::gen7_emit_surface_states(struct brw_context *brw)
+{
+}
+
+void
brw_blorp_params::gen7_emit_ps_config(struct brw_context *brw) const
{
gen7_blorp_emit_constant_ps_disable(brw);
@@ -765,6 +770,31 @@ void
brw_blorp_blit_params::gen7_emit_wm_config(struct brw_context *brw) const
{
gen7_blorp_emit_wm_config(brw, this, prog_data);
+ gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
+}
+
+void
+brw_blorp_blit_params::gen7_emit_surface_states(struct brw_context *brw)
+{
+ uint32_t wm_surf_offset_renderbuffer;
+ uint32_t wm_surf_offset_texture = 0;
+ intel_miptree_used_for_rendering(dst.mt);
+ wm_surf_offset_renderbuffer =
+ gen7_blorp_emit_surface_state(brw, dst,
+I915_GEM_DOMAIN_RENDER,
+I915_GEM_DOMAIN_RENDER,
+true /* is_render_target */);
+ if (src.mt) {
+ wm_surf_offset_texture =
+ gen7_blorp_emit_surface_state(brw, src,
+ I915_GEM_DOMAIN_SAMPLER, 0,
+ false /* is_render_target */);
+ }
+
+ wm_bind_bo_offset =
+ gen6_blorp_emit_binding_table(brw,
+wm_surf_offset_renderbuffer,
+wm_surf_offset_texture);
}
void
@@ -787,7 +817,6 @@ gen7_blorp_exec(struct brw_context *brw,
uint32_t cc_blend_state_offset = 0;
uint32_t cc_state_offset = 0;
uint32_t depthstencil_offset;
- uint32_t wm_bind_bo_offset = 0;
gen6_emit_3dstate_multisample(brw, params-dst.num_samples);
gen6_emit_3dstate_sample_mask(brw,
@@ -805,26 +834,7 @@ gen7_blorp_exec(struct brw_context *brw,
depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
gen7_blorp_emit_depth_stencil_state_pointers(brw, depthstencil_offset);
params-gen6_emit_wm_constants(brw);
- if (params-use_wm_prog) {
- uint32_t wm_surf_offset_renderbuffer;
- uint32_t wm_surf_offset_texture = 0;
- intel_miptree_used_for_rendering(params-dst.mt);
- wm_surf_offset_renderbuffer =
- gen7_blorp_emit_surface_state(brw, params-dst,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER,
- true /* is_render_target */);
- if (params-src.mt) {
- wm_surf_offset_texture =
-gen7_blorp_emit_surface_state(brw, params-src,
- I915_GEM_DOMAIN_SAMPLER, 0,
- false /* is_render_target */);
- }
- wm_bind_bo_offset =
- gen6_blorp_emit_binding_table(brw,
- wm_surf_offset_renderbuffer,
- wm_surf_offset_texture);
- }
+ params-gen7_emit_surface_states(brw);
params-gen6_emit_sampler_state(brw);
gen7_blorp_emit_vs_disable(brw);
gen7_blorp_emit_hs_disable(brw);
@@ -835,9 +845,6 @@ gen7_blorp_exec(struct brw_context *brw,
gen6_blorp_emit_clip_disable(brw);
gen7_blorp_emit_sf_config(brw, params);
params-gen7_emit_wm_config(brw);
- if (params-use_wm_prog) {
- gen7_blorp_emit_binding_table_pointers_ps(brw,
[Mesa-dev] [PATCH 04/16] i965/gen7/blorp: Remove unused arguments
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 75
1 file changed, 28 insertions(+), 47 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index d841346..c9e7cb7 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -48,8 +48,7 @@
* valid.
*/
static void
-gen7_blorp_emit_urb_config(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_urb_config(struct brw_context *brw)
{
unsigned urb_size = (brw-is_haswell brw-gt == 3) ? 32 : 16;
gen7_emit_push_constant_state(brw,
@@ -73,7 +72,6 @@ gen7_blorp_emit_urb_config(struct brw_context *brw,
/* 3DSTATE_BLEND_STATE_POINTERS */
static void
gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
-const brw_blorp_params *params,
uint32_t cc_blend_state_offset)
{
BEGIN_BATCH(2);
@@ -86,7 +84,6 @@ gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
/* 3DSTATE_CC_STATE_POINTERS */
static void
gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t cc_state_offset)
{
BEGIN_BATCH(2);
@@ -96,8 +93,7 @@ gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
}
static void
-gen7_blorp_emit_cc_viewport(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_cc_viewport(struct brw_context *brw)
{
struct brw_cc_viewport *ccv;
uint32_t cc_vp_offset;
@@ -121,7 +117,6 @@ gen7_blorp_emit_cc_viewport(struct brw_context *brw,
*/
static void
gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t depthstencil_offset)
{
BEGIN_BATCH(2);
@@ -136,7 +131,6 @@ gen7_blorp_emit_depth_stencil_state_pointers(struct
brw_context *brw,
*/
static uint32_t
gen7_blorp_emit_surface_state(struct brw_context *brw,
- const brw_blorp_params *params,
const brw_blorp_surface_info *surface,
uint32_t read_domains, uint32_t write_domain,
bool is_render_target)
@@ -228,8 +222,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
* Disable vertex shader.
*/
static void
-gen7_blorp_emit_vs_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_vs_disable(struct brw_context *brw)
{
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_CONSTANT_VS 16 | (7 - 2));
@@ -257,8 +250,7 @@ gen7_blorp_emit_vs_disable(struct brw_context *brw,
* Disable the hull shader.
*/
static void
-gen7_blorp_emit_hs_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_hs_disable(struct brw_context *brw)
{
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_CONSTANT_HS 16 | (7 - 2));
@@ -287,8 +279,7 @@ gen7_blorp_emit_hs_disable(struct brw_context *brw,
* Disable the tesselation engine.
*/
static void
-gen7_blorp_emit_te_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_te_disable(struct brw_context *brw)
{
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_TE 16 | (4 - 2));
@@ -304,8 +295,7 @@ gen7_blorp_emit_te_disable(struct brw_context *brw,
* Disable the domain shader.
*/
static void
-gen7_blorp_emit_ds_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_ds_disable(struct brw_context *brw)
{
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_CONSTANT_DS 16 | (7 - 2));
@@ -332,8 +322,7 @@ gen7_blorp_emit_ds_disable(struct brw_context *brw,
* Disable the geometry shader.
*/
static void
-gen7_blorp_emit_gs_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_gs_disable(struct brw_context *brw)
{
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_CONSTANT_GS 16 | (7 - 2));
@@ -377,8 +366,7 @@ gen7_blorp_emit_gs_disable(struct brw_context *brw,
* Disable streamout.
*/
static void
-gen7_blorp_emit_streamout_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_streamout_disable(struct brw_context *brw)
{
BEGIN_BATCH(3);
OUT_BATCH(_3DSTATE_STREAMOUT 16 | (3 - 2));
@@ -544,7 +532,6 @@ gen7_blorp_emit_ps_config(struct brw_context *brw,
static void
gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t wm_bind_bo_offset)
{
[Mesa-dev] [PATCH 01/16] i965/blorp: Remove constant parameter
This was still needed when we had support for blorp clears but now
this is fixed to nop.
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 1 -
src/mesa/drivers/dri/i965/brw_blorp.h| 8
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 11 ---
3 files changed, 20 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 131e155..b0de55d 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -162,7 +162,6 @@ brw_blorp_params::brw_blorp_params()
y1(0),
depth_format(0),
hiz_op(GEN6_HIZ_OP_NONE),
- fast_clear_op(GEN7_FAST_CLEAR_OP_NONE),
use_wm_prog(false)
{
color_write_disable[0] = false;
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index ff68000..59aecab 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -208,13 +208,6 @@ struct brw_blorp_prog_data
};
-enum gen7_fast_clear_op {
- GEN7_FAST_CLEAR_OP_NONE,
- GEN7_FAST_CLEAR_OP_FAST_CLEAR,
- GEN7_FAST_CLEAR_OP_RESOLVE,
-};
-
-
class brw_blorp_params
{
public:
@@ -232,7 +225,6 @@ public:
brw_blorp_surface_info src;
brw_blorp_surface_info dst;
enum gen6_hiz_op hiz_op;
- enum gen7_fast_clear_op fast_clear_op;
bool use_wm_prog;
brw_blorp_wm_push_constants wm_push_consts;
bool color_write_disable[4];
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index fb6a0dd..8215fe9 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -529,17 +529,6 @@ gen7_blorp_emit_ps_config(struct brw_context *brw,
dw5 |= prog_data-first_curbe_grf GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
}
- switch (params-fast_clear_op) {
- case GEN7_FAST_CLEAR_OP_FAST_CLEAR:
- dw4 |= GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
- break;
- case GEN7_FAST_CLEAR_OP_RESOLVE:
- dw4 |= GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE;
- break;
- default:
- break;
- }
-
BEGIN_BATCH(8);
OUT_BATCH(_3DSTATE_PS 16 | (8 - 2));
OUT_BATCH(params-use_wm_prog ? prog_offset : 0);
--
1.9.3
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[Mesa-dev] [PATCH 11/16] i965/blorp: Move push const setup for the parameter type to handle
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_blorp.h| 7 ++-
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 22 +++---
src/mesa/drivers/dri/i965/gen6_blorp.h | 2 +-
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 10 --
src/mesa/drivers/dri/i965/gen7_blorp.h | 2 +-
6 files changed, 28 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 300cafe..680db75 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -207,7 +207,7 @@ intel_hiz_exec(struct brw_context *brw, struct
intel_mipmap_tree *mt,
} /* extern C */
void
-brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
+brw_blorp_exec(struct brw_context *brw, brw_blorp_params *params)
{
struct gl_context *ctx = brw-ctx;
uint32_t estimated_max_batch_usage = 1500;
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index a2682da..0149197 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -215,6 +215,8 @@ public:
unsigned num_draw_buffers = 1,
unsigned num_layers = 1);
+ virtual void gen6_emit_wm_constants(struct brw_context *brw);
+
virtual void gen6_emit_wm_config(struct brw_context *brw) const;
virtual void gen7_emit_wm_config(struct brw_context *brw) const;
@@ -238,7 +240,7 @@ public:
void
-brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params);
+brw_blorp_exec(struct brw_context *brw, brw_blorp_params *params);
/**
@@ -353,6 +355,8 @@ public:
GLfloat dst_x1, GLfloat dst_y1,
GLenum filter, bool mirror_x, bool mirror_y);
+ virtual void gen6_emit_wm_constants(struct brw_context *brw);
+
virtual void gen6_emit_wm_config(struct brw_context *brw) const;
virtual void gen7_emit_wm_config(struct brw_context *brw) const;
@@ -365,6 +369,7 @@ private:
brw_blorp_prog_data *prog_data;
uint32_t prog_offset;
+ uint32_t wm_push_const_offset;
};
/**
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 39fbb24..d42b7f3 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -999,14 +999,27 @@ gen6_blorp_emit_primitive(struct brw_context *brw,
}
void
+brw_blorp_params::gen6_emit_wm_constants(struct brw_context *)
+{
+}
+
+void
brw_blorp_params::gen6_emit_wm_config(struct brw_context *brw) const
{
+ gen6_blorp_emit_constant_ps_disable(brw, this);
gen6_blorp_emit_wm_config(brw, this, 0, NULL);
}
void
+brw_blorp_blit_params::gen6_emit_wm_constants(struct brw_context *brw)
+{
+ wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, this);
+}
+
+void
brw_blorp_blit_params::gen6_emit_wm_config(struct brw_context *brw) const
{
+ gen6_blorp_emit_constant_ps(brw, this, wm_push_const_offset);
gen6_blorp_emit_wm_config(brw, this, prog_offset, prog_data);
}
@@ -1021,12 +1034,11 @@ brw_blorp_blit_params::gen6_emit_wm_config(struct
brw_context *brw) const
*/
void
gen6_blorp_exec(struct brw_context *brw,
-const brw_blorp_params *params)
+brw_blorp_params *params)
{
uint32_t cc_blend_state_offset = 0;
uint32_t cc_state_offset = 0;
uint32_t depthstencil_offset;
- uint32_t wm_push_const_offset = 0;
uint32_t wm_bind_bo_offset = 0;
/* Emit workaround flushes when we switch from drawing to blorping. */
@@ -1046,11 +1058,11 @@ gen6_blorp_exec(struct brw_context *brw,
depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
gen6_blorp_emit_cc_state_pointers(brw, params, cc_blend_state_offset,
depthstencil_offset, cc_state_offset);
+ params-gen6_emit_wm_constants(brw);
if (params-use_wm_prog) {
uint32_t wm_surf_offset_renderbuffer;
uint32_t wm_surf_offset_texture = 0;
uint32_t sampler_offset;
- wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
intel_miptree_used_for_rendering(params-dst.mt);
wm_surf_offset_renderbuffer =
gen6_blorp_emit_surface_state(brw, params, params-dst,
@@ -1073,10 +1085,6 @@ gen6_blorp_exec(struct brw_context *brw,
gen6_blorp_emit_gs_disable(brw, params);
gen6_blorp_emit_clip_disable(brw);
gen6_blorp_emit_sf_config(brw, params);
- if (params-use_wm_prog)
- gen6_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
- else
- gen6_blorp_emit_constant_ps_disable(brw, params);
params-gen6_emit_wm_config(brw);
if (params-use_wm_prog)
gen6_blorp_emit_binding_table_pointers(brw, wm_bind_bo_offset);
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.h
[Mesa-dev] [PATCH 05/16] i965/blorp: Remove unused arguments
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.h| 7 ++-
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 20 +++-
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 6 +++---
3 files changed, 12 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 63dfe5b..5889f3e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -380,8 +380,7 @@ gen6_blorp_emit_blend_state(struct brw_context *brw,
const brw_blorp_params *params);
uint32_t
-gen6_blorp_emit_cc_state(struct brw_context *brw,
- const brw_blorp_params *params);
+gen6_blorp_emit_cc_state(struct brw_context *brw);
uint32_t
gen6_blorp_emit_wm_constants(struct brw_context *brw,
@@ -393,7 +392,6 @@ gen6_blorp_emit_vs_disable(struct brw_context *brw,
uint32_t
gen6_blorp_emit_binding_table(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t wm_surf_offset_renderbuffer,
uint32_t wm_surf_offset_texture);
@@ -406,8 +404,7 @@ gen6_blorp_emit_gs_disable(struct brw_context *brw,
const brw_blorp_params *params);
void
-gen6_blorp_emit_clip_disable(struct brw_context *brw,
- const brw_blorp_params *params);
+gen6_blorp_emit_clip_disable(struct brw_context *brw);
void
gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index ae4f34d..9b54b93 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -268,8 +268,7 @@ gen6_blorp_emit_blend_state(struct brw_context *brw,
/* CC_STATE */
uint32_t
-gen6_blorp_emit_cc_state(struct brw_context *brw,
- const brw_blorp_params *params)
+gen6_blorp_emit_cc_state(struct brw_context *brw)
{
uint32_t cc_state_offset;
@@ -431,7 +430,6 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
/* BINDING_TABLE. See brw_wm_binding_table(). */
uint32_t
gen6_blorp_emit_binding_table(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t wm_surf_offset_renderbuffer,
uint32_t wm_surf_offset_texture)
{
@@ -502,7 +500,6 @@ gen6_blorp_emit_sampler_state(struct brw_context *brw,
*/
static void
gen6_blorp_emit_sampler_state_pointers(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t sampler_offset)
{
BEGIN_BATCH(4);
@@ -602,8 +599,7 @@ gen6_blorp_emit_gs_disable(struct brw_context *brw,
* output, but does spare a few electrons.
*/
void
-gen6_blorp_emit_clip_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen6_blorp_emit_clip_disable(struct brw_context *brw)
{
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_CLIP 16 | (4 - 2));
@@ -767,7 +763,6 @@ gen6_blorp_emit_constant_ps_disable(struct brw_context *brw,
*/
static void
gen6_blorp_emit_binding_table_pointers(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t wm_bind_bo_offset)
{
BEGIN_BATCH(4);
@@ -1036,7 +1031,7 @@ gen6_blorp_exec(struct brw_context *brw,
gen6_blorp_emit_urb_config(brw, params);
if (params-use_wm_prog) {
cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
- cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
+ cc_state_offset = gen6_blorp_emit_cc_state(brw);
}
depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
gen6_blorp_emit_cc_state_pointers(brw, params, cc_blend_state_offset,
@@ -1057,17 +1052,16 @@ gen6_blorp_exec(struct brw_context *brw,
I915_GEM_DOMAIN_SAMPLER, 0);
}
wm_bind_bo_offset =
- gen6_blorp_emit_binding_table(brw, params,
+ gen6_blorp_emit_binding_table(brw,
wm_surf_offset_renderbuffer,
wm_surf_offset_texture);
sampler_offset =
gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
-
- gen6_blorp_emit_sampler_state_pointers(brw, params, sampler_offset);
+ gen6_blorp_emit_sampler_state_pointers(brw, sampler_offset);
}
gen6_blorp_emit_vs_disable(brw, params);
gen6_blorp_emit_gs_disable(brw, params);
- gen6_blorp_emit_clip_disable(brw, params);
+ gen6_blorp_emit_clip_disable(brw);
gen6_blorp_emit_sf_config(brw, params);
if (params-use_wm_prog)
[Mesa-dev] [PATCH 0.5/18] i965/gen8: Use constant pointers for reading miptree details
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 011c685..b9bbb73 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -70,7 +70,7 @@ surface_tiling_mode(uint32_t tiling)
}
static unsigned
-vertical_alignment(struct intel_mipmap_tree *mt)
+vertical_alignment(const struct intel_mipmap_tree *mt)
{
switch (mt-align_h) {
case 4:
@@ -85,7 +85,7 @@ vertical_alignment(struct intel_mipmap_tree *mt)
}
static unsigned
-horizontal_alignment(struct intel_mipmap_tree *mt)
+horizontal_alignment(const struct intel_mipmap_tree *mt)
{
switch (mt-align_w) {
case 4:
--
1.9.3
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Re: [Mesa-dev] [PATCH V2 03/22] i965: Move intel_miptree_choose_tiling() to brw_tex_layout.c
On Fri, Apr 17, 2015 at 04:51:24PM -0700, Anuj Phogat wrote:
Patch continues code refactoring.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 105
++
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 104 -
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 8 --
3 files changed, 105 insertions(+), 112 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index b8408d3..08ef7a6 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -377,6 +377,111 @@ brw_miptree_layout_texture_3d(struct brw_context *brw,
align_cube(mt);
}
+/**
+ * \brief Helper function for intel_miptree_create().
+ */
+static uint32_t
+intel_miptree_choose_tiling(struct brw_context *brw,
All the other functions in this file use brw_miptree-prefix, perhaps
this should be as well?
+mesa_format format,
+uint32_t width0,
+uint32_t num_samples,
+enum intel_miptree_tiling_mode requested,
+struct intel_mipmap_tree *mt)
You could change both 'brw' and 'mt' to constant pointers, they are only
used for reading.
With that:
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
+{
+ if (format == MESA_FORMAT_S_UINT8) {
+ /* The stencil buffer is W tiled. However, we request from the kernel a
+ * non-tiled buffer because the GTT is incapable of W fencing.
+ */
+ return I915_TILING_NONE;
+ }
+
+ /* Some usages may want only one type of tiling, like depth miptrees (Y
+* tiled), or temporary BOs for uploading data once (linear).
+*/
+ switch (requested) {
+ case INTEL_MIPTREE_TILING_ANY:
+ break;
+ case INTEL_MIPTREE_TILING_Y:
+ return I915_TILING_Y;
+ case INTEL_MIPTREE_TILING_NONE:
+ return I915_TILING_NONE;
+ }
+
+ if (num_samples 1) {
+ /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE (Tiled
+ * Surface):
+ *
+ * [DevSNB+]: For multi-sample render targets, this field must be
+ * 1. MSRTs can only be tiled.
+ *
+ * Our usual reason for preferring X tiling (fast blits using the
+ * blitting engine) doesn't apply to MSAA, since we'll generally be
+ * downsampling or upsampling when blitting between the MSAA buffer
+ * and another buffer, and the blitting engine doesn't support that.
+ * So use Y tiling, since it makes better use of the cache.
+ */
+ return I915_TILING_Y;
+ }
+
+ GLenum base_format = _mesa_get_format_base_format(format);
+ if (base_format == GL_DEPTH_COMPONENT ||
+ base_format == GL_DEPTH_STENCIL_EXT)
+ return I915_TILING_Y;
+
+ /* 1D textures (and 1D array textures) don't get any benefit from tiling,
+* in fact it leads to a less efficient use of memory space and bandwidth
+* due to tile alignment.
+*/
+ if (mt-logical_height0 == 1)
+ return I915_TILING_NONE;
+
+ int minimum_pitch = mt-total_width * mt-cpp;
+
+ /* If the width is much smaller than a tile, don't bother tiling. */
+ if (minimum_pitch 64)
+ return I915_TILING_NONE;
+
+ if (ALIGN(minimum_pitch, 512) = 32768 ||
+ mt-total_width = 32768 || mt-total_height = 32768) {
+ perf_debug(%dx%d miptree too large to blit, falling back to untiled,
+ mt-total_width, mt-total_height);
+ return I915_TILING_NONE;
+ }
+
+ /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
+ if (brw-gen 6)
+ return I915_TILING_X;
+
+ /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
+* NOTE: 128BPE Format Color Buffer ( render target ) MUST be either
TileX
+* or Linear.
+* 128 bits per pixel translates to 16 bytes per pixel. This is necessary
+* all the way back to 965, but is permitted on Gen7+.
+*/
+ if (brw-gen 7 mt-cpp = 16)
+ return I915_TILING_X;
+
+ /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
+* messages), on p64, under the heading Surface Vertical Alignment:
+*
+* This field must be set to VALIGN_4 for all tiled Y Render Target
+* surfaces.
+*
+* So if the surface is renderable and uses a vertical alignment of 2,
+* force it to be X tiled. This is somewhat conservative (it's possible
+* that the client won't ever render to this surface), but it's difficult
+* to know that ahead of time. And besides, since we use a vertical
+* alignment of 4 as often as we can, this shouldn't happen very often.
+*/
+ if (brw-gen == 7 mt-align_h == 2
+ brw-format_supported_as_render_target[format]) {
+ return I915_TILING_X;
+ }
+
+
[Mesa-dev] [PATCH 13/16] i965/blorp/gen6: Move surface setup for the parameter type to handle
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.h| 5
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 50 ++--
2 files changed, 34 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 7ea82c0..d07d3c0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -217,6 +217,8 @@ public:
virtual void gen6_emit_wm_constants(struct brw_context *brw);
+ virtual void gen6_emit_surface_states(struct brw_context *brw);
+
virtual void gen6_emit_wm_config(struct brw_context *brw) const;
virtual void gen7_emit_wm_config(struct brw_context *brw) const;
@@ -359,6 +361,8 @@ public:
virtual void gen6_emit_wm_constants(struct brw_context *brw);
+ virtual void gen6_emit_surface_states(struct brw_context *brw);
+
virtual void gen6_emit_wm_config(struct brw_context *brw) const;
virtual void gen7_emit_wm_config(struct brw_context *brw) const;
@@ -374,6 +378,7 @@ private:
brw_blorp_prog_data *prog_data;
uint32_t prog_offset;
uint32_t wm_push_const_offset;
+ uint32_t wm_bind_bo_offset;
};
/**
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index d5f89bb..612a06d 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -1005,6 +1005,11 @@ brw_blorp_params::gen6_emit_wm_constants(struct
brw_context *)
}
void
+brw_blorp_params::gen6_emit_surface_states(struct brw_context *brw)
+{
+}
+
+void
brw_blorp_params::gen6_emit_wm_config(struct brw_context *brw) const
{
gen6_blorp_emit_constant_ps_disable(brw, this);
@@ -1023,10 +1028,33 @@ brw_blorp_blit_params::gen6_emit_wm_constants(struct
brw_context *brw)
}
void
+brw_blorp_blit_params::gen6_emit_surface_states(struct brw_context *brw)
+{
+ uint32_t wm_surf_offset_renderbuffer;
+ uint32_t wm_surf_offset_texture = 0;
+
+ intel_miptree_used_for_rendering(dst.mt);
+ wm_surf_offset_renderbuffer =
+ gen6_blorp_emit_surface_state(brw, this, dst,
+I915_GEM_DOMAIN_RENDER,
+I915_GEM_DOMAIN_RENDER);
+ if (src.mt)
+ wm_surf_offset_texture =
+ gen6_blorp_emit_surface_state(brw, this, src,
+ I915_GEM_DOMAIN_SAMPLER, 0);
+
+ wm_bind_bo_offset =
+ gen6_blorp_emit_binding_table(brw,
+wm_surf_offset_renderbuffer,
+wm_surf_offset_texture);
+}
+
+void
brw_blorp_blit_params::gen6_emit_wm_config(struct brw_context *brw) const
{
gen6_blorp_emit_constant_ps(brw, this, wm_push_const_offset);
gen6_blorp_emit_wm_config(brw, this, prog_offset, prog_data);
+ gen6_blorp_emit_binding_table_pointers(brw, wm_bind_bo_offset);
}
void
@@ -1061,7 +1089,6 @@ gen6_blorp_exec(struct brw_context *brw,
uint32_t cc_blend_state_offset = 0;
uint32_t cc_state_offset = 0;
uint32_t depthstencil_offset;
- uint32_t wm_bind_bo_offset = 0;
/* Emit workaround flushes when we switch from drawing to blorping. */
intel_emit_post_sync_nonzero_flush(brw);
@@ -1081,32 +1108,13 @@ gen6_blorp_exec(struct brw_context *brw,
gen6_blorp_emit_cc_state_pointers(brw, params, cc_blend_state_offset,
depthstencil_offset, cc_state_offset);
params-gen6_emit_wm_constants(brw);
- if (params-use_wm_prog) {
- uint32_t wm_surf_offset_renderbuffer;
- uint32_t wm_surf_offset_texture = 0;
- intel_miptree_used_for_rendering(params-dst.mt);
- wm_surf_offset_renderbuffer =
- gen6_blorp_emit_surface_state(brw, params, params-dst,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
- if (params-src.mt) {
- wm_surf_offset_texture =
-gen6_blorp_emit_surface_state(brw, params, params-src,
- I915_GEM_DOMAIN_SAMPLER, 0);
- }
- wm_bind_bo_offset =
- gen6_blorp_emit_binding_table(brw,
- wm_surf_offset_renderbuffer,
- wm_surf_offset_texture);
- }
+ params-gen6_emit_surface_states(brw);
params-gen6_emit_sampler_state(brw);
gen6_blorp_emit_vs_disable(brw, params);
gen6_blorp_emit_gs_disable(brw, params);
gen6_blorp_emit_clip_disable(brw);
gen6_blorp_emit_sf_config(brw, params);
params-gen6_emit_wm_config(brw);
- if (params-use_wm_prog)
- gen6_blorp_emit_binding_table_pointers(brw, wm_bind_bo_offset);
gen6_blorp_emit_viewport_state(brw, params);
if (params-depth.mt)
--
1.9.3
___
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[Mesa-dev] [PATCH 07/16] i965/blorp: Allow blend state to be set for multiple render targets
Original blorp writes only one buffer per shader invocation. Once
the launch mechanism is shared with glsl-based programs there will
be need for supporting multiple render targets.
Also drop the always constant color write disable settings.
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 10 --
src/mesa/drivers/dri/i965/brw_blorp.h| 5 +++--
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 22 +++---
3 files changed, 18 insertions(+), 19 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 0c0cd2b..8f82851 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -155,7 +155,8 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t
*tile_x,
}
-brw_blorp_params::brw_blorp_params(unsigned num_varyings)
+brw_blorp_params::brw_blorp_params(unsigned num_varyings,
+ unsigned num_draw_buffers)
: x0(0),
y0(0),
x1(0),
@@ -163,12 +164,9 @@ brw_blorp_params::brw_blorp_params(unsigned num_varyings)
depth_format(0),
hiz_op(GEN6_HIZ_OP_NONE),
use_wm_prog(false),
- num_varyings(num_varyings)
+ num_varyings(num_varyings),
+ num_draw_buffers(num_draw_buffers)
{
- color_write_disable[0] = false;
- color_write_disable[1] = false;
- color_write_disable[2] = false;
- color_write_disable[3] = false;
}
extern C {
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index a84b664..fe1c24a 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -211,7 +211,8 @@ struct brw_blorp_prog_data
class brw_blorp_params
{
public:
- explicit brw_blorp_params(unsigned num_varyings = 0);
+ brw_blorp_params(unsigned num_varyings = 0,
+unsigned num_draw_buffers = 1);
virtual uint32_t get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data) const = 0;
@@ -227,8 +228,8 @@ public:
enum gen6_hiz_op hiz_op;
bool use_wm_prog;
brw_blorp_wm_push_constants wm_push_consts;
- bool color_write_disable[4];
const unsigned num_varyings;
+ const unsigned num_draw_buffers;
};
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 2954750..2bec265 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -246,21 +246,21 @@ gen6_blorp_emit_blend_state(struct brw_context *brw,
{
uint32_t cc_blend_state_offset;
+ assume(params-num_draw_buffers);
+
+ const unsigned size = params-num_draw_buffers *
+ sizeof(struct gen6_blend_state);
struct gen6_blend_state *blend = (struct gen6_blend_state *)
- brw_state_batch(brw, AUB_TRACE_BLEND_STATE,
- sizeof(struct gen6_blend_state), 64,
+ brw_state_batch(brw, AUB_TRACE_BLEND_STATE, size, 64,
cc_blend_state_offset);
- memset(blend, 0, sizeof(*blend));
-
- blend-blend1.pre_blend_clamp_enable = 1;
- blend-blend1.post_blend_clamp_enable = 1;
- blend-blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT;
+ memset(blend, 0, size);
- blend-blend1.write_disable_r = params-color_write_disable[0];
- blend-blend1.write_disable_g = params-color_write_disable[1];
- blend-blend1.write_disable_b = params-color_write_disable[2];
- blend-blend1.write_disable_a = params-color_write_disable[3];
+ for (unsigned i = 0; i params-num_draw_buffers; ++i) {
+ blend[i].blend1.pre_blend_clamp_enable = 1;
+ blend[i].blend1.post_blend_clamp_enable = 1;
+ blend[i].blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT;
+ }
return cc_blend_state_offset;
}
--
1.9.3
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[Mesa-dev] [PATCH 12/16] i965/blorp: Move sampler setup for the parameter type to handle
Also move the gen = 7 specific logic into gen6_blorp.ccp, this
will help to avoid more duplication when corresponding logic for
glsl-based programs is added.
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.h| 9 +++---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 47 ++--
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 16 +--
3 files changed, 38 insertions(+), 34 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 0149197..7ea82c0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -220,6 +220,8 @@ public:
virtual void gen6_emit_wm_config(struct brw_context *brw) const;
virtual void gen7_emit_wm_config(struct brw_context *brw) const;
+ virtual void gen6_emit_sampler_state(struct brw_context *brw) const;
+
virtual void gen7_emit_ps_config(struct brw_context *brw) const;
uint32_t x0;
@@ -360,6 +362,8 @@ public:
virtual void gen6_emit_wm_config(struct brw_context *brw) const;
virtual void gen7_emit_wm_config(struct brw_context *brw) const;
+ virtual void gen6_emit_sampler_state(struct brw_context *brw) const;
+
virtual void gen7_emit_ps_config(struct brw_context *brw) const;
private:
@@ -425,11 +429,6 @@ void
gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
const brw_blorp_params *params);
-uint32_t
-gen6_blorp_emit_sampler_state(struct brw_context *brw,
- unsigned tex_filter, unsigned max_lod,
- bool use_unorm_coords);
-
/** \} */
#endif /* __cplusplus */
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index d42b7f3..d5f89bb 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -451,22 +451,15 @@ gen6_blorp_emit_binding_table(struct brw_context *brw,
/**
* SAMPLER_STATE. See brw_update_sampler_state().
*/
-uint32_t
+static uint32_t
gen6_blorp_emit_sampler_state(struct brw_context *brw,
- unsigned tex_filter, unsigned max_lod,
- bool use_unorm_coords)
+ unsigned address_rounding, unsigned tex_filter,
+ unsigned max_lod, bool use_unorm_coords)
{
uint32_t sampler_offset;
uint32_t *sampler_state = (uint32_t *)
brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE, 16, 32, sampler_offset);
- unsigned address_rounding = BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
- BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
- BRW_ADDRESS_ROUNDING_ENABLE_R_MIN |
- BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
- BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
- BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
-
/* XXX: I don't think that using firstLevel, lastLevel works,
* because we always setup the surface state as if firstLevel ==
* level zero. Probably have to subtract firstLevel from each of
@@ -502,6 +495,14 @@ static void
gen6_blorp_emit_sampler_state_pointers(struct brw_context *brw,
uint32_t sampler_offset)
{
+ if (brw-gen = 7) {
+ BEGIN_BATCH(2);
+ OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS 16 | (2 - 2));
+ OUT_BATCH(sampler_offset);
+ ADVANCE_BATCH();
+ return;
+ }
+
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS 16 |
VS_SAMPLER_STATE_CHANGE |
@@ -1011,6 +1012,11 @@ brw_blorp_params::gen6_emit_wm_config(struct brw_context
*brw) const
}
void
+brw_blorp_params::gen6_emit_sampler_state(struct brw_context *brw) const
+{
+}
+
+void
brw_blorp_blit_params::gen6_emit_wm_constants(struct brw_context *brw)
{
wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, this);
@@ -1023,6 +1029,22 @@ brw_blorp_blit_params::gen6_emit_wm_config(struct
brw_context *brw) const
gen6_blorp_emit_wm_config(brw, this, prog_offset, prog_data);
}
+void
+brw_blorp_blit_params::gen6_emit_sampler_state(struct brw_context *brw) const
+{
+ const unsigned address_rounding = BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
+ BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
+ BRW_ADDRESS_ROUNDING_ENABLE_R_MIN |
+ BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
+ BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
+ BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
+ const unsigned max_lod = 0;
+ const uint32_t sampler_offset =
+ gen6_blorp_emit_sampler_state(brw, address_rounding,
+BRW_MAPFILTER_LINEAR, max_lod, true);
+ gen6_blorp_emit_sampler_state_pointers(brw, sampler_offset);
+}
+
/**
*
[Mesa-dev] [PATCH 08/16] i965/blorp: Add support for layered rendering
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 6 --
src/mesa/drivers/dri/i965/brw_blorp.h| 4 +++-
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 2 +-
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 2 +-
4 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 8f82851..b404869 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -156,7 +156,8 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t
*tile_x,
brw_blorp_params::brw_blorp_params(unsigned num_varyings,
- unsigned num_draw_buffers)
+ unsigned num_draw_buffers,
+ unsigned num_layers)
: x0(0),
y0(0),
x1(0),
@@ -165,7 +166,8 @@ brw_blorp_params::brw_blorp_params(unsigned num_varyings,
hiz_op(GEN6_HIZ_OP_NONE),
use_wm_prog(false),
num_varyings(num_varyings),
- num_draw_buffers(num_draw_buffers)
+ num_draw_buffers(num_draw_buffers),
+ num_layers(num_layers)
{
}
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index fe1c24a..695414a 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -212,7 +212,8 @@ class brw_blorp_params
{
public:
brw_blorp_params(unsigned num_varyings = 0,
-unsigned num_draw_buffers = 1);
+unsigned num_draw_buffers = 1,
+unsigned num_layers = 1);
virtual uint32_t get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data) const = 0;
@@ -230,6 +231,7 @@ public:
brw_blorp_wm_push_constants wm_push_consts;
const unsigned num_varyings;
const unsigned num_draw_buffers;
+ const unsigned num_layers;
};
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 2bec265..4f4d752 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -992,7 +992,7 @@ gen6_blorp_emit_primitive(struct brw_context *brw,
GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL);
OUT_BATCH(3); /* vertex count per instance */
OUT_BATCH(0);
- OUT_BATCH(1); /* instance count */
+ OUT_BATCH(params-num_layers); /* instance count */
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 3065a4c..2bdc82b 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -753,7 +753,7 @@ gen7_blorp_emit_primitive(struct brw_context *brw,
_3DPRIM_RECTLIST);
OUT_BATCH(3); /* vertex count per instance */
OUT_BATCH(0);
- OUT_BATCH(1); /* instance count */
+ OUT_BATCH(params-num_layers); /* instance count */
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
--
1.9.3
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[Mesa-dev] [PATCH 02/16] i965/blorp: Refactor vertex buffer state setup
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 60 ++--
1 file changed, 34 insertions(+), 26 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index e45705a..6c139ec 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -93,6 +93,37 @@ gen6_blorp_emit_state_base_address(struct brw_context *brw,
ADVANCE_BATCH();
}
+static void
+gen6_blorp_emit_vertex_buffer_state(struct brw_context *brw,
+unsigned num_elems,
+unsigned vbo_size,
+uint32_t vertex_offset)
+{
+ /* 3DSTATE_VERTEX_BUFFERS */
+ const int num_buffers = 1;
+ const int batch_length = 1 + 4 * num_buffers;
+
+ uint32_t dw0 = GEN6_VB0_ACCESS_VERTEXDATA |
+ (num_elems * sizeof(float)) BRW_VB0_PITCH_SHIFT;
+
+ if (brw-gen = 7)
+ dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
+
+ if (brw-gen == 7)
+ dw0 |= GEN7_MOCS_L3 16;
+
+ BEGIN_BATCH(batch_length);
+ OUT_BATCH((_3DSTATE_VERTEX_BUFFERS 16) | (batch_length - 2));
+ OUT_BATCH(dw0);
+ /* start address */
+ OUT_RELOC(brw-batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
+ vertex_offset);
+ /* end address */
+ OUT_RELOC(brw-batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
+ vertex_offset + vbo_size - 1);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+}
void
gen6_blorp_emit_vertices(struct brw_context *brw,
@@ -144,32 +175,9 @@ gen6_blorp_emit_vertices(struct brw_context *brw,
memcpy(vertex_data, vertices, GEN6_BLORP_VBO_SIZE);
}
- /* 3DSTATE_VERTEX_BUFFERS */
- {
- const int num_buffers = 1;
- const int batch_length = 1 + 4 * num_buffers;
-
- uint32_t dw0 = GEN6_VB0_ACCESS_VERTEXDATA |
- (GEN6_BLORP_NUM_VUE_ELEMS * sizeof(float))
BRW_VB0_PITCH_SHIFT;
-
- if (brw-gen = 7)
- dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
-
- if (brw-gen == 7)
- dw0 |= GEN7_MOCS_L3 16;
-
- BEGIN_BATCH(batch_length);
- OUT_BATCH((_3DSTATE_VERTEX_BUFFERS 16) | (batch_length - 2));
- OUT_BATCH(dw0);
- /* start address */
- OUT_RELOC(brw-batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
- vertex_offset);
- /* end address */
- OUT_RELOC(brw-batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
- vertex_offset + GEN6_BLORP_VBO_SIZE - 1);
- OUT_BATCH(0);
- ADVANCE_BATCH();
- }
+ gen6_blorp_emit_vertex_buffer_state(brw, GEN6_BLORP_NUM_VUE_ELEMS,
+ GEN6_BLORP_VBO_SIZE,
+ vertex_offset);
/* 3DSTATE_VERTEX_ELEMENTS
*
--
1.9.3
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[Mesa-dev] [PATCH 11/14] i965/blorp/gen7: Prepare re-using for gen8
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 7ee62f7..d41d592 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -50,7 +50,9 @@
static void
gen7_blorp_emit_urb_config(struct brw_context *brw)
{
- unsigned urb_size = (brw-is_haswell brw-gt == 3) ? 32 : 16;
+ const unsigned urb_size =
+ (brw-gen = 8 || (brw-is_haswell brw-gt == 3)) ? 32 : 16;
+
gen7_emit_push_constant_state(brw,
urb_size / 2 /* vs_size */,
0 /* gs_size */,
@@ -346,7 +348,7 @@ gen7_blorp_emit_gs_disable(struct brw_context *brw)
* whole fixed function pipeline means to emit a PIPE_CONTROL with the CS
* Stall bit set.
*/
- if (!brw-is_haswell brw-gt == 2 brw-gs.enabled)
+ if (brw-gen 8 !brw-is_haswell brw-gt == 2 brw-gs.enabled)
gen7_emit_cs_stall_flush(brw);
BEGIN_BATCH(7);
--
1.9.3
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[Mesa-dev] [PATCH 01/14] i965/blorp/gen7: Support for loading glsl-based fragment shaders
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 15 +
src/mesa/drivers/dri/i965/brw_blorp.h| 41
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 22 +
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 54
4 files changed, 132 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 680db75..bd080b0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -335,3 +335,18 @@ brw_hiz_op_params::brw_hiz_op_params(struct
intel_mipmap_tree *mt,
default:unreachable(not reached);
}
}
+
+/**
+ * Set relevant fields such as normal gl-state based program loading would.
+ */
+struct brw_stage_state
+brw_meta_fs_params::create_stage_state(const struct gl_fragment_program *fp,
+ uint32_t wm_prog_offset)
+{
+ struct brw_stage_state res;
+ res.stage = MESA_SHADER_FRAGMENT;
+ res.scratch_bo = NULL;
+ res.sampler_count = _mesa_fls(fp-Base.SamplersUsed);
+ res.prog_offset = wm_prog_offset;
+ return res;
+}
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 2abe654..aa83c66 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -388,6 +388,47 @@ private:
uint32_t sampler_offset;
};
+class brw_meta_fs_params : public brw_blorp_params
+{
+public:
+ brw_meta_fs_params(unsigned dst_num_samples,
+ unsigned num_draw_buffers, unsigned num_layers,
+ const struct gl_fragment_program *fp,
+ uint32_t wm_prog_offset,
+ const struct brw_wm_prog_data *wm_prog_data,
+ unsigned fast_clear_op)
+ : brw_blorp_params(wm_prog_data-num_varying_inputs,
+ num_draw_buffers, num_layers),
+dst_num_samples(dst_num_samples), fp(fp), wm_prog_data(wm_prog_data),
+wm_prog_offset(wm_prog_offset), fast_clear_op(fast_clear_op),
+wm_stage_state(create_stage_state(fp, wm_prog_offset))
+ {
+ }
+
+ virtual void gen6_emit_wm_constants(struct brw_context *brw);
+
+ virtual void gen7_emit_wm_config(struct brw_context *brw) const;
+
+ virtual void gen6_emit_multisample_state(struct brw_context *brw) const;
+
+ virtual void gen7_emit_ps_config(struct brw_context *brw) const;
+
+protected:
+ const unsigned dst_num_samples;
+ const struct gl_fragment_program * const fp;
+ const struct brw_wm_prog_data * const wm_prog_data;
+ const uint32_t wm_prog_offset;
+ const unsigned fast_clear_op;
+ struct brw_stage_state wm_stage_state;
+ uint32_t wm_bind_bo_offset;
+ uint32_t sampler_offset;
+
+private:
+ static struct brw_stage_state create_stage_state(
+const struct gl_fragment_program *fp,
+uint32_t wm_prog_offset);
+};
+
/**
* \name BLORP internals
* \{
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 77de474..39d32df 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -1081,6 +1081,28 @@ brw_blorp_blit_params::gen6_emit_sampler_state(struct
brw_context *brw) const
gen6_blorp_emit_sampler_state_pointers(brw, sampler_offset);
}
+void
+brw_meta_fs_params::gen6_emit_wm_constants(struct brw_context *brw)
+{
+ gen6_upload_push_constants(brw, fp-Base, wm_prog_data-base,
+ wm_stage_state, AUB_TRACE_WM_CONSTANTS);
+
+ if (brw-gen = 7) {
+ gen7_upload_constant_state(brw, wm_stage_state, true,
+ _3DSTATE_CONSTANT_PS);
+ }
+}
+
+void
+brw_meta_fs_params::gen6_emit_multisample_state(struct brw_context *brw) const
+{
+ const unsigned sample_mask =
+ dst_num_samples 1 ? (1 dst_num_samples) - 1 : 1;
+
+ gen6_emit_3dstate_multisample(brw, dst_num_samples);
+ gen6_emit_3dstate_sample_mask(brw, sample_mask);
+}
+
/**
* \brief Execute a blit or render pass operation.
*
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index f430fa0..f52937b 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -478,6 +478,39 @@ gen7_blorp_emit_wm_config(struct brw_context *brw,
ADVANCE_BATCH();
}
+static void
+gen7_blorp_upload_wm_state(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_wm_prog_data *prog_data,
+ bool multisampled_fbo)
+{
+ uint32_t dw1, dw2;
+
+ dw1 = dw2 = 0;
+ dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
+ dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
+
+ dw1 |= prog_data-computed_depth_mode
[Mesa-dev] [PATCH 06/14] i965/blorp: Add support for loading vertices for glsl-based blits
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.h| 5 ++
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 94
2 files changed, 99 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 253d6e6..92db991 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -415,6 +415,9 @@ public:
virtual void gen7_emit_ps_config(struct brw_context *brw) const;
protected:
+ static void gen6_emit_vertex_elems(struct brw_context *brw,
+ bool with_tex_coords);
+
const unsigned dst_num_samples;
const struct gl_fragment_program * const fp;
const struct brw_wm_prog_data * const wm_prog_data;
@@ -449,6 +452,8 @@ public:
GLenum filter, GLenum target,
bool mirror_x, bool mirror_y);
+ virtual void gen6_emit_vertices(struct brw_context *brw) const;
+
private:
const float src_x0, src_y0, src_x1, src_y1;
const struct gl_framebuffer * const read_fb;
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 7ba414e..5a4c301 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -1177,6 +1177,100 @@ brw_meta_fs_params::gen6_emit_multisample_state(struct
brw_context *brw) const
gen6_emit_3dstate_sample_mask(brw, sample_mask);
}
+void
+brw_meta_fs_params::gen6_emit_vertex_elems(struct brw_context *brw,
+ bool with_tex_coords)
+{
+ /* 3DSTATE_VERTEX_ELEMENTS
+*
+* These are instructions for VF (vertex fetcher) how the URB is to be
+* filled with vertex data.
+*
+* First element is the vertex header. Second component designates the
+* layer and gets assigned to the primitive instance identifier. All
+* other three components are zero and we can tell the VF to fill them
+* with constants instead of supplying data from the buffer.
+* Second element contains the vertex coordinates (x,y,w,z). We tell the
+* VF to load X and Y from the vertex buffer and to use constant values
+* of zero and one for the Z and W coordinates respectively.
+* Finally the third element contains the texture coordinates. Similarly
+* to the vertex coordinates, X and Y are supplied in the vertex buffer
+* while Z and W are constants.
+*/
+ const int num_elements = with_tex_coords ? 3 : 2;
+ const int batch_length = 1 + 2 * num_elements;
+
+ BEGIN_BATCH(batch_length);
+ OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS 16) | (batch_length - 2));
+ /* Element 0 */
+ OUT_BATCH(GEN6_VE0_VALID |
+ BRW_SURFACEFORMAT_R32G32B32A32_FLOAT BRW_VE0_FORMAT_SHIFT |
+ 0 BRW_VE0_SRC_OFFSET_SHIFT);
+ OUT_BATCH(BRW_VE1_COMPONENT_STORE_0 BRW_VE1_COMPONENT_0_SHIFT |
+ BRW_VE1_COMPONENT_STORE_IID BRW_VE1_COMPONENT_1_SHIFT |
+ BRW_VE1_COMPONENT_STORE_0 BRW_VE1_COMPONENT_2_SHIFT |
+ BRW_VE1_COMPONENT_STORE_0 BRW_VE1_COMPONENT_3_SHIFT);
+ /* Element 1 */
+ OUT_BATCH(GEN6_VE0_VALID |
+ BRW_SURFACEFORMAT_R32G32_FLOAT BRW_VE0_FORMAT_SHIFT |
+ 0 BRW_VE0_SRC_OFFSET_SHIFT);
+ OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC BRW_VE1_COMPONENT_0_SHIFT |
+ BRW_VE1_COMPONENT_STORE_SRC BRW_VE1_COMPONENT_1_SHIFT |
+ BRW_VE1_COMPONENT_STORE_0 BRW_VE1_COMPONENT_2_SHIFT |
+ BRW_VE1_COMPONENT_STORE_1_FLT BRW_VE1_COMPONENT_3_SHIFT);
+ /* Element 2 */
+ if (with_tex_coords) {
+ OUT_BATCH(GEN6_VE0_VALID |
+BRW_SURFACEFORMAT_R32G32B32_FLOAT BRW_VE0_FORMAT_SHIFT |
+8 BRW_VE0_SRC_OFFSET_SHIFT);
+ OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC BRW_VE1_COMPONENT_0_SHIFT |
+BRW_VE1_COMPONENT_STORE_SRC BRW_VE1_COMPONENT_1_SHIFT |
+BRW_VE1_COMPONENT_STORE_SRC BRW_VE1_COMPONENT_2_SHIFT |
+BRW_VE1_COMPONENT_STORE_1_FLT BRW_VE1_COMPONENT_3_SHIFT);
+ }
+ ADVANCE_BATCH();
+}
+
+void
+brw_meta_blit_params::gen6_emit_vertices(struct brw_context *brw) const
+{
+ uint32_t vertex_offset;
+ const bool use_unorm_tex_coords = target == GL_TEXTURE_RECTANGLE;
+ const float s0 = src_x0 / (use_unorm_tex_coords ? 1 : src.width);
+ const float s1 = src_x1 / (use_unorm_tex_coords ? 1 : src.width);
+ const float t0 = src_y0 / (use_unorm_tex_coords ? 1 : src.height);
+ const float t1 = src_y1 / (use_unorm_tex_coords ? 1 : src.height);
+
+ /* Minimum layer setting works for all the textures types but texture_3d
+* for which the setting has no effect. Use the z-coordinate instead.
+* Note also that in texture_3d case hardware wants the depth coordinate
+* as normalized.
+*/
+ const float z_normalizer = MAX2(((float)src.mt-logical_depth0) - 1, 1);
+ const float z = target == GL_TEXTURE_3D
[Mesa-dev] [PATCH 08/14] i965/blorp: Add support for setting samplers for glsl-based blits
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.h| 2 ++
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 30 ++
2 files changed, 32 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index c0f416a..12b4133 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -457,6 +457,8 @@ public:
virtual void gen6_emit_surface_states(struct brw_context *brw);
virtual void gen7_emit_surface_states(struct brw_context *brw);
+ virtual void gen6_emit_sampler_state(struct brw_context *brw) const;
+
private:
const float src_x0, src_y0, src_x1, src_y1;
const struct gl_framebuffer * const read_fb;
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index c0e3a06..f45dcd4 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -1301,6 +1301,36 @@ brw_meta_blit_params::gen6_emit_surface_states(struct
brw_context *brw)
wm_stage_state);
}
+void
+brw_meta_blit_params::gen6_emit_sampler_state(struct brw_context *brw) const
+{
+ const float min_lod = -1000.0f;
+ const float max_lod = 1000.0f;
+ const float lod_bias = 0.0f;
+ const float max_anisotropy = 1.0f;
+ const struct gl_sampler_object sampler =
+ { 0, 0, 0, GL_CLAMP_TO_EDGE, GL_CLAMP_TO_EDGE, GL_CLAMP_TO_EDGE,
+filter, filter, { 0.0, 0.0, 0.0, 0.0 }, min_lod, max_lod, lod_bias,
+max_anisotropy, GL_NONE, GL_LEQUAL, GL_DECODE_EXT, GL_FALSE };
+
+ uint32_t sampler_offset;
+ uint32_t *sampler_state = (uint32_t *)
+ brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE, 16, 32, sampler_offset);
+
+ const struct gl_renderbuffer *irb = read_fb-_ColorReadBuffer;
+ const bool tex_cube_map_seamless = false;
+ const float tex_unit_lod_bias = 0.0f;
+ const bool is_integer_format = false;
+ brw_update_sampler_state(brw,
+target, tex_cube_map_seamless,
+tex_unit_lod_bias,
+irb-Format, irb-_BaseFormat,
+is_integer_format,
+sampler,
+sampler_state, sampler_offset);
+ gen6_blorp_emit_sampler_state_pointers(brw, sampler_offset);
+}
+
/**
* \brief Execute a blit or render pass operation.
*
--
1.9.3
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[Mesa-dev] [PATCH 04/14] i965/meta: Add helper for looking up blit programs
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_meta_util.c | 148 ++
src/mesa/drivers/dri/i965/brw_meta_util.h | 9 ++
2 files changed, 157 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c
b/src/mesa/drivers/dri/i965/brw_meta_util.c
index a3b0604..0ff9445 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -21,8 +21,13 @@
* IN THE SOFTWARE.
*/
+#include brw_context.h
+#include brw_wm.h
+#include brw_state.h
#include brw_meta_util.h
#include main/fbobject.h
+#include main/shaderobj.h
+#include drivers/common/meta.h
/**
* Helper function for handling mirror image blits.
@@ -157,3 +162,146 @@ brw_meta_mirror_clip_and_scissor(const struct gl_context
*ctx,
return false;
}
+
+/**
+ * Meta shaders used for 2D blits and clears use pass-thru vertex shaders
+ * which just pass the vertices unmodified to clipping. This is exploit in
+ * the pipeline setup by disabling the vertex shader stage and passing the
+ * vertices directly to clip unit. Hence we only need to store the details
+ * for the fragment program.
+ */
+static bool
+meta_recompile(struct brw_context *brw,
+ struct brw_wm_prog_key *key,
+ struct gl_shader_program *sh_prog,
+ uint32_t *wm_prog_offset,
+ const struct brw_wm_prog_data **wm_prog_data)
+{
+ if (brw_search_cache(brw-cache, BRW_CACHE_FS_PROG, key, sizeof(*key),
+wm_prog_offset, wm_prog_data))
+ return true;
+
+ struct gl_shader *sh = sh_prog-_LinkedShaders[MESA_SHADER_FRAGMENT];
+ struct gl_fragment_program *fp = (struct gl_fragment_program *)sh-Program;
+
+ /* In case a program is already compiled but not available in the cache it
+* means there isn't yet a version that writes the same number of
+* renderbuffers as will be needed next. Hence compile another flavour.
+*/
+ uint32_t old_prog_offset = brw-wm.base.prog_offset;
+ struct brw_wm_prog_data *old_prog_data = brw-wm.prog_data;
+ bool status = brw_compile_wm_prog(brw, sh_prog, brw_fragment_program(fp),
+ key);
+ *wm_prog_offset = brw-wm.base.prog_offset;
+ *wm_prog_data = brw-wm.prog_data;
+ brw-wm.base.prog_offset = old_prog_offset;
+ brw-wm.prog_data = old_prog_data;
+
+ return status;
+}
+
+static struct gl_shader_program *
+get_blit_shader(struct brw_context *brw, GLenum target, bool do_depth)
+{
+ struct gl_context *ctx = brw-ctx;
+ struct blit_state *blit = ctx-Meta-Blit;
+ struct blit_shader_table *tbl = do_depth ? blit-shaders_with_depth :
+ blit-shaders_without_depth;
+ const struct blit_shader *sh = _mesa_meta_choose_blit_shader(target, tbl);
+
+ /* Reset the core context state to the default except the current fbo
+* settings and compile the blit program of the desired type. After the
+* compilation restore the core context to the state it was before.
+*/
+ if (!sh-shader_prog) {
+ _mesa_meta_begin(ctx, MESA_META_ALL ~MESA_META_DRAW_BUFFERS);
+ sh = _mesa_meta_setup_blit_shader(ctx, target, do_depth, tbl);
+ _mesa_meta_end(ctx);
+ }
+
+ return _mesa_lookup_shader_program_err(ctx, sh-shader_prog, __FUNCTION__);
+}
+
+/* Mimick the algorithm used in core meta to deduce the texture target. */
+static GLenum
+resolve_target(const struct gl_context *ctx, bool do_depth)
+{
+ const struct gl_framebuffer *read_fb = ctx-ReadBuffer;
+ int att_index = do_depth ? BUFFER_DEPTH : read_fb-_ColorReadBufferIndex;
+ const struct gl_renderbuffer_attachment *read_att =
+ read_fb-Attachment[att_index];
+
+ if (read_att-Texture) {
+ /* The six faces of a cube are laid out in the memory identically
+ * to a 2D texture array of the same size (having depth six). Hence
+ * the blit can be performed using the simpler 2D array program.
+ */
+ if (read_att-Texture-Target == GL_TEXTURE_CUBE_MAP ||
+ read_att-Texture-Target == GL_TEXTURE_CUBE_MAP_ARRAY)
+ return GL_TEXTURE_2D_ARRAY;
+
+ return read_att-Texture-Target;
+ }
+
+ if (read_att-Renderbuffer-NumSamples 1)
+ return GL_TEXTURE_2D_MULTISAMPLE;
+
+ return GL_TEXTURE_2D;
+}
+
+static void
+get_current_blit_wm_prog_key(const struct gl_context *ctx,
+ const struct brw_fragment_program *fp,
+ struct brw_wm_prog_key *key)
+{
+ memset(key, 0, sizeof(*key));
+
+ key-nr_color_regions = ctx-DrawBuffer-_NumColorDrawBuffers;
+ key-program_string_id = fp-id;
+
+ /* Every blit program has one and only one texture tobe sampled. And
+* none of the blit runs use settings that would require special flavour
+* of the program. All the texture key settings are fixed to default.
+*/
+ key-tex.swizzles[0] = SWIZZLE_NOOP;
+}
+
+bool
[Mesa-dev] [PATCH 05/14] i965/blorp: Add plumbing for glsl-based color blits
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.h| 27 +
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 90
2 files changed, 117 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 9fd4193..253d6e6 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -430,6 +430,33 @@ private:
uint32_t wm_prog_offset);
};
+class brw_meta_blit_params : public brw_meta_fs_params
+{
+public:
+ brw_meta_blit_params(struct brw_context *brw,
+const struct gl_fragment_program *fp,
+uint32_t wm_prog_offset,
+const struct brw_wm_prog_data *wm_prog_data,
+const struct gl_framebuffer *read_fb,
+const struct gl_framebuffer *draw_fb,
+struct intel_mipmap_tree *src_mt,
+unsigned src_level, unsigned src_layer,
+mesa_format src_format,
+float src_x0, float src_y0,
+float src_x1, float src_y1,
+float dst_x0, float dst_y0,
+float dst_x1, float dst_y1,
+GLenum filter, GLenum target,
+bool mirror_x, bool mirror_y);
+
+private:
+ const float src_x0, src_y0, src_x1, src_y1;
+ const struct gl_framebuffer * const read_fb;
+ const struct gl_framebuffer * const draw_fb;
+ const GLenum filter;
+ const GLenum target;
+};
+
/**
* \name BLORP internals
* \{
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 947f3b0..17b884f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -345,6 +345,63 @@ brw_blorp_framebuffer(struct brw_context *brw,
return mask;
}
+bool
+brw_meta_fbo_color_blit(struct brw_context *brw,
+struct gl_framebuffer *read_fb,
+struct gl_framebuffer *draw_fb,
+float src_x0, float src_y0,
+float src_x1, float src_y1,
+float dst_x0, float dst_y0,
+float dst_x1, float dst_y1,
+GLenum filter)
+{
+ /* Sync up the state of window system buffers. We need to do this before
+* we go looking for the buffers.
+*/
+ intel_prepare_render(brw);
+
+ bool mirror_x, mirror_y;
+ if (brw_meta_mirror_clip_and_scissor(brw-ctx, read_fb, draw_fb,
+src_x0, src_y0, src_x1, src_y1,
+dst_x0, dst_y0, dst_x1, dst_y1,
+mirror_x, mirror_y))
+ return true;
+
+ GLenum target;
+ const struct gl_fragment_program *fp;
+ uint32_t wm_prog_offset;
+ const struct brw_wm_prog_data *wm_prog_data;
+
+ if (!brw_meta_choose_blit_shader(brw, GL_COLOR_BUFFER_BIT, filter, target,
+fp, wm_prog_offset, wm_prog_data))
+ return false;
+
+ struct intel_renderbuffer *src_irb =
+ intel_renderbuffer(read_fb-_ColorReadBuffer);
+ struct intel_mipmap_tree *src_mt =
+ find_miptree(GL_COLOR_BUFFER_BIT, src_irb);
+
+ intel_miptree_resolve_color(brw, src_mt);
+ brw_meta_blit_params params(brw, fp, wm_prog_offset, wm_prog_data,
+ read_fb, draw_fb, src_mt,
+ src_irb-mt_level, src_irb-mt_layer,
+ src_irb-Base.Base.Format,
+ src_x0, src_y0,
+ src_x1, src_y1,
+ dst_x0, dst_y0,
+ dst_x1, dst_y1,
+ filter, target, mirror_x, mirror_y);
+
+ /* Manually store and disable current srgb setting. */
+ bool srgb_save = brw-ctx.Color.sRGBEnabled;
+ brw-ctx.Color.sRGBEnabled = false;
+
+ brw_blorp_exec(brw, params);
+
+ brw-ctx.Color.sRGBEnabled = srgb_save;
+
+ return true;
+}
/**
* Enum to specify the order of arguments in a sampler message
@@ -2136,3 +2193,36 @@ brw_blorp_blit_params::set_wm_prog(struct brw_context
*brw)
prog_offset, prog_data);
}
}
+
+brw_meta_blit_params::brw_meta_blit_params(
+ struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ uint32_t wm_prog_offset,
+ const struct brw_wm_prog_data *wm_prog_data,
+ const struct gl_framebuffer *read_fb,
+ const struct gl_framebuffer *draw_fb,
+ struct intel_mipmap_tree *src_mt,
+ unsigned
[Mesa-dev] i965: Don't use gl-context for fbo-blits
This series introduces new blorp parameter type for blit programs compiled from glsl-sources. For most parts the launch logic just calls core i965 batch emission logic. Vertex batches are handcrafted containing full vertex header information. This is needed because the pipeline is programmed to skip vertex shader, clip and viewport transformation in stripsfans (SF) but to provide the vertices directly from vertex fetcher (VF) to the windower (WM). Topi Pohjolainen (14): i965/blorp/gen7: Support for loading glsl-based fragment shaders i965/blorp/gen6: Support for loading glsl-based fragment shaders meta: Provide read access to blit shaders i965/meta: Add helper for looking up blit programs i965/blorp: Add plumbing for glsl-based color blits i965/blorp: Add support for loading vertices for glsl-based blits i965/blorp: Add support for setting up surfaces for glsl-based blits i965/blorp: Add support for setting samplers for glsl-based blits i965/gen6: Add support for setting minimum layer for tex surfaces i965/blorp: Enable glsl-based fbo blits i965/blorp/gen7: Prepare re-using for gen8 i965/blorp/gen7: Expose state setup applicable to gen8 i965/blorp/gen6: Prepare vertex buffer setup logic for gen8 i965/blorp/gen8: Execution support src/mesa/drivers/common/meta.c | 17 +- src/mesa/drivers/common/meta.h | 5 +- src/mesa/drivers/dri/i965/Makefile.sources | 1 + src/mesa/drivers/dri/i965/brw_blorp.cpp | 21 +- src/mesa/drivers/dri/i965/brw_blorp.h| 127 ++ src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 90 + src/mesa/drivers/dri/i965/brw_context.h | 10 + src/mesa/drivers/dri/i965/brw_meta_util.c| 148 +++ src/mesa/drivers/dri/i965/brw_meta_util.h| 9 + src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 +- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 280 - src/mesa/drivers/dri/i965/gen7_blorp.cpp | 87 +++- src/mesa/drivers/dri/i965/gen8_blorp.cpp | 494 +++ src/mesa/drivers/dri/i965/intel_fbo.c| 11 + 14 files changed, 1273 insertions(+), 32 deletions(-) create mode 100644 src/mesa/drivers/dri/i965/gen8_blorp.cpp -- 1.9.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 12/14] i965/blorp/gen7: Expose state setup applicable to gen8
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.h| 36
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 20 +-
2 files changed, 46 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 12b4133..750ec5f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -516,6 +516,42 @@ void
gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
const brw_blorp_params *params);
+void
+gen7_blorp_emit_urb_config(struct brw_context *brw);
+
+void
+gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
+uint32_t cc_blend_state_offset);
+
+void
+gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
+ uint32_t cc_state_offset);
+
+void
+gen7_blorp_emit_cc_viewport(struct brw_context *brw);
+
+void
+gen7_blorp_emit_te_disable(struct brw_context *brw);
+
+void
+gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
+ uint32_t wm_bind_bo_offset);
+
+void
+gen7_blorp_emit_clear_params(struct brw_context *brw,
+ const brw_blorp_params *params);
+
+void
+gen7_blorp_emit_constant_ps(struct brw_context *brw,
+uint32_t wm_push_const_offset);
+
+void
+gen7_blorp_emit_constant_ps_disable(struct brw_context *brw);
+
+void
+gen7_blorp_emit_primitive(struct brw_context *brw,
+ const brw_blorp_params *params);
+
/** \} */
#endif /* __cplusplus */
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index d41d592..472e12a 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -47,7 +47,7 @@
* programmed in order for the programming of this state to be
* valid.
*/
-static void
+void
gen7_blorp_emit_urb_config(struct brw_context *brw)
{
const unsigned urb_size =
@@ -72,7 +72,7 @@ gen7_blorp_emit_urb_config(struct brw_context *brw)
/* 3DSTATE_BLEND_STATE_POINTERS */
-static void
+void
gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
uint32_t cc_blend_state_offset)
{
@@ -84,7 +84,7 @@ gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
/* 3DSTATE_CC_STATE_POINTERS */
-static void
+void
gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
uint32_t cc_state_offset)
{
@@ -94,7 +94,7 @@ gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
ADVANCE_BATCH();
}
-static void
+void
gen7_blorp_emit_cc_viewport(struct brw_context *brw)
{
struct brw_cc_viewport *ccv;
@@ -280,7 +280,7 @@ gen7_blorp_emit_hs_disable(struct brw_context *brw)
*
* Disable the tesselation engine.
*/
-static void
+void
gen7_blorp_emit_te_disable(struct brw_context *brw)
{
BEGIN_BATCH(4);
@@ -567,7 +567,7 @@ gen7_blorp_emit_ps_config(struct brw_context *brw,
}
-static void
+void
gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
uint32_t wm_bind_bo_offset)
{
@@ -578,7 +578,7 @@ gen7_blorp_emit_binding_table_pointers_ps(struct
brw_context *brw,
}
-static void
+void
gen7_blorp_emit_constant_ps(struct brw_context *brw,
uint32_t wm_push_const_offset)
{
@@ -605,7 +605,7 @@ gen7_blorp_emit_constant_ps(struct brw_context *brw,
ADVANCE_BATCH();
}
-static void
+void
gen7_blorp_emit_constant_ps_disable(struct brw_context *brw)
{
BEGIN_BATCH(7);
@@ -754,7 +754,7 @@ gen7_blorp_emit_depth_disable(struct brw_context *brw)
*with the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
*3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
*/
-static void
+void
gen7_blorp_emit_clear_params(struct brw_context *brw,
const brw_blorp_params *params)
{
@@ -767,7 +767,7 @@ gen7_blorp_emit_clear_params(struct brw_context *brw,
/* 3DPRIMITIVE */
-static void
+void
gen7_blorp_emit_primitive(struct brw_context *brw,
const brw_blorp_params *params)
{
--
1.9.3
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 07/14] i965/blorp: Add support for setting up surfaces for glsl-based blits
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.h| 3 +++
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 30 ++
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 7 +++
3 files changed, 40 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 92db991..c0f416a 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -454,6 +454,9 @@ public:
virtual void gen6_emit_vertices(struct brw_context *brw) const;
+ virtual void gen6_emit_surface_states(struct brw_context *brw);
+ virtual void gen7_emit_surface_states(struct brw_context *brw);
+
private:
const float src_x0, src_y0, src_x1, src_y1;
const struct gl_framebuffer * const read_fb;
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 5a4c301..c0e3a06 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -1271,6 +1271,36 @@ brw_meta_blit_params::gen6_emit_vertices(struct
brw_context *brw) const
gen6_emit_vertex_elems(brw, true);
}
+void
+brw_meta_blit_params::gen6_emit_surface_states(struct brw_context *brw)
+{
+ brw_update_renderbuffer_surfaces(
+ brw, draw_fb,
+ wm_prog_data-binding_table.render_target_start,
+ wm_stage_state.surf_offset);
+
+ const uint32_t tex_surf_index =
+ wm_prog_data-base.binding_table.texture_start;
+ uint32_t *surf_offset = wm_stage_state.surf_offset[tex_surf_index];
+
+ /* For texture_3d the layer gets selected using z-sampler coordinate. */
+ const unsigned min_layer = target != GL_TEXTURE_3D ? src.layer : 0;
+ const bool for_gather = false;
+ const bool is_integer_format = false;
+ const unsigned mip_count = 0;
+
+ brw-vtbl.update_texture_surface(brw, src.mt, src.brw_surfaceformat,
+is_integer_format, target,
+src.mt-logical_depth0, min_layer,
+src.level, mip_count, SWIZZLE_XYZW,
+surf_offset, for_gather);
+
+ const GLbitfield dirty_flags = 0;
+ brw_upload_binding_table(brw, _3DSTATE_BINDING_TABLE_POINTERS_PS,
+dirty_flags, wm_prog_data-base,
+wm_stage_state);
+}
+
/**
* \brief Execute a blit or render pass operation.
*
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index f52937b..7ee62f7 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -858,6 +858,13 @@ brw_meta_fs_params::gen7_emit_ps_config(struct brw_context
*brw) const
fast_clear_op);
}
+void
+brw_meta_blit_params::gen7_emit_surface_states(struct brw_context *brw)
+{
+ /* Implementation for gen6 already uses gen-aware jump table. */
+ gen6_emit_surface_states(brw);
+}
+
/**
* \copydoc gen6_blorp_exec()
*/
--
1.9.3
___
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mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 14/14] i965/blorp/gen8: Execution support
Batch emission logic for launching glsl-based programs without
reading/writing the current gl-context.
Initially I wrote support also for launching the handwritten
assembly programs but I took it out. It is very unlikely that we
ever want to use them for gen = 8. The whole idea of this series
is to allow even gen 8 to use the glsl-based programs instead.
I have the (untested) support in my local trees though.
I thought about exposing the i965 core support for disabling HS,
DS, etc. stages and re-using it here. I decided against in the end
as the core is likely to enable some of them in the future. If we
like to do this instead I can do it as follow-up, similar thing
applies to gen7 also.
Finally, it should be noted that the patch does not introduce
gen8_emit_surface_states(). Instead gen8_blorp_exec() calls
gen6_emit_surface_states() which is already implemented for
glsl-based programs using the gen-aware jump tables that the core
i965 batch submission mechanism provides.
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
src/mesa/drivers/dri/i965/brw_blorp.cpp| 6 +-
src/mesa/drivers/dri/i965/brw_blorp.h | 12 +
src/mesa/drivers/dri/i965/gen8_blorp.cpp | 494 +
4 files changed, 512 insertions(+), 1 deletion(-)
create mode 100644 src/mesa/drivers/dri/i965/gen8_blorp.cpp
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
b/src/mesa/drivers/dri/i965/Makefile.sources
index 6d4659f..62d6860 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -164,6 +164,7 @@ i965_FILES = \
gen7_wm_state.c \
gen7_wm_surface_state.c \
gen8_blend_state.c \
+ gen8_blorp.cpp \
gen8_depth_state.c \
gen8_disable.c \
gen8_draw_upload.c \
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index bd080b0..eb1a950 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -210,7 +210,7 @@ void
brw_blorp_exec(struct brw_context *brw, brw_blorp_params *params)
{
struct gl_context *ctx = brw-ctx;
- uint32_t estimated_max_batch_usage = 1500;
+ uint32_t estimated_max_batch_usage = brw-gen = 8 ? 2048 : 1500;
bool check_aperture_failed_once = false;
/* Flush the sampler and render caches. We definitely need to flush the
@@ -236,6 +236,10 @@ retry:
case 7:
gen7_blorp_exec(brw, params);
break;
+ case 8:
+ case 9:
+ gen8_blorp_exec(brw, params);
+ break;
default:
/* BLORP is not supported before Gen6. */
unreachable(not reached);
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 750ec5f..638d6e7 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -222,14 +222,18 @@ public:
virtual void gen6_emit_wm_config(struct brw_context *brw) const;
virtual void gen7_emit_wm_config(struct brw_context *brw) const;
+ virtual void gen8_emit_wm_config(struct brw_context *brw) const;
virtual void gen6_emit_sampler_state(struct brw_context *brw) const;
virtual void gen6_emit_multisample_state(struct brw_context *brw) const;
+ virtual void gen8_emit_multisample_state(struct brw_context *brw) const;
virtual void gen7_emit_ps_config(struct brw_context *brw) const;
+ virtual void gen8_emit_ps_config(struct brw_context *brw) const;
virtual void gen6_emit_vertices(struct brw_context *brw) const;
+ virtual void gen8_emit_vertices_extra(struct brw_context *brw) const;
uint32_t x0;
uint32_t y0;
@@ -251,6 +255,9 @@ public:
void
brw_blorp_exec(struct brw_context *brw, brw_blorp_params *params);
+void
+gen8_blorp_exec(struct brw_context *brw, brw_blorp_params *params);
+
/**
* Parameters for a HiZ or depth resolve operation.
@@ -409,10 +416,14 @@ public:
virtual void gen6_emit_wm_config(struct brw_context *brw) const;
virtual void gen7_emit_wm_config(struct brw_context *brw) const;
+ virtual void gen8_emit_wm_config(struct brw_context *brw) const;
+
+ virtual void gen8_emit_multisample_state(struct brw_context *brw) const;
virtual void gen6_emit_multisample_state(struct brw_context *brw) const;
virtual void gen7_emit_ps_config(struct brw_context *brw) const;
+ virtual void gen8_emit_ps_config(struct brw_context *brw) const;
protected:
static void gen6_emit_vertex_elems(struct brw_context *brw,
@@ -453,6 +464,7 @@ public:
bool mirror_x, bool mirror_y);
virtual void gen6_emit_vertices(struct brw_context *brw) const;
+ virtual void gen8_emit_vertices_extra(struct brw_context *brw) const;
virtual void gen6_emit_surface_states(struct brw_context *brw);
virtual void gen7_emit_surface_states(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.cpp
[Mesa-dev] [PATCH 03/14] meta: Provide read access to blit shaders
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/common/meta.c | 17 -
src/mesa/drivers/common/meta.h | 5 -
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index cf99d95..8c69b5d 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -92,9 +92,6 @@
static void
meta_clear(struct gl_context *ctx, GLbitfield buffers, bool glsl);
-static struct blit_shader *
-choose_blit_shader(GLenum target, struct blit_shader_table *table);
-
static void cleanup_temp_texture(struct temp_texture *tex);
static void meta_glsl_clear_cleanup(struct clear_state *clear);
static void meta_decompress_cleanup(struct decompress_state *decompress);
@@ -240,14 +237,14 @@ _mesa_meta_compile_and_link_program(struct gl_context
*ctx,
*
* \returns a handle to a shader program on success or zero on failure.
*/
-void
+const struct blit_shader *
_mesa_meta_setup_blit_shader(struct gl_context *ctx,
GLenum target,
bool do_depth,
struct blit_shader_table *table)
{
char *vs_source, *fs_source;
- struct blit_shader *shader = choose_blit_shader(target, table);
+ struct blit_shader *shader = _mesa_meta_choose_blit_shader(target, table);
const char *vs_input, *vs_output, *fs_input, *vs_preprocess, *fs_preprocess;
void *mem_ctx;
@@ -270,7 +267,7 @@ _mesa_meta_setup_blit_shader(struct gl_context *ctx,
if (shader-shader_prog != 0) {
_mesa_UseProgram(shader-shader_prog);
- return;
+ return shader;
}
mem_ctx = ralloc_context(NULL);
@@ -306,6 +303,8 @@ _mesa_meta_setup_blit_shader(struct gl_context *ctx,
shader-type),
shader-shader_prog);
ralloc_free(mem_ctx);
+
+ return shader;
}
/**
@@ -2615,9 +2614,9 @@ _mesa_meta_setup_texture_coords(GLenum faceTarget,
assert(!unexpected target in _mesa_meta_setup_texture_coords());
}
}
-
-static struct blit_shader *
-choose_blit_shader(GLenum target, struct blit_shader_table *table)
+
+struct blit_shader *
+_mesa_meta_choose_blit_shader(GLenum target, struct blit_shader_table *table)
{
switch(target) {
case GL_TEXTURE_1D:
diff --git a/src/mesa/drivers/common/meta.h b/src/mesa/drivers/common/meta.h
index e7d894d..d3bb3a5 100644
--- a/src/mesa/drivers/common/meta.h
+++ b/src/mesa/drivers/common/meta.h
@@ -634,7 +634,10 @@ _mesa_meta_setup_copypix_texture(struct gl_context *ctx,
GLenum intFormat,
GLenum filter);
-void
+struct blit_shader *
+_mesa_meta_choose_blit_shader(GLenum target, struct blit_shader_table *table);
+
+const struct blit_shader *
_mesa_meta_setup_blit_shader(struct gl_context *ctx,
GLenum target,
bool do_depth,
--
1.9.3
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[Mesa-dev] [PATCH 02/14] i965/blorp/gen6: Support for loading glsl-based fragment shaders
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.h| 1 +
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 74
2 files changed, 75 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index aa83c66..9fd4193 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -407,6 +407,7 @@ public:
virtual void gen6_emit_wm_constants(struct brw_context *brw);
+ virtual void gen6_emit_wm_config(struct brw_context *brw) const;
virtual void gen7_emit_wm_config(struct brw_context *brw) const;
virtual void gen6_emit_multisample_state(struct brw_context *brw) const;
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 39d32df..7ba414e 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -34,6 +34,8 @@
#include brw_blorp.h
#include gen6_blorp.h
+#include program/program.h
+
/**
* \name Constants for BLORP VBO
* \{
@@ -719,6 +721,67 @@ gen6_blorp_emit_wm_config(struct brw_context *brw,
ADVANCE_BATCH();
}
+static void
+gen6_meta_emit_wm_config(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_wm_prog_data *prog_data,
+ const struct brw_stage_state *stage_state,
+ bool multisampled_fbo)
+{
+ uint32_t dw2, dw4, dw5, dw6, ksp0, ksp2;
+
+ dw2 = dw4 = dw5 = dw6 = ksp0 = ksp2 = 0;
+
+ dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
+ dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
+ dw5 |= (brw-max_wm_threads - 1) GEN6_WM_MAX_THREADS_SHIFT;
+ dw6 |= prog_data-num_varying_inputs GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
+
+ dw6 |= prog_data-barycentric_interp_modes
+ GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
+
+ dw2 |= (ALIGN(stage_state-sampler_count, 4) / 4)
+ GEN6_WM_SAMPLER_COUNT_SHIFT;
+
+ dw2 |= (prog_data-base.binding_table.size_bytes / 4)
+ GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT;
+
+ if (prog_data-uses_kill | prog_data-uses_omask)
+ dw5 |= GEN6_WM_KILL_ENABLE;
+
+ dw5 |= GEN6_WM_DISPATCH_ENABLE; /* We are rendering */
+
+ if (prog_data-uses_omask)
+ dw5 |= GEN6_WM_OMASK_TO_RENDER_TARGET;
+
+ if (multisampled_fbo)
+ dw6 |= GEN6_WM_MSDISPMODE_PERPIXEL;
+ else
+ dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
+
+ dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
+
+ if (prog_data-uses_pos_offset)
+ dw6 |= GEN6_WM_POSOFFSET_SAMPLE;
+ else
+ dw6 |= GEN6_WM_POSOFFSET_NONE;
+
+ const int min_inv_per_frag = 1;
+ gen6_wm_state_set_programs(prog_data, stage_state, min_inv_per_frag,
+ ksp0, ksp2, dw4, dw5, dw6);
+
+ BEGIN_BATCH(9);
+ OUT_BATCH(_3DSTATE_WM 16 | (9 - 2));
+ OUT_BATCH(ksp0);
+ OUT_BATCH(dw2);
+ OUT_BATCH(0); /* No scratch needed */
+ OUT_BATCH(dw4);
+ OUT_BATCH(dw5);
+ OUT_BATCH(dw6);
+ OUT_BATCH(0); /* No other programs */
+ OUT_BATCH(ksp2);
+ ADVANCE_BATCH();
+}
static void
gen6_blorp_emit_constant_ps(struct brw_context *brw,
@@ -1094,6 +1157,17 @@ brw_meta_fs_params::gen6_emit_wm_constants(struct
brw_context *brw)
}
void
+brw_meta_fs_params::gen6_emit_wm_config(struct brw_context *brw) const
+{
+ gen6_upload_constant_state(brw, wm_prog_data, wm_stage_state);
+
+ const bool multisampled_fbo = dst_num_samples 1;
+ gen6_meta_emit_wm_config(brw, fp, wm_prog_data, wm_stage_state,
+multisampled_fbo);
+ gen6_blorp_emit_binding_table_pointers(brw, wm_stage_state.bind_bo_offset);
+}
+
+void
brw_meta_fs_params::gen6_emit_multisample_state(struct brw_context *brw) const
{
const unsigned sample_mask =
--
1.9.3
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[Mesa-dev] [PATCH 10/14] i965/blorp: Enable glsl-based fbo blits
Use meta-path instead of blorp for 2D-blits.
Reduces cpu-overhead increasing the performance of meta-path. On
IVB (blorp disabled and hence meta path enabled) a microbenchmark
found in mesa-demos (copypixrate -blit -back):
x 62 10665.83 13388.95 11357.77 11467.463 574.57333
+ 62 19933.73 21140.67 20780.81 20757.792 184.91425
Difference at 95.0% confidence
9290.33 +/- 150.247
81.0147% +/- 1.3102%
Compared to default blorp meta is now on par (1-2% faster).
On BDW (where blorp isn't available) the same benchmark:
x 137 9055.4 14551.12 12020.87 12011.815 762.67232
+ 137 13963.49 18281.85 17031.56 16985.443 712.08714
Difference at 95.0% confidence
4973.63 +/- 174.726
41.4061% +/- 1.45462%
No visible changes in public benchmarks. No piglit regressions.
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 10 ++
src/mesa/drivers/dri/i965/intel_fbo.c | 11 +++
2 files changed, 21 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index ae28955..a22f627 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1752,6 +1752,16 @@ brw_blorp_framebuffer(struct brw_context *brw,
GLbitfield mask, GLenum filter);
bool
+brw_meta_fbo_color_blit(struct brw_context *brw,
+struct gl_framebuffer *read_fb,
+struct gl_framebuffer *draw_fb,
+float src_x0, float src_y0,
+float src_x1, float src_y1,
+float dst_x0, float dst_y0,
+float dst_x1, float dst_y1,
+GLenum filter);
+
+bool
brw_blorp_copytexsubimage(struct brw_context *brw,
struct gl_renderbuffer *src_rb,
struct gl_texture_image *dst_image,
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index aebed72..077eb8b 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -878,6 +878,17 @@ intel_blit_framebuffer(struct gl_context *ctx,
if (!_mesa_check_conditional_render(ctx))
return;
+ if (brw-gen = 6 (mask GL_COLOR_BUFFER_BIT)) {
+ if (brw_meta_fbo_color_blit(brw, readFb, drawFb,
+ srcX0, srcY0, srcX1, srcY1,
+ dstX0, dstY0, dstX1, dstY1,
+ filter)) {
+ mask = ~GL_COLOR_BUFFER_BIT;
+ if (mask == 0x0)
+return;
+ }
+ }
+
mask = brw_blorp_framebuffer(brw, readFb, drawFb,
srcX0, srcY0, srcX1, srcY1,
dstX0, dstY0, dstX1, dstY1,
--
1.9.3
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[Mesa-dev] [PATCH 09/14] i965/gen6: Add support for setting minimum layer for tex surfaces
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index ad5ddb5..c006762 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -314,7 +314,7 @@ brw_update_texture_surface(struct brw_context *brw, bool is_integer_format /* unused */, GLenum target, uint32_t effective_depth /* unused */, - uint32_t min_layer /* unused */, + uint32_t min_layer, uint32_t min_lod, uint32_t mip_count, int swizzle /* unused */, uint32_t *surf_offset, @@ -372,6 +372,9 @@ brw_update_texture_surface(struct brw_context *brw, surf[4] = brw_get_surface_num_multisamples(mt-num_samples) | SET_FIELD(min_lod, BRW_SURFACE_MIN_LOD); + if (brw-gen == 6) + surf[4] |= SET_FIELD(min_layer, BRW_SURFACE_MIN_ARRAY_ELEMENT); + surf[5] = mt-align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0; /* Emit relocation to surface contents */ -- 1.9.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2] mesa: add support for exposing up to GL4.2
Reviewed-by: Matt Turner matts...@gmail.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH V2 04/22] i965: Create a helper function intel_miptree_total_width_height()
On Fri, Apr 17, 2015 at 04:51:25PM -0700, Anuj Phogat wrote: and some more code refactoring. No functional changes in this patch. Signed-off-by: Anuj Phogat anuj.pho...@gmail.com Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v5] i965/aa: fixing anti-aliasing bug for thinnest width lines - GEN7
On SNB and IVB hw, for 1 pixel line thickness or less,
the general anti-aliasing algorithm give up - garbage line is generated.
Setting a Line Width of 0.0 specifies the rasterization of
the “thinnest” (one-pixel-wide), non-antialiased lines.
Lines rendered with zero Line Width are rasterized using
Grid Intersection Quantization rules as specified
by bspec section 6.3.12.1 Zero-Width (Cosmetic) Line Rasterization.
v2: Daniel Stone: Fix = used instead of == in an if-statement.
v3: Ian Romanick: Use ._Enabled flag insteed .Enabled.
Add code comments. re-word wrap the commit message.
Add a complete bugzillia list.
Improve the hardcoded values to produce better results.
v4: Matt Turner: typo fixes and adjust = 1.49 to become 1.5
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28832
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=9951
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27007
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60797
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=15006
Signed-off-by: Marius Predut marius.pre...@intel.com
---
src/mesa/drivers/dri/i965/gen7_sf_state.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c
b/src/mesa/drivers/dri/i965/gen7_sf_state.c
index 69853e6..58e3337 100644
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c
@@ -198,9 +198,24 @@ upload_sf_state(struct brw_context *brw)
float line_width =
roundf(CLAMP(ctx-Line.Width, 0.0, ctx-Const.MaxLineWidth));
uint32_t line_width_u3_7 = U_FIXED(line_width, 7);
- /* TODO: line width of 0 is not allowed when MSAA enabled */
- if (line_width_u3_7 == 0)
- line_width_u3_7 = 1;
+ /* Line width of 0 is not allowed when MSAA enabled */
+ if (ctx-Multisample._Enabled) {
+ if (line_width_u3_7 == 0)
+ line_width_u3_7 = 1;
+ } else if (ctx-Line.SmoothFlag ctx-Line.Width 1.5) {
+ /* For 1 pixel line thickness or less, the general
+ * anti-aliasing algorithm gives up, and a garbage line is
+ * generated. Setting a Line Width of 0.0 specifies the
+ * rasterization of the thinnest (one-pixel-wide),
+ * non-antialiased lines.
+ *
+ * Lines rendered with zero Line Width are rasterized using
+ * Grid Intersection Quantization rules as specified by
+ * bspec section 6.3.12.1 Zero-Width (Cosmetic) Line
+ * Rasterization.
+ */
+ line_width_u3_7 = 0;
+ }
dw2 |= line_width_u3_7 GEN6_SF_LINE_WIDTH_SHIFT;
}
if (ctx-Line.SmoothFlag) {
--
1.9.1
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Re: [Mesa-dev] [PATCH] mesa: add support for exposing up to GL4.2
On Thu, Apr 23, 2015 at 7:53 AM, Ilia Mirkin imir...@alum.mit.edu wrote: Add the 4.0/4.1/4.2 extensions lists to compute_version. A coule of extensions aren't in mesa yet, so those are marked with 0 until they become supported. Signed-off-by: Ilia Mirkin imir...@alum.mit.edu --- I wasn't 100% sure about shading_language_packing -- it includes a couple of functions that don't appear until GL 4.2. However since it's enabled for all the drivers that matter in mesa, wtvr. What makes you think that? I actually fixed something recently where we were exposing some shading_language_packing functions as GLSL 4.0 instead of 4.2. As far as I'm aware, it's part of 4.2. commit 8d3aa5926b73c67c7dbd4477b7177aaa00c533e5 Author: Matt Turner matts...@gmail.com Date: Wed Mar 11 18:14:28 2015 -0700 glsl: Expose built-in packing functions under GLSL 4.2. ARB_shading_language_packing is part of GLSL 4.2, not 4.0 as I mistakenly believed. The following functions are available only with ARB_shading_language_packing, GLSL 4.2 (not GLSL 4.0), or ES 3.0: - packSnorm2x16 - unpackSnorm2x16 - packHalf2x16 - unpackHalf2x16 Reviewed-by: Carl Worth cwo...@cworth.org Reviewed-by: Marek Olšák marek.ol...@amd.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: add support for exposing up to GL4.2
On Thu, Apr 23, 2015 at 8:15 AM, Ilia Mirkin imir...@alum.mit.edu wrote: On Thu, Apr 23, 2015 at 11:08 AM, Matt Turner matts...@gmail.com wrote: On Thu, Apr 23, 2015 at 7:53 AM, Ilia Mirkin imir...@alum.mit.edu wrote: Add the 4.0/4.1/4.2 extensions lists to compute_version. A coule of extensions aren't in mesa yet, so those are marked with 0 until they become supported. Signed-off-by: Ilia Mirkin imir...@alum.mit.edu --- I wasn't 100% sure about shading_language_packing -- it includes a couple of functions that don't appear until GL 4.2. However since it's enabled for all the drivers that matter in mesa, wtvr. What makes you think that? I actually fixed something recently where we were exposing some shading_language_packing functions as GLSL 4.0 instead of 4.2. As far as I'm aware, it's part of 4.2. commit 8d3aa5926b73c67c7dbd4477b7177aaa00c533e5 Author: Matt Turner matts...@gmail.com Date: Wed Mar 11 18:14:28 2015 -0700 glsl: Expose built-in packing functions under GLSL 4.2. ARB_shading_language_packing is part of GLSL 4.2, not 4.0 as I mistakenly believed. The following functions are available only with ARB_shading_language_packing, GLSL 4.2 (not GLSL 4.0), or ES 3.0: - packSnorm2x16 - unpackSnorm2x16 - packHalf2x16 - unpackHalf2x16 Reviewed-by: Carl Worth cwo...@cworth.org Reviewed-by: Marek Olšák marek.ol...@amd.com Right. Those were the functions from shading_language_packing that don't appear until GL 4.2. But other ones it includes are in GL 4.0 (packUnorm*, packSnorm4x8). In a theoretical world where we wanted to support every possibility, we'd have a separate packing_400 internal enable which would imply that only the 4.0 ones are there. But in practice, it's all-or-nothing, so who cares. So I included it in the 4.0 list. Buuut... oops. Looks like those actually come in via ARB_gpu_shader5 as well. And shading_language_packing has those *and* the extra ones (for GPUs that don't do gs5). OK. I'll move it to the 4.2 list. Right, I should have mentioned that. As you can tell, the packing/unpacking functions are really a disaster. To make things worse, ES 3.0 exposes a different set of functions than does gpu_shader5 or shading_language_packing. There are actually *three* distinct subsets of shading_language_packing that may be exposed depending on the API and extensions! ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 13/14] i965/blorp/gen6: Prepare vertex buffer setup logic for gen8
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 30 ++
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index f45dcd4..22ea86c 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -111,19 +111,33 @@ gen6_blorp_emit_vertex_buffer_state(struct brw_context
*brw,
if (brw-gen = 7)
dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
- if (brw-gen == 7)
+ switch (brw-gen) {
+ case 7:
dw0 |= GEN7_MOCS_L3 16;
+ break;
+ case 8:
+ dw0 |= BDW_MOCS_WB 16;
+ break;
+ case 9:
+ dw0 |= SKL_MOCS_WB 16;
+ break;
+ }
BEGIN_BATCH(batch_length);
OUT_BATCH((_3DSTATE_VERTEX_BUFFERS 16) | (batch_length - 2));
OUT_BATCH(dw0);
- /* start address */
- OUT_RELOC(brw-batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
- vertex_offset);
- /* end address */
- OUT_RELOC(brw-batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
- vertex_offset + vbo_size - 1);
- OUT_BATCH(0);
+ if (brw-gen = 8) {
+ OUT_RELOC64(brw-batch.bo, I915_GEM_DOMAIN_VERTEX, 0, vertex_offset);
+ OUT_BATCH(vbo_size);
+ } else {
+ /* start address */
+ OUT_RELOC(brw-batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
+vertex_offset);
+ /* end address */
+ OUT_RELOC(brw-batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
+vertex_offset + vbo_size - 1);
+ OUT_BATCH(0);
+ }
ADVANCE_BATCH();
}
--
1.9.3
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Re: [Mesa-dev] [PATCH 17/18] i965/ps/gen8: Refactor state uploading
On Thu, Apr 23, 2015 at 11:53:49AM -0700, Matt Turner wrote:
On Wed, Apr 22, 2015 at 1:47 PM, Topi Pohjolainen
topi.pohjolai...@intel.com wrote:
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_state.h | 12 +
src/mesa/drivers/dri/i965/gen8_ps_state.c | 74
---
2 files changed, 59 insertions(+), 27 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 178f039..0c4f65e 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -265,6 +265,18 @@ void gen7_set_surface_mcs_info(struct brw_context *brw,
void gen7_check_surface_setup(uint32_t *surf, bool is_render_target);
void gen7_init_vtable_surface_functions(struct brw_context *brw);
+/* gen8_ps_state.c */
+void gen8_upload_ps_state(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_stage_state *stage_state,
+ const struct brw_wm_prog_data *prog_data,
+ uint32_t fast_clear_op);
+
+void gen8_upload_ps_extra(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_wm_prog_data *prog_data,
+ bool multisampled_fbo);
+
/* gen7_sol_state.c */
void gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
const struct brw_vue_map *vue_map);
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c
b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index 5f39e12..da6136b 100644
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -27,15 +27,13 @@
#include brw_defines.h
#include intel_batchbuffer.h
-static void
-upload_ps_extra(struct brw_context *brw)
+void
+gen8_upload_ps_extra(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_wm_prog_data *prog_data,
+ bool multisampled_fbo)
{
struct gl_context *ctx = brw-ctx;
- /* BRW_NEW_FRAGMENT_PROGRAM */
- const struct brw_fragment_program *fp =
- brw_fragment_program_const(brw-fragment_program);
- /* BRW_NEW_FS_PROG_DATA */
- const struct brw_wm_prog_data *prog_data = brw-wm.prog_data;
uint32_t dw1 = 0;
dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
@@ -47,16 +45,14 @@ upload_ps_extra(struct brw_context *brw)
if (prog_data-num_varying_inputs != 0)
dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
- if (fp-program.Base.InputsRead VARYING_BIT_POS)
+ if (fp-Base.InputsRead VARYING_BIT_POS)
dw1 |= GEN8_PSX_USES_SOURCE_DEPTH | GEN8_PSX_USES_SOURCE_W;
- /* BRW_NEW_NUM_SAMPLES | _NEW_MULTISAMPLE */
- bool multisampled_fbo = brw-num_samples 1;
if (multisampled_fbo
- _mesa_get_min_invocations_per_fragment(ctx, fp-program, false)
1)
+ _mesa_get_min_invocations_per_fragment(ctx, fp, false) 1)
dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
- if (fp-program.Base.SystemValuesRead SYSTEM_BIT_SAMPLE_MASK_IN)
+ if (fp-Base.SystemValuesRead SYSTEM_BIT_SAMPLE_MASK_IN)
dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK;
if (prog_data-uses_omask)
@@ -68,6 +64,20 @@ upload_ps_extra(struct brw_context *brw)
ADVANCE_BATCH();
}
+static void
+upload_ps_extra(struct brw_context *brw)
+{
+ /* BRW_NEW_FRAGMENT_PROGRAM */
+ const struct brw_fragment_program *fp =
+ brw_fragment_program_const(brw-fragment_program);
+ /* BRW_NEW_FS_PROG_DATA */
+ const struct brw_wm_prog_data *prog_data = brw-wm.prog_data;
+ /* BRW_NEW_NUM_SAMPLES | _NEW_MULTISAMPLE */
+ const bool multisampled_fbo = brw-num_samples 1;
+
+ gen8_upload_ps_extra(brw, fp-program, prog_data, multisampled_fbo);
+}
+
const struct brw_tracked_state gen8_ps_extra = {
.dirty = {
.mesa = _NEW_MULTISAMPLE,
@@ -118,23 +128,24 @@ const struct brw_tracked_state gen8_wm_state = {
.emit = upload_wm_state,
};
-static void
-upload_ps_state(struct brw_context *brw)
+void
+gen8_upload_ps_state(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_stage_state *stage_state,
+ const struct brw_wm_prog_data *prog_data,
+ uint32_t fast_clear_op)
{
struct gl_context *ctx = brw-ctx;
uint32_t dw3 = 0, dw6 = 0, dw7 = 0, ksp0, ksp2 = 0;
- /* BRW_NEW_FS_PROG_DATA */
- const struct brw_wm_prog_data *prog_data = brw-wm.prog_data;
-
/* Initialize the execution mask with VMask. Otherwise, derivatives are
* incorrect for subspans where some of the pixels are unlit. We
Re: [Mesa-dev] [PATCH 18/18] i965/gen8: Expose state base address setup
On Thu, Apr 23, 2015 at 11:53:57AM -0700, Matt Turner wrote: On Wed, Apr 22, 2015 at 1:47 PM, Topi Pohjolainen topi.pohjolai...@intel.com wrote: Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com --- src/mesa/drivers/dri/i965/brw_state.h | 3 +++ src/mesa/drivers/dri/i965/gen8_misc_state.c | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index 0c4f65e..73dcca1 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -171,6 +171,9 @@ void brw_upload_invariant_state(struct brw_context *brw); uint32_t brw_depthbuffer_format(struct brw_context *brw); +/* gen8_misc_state.c */ +void gen8_upload_state_base_address(struct brw_context *brw); + /*** * brw_state.c diff --git a/src/mesa/drivers/dri/i965/gen8_misc_state.c b/src/mesa/drivers/dri/i965/gen8_misc_state.c index 88e425f..b20038e 100644 --- a/src/mesa/drivers/dri/i965/gen8_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen8_misc_state.c @@ -29,7 +29,7 @@ /** * Define the base addresses which some state is referenced from. */ -static void upload_state_base_address(struct brw_context *brw) +void gen8_upload_state_base_address(struct brw_context *brw) Presumably this patch is needed for something else? gen8_upload_state_base_address is still only used in this file. Yes, this is just preparing things for my launch glsl-based programs using blorp-logic-series. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Add an INTEL_DEBUG=spill option to test spilling
On Thu, Apr 23, 2015 at 2:50 PM, Jason Ekstrand ja...@jlekstrand.net wrote: diff --git a/src/mesa/drivers/dri/i965/intel_debug.h b/src/mesa/drivers/dri/i965/intel_debug.h index 807ad98..e5af998 100644 --- a/src/mesa/drivers/dri/i965/intel_debug.h +++ b/src/mesa/drivers/dri/i965/intel_debug.h @@ -64,6 +64,7 @@ extern uint64_t INTEL_DEBUG; #define DEBUG_ANNOTATION (1 28) #define DEBUG_NO8 (1 29) #define DEBUG_VEC4VS (1 30) +#define DEBUG_SPILL (1l 31) That seems awkward... did you mean 1U? FWIW mesa's not at all careful about that... ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 18/18] i965/gen8: Expose state base address setup
On Wed, Apr 22, 2015 at 1:47 PM, Topi Pohjolainen
topi.pohjolai...@intel.com wrote:
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_state.h | 3 +++
src/mesa/drivers/dri/i965/gen8_misc_state.c | 4 ++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 0c4f65e..73dcca1 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -171,6 +171,9 @@ void brw_upload_invariant_state(struct brw_context *brw);
uint32_t
brw_depthbuffer_format(struct brw_context *brw);
+/* gen8_misc_state.c */
+void gen8_upload_state_base_address(struct brw_context *brw);
+
/***
* brw_state.c
diff --git a/src/mesa/drivers/dri/i965/gen8_misc_state.c
b/src/mesa/drivers/dri/i965/gen8_misc_state.c
index 88e425f..b20038e 100644
--- a/src/mesa/drivers/dri/i965/gen8_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_misc_state.c
@@ -29,7 +29,7 @@
/**
* Define the base addresses which some state is referenced from.
*/
-static void upload_state_base_address(struct brw_context *brw)
+void gen8_upload_state_base_address(struct brw_context *brw)
Presumably this patch is needed for something else?
gen8_upload_state_base_address is still only used in this file.
{
uint32_t mocs_wb = brw-gen = 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
int pkt_len = brw-gen = 9 ? 19 : 16;
@@ -78,5 +78,5 @@ const struct brw_tracked_state gen8_state_base_address = {
.brw = BRW_NEW_BATCH |
BRW_NEW_PROGRAM_CACHE,
},
- .emit = upload_state_base_address
+ .emit = gen8_upload_state_base_address
};
--
1.9.3
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Re: [Mesa-dev] [PATCH 02/18] i965: Expose and refactor brw_update_renderbuffer_surfaces()
On Wed, Apr 22, 2015 at 1:47 PM, Topi Pohjolainen
topi.pohjolai...@intel.com wrote:
Note that brw_update_renderbuffer_surfaces() already had a helper
variable which was used in parallel to direct access of the current
draw buffer of the context.
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_state.h| 5 +++
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 51
++--
2 files changed, 35 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index cfa67b6..83058b9 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -233,6 +233,11 @@ GLuint translate_tex_format(struct brw_context *brw,
int brw_get_texture_swizzle(const struct gl_context *ctx,
const struct gl_texture_object *t);
+void brw_update_renderbuffer_surfaces(struct brw_context *brw,
+ const struct gl_framebuffer *fb,
+ uint32_t render_target_start,
+ uint32_t *surf_offset);
+
/* gen7_wm_surface_state.c */
uint32_t gen7_surface_tiling_mode(uint32_t tiling);
uint32_t gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout
l);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 959d6c2..82dd92b 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -731,40 +731,49 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
/**
* Construct SURFACE_STATE objects for renderbuffers/draw buffers.
*/
-static void
-brw_update_renderbuffer_surfaces(struct brw_context *brw)
+void
+brw_update_renderbuffer_surfaces(struct brw_context *brw,
+ const struct gl_framebuffer *fb,
+ uint32_t render_target_start,
+ uint32_t *surf_offset)
{
- struct gl_context *ctx = brw-ctx;
- /* _NEW_BUFFERS */
- const struct gl_framebuffer *fb = ctx-DrawBuffer;
GLuint i;
- /* _NEW_BUFFERS | _NEW_COLOR */
/* Update surfaces for drawing buffers */
- if (ctx-DrawBuffer-_NumColorDrawBuffers = 1) {
- for (i = 0; i ctx-DrawBuffer-_NumColorDrawBuffers; i++) {
- const uint32_t surf_index =
Extra space at the end of this line.
-brw-wm.prog_data-binding_table.render_target_start + i;
+ if (fb-_NumColorDrawBuffers = 1) {
+ for (i = 0; i fb-_NumColorDrawBuffers; i++) {
+ const uint32_t surf_index = render_target_start + i;
-if (intel_renderbuffer(ctx-DrawBuffer-_ColorDrawBuffers[i])) {
-brw-wm.base.surf_offset[surf_index] =
+if (intel_renderbuffer(fb-_ColorDrawBuffers[i])) {
Remove the tab here while we're changing it.
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Re: [Mesa-dev] [PATCH 06/18] i965: Move texture buffer dispatch into single location
On Wed, Apr 22, 2015 at 1:47 PM, Topi Pohjolainen topi.pohjolai...@intel.com wrote: All generations do the same exacr dispatch and it could be typo: exact ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 17/18] i965/ps/gen8: Refactor state uploading
On Wed, Apr 22, 2015 at 1:47 PM, Topi Pohjolainen
topi.pohjolai...@intel.com wrote:
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_state.h | 12 +
src/mesa/drivers/dri/i965/gen8_ps_state.c | 74
---
2 files changed, 59 insertions(+), 27 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 178f039..0c4f65e 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -265,6 +265,18 @@ void gen7_set_surface_mcs_info(struct brw_context *brw,
void gen7_check_surface_setup(uint32_t *surf, bool is_render_target);
void gen7_init_vtable_surface_functions(struct brw_context *brw);
+/* gen8_ps_state.c */
+void gen8_upload_ps_state(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_stage_state *stage_state,
+ const struct brw_wm_prog_data *prog_data,
+ uint32_t fast_clear_op);
+
+void gen8_upload_ps_extra(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_wm_prog_data *prog_data,
+ bool multisampled_fbo);
+
/* gen7_sol_state.c */
void gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
const struct brw_vue_map *vue_map);
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c
b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index 5f39e12..da6136b 100644
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -27,15 +27,13 @@
#include brw_defines.h
#include intel_batchbuffer.h
-static void
-upload_ps_extra(struct brw_context *brw)
+void
+gen8_upload_ps_extra(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_wm_prog_data *prog_data,
+ bool multisampled_fbo)
{
struct gl_context *ctx = brw-ctx;
- /* BRW_NEW_FRAGMENT_PROGRAM */
- const struct brw_fragment_program *fp =
- brw_fragment_program_const(brw-fragment_program);
- /* BRW_NEW_FS_PROG_DATA */
- const struct brw_wm_prog_data *prog_data = brw-wm.prog_data;
uint32_t dw1 = 0;
dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
@@ -47,16 +45,14 @@ upload_ps_extra(struct brw_context *brw)
if (prog_data-num_varying_inputs != 0)
dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
- if (fp-program.Base.InputsRead VARYING_BIT_POS)
+ if (fp-Base.InputsRead VARYING_BIT_POS)
dw1 |= GEN8_PSX_USES_SOURCE_DEPTH | GEN8_PSX_USES_SOURCE_W;
- /* BRW_NEW_NUM_SAMPLES | _NEW_MULTISAMPLE */
- bool multisampled_fbo = brw-num_samples 1;
if (multisampled_fbo
- _mesa_get_min_invocations_per_fragment(ctx, fp-program, false) 1)
+ _mesa_get_min_invocations_per_fragment(ctx, fp, false) 1)
dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
- if (fp-program.Base.SystemValuesRead SYSTEM_BIT_SAMPLE_MASK_IN)
+ if (fp-Base.SystemValuesRead SYSTEM_BIT_SAMPLE_MASK_IN)
dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK;
if (prog_data-uses_omask)
@@ -68,6 +64,20 @@ upload_ps_extra(struct brw_context *brw)
ADVANCE_BATCH();
}
+static void
+upload_ps_extra(struct brw_context *brw)
+{
+ /* BRW_NEW_FRAGMENT_PROGRAM */
+ const struct brw_fragment_program *fp =
+ brw_fragment_program_const(brw-fragment_program);
+ /* BRW_NEW_FS_PROG_DATA */
+ const struct brw_wm_prog_data *prog_data = brw-wm.prog_data;
+ /* BRW_NEW_NUM_SAMPLES | _NEW_MULTISAMPLE */
+ const bool multisampled_fbo = brw-num_samples 1;
+
+ gen8_upload_ps_extra(brw, fp-program, prog_data, multisampled_fbo);
+}
+
const struct brw_tracked_state gen8_ps_extra = {
.dirty = {
.mesa = _NEW_MULTISAMPLE,
@@ -118,23 +128,24 @@ const struct brw_tracked_state gen8_wm_state = {
.emit = upload_wm_state,
};
-static void
-upload_ps_state(struct brw_context *brw)
+void
+gen8_upload_ps_state(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_stage_state *stage_state,
+ const struct brw_wm_prog_data *prog_data,
+ uint32_t fast_clear_op)
{
struct gl_context *ctx = brw-ctx;
uint32_t dw3 = 0, dw6 = 0, dw7 = 0, ksp0, ksp2 = 0;
- /* BRW_NEW_FS_PROG_DATA */
- const struct brw_wm_prog_data *prog_data = brw-wm.prog_data;
-
/* Initialize the execution mask with VMask. Otherwise, derivatives are
* incorrect for subspans where some of the pixels are unlit. We believe
* the bit just didn't take effect in previous generations.
*/
dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
- dw3 |=
- (ALIGN(brw-wm.base.sampler_count, 4) / 4)
Re: [Mesa-dev] [PATCH] i965: Add an INTEL_DEBUG=spill option to test spilling
Ilia Mirkin imir...@alum.mit.edu writes: That seems awkward... did you mean 1U? FWIW mesa's not at all careful about that... Or maybe even UINT64_C(1). 1l would still be 32-bit on 32-bit architectures. I guess this is more of a problem for subsequent flags that go over 32-bit. - Neil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Add an INTEL_DEBUG=spill option to test spilling
On Apr 23, 2015 12:19 PM, Neil Roberts n...@linux.intel.com wrote: Ilia Mirkin imir...@alum.mit.edu writes: That seems awkward... did you mean 1U? FWIW mesa's not at all careful about that... Or maybe even UINT64_C(1). 1l would still be 32-bit on 32-bit architectures. I guess this is more of a problem for subsequent flags that go over 32-bit. How about 1ull? --Jason ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Add an INTEL_DEBUG=spill option to test spilling
On Thu, Apr 23, 2015 at 3:20 PM, Jason Ekstrand ja...@jlekstrand.net wrote: On Apr 23, 2015 12:19 PM, Neil Roberts n...@linux.intel.com wrote: Ilia Mirkin imir...@alum.mit.edu writes: That seems awkward... did you mean 1U? FWIW mesa's not at all careful about that... Or maybe even UINT64_C(1). 1l would still be 32-bit on 32-bit architectures. I guess this is more of a problem for subsequent flags that go over 32-bit. Technically 1 31 is undefined in C. Practically it works just fine. How about 1ull? That works too. FWIW I've always done ULL, not ull -- not sure what the mesa convention is. Oftentimes there are BIT() and BIT64() macros that abstract all this out, but I couldn't find them on a quick scan. -ilia ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] i965: Add an INTEL_DEBUG=spill option to test spilling
---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 2 +-
src/mesa/drivers/dri/i965/intel_debug.c | 1 +
src/mesa/drivers/dri/i965/intel_debug.h | 1 +
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index dc433b0..94e1a0a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -627,7 +627,7 @@ fs_visitor::assign_regs(bool allow_spilling)
}
/* Debug of register spilling: Go spill everything. */
- if (0) {
+ if (unlikely(INTEL_DEBUG DEBUG_SPILL)) {
int reg = choose_spill_reg(g);
if (reg != -1) {
diff --git a/src/mesa/drivers/dri/i965/intel_debug.c
b/src/mesa/drivers/dri/i965/intel_debug.c
index a5b883c..19be464 100644
--- a/src/mesa/drivers/dri/i965/intel_debug.c
+++ b/src/mesa/drivers/dri/i965/intel_debug.c
@@ -69,6 +69,7 @@ static const struct dri_debug_control debug_control[] = {
{ ann, DEBUG_ANNOTATION },
{ no8, DEBUG_NO8 },
{ vec4vs, DEBUG_VEC4VS },
+ { spill, DEBUG_SPILL },
{ NULL,0 }
};
diff --git a/src/mesa/drivers/dri/i965/intel_debug.h
b/src/mesa/drivers/dri/i965/intel_debug.h
index 807ad98..e5af998 100644
--- a/src/mesa/drivers/dri/i965/intel_debug.h
+++ b/src/mesa/drivers/dri/i965/intel_debug.h
@@ -64,6 +64,7 @@ extern uint64_t INTEL_DEBUG;
#define DEBUG_ANNOTATION (1 28)
#define DEBUG_NO8 (1 29)
#define DEBUG_VEC4VS (1 30)
+#define DEBUG_SPILL (1l 31)
#ifdef HAVE_ANDROID_PLATFORM
#define LOG_TAG INTEL-MESA
--
2.3.5
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Re: [Mesa-dev] i965: Batch emission refactoring
I've looked through all 18 patches, and they look fine to me -- but I'm not sure how much that's worth. I noted a bunch of whitespace mistakes (Is there a way to configure git commit to warn you about things like this?) but not much else. I don't know if that's because the series is perfect or if I don't know enough to actually do a meaningful review. I feel comfortable giving an Acked-by: Matt Turner matts...@gmail.com for the first 17 patches. I wasn't sure about removing 'static' in 18. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Add an INTEL_DEBUG=spill option to test spilling
On Thu, Apr 23, 2015 at 3:24 PM, Jordan Justen jordan.l.jus...@intel.com wrote: +#define DEBUG_SPILL (1l 31) That seems awkward... did you mean 1U? FWIW mesa's not at all careful about that... Yeah, I agree. 1l is awkward. But I think 1U is just unsigned. I don't think that is guaranteed to be 64-bit. In fact it's guaranteed to be 32-bit. Which can hold 1 31 just fine :) -ilia ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 13/18] i965: Pass slice details as parameters for surface setup
On Wed, Apr 22, 2015 at 1:47 PM, Topi Pohjolainen
topi.pohjolai...@intel.com wrote:
Also changed a couple of direct shifts into SET_FIELD().
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 3 ++-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 30
+--
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 14 +--
src/mesa/drivers/dri/i965/gen8_surface_state.c| 10 +++-
4 files changed, 29 insertions(+), 28 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index b90d329..ae28955 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -964,10 +964,11 @@ struct brw_context
{
void (*update_texture_surface)(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
- struct gl_texture_object *tObj,
uint32_t tex_format,
bool is_integer_format,
GLenum target, uint32_t effective_depth,
+ uint32_t min_layer,
+ uint32_t min_lod, uint32_t mip_count,
Trailing whitespace.
int swizzle, uint32_t *surf_offset,
bool for_gather);
uint32_t (*update_renderbuffer_surface)(struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index f7acad4..ad5ddb5 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -310,16 +310,16 @@ update_buffer_texture_surface(struct gl_context *ctx,
static void
brw_update_texture_surface(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
- struct gl_texture_object *tObj,
uint32_t tex_format,
bool is_integer_format /* unused */,
GLenum target,
uint32_t effective_depth /* unused */,
+ uint32_t min_layer /* unused */,
+ uint32_t min_lod, uint32_t mip_count,
Trailing whitespace.
int swizzle /* unused */,
uint32_t *surf_offset,
bool for_gather)
{
- struct intel_texture_object *intelObj = intel_texture_object(tObj);
uint32_t *surf;
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
@@ -361,16 +361,16 @@ brw_update_texture_surface(struct brw_context *brw,
surf[1] = mt-bo-offset64 + mt-offset; /* reloc */
- surf[2] = ((intelObj-_MaxLevel - tObj-BaseLevel)
BRW_SURFACE_LOD_SHIFT |
- (mt-logical_width0 - 1) BRW_SURFACE_WIDTH_SHIFT |
- (mt-logical_height0 - 1) BRW_SURFACE_HEIGHT_SHIFT);
+ surf[2] = SET_FIELD(mip_count, BRW_SURFACE_LOD) |
+ SET_FIELD(mt-logical_width0 - 1, BRW_SURFACE_WIDTH) |
+ SET_FIELD(mt-logical_height0 - 1, BRW_SURFACE_HEIGHT);
- surf[3] = (brw_get_surface_tiling_bits(mt-tiling) |
- (mt-logical_depth0 - 1) BRW_SURFACE_DEPTH_SHIFT |
- (mt-pitch - 1) BRW_SURFACE_PITCH_SHIFT);
+ surf[3] = brw_get_surface_tiling_bits(mt-tiling) |
+SET_FIELD(mt-logical_depth0 - 1, BRW_SURFACE_DEPTH) |
+SET_FIELD(mt-pitch - 1, BRW_SURFACE_PITCH);
Remove the tabs in these two lines.
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Re: [Mesa-dev] [PATCH 15/18] i965/wm/gen6: Refactor push constant state uploading
On Wed, Apr 22, 2015 at 1:47 PM, Topi Pohjolainen
topi.pohjolai...@intel.com wrote:
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_state.h | 5
src/mesa/drivers/dri/i965/gen6_wm_state.c | 50
++-
2 files changed, 34 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index ca3274d..5be8035 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -300,6 +300,11 @@ gen6_wm_state_set_programs(const struct brw_wm_prog_data
*prog_data,
uint32_t *ksp0, uint32_t *ksp2,
uint32_t *dw4, uint32_t *dw5, uint32_t *dw6);
+void
+gen6_upload_constant_state(struct brw_context *brw,
+ const struct brw_wm_prog_data *prog_data,
+ const struct brw_stage_state *stage_state);
+
/* gen6_sf_state.c */
void
calculate_attr_overrides(const struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c
b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index bc921e5..9edaf81 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -96,26 +96,11 @@ gen6_wm_state_set_programs(const struct brw_wm_prog_data
*prog_data,
}
}
-static void
-upload_wm_state(struct brw_context *brw)
+void
+gen6_upload_constant_state(struct brw_context *brw,
+ const struct brw_wm_prog_data *prog_data,
+ const struct brw_stage_state *stage_state)
{
- struct gl_context *ctx = brw-ctx;
- /* BRW_NEW_FRAGMENT_PROGRAM */
- const struct brw_fragment_program *fp =
- brw_fragment_program_const(brw-fragment_program);
- /* BRW_NEW_FS_PROG_DATA */
- const struct brw_wm_prog_data *prog_data = brw-wm.prog_data;
- uint32_t dw2, dw4, dw5, dw6, ksp0, ksp2;
-
- /* _NEW_BUFFERS */
- bool multisampled_fbo = ctx-DrawBuffer-Visual.samples 1;
-
- /* We can't fold this into gen6_upload_wm_push_constants(), because
-* according to the SNB PRM, vol 2 part 1 section 7.2.2
-* (3DSTATE_CONSTANT_PS [DevSNB]):
-*
-* [DevSNB]: This packet must be followed by WM_STATE.
-*/
if (prog_data-base.nr_params == 0) {
/* Disable the push constant buffers. */
BEGIN_BATCH(5);
@@ -133,13 +118,36 @@ upload_wm_state(struct brw_context *brw)
/* Pointer to the WM constant buffer. Covered by the set of
* state flags from gen6_upload_wm_push_constants.
*/
- OUT_BATCH(brw-wm.base.push_const_offset +
- brw-wm.base.push_const_size - 1);
+ OUT_BATCH(stage_state-push_const_offset +
+ stage_state-push_const_size - 1);
Tab.
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Re: [Mesa-dev] [PATCH 05/18] i965: Refactor sampler state setup
On Wed, Apr 22, 2015 at 1:47 PM, Topi Pohjolainen
topi.pohjolai...@intel.com wrote:
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_sampler_state.c | 60
+--
src/mesa/drivers/dri/i965/brw_state.h | 9
2 files changed, 47 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c
b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index c78e2e3..c1daa44 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -375,21 +375,16 @@ upload_default_color(struct brw_context *brw,
* Sets the sampler state for a single unit based off of the sampler key
* entry.
*/
-static void
+void
brw_update_sampler_state(struct brw_context *brw,
- int unit,
+ GLenum target, bool tex_cube_map_seamless,
+ GLfloat tex_unit_lod_bias,
+ mesa_format format, GLenum base_format,
+ bool is_integer_format,
+ const struct gl_sampler_object* sampler,
* with the parameter name.
uint32_t *sampler_state,
uint32_t batch_offset_for_sampler_state)
{
- struct gl_context *ctx = brw-ctx;
- const struct gl_texture_unit *texUnit = ctx-Texture.Unit[unit];
- const struct gl_texture_object *texObj = texUnit-_Current;
- const struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
-
- /* These don't use samplers at all. */
- if (texObj-Target == GL_TEXTURE_BUFFER)
- return;
-
unsigned min_filter, mag_filter, mip_filter;
/* Select min and mip filters. */
@@ -459,12 +454,12 @@ brw_update_sampler_state(struct brw_context *brw,
unsigned wrap_t = translate_wrap_mode(brw, sampler-WrapT,
either_nearest);
unsigned wrap_r = translate_wrap_mode(brw, sampler-WrapR,
either_nearest);
- if (texObj-Target == GL_TEXTURE_CUBE_MAP ||
- texObj-Target == GL_TEXTURE_CUBE_MAP_ARRAY) {
+ if (target == GL_TEXTURE_CUBE_MAP ||
+ target == GL_TEXTURE_CUBE_MAP_ARRAY) {
/* Cube maps must use the same wrap mode for all three coordinate
* dimensions. Prior to Haswell, only CUBE and CLAMP are valid.
*/
- if ((ctx-Texture.CubeMapSeamless || sampler-CubeMapSeamless)
+ if ((tex_cube_map_seamless || sampler-CubeMapSeamless)
(sampler-MinFilter != GL_NEAREST ||
sampler-MagFilter != GL_NEAREST)) {
wrap_s = BRW_TEXCOORDMODE_CUBE;
@@ -475,7 +470,7 @@ brw_update_sampler_state(struct brw_context *brw,
wrap_t = BRW_TEXCOORDMODE_CLAMP;
wrap_r = BRW_TEXCOORDMODE_CLAMP;
}
- } else if (texObj-Target == GL_TEXTURE_1D) {
+ } else if (target == GL_TEXTURE_1D) {
/* There's a bug in 1D texture sampling - it actually pays
* attention to the wrap_t value, though it should not.
* Override the wrap_t value here to GL_REPEAT to keep
@@ -495,7 +490,7 @@ brw_update_sampler_state(struct brw_context *brw,
const unsigned min_lod = U_FIXED(CLAMP(sampler-MinLod, 0, 13), lod_bits);
const unsigned max_lod = U_FIXED(CLAMP(sampler-MaxLod, 0, 13), lod_bits);
const int lod_bias =
- S_FIXED(CLAMP(texUnit-LodBias + sampler-LodBias, -16, 15), lod_bits);
+ S_FIXED(CLAMP(tex_unit_lod_bias + sampler-LodBias, -16, 15),
lod_bits);
const unsigned base_level = U_FIXED(0, 1);
/* Upload the border color if necessary. If not, just point it at
@@ -506,14 +501,12 @@ brw_update_sampler_state(struct brw_context *brw,
if (wrap_mode_needs_border_color(wrap_s) ||
wrap_mode_needs_border_color(wrap_t) ||
wrap_mode_needs_border_color(wrap_r)) {
- const struct gl_texture_image *first_image =
- texObj-Image[0][texObj-BaseLevel];
upload_default_color(brw, sampler,
- first_image-TexFormat, first_image-_BaseFormat,
- texObj-_IsIntegerFormat, border_color_offset);
+ format, base_format, is_integer_format,
+ border_color_offset);
}
- const bool non_normalized_coords = texObj-Target == GL_TEXTURE_RECTANGLE;
+ const bool non_normalized_coords = target == GL_TEXTURE_RECTANGLE;
brw_emit_sampler_state(brw,
sampler_state,
@@ -528,6 +521,29 @@ brw_update_sampler_state(struct brw_context *brw,
border_color_offset);
}
+static void
+update_sampler_state(struct brw_context *brw,
+ int unit,
+ uint32_t *sampler_state,
+ uint32_t batch_offset_for_sampler_state)
+{
+ struct gl_context *ctx = brw-ctx;
+ const struct gl_texture_unit *texUnit = ctx-Texture.Unit[unit];
+ const struct gl_texture_object *texObj =
Re: [Mesa-dev] [PATCH] i965: Add an INTEL_DEBUG=spill option to test spilling
On 2015-04-23 12:01:41, Ilia Mirkin wrote: On Thu, Apr 23, 2015 at 2:50 PM, Jason Ekstrand ja...@jlekstrand.net wrote: diff --git a/src/mesa/drivers/dri/i965/intel_debug.h b/src/mesa/drivers/dri/i965/intel_debug.h index 807ad98..e5af998 100644 --- a/src/mesa/drivers/dri/i965/intel_debug.h +++ b/src/mesa/drivers/dri/i965/intel_debug.h @@ -64,6 +64,7 @@ extern uint64_t INTEL_DEBUG; #define DEBUG_ANNOTATION (1 28) #define DEBUG_NO8 (1 29) #define DEBUG_VEC4VS (1 30) +#define DEBUG_SPILL (1l 31) That seems awkward... did you mean 1U? FWIW mesa's not at all careful about that... Yeah, I agree. 1l is awkward. But I think 1U is just unsigned. I don't think that is guaranteed to be 64-bit. Wouldn't 1ULL be what we want? In brw_context.h we use 'ull' in a similar scenario. I prefer the upper case version because it stands out better, and avoids the l/1 confusion. With 1ULL (or 1ull) Reviewed-by: Jordan Justen jordan.l.jus...@intel.com -Jordan ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 01/18] i965: Refactor rb surface setup to allow caller to store offsets
On Wed, Apr 22, 2015 at 1:47 PM, Topi Pohjolainen
topi.pohjolai...@intel.com wrote:
Notice that in gen7_wm_surface_state.c there is also indentation
change in the surrounding code removing tabs.
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 8 +++
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 28
---
src/mesa/drivers/dri/i965/gen6_surface_state.c| 17 +++---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 20
src/mesa/drivers/dri/i965/gen8_surface_state.c| 18 +++
5 files changed, 46 insertions(+), 45 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index a6d6787..9f4eddd 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -966,10 +966,10 @@ struct brw_context
unsigned unit,
uint32_t *surf_offset,
bool for_gather);
- void (*update_renderbuffer_surface)(struct brw_context *brw,
- struct gl_renderbuffer *rb,
- bool layered,
- unsigned unit);
+ uint32_t (*update_renderbuffer_surface)(struct brw_context *brw,
+ struct gl_renderbuffer *rb,
+ bool layered, unsigned unit,
+ uint32_t surf_index);
void (*emit_buffer_surface_state)(struct brw_context *brw,
uint32_t *out_offset,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 161d140..959d6c2 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -626,11 +626,11 @@ brw_emit_null_surface_state(struct brw_context *brw,
* While it is only used for the front/back buffer currently, it should be
* usable for further buffers when doing ARB_draw_buffer support.
*/
-static void
+static uint32_t
brw_update_renderbuffer_surface(struct brw_context *brw,
struct gl_renderbuffer *rb,
- bool layered,
- unsigned int unit)
+ bool layered, unsigned unit,
Since you have to modify this line, take the opportunity to remove the
tabs from it.
+uint32_t surf_index)
{
struct gl_context *ctx = brw-ctx;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
@@ -638,11 +638,10 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
uint32_t *surf;
uint32_t tile_x, tile_y;
uint32_t format = 0;
+ uint32_t offset;
/* _NEW_BUFFERS */
mesa_format rb_format = _mesa_get_render_format(ctx,
intel_rb_format(irb));
/* BRW_NEW_FS_PROG_DATA */
- uint32_t surf_index =
- brw-wm.prog_data-binding_table.render_target_start + unit;
assert(!layered);
@@ -663,8 +662,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
intel_miptree_used_for_rendering(irb-mt);
- surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
- brw-wm.base.surf_offset[surf_index]);
+ surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, offset);
format = brw-render_target_format[rb_format];
if (unlikely(!brw-format_supported_as_render_target[rb_format])) {
@@ -721,11 +719,13 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
}
drm_intel_bo_emit_reloc(brw-batch.bo,
- brw-wm.base.surf_offset[surf_index] + 4,
+ offset + 4,
Tabs.
mt-bo,
surf[1] - mt-bo-offset64,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER);
+
+ return offset;
}
/**
@@ -743,13 +743,15 @@ brw_update_renderbuffer_surfaces(struct brw_context
*brw)
/* Update surfaces for drawing buffers */
if (ctx-DrawBuffer-_NumColorDrawBuffers = 1) {
for (i = 0; i ctx-DrawBuffer-_NumColorDrawBuffers; i++) {
+ const uint32_t surf_index =
+brw-wm.prog_data-binding_table.render_target_start + i;
+
if (intel_renderbuffer(ctx-DrawBuffer-_ColorDrawBuffers[i])) {
- brw-vtbl.update_renderbuffer_surface(brw,
ctx-DrawBuffer-_ColorDrawBuffers[i],
-
ctx-DrawBuffer-MaxNumLayers 0, i);
+brw-wm.base.surf_offset[surf_index] =
Extra whitespace at the end of this line.
+ brw-vtbl.update_renderbuffer_surface(
Re: [Mesa-dev] [PATCH 08/18] i965: Move tex miptree and format resolving into dispatcher
On Wed, Apr 22, 2015 at 1:47 PM, Topi Pohjolainen
topi.pohjolai...@intel.com wrote:
All hardware platforms have this in common, so do it in the
hardware independent dispatcher.
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 4 ++-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 30
---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 11 +++--
src/mesa/drivers/dri/i965/gen8_surface_state.c| 16 +++-
4 files changed, 30 insertions(+), 31 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 76d4630..096bc4d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -963,7 +963,9 @@ struct brw_context
struct
{
void (*update_texture_surface)(struct gl_context *ctx,
- unsigned unit,
+ const struct intel_mipmap_tree *mt,
+ struct gl_texture_object *tObj,
+ uint32_t tex_format,
uint32_t *surf_offset,
bool for_gather);
uint32_t (*update_renderbuffer_surface)(struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 0f739bb..d8faf82 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -309,23 +309,19 @@ update_buffer_texture_surface(struct gl_context *ctx,
static void
brw_update_texture_surface(struct gl_context *ctx,
- unsigned unit,
+ const struct intel_mipmap_tree *mt,
+ struct gl_texture_object *tObj,
+ uint32_t tex_format,
uint32_t *surf_offset,
bool for_gather)
{
struct brw_context *brw = brw_context(ctx);
- struct gl_texture_object *tObj = ctx-Texture.Unit[unit]._Current;
struct intel_texture_object *intelObj = intel_texture_object(tObj);
- struct intel_mipmap_tree *mt = intelObj-mt;
- struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
uint32_t *surf;
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
6 * 4, 32, surf_offset);
- uint32_t tex_format = translate_tex_format(brw, mt-format,
- sampler-sRGBDecode);
-
if (for_gather) {
/* Sandybridge's gather4 message is broken for integer formats.
* To work around this, we pretend the surface is UNORM for
@@ -796,14 +792,30 @@ update_texture_surface(struct gl_context *ctx,
bool for_gather)
{
struct brw_context *brw = brw_context(ctx);
- const struct gl_texture_object *tObj = ctx-Texture.Unit[unit]._Current;
+ struct gl_texture_object *tObj = ctx-Texture.Unit[unit]._Current;
+ struct intel_texture_object *intelObj = intel_texture_object(tObj);
+ const struct intel_mipmap_tree *mt = intelObj-mt;
+ const struct gl_texture_image *firstImage =
tObj-Image[0][tObj-BaseLevel];
+ const struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
if (tObj-Target == GL_TEXTURE_BUFFER) {
update_buffer_texture_surface(ctx, unit, surf_offset);
return;
}
- brw-vtbl.update_texture_surface(ctx, unit, surf_offset, for_gather);
+ mesa_format format = intelObj-_Format;
+ if (tObj-StencilSampling firstImage-_BaseFormat == GL_DEPTH_STENCIL)
{
+ assert(brw-gen = 8);
+ mt = mt-stencil_mt;
+ assert(mt-format == MESA_FORMAT_S_UINT8);
+ format = mt-format;
+ }
+
Extra whitespace on this line.
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Re: [Mesa-dev] i965: Batch emission refactoring
On Thu, Apr 23, 2015 at 11:56:31AM -0700, Matt Turner wrote: I've looked through all 18 patches, and they look fine to me -- but I'm not sure how much that's worth. I noted a bunch of whitespace mistakes (Is there a way to configure git commit to warn you about things like this?) but not much else. I don't know if that's because the series is perfect or if I don't know enough to actually do a meaningful review. Thanks for noticing the whitespace errors, I'll check my tools to warn me about them instead of bothering other people in the future. I feel comfortable giving an Acked-by: Matt Turner matts...@gmail.com for the first 17 patches. I wasn't sure about removing 'static' in 18. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] Fix 32bit compilation with -Werror=implicit-function-declaration
On Monday 13 April 2015 22:35:03 Pali Rohár wrote: On Monday 13 April 2015 22:32:10 Brian Paul wrote: On 04/13/2015 01:49 PM, Pali Rohár wrote: On Monday 13 April 2015 21:26:32 Pali Rohár wrote: File glapi_entrypoint.c calls memcpy() function, but does not include string.h header. So compilation can fail at error: implicit declaration of function 'memcpy'. --- src/mapi/glapi/glapi_entrypoint.c2015-04-13 21:11:09.0 +0200 +++ src/mapi/glapi/glapi_entrypoint.c2015-04-13 21:11:55.284118513 +0200 @@ -33,6 +33,7 @@ #include glapi/glapi_priv.h #include u_execmem.h +#include string.h #ifdef USE_X86_ASM This problem is caused by commit: https://urldefense.proofpoint.com/v2/url?u=http-3A__cgit.fre edesktop.org_mesa_mesa_commit_-3Fid-3D9fbbd60c1da4467683d935 40c64164ad337ce454d=AwIFaQc=Sqcl0Ez6M0X8aeM67LKIiDJAXVeAw- YihVMNtXt-uEsr=T0t4QG7chq2ZwJo6wilkFznRSFy-8uDKartPGbomVj8 m=cHbB4rMFT3az-q-Y6KO11a04PyYTYhOCPMZ3PAFmydss=lvCbo4YTBIN1 5kh-3Wu1-rQAsyFcdKtCE-Ywc4u_muge= which removes #include string.h from glapi_priv.h file. What configure or autogen.sh options did you use? I haven't seen this on any of my systems. -Brian If it helps here is full build log with error message: https://launchpadlibrarian.net/203127592/buildlog_ubuntu-precise-i386.mesa_10.6.0-git201504131208.36ceda4~ubuntu12.04.1_BUILDING.txt.gz Its compiled on Ubuntu 12.04 Precise box. Hello, this problem is still not fixed and compilation from git still failing... Please can you look at it and include missing string.h file? It is obvious problem in mesa and I also found which commit broke compilation... -- Pali Rohár pali.ro...@gmail.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] Fix 32bit compilation with -Werror=implicit-function-declaration
On 23/04/15 18:46, Pali Rohár wrote: On Monday 13 April 2015 22:35:03 Pali Rohár wrote: On Monday 13 April 2015 22:32:10 Brian Paul wrote: On 04/13/2015 01:49 PM, Pali Rohár wrote: On Monday 13 April 2015 21:26:32 Pali Rohár wrote: File glapi_entrypoint.c calls memcpy() function, but does not include string.h header. So compilation can fail at error: implicit declaration of function 'memcpy'. --- src/mapi/glapi/glapi_entrypoint.c 2015-04-13 21:11:09.0 +0200 +++ src/mapi/glapi/glapi_entrypoint.c 2015-04-13 21:11:55.284118513 +0200 @@ -33,6 +33,7 @@ #include glapi/glapi_priv.h #include u_execmem.h +#include string.h #ifdef USE_X86_ASM This problem is caused by commit: https://urldefense.proofpoint.com/v2/url?u=http-3A__cgit.fre edesktop.org_mesa_mesa_commit_-3Fid-3D9fbbd60c1da4467683d935 40c64164ad337ce454d=AwIFaQc=Sqcl0Ez6M0X8aeM67LKIiDJAXVeAw- YihVMNtXt-uEsr=T0t4QG7chq2ZwJo6wilkFznRSFy-8uDKartPGbomVj8 m=cHbB4rMFT3az-q-Y6KO11a04PyYTYhOCPMZ3PAFmydss=lvCbo4YTBIN1 5kh-3Wu1-rQAsyFcdKtCE-Ywc4u_muge= which removes #include string.h from glapi_priv.h file. What configure or autogen.sh options did you use? I haven't seen this on any of my systems. -Brian If it helps here is full build log with error message: https://urldefense.proofpoint.com/v2/url?u=https-3A__launchpadlibrarian.net_203127592_buildlog-5Fubuntu-2Dprecise-2Di386.mesa-5F10.6.0-2Dgit201504131208.36ceda4-7Eubuntu12.04.1-5FBUILDING.txt.gzd=AwIDaQc=Sqcl0Ez6M0X8aeM67LKIiDJAXVeAw-YihVMNtXt-uEsr=zfmBZnnVGHeYde45pMKNnVyzeaZbdIqVLprmZCM2zzEm=APogfpCq-vsnsGAuf6IWkOzXLZ4dY83aVZTYvsJsdtIs=6SlGiWJZZsOV1qK8l0vLE5nJaRUhJn0DTwSw2hQdbXAe= Its compiled on Ubuntu 12.04 Precise box. Hello, this problem is still not fixed and compilation from git still failing... Please can you look at it and include missing string.h file? It is obvious problem in mesa and I also found which commit broke compilation... I pushed your fix. Sorry for the delay. It wasn't intentional. There's so much traffic in Mesa, it's easy for things to fall through cracks. Jose ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 1/2] i965/debug: Use the ull specifier for DEBUG enum defines
The INTEL_DEBUG variable is a uint64_t and if we want a enum value higer than 32 bits, you need to use ull. We might as well use it for all of them. --- src/mesa/drivers/dri/i965/intel_debug.h | 62 - 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_debug.h b/src/mesa/drivers/dri/i965/intel_debug.h index 807ad98..a741a16 100644 --- a/src/mesa/drivers/dri/i965/intel_debug.h +++ b/src/mesa/drivers/dri/i965/intel_debug.h @@ -33,37 +33,37 @@ extern uint64_t INTEL_DEBUG; -#define DEBUG_TEXTURE (1 0) -#define DEBUG_STATE (1 1) -#define DEBUG_BLIT(1 2) -#define DEBUG_MIPTREE (1 3) -#define DEBUG_PERF(1 4) -#define DEBUG_PERFMON (1 5) -#define DEBUG_BATCH (1 6) -#define DEBUG_PIXEL (1 7) -#define DEBUG_BUFMGR (1 8) -#define DEBUG_FBO (1 9) -#define DEBUG_GS (1 10) -#define DEBUG_SYNC(1 11) -#define DEBUG_PRIMS (1 12) -#define DEBUG_VERTS (1 13) -#define DEBUG_DRI (1 14) -#define DEBUG_SF (1 15) -#define DEBUG_STATS (1 16) -#define DEBUG_WM (1 17) -#define DEBUG_URB (1 18) -#define DEBUG_VS (1 19) -#define DEBUG_CLIP(1 20) -#define DEBUG_AUB (1 21) -#define DEBUG_SHADER_TIME (1 22) -#define DEBUG_BLORP (1 23) -#define DEBUG_NO16(1 24) -#define DEBUG_VUE (1 25) -#define DEBUG_NO_DUAL_OBJECT_GS (1 26) -#define DEBUG_OPTIMIZER (1 27) -#define DEBUG_ANNOTATION (1 28) -#define DEBUG_NO8 (1 29) -#define DEBUG_VEC4VS (1 30) +#define DEBUG_TEXTURE (1ull 0) +#define DEBUG_STATE (1ull 1) +#define DEBUG_BLIT(1ull 2) +#define DEBUG_MIPTREE (1ull 3) +#define DEBUG_PERF(1ull 4) +#define DEBUG_PERFMON (1ull 5) +#define DEBUG_BATCH (1ull 6) +#define DEBUG_PIXEL (1ull 7) +#define DEBUG_BUFMGR (1ull 8) +#define DEBUG_FBO (1ull 9) +#define DEBUG_GS (1ull 10) +#define DEBUG_SYNC(1ull 11) +#define DEBUG_PRIMS (1ull 12) +#define DEBUG_VERTS (1ull 13) +#define DEBUG_DRI (1ull 14) +#define DEBUG_SF (1ull 15) +#define DEBUG_STATS (1ull 16) +#define DEBUG_WM (1ull 17) +#define DEBUG_URB (1ull 18) +#define DEBUG_VS (1ull 19) +#define DEBUG_CLIP(1ull 20) +#define DEBUG_AUB (1ull 21) +#define DEBUG_SHADER_TIME (1ull 22) +#define DEBUG_BLORP (1ull 23) +#define DEBUG_NO16(1ull 24) +#define DEBUG_VUE (1ull 25) +#define DEBUG_NO_DUAL_OBJECT_GS (1ull 26) +#define DEBUG_OPTIMIZER (1ull 27) +#define DEBUG_ANNOTATION (1ull 28) +#define DEBUG_NO8 (1ull 29) +#define DEBUG_VEC4VS (1ull 30) #ifdef HAVE_ANDROID_PLATFORM #define LOG_TAG INTEL-MESA -- 2.3.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 2/2] i965: Add an INTEL_DEBUG=spill option to test spilling
---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 2 +-
src/mesa/drivers/dri/i965/intel_debug.c | 1 +
src/mesa/drivers/dri/i965/intel_debug.h | 1 +
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index dc433b0..94e1a0a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -627,7 +627,7 @@ fs_visitor::assign_regs(bool allow_spilling)
}
/* Debug of register spilling: Go spill everything. */
- if (0) {
+ if (unlikely(INTEL_DEBUG DEBUG_SPILL)) {
int reg = choose_spill_reg(g);
if (reg != -1) {
diff --git a/src/mesa/drivers/dri/i965/intel_debug.c
b/src/mesa/drivers/dri/i965/intel_debug.c
index a5b883c..19be464 100644
--- a/src/mesa/drivers/dri/i965/intel_debug.c
+++ b/src/mesa/drivers/dri/i965/intel_debug.c
@@ -69,6 +69,7 @@ static const struct dri_debug_control debug_control[] = {
{ ann, DEBUG_ANNOTATION },
{ no8, DEBUG_NO8 },
{ vec4vs, DEBUG_VEC4VS },
+ { spill, DEBUG_SPILL },
{ NULL,0 }
};
diff --git a/src/mesa/drivers/dri/i965/intel_debug.h
b/src/mesa/drivers/dri/i965/intel_debug.h
index a741a16..e0e9cb7 100644
--- a/src/mesa/drivers/dri/i965/intel_debug.h
+++ b/src/mesa/drivers/dri/i965/intel_debug.h
@@ -64,6 +64,7 @@ extern uint64_t INTEL_DEBUG;
#define DEBUG_ANNOTATION (1ull 28)
#define DEBUG_NO8 (1ull 29)
#define DEBUG_VEC4VS (1ull 30)
+#define DEBUG_SPILL (1ull 31)
#ifdef HAVE_ANDROID_PLATFORM
#define LOG_TAG INTEL-MESA
--
2.3.5
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[Mesa-dev] [PATCH 06/16] i965/blorp: Prepare for attributes other than render position
Note that the magic number of one in gen7 logic is replaced by
BRW_SF_URB_ENTRY_READ_OFFSET ( == 1 also) for clarity.
On gen6 the change from zero to one (BRW_SF_URB_ENTRY_READ_OFFSET)
has no effect for native blorp as blorp doesn't use any
additional attributes. In fact, regular pipeline setup always
uses BRW_SF_URB_ENTRY_READ_OFFSET even when there are no additional
attributes. Hence the change makes the two (blorp and regular)
consistent.
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 5 +++--
src/mesa/drivers/dri/i965/brw_blorp.h| 3 ++-
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 5 +++--
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 6 --
4 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index b0de55d..0c0cd2b 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -155,14 +155,15 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t
*tile_x,
}
-brw_blorp_params::brw_blorp_params()
+brw_blorp_params::brw_blorp_params(unsigned num_varyings)
: x0(0),
y0(0),
x1(0),
y1(0),
depth_format(0),
hiz_op(GEN6_HIZ_OP_NONE),
- use_wm_prog(false)
+ use_wm_prog(false),
+ num_varyings(num_varyings)
{
color_write_disable[0] = false;
color_write_disable[1] = false;
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 5889f3e..a84b664 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -211,7 +211,7 @@ struct brw_blorp_prog_data
class brw_blorp_params
{
public:
- brw_blorp_params();
+ explicit brw_blorp_params(unsigned num_varyings = 0);
virtual uint32_t get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data) const = 0;
@@ -228,6 +228,7 @@ public:
bool use_wm_prog;
brw_blorp_wm_push_constants wm_push_consts;
bool color_write_disable[4];
+ const unsigned num_varyings;
};
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 9b54b93..2954750 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -634,9 +634,10 @@ gen6_blorp_emit_sf_config(struct brw_context *brw,
{
BEGIN_BATCH(20);
OUT_BATCH(_3DSTATE_SF 16 | (20 - 2));
- OUT_BATCH((1 - 1) GEN6_SF_NUM_OUTPUTS_SHIFT | /* only position */
+ OUT_BATCH(params-num_varyings GEN6_SF_NUM_OUTPUTS_SHIFT |
1 GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
- 0 GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT);
+ BRW_SF_URB_ENTRY_READ_OFFSET
+GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT);
OUT_BATCH(0); /* dw2 */
OUT_BATCH(params-dst.num_samples 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
for (int i = 0; i 16; ++i)
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 12f515d..3065a4c 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -415,9 +415,11 @@ gen7_blorp_emit_sf_config(struct brw_context *brw,
{
BEGIN_BATCH(14);
OUT_BATCH(_3DSTATE_SBE 16 | (14 - 2));
- OUT_BATCH((1 - 1) GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
+ OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE |
+params-num_varyings GEN7_SBE_NUM_OUTPUTS_SHIFT |
1 GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
-0 GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
+BRW_SF_URB_ENTRY_READ_OFFSET
+ GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
for (int i = 0; i 12; ++i)
OUT_BATCH(0);
ADVANCE_BATCH();
--
1.9.3
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[Mesa-dev] i965: Blorp state setup refactors
This series introduces virtual member functions for blorp parameters that know how certain part of the batch is to be programmed for the shader in question. This will be taken advantage of later on when I add support for launching glsl-based programs. Topi Pohjolainen (16): i965/blorp: Remove constant parameter i965/blorp: Refactor vertex buffer state setup i965/blorp: Allow caller to provide sampler settings i965/gen7/blorp: Remove unused arguments i965/blorp: Remove unused arguments i965/blorp: Prepare for attributes other than render position i965/blorp: Allow blend state to be set for multiple render targets i965/blorp: Add support for layered rendering i965/blorp: Prepare drawing rectangle for flipped coordinates i965/blorp: Use virtual function for wm/ps configuration i965/blorp: Move push const setup for the parameter type to handle i965/blorp: Move sampler setup for the parameter type to handle i965/blorp/gen6: Move surface setup for the parameter type to handle i965/blorp/gen7: Move surface setup for the parameter type to handle i965/blorp: Move vertex uploading for parameter type to handle i965/blorp: Move multisample setup for parameter type to handle src/mesa/drivers/dri/i965/brw_blorp.cpp | 23 +-- src/mesa/drivers/dri/i965/brw_blorp.h| 73 --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 13 +- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 273 --- src/mesa/drivers/dri/i965/gen6_blorp.h | 2 +- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 204 +--- src/mesa/drivers/dri/i965/gen7_blorp.h | 2 +- 7 files changed, 316 insertions(+), 274 deletions(-) -- 1.9.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/7] i965: Add all surface types to the batch decode
On Thu, Apr 23, 2015 at 4:49 PM, Ben Widawsky
benjamin.widaw...@intel.com wrote:
It's true that not all surfaces apply for every gen, but for the most part
this
is what we want. (The unfortunate case is when we use an valid surface, but
not
for the specific GEN).
This was automated with a vim macro.
v2: Shortened common forms such as R8G8B8A8-RGBA8. Note that this makes some
of
the sample output in subsequent commits slightly incorrect.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_state_dump.c | 226
-
1 file changed, 219 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c
b/src/mesa/drivers/dri/i965/brw_state_dump.c
index 5cf70eb..a688ba3 100644
--- a/src/mesa/drivers/dri/i965/brw_state_dump.c
+++ b/src/mesa/drivers/dri/i965/brw_state_dump.c
@@ -67,13 +67,225 @@ get_965_surfacetype(unsigned int surfacetype)
static const char *
get_965_surface_format(unsigned int surface_format)
{
-switch (surface_format) {
-case 0x000: return r32g32b32a32_float;
-case 0x0c1: return b8g8r8a8_unorm;
-case 0x100: return b5g6r5_unorm;
-case 0x102: return b5g5r5a1_unorm;
-case 0x104: return b4g4r4a4_unorm;
-default: return unknown;
+ switch (surface_format) {
+ case BRW_SURFACEFORMAT_R32G32B32A32_FLOAT: return RGBA32_FLOAT;
We don't indent case.
(Would this work better as a table?)
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Re: [Mesa-dev] [PATCH V2 02/22] i965: Choose tiling in brw_miptree_layout() function
On Fri, Apr 17, 2015 at 04:51:23PM -0700, Anuj Phogat wrote:
This refactoring is required by later patches in this series.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 19 +++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 31
++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 19 ++--
3 files changed, 51 insertions(+), 18 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 7a1e09d..b8408d3 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -378,7 +378,13 @@ brw_miptree_layout_texture_3d(struct brw_context *brw,
}
void
-brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt)
+brw_miptree_layout(struct brw_context *brw,
+ mesa_format format,
+ uint32_t width0,
+ uint32_t num_samples,
+ bool for_bo,
+ enum intel_miptree_tiling_mode requested,
+ struct intel_mipmap_tree *mt)
{
bool multisampled = mt-num_samples 1;
Doesn't given num_samples equal to mt-num_samples, width0 equal to
mt-logical_width0 and format equal to mt-format at this point?
bool gen6_hiz_or_stencil = false;
@@ -461,5 +467,16 @@ brw_miptree_layout(struct brw_context *brw, struct
intel_mipmap_tree *mt)
}
DBG(%s: %dx%dx%d\n, __FUNCTION__,
mt-total_width, mt-total_height, mt-cpp);
+
+/* pitch == 0 || height == 0 indicates the null texture */
+ if (!mt || !mt-total_width || !mt-total_height) {
+ intel_miptree_release(mt);
+ return;
+ }
+
+ if (!for_bo)
+ mt-tiling = intel_miptree_choose_tiling(brw, format, width0,
+ num_samples,
+ requested, mt);
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index eb226d5..7a64282 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -232,6 +232,7 @@ intel_miptree_create_layout(struct brw_context *brw,
GLuint depth0,
bool for_bo,
GLuint num_samples,
+enum intel_miptree_tiling_mode requested,
bool force_all_slices_at_each_lod)
{
struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
@@ -432,7 +433,7 @@ intel_miptree_create_layout(struct brw_context *brw,
if (force_all_slices_at_each_lod)
mt-array_layout = ALL_SLICES_AT_EACH_LOD;
- brw_miptree_layout(brw, mt);
+ brw_miptree_layout(brw, format, width0, num_samples, for_bo, requested,
mt);
return mt;
}
@@ -440,7 +441,7 @@ intel_miptree_create_layout(struct brw_context *brw,
/**
* \brief Helper function for intel_miptree_create().
*/
-static uint32_t
+uint32_t
intel_miptree_choose_tiling(struct brw_context *brw,
mesa_format format,
uint32_t width0,
@@ -609,14 +610,11 @@ intel_miptree_create(struct brw_context *brw,
first_level, last_level, width0,
height0, depth0,
false, num_samples,
+requested_tiling,
Just as Matt instructed me, you could fix tabs here in the argument list.
force_all_slices_at_each_lod);
- /*
-* pitch == 0 || height == 0 indicates the null texture
-*/
- if (!mt || !mt-total_width || !mt-total_height) {
- intel_miptree_release(mt);
+
+ if (!mt)
return NULL;
- }
total_width = mt-total_width;
total_height = mt-total_height;
@@ -627,16 +625,11 @@ intel_miptree_create(struct brw_context *brw,
total_height = ALIGN(total_height, 64);
}
- uint32_t tiling = intel_miptree_choose_tiling(brw, format, width0,
- num_samples,
requested_tiling,
- mt);
bool y_or_x = false;
- if (tiling == (I915_TILING_Y | I915_TILING_X)) {
+ if (mt-tiling == (I915_TILING_Y | I915_TILING_X)) {
y_or_x = true;
mt-tiling = I915_TILING_Y;
- } else {
- mt-tiling = tiling;
}
unsigned long pitch;
@@ -721,10 +714,18 @@ intel_miptree_create_for_bo(struct brw_context *brw,
target = depth 1 ? GL_TEXTURE_2D_ARRAY : GL_TEXTURE_2D;
+ /* 'requested' parameter of intel_miptree_create_layout() is relevant
+* only for non bo miptree. Tiling for bo is already computed above.
+* So, the tiling requested (INTEL_MIPTREE_TILING_ANY)
Re: [Mesa-dev] [PATCH v2 1/2] i965/debug: Use the ull specifier for DEBUG enum defines
Both are Reviewed-by: Matt Turner matts...@gmail.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH V2 06/22] i965/gen9: Set tiled resource mode for the miptree
On Fri, Apr 17, 2015 at 04:51:27PM -0700, Anuj Phogat wrote:
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 2 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 ++
2 files changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 68c6634..19ff5b8 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -540,6 +540,8 @@ brw_miptree_layout(struct brw_context *brw,
{
bool gen6_hiz_or_stencil = false;
+ mt-tr_mode = INTEL_MIPTREE_TRMODE_NONE;
+
if (brw-gen == 6 mt-array_layout == ALL_SLICES_AT_EACH_LOD) {
const GLenum base_format = _mesa_get_format_base_format(mt-format);
gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index b03ffe7..2669817 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -338,6 +338,7 @@ struct intel_mipmap_tree
uint32_t pitch; /** pitch in bytes. */
uint32_t tiling; /** One of the I915_TILING_* flags */
+ uint32_t tr_mode; /** One of the INTEL_MIPTREE_TRMODE_* flags */
/* Effectively the key:
*/
@@ -503,6 +504,11 @@ enum intel_miptree_tiling_mode {
INTEL_MIPTREE_TILING_NONE,
};
+/* Tile resource modes */
+#define INTEL_MIPTREE_TRMODE_NONE0
+#define INTEL_MIPTREE_TRMODE_YF 1
+#define INTEL_MIPTREE_TRMODE_YS 2
+
I think we can use an enum here. We don't do that for tiling but those
are readily shifted values to go into batches. These values here are
instead used only by software to make runtime decisions. Enumeration
gives us compiler warning support and debugger giving the human readable
value instead of just number.
With that:
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
bool
intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
struct intel_mipmap_tree *mt);
--
2.3.4
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Re: [Mesa-dev] [PATCH] gallium/radeon: don't crash when getting out-of-bounds TEMP references
On Sat, Apr 11, 2015 at 09:11:13PM +0200, Marek Olšák wrote:
From: Marek Olšák marek.ol...@amd.com
Reviewed-by: Tom Stellard thomas.stell...@amd.com
---
src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 1690194..333f7ae 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -191,6 +191,8 @@ emit_fetch(
break;
case TGSI_FILE_TEMPORARY:
+ if (reg-Register.Index = ctx-temps_count)
+ return LLVMGetUndef(tgsi2llvmtype(bld_base, type));
if (uses_temp_indirect_addressing(bld_base)) {
ptr = lp_get_temp_ptr_soa(bld, reg-Register.Index,
swizzle);
break;
@@ -395,6 +397,8 @@ emit_store(
break;
case TGSI_FILE_TEMPORARY:
+ if (range.First + i = ctx-temps_count)
+ continue;
if
(uses_temp_indirect_addressing(bld_base))
temp_ptr =
lp_get_temp_ptr_soa(bld, i + range.First, chan_index);
else
@@ -416,6 +420,8 @@ emit_store(
break;
case TGSI_FILE_TEMPORARY:
+ if (reg-Register.Index = ctx-temps_count)
+ continue;
if (uses_temp_indirect_addressing(bld_base)) {
temp_ptr = NULL;
break;
--
2.1.0
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Re: [Mesa-dev] Initial amdgpu driver release
On 21/04/15 16:41, Alex Deucher wrote: On Tue, Apr 21, 2015 at 11:56 AM, Emil Velikov emil.l.veli...@gmail.com wrote: Hi Alex, On 20 April 2015 at 23:33, Alex Deucher alexdeuc...@gmail.com wrote: I'm pleased to announce the initial release of the new amdgpu driver. This is a partial replacement for the radeon driver for newer AMD asics. A number of components are still shared. Here is a comparison of the radeon and amdgpu stacks: 1. radeon stack kernel driver: radeon.ko libdrm: libdrm_radeon mesa: radeon, r200, r300, r600, radeonsi ddx: xf86-video-ati 2. amdgpu stack kernel driver: amdgpu.ko libdrm: libdrm_amdgpu mesa: radeonsi ddx: xf86-video-amdgpu Older asics will continue to be supported by the radeon stack; new asics will be supported by the amdgpu stack. CI (Sea Islands) asics have support in both driver stacks, but this is purely for testing purposes. CI parts are officially supported in the radeon stack. Support for CI on the amdgpu stack is determined by a config option in the kernel. CI support is not enabled by default for amdgpu. Most of our focus has been on Carrizo support, so there are some gaps in the dGPU support for Tonga and Iceland, notably power management. Those gaps will be filled in eventually. Also included in this code base are full register headers for just about every block on the asics. Barring the gaps mentioned above, the driver stack is functionally on par with radeon including: - OpenGL 3.3 support using the radeonsi mesa driver - Video decode support using UVD - Video encode support using VCE The code can be found in the amdgpu branches of the following git trees. xf86-video-amdgpu: http://cgit.freedesktop.org/~agd5f/xf86-video-amdgpu/log/?h=amdgpu libdrm: http://cgit.freedesktop.org/~agd5f/drm/log/?h=amdgpu kernel: http://cgit.freedesktop.org/~agd5f/linux/log/?h=amdgpu mesa: http://cgit.freedesktop.org/~mareko/mesa/log/?h=amdgpu To test the new driver stack you will need to specify a device section in your xorg.conf with the driver set to amdgpu rather than radeon. Please review! Do you plan to sending out the libdrm patches to the ML ? I have a few comments that you might be interested in :-) Yeah, just sent them out now. Ran out of time last night. Some of the patches in the kernel and the ddx patch are really big so probably too big for the ML. Fair enough, did not mean to come out as impatient - was the first thing that pope at my email client after a short break. Just a random question on the ddx front - do you see many benefits of supporting old xservers ? If you target xserver 1.16 and later you can drop a fair bit of code/wrappers - Non DRI2 enabled xserver. - HAS_DEVPRIVATEKEYREC (new with 1.10, released 4+ years ago) - xorg-list (new with 1.12, released 3+ years ago) - DRI2_PRIME (new with 1.13, released 2+ years ago) - AMDGPU_PIXMAP_SHARING (XF86_CRTC_VERSION = 5, new with 1.13) - Support for external the glamor library (new with 1.16) While you're there you might want to drop support for xextproto pre 7.1. 7.1.0 was released 6+ years ago. The README and .gitignore mention xf86-video-ati. Hope you find any of the above useful :) -Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] mesa: refactor active attrib queries for glGetProgramiv
Main motivation here is to get rid of iterating IR and
encapsulate queries within program resources.
No functional changes.
Piglit tests calling the modified functionality:
- gl-get-active-attrib-returns-all-inputs
- glsl-1.50-get-active-attrib-array
- getactiveattrib
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
---
src/mesa/main/shader_query.cpp | 39 ++-
1 file changed, 14 insertions(+), 25 deletions(-)
diff --git a/src/mesa/main/shader_query.cpp b/src/mesa/main/shader_query.cpp
index bc6fec5..e047b09 100644
--- a/src/mesa/main/shader_query.cpp
+++ b/src/mesa/main/shader_query.cpp
@@ -291,7 +291,6 @@ _mesa_GetAttribLocation(GLhandleARB program, const
GLcharARB * name)
return (loc = 0) ? loc : -1;
}
-
unsigned
_mesa_count_active_attribs(struct gl_shader_program *shProg)
{
@@ -300,19 +299,13 @@ _mesa_count_active_attribs(struct gl_shader_program
*shProg)
return 0;
}
- exec_list *const ir = shProg-_LinkedShaders[MESA_SHADER_VERTEX]-ir;
- unsigned i = 0;
-
- foreach_in_list(ir_instruction, node, ir) {
- const ir_variable *const var = node-as_variable();
-
- if (!is_active_attrib(var))
- continue;
-
- i++;
+ struct gl_program_resource *res = shProg-ProgramResourceList;
+ unsigned count = 0;
+ for (unsigned j = 0; j shProg-NumProgramResourceList; j++, res++) {
+ if (is_active_attrib(RESOURCE_VAR(res)))
+count++;
}
-
- return i;
+ return count;
}
@@ -324,20 +317,16 @@ _mesa_longest_attribute_name_length(struct
gl_shader_program *shProg)
return 0;
}
- exec_list *const ir = shProg-_LinkedShaders[MESA_SHADER_VERTEX]-ir;
+ struct gl_program_resource *res = shProg-ProgramResourceList;
size_t longest = 0;
+ for (unsigned j = 0; j shProg-NumProgramResourceList; j++, res++) {
+ if (res-Type == GL_PROGRAM_INPUT
+ res-StageReferences (1 MESA_SHADER_VERTEX)) {
- foreach_in_list(ir_instruction, node, ir) {
- const ir_variable *const var = node-as_variable();
-
- if (var == NULL
- || var-data.mode != ir_var_shader_in
- || var-data.location == -1)
-continue;
-
- const size_t len = strlen(var-name);
- if (len = longest)
-longest = len + 1;
+ const size_t length = strlen(RESOURCE_VAR(res)-name);
+ if (length longest)
+ longest = length + 1;
+ }
}
return longest;
--
2.1.0
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Re: [Mesa-dev] [RFC PATCH 1/2] glsl: Transform pow(x, 4) into (x*x)*(x*x).
On 22.04.2015 20:14, Matt Turner wrote: On Fri, Apr 17, 2015 at 1:56 PM, Matt Turner matts...@gmail.com wrote: Updated numbers look a lot better! On Tue, Mar 17, 2015 at 4:23 PM, Matt Turner matts...@gmail.com wrote: Without NIR: total instructions in shared programs: 6190374 - 6190153 (-0.00%) instructions in affected programs: 61126 - 60905 (-0.36%) helped:156 total instructions in shared programs: 6191351 - 6191130 (-0.00%) instructions in affected programs: 61032 - 60811 (-0.36%) helped:156 With NIR: total instructions in shared programs: 6271584 - 6271471 (-0.00%) instructions in affected programs: 47656 - 47543 (-0.24%) helped:113 GAINED:4 LOST: 41 total instructions in shared programs: 6099580 - 6099443 (-0.00%) instructions in affected programs: 47526 - 47389 (-0.29%) helped:137 Ping. Patch look ok to me. Reviewed-by: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] draw: fix prim ids when there's no gs
On 23/04/15 00:06, srol...@vmware.com wrote:
From: Roland Scheidegger srol...@vmware.com
We were resetting the prim id count for each run of the prim assembler,
hence this only worked when the draw calls were very small (the exact limit
depending on the vertex size), since larger draw calls get split up.
So, do the same as we do already if there's a gs, reset it to zero explicitly
for every new instance (this possibly could use the same variable but that
isn't doable without some heavy refactoring and I'm not sure it makes sense).
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=90130.
---
src/gallium/auxiliary/draw/draw_context.c| 1 +
src/gallium/auxiliary/draw/draw_prim_assembler.c | 13 +++--
src/gallium/auxiliary/draw/draw_prim_assembler.h | 3 +++
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/src/gallium/auxiliary/draw/draw_context.c
b/src/gallium/auxiliary/draw/draw_context.c
index 04cf5b7..ee009c1 100644
--- a/src/gallium/auxiliary/draw/draw_context.c
+++ b/src/gallium/auxiliary/draw/draw_context.c
@@ -182,6 +182,7 @@ boolean draw_init(struct draw_context *draw)
void draw_new_instance(struct draw_context *draw)
{
draw_geometry_shader_new_instance(draw-gs.geometry_shader);
+ draw_prim_assembler_new_instance(draw-ia);
}
diff --git a/src/gallium/auxiliary/draw/draw_prim_assembler.c
b/src/gallium/auxiliary/draw/draw_prim_assembler.c
index 776c172..7ff705a 100644
--- a/src/gallium/auxiliary/draw/draw_prim_assembler.c
+++ b/src/gallium/auxiliary/draw/draw_prim_assembler.c
@@ -189,7 +189,6 @@ draw_prim_assembler_prepare_outputs(struct draw_assembler
*ia)
} else {
ia-primid_slot = -1;
}
- ia-primid = 0;
}
@@ -233,7 +232,6 @@ draw_prim_assembler_run(struct draw_context *draw,
asmblr-input_prims = input_prims;
asmblr-input_verts = input_verts;
asmblr-needs_primid = needs_primid(asmblr-draw);
- asmblr-primid = 0;
asmblr-num_prims = 0;
output_prims-linear = TRUE;
@@ -284,3 +282,14 @@ draw_prim_assembler_destroy(struct draw_assembler *ia)
{
FREE(ia);
}
+
+
+/*
+ * Called at the very begin of the draw call with a new instance
+ * Used to reset state that should persist between primitive restart.
+ */
+void
+draw_prim_assembler_new_instance(struct draw_assembler *asmblr)
+{
+ asmblr-primid = 0;
+}
diff --git a/src/gallium/auxiliary/draw/draw_prim_assembler.h
b/src/gallium/auxiliary/draw/draw_prim_assembler.h
index 5ba715b..5ee7317 100644
--- a/src/gallium/auxiliary/draw/draw_prim_assembler.h
+++ b/src/gallium/auxiliary/draw/draw_prim_assembler.h
@@ -70,5 +70,8 @@ draw_prim_assembler_run(struct draw_context *draw,
void
draw_prim_assembler_prepare_outputs(struct draw_assembler *ia);
+void
+draw_prim_assembler_new_instance(struct draw_assembler *ia);
+
#endif
Looks good to me.
Reviewed-by: Jose Fonseca jfons...@vmware.com
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[Mesa-dev] New stable-branch 10.5 candidate pushed
Hello list,
The candidate for the Mesa 10.5.4 is now available. The current patch queue
is as follows:
- 22 queued
- 7 nominated (outstanding)
- and 1 rejected (obsolete) patches
This time around we have a handful of fixes in st/mesa and the glsl to tgsi
codebase, affecting all gallium drivers, a drirc workaround for Second Life,
plus i965 fixes. For the Android users out there, this resolves most of the
compilation issues with a bit more to come in the next release.
Take a look at section Mesa stable queue for more information.
Testing
---
The following results are against piglit 305ecc3ac89.
Changes - classic i965(snb)
---
None.
Changes - swrast classic
None.
Changes - gallium softpipe, llvmpipe (LLVM 3.6)
---
None.
Testing reports/general approval
Any testing reports (or general approval of the state of the branch)
will be greatly appreciated.
Trivial merge conflicts
---
None.
The plan is to have 10.5.4 this Friday(24th April).
If you have any questions or comments that you would like to share
before the release, please go ahead.
Cheers,
Emil
Mesa stable queue
-
Nominated (7)
=
Boyan Ding (2):
i965: Add XRGB format to intel_screen_make_configs
i915: Add XRGB format to intel_screen_make_configs
Brian Paul (1):
configure: don't try to build gallium DRI drivers if --disable-dri is set
Emil Velikov (1):
r300: do not link against libdrm_intel
Kenneth Graunke (2):
i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.
i965: Disallow linear blits that are not cacheline aligned.
Tom Stellard (1):
clover: Update the wait_count of the correct event when chaining events
Rejected/Obsolete (1)
=
Tom Stellard (1):
clover: Update the wait_count of the correct event when chaining events
Queued (22)
===
Brian Paul (1):
glsl: rewrite glsl_type::record_key_hash() to avoid buffer overflow
Dave Airlie (2):
st/mesa: convert sub image for cube map arrays to 2d arrays for upload
st/mesa: align cube map arrays layers
Emil Velikov (10):
docs: Add 256 sums for the 10.5.3 release
radeonsi: remove unused si_dump_key()
android: use LOCAL_SHARED_LIBRARIES over TARGET_OUT_HEADERS
android: add $(mesa_top)/src include to the whole of mesa
android: egl: add libsync_cflags to the build
android: dri/common: conditionally include drm_cflags/set __NOT_HAVE_DRM_H
android: add HAVE__BUILTIN_* and HAVE_FUNC_ATTRIBUTE_* defines
android: add $(mesa_top)/src/mesa/main to the includes list
android: dri: link against libmesa_util
android: mesa: fix the path of the SSE4_1 optimisations
Ian Romanick (1):
nir: Fix typo in ushr by 0 algebraic replacement
Kenneth Graunke (2):
i965: Fix software primitive restart with indirect draws.
drirc: Add Second Life quirk (allow_glsl_extension_directive_midshader).
Kristian Høgsberg (1):
i965: Rewrite ir_tex to ir_txl with lod 0 for vertex shaders
Marek Olšák (2):
glsl_to_tgsi: fix out-of-bounds constant access and crash for uniforms
glsl_to_tgsi: don't use a potentially-undefined immediate for
ir_query_levels
Mathias Froehlich (1):
i965: Flush batchbuffer containing the query on glQueryCounter.
Mauro Rossi (2):
android: mesa: generate the format_{un,}pack.[ch] sources
android: add inital NIR build
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Re: [Mesa-dev] [Mesa-stable] [PATCH] clover: Call clBuildProgram() notification function when build completes
Emil Velikov emil.l.veli...@gmail.com writes:
Humble ping.
This patch is obsolete. IIRC Tom sent a v2 to which I replied with some
(mostly trivial) suggestions. There's no v3 yet AFAIK.
-Emil
On 08/04/15 18:34, Emil Velikov wrote:
Hi Tom,
Just a friendly reminder that this patch hasn't landed in master yet.
Just making sure it doesn't fall through the cracks :-)
Cheers
Emil
On 24 March 2015 at 19:44, Tom Stellard thomas.stell...@amd.com wrote:
Cc: 10.5 10.4 mesa-sta...@lists.freedesktop.org
---
src/gallium/state_trackers/clover/api/program.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/src/gallium/state_trackers/clover/api/program.cpp
b/src/gallium/state_trackers/clover/api/program.cpp
index 60184ed..fcec1d7 100644
--- a/src/gallium/state_trackers/clover/api/program.cpp
+++ b/src/gallium/state_trackers/clover/api/program.cpp
@@ -180,8 +180,12 @@ clBuildProgram(cl_program d_prog, cl_uint num_devs,
validate_build_program_common(prog, num_devs, d_devs, pfn_notify,
user_data);
prog.build(devs, opts);
+ if (pfn_notify)
+ pfn_notify(d_prog, user_data);
return CL_SUCCESS;
} catch (error e) {
+ if (pfn_notify)
+ pfn_notify(d_prog, user_data);
if (e.get() == CL_INVALID_COMPILER_OPTIONS)
return CL_INVALID_BUILD_OPTIONS;
if (e.get() == CL_COMPILE_PROGRAM_FAILURE)
--
2.0.4
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Re: [Mesa-dev] [PATCH] mesa: fix glGetActiveUniformsiv regression
On Thu, Apr 23, 2015 at 7:34 AM, Martin Peres
martin.pe...@linux.intel.com wrote:
On 23/04/15 14:19, Tapani Pälli wrote:
Commit 7519ddb caused regression to glGetActiveUniformsiv.
Patch adds back validation loop of all given uniforms before
writing any values, not touching params in case of errors
is tested by the conformance suite.
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90149
Not good for performance, but this is not too sensitive and we are just
following the spec.
If you cared about performance, you could store the results from the
first loop and use them in the second one. Either with a malloc or
alloca, but that's not the end of the world.
Reviewed-by: Martin Peres martin.pe...@linux.intel.com
---
src/mesa/main/uniform_query.cpp | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/uniform_query.cpp
b/src/mesa/main/uniform_query.cpp
index 4e77b32..3e857ed 100644
--- a/src/mesa/main/uniform_query.cpp
+++ b/src/mesa/main/uniform_query.cpp
@@ -129,14 +129,26 @@ _mesa_GetActiveUniformsiv(GLuint program,
res_prop = resource_prop_from_uniform_prop(pname);
+ /* We need to first verify that each entry exists as active uniform.
If
+* not, generate error and do not cause any other side effects.
+*
+* In the case of and error condition, Page 16 (section 2.3.1 Errors)
+* of the OpenGL 4.5 spec says:
+*
+* If the generating command modifies values through a pointer
argu-
+* ment, no change is made to these values.
+*/
for (int i = 0; i uniformCount; i++) {
- res = _mesa_program_resource_find_index(shProg, GL_UNIFORM,
- uniformIndices[i]);
- if (!res) {
+ if (!_mesa_program_resource_find_index(shProg, GL_UNIFORM,
+ uniformIndices[i])) {
_mesa_error(ctx, GL_INVALID_VALUE,
glGetActiveUniformsiv(index));
- break;
+ return;
}
+ }
+ for (int i = 0; i uniformCount; i++) {
+ res = _mesa_program_resource_find_index(shProg, GL_UNIFORM,
+ uniformIndices[i]);
if (!_mesa_program_resource_prop(shProg, res, uniformIndices[i],
res_prop, params[i],
glGetActiveUniformsiv))
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Re: [Mesa-dev] New stable-branch 10.5 candidate pushed
Hi, On 23 April 2015 at 14:12, Emil Velikov emil.l.veli...@gmail.com wrote: Boyan Ding (2): i965: Add XRGB format to intel_screen_make_configs i915: Add XRGB format to intel_screen_make_configs This fixes https://bugs.freedesktop.org/show_bug.cgi?id=89689 but re-breaks ES3 MSAA by reverting http://cgit.freedesktop.org/mesa/mesa/commit/?id=75b7e1df13. What a mess ... Ian - did you see the TRANSPARENT_ALPHA thread? Cheers, Daniel ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] mesa: fix glGetActiveUniformsiv regression
Commit 7519ddb caused regression to glGetActiveUniformsiv.
Patch adds back validation loop of all given uniforms before
writing any values, not touching params in case of errors
is tested by the conformance suite.
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90149
---
src/mesa/main/uniform_query.cpp | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
index 4e77b32..3e857ed 100644
--- a/src/mesa/main/uniform_query.cpp
+++ b/src/mesa/main/uniform_query.cpp
@@ -129,14 +129,26 @@ _mesa_GetActiveUniformsiv(GLuint program,
res_prop = resource_prop_from_uniform_prop(pname);
+ /* We need to first verify that each entry exists as active uniform. If
+* not, generate error and do not cause any other side effects.
+*
+* In the case of and error condition, Page 16 (section 2.3.1 Errors)
+* of the OpenGL 4.5 spec says:
+*
+* If the generating command modifies values through a pointer argu-
+* ment, no change is made to these values.
+*/
for (int i = 0; i uniformCount; i++) {
- res = _mesa_program_resource_find_index(shProg, GL_UNIFORM,
- uniformIndices[i]);
- if (!res) {
+ if (!_mesa_program_resource_find_index(shProg, GL_UNIFORM,
+ uniformIndices[i])) {
_mesa_error(ctx, GL_INVALID_VALUE, glGetActiveUniformsiv(index));
- break;
+ return;
}
+ }
+ for (int i = 0; i uniformCount; i++) {
+ res = _mesa_program_resource_find_index(shProg, GL_UNIFORM,
+ uniformIndices[i]);
if (!_mesa_program_resource_prop(shProg, res, uniformIndices[i],
res_prop, params[i],
glGetActiveUniformsiv))
--
2.1.0
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Re: [Mesa-dev] [PATCH] mesa: refactor active attrib queries for glGetProgramiv
On 23/04/15 11:13, Tapani Pälli wrote:
Main motivation here is to get rid of iterating IR and
encapsulate queries within program resources.
No functional changes.
Piglit tests calling the modified functionality:
- gl-get-active-attrib-returns-all-inputs
- glsl-1.50-get-active-attrib-array
- getactiveattrib
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
---
src/mesa/main/shader_query.cpp | 39 ++-
1 file changed, 14 insertions(+), 25 deletions(-)
diff --git a/src/mesa/main/shader_query.cpp b/src/mesa/main/shader_query.cpp
index bc6fec5..e047b09 100644
--- a/src/mesa/main/shader_query.cpp
+++ b/src/mesa/main/shader_query.cpp
@@ -291,7 +291,6 @@ _mesa_GetAttribLocation(GLhandleARB program, const
GLcharARB * name)
return (loc = 0) ? loc : -1;
}
-
unsigned
_mesa_count_active_attribs(struct gl_shader_program *shProg)
{
@@ -300,19 +299,13 @@ _mesa_count_active_attribs(struct gl_shader_program
*shProg)
return 0;
}
- exec_list *const ir = shProg-_LinkedShaders[MESA_SHADER_VERTEX]-ir;
- unsigned i = 0;
-
- foreach_in_list(ir_instruction, node, ir) {
- const ir_variable *const var = node-as_variable();
-
- if (!is_active_attrib(var))
- continue;
-
- i++;
+ struct gl_program_resource *res = shProg-ProgramResourceList;
+ unsigned count = 0;
+ for (unsigned j = 0; j shProg-NumProgramResourceList; j++, res++) {
+ if (is_active_attrib(RESOURCE_VAR(res)))
+count++;
}
-
- return i;
+ return count;
}
@@ -324,20 +317,16 @@ _mesa_longest_attribute_name_length(struct gl_shader_program *shProg)
return 0;
}
- exec_list *const ir = shProg-_LinkedShaders[MESA_SHADER_VERTEX]-ir;
+ struct gl_program_resource *res = shProg-ProgramResourceList;
size_t longest = 0;
+ for (unsigned j = 0; j shProg-NumProgramResourceList; j++, res++) {
+ if (res-Type == GL_PROGRAM_INPUT
+ res-StageReferences (1 MESA_SHADER_VERTEX)) {
- foreach_in_list(ir_instruction, node, ir) {
- const ir_variable *const var = node-as_variable();
-
- if (var == NULL
- || var-data.mode != ir_var_shader_in
- || var-data.location == -1)
-continue;
-
- const size_t len = strlen(var-name);
- if (len = longest)
-longest = len + 1;
+ const size_t length = strlen(RESOURCE_VAR(res)-name);
+ if (length longest)
The condition above is wrong, it should be length = longest like the
original hunk.
Other than that, it looks like a nice refactoring.
Reviewed-by: Martin Peres martin.pe...@linux.intel.com
+ longest = length + 1;
+ }
}
return longest;
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Re: [Mesa-dev] [PATCH 03/14] i965: Add helper functions to calculate the slice pitch of an array or 3D miptree.
I'm going to push patches 3 to 5 from this old series in 48h, they're
too much effort to keep up to date.
Francisco Jerez curroje...@riseup.net writes:
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 45
+--
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 18 +++
2 files changed, 53 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 0e2841f..2bc718b 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -227,6 +227,39 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
}
}
+unsigned
+brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt,
+ unsigned level)
+{
+ if (mt-target == GL_TEXTURE_3D ||
+ (brw-gen == 4 mt-target == GL_TEXTURE_CUBE_MAP)) {
+ return ALIGN(minify(mt-physical_width0, level), mt-align_w);
+ } else {
+ return 0;
+ }
+}
+
+unsigned
+brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt,
+ unsigned level)
+{
+ if (mt-target == GL_TEXTURE_3D ||
+ (brw-gen == 4 mt-target == GL_TEXTURE_CUBE_MAP)) {
+ return ALIGN(minify(mt-physical_height0, level), mt-align_h);
+
+ } else {
+ const unsigned h0 = ALIGN(mt-physical_height0, mt-align_h);
+ const unsigned h1 = ALIGN(minify(mt-physical_height0, 1),
mt-align_h);
+
+ if (mt-array_layout == ALL_SLICES_AT_EACH_LOD)
+ return h0;
+ else
+ return h0 + h1 + (brw-gen = 7 ? 12 : 11) * mt-align_h;
+ }
+}
+
static void
align_cube(struct intel_mipmap_tree *mt)
{
@@ -243,17 +276,9 @@ static void
brw_miptree_layout_texture_array(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
- int h0, h1;
- unsigned height = mt-physical_height0;
-
- h0 = ALIGN(mt-physical_height0, mt-align_h);
- h1 = ALIGN(minify(mt-physical_height0, 1), mt-align_h);
- if (mt-array_layout == ALL_SLICES_AT_EACH_LOD)
- mt-qpitch = h0;
- else
- mt-qpitch = (h0 + h1 + (brw-gen = 7 ? 12 : 11) * mt-align_h);
-
+ mt-qpitch = brw_miptree_get_vertical_slice_pitch(brw, mt, 0);
int physical_qpitch = mt-compressed ? mt-qpitch / 4 : mt-qpitch;
+ unsigned height = mt-physical_height0;
brw_miptree_layout_2d(mt);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index ee9cf1e..e17132d 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -715,6 +715,24 @@ intel_miptree_updownsample(struct brw_context *brw,
struct intel_mipmap_tree *src,
struct intel_mipmap_tree *dst);
+/**
+ * Horizontal distance from one slice to the next in the two-dimensional
+ * miptree layout.
+ */
+unsigned
+brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt,
+ unsigned level);
+
+/**
+ * Vertical distance from one slice to the next in the two-dimensional
miptree
+ * layout.
+ */
+unsigned
+brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt,
+ unsigned level);
+
void brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree
*mt);
void *intel_miptree_map_raw(struct brw_context *brw,
--
2.1.3
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Re: [Mesa-dev] [PATCH] mesa: fix glGetActiveUniformsiv regression
On 23/04/15 14:19, Tapani Pälli wrote:
Commit 7519ddb caused regression to glGetActiveUniformsiv.
Patch adds back validation loop of all given uniforms before
writing any values, not touching params in case of errors
is tested by the conformance suite.
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90149
Not good for performance, but this is not too sensitive and we are just
following the spec.
Reviewed-by: Martin Peres martin.pe...@linux.intel.com
---
src/mesa/main/uniform_query.cpp | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
index 4e77b32..3e857ed 100644
--- a/src/mesa/main/uniform_query.cpp
+++ b/src/mesa/main/uniform_query.cpp
@@ -129,14 +129,26 @@ _mesa_GetActiveUniformsiv(GLuint program,
res_prop = resource_prop_from_uniform_prop(pname);
+ /* We need to first verify that each entry exists as active uniform. If
+* not, generate error and do not cause any other side effects.
+*
+* In the case of and error condition, Page 16 (section 2.3.1 Errors)
+* of the OpenGL 4.5 spec says:
+*
+* If the generating command modifies values through a pointer argu-
+* ment, no change is made to these values.
+*/
for (int i = 0; i uniformCount; i++) {
- res = _mesa_program_resource_find_index(shProg, GL_UNIFORM,
- uniformIndices[i]);
- if (!res) {
+ if (!_mesa_program_resource_find_index(shProg, GL_UNIFORM,
+ uniformIndices[i])) {
_mesa_error(ctx, GL_INVALID_VALUE, glGetActiveUniformsiv(index));
- break;
+ return;
}
+ }
+ for (int i = 0; i uniformCount; i++) {
+ res = _mesa_program_resource_find_index(shProg, GL_UNIFORM,
+ uniformIndices[i]);
if (!_mesa_program_resource_prop(shProg, res, uniformIndices[i],
res_prop, params[i],
glGetActiveUniformsiv))
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Re: [Mesa-dev] [Mesa-stable] [PATCH] clover: Call clBuildProgram() notification function when build completes
Humble ping.
-Emil
On 08/04/15 18:34, Emil Velikov wrote:
Hi Tom,
Just a friendly reminder that this patch hasn't landed in master yet.
Just making sure it doesn't fall through the cracks :-)
Cheers
Emil
On 24 March 2015 at 19:44, Tom Stellard thomas.stell...@amd.com wrote:
Cc: 10.5 10.4 mesa-sta...@lists.freedesktop.org
---
src/gallium/state_trackers/clover/api/program.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/src/gallium/state_trackers/clover/api/program.cpp
b/src/gallium/state_trackers/clover/api/program.cpp
index 60184ed..fcec1d7 100644
--- a/src/gallium/state_trackers/clover/api/program.cpp
+++ b/src/gallium/state_trackers/clover/api/program.cpp
@@ -180,8 +180,12 @@ clBuildProgram(cl_program d_prog, cl_uint num_devs,
validate_build_program_common(prog, num_devs, d_devs, pfn_notify,
user_data);
prog.build(devs, opts);
+ if (pfn_notify)
+ pfn_notify(d_prog, user_data);
return CL_SUCCESS;
} catch (error e) {
+ if (pfn_notify)
+ pfn_notify(d_prog, user_data);
if (e.get() == CL_INVALID_COMPILER_OPTIONS)
return CL_INVALID_BUILD_OPTIONS;
if (e.get() == CL_COMPILE_PROGRAM_FAILURE)
--
2.0.4
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Re: [Mesa-dev] [PATCH V2 05/22] i965: Pass miptree pointer as function parameter in intel_vertical_texture_alignment_unit
On Fri, Apr 17, 2015 at 04:51:26PM -0700, Anuj Phogat wrote:
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index e74e263..68c6634 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -90,7 +90,7 @@ intel_horizontal_texture_alignment_unit(struct brw_context
*brw,
static unsigned int
intel_vertical_texture_alignment_unit(struct brw_context *brw,
- mesa_format format, bool multisampled)
+ struct intel_mipmap_tree *mt)
const (only used for reading).
{
/**
* From the Alignment Unit Size section of various specs, namely:
@@ -115,10 +115,10 @@ intel_vertical_texture_alignment_unit(struct
brw_context *brw,
* Where * means either VALIGN_2 or VALIGN_4 depending on the setting of
* the SURFACE_STATE Surface Vertical Alignment field.
*/
- if (_mesa_is_format_compressed(format))
+ if (_mesa_is_format_compressed(mt-format))
return 4;
- if (format == MESA_FORMAT_S_UINT8)
+ if (mt-format == MESA_FORMAT_S_UINT8)
return brw-gen = 7 ? 8 : 4;
/* Broadwell only supports VALIGN of 4, 8, and 16. The BSpec says 4
@@ -127,10 +127,10 @@ intel_vertical_texture_alignment_unit(struct
brw_context *brw,
if (brw-gen = 8)
return 4;
- if (multisampled)
+ if (mt-num_samples 1)
return 4;
- GLenum base_format = _mesa_get_format_base_format(format);
+ GLenum base_format = _mesa_get_format_base_format(mt-format);
if (brw-gen = 6
(base_format == GL_DEPTH_COMPONENT ||
@@ -151,7 +151,7 @@ intel_vertical_texture_alignment_unit(struct brw_context
*brw,
*
* VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
*/
- if (base_format == GL_YCBCR_MESA || format == MESA_FORMAT_RGB_FLOAT32)
+ if (base_format == GL_YCBCR_MESA || mt-format ==
MESA_FORMAT_RGB_FLOAT32)
return 2;
return 4;
@@ -538,7 +538,6 @@ brw_miptree_layout(struct brw_context *brw,
enum intel_miptree_tiling_mode requested,
struct intel_mipmap_tree *mt)
{
- bool multisampled = mt-num_samples 1;
bool gen6_hiz_or_stencil = false;
if (brw-gen == 6 mt-array_layout == ALL_SLICES_AT_EACH_LOD) {
@@ -570,9 +569,8 @@ brw_miptree_layout(struct brw_context *brw,
mt-align_h = 32;
}
} else {
- mt-align_w = intel_horizontal_texture_alignment_unit(brw, mt);
- mt-align_h =
- intel_vertical_texture_alignment_unit(brw, mt-format,
multisampled);
+ mt-align_w = intel_horizontal_texture_alignment_unit(brw, mt);
extra space
Otherwise:
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
+ mt-align_h = intel_vertical_texture_alignment_unit(brw, mt);
}
intel_miptree_total_width_height(brw, mt);
--
2.3.4
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[Mesa-dev] [PATCH 1/7] i965: Add all surface types to the batch decode
It's true that not all surfaces apply for every gen, but for the most part this
is what we want. (The unfortunate case is when we use an valid surface, but not
for the specific GEN).
This was automated with a vim macro.
v2: Shortened common forms such as R8G8B8A8-RGBA8. Note that this makes some of
the sample output in subsequent commits slightly incorrect.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_state_dump.c | 226 -
1 file changed, 219 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c
b/src/mesa/drivers/dri/i965/brw_state_dump.c
index 5cf70eb..a688ba3 100644
--- a/src/mesa/drivers/dri/i965/brw_state_dump.c
+++ b/src/mesa/drivers/dri/i965/brw_state_dump.c
@@ -67,13 +67,225 @@ get_965_surfacetype(unsigned int surfacetype)
static const char *
get_965_surface_format(unsigned int surface_format)
{
-switch (surface_format) {
-case 0x000: return r32g32b32a32_float;
-case 0x0c1: return b8g8r8a8_unorm;
-case 0x100: return b5g6r5_unorm;
-case 0x102: return b5g5r5a1_unorm;
-case 0x104: return b4g4r4a4_unorm;
-default: return unknown;
+ switch (surface_format) {
+ case BRW_SURFACEFORMAT_R32G32B32A32_FLOAT: return RGBA32_FLOAT;
+ case BRW_SURFACEFORMAT_R32G32B32A32_SINT: return RGBA32_SINT;
+ case BRW_SURFACEFORMAT_R32G32B32A32_UINT: return RGBA32_UINT;
+ case BRW_SURFACEFORMAT_R32G32B32A32_UNORM: return RGBA32_UNORM;
+ case BRW_SURFACEFORMAT_R32G32B32A32_SNORM: return RGBA32_SNORM;
+ case BRW_SURFACEFORMAT_R64G64_FLOAT: return R64G64_FLOAT;
+ case BRW_SURFACEFORMAT_R32G32B32X32_FLOAT: return RGB32X32_FLOAT;
+ case BRW_SURFACEFORMAT_R32G32B32A32_SSCALED: return RGBA32_SSCALED;
+ case BRW_SURFACEFORMAT_R32G32B32A32_USCALED: return RGBA32_USCALED;
+ case BRW_SURFACEFORMAT_R32G32B32A32_SFIXED: return RGBA32_SFIXED;
+ case BRW_SURFACEFORMAT_R64G64_PASSTHRU: return R64G64_PASSTHRU;
+ case BRW_SURFACEFORMAT_R32G32B32_FLOAT: return RGB32_FLOAT;
+ case BRW_SURFACEFORMAT_R32G32B32_SINT: return RGB32_SINT;
+ case BRW_SURFACEFORMAT_R32G32B32_UINT: return RGB32_UINT;
+ case BRW_SURFACEFORMAT_R32G32B32_UNORM: return RGB32_UNORM;
+ case BRW_SURFACEFORMAT_R32G32B32_SNORM: return RGB32_SNORM;
+ case BRW_SURFACEFORMAT_R32G32B32_SSCALED: return RGB32_SSCALED;
+ case BRW_SURFACEFORMAT_R32G32B32_USCALED: return RGB32_USCALED;
+ case BRW_SURFACEFORMAT_R32G32B32_SFIXED: return RGB32_SFIXED;
+ case BRW_SURFACEFORMAT_R16G16B16A16_UNORM: return RGBA16_UNORM;
+ case BRW_SURFACEFORMAT_R16G16B16A16_SNORM: return RGBA16_SNORM;
+ case BRW_SURFACEFORMAT_R16G16B16A16_SINT: return RGBA16_SINT;
+ case BRW_SURFACEFORMAT_R16G16B16A16_UINT: return RGBA16_UINT;
+ case BRW_SURFACEFORMAT_R16G16B16A16_FLOAT: return RGBA16_FLOAT;
+ case BRW_SURFACEFORMAT_R32G32_FLOAT: return R32G32_FLOAT;
+ case BRW_SURFACEFORMAT_R32G32_SINT: return R32G32_SINT;
+ case BRW_SURFACEFORMAT_R32G32_UINT: return R32G32_UINT;
+ case BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS: return
R32_FLOAT_X8X24_TYPELESS;
+ case BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT: return
X32_TYPELESS_G8X24_UINT;
+ case BRW_SURFACEFORMAT_L32A32_FLOAT: return L32A32_FLOAT;
+ case BRW_SURFACEFORMAT_R32G32_UNORM: return R32G32_UNORM;
+ case BRW_SURFACEFORMAT_R32G32_SNORM: return R32G32_SNORM;
+ case BRW_SURFACEFORMAT_R64_FLOAT: return R64_FLOAT;
+ case BRW_SURFACEFORMAT_R16G16B16X16_UNORM: return RGBX16_UNORM;
+ case BRW_SURFACEFORMAT_R16G16B16X16_FLOAT: return RGBX16_FLOAT;
+ case BRW_SURFACEFORMAT_A32X32_FLOAT: return A32X32_FLOAT;
+ case BRW_SURFACEFORMAT_L32X32_FLOAT: return L32X32_FLOAT;
+ case BRW_SURFACEFORMAT_I32X32_FLOAT: return I32X32_FLOAT;
+ case BRW_SURFACEFORMAT_R16G16B16A16_SSCALED: return RGBA16_SSCALED;
+ case BRW_SURFACEFORMAT_R16G16B16A16_USCALED: return RGBA16_USCALED;
+ case BRW_SURFACEFORMAT_R32G32_SSCALED: return R32G32_SSCALED;
+ case BRW_SURFACEFORMAT_R32G32_USCALED: return R32G32_USCALED;
+ case BRW_SURFACEFORMAT_R32G32_FLOAT_LD: return R32G32_FLOAT_LD;
+ case BRW_SURFACEFORMAT_R32G32_SFIXED: return R32G32_SFIXED;
+ case BRW_SURFACEFORMAT_R64_PASSTHRU: return R64_PASSTHRU;
+ case BRW_SURFACEFORMAT_B8G8R8A8_UNORM: return B8G8R8A8_UNORM;
+ case BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB: return B8G8R8A8_UNORM_SRGB;
+ case BRW_SURFACEFORMAT_R10G10B10A2_UNORM: return R10G10B10A2_UNORM;
+ case BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB: return
R10G10B10A2_UNORM_SRGB;
+ case BRW_SURFACEFORMAT_R10G10B10A2_UINT: return R10G10B10A2_UINT;
+ case BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM: return
R10G10B10_SNORM_A2_UNORM;
+ case BRW_SURFACEFORMAT_R8G8B8A8_UNORM: return RGBA8_UNORM;
+ case BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB: return RGBA8_UNORM_SRGB;
+ case BRW_SURFACEFORMAT_R8G8B8A8_SNORM:
[Mesa-dev] [PATCH 3/7] i965: Add gen7+ sampler state to batch debug
OLD:
0x7e00: 0x1000: WM SAMP0: filtering
0x7e04: 0x000d: WM SAMP0: wrapping, lod
0x7e08: 0x: WM SAMP0: default color pointer
0x7e0c: 0x0090: WM SAMP0: chroma key, aniso
NEW:
0x7e00: 0x1000: SAMPLER_STATE 0: Disabled = no, Base Mip: 0.0,
Mip/Mag/Min Filter: NONE/NEAREST/NEAREST, LOD Bias: 0.0
0x7e04: 0x000d: SAMPLER_STATE 0: Min LOD: 0.0, Max LOD: 13.0
0x7e08: 0x: SAMPLER_STATE 0: Border Color
0x7e0c: 0x0090: SAMPLER_STATE 0: Max aniso: RATIO 2:1, TC[XYZ]
Address Control: CLAMP|CLAMP|WRAP
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_state_dump.c | 71 +-
1 file changed, 70 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c
b/src/mesa/drivers/dri/i965/brw_state_dump.c
index 89c1a29..21a3d8f 100644
--- a/src/mesa/drivers/dri/i965/brw_state_dump.c
+++ b/src/mesa/drivers/dri/i965/brw_state_dump.c
@@ -32,6 +32,33 @@
#include brw_defines.h
#include brw_eu.h
+static const char *sampler_mip_filter[] = {
+ NONE,
+ NEAREST,
+ RSVD,
+ LINEAR
+};
+
+static const char *sampler_mag_filter[] = {
+ NEAREST,
+ LINEAR,
+ ANISOTROPIC,
+ FLEXIBLE (GEN8+),
+ RSVD, RSVD,
+ MONO,
+ RSVD
+};
+
+static const char *sampler_addr_mode[] = {
+ WRAP,
+ MIRROR,
+ CLAMP,
+ CUBE,
+ CLAMP_BORDER,
+ MIRROR_ONCE,
+ HALF_BORDER
+};
+
static void
batch_out(struct brw_context *brw, const char *name, uint32_t offset,
int index, char *fmt, ...) PRINTFLIKE(5, 6);
@@ -483,6 +510,45 @@ static void dump_sampler_state(struct brw_context *brw,
}
}
+static void gen7_dump_sampler_state(struct brw_context *brw,
+uint32_t offset, uint32_t size)
+{
+ uint32_t *samp = brw-batch.bo-virtual + offset;
+ char name[20];
+
+ for (int i = 0; i size / 16; i++) {
+ sprintf(name, SAMPLER_STATE %d, i);
+ batch_out(brw, name, offset, i,
+Disabled = %s, Base Mip: %u.%u, Mip/Mag/Min Filter: %s/%s/%s,
LOD Bias: %d.%d\n,
+GET_BITS(samp[0], 31, 31) ? yes : no,
+GET_BITS(samp[0], 26, 23),
+GET_BITS(samp[0], 22, 22),
+sampler_mip_filter[GET_FIELD(samp[0], BRW_SAMPLER_MIP_FILTER)],
+sampler_mag_filter[GET_FIELD(samp[0], BRW_SAMPLER_MAG_FILTER)],
+/* min filter defs are the same as mag */
+sampler_mag_filter[GET_FIELD(samp[0], BRW_SAMPLER_MIN_FILTER)],
+GET_BITS(samp[0], 13, 10),
+GET_BITS(samp[0], 9, 1)
+ );
+ batch_out(brw, name, offset, i+1, Min LOD: %u.%u, Max LOD: %u.%u\n,
+GET_BITS(samp[1], 31, 28),
+GET_BITS(samp[1], 27, 20),
+GET_BITS(samp[1], 19, 16),
+GET_BITS(samp[1], 15, 8)
+ );
+ batch_out(brw, name, offset, i+2, Border Color\n); /* FINISHME: gen8+
*/
+ batch_out(brw, name, offset, i+3, Max aniso: RATIO %d:1, TC[XYZ]
Address Control: %s|%s|%s\n,
+(GET_FIELD(samp[3], BRW_SAMPLER_MAX_ANISOTROPY) + 1) * 2,
+sampler_addr_mode[GET_FIELD(samp[3],
BRW_SAMPLER_TCX_WRAP_MODE)],
+sampler_addr_mode[GET_FIELD(samp[3],
BRW_SAMPLER_TCY_WRAP_MODE)],
+sampler_addr_mode[GET_FIELD(samp[3],
BRW_SAMPLER_TCZ_WRAP_MODE)]
+ );
+
+ samp += 4;
+ offset += 4 * sizeof(uint32_t);
+ }
+}
+
static void dump_sf_viewport_state(struct brw_context *brw,
uint32_t offset)
{
@@ -784,7 +850,10 @@ dump_state_batch(struct brw_context *brw)
}
break;
case AUB_TRACE_SAMPLER_STATE:
- dump_sampler_state(brw, offset, size);
+ if (brw-gen = 7)
+gen7_dump_sampler_state(brw, offset, size);
+ else
+dump_sampler_state(brw, offset, size);
break;
case AUB_TRACE_SAMPLER_DEFAULT_COLOR:
dump_sdc(brw, offset);
--
2.3.6
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[Mesa-dev] [PATCH 0/7] surface state decode improvements (gen8+)
While trying to debug Skylake fast color clears, I noticed that the surface state generated by our decoder was woefully inadequate. Much of the dumped state was so stale as to be useless. Just to be clear, the code is not auto generated from a spec, and so I'm certain there are bugs in the decoder. There are the typo kind of bugs, and then some bugs where I feel the hardware spec is a bit vague, and I took a guess as to how things should work (I am looking at you Base mips). I guarantee that even with whatever bugs present, the output with INTEL_DEBUG=batch is significantly improved on all gen8+ platforms. Therefore, I think it makes a lot of sense to not worry too much about any minor issues, and fix them up in later patches... but it's your call. I made all of the character strings global since really any new code added to the file would likely benefit from having it there. (Also potentially we get slightly less bad performance when using INTEL_DEBUG=batch) I didn't intend to leave any major state changes out, so if you're aware of one I've missed, please don't hesitate to have me add it. Ben Widawsky (7): i965: Add all surface types to the batch decode i965: Add viewport extents (gen8) to batch decode i965: Add gen7+ sampler state to batch debug i965: Add gen8 surface state debug info i965: Add gen9 surface state decoding i965: Add renderbuffer surface indexes to debug i965: Add gen8 blend state src/mesa/drivers/dri/i965/brw_context.h| 1 + src/mesa/drivers/dri/i965/brw_defines.h| 7 +- src/mesa/drivers/dri/i965/brw_state.h | 13 +- src/mesa/drivers/dri/i965/brw_state_batch.c| 20 +- src/mesa/drivers/dri/i965/brw_state_dump.c | 405 +++-- src/mesa/drivers/dri/i965/gen8_surface_state.c | 15 +- 6 files changed, 423 insertions(+), 38 deletions(-) -- 2.3.6 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 7/7] i965: Add gen8 blend state
OLD:
0x7340: 0x0080:BLEND:
0x7344: 0x84202100:BLEND:
NEW:
0x7340: 0x0080:BLEND: Alpha blend/test
0x7344: 0x000b84202100: BLEND_ENTRY00:
Color Buffer Blend factor ONE,ONE,ONE,ONE (src,dst,src
alpha, dst alpha)
function ADD,ADD (color, alpha), Disables:
0x734c: 0x000b84202100: BLEND_ENTRY01:
Color Buffer Blend factor ONE,ONE,ONE,ONE (src,dst,src
alpha, dst alpha)
function ADD,ADD (color, alpha), Disables:
0x7354: 0x000b84202100: BLEND_ENTRY02:
Color Buffer Blend factor ONE,ONE,ONE,ONE (src,dst,src
alpha, dst alpha)
function ADD,ADD (color, alpha), Disables:
0x735c: 0x000b84202100: BLEND_ENTRY03:
Color Buffer Blend factor ONE,ONE,ONE,ONE (src,dst,src
alpha, dst alpha)
function ADD,ADD (color, alpha), Disables:
0x7364: 0x000b84202100: BLEND_ENTRY04:
Color Buffer Blend factor ONE,ONE,ONE,ONE (src,dst,src
alpha, dst alpha)
function ADD,ADD (color, alpha), Disables:
0x736c: 0x000b84202100: BLEND_ENTRY05:
Color Buffer Blend factor ONE,ONE,ONE,ONE (src,dst,src
alpha, dst alpha)
function ADD,ADD (color, alpha), Disables:
0x7374: 0x000b84202100: BLEND_ENTRY06:
Color Buffer Blend factor ONE,ONE,ONE,ONE (src,dst,src
alpha, dst alpha)
function ADD,ADD (color, alpha), Disables:
0x737c: 0x000b84202100: BLEND_ENTRY07:
Color Buffer Blend factor ONE,ONE,ONE,ONE (src,dst,src
alpha, dst alpha)
function ADD,ADD (color, alpha), Disables:
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_state_dump.c | 105 -
1 file changed, 103 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c
b/src/mesa/drivers/dri/i965/brw_state_dump.c
index 7217141..a98cef7 100644
--- a/src/mesa/drivers/dri/i965/brw_state_dump.c
+++ b/src/mesa/drivers/dri/i965/brw_state_dump.c
@@ -1,5 +1,5 @@
/*
- * Copyright © 2007 Intel Corporation
+ * Copyright © 2007-2015 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
@@ -93,6 +93,25 @@ batch_out(struct brw_context *brw, const char *name,
uint32_t offset,
va_end(va);
}
+static void
+batch_out64(struct brw_context *brw, const char *name, uint32_t offset,
+int index, char *fmt, ...)
+{
+ uint32_t *tmp = brw-batch.bo-virtual + offset;
+
+ /* Swap the dwords since we want to handle this as a 64b value, but the data
+* is typically emitted as dwords.
+*/
+ uint64_t data = ((uint64_t)tmp[index + 1]) 32 | tmp[index];
+ va_list va;
+
+ fprintf(stderr, 0x%08x: 0x%016 PRIx64 : %8s: ,
+ offset + index * 4, data, name);
+ va_start(va, fmt);
+ vfprintf(stderr, fmt, va);
+ va_end(va);
+}
+
static const char *
get_965_surfacetype(unsigned int surfacetype)
{
@@ -784,6 +803,85 @@ static void dump_blend_state(struct brw_context *brw,
uint32_t offset)
}
static void
+gen8_dump_blend_state(struct brw_context *brw, uint32_t offset, uint32_t size)
+{
+ uint32_t *blend = brw-batch.bo-virtual + offset;
+ const char *logicop[] =
+ {
+LOGICOP_CLEAR (BLACK),
+LOGICOP_NOR,
+LOGICOP_AND_INVERTED,
+LOGICOP_COPY_INVERTED,
+LOGICOP_AND_REVERSE,
+LOGICOP_INVERT,
+LOGICOP_XOR,
+LOGICOP_NAND,
+LOGICOP_AND,
+LOGICOP_EQUIV,
+LOGICOP_NOOP,
+LOGICOP_OR_INVERTED,
+LOGICOP_COPY,
+LOGICOP_OR_REVERSE,
+LOGICOP_OR,
+LOGICOP_SET (WHITE)
+ };
+
+ const char *blend_function[] =
+ { ADD, SUBTRACT, REVERSE_SUBTRACT, MIN, MAX}; };
+
+ const char *blend_factor[0x1b] =
+ {
+ RSVD,
+ ONE,
+ SRC_COLOR, SRC_ALPHA,
+ DST_ALPHA, DST_COLOR,
+ SRC_ALPHA_SATURATE,
+ CONST_COLOR, CONST_ALPHA,
+ SRC1_COLOR, SRC1_ALPHA,
+ RSVD, RSVD, RSVD, RSVD, RSVD, RSVD,
+ ZERO,
+ INV_SRC_COLOR, INV_SRC_ALPHA,
+ INV_DST_ALPHA, INV_DST_COLOR,
+ RSVD,
+ INV_CONST_COLOR, INV_CONST_ALPHA,
+ INV_SRC1_COLOR, INV_SRC1_ALPHA
+ };
+
+ batch_out(brw, BLEND, offset, 0, Alpha blend/test\n);
+
+ if (((size) % 2) != 0)
+ fprintf(stderr, Invalid blend state size %d\n, size);
+
+ for (int i = 1; i size / 4; i += 2) {
+ char name[] = BLEND_ENTRYXXX;
+ sprintf(name, BLEND_ENTRY%02d, (i - 1) / 2);
+ if (blend[i + 1] GEN8_BLEND_LOGIC_OP_ENABLE) {
+ batch_out(brw, name, offset, i + 1, %s\n,
+
[Mesa-dev] [PATCH 6/7] i965: Add renderbuffer surface indexes to debug
This patch is optional in the series. It does make the output much cleaner, but
there is some risk.
Sample output:
0x7180: 0x231d7000: SURF005: 2D R8G8B8A8_UNORM VALIGN4 HALIGN4
Y-tiled
0x7184: 0x1800: SURF005: MOCS: 0x18 Base MIP: 3 (0 mips) Surface
QPitch: 0
0x7188: 0x001f001f: SURF005: 32x32 [AUX_NONE]
0x718c: 0x007f: SURF005: 1 slices (depth), pitch: 128
0x7190: 0x: SURF005: min array element: 0, array extent 1,
MULTISAMPLE_1
0x7194: 0x: SURF005: x,y offset: 0,0, min LOD: 0
0x7198: 0x: SURF005: AUX pitch: 0 qpitch: 0
0x719c: 0x0977: SURF005: Clear color:
0x7140: 0x231d7000: SURF006: 2D R8G8B8A8_UNORM VALIGN4 HALIGN4
Y-tiled
0x7144: 0x1800: SURF006: MOCS: 0x18 Base MIP: 3 (0 mips) Surface
QPitch: 0
0x7148: 0x001f001f: SURF006: 32x32 [AUX_NONE]
0x714c: 0x007f: SURF006: 1 slices (depth), pitch: 128
0x7150: 0x: SURF006: min array element: 0, array extent 1,
MULTISAMPLE_1
0x7154: 0x: SURF006: x,y offset: 0,0, min LOD: 0
0x7158: 0x: SURF006: AUX pitch: 0 qpitch: 0
0x715c: 0x0977: SURF006: Clear color:
0x7100: 0x231d7000: SURF007: 2D R8G8B8A8_UNORM VALIGN4 HALIGN4
Y-tiled
0x7104: 0x1800: SURF007: MOCS: 0x18 Base MIP: 3 (0 mips) Surface
QPitch: 0
0x7108: 0x001f001f: SURF007: 32x32 [AUX_NONE]
0x710c: 0x007f: SURF007: 1 slices (depth), pitch: 128
0x7110: 0x: SURF007: min array element: 0, array extent 1,
MULTISAMPLE_1
0x7114: 0x: SURF007: x,y offset: 0,0, min LOD: 0
0x7118: 0x: SURF007: AUX pitch: 0 qpitch: 0
0x711c: 0x0977: SURF007: Clear color:
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_context.h| 1 +
src/mesa/drivers/dri/i965/brw_state.h | 13 -
src/mesa/drivers/dri/i965/brw_state_batch.c| 20
src/mesa/drivers/dri/i965/brw_state_dump.c | 12
src/mesa/drivers/dri/i965/gen8_surface_state.c | 15 ---
5 files changed, 37 insertions(+), 24 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index f79729b..0a6edcf 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1415,6 +1415,7 @@ struct brw_context
uint32_t offset;
uint32_t size;
enum aub_state_struct_type type;
+ int index;
} *state_batch_list;
int state_batch_count;
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index cfa67b6..7685178 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -205,11 +205,14 @@ void brw_destroy_caches( struct brw_context *brw );
#define BRW_BATCH_STRUCT(brw, s) \
intel_batchbuffer_data(brw, (s), sizeof(*(s)), RENDER_RING)
-void *brw_state_batch(struct brw_context *brw,
- enum aub_state_struct_type type,
- int size,
- int alignment,
- uint32_t *out_offset);
+void *__brw_state_batch(struct brw_context *brw,
+enum aub_state_struct_type type,
+int size,
+int alignment,
+int index,
+uint32_t *out_offset);
+#define brw_state_batch(brw, type, size, alignment, out_offset) \
+ __brw_state_batch(brw, type, size, alignment, 0, out_offset)
/* brw_wm_surface_state.c */
void gen4_init_vtable_surface_functions(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/brw_state_batch.c
b/src/mesa/drivers/dri/i965/brw_state_batch.c
index 45dca69..0377606 100644
--- a/src/mesa/drivers/dri/i965/brw_state_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_state_batch.c
@@ -38,7 +38,8 @@ static void
brw_track_state_batch(struct brw_context *brw,
enum aub_state_struct_type type,
uint32_t offset,
- int size)
+ int size,
+ int index)
{
struct intel_batchbuffer *batch = brw-batch;
@@ -53,6 +54,7 @@ brw_track_state_batch(struct brw_context *brw,
brw-state_batch_list[brw-state_batch_count].offset = offset;
brw-state_batch_list[brw-state_batch_count].size = size;
brw-state_batch_list[brw-state_batch_count].type = type;
+ brw-state_batch_list[brw-state_batch_count].index = index;
brw-state_batch_count++;
}
@@ -108,18 +110,20 @@ brw_annotate_aub(struct brw_context *brw)
* margin (4096 bytes, even if the object is just a 20-byte surface
* state), and more buffers to walk and count for aperture size checking.
*
- * However, due to the restrictions inposed by the aperture size
+ * However, due to
[Mesa-dev] [PATCH 5/7] i965: Add Gen9 surface state decoding
Gen9 surface state is very similar to the previous generation. The important
changes here are aux mode, and the way clear colors work.
NOTE: There are some things intentionally left out of this decoding.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_state_dump.c | 36 --
1 file changed, 29 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c
b/src/mesa/drivers/dri/i965/brw_state_dump.c
index 642bdc8..60e6b05 100644
--- a/src/mesa/drivers/dri/i965/brw_state_dump.c
+++ b/src/mesa/drivers/dri/i965/brw_state_dump.c
@@ -491,6 +491,22 @@ static void dump_gen8_surface_state(struct brw_context
*brw, uint32_t offset)
{
const char *name = SURF;
uint32_t *surf = brw-batch.bo-virtual + offset;
+ int aux_mode = surf[7] INTEL_MASK(2, 0);
+ const char *aux_str;
+
+ if (brw-gen = 9) {
+ bool msrt = GET_BITS(surf[4], 5, 3) 0;
+ switch (aux_mode) {
+ case 5:
+ aux_str = msrt ? AUX_CCS_E [MCS] : AUX_CCS_D [MCS];
+ break;
+ case 1:
+ aux_str = msrt ? AUX_CCS_E [CCS] : AUX_CCS_D [MCS];
+ default:
+ aux_str = surface_aux_mode[aux_mode];
+ }
+ } else
+ aux_str = surface_aux_mode[aux_mode];
batch_out(brw, SURF', offset, 0, %s %s %s VALIGN%d HALIGN%d %s\n,
get_965_surfacetype(GET_FIELD(surf[0], BRW_SURFACE_TYPE)),
@@ -509,7 +525,7 @@ static void dump_gen8_surface_state(struct brw_context
*brw, uint32_t offset)
batch_out(brw, name, offset, 2, %dx%d [%s]\n,
GET_FIELD(surf[2], GEN7_SURFACE_WIDTH) + 1,
GET_FIELD(surf[2], GEN7_SURFACE_HEIGHT) + 1,
- surface_aux_mode[surf[7] INTEL_MASK(2, 0)]
+ aux_str
);
batch_out(brw, name, offset, 3, %d slices (depth), pitch: %d\n,
GET_FIELD(surf[3], BRW_SURFACE_DEPTH) + 1,
@@ -529,12 +545,18 @@ static void dump_gen8_surface_state(struct brw_context
*brw, uint32_t offset)
GET_FIELD(surf[6], GEN8_SURFACE_AUX_QPITCH) 2,
GET_FIELD(surf[6], GEN8_SURFACE_AUX_PITCH) 2
);
- batch_out(brw, name, offset, 7, Clear color: %c%c%c%c\n,
- GET_BITS(surf[7], 31, 31) ? 'R' : '-',
- GET_BITS(surf[7], 30, 30) ? 'G' : '-',
- GET_BITS(surf[7], 29, 29) ? 'B' : '-',
- GET_BITS(surf[7], 28, 28) ? 'A' : '-'
-);
+ if (brw-gen = 9) {
+ batch_out(brw, name, offset, 7, Clear color: R(%x)G(%x)B(%x)A(%x)\n,
+surf[12], surf[13], surf[14], surf[15]
+ );
+ } else {
+ batch_out(brw, name, offset, 7, Clear color: %c%c%c%c\n,
+GET_BITS(surf[7], 31, 31) ? 'R' : '-',
+GET_BITS(surf[7], 30, 30) ? 'G' : '-',
+GET_BITS(surf[7], 29, 29) ? 'B' : '-',
+GET_BITS(surf[7], 28, 28) ? 'A' : '-'
+ );
+ }
}
static void
--
2.3.6
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[Mesa-dev] [PATCH 8/8] for test only
---
src/mesa/drivers/dri/i965/intel_debug.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_debug.c
b/src/mesa/drivers/dri/i965/intel_debug.c
index a5b883c..b4ec59e 100644
--- a/src/mesa/drivers/dri/i965/intel_debug.c
+++ b/src/mesa/drivers/dri/i965/intel_debug.c
@@ -34,7 +34,7 @@
#include utils.h
#include util/u_atomic.h /* for p_atomic_cmpxchg */
-uint64_t INTEL_DEBUG = 0;
+uint64_t INTEL_DEBUG = DEBUG_BATCH;
static const struct dri_debug_control debug_control[] = {
{ tex, DEBUG_TEXTURE},
--
2.3.5
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[Mesa-dev] [PATCH 2/7] i965: Add viewport extents (gen8) to batch decode
0x7da0: 0xc1da740e: SF_CLIP VP: guardband xmin = -27.306667
0x7da4: 0x41da740e: SF_CLIP VP: guardband xmax = 27.306667
0x7da4: 0x41da740e: SF_CLIP VP: guardband ymin = -23.405714
0x7da8: 0xc1bb3ee7: SF_CLIP VP: guardband ymax = 23.405714
0x7db0: 0x: SF_CLIP VP: Min extents: 0.00x0.00
0x7db8: 0x: SF_CLIP VP: Max extents: 299.00x349.00
While here, fix the wrong offsets for the guardband (I didn't check if it used
to be valid on GEN4).
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_defines.h| 1 +
src/mesa/drivers/dri/i965/brw_state_dump.c | 15 +++
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index bd3218a..e37d2e0 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -38,6 +38,7 @@
fieldval field ## _MASK;\
})
+#define GET_BITS(data, high, low) ((data INTEL_MASK(high, low)) low)
#define GET_FIELD(word, field) (((word) field ## _MASK) field ## _SHIFT)
#ifndef BRW_DEFINES_H
diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c
b/src/mesa/drivers/dri/i965/brw_state_dump.c
index a688ba3..89c1a29 100644
--- a/src/mesa/drivers/dri/i965/brw_state_dump.c
+++ b/src/mesa/drivers/dri/i965/brw_state_dump.c
@@ -532,10 +532,17 @@ static void dump_sf_clip_viewport_state(struct
brw_context *brw,
batch_out(brw, name, offset, 3, m30 = %f\n, vp-viewport.m30);
batch_out(brw, name, offset, 4, m31 = %f\n, vp-viewport.m31);
batch_out(brw, name, offset, 5, m32 = %f\n, vp-viewport.m32);
- batch_out(brw, name, offset, 6, guardband xmin = %f\n,
vp-guardband.xmin);
- batch_out(brw, name, offset, 7, guardband xmax = %f\n,
vp-guardband.xmax);
- batch_out(brw, name, offset, 8, guardband ymin = %f\n,
vp-guardband.ymin);
- batch_out(brw, name, offset, 9, guardband ymax = %f\n,
vp-guardband.ymax);
+ batch_out(brw, name, offset, 8, guardband xmin = %f\n,
vp-guardband.xmin);
+ batch_out(brw, name, offset, 9, guardband xmax = %f\n,
vp-guardband.xmax);
+ batch_out(brw, name, offset, 9, guardband ymin = %f\n,
vp-guardband.ymin);
+ batch_out(brw, name, offset, 10, guardband ymax = %f\n,
vp-guardband.ymax);
+ if (brw-gen = 8) {
+ float *cc_vp = brw-batch.bo-virtual + offset;
+ batch_out(brw, name, offset, 12, Min extents: %.2fx%.2f\n,
+cc_vp[12], cc_vp[14]);
+ batch_out(brw, name, offset, 14, Max extents: %.2fx%.2f\n,
+cc_vp[13], cc_vp[15]);
+ }
}
--
2.3.6
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[Mesa-dev] [PATCH 4/7] i965: Add gen8 surface state debug info
AFAICT, none of the old data was wrong (the gen7 decoder), but it wa smissing a
bunch of stuff.
Adds a tick (') to denote the beginning of the surface state for easier reading.
This will be replaced later with some better, but more risky code.
OLD:
0x7980: 0x23016000: SURF: 2D BRW_SURFACEFORMAT_B8G8R8A8_UNORM
0x7984: 0x1800: SURF: offset
0x7988: 0x00ff00ff: SURF: 256x256 size, 0 mips, 1 slices
0x798c: 0x03ff: SURF: pitch 1024, tiled
0x7990: 0x: SURF: min array element 0, array extent 1
0x7994: 0x: SURF: mip base 0
0x7998: 0x: SURF: x,y offset: 0,0
0x799c: 0x0977: SURF:
0x7940: 0x231d7000: SURF: 2D BRW_SURFACEFORMAT_R8G8B8A8_UNORM
0x7944: 0x7800: SURF: offset
0x7948: 0x001f001f: SURF: 32x32 size, 0 mips, 1 slices
0x794c: 0x007f: SURF: pitch 128, tiled
0x7950: 0x: SURF: min array element 0, array extent 1
0x7954: 0x: SURF: mip base 0
0x7958: 0x: SURF: x,y offset: 0,0
0x795c: 0x0977: SURF:
NEW:
0x7980: 0x23016000:SURF': 2D B8G8R8A8_UNORM VALIGN4 HALIGN4
X-tiled
0x7984: 0x1800: SURF: MOCS: 0x18 Base MIP: 0.0 (0 mips)
Surface QPitch: 0
0x7988: 0x00ff00ff: SURF: 256x256 [AUX_NONE]
0x798c: 0x03ff: SURF: 1 slices (depth), pitch: 1024
0x7990: 0x: SURF: min array element: 0, array extent 1,
MULTISAMPLE_1
0x7994: 0x: SURF: x,y offset: 0,0, min LOD: 0
0x7998: 0x: SURF: AUX pitch: 0 qpitch: 0
0x799c: 0x0977: SURF: Clear color:
0x7940: 0x231d7000:SURF': 2D R8G8B8A8_UNORM VALIGN4 HALIGN4
Y-tiled
0x7944: 0x7800: SURF: MOCS: 0x78 Base MIP: 0 (0 mips) Surface
QPitch: ff
0x7948: 0x001f001f: SURF: 32x32 [AUX_NONE]
0x794c: 0x007f: SURF: 1 slices (depth), pitch: 128
0x7950: 0x: SURF: min array element: 0, array extent 1,
MULTISAMPLE_1
0x7954: 0x: SURF: x,y offset: 0,0, min LOD: 0
0x7958: 0x: SURF: AUX pitch: 0 qpitch: 0
0x795c: 0x0977: SURF: Clear color:
0x7920: 0x7980:BIND0: surface state address
0x7924: 0x7940:BIND1: surface state address
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_defines.h| 4 +-
src/mesa/drivers/dri/i965/brw_state_dump.c | 86 --
2 files changed, 85 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index e37d2e0..b9aae29 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -529,9 +529,11 @@
#define GEN7_SURFACE_ARYSPC_FULL (0 10)
#define GEN7_SURFACE_ARYSPC_LOD0 (1 10)
-/* Surface state DW0 */
+/* Surface state DW1 */
#define GEN8_SURFACE_MOCS_SHIFT 24
#define GEN8_SURFACE_MOCS_MASK INTEL_MASK(30, 24)
+#define GEN8_SURFACE_QPITCH_SHIFT 0
+#define GEN8_SURFACE_QPITCH_MASKINTEL_MASK(14, 0)
/* Surface state DW2 */
#define BRW_SURFACE_HEIGHT_SHIFT 19
diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c
b/src/mesa/drivers/dri/i965/brw_state_dump.c
index 21a3d8f..642bdc8 100644
--- a/src/mesa/drivers/dri/i965/brw_state_dump.c
+++ b/src/mesa/drivers/dri/i965/brw_state_dump.c
@@ -59,6 +59,22 @@ static const char *sampler_addr_mode[] = {
HALF_BORDER
};
+static const char *surface_tiling[] = {
+ LINEAR,
+ W-tiled,
+ X-tiled,
+ Y-tiled
+};
+
+static const char *surface_aux_mode[] = {
+ AUX_NONE,
+ AUX_MCS,
+ AUX_APPEND,
+ AUX_HIZ,
+ RSVD,
+ RSVD
+};
+
static void
batch_out(struct brw_context *brw, const char *name, uint32_t offset,
int index, char *fmt, ...) PRINTFLIKE(5, 6);
@@ -461,6 +477,66 @@ static void dump_gen7_surface_state(struct brw_context
*brw, uint32_t offset)
batch_out(brw, name, offset, 7, \n);
}
+static float q_to_float(uint32_t data, int integer_end, int integer_start,
+int fractional_end, int fractional_start)
+{
+ /* Convert the number to floating point. */
+ float n = GET_BITS(data, integer_start, fractional_end);
+
+ /* Multiple by 2^-n */
+ return n * pow(2, -(fractional_end - fractional_start + 1));
+}
+
+static void dump_gen8_surface_state(struct brw_context *brw, uint32_t offset)
+{
+ const char *name = SURF;
+ uint32_t *surf = brw-batch.bo-virtual + offset;
+
+ batch_out(brw, SURF', offset, 0, %s %s %s VALIGN%d HALIGN%d %s\n,
+ get_965_surfacetype(GET_FIELD(surf[0], BRW_SURFACE_TYPE)),
+ get_965_surface_format(GET_FIELD(surf[0], BRW_SURFACE_FORMAT)),
+ (surf[0] GEN7_SURFACE_IS_ARRAY) ? array : ,
+
[Mesa-dev] [PATCH 5/8] i965: Add gen9 surface state decoding
Gen9 is mostly the same as Gen8.
NOTE: There are some things intentionally left out of this decoding.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_state_dump.c | 30 +++---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c
b/src/mesa/drivers/dri/i965/brw_state_dump.c
index abda1e9..d199a89 100644
--- a/src/mesa/drivers/dri/i965/brw_state_dump.c
+++ b/src/mesa/drivers/dri/i965/brw_state_dump.c
@@ -449,9 +449,19 @@ static void dump_gen8_surface_state(struct brw_context
*brw, uint32_t offset)
const char *name = SURF;
uint32_t *surf = brw-batch.bo-virtual + offset;
const char *tiling_modes[] = { LINEAR, W-tiled, X-tiled, Y-tiled };
- const char *aux_mode[] =
+ char *aux_mode[] =
{AUX_NONE, AUX_MCS, AUX_APPEND, AUX_HIZ, RSVD, RSVD};
+ if (brw-gen = 9) {
+ if (GET_BITS(surf[4], 5, 3) 0) {
+ aux_mode[1] = AUX_CCS_D (MCS);
+ aux_mode[5] = AUX_CCS_E (MCS);
+ } else {
+ aux_mode[1] = AUX_CCS_D (CCS);
+ aux_mode[5] = AUX_CCS_E (CCS);
+ }
+ }
+
batch_out(brw, SURF', offset, 0, %s %s %s VALIGN%d HALIGN%d %s\n,
get_965_surfacetype(GET_FIELD(surf[0], BRW_SURFACE_TYPE)),
get_965_surface_format(GET_FIELD(surf[0], BRW_SURFACE_FORMAT)),
@@ -489,12 +499,18 @@ static void dump_gen8_surface_state(struct brw_context
*brw, uint32_t offset)
GET_FIELD(surf[6], GEN8_SURFACE_AUX_QPITCH) 2,
GET_FIELD(surf[6], GEN8_SURFACE_AUX_PITCH) 2
);
- batch_out(brw, name, offset, 7, Clear color: %c%c%c%c\n,
- GET_BITS(surf[7], 31, 31) ? 'R' : '-',
- GET_BITS(surf[7], 30, 30) ? 'G' : '-',
- GET_BITS(surf[7], 29, 29) ? 'B' : '-',
- GET_BITS(surf[7], 28, 28) ? 'A' : '-'
-);
+ if (brw-gen = 9) {
+ batch_out(brw, name, offset, 7, Clear color: R(%x)G(%x)B(%x)A(%x)\n,
+surf[12], surf[13], surf[14], surf[15]
+ );
+ } else {
+ batch_out(brw, name, offset, 7, Clear color: %c%c%c%c\n,
+GET_BITS(surf[7], 31, 31) ? 'R' : '-',
+GET_BITS(surf[7], 30, 30) ? 'G' : '-',
+GET_BITS(surf[7], 29, 29) ? 'B' : '-',
+GET_BITS(surf[7], 28, 28) ? 'A' : '-'
+ );
+ }
}
static void
--
2.3.5
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Re: [Mesa-dev] [PATCH V2 14/22] i965/gen9: Set vertical and horizontal surface alignments
On Fri, Apr 17, 2015 at 04:51:35PM -0700, Anuj Phogat wrote:
Patch sets the alignments for texture and renderbuffer surfaces.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 34
+++---
1 file changed, 30 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 1ec57c0..189f1db 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -218,10 +218,23 @@ gen8_update_texture_surface(struct gl_context *ctx,
surf[0] = surf_type BRW_SURFACE_TYPE_SHIFT |
tex_format BRW_SURFACE_FORMAT_SHIFT |
- vertical_alignment(mt) |
- horizontal_alignment(mt) |
tiling_mode;
+ if (brw-gen 9) {
+ surf[0] |= horizontal_alignment(mt) | vertical_alignment(mt);
+ }
+ /* Horizontal alignment is ignored when Tiled Resource Mode is not
+* TRMODE_NONE. Vertical alignment is ignored for 1D surfaces and when
+* Tiled Resource Mode is not TRMODE_NONE.
+*/
+ else if (tr_mode == GEN9_SURFACE_TRMODE_NONE) {
+ if (!gen9_use_linear_1d_layout(brw, mt))
+ surf[0] |= horizontal_alignment(mt);
+
+ if (surf_type != BRW_SURFACE_1D)
+ surf[0] |= vertical_alignment(mt);
+ }
Wouldn't it be cleaner to patch both horizontal_alignment() and
vertical_alignment() passing them the additional information as extra
arguments?
+
if (surf_type == BRW_SURFACE_CUBE) {
surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
}
@@ -400,10 +413,23 @@ gen8_update_renderbuffer_surface(struct brw_context
*brw,
surf[0] = (surf_type BRW_SURFACE_TYPE_SHIFT) |
(is_array ? GEN7_SURFACE_IS_ARRAY : 0) |
(format BRW_SURFACE_FORMAT_SHIFT) |
- vertical_alignment(mt) |
- horizontal_alignment(mt) |
surface_tiling_mode(tiling);
+ if (brw-gen 9) {
+ surf[0] |= horizontal_alignment(mt) | vertical_alignment(mt);
+ }
+ /* Horizontal alignment is ignored when Tiled Resource Mode is not
+* TRMODE_NONE. Vertical alignment is ignored for 1D surfaces and when
+* Tiled Resource Mode is not TRMODE_NONE.
+*/
+ else if (tr_mode == GEN9_SURFACE_TRMODE_NONE) {
+ if (!gen9_use_linear_1d_layout(brw, mt))
+ surf[0] |= horizontal_alignment(mt);
+
+ if (surf_type != BRW_SURFACE_1D)
+ surf[0] |= vertical_alignment(mt);
+ }
+
surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS) | mt-qpitch 2;
surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
--
2.3.4
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Re: [Mesa-dev] [PATCH V2 13/22] i965: Use BRW_SURFACE_* in place of GL_TEXTURE_*
On Fri, Apr 17, 2015 at 04:51:34PM -0700, Anuj Phogat wrote:
Makes no functional changes in the code.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
Reviewed-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index d2eceff..1ec57c0 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -172,6 +172,7 @@ gen8_update_texture_surface(struct gl_context *ctx,
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
struct intel_mipmap_tree *aux_mt = NULL;
uint32_t aux_mode = 0;
+ uint32_t surf_type;
mesa_format format = intelObj-_Format;
uint32_t mocs_wb = brw-gen = 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
@@ -201,29 +202,31 @@ gen8_update_texture_surface(struct gl_context *ctx,
aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
}
+ surf_type = translate_tex_target(tObj-Target);
+
I would rather just write:
const uint32_t surf_type = translate_tex_target(tObj-Target);
/* If this is a view with restricted NumLayers, then our effective depth
* is not just the miptree depth.
*/
uint32_t effective_depth =
- (tObj-Immutable tObj-Target != GL_TEXTURE_3D) ? tObj-NumLayers
- :
mt-logical_depth0;
+ (tObj-Immutable surf_type != BRW_SURFACE_3D) ? tObj-NumLayers
+ : mt-logical_depth0;
uint32_t tex_format = translate_tex_format(brw, format,
sampler-sRGBDecode);
uint32_t *surf = allocate_surface_state(brw, surf_offset);
- surf[0] = translate_tex_target(tObj-Target) BRW_SURFACE_TYPE_SHIFT |
+
I guess you didn't mean to have extra newline here.
+ surf[0] = surf_type BRW_SURFACE_TYPE_SHIFT |
Lets use SET_FIELD(surf_type, BRW_SURFACE_TYPE) instead.
With those:
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
Having said that, would you mind rebasing this on top of my series that
moves all the decision making common to all hardware platforms into one
place?
tex_format BRW_SURFACE_FORMAT_SHIFT |
vertical_alignment(mt) |
horizontal_alignment(mt) |
tiling_mode;
- if (tObj-Target == GL_TEXTURE_CUBE_MAP ||
- tObj-Target == GL_TEXTURE_CUBE_MAP_ARRAY) {
+ if (surf_type == BRW_SURFACE_CUBE) {
surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
}
- if (mt-logical_depth0 1 tObj-Target != GL_TEXTURE_3D)
+ if (mt-logical_depth0 1 surf_type != BRW_SURFACE_3D)
surf[0] |= GEN8_SURFACE_IS_ARRAY;
surf[1] = SET_FIELD(mocs_wb, GEN8_SURFACE_MOCS) | mt-qpitch 2;
--
2.3.4
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