Re: [Mesa-dev] [PATCH 1/7] i965/fs_surface_builder: Explicitly handle FORMAT_NONE in num_image_coordinates

[Jason Ekstrand]

On Mon, Nov 23, 2015 at 6:15 AM, Francisco Jerez  wrote:
> Jason Ekstrand  writes:
>
>> On Fri, Nov 20, 2015 at 5:49 AM, Francisco Jerez  
>> wrote:
>>> Chad Versace  writes:
>>>
 On Wed 04 Nov 2015, Jason Ekstrand wrote:
> Previously, we were relying on has_matching_typed_format returning true 
> for
> MESA_FORMAT_NONE which, in turn, relied on _mesa_get_format_bytes 
> returning
> 1 for MESA_FORMAT_NONE.  All of this is extremely non-obvious.  Instead,
> this commit makes us handle it explicitly.
> ---
>  src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp 
> b/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp
> index 534d849..31ecb5b 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp
> @@ -409,6 +409,7 @@ namespace {
>* reads want the array index to be at the Z component.
>*/
>   const bool array_index_at_z =
> +format != MESA_FORMAT_NONE &&
>  !image_format_info::has_matching_typed_format(
> bld.shader->devinfo, format);
>   const unsigned zero_dims =


 Knowing nothing about the implicit assumptions you discovered that
 relied on _mesa_get_format_bytes(MESA_FORMAT_NONE) => 1, the patch is
 still looks like an improvement to me.

>>> It didn't.  It relied on _mesa_get_format_bytes(MESA_FORMAT_NONE) not
>>> being greater than 4, which seems sensible anyway.
>>
>> I can change the commit message to say
>>
>> Previously, we were relying on has_matching_typed_format returning true for
>> MESA_FORMAT_NONE which, in turn, relied on _mesa_get_format_bytes returning
>> a value <= 4 for MESA_FORMAT_NONE.  While reliable, this is extremely
>> non-obvious.  Instead,
>> this commit makes us handle it explicitly.
>
> has_matching_typed_format(MESA_FORMAT_NONE) returned true by design,
> GL_NONE/MESA_FORMAT_NONE represents a shader-unspecified format
> throughout the image load/store code, and in Gen hardware that
> necessarily implies typed (since otherwise we would need to know the
> format for the compiler to be able to generate appropriate format
> conversion code, but we don't).  Its semantics are blurred quite a bit
> in this series though: All instances of MESA_FORMAT_NONE are replaced
> with BRW_SURFACEFORMAT_RAW, which is already used in the image surface
> state setup code to represent an *untyped* format (that's what a RAW
> surface format means on Gen hardware), i.e. a set of formats fully
> disjoint from what MESA_FORMAT_NONE used to represent.

I wish that had been better documented...  However, with the
experience I have gained hooking up image_load_store in other
places,that makes sense.

> For that reason 'has_matching_typed_format(MESA_FORMAT_NONE) = true'
> makes sense to me, but 'has_matching_typed_format(BRW_SURFACEFORMAT_RAW)
> = true' and the identification of MESA_FORMAT_NONE with
> BRW_SURFACEFORMAT_RAW does not.

Yeah, that's a distinction I would like to keep.  Perhaps a
BRW_SURFACEFORMAT_INVALID?  That's what we're doing in libisl right
now.  Does that sound reasonable?

> I believe this confusion may not have led to any actual bugs though,
> because BRW_SURFACEFORMAT_RAW was only used in the state upload code and
> was never actually visible to the compiler.  Likewise MESA_FORMAT_NONE
> was never visible to the state upload code because an image unit with
> invalid format would have been caught by the _mesa_is_image_unit_valid()
> check before the translation to native formats.  Seems rather
> disquieting still...
>
>>
 Acked-by: Chad Versace 
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Re: [Mesa-dev] [PATCH 1/2] targets/nine: remove vc4 target

[Emil Velikov]

On 23 November 2015 at 18:36, Emil Velikov  wrote:
> Any nir powered targets outside of DRI have been broken for a little
> while now (due to unresolved symbols).
PEBKAC things link fine.

-Emil
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Re: [Mesa-dev] [PATCH] i965: Always use Y-tiled buffers on SKL+

[Neil Roberts]

Hi,

Has this situation changed at all? It's probably quite important to get
this working because we have to disable fast clears for X-tiled buffers
on SKL which effectively means we currently can't do it for window
system buffers.

Regards,
- Neil

Chris Wilson  writes:

> On Mon, Apr 13, 2015 at 04:31:29PM +0200, Daniel Vetter wrote:
>> On Sat, Apr 11, 2015 at 01:16:11PM -0700, Ben Widawsky wrote:
>> > Starting with Skylake, the display engine is capable of scanning out from
>> > Y-tiled buffers. As such, we can and should use Y-tiling for better 
>> > efficiency.
>> > 
>> > Note that the buffer allocation done for mipmaps will already never 
>> > allocate an
>> > X-tiled buffer for GEN9.
>> > 
>> > Signed-off-by: Ben Widawsky 
>> 
>> You need a recent enough ddx to make use of Y-tiled buffers, which atm
>> still doesn't yet exist. This would at least need some kind of handshake
>> with the compositor to make sure it understands this, presuming I didn't
>> miss something.
>
> You can send Y-tiled buffers to the DDX. The problem is that the kernel
> won't allow us to display them and so we will (and always have been)
> copying from them.
> -Chris
>
> -- 
> Chris Wilson, Intel Open Source Technology Centre
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Re: [Mesa-dev] [PATCH 2/2] targets/nine: remove freedreno target

[Emil Velikov]

On 23 November 2015 at 18:44, Rob Clark  wrote:
> just curious, but which syms?
>
Seems that I had some local glsl/nir changes which caused the issue. I
should stop doing so many things at one :-)

> That said, I'm not really sure if wine/gallium9 has much usefulness on ARM, so
>
> Acked-by: Rob Clark 

Yes, pretty much. Thanks

-Emil
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[Mesa-dev] [PATCH 2/2] targets/nine: remove freedreno target

[Emil Velikov]

Analogous to previous commit. As we no longer have anyone who uses NIR
we can drop the link.

Cc: Rob Clark 
Signed-off-by: Emil Velikov 
---
 src/gallium/targets/d3dadapter9/Makefile.am | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/gallium/targets/d3dadapter9/Makefile.am 
b/src/gallium/targets/d3dadapter9/Makefile.am
index 4414f4b..8b27938 100644
--- a/src/gallium/targets/d3dadapter9/Makefile.am
+++ b/src/gallium/targets/d3dadapter9/Makefile.am
@@ -62,7 +62,6 @@ endif # HAVE_LD_VERSION_SCRIPT
 d3dadapter9_la_LIBADD = \
$(top_builddir)/src/gallium/auxiliary/libgalliumvl_stub.la \
$(top_builddir)/src/gallium/auxiliary/libgallium.la \
-   $(top_builddir)/src/glsl/libnir.la \
$(top_builddir)/src/gallium/state_trackers/nine/libninetracker.la \
$(top_builddir)/src/util/libmesautil.la \
$(EXPAT_LIBS) \
@@ -87,8 +86,6 @@ include 
$(top_srcdir)/src/gallium/drivers/radeonsi/Automake.inc
 
 include $(top_srcdir)/src/gallium/drivers/svga/Automake.inc
 
-include $(top_srcdir)/src/gallium/drivers/freedreno/Automake.inc
-
 include $(top_srcdir)/src/gallium/drivers/softpipe/Automake.inc
 include $(top_srcdir)/src/gallium/drivers/llvmpipe/Automake.inc
 
-- 
2.6.2

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Re: [Mesa-dev] [PATCH 2/2] targets/nine: remove freedreno target

[Rob Clark]

just curious, but which syms?

That said, I'm not really sure if wine/gallium9 has much usefulness on ARM, so

Acked-by: Rob Clark 

On Mon, Nov 23, 2015 at 1:36 PM, Emil Velikov  wrote:
> Analogous to previous commit. As we no longer have anyone who uses NIR
> we can drop the link.
>
> Cc: Rob Clark 
> Signed-off-by: Emil Velikov 
> ---
>  src/gallium/targets/d3dadapter9/Makefile.am | 3 ---
>  1 file changed, 3 deletions(-)
>
> diff --git a/src/gallium/targets/d3dadapter9/Makefile.am 
> b/src/gallium/targets/d3dadapter9/Makefile.am
> index 4414f4b..8b27938 100644
> --- a/src/gallium/targets/d3dadapter9/Makefile.am
> +++ b/src/gallium/targets/d3dadapter9/Makefile.am
> @@ -62,7 +62,6 @@ endif # HAVE_LD_VERSION_SCRIPT
>  d3dadapter9_la_LIBADD = \
> $(top_builddir)/src/gallium/auxiliary/libgalliumvl_stub.la \
> $(top_builddir)/src/gallium/auxiliary/libgallium.la \
> -   $(top_builddir)/src/glsl/libnir.la \
> $(top_builddir)/src/gallium/state_trackers/nine/libninetracker.la \
> $(top_builddir)/src/util/libmesautil.la \
> $(EXPAT_LIBS) \
> @@ -87,8 +86,6 @@ include 
> $(top_srcdir)/src/gallium/drivers/radeonsi/Automake.inc
>
>  include $(top_srcdir)/src/gallium/drivers/svga/Automake.inc
>
> -include $(top_srcdir)/src/gallium/drivers/freedreno/Automake.inc
> -
>  include $(top_srcdir)/src/gallium/drivers/softpipe/Automake.inc
>  include $(top_srcdir)/src/gallium/drivers/llvmpipe/Automake.inc
>
> --
> 2.6.2
>
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[Mesa-dev] [PATCH 1/2] targets/nine: remove vc4 target

[Emil Velikov]

Any nir powered targets outside of DRI have been broken for a little
while now (due to unresolved symbols). Not to mention that there are
no users for it, yet.

Cc: Eric Anholt 
Signed-off-by: Emil Velikov 
---
 src/gallium/targets/d3dadapter9/Makefile.am | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/gallium/targets/d3dadapter9/Makefile.am 
b/src/gallium/targets/d3dadapter9/Makefile.am
index d1d9829..4414f4b 100644
--- a/src/gallium/targets/d3dadapter9/Makefile.am
+++ b/src/gallium/targets/d3dadapter9/Makefile.am
@@ -89,8 +89,6 @@ include $(top_srcdir)/src/gallium/drivers/svga/Automake.inc
 
 include $(top_srcdir)/src/gallium/drivers/freedreno/Automake.inc
 
-include $(top_srcdir)/src/gallium/drivers/vc4/Automake.inc
-
 include $(top_srcdir)/src/gallium/drivers/softpipe/Automake.inc
 include $(top_srcdir)/src/gallium/drivers/llvmpipe/Automake.inc
 
-- 
2.6.2

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[Mesa-dev] [PATCH 1/5] pipe-loader: check if winsys.name is non-null prior to strcmp

[Emil Velikov]

In theory this wouldn't be an issue, as we'll find the correct name and
break out of the loop before we hit the sentinel.

Let's fix this and avoid issues in the future.

Spotted by Coverity.

Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Emil Velikov 
---
 src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c 
b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
index 5539a73..6c1571b 100644
--- a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
+++ b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
@@ -136,7 +136,7 @@ pipe_loader_sw_probe_dri(struct pipe_loader_device **devs, 
struct drisw_loader_f
if (!pipe_loader_sw_probe_init_common(sdev))
   goto fail;
 
-   for (i = 0; sdev->dd->winsys; i++) {
+   for (i = 0; sdev->dd->winsys[i].name; i++) {
   if (strcmp(sdev->dd->winsys[i].name, "dri") == 0) {
  sdev->ws = sdev->dd->winsys[i].create_winsys(drisw_lf);
  break;
@@ -168,7 +168,7 @@ pipe_loader_sw_probe_kms(struct pipe_loader_device **devs, 
int fd)
if (!pipe_loader_sw_probe_init_common(sdev))
   goto fail;
 
-   for (i = 0; sdev->dd->winsys; i++) {
+   for (i = 0; sdev->dd->winsys[i].name; i++) {
   if (strcmp(sdev->dd->winsys[i].name, "kms_dri") == 0) {
  sdev->ws = sdev->dd->winsys[i].create_winsys(fd);
  break;
@@ -199,7 +199,7 @@ pipe_loader_sw_probe_null(struct pipe_loader_device **devs)
if (!pipe_loader_sw_probe_init_common(sdev))
   goto fail;
 
-   for (i = 0; sdev->dd->winsys; i++) {
+   for (i = 0; sdev->dd->winsys[i].name; i++) {
   if (strcmp(sdev->dd->winsys[i].name, "null") == 0) {
  sdev->ws = sdev->dd->winsys[i].create_winsys();
  break;
@@ -244,7 +244,7 @@ pipe_loader_sw_probe_wrapped(struct pipe_loader_device 
**dev,
if (!pipe_loader_sw_probe_init_common(sdev))
   goto fail;
 
-   for (i = 0; sdev->dd->winsys; i++) {
+   for (i = 0; sdev->dd->winsys[i].name; i++) {
   if (strcmp(sdev->dd->winsys[i].name, "wrapped") == 0) {
  sdev->ws = sdev->dd->winsys[i].create_winsys(screen);
  break;
-- 
2.6.2

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[Mesa-dev] [PATCH 3/5] st/xa: fd management cleanups

[Emil Velikov]

Analogous to previous commit.

Spotted by Coverity.

Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Emil Velikov 
---
 src/gallium/state_trackers/xa/xa_tracker.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/gallium/state_trackers/xa/xa_tracker.c 
b/src/gallium/state_trackers/xa/xa_tracker.c
index faa630c..d57464b 100644
--- a/src/gallium/state_trackers/xa/xa_tracker.c
+++ b/src/gallium/state_trackers/xa/xa_tracker.c
@@ -152,11 +152,15 @@ xa_tracker_create(int drm_fd)
 struct xa_tracker *xa = calloc(1, sizeof(struct xa_tracker));
 enum xa_surface_type stype;
 unsigned int num_formats;
+int fd = -1;
 
 if (!xa)
return NULL;
 
-if (pipe_loader_drm_probe_fd(>dev, dup(drm_fd)))
+if (drm_fd < 0 || (fd = dup(drm_fd)) < 0)
+   goto out_no_fd;
+
+if (pipe_loader_drm_probe_fd(>dev, fd))
xa->screen = pipe_loader_create_screen(xa->dev);
 
 if (!xa->screen)
@@ -208,6 +212,9 @@ xa_tracker_create(int drm_fd)
  out_no_screen:
 if (xa->dev)
pipe_loader_release(>dev, 1);
+fd = -1;
+ out_no_fd:
+close(fd);
 free(xa);
 return NULL;
 }
-- 
2.6.2

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[Mesa-dev] [PATCH 4/5] auxiliary/vl/drm: fd management cleanups

[Emil Velikov]

Analogous to previous commit.

Spotted by Coverity.

Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Emil Velikov 
---
 src/gallium/auxiliary/vl/vl_winsys_drm.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/vl/vl_winsys_drm.c 
b/src/gallium/auxiliary/vl/vl_winsys_drm.c
index f993e2c..6d9d947 100644
--- a/src/gallium/auxiliary/vl/vl_winsys_drm.c
+++ b/src/gallium/auxiliary/vl/vl_winsys_drm.c
@@ -41,12 +41,16 @@ struct vl_screen *
 vl_drm_screen_create(int fd)
 {
struct vl_screen *vscreen;
+   int new_fd = -1;
 
vscreen = CALLOC_STRUCT(vl_screen);
if (!vscreen)
   return NULL;
 
-   if (pipe_loader_drm_probe_fd(>dev, dup(fd)))
+   if (fd < 0 || (new_fd = dup(fd)) < 0)
+  goto error;
+
+   if (pipe_loader_drm_probe_fd(>dev, new_fd))
   vscreen->pscreen = pipe_loader_create_screen(vscreen->dev);
 
if (!vscreen->pscreen)
@@ -63,6 +67,8 @@ vl_drm_screen_create(int fd)
 error:
if (vscreen->dev)
   pipe_loader_release(>dev, 1);
+   else
+  close(new_fd);
 
FREE(vscreen);
return NULL;
-- 
2.6.2

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[Mesa-dev] [PATCH 5/5] auxiliary/vl/dri: fd management cleanups

[Emil Velikov]

Analogous to previous commit, minus the extra dup. We are the one
opening the device thus we can directly use the fd.

Spotted by Coverity.

Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Emil Velikov 
---
 src/gallium/auxiliary/vl/vl_winsys_dri.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/vl/vl_winsys_dri.c 
b/src/gallium/auxiliary/vl/vl_winsys_dri.c
index ae0d4cd..758f50d 100644
--- a/src/gallium/auxiliary/vl/vl_winsys_dri.c
+++ b/src/gallium/auxiliary/vl/vl_winsys_dri.c
@@ -392,7 +392,7 @@ vl_dri2_screen_create(Display *display, int screen)
   goto free_connect;
 
if (drmGetMagic(fd, ))
-  goto free_connect;
+  goto close_fd;
 
authenticate_cookie = xcb_dri2_authenticate_unchecked(scrn->conn,
  get_xcb_screen(s, 
screen)->root,
@@ -402,7 +402,7 @@ vl_dri2_screen_create(Display *display, int screen)
if (authenticate == NULL || !authenticate->authenticated)
   goto free_authenticate;
 
-   if (pipe_loader_drm_probe_fd(>base.dev, dup(fd)))
+   if (pipe_loader_drm_probe_fd(>base.dev, fd))
   scrn->base.pscreen = pipe_loader_create_screen(scrn->base.dev);
 
if (!scrn->base.pscreen)
@@ -428,8 +428,11 @@ vl_dri2_screen_create(Display *display, int screen)
 release_pipe:
if (scrn->base.dev)
   pipe_loader_release(>base.dev, 1);
+   fd = -1;
 free_authenticate:
free(authenticate);
+close_fd:
+   close(fd);
 free_connect:
free(connect);
 free_query:
-- 
2.6.2

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[Mesa-dev] [PATCH 2/5] st/dri: fd management cleanups

[Emil Velikov]

Add some checks if the original/dup'd fd is valid, one and ensure that
we don't leak it on error. In the former case the pipe_loader would
correctly handle things, although let's make things more explicit.

Spotted by Coverity.

Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Emil Velikov 
---
 src/gallium/state_trackers/dri/dri2.c | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/src/gallium/state_trackers/dri/dri2.c 
b/src/gallium/state_trackers/dri/dri2.c
index beb0866..a11a6cb 100644
--- a/src/gallium/state_trackers/dri/dri2.c
+++ b/src/gallium/state_trackers/dri/dri2.c
@@ -1446,6 +1446,7 @@ dri2_init_screen(__DRIscreen * sPriv)
struct pipe_screen *pscreen = NULL;
const struct drm_conf_ret *throttle_ret;
const struct drm_conf_ret *dmabuf_ret;
+   int fd = -1;
 
screen = CALLOC_STRUCT(dri_screen);
if (!screen)
@@ -1457,7 +1458,10 @@ dri2_init_screen(__DRIscreen * sPriv)
 
sPriv->driverPrivate = (void *)screen;
 
-   if (pipe_loader_drm_probe_fd(>dev, dup(screen->fd)))
+   if (screen->fd < 0 || (fd = dup(screen->fd)) < 0)
+  goto fail;
+
+   if (pipe_loader_drm_probe_fd(>dev, fd))
   pscreen = pipe_loader_create_screen(screen->dev);
 
if (!pscreen)
@@ -1502,6 +1506,8 @@ fail:
dri_destroy_screen_helper(screen);
if (screen->dev)
   pipe_loader_release(>dev, 1);
+   else
+  close(fd);
FREE(screen);
return NULL;
 }
@@ -1519,6 +1525,7 @@ dri_kms_init_screen(__DRIscreen * sPriv)
struct dri_screen *screen;
struct pipe_screen *pscreen = NULL;
uint64_t cap;
+   int fd = -1;
 
screen = CALLOC_STRUCT(dri_screen);
if (!screen)
@@ -1529,7 +1536,10 @@ dri_kms_init_screen(__DRIscreen * sPriv)
 
sPriv->driverPrivate = (void *)screen;
 
-   if (pipe_loader_sw_probe_kms(>dev, dup(screen->fd)))
+   if (screen->fd < 0 || (fd = dup(screen->fd)) < 0)
+  goto fail;
+
+   if (pipe_loader_sw_probe_kms(>dev, fd))
   pscreen = pipe_loader_create_screen(screen->dev);
 
if (!pscreen)
@@ -1557,6 +1567,8 @@ fail:
dri_destroy_screen_helper(screen);
if (screen->dev)
   pipe_loader_release(>dev, 1);
+   else
+  close(fd);
FREE(screen);
 #endif // GALLIUM_SOFTPIPE
return NULL;
-- 
2.6.2

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[Mesa-dev] [PATCH] nv50: add edgeflag support when using inline vertex data submit

[Samuel Pitoiset]

Fixes the following piglit tests:
 - gl-1.0-edgeflag
 - gl-1.0-edgeflag-quads
 - gl-2.0-edgeflag
 - gl-2.0-edgeflag-immediate
 - point-vertex-id divisor
 - point-vertex-id gl_InstanceID
 - point-vertex-id gl_InstanceID divisor

I still need to figure out why point-vertex-id fails with gl_vertexID.

Signed-off-by: Samuel Pitoiset 
---
 src/gallium/drivers/nouveau/nv50/nv50_program.c |   5 +-
 src/gallium/drivers/nouveau/nv50/nv50_push.c| 246 
 src/gallium/drivers/nouveau/nv50/nv50_surface.c |   2 +-
 src/gallium/drivers/nouveau/nv50/nv50_vbo.c |   3 +-
 4 files changed, 210 insertions(+), 46 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.c 
b/src/gallium/drivers/nouveau/nv50/nv50_program.c
index a4b8ddf..b904581 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_program.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_program.c
@@ -97,9 +97,6 @@ nv50_vertprog_assign_slots(struct nv50_ir_prog_info *info)
   case TGSI_SEMANTIC_CLIPDIST:
  prog->vp.clpd[info->out[i].si] = n;
  break;
-  case TGSI_SEMANTIC_EDGEFLAG:
- prog->vp.edgeflag = i;
- break;
   case TGSI_SEMANTIC_BCOLOR:
  prog->vp.bfc[info->out[i].si] = i;
  break;
@@ -349,7 +346,6 @@ nv50_program_translate(struct nv50_program *prog, uint16_t 
chipset,
 
prog->vp.bfc[0] = 0xff;
prog->vp.bfc[1] = 0xff;
-   prog->vp.edgeflag = 0xff;
prog->vp.clpd[0] = map_undef;
prog->vp.clpd[1] = map_undef;
prog->vp.psiz = map_undef;
@@ -383,6 +379,7 @@ nv50_program_translate(struct nv50_program *prog, uint16_t 
chipset,
prog->tls_space = info->bin.tlsSpace;
 
prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
+   prog->vp.edgeflag = info->io.edgeFlagIn;
 
if (prog->type == PIPE_SHADER_FRAGMENT) {
   if (info->prop.fp.writesDepth) {
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_push.c 
b/src/gallium/drivers/nouveau/nv50/nv50_push.c
index cbef95d..dae1e34 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_push.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_push.c
@@ -15,9 +15,6 @@ struct push_context {
 
const void *idxbuf;
 
-   float edgeflag;
-   int edgeflag_attr;
-
uint32_t vertex_words;
uint32_t packet_vertex_limit;
 
@@ -31,8 +28,40 @@ struct push_context {
uint32_t prim;
uint32_t restart_index;
uint32_t instance_id;
+
+   struct {
+  bool enabled;
+  bool value;
+  uint8_t width;
+  unsigned stride;
+  const uint8_t *data;
+   } edgeflag;
 };
 
+static inline void
+nv50_push_map_edgeflag(struct push_context *ctx, struct nv50_context *nv50,
+   int32_t index_bias)
+{
+
+   unsigned attr = nv50->vertprog->vp.edgeflag;
+   struct pipe_vertex_element *ve = >vertex->element[attr].pipe;
+   struct pipe_vertex_buffer *vb = >vtxbuf[ve->vertex_buffer_index];
+   struct nv04_resource *buf = nv04_resource(vb->buffer);
+
+   ctx->edgeflag.stride = vb->stride;
+   ctx->edgeflag.width = util_format_get_blocksize(ve->src_format);
+   if (buf) {
+  unsigned offset = vb->buffer_offset + ve->src_offset;
+  ctx->edgeflag.data =
+ nouveau_resource_map_offset(>base, buf, offset, NOUVEAU_BO_RD);
+   } else {
+  ctx->edgeflag.data = (const uint8_t *)vb->user_buffer + ve->src_offset;
+   }
+
+   if (index_bias)
+  ctx->edgeflag.data += (intptr_t)index_bias * vb->stride;
+}
+
 static inline unsigned
 prim_restart_search_i08(uint8_t *elts, unsigned push, uint8_t index)
 {
@@ -63,6 +92,75 @@ prim_restart_search_i32(uint32_t *elts, unsigned push, 
uint32_t index)
return i;
 }
 
+static inline bool
+ef_value_8(const struct push_context *ctx, uint32_t index)
+{
+   uint8_t *pf = (uint8_t *)>edgeflag.data[index * ctx->edgeflag.stride];
+   return !!*pf;
+}
+
+static inline bool
+ef_value_32(const struct push_context *ctx, uint32_t index)
+{
+   uint32_t *pf = (uint32_t *)>edgeflag.data[index * 
ctx->edgeflag.stride];
+   return !!*pf;
+}
+
+static inline bool
+ef_toggle(struct push_context *ctx)
+{
+   ctx->edgeflag.value = !ctx->edgeflag.value;
+   return ctx->edgeflag.value;
+}
+
+static inline unsigned
+ef_toggle_search_i08(struct push_context *ctx, const uint8_t *elts, unsigned n)
+{
+   unsigned i;
+   bool ef = ctx->edgeflag.value;
+   if (ctx->edgeflag.width == 1)
+  for (i = 0; i < n && ef_value_8(ctx, elts[i]) == ef; ++i);
+   else
+  for (i = 0; i < n && ef_value_32(ctx, elts[i]) == ef; ++i);
+   return i;
+}
+
+static inline unsigned
+ef_toggle_search_i16(struct push_context *ctx, const uint16_t *elts, unsigned 
n)
+{
+   unsigned i;
+   bool ef = ctx->edgeflag.value;
+   if (ctx->edgeflag.width == 1)
+  for (i = 0; i < n && ef_value_8(ctx, elts[i]) == ef; ++i);
+   else
+  for (i = 0; i < n && ef_value_32(ctx, elts[i]) == ef; ++i);
+   return i;
+}
+
+static inline unsigned
+ef_toggle_search_i32(struct push_context *ctx, const uint32_t *elts, unsigned 
n)
+{
+   unsigned i;
+   

[Mesa-dev] [Bug 93053] GL_PROGRAM_BINARY_LENGTH always reports 0

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=93053

--- Comment #2 from Tapani Pälli  ---
Mesa does not support program binary extension, you seem to be using a custom
branch (?)

-- 
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Re: [Mesa-dev] [PATCH 3/3] mesa: return initial value for VALIDATE_STATUS if pipe not bound

[Timothy Arceri]

On Mon, 2015-11-23 at 08:28 +0200, Tapani Pälli wrote:
> 
> On 11/22/2015 01:25 PM, Timothy Arceri wrote:
> > On Sun, 2015-11-22 at 11:00 +0100, gregory hainaut wrote:
> > > On Sun, 22 Nov 2015 14:25:31 +1100
> > > Timothy Arceri  wrote:
> > > 
> > > > On Tue, 2015-09-01 at 13:53 +0300, Tapani Pälli wrote:
> > > > >  From OpenGL 4.5 Core spec (7.13):
> > > > > 
> > > > >  "If pipeline is a name that has been generated (without
> > > > > subsequent
> > > > >  deletion) by GenProgramPipelines, but refers to a
> > > > > program
> > > > > pipeline
> > > > >  object that has not been previously bound, the GL first
> > > > > creates
> > > > > a new state vector in the same manner as when
> > > > > BindProgramPipeline
> > > > >  creates a new program pipeline object."
> > > > > 
> > > > > I interpret this as "If GetProgramPipelineiv gets called
> > > > > without
> > > > > a
> > > > > bound (but valid) pipeline object, the state should reflect
> > > > > initial
> > > > > state of a new pipeline object." This is also expected
> > > > > behaviour
> > > > > by
> > > > > ES31-CTS.sepshaderobjs.PipelineApi conformance test.
> > > > > 
> > > > > Signed-off-by: Tapani Pälli 
> > > > > ---
> > > > >   src/mesa/main/pipelineobj.c | 3 ++-
> > > > >   1 file changed, 2 insertions(+), 1 deletion(-)
> > > > > 
> > > > > diff --git a/src/mesa/main/pipelineobj.c
> > > > > b/src/mesa/main/pipelineobj.c
> > > > > index 07acbf1..c2e1d29 100644
> > > > > --- a/src/mesa/main/pipelineobj.c
> > > > > +++ b/src/mesa/main/pipelineobj.c
> > > > > @@ -614,7 +614,8 @@ _mesa_GetProgramPipelineiv(GLuint
> > > > > pipeline,
> > > > > GLenum pname, GLint *params)
> > > > > *params = pipe->InfoLog ? strlen(pipe->InfoLog) + 1 :
> > > > > 0;
> > > > > return;
> > > > >  case GL_VALIDATE_STATUS:
> > > > > -  *params = pipe->Validated;
> > > > > +  /* If pipeline is not bound, return initial value 0.
> > > > > */
> > > > > +  *params = (ctx->_Shader->Name != pipe->Name)
> > > > > ? 0 : pipe->Validated;
> > > > 
> > > > Hi Tapani,
> > > > 
> > > > As Gregory has pointed out this change causes a large number of
> > > > the
> > > > SSO deqp tests to fail.
> > > > 
> > > > I'm not sure what the solution is yet but one thing I have
> > > > noticed
> > > > is
> > > > that with this change we will always return a value of 0 as
> > > > nothing
> > > > ever sets the value of ctx->_Shader->Name.
> > > > 
> > > > I did try setting it when the bind is done but the deqp tests
> > > > still
> > > > fail as the bind is done after the validate in those tests. Are
> > > > you
> > > > sure that this must return 0 if the pipe is not bound?
> > > > 
> > > > Tim
> > > > 
> > > > > return;
> > > > >  case GL_VERTEX_SHADER:
> > > > > *params = pipe->CurrentProgram[MESA_SHADER_VERTEX]
> > > 
> > > Hello,
> > > 
> > > Here my understanding of the specification (with my point of view
> > > of
> > > GL
> > > users).
> > > 
> > > On various objects, gen* cmds reserve a key in a hash table but
> > > objects
> > > aren't created. Generally the object are created when they're
> > > bound
> > > (often call bind to
> > > create). However SSO API is (closer of the/a) direct state access
> > > API. It is really
> > > awkward to bind the object to modify it. Besides there is now
> > > full
> > > DSA.
> > > 
> > > So for me, the following pipeline command must created the object
> > > if
> > > it
> > > wasn't created (read if it wasn't bound)
> > > 
> > > 1/ BindProgramPipeline
> > > 2/ UseProgramStages
> > > 3/ CreateProgramPipelines (???: not sure, but likely)
> > > 4/ ActiveShaderProgram
> > > 5/ GetProgramPipelineiv
> > > 6/ ValidateProgramPipeline
> > > 
> > > Note: can be read as all pipeline commands, so it is nearly
> > > equivalent to
> > > create the object in GenProgramPipelines. The only exception is
> > > IsProgramPipeline.
> > > 
> > > 
> > > So GetProgramPipelineiv (and others gl cmd) must start with:
> > > if (! pipe->IsCreated ) {
> > >  pipe->Init();
> > >  pipe->IsCreated = true;
> > > }
> > > 
> > > 
> > > For example:
> > > GenProgramPipelines(1, );
> > > GetProgramPipelineiv(pipe, X, X); // Must create the object and
> > > therefore will return the initial value (0)
> > > 
> > > GenProgramPipelines(1, );
> > > ValidateProgramPipeline(pipe2); // Will create the object
> > > GetProgramPipelineiv(pipe2, X, X); // object was created by
> > > ValidateProgramPipeline, we can return the property
> > > 
> > > As a side note, if Mesa is updated. Piglit test will need some
> > > updates too.
> > > 
> > > Best regards,
> > > Gregory
> > 
> > I did some digging in the khronos private bugzilla and it seems
> > this
> > issue was resolved and the spec updated to include the following
> > failure case to validation:
> > 
> > "There is no current program object specified byUseProgram, there
> > is
> > acurrent program pipeline object, and that object is 

Re: [Mesa-dev] [PATCH v2] mesa: error out in indirect draw when vertex bindings mismatch

[Fredrik Höglund]

On Thursday 19 November 2015, Tapani Pälli wrote:
> Patch adds additional mask for tracking which vertex buffer bindings
> are set. This array can be directly compared to which vertex arrays
> are enabled and should match when drawing.
> 
> Fixes following CTS tests:
> 
>ES31-CTS.draw_indirect.negative-noVBO-arrays
>ES31-CTS.draw_indirect.negative-noVBO-elements
> 
> v2: update mask in vertex_array_attrib_binding
> 
> Signed-off-by: Tapani Pälli 
> ---
>  src/mesa/main/api_validate.c | 13 +
>  src/mesa/main/mtypes.h   |  3 +++
>  src/mesa/main/varray.c   |  7 +++
>  3 files changed, 23 insertions(+)
> 
> diff --git a/src/mesa/main/api_validate.c b/src/mesa/main/api_validate.c
> index a490189..e82e89a 100644
> --- a/src/mesa/main/api_validate.c
> +++ b/src/mesa/main/api_validate.c
> @@ -710,6 +710,19 @@ valid_draw_indirect(struct gl_context *ctx,
>return GL_FALSE;
> }
>  
> +   /* From OpenGL ES 3.1 spec. section 10.5:
> +* "An INVALID_OPERATION error is generated if zero is bound to
> +* VERTEX_ARRAY_BINDING, DRAW_INDIRECT_BUFFER or to any enabled
> +* vertex array."
> +*
> +* Here we check that vertex buffer bindings match with enabled
> +* vertex arrays.
> +*/
> +   if (ctx->Array.VAO->_Enabled != ctx->Array.VAO->VertexBindingMask) {
> +  _mesa_error(ctx, GL_INVALID_OPERATION, "%s(No VBO bound)", name);
> +  return GL_FALSE;
> +   }
> +
> if (!_mesa_valid_prim_mode(ctx, mode, name))
>return GL_FALSE;
>  
> diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
> index 4efdf1e..6c6187f 100644
> --- a/src/mesa/main/mtypes.h
> +++ b/src/mesa/main/mtypes.h
> @@ -1419,6 +1419,9 @@ struct gl_vertex_array_object
> /** Vertex buffer bindings */
> struct gl_vertex_buffer_binding VertexBinding[VERT_ATTRIB_MAX];
>  
> +   /** Mask indicating which binding points are set. */
> +   GLbitfield64 VertexBindingMask;
> +
> /** Mask of VERT_BIT_* values indicating which arrays are enabled */
> GLbitfield64 _Enabled;
>  
> diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c
> index 887d0c0..e24342a 100644
> --- a/src/mesa/main/varray.c
> +++ b/src/mesa/main/varray.c
> @@ -174,6 +174,11 @@ bind_vertex_buffer(struct gl_context *ctx,
>binding->Offset = offset;
>binding->Stride = stride;
>  
> +  if (vbo == ctx->Shared->NullBufferObj)
> + vao->VertexBindingMask &= ~VERT_BIT(index);
> +  else
> + vao->VertexBindingMask |= VERT_BIT(index);
> +
>vao->NewArrays |= binding->_BoundArrays;
> }
>  }
> @@ -2126,6 +2131,8 @@ vertex_array_attrib_binding(struct gl_context *ctx,
>  
> assert(VERT_ATTRIB_GENERIC(attribIndex) < ARRAY_SIZE(vao->VertexAttrib));
>  
> +   vao->VertexBindingMask |= VERT_BIT_GENERIC(attribIndex);

So there are still a few problems here.  The _Enabled bitfield is a mask
of vertex arrays, while VertexBindingMask is a mask of vertex buffer
binding points.  There is no fixed coupling between these states, so the
two bitfields can't be compared.  Yet valid_draw_indirect() compares them.

bind_vertex_buffer() treats VertexBindingMask as a mask of vertex
buffer bindings, while vertex_array_attrib_binding() treats it as a mask
of vertex arrays.  The latter function also incorrectly assumes that if
the association between an vertex attribute and a buffer binding point is
changed, then the new binding point has a vertex buffer set.

I suggest making VertexBindingMask a mask of vertex arrays instead,
so it can be compared with _Enabled, and renaming it to
VertexAttribBufferMask or something similar.  bind_vertex_buffer()
then needs to be changed to set or clear the _BoundArrays bits in the
mask instead of the index bit.  vertex_array_attrib_binding() also
needs to check if the new binding has a buffer set, and update the
attribIndex bit in the mask accordingly.

> vertex_attrib_binding(ctx, vao,
>   VERT_ATTRIB_GENERIC(attribIndex),
>   VERT_ATTRIB_GENERIC(bindingIndex));
> 

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Re: [Mesa-dev] [PATCH 3/5] i965: Check base format to determine whether to use tiled memcpy

[Neil Roberts]

Ben Widawsky  writes:

> I really don't know the corner cases well enough, but concept seems
> good to me. In particular, I assume this is now going to return false
> for more cases than previously - and that's okay, I guess?

In practice I don't think it will disable any extra formats because the
intel_get_memcpy function which this calls is a lot more strict about
which specific formats it takes anyway. It's a bit weird because
intel_get_memcpy explicitly allows BGRX and RGBX so Jason's original
patch could have been implemented by just removing that explicit
support. However now that the condition is being changed to look at
_BaseFormat instead I think it does make more sense to leave the check
in intel_gettexsubimage_tiled_memcpy.

Regards,
- Neil
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Re: [Mesa-dev] [PATCH 5/5] i965/gen9: Don't allow the RGBX formats for texturing/rendering

[Neil Roberts]

Ben Widawsky  writes:

>> +   /* The RGBX formats are not renderable. Normally these get mapped
>> +* internally to RGBA formats when rendering. However on Gen9+ when this
>> +* internal override is used fast clears don't work so they are disabled 
>> in
>> +* brw_meta_fast_clear. To avoid this problem we can just pretend not to
>> +* support RGBX formats at all. This will cause the upper layers of Mesa 
>> to
>> +* pick the RGBA formats instead. This works fine because when it is used
>
> A lot of these formats are already unsupported for fast clears. In fact, I
> believe only MESA_FORMAT_R8G8B8X8_UNORM is a problem. Are you trying to
> accomplish something else here as well?

I tested all of the formats with the fast-clear Piglit test and I think
all of them are supported for fast clears on MSRTs. Don't forget that
the ccs_e field in the surface_format_info isn't used for MSRTs. The
first three do actually cause failures but for some reason
MESA_FORMAT_RGBX_FLOAT16 does actually work. MESA_FORMAT_RGBX_FLOAT32
isn't used because there is no override to make it use
MESA_FORMAT_RGBA_FLOAT32 as a render target anyway. Presumably that
means it will end up using RGBA for sampling as well and there are
probably going to be some bugs with this format on platforms without
texture swizzle or that the use the blorp so it probably should have
this override. However I think that is a separate patch. If we did fix
that then it would make sense to leave this format in this patch.

Regards,
- Neil
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Re: [Mesa-dev] [PATCH 1/5] i965/gen9: Don't disallow fast clear for MSRT formats matching render

[Neil Roberts]

Ben Widawsky  writes:

>> +  if (brw->gen >= 9 &&
>> +  brw_format_for_mesa_format(irb->mt->format) !=
>> +  brw->render_target_format[irb->mt->format])
>
> Could you just do
> !brw->format_supported_as_render_target[irb->mt->format]?

Hrm, yes, you're right, that would be much neater.

> I forget, did you find failures for this in the non-MSRT case? If not,
> maybe we could skip this patch and just take the rest of the series?
> That way we can avoid the "perf regression" of RGBX clears which we do
> hit on certain workloads.

I couldn't find any regressions for the non-MSRT case. However, it looks
like the RGBX formats don't use fast clears on non-MSRT anyway because
none of them are marked as having lossless compression support. In fact,
if we land the whole series then it should be a performance
*improvement* on non-MSRT because the RGBX clears become RGBA clears
internally and those do support fast clears.

Regards,
- Neil
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[Mesa-dev] [PATCH 1/2] target-hepers: add non inline sw helpers

[Emil Velikov]

Feeling rather dirty copying the inline ones, yet we need the inline
ones for swrast only targets like libgl-xlib, osmesa.

Cc: "11.1" 
Cc: Oded Gabbay 
Cc: Ilia Mirkin 
Cc: Edward O'Callaghan 
Signed-off-by: Emil Velikov 
---
 src/gallium/auxiliary/target-helpers/sw_helper.h   | 73 ++
 .../auxiliary/target-helpers/sw_helper_public.h| 10 +++
 2 files changed, 83 insertions(+)
 create mode 100644 src/gallium/auxiliary/target-helpers/sw_helper.h
 create mode 100644 src/gallium/auxiliary/target-helpers/sw_helper_public.h

diff --git a/src/gallium/auxiliary/target-helpers/sw_helper.h 
b/src/gallium/auxiliary/target-helpers/sw_helper.h
new file mode 100644
index 000..ae5f3de
--- /dev/null
+++ b/src/gallium/auxiliary/target-helpers/sw_helper.h
@@ -0,0 +1,73 @@
+
+#ifndef SW_HELPER_H
+#define SW_HELPER_H
+
+#include "pipe/p_compiler.h"
+#include "util/u_debug.h"
+#include "target-helpers/sw_helper_public.h"
+#include "state_tracker/sw_winsys.h"
+
+
+/* Helper function to choose and instantiate one of the software rasterizers:
+ * llvmpipe, softpipe.
+ */
+
+#ifdef GALLIUM_SOFTPIPE
+#include "softpipe/sp_public.h"
+#endif
+
+#ifdef GALLIUM_LLVMPIPE
+#include "llvmpipe/lp_public.h"
+#endif
+
+#ifdef GALLIUM_VIRGL
+#include "virgl/virgl_public.h"
+#include "virgl/vtest/virgl_vtest_public.h"
+#endif
+
+static inline struct pipe_screen *
+sw_screen_create_named(struct sw_winsys *winsys, const char *driver)
+{
+   struct pipe_screen *screen = NULL;
+
+#if defined(GALLIUM_LLVMPIPE)
+   if (screen == NULL && strcmp(driver, "llvmpipe") == 0)
+  screen = llvmpipe_create_screen(winsys);
+#endif
+
+#if defined(GALLIUM_VIRGL)
+   if (screen == NULL && strcmp(driver, "virpipe") == 0) {
+  struct virgl_winsys *vws;
+  vws = virgl_vtest_winsys_wrap(winsys);
+  screen = virgl_create_screen(vws);
+   }
+#endif
+
+#if defined(GALLIUM_SOFTPIPE)
+   if (screen == NULL)
+  screen = softpipe_create_screen(winsys);
+#endif
+
+   return screen;
+}
+
+
+struct pipe_screen *
+sw_screen_create(struct sw_winsys *winsys)
+{
+   const char *default_driver;
+   const char *driver;
+
+#if defined(GALLIUM_LLVMPIPE)
+   default_driver = "llvmpipe";
+#elif defined(GALLIUM_SOFTPIPE)
+   default_driver = "softpipe";
+#else
+   default_driver = "";
+#endif
+
+   driver = debug_get_option("GALLIUM_DRIVER", default_driver);
+   return sw_screen_create_named(winsys, driver);
+}
+
+#endif
diff --git a/src/gallium/auxiliary/target-helpers/sw_helper_public.h 
b/src/gallium/auxiliary/target-helpers/sw_helper_public.h
new file mode 100644
index 000..12b301b
--- /dev/null
+++ b/src/gallium/auxiliary/target-helpers/sw_helper_public.h
@@ -0,0 +1,10 @@
+#ifndef _SW_HELPER_PUBLIC_H
+#define _SW_HELPER_PUBLIC_H
+
+struct pipe_screen;
+struct sw_winsys;
+
+struct pipe_screen *
+sw_screen_create(struct sw_winsys *winsys);
+
+#endif /* _SW_HELPER_PUBLIC_H */
-- 
2.6.2

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[Mesa-dev] [PATCH 2/2] targets/dri: use the non-inline sw helpers

[Emil Velikov]

Previously (with the inline ones) things were embedded into the
pipe-loader, which means that we cannot control/select what we want in
each target.

Cc: "11.1" 
Cc: Oded Gabbay 
Cc: Ilia Mirkin 
Cc: Edward O'Callaghan 
Signed-off-by: Emil Velikov 
---
 src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c | 3 ++-
 src/gallium/targets/dri/target.c   | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c 
b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
index 5539a73..1c38750 100644
--- a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
+++ b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
@@ -33,9 +33,10 @@
 #include "sw/kms-dri/kms_dri_sw_winsys.h"
 #include "sw/null/null_sw_winsys.h"
 #include "sw/wrapper/wrapper_sw_winsys.h"
-#include "target-helpers/inline_sw_helper.h"
+#include "target-helpers/sw_helper_public.h"
 #include "state_tracker/drisw_api.h"
 #include "state_tracker/sw_driver.h"
+#include "state_tracker/sw_winsys.h"
 
 struct pipe_loader_sw_device {
struct pipe_loader_device base;
diff --git a/src/gallium/targets/dri/target.c b/src/gallium/targets/dri/target.c
index d6fbd01..01532e2 100644
--- a/src/gallium/targets/dri/target.c
+++ b/src/gallium/targets/dri/target.c
@@ -1,4 +1,5 @@
 #include "target-helpers/drm_helper.h"
+#include "target-helpers/sw_helper.h"
 
 #include "dri_screen.h"
 
-- 
2.6.2

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Re: [Mesa-dev] [PATCH v2] mesa: error out in indirect draw when vertex bindings mismatch

[Tapani Pälli]

On 11/23/2015 11:17 AM, Fredrik Höglund wrote:

On Thursday 19 November 2015, Tapani Pälli wrote:

Patch adds additional mask for tracking which vertex buffer bindings
are set. This array can be directly compared to which vertex arrays
are enabled and should match when drawing.

Fixes following CTS tests:

ES31-CTS.draw_indirect.negative-noVBO-arrays
ES31-CTS.draw_indirect.negative-noVBO-elements

v2: update mask in vertex_array_attrib_binding

Signed-off-by: Tapani Pälli 
---
  src/mesa/main/api_validate.c | 13 +
  src/mesa/main/mtypes.h   |  3 +++
  src/mesa/main/varray.c   |  7 +++
  3 files changed, 23 insertions(+)

diff --git a/src/mesa/main/api_validate.c b/src/mesa/main/api_validate.c
index a490189..e82e89a 100644
--- a/src/mesa/main/api_validate.c
+++ b/src/mesa/main/api_validate.c
@@ -710,6 +710,19 @@ valid_draw_indirect(struct gl_context *ctx,
return GL_FALSE;
 }

+   /* From OpenGL ES 3.1 spec. section 10.5:
+* "An INVALID_OPERATION error is generated if zero is bound to
+* VERTEX_ARRAY_BINDING, DRAW_INDIRECT_BUFFER or to any enabled
+* vertex array."
+*
+* Here we check that vertex buffer bindings match with enabled
+* vertex arrays.
+*/
+   if (ctx->Array.VAO->_Enabled != ctx->Array.VAO->VertexBindingMask) {
+  _mesa_error(ctx, GL_INVALID_OPERATION, "%s(No VBO bound)", name);
+  return GL_FALSE;
+   }
+
 if (!_mesa_valid_prim_mode(ctx, mode, name))
return GL_FALSE;

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 4efdf1e..6c6187f 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1419,6 +1419,9 @@ struct gl_vertex_array_object
 /** Vertex buffer bindings */
 struct gl_vertex_buffer_binding VertexBinding[VERT_ATTRIB_MAX];

+   /** Mask indicating which binding points are set. */
+   GLbitfield64 VertexBindingMask;
+
 /** Mask of VERT_BIT_* values indicating which arrays are enabled */
 GLbitfield64 _Enabled;

diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c
index 887d0c0..e24342a 100644
--- a/src/mesa/main/varray.c
+++ b/src/mesa/main/varray.c
@@ -174,6 +174,11 @@ bind_vertex_buffer(struct gl_context *ctx,
binding->Offset = offset;
binding->Stride = stride;

+  if (vbo == ctx->Shared->NullBufferObj)
+ vao->VertexBindingMask &= ~VERT_BIT(index);
+  else
+ vao->VertexBindingMask |= VERT_BIT(index);
+
vao->NewArrays |= binding->_BoundArrays;
 }
  }
@@ -2126,6 +2131,8 @@ vertex_array_attrib_binding(struct gl_context *ctx,

 assert(VERT_ATTRIB_GENERIC(attribIndex) < ARRAY_SIZE(vao->VertexAttrib));

+   vao->VertexBindingMask |= VERT_BIT_GENERIC(attribIndex);


So there are still a few problems here.  The _Enabled bitfield is a mask
of vertex arrays, while VertexBindingMask is a mask of vertex buffer
binding points.  There is no fixed coupling between these states, so the
two bitfields can't be compared.  Yet valid_draw_indirect() compares them.

bind_vertex_buffer() treats VertexBindingMask as a mask of vertex
buffer bindings, while vertex_array_attrib_binding() treats it as a mask
of vertex arrays.  The latter function also incorrectly assumes that if
the association between an vertex attribute and a buffer binding point is
changed, then the new binding point has a vertex buffer set.


There is perhaps some confusion with the name here, I agree that name of 
the mask is bad and suggested 'VertexAttribBufferMask' would be much 
better. Mask exists to check 'which vertex arrays have been associated 
with a vertex buffer', it is definitely not a 'mask of vertex buffer 
binding points' like you state above. My intention is that I'm setting 
those vertex array bits that have a vertex buffer and when drawing that 
needs to match which arrays are enabled.


Following that logic, bind_vertex_buffer() sets the bit for the vertex 
array which some buffer was bound for and in 
vertex_array_attrib_binding() we update bit of vertex array in the mask 
in same manner.


It is true that there is no check if such vbo exists, so if I understand 
you correctly this is what is actually missing?




I suggest making VertexBindingMask a mask of vertex arrays instead,
so it can be compared with _Enabled, and renaming it to
VertexAttribBufferMask or something similar.  bind_vertex_buffer()
then needs to be changed to set or clear the _BoundArrays bits in the
mask instead of the index bit.  vertex_array_attrib_binding() also
needs to check if the new binding has a buffer set, and update the
attribIndex bit in the mask accordingly.


 vertex_attrib_binding(ctx, vao,
   VERT_ATTRIB_GENERIC(attribIndex),
   VERT_ATTRIB_GENERIC(bindingIndex));



OK, I'll see how this would look. As it is legal to call 
glVertexAttribBinding with a binding index that does not have existing 
vbo I'm not sure if using BoundArrays makes this any 

Re: [Mesa-dev] [PATCH 1/5] i965/gen9: Don't disallow fast clear for MSRT formats matching render

[Neil Roberts]

> Ben Widawsky  writes:
>
>>> +  if (brw->gen >= 9 &&
>>> +  brw_format_for_mesa_format(irb->mt->format) !=
>>> +  brw->render_target_format[irb->mt->format])
>>
>> Could you just do
>> !brw->format_supported_as_render_target[irb->mt->format]?

Neil Roberts  writes:

> Hrm, yes, you're right, that would be much neater.

Oh wait, no, that won't work because the formats that have this render
target override are marked as renderable.

Regards,
- Neil
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Re: [Mesa-dev] [PATCH 3/3] mesa: return initial value for VALIDATE_STATUS if pipe not bound

[Tapani Pälli]

On 11/23/2015 10:18 AM, Timothy Arceri wrote:

On Mon, 2015-11-23 at 08:28 +0200, Tapani Pälli wrote:


On 11/22/2015 01:25 PM, Timothy Arceri wrote:

On Sun, 2015-11-22 at 11:00 +0100, gregory hainaut wrote:

On Sun, 22 Nov 2015 14:25:31 +1100
Timothy Arceri  wrote:


On Tue, 2015-09-01 at 13:53 +0300, Tapani Pälli wrote:

  From OpenGL 4.5 Core spec (7.13):

  "If pipeline is a name that has been generated (without
subsequent
  deletion) by GenProgramPipelines, but refers to a
program
pipeline
  object that has not been previously bound, the GL first
creates
a new state vector in the same manner as when
BindProgramPipeline
  creates a new program pipeline object."

I interpret this as "If GetProgramPipelineiv gets called
without
a
bound (but valid) pipeline object, the state should reflect
initial
state of a new pipeline object." This is also expected
behaviour
by
ES31-CTS.sepshaderobjs.PipelineApi conformance test.

Signed-off-by: Tapani Pälli 
---
   src/mesa/main/pipelineobj.c | 3 ++-
   1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/main/pipelineobj.c
b/src/mesa/main/pipelineobj.c
index 07acbf1..c2e1d29 100644
--- a/src/mesa/main/pipelineobj.c
+++ b/src/mesa/main/pipelineobj.c
@@ -614,7 +614,8 @@ _mesa_GetProgramPipelineiv(GLuint
pipeline,
GLenum pname, GLint *params)
 *params = pipe->InfoLog ? strlen(pipe->InfoLog) + 1 :
0;
 return;
  case GL_VALIDATE_STATUS:
-  *params = pipe->Validated;
+  /* If pipeline is not bound, return initial value 0.
*/
+  *params = (ctx->_Shader->Name != pipe->Name)
? 0 : pipe->Validated;


Hi Tapani,

As Gregory has pointed out this change causes a large number of
the
SSO deqp tests to fail.

I'm not sure what the solution is yet but one thing I have
noticed
is
that with this change we will always return a value of 0 as
nothing
ever sets the value of ctx->_Shader->Name.

I did try setting it when the bind is done but the deqp tests
still
fail as the bind is done after the validate in those tests. Are
you
sure that this must return 0 if the pipe is not bound?

Tim


 return;
  case GL_VERTEX_SHADER:
 *params = pipe->CurrentProgram[MESA_SHADER_VERTEX]


Hello,

Here my understanding of the specification (with my point of view
of
GL
users).

On various objects, gen* cmds reserve a key in a hash table but
objects
aren't created. Generally the object are created when they're
bound
(often call bind to
create). However SSO API is (closer of the/a) direct state access
API. It is really
awkward to bind the object to modify it. Besides there is now
full
DSA.

So for me, the following pipeline command must created the object
if
it
wasn't created (read if it wasn't bound)

1/ BindProgramPipeline
2/ UseProgramStages
3/ CreateProgramPipelines (???: not sure, but likely)
4/ ActiveShaderProgram
5/ GetProgramPipelineiv
6/ ValidateProgramPipeline

Note: can be read as all pipeline commands, so it is nearly
equivalent to
create the object in GenProgramPipelines. The only exception is
IsProgramPipeline.


So GetProgramPipelineiv (and others gl cmd) must start with:
if (! pipe->IsCreated ) {
  pipe->Init();
  pipe->IsCreated = true;
}


For example:
GenProgramPipelines(1, );
GetProgramPipelineiv(pipe, X, X); // Must create the object and
therefore will return the initial value (0)

GenProgramPipelines(1, );
ValidateProgramPipeline(pipe2); // Will create the object
GetProgramPipelineiv(pipe2, X, X); // object was created by
ValidateProgramPipeline, we can return the property

As a side note, if Mesa is updated. Piglit test will need some
updates too.

Best regards,
Gregory


I did some digging in the khronos private bugzilla and it seems
this
issue was resolved and the spec updated to include the following
failure case to validation:

"There is no current program object specified byUseProgram, there
is
acurrent program pipeline object, and that object is empty (no
executable code is installed for any stage)."

So it seems the CTS is correct and the DEQP tests are wrong.

However as I pointed out I think this patch is still broken as
_Shader
->Name is always 0 currently as far as I could tell.


IMO the check done by this patch is valid, Name field has the name of
currently bound program pipeline, it changes when current pipeline
object gets changed. If name does not match the pipeline given to
GetProgramPipelineiv it means it is not bound. If you call
BindProgramPipeline, Name changes.


Right thanks, I wasn't saying it wasn't correct to do the check just
that I couldn't see where name was set. I see how it works now, thanks.

Not a big deal but the check should probably be moved into the validate
function as it is one of the validation rules.


There is check in validation if pipeline is bound because validation can 
be also run against a pipeline that is not bound. In this case there is 
some difference in error reporting compared to running 

[Mesa-dev] nouveau -> dmabuf -> intel seems to requires linear layout

[Julien Isorce]

Hi,

I tried zero-copy decoding with the following scheme:
"nouveau" HW decoding -> dmabuf -> intel GL
but it showed garbage. Colors looked okish but not pixel positions.

(note that nouveau dec -> dmabuf -> nouveau GL and  intel dec -> dmabuf ->
intel GL are both working)

So I was thinking a problem with the layout. So the hack from attached
patch made it work :)
EGL_EXT_image_dma_buf_import does not mention anything about layout, only
some hints for YUVs.

I would appreciate any feedback on this. Thx

Infos:
Linux 4.4
Mesa latest master
GPU1: GeForce GT 750M
GPU2: Haswell

Cheers
Julien

PS: Note that in all cases, there is an extra step to convert NV12 to RGBX
which is done in HW (through VA-API - Post Processing)
Indeed vaAcquireBufferHandle only allow to export contiguous memory which
is not the case for nouveau (templ.target = PIPE_TEXTURE_2D_ARRAY)
From e47d127a891b1469f1255c11d0a2ed2a0b477c0e Mon Sep 17 00:00:00 2001
From: Julien Isorce 
Date: Mon, 23 Nov 2015 09:20:14 +
Subject: [PATCH] WIP: force linear layout for RGBA/RGBX

Signed-off-by: Julien Isorce 
---
 src/gallium/auxiliary/vl/vl_video_buffer.c  | 10 +-
 src/gallium/drivers/nouveau/nouveau_vp3_video.c |  3 +++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/vl/vl_video_buffer.c b/src/gallium/auxiliary/vl/vl_video_buffer.c
index 6cd2557..c683afb 100644
--- a/src/gallium/auxiliary/vl/vl_video_buffer.c
+++ b/src/gallium/auxiliary/vl/vl_video_buffer.c
@@ -114,8 +114,9 @@ vl_video_buffer_formats(struct pipe_screen *screen, enum pipe_format format)
case PIPE_FORMAT_B8G8R8A8_UNORM:
   return const_resource_formats_VUYA;
 
+   // XXX: submit this separately
case PIPE_FORMAT_R8G8B8X8_UNORM:
-  return const_resource_formats_VUYX;
+  return const_resource_formats_YUVX;
 
case PIPE_FORMAT_B8G8R8X8_UNORM:
   return const_resource_formats_VUYX;
@@ -253,6 +254,13 @@ vl_video_buffer_template(struct pipe_resource *templ,
templ->bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET;
templ->usage = usage;
 
+   // XXX. This is a hack to force linear layout.
+   if (tmpl->buffer_format == PIPE_FORMAT_B8G8R8A8_UNORM  ||
+   tmpl->buffer_format == PIPE_FORMAT_R8G8B8A8_UNORM  ||
+   tmpl->buffer_format == PIPE_FORMAT_B8G8R8X8_UNORM  ||
+   tmpl->buffer_format == PIPE_FORMAT_R8G8B8X8_UNORM)
+  templ->bind |= PIPE_BIND_LINEAR;
+
if (plane > 0) {
   if (tmpl->chroma_format == PIPE_VIDEO_CHROMA_FORMAT_420) {
  templ->width0 /= 2;
diff --git a/src/gallium/drivers/nouveau/nouveau_vp3_video.c b/src/gallium/drivers/nouveau/nouveau_vp3_video.c
index d76d932..5e1d327 100644
--- a/src/gallium/drivers/nouveau/nouveau_vp3_video.c
+++ b/src/gallium/drivers/nouveau/nouveau_vp3_video.c
@@ -83,6 +83,9 @@ nouveau_vp3_video_buffer_create(struct pipe_context *pipe,
struct pipe_sampler_view sv_templ;
struct pipe_surface surf_templ;
 
+   // XXX Note that NVC0_RESOURCE_FLAG_VIDEO is lost when calling
+   // nvc0_video_buffer_create -> nouveau_vp3_video_buffer_create
+   // -> vl_video_buffer_create if format is not NV12.
if (getenv("XVMC_VL") || templat->buffer_format != PIPE_FORMAT_NV12)
   return vl_video_buffer_create(pipe, templat);
 
-- 
1.9.1

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Re: [Mesa-dev] [Mesa-announce] Mesa 11.1.0 release candidate 1

[Emil Velikov]

On 23 November 2015 at 09:18, Thierry Vignaud  wrote:
> On 21 November 2015 at 15:28, Emil Velikov  wrote:
>> The first release candidate for Mesa 11.1.0 is now available.
>>
>> The plan is to have one release candidate every Friday, until the final
>> release on December 11th 2015.
>>
>> As a reminder, with the 11.1 branch now created, patches nominated with:
>>
>> CC: 
>>
>> will now be candidates only for the new 11.1 branch. To nominate patches
>> for the older 11.0 branch as well, please use:
>>
>> CC: "11.0 11.1" 
>>
>> The expectation is that the 11.0 branch will remain alive with bi-weekly
>> releases until after 11.1.1 release.
>
> It failed to build when we tried it yesterday on Mageia.
> See
> http://pkgsubmit.mageia.org/uploads/failure/cauldron/core/release/20151122205943.tv.valstar.4312/log/mesa-11.1.0~rc1-1.mga6/build.0.20151122210002.log
>
>   CC   libloader_la-loader.lo
> In file included from loader.c:93:0:
> pci_id_driver_map.h:16:34: fatal error: pci_ids/i915_pci_ids.h: No
> such file or directory
> compilation terminated.
> Makefile:628: recipe for target 'libloader_la-loader.lo' failed

Just pushed three patches which should resolve this + related issues.

http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a6d4765880a2c9000970b2b6e584291090b1dc3
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9b0a1f58e41ba4027a16300393835dc8c632f50
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b89d1b2ccf16c0bee3708560b69e99b6dbb212f0

They will make it into rc2 coming later this week.

Thanks
Emil
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Re: [Mesa-dev] [PATCH] glsl: implement recent spec update to SSO validation

[Timothy Arceri]

On Mon, 2015-11-23 at 23:24 +1100, Timothy Arceri wrote:
> From: Timothy Arceri 
> 
> Enables 200+ dEQP SSO tests to proceed passed validation,
> while not regressing ES31-CTS.sepshaderobjs.PipelineApi.
> 
> Cc: Tapani Pälli 
> Cc: Gregory Hainaut 
> ---
>  src/mesa/main/pipelineobj.c | 25 -
>  1 file changed, 24 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/main/pipelineobj.c
> b/src/mesa/main/pipelineobj.c
> index 90dff13..99e1491 100644
> --- a/src/mesa/main/pipelineobj.c
> +++ b/src/mesa/main/pipelineobj.c
> @@ -646,7 +646,7 @@ _mesa_GetProgramPipelineiv(GLuint pipeline,
> GLenum pname, GLint *params)
>return;
> case GL_VALIDATE_STATUS:
>/* If pipeline is not bound, return initial value 0. */

Whoops, I've removed this comment locally also.

> -  *params = (ctx->_Shader->Name != pipe->Name) ? 0 : pipe
> ->Validated;
> +  *params = pipe->Validated;
>return;
> case GL_VERTEX_SHADER:
>*params = pipe->CurrentProgram[MESA_SHADER_VERTEX]
> @@ -858,6 +858,29 @@ _mesa_validate_program_pipeline(struct
> gl_context* ctx,
>}
> }
>  
> +   /* Section 11.1.3.11 (Validation) of the OpenGL 4.5 spec says:
> +*
> +*"An INVALID_OPERATION error is generated by any command
> that trans-
> +*fers vertices to the GL or launches compute work if the
> current set
> +*of active program objects cannot be executed, for reasons
> including:
> +*
> +*   ...
> +*
> +*   - There is no current program object specified by
> UseProgram,
> +* there is a current program pipeline object, and that
> object is
> +* empty (no executable code is installed for any stage).
> +*/
> +   bool program_empty = true;
> +   for (i = 0; i < MESA_SHADER_STAGES; i++) {
> +  if (pipe->CurrentProgram[i]) {
> + program_empty = false;
> + break;
> +  }
> +   }
> +   if(program_empty) {
> +  goto err;
> +   }
> +
> /* Section 2.11.11 (Shader Execution), subheading "Validation,"
> of the
>  * OpenGL 4.1 spec says:
>  *
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[Mesa-dev] [PATCH 0/2] Improve emitted code for copies of large buffer-backed variables

[Iago Toral Quiroga]

Fixes linking issues when copying large variables backed by buffers (ubos, 
ssbos, etc).
In these cases, lower_ubo_reference would split the rhs into loads for all the 
elements 
first and then the lhs into writes to all the elements. This is not efficient, 
because
it requires the whole set of loads to be alive until we start consuming them 
with
the writes.   

These patches fix this by splitting array and struct copies into multiple
single-element copies so that we generate consecutive loads and stores for each
element, reducing the lifespan of the loads and thus reducing register pressure.

No regressions in dEQP's SSBO functional tests.

Fixes:
spec/arb_shader_storage_buffer_object/execution/large-field-copy.shader_test
spec/arb_shader_storage_buffer_object/linker/copy-large-array.shader_test

Iago Toral Quiroga (2):
  glsl/lower_ubo_reference: split array copies into element copies
  glsl/lower_ubo_reference: split struct copies into element copies

 src/glsl/lower_ubo_reference.cpp | 119 +++
 1 file changed, 119 insertions(+)

-- 
1.9.1

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Re: [Mesa-dev] [PATCH] glsl: implement recent spec update to SSO validation

[Gregory Hainaut]

Thanks. Yes I think it must be this way. I said the same to Tapani 1
hour ago (but stupid gmail didn't reply all...).

On 11/23/15, Timothy Arceri  wrote:
> On Mon, 2015-11-23 at 23:24 +1100, Timothy Arceri wrote:
>> From: Timothy Arceri 
>>
>> Enables 200+ dEQP SSO tests to proceed passed validation,
>> while not regressing ES31-CTS.sepshaderobjs.PipelineApi.
>>
>> Cc: Tapani Pälli 
>> Cc: Gregory Hainaut 
>> ---
>>  src/mesa/main/pipelineobj.c | 25 -
>>  1 file changed, 24 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/mesa/main/pipelineobj.c
>> b/src/mesa/main/pipelineobj.c
>> index 90dff13..99e1491 100644
>> --- a/src/mesa/main/pipelineobj.c
>> +++ b/src/mesa/main/pipelineobj.c
>> @@ -646,7 +646,7 @@ _mesa_GetProgramPipelineiv(GLuint pipeline,
>> GLenum pname, GLint *params)
>>return;
>> case GL_VALIDATE_STATUS:
>>/* If pipeline is not bound, return initial value 0. */
>
> Whoops, I've removed this comment locally also.
>
>> -  *params = (ctx->_Shader->Name != pipe->Name) ? 0 : pipe
>> ->Validated;
>> +  *params = pipe->Validated;
>>return;
>> case GL_VERTEX_SHADER:
>>*params = pipe->CurrentProgram[MESA_SHADER_VERTEX]
>> @@ -858,6 +858,29 @@ _mesa_validate_program_pipeline(struct
>> gl_context* ctx,
>>}
>> }
>>
>> +   /* Section 11.1.3.11 (Validation) of the OpenGL 4.5 spec says:
>> +*
>> +*"An INVALID_OPERATION error is generated by any command
>> that trans-
>> +*fers vertices to the GL or launches compute work if the
>> current set
>> +*of active program objects cannot be executed, for reasons
>> including:
>> +*
>> +*   ...
>> +*
>> +*   - There is no current program object specified by
>> UseProgram,
>> +* there is a current program pipeline object, and that
>> object is
>> +* empty (no executable code is installed for any stage).
>> +*/
>> +   bool program_empty = true;
>> +   for (i = 0; i < MESA_SHADER_STAGES; i++) {
>> +  if (pipe->CurrentProgram[i]) {
>> + program_empty = false;
>> + break;
>> +  }
>> +   }
>> +   if(program_empty) {
>> +  goto err;
>> +   }
>> +
>> /* Section 2.11.11 (Shader Execution), subheading "Validation,"
>> of the
>>  * OpenGL 4.1 spec says:
>>  *
>
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Re: [Mesa-dev] [PATCH] gallium: build virgl by default.

[Marek Olšák]

On Mon, Nov 23, 2015 at 12:41 PM, Emil Velikov  wrote:
> On 23 November 2015 at 07:57, Albert Freeman  
> wrote:
>> On 23 November 2015 at 03:17, Ilia Mirkin  wrote:
>>> On Sun, Nov 22, 2015 at 9:28 PM, Dave Airlie  wrote:
 From: Dave Airlie 

 No reason not to build this, it has no external
 requirements at the moment.
>>>
>>> Not that I object, but what's the policy around these defaults? Should
>>> we also add nouveau? freedreno? vc4?
>>>
> Yes please.
>
> For those wondering about radeonsi, i915g or ilo. The first one has
> llvm dependency which we cannot enforce onto the unaware user. With
> the latter two - while I cannot comment on their quality/completeness,
> they see almost no action (dev. wise) plus having them will bring
> serious classic vs gallium confusion.

r300 also depends on LLVM. It can be worked around by modifying
configure.ac, but you can't build r300 without llvm on x86 by default.
(the reason is that some r300 IGPs don't have vertex shaders and draw
is used instead, which is terribly slow without llvm)

Marek
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Re: [Mesa-dev] [PATCH 2/3] i965: Use implicit backend_reg copy-constructor.

[Francisco Jerez]

Matt Turner  writes:

> In order to do this, we have to change the signature of the
> backend_reg(brw_reg) constructor to take a reference to a brw_reg in
> order to avoid unresolvable ambiguity about which constructor is
> actually being called in the other modifications in this patch.
>
> As far as I understand it, the rule in C++ is that if multiple
> constructors are available for parent classes, the one closest to you in
> the class heirarchy is closen, but if one of them didn't take a
> reference, that screws things up.

I believe that the reason is that the ordering between more and less
derived classes is only defined for values of the same kind, i.e. a
conversion from 'const src_reg &' to 'const backend_reg &' is considered
a better match than 'const src_reg &' to 'const brw_reg &', and a
conversion from 'src_reg' to backend_reg' would have been considered
better than 'src_reg' to 'brw_reg', but that doesn't necessarily
disambiguate between the conversions to 'const backend_reg &' and
'brw_reg'.  Anyway there was no good reason to pass the brw_reg object
by value.  For the series:

Reviewed-by: Francisco Jerez 

> ---
>  src/mesa/drivers/dri/i965/brw_shader.h | 2 +-
>  src/mesa/drivers/dri/i965/brw_vec4.cpp | 6 ++
>  2 files changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.h 
> b/src/mesa/drivers/dri/i965/brw_shader.h
> index 718a225..abf04cf 100644
> --- a/src/mesa/drivers/dri/i965/brw_shader.h
> +++ b/src/mesa/drivers/dri/i965/brw_shader.h
> @@ -42,7 +42,7 @@
>  struct backend_reg : public brw_reg
>  {
> backend_reg() {}
> -   backend_reg(struct brw_reg reg) : brw_reg(reg) {}
> +   backend_reg(const struct brw_reg ) : brw_reg(reg) {}
>  
> bool equals(const backend_reg ) const;
>  
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> index a23fd82..60b2fed 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> @@ -79,9 +79,8 @@ src_reg::src_reg(struct brw_reg reg) :
>  }
>  
>  src_reg::src_reg(const dst_reg ) :
> -   backend_reg(static_cast(reg))
> +   backend_reg(reg)
>  {
> -   this->reg_offset = reg.reg_offset;
> this->reladdr = reg.reladdr;
> this->swizzle = brw_swizzle_for_mask(reg.writemask);
>  }
> @@ -137,9 +136,8 @@ dst_reg::dst_reg(struct brw_reg reg) :
>  }
>  
>  dst_reg::dst_reg(const src_reg ) :
> -   backend_reg(static_cast(reg))
> +   backend_reg(reg)
>  {
> -   this->reg_offset = reg.reg_offset;
> this->writemask = brw_mask_for_swizzle(reg.swizzle);
> this->reladdr = reg.reladdr;
>  }
> -- 
> 2.4.9


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Re: [Mesa-dev] [PATCH] gallium: build virgl by default.

[Emil Velikov]

On 23 November 2015 at 07:57, Albert Freeman  wrote:
> On 23 November 2015 at 03:17, Ilia Mirkin  wrote:
>> On Sun, Nov 22, 2015 at 9:28 PM, Dave Airlie  wrote:
>>> From: Dave Airlie 
>>>
>>> No reason not to build this, it has no external
>>> requirements at the moment.
>>
>> Not that I object, but what's the policy around these defaults? Should
>> we also add nouveau? freedreno? vc4?
>>
Yes please.

For those wondering about radeonsi, i915g or ilo. The first one has
llvm dependency which we cannot enforce onto the unaware user. With
the latter two - while I cannot comment on their quality/completeness,
they see almost no action (dev. wise) plus having them will bring
serious classic vs gallium confusion.

>> Of course my personal preference would be to just error the build if
>> no drivers are specified... but I guess that won't work for some
>> people?
Ideal case will be to 1) select everything regardless of dependencies
or 2) select the ones that have their dependencies resolved. I'm
leaning towards the latter, although that'll need a lot churn.

> I do agree with this, it will cause some of those people to look
> through all the gallium drivers to see which ones they need (maybe
> that will result in them using more...), reduce compilation time and
> decrease used storage space. It should also prevent people from not
> including the drivers they need (only for gallium drivers). Of course
> it will break a few peoples builds (though they will also reap the
> benefits), but almost everyone uses the flag.
>
In practise most (99%?) people building mesa provide their own drivers
list. The default list covers the remaining people, which have little
to no idea what they want/need. Thus building everything * (see note
above) is the reasonable thing to do.

Once people get the feel - "I want vc4/nouveau/etc", they can tweak
the list and get compilation time/size savings.

> The only other fair alternative is to build all the drivers, which has
> a negative impact on all those points (excluding broken builds) +
> dependency issues (other broken builds (less though: some people would
> have the required dependencies)).
>>
>>>
>>> Signed-off-by: Dave Airlie 

Dave feel free to add:

Reviewed-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] [PATCH] gallium: build virgl by default.

[Emil Velikov]

On 23 November 2015 at 11:49, Marek Olšák  wrote:
> On Mon, Nov 23, 2015 at 12:41 PM, Emil Velikov  
> wrote:
>> On 23 November 2015 at 07:57, Albert Freeman  
>> wrote:
>>> On 23 November 2015 at 03:17, Ilia Mirkin  wrote:
 On Sun, Nov 22, 2015 at 9:28 PM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> No reason not to build this, it has no external
> requirements at the moment.

 Not that I object, but what's the policy around these defaults? Should
 we also add nouveau? freedreno? vc4?

>> Yes please.
>>
>> For those wondering about radeonsi, i915g or ilo. The first one has
>> llvm dependency which we cannot enforce onto the unaware user. With
>> the latter two - while I cannot comment on their quality/completeness,
>> they see almost no action (dev. wise) plus having them will bring
>> serious classic vs gallium confusion.
>
> r300 also depends on LLVM. It can be worked around by modifying
> configure.ac, but you can't build r300 without llvm on x86 by default.
> (the reason is that some r300 IGPs don't have vertex shaders and draw
> is used instead, which is terribly slow without llvm)
>
As you pointed out the r300+llvm+x86 story is slightly different.

-Emil
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[Mesa-dev] [PATCH] glsl: implement recent spec update to SSO validation

[Timothy Arceri]

From: Timothy Arceri 

Enables 200+ dEQP SSO tests to proceed passed validation,
while not regressing ES31-CTS.sepshaderobjs.PipelineApi.

Cc: Tapani Pälli 
Cc: Gregory Hainaut 
---
 src/mesa/main/pipelineobj.c | 25 -
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/src/mesa/main/pipelineobj.c b/src/mesa/main/pipelineobj.c
index 90dff13..99e1491 100644
--- a/src/mesa/main/pipelineobj.c
+++ b/src/mesa/main/pipelineobj.c
@@ -646,7 +646,7 @@ _mesa_GetProgramPipelineiv(GLuint pipeline, GLenum pname, 
GLint *params)
   return;
case GL_VALIDATE_STATUS:
   /* If pipeline is not bound, return initial value 0. */
-  *params = (ctx->_Shader->Name != pipe->Name) ? 0 : pipe->Validated;
+  *params = pipe->Validated;
   return;
case GL_VERTEX_SHADER:
   *params = pipe->CurrentProgram[MESA_SHADER_VERTEX]
@@ -858,6 +858,29 @@ _mesa_validate_program_pipeline(struct gl_context* ctx,
   }
}
 
+   /* Section 11.1.3.11 (Validation) of the OpenGL 4.5 spec says:
+*
+*"An INVALID_OPERATION error is generated by any command that trans-
+*fers vertices to the GL or launches compute work if the current set
+*of active program objects cannot be executed, for reasons including:
+*
+*   ...
+*
+*   - There is no current program object specified by UseProgram,
+* there is a current program pipeline object, and that object is
+* empty (no executable code is installed for any stage).
+*/
+   bool program_empty = true;
+   for (i = 0; i < MESA_SHADER_STAGES; i++) {
+  if (pipe->CurrentProgram[i]) {
+ program_empty = false;
+ break;
+  }
+   }
+   if(program_empty) {
+  goto err;
+   }
+
/* Section 2.11.11 (Shader Execution), subheading "Validation," of the
 * OpenGL 4.1 spec says:
 *
-- 
2.4.3

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[Mesa-dev] [PATCH 2/2] glsl/lower_ubo_reference: split struct copies into element copies

[Iago Toral Quiroga]

Improves register pressure, since otherwise we end up emitting
loads for all the elements in the RHS and them emitting
stores for all elements in the LHS.
---
 src/glsl/lower_ubo_reference.cpp | 56 ++--
 1 file changed, 54 insertions(+), 2 deletions(-)

diff --git a/src/glsl/lower_ubo_reference.cpp b/src/glsl/lower_ubo_reference.cpp
index b82d800..8ec8346 100644
--- a/src/glsl/lower_ubo_reference.cpp
+++ b/src/glsl/lower_ubo_reference.cpp
@@ -155,6 +155,7 @@ public:
   ir_rvalue *offset);
 
bool check_for_buffer_array_copy(ir_assignment *ir);
+   bool check_for_buffer_struct_copy(ir_assignment *ir);
void check_for_ssbo_store(ir_assignment *ir);
void write_to_memory(ir_dereference *deref,
 ir_variable *var,
@@ -1190,12 +1191,60 @@ 
lower_ubo_reference_visitor::check_for_buffer_array_copy(ir_assignment *ir)
return true;
 }
 
+bool
+lower_ubo_reference_visitor::check_for_buffer_struct_copy(ir_assignment *ir)
+{
+   if (!ir || !ir->lhs || !ir->rhs)
+  return false;
+
+   /* LHS and RHS must be records */
+   if (!ir->lhs->type->is_record() || !ir->rhs->type->is_record())
+  return false;
+
+   /* RHS must be a buffer-backed variable. This is what can cause the problem
+* since it would lead to a series of loads that need to live until we
+* see the writes to the LHS.
+*/
+   ir_variable *rhs_var = ir->rhs->variable_referenced();
+   if (!rhs_var || !is_buffer_backed_variable(rhs_var))
+  return false;
+
+   /* Split the struct copy into individual element copies to reduce
+* register pressure
+*/
+   ir_dereference *rhs_deref = ir->rhs->as_dereference();
+   if (!rhs_deref)
+  return false;
+
+   ir_dereference *lhs_deref = ir->lhs->as_dereference();
+   if (!lhs_deref)
+  return false;
+
+   assert(lhs_deref->type->record_compare(rhs_deref->type));
+   mem_ctx = ralloc_parent(shader->ir);
+
+   for (unsigned i = 0; i < lhs_deref->type->length; i++) {
+  const char *field_name = lhs_deref->type->fields.structure[i].name;
+  ir_dereference *lhs_field =
+ new(mem_ctx) ir_dereference_record(lhs_deref->clone(mem_ctx, NULL),
+field_name);
+  ir_dereference *rhs_field =
+ new(mem_ctx) ir_dereference_record(rhs_deref->clone(mem_ctx, NULL),
+field_name);
+  ir->insert_after(assign(lhs_field, rhs_field));
+   }
+
+   ir->remove();
+   progress = true;
+   return true;
+}
+
 ir_visitor_status
 lower_ubo_reference_visitor::visit_enter(ir_assignment *ir)
 {
-   /* Array copies could involve large amounts of load/store
+   /* Array and struct copies could involve large amounts of load/store
 * operations. To improve register pressure we want to special-case
-* these and split array copies into individual element copies.
+* these and split them into individual element copies.
 * This way we avoid emitting all the loads for the RHS first and
 * all the writes for the LHS second and register usage is more
 * efficient.
@@ -1203,6 +1252,9 @@ lower_ubo_reference_visitor::visit_enter(ir_assignment 
*ir)
if (check_for_buffer_array_copy(ir))
   return visit_continue_with_parent;
 
+   if (check_for_buffer_struct_copy(ir))
+  return visit_continue_with_parent;
+
check_ssbo_unsized_array_length_assignment(ir);
check_for_ssbo_store(ir);
return rvalue_visit(ir);
-- 
1.9.1

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[Mesa-dev] [PATCH 1/2] glsl/lower_ubo_reference: split array copies into element copies

[Iago Toral Quiroga]

Improves register pressure, since otherwise we end up emitting
loads for all the elements in the RHS and them emitting
stores for all elements in the LHS.

v2:
  - Mark progress properly. This also fixes some instances where the added
nodes with individual element copies where not being lowered, which is
expected behavior as explained in the documentation for
visit_list_elements.
  - Only need to do this if the RHS is a buffer-backed variable.
  - We can also have arrays inside structs. A later patch will make it so
we also split struct copies and end up with multiple
ir_dereference_record assignments, so make sure that if any of these
is an array copy, we also split it.

Fixes the following piglit tests:
tests/spec/arb_shader_storage_buffer_object/execution/large-field-copy.shader_test
tests/spec/arb_shader_storage_buffer_object/linker/copy-large-array.shader_test
---
 src/glsl/lower_ubo_reference.cpp | 67 
 1 file changed, 67 insertions(+)

diff --git a/src/glsl/lower_ubo_reference.cpp b/src/glsl/lower_ubo_reference.cpp
index b74aa3d..b82d800 100644
--- a/src/glsl/lower_ubo_reference.cpp
+++ b/src/glsl/lower_ubo_reference.cpp
@@ -154,6 +154,7 @@ public:
ir_call *ssbo_load(const struct glsl_type *type,
   ir_rvalue *offset);
 
+   bool check_for_buffer_array_copy(ir_assignment *ir);
void check_for_ssbo_store(ir_assignment *ir);
void write_to_memory(ir_dereference *deref,
 ir_variable *var,
@@ -1132,10 +1133,76 @@ 
lower_ubo_reference_visitor::check_for_ssbo_store(ir_assignment *ir)
progress = true;
 }
 
+static bool
+is_buffer_backed_variable(ir_variable *var)
+{
+   return var->is_in_buffer_block() ||
+  var->data.mode == ir_var_shader_shared;
+}
+
+bool
+lower_ubo_reference_visitor::check_for_buffer_array_copy(ir_assignment *ir)
+{
+   if (!ir || !ir->lhs || !ir->rhs)
+  return false;
+
+   /* LHS and RHS must be arrays
+* FIXME: arrays of arrays?
+*/
+   if (!ir->lhs->type->is_array() || !ir->rhs->type->is_array())
+  return false;
+
+   /* RHS must be a buffer-backed variable. This is what can cause the problem
+* since it would lead to a series of loads that need to live until we
+* see the writes to the LHS.
+*/
+   ir_variable *rhs_var = ir->rhs->variable_referenced();
+   if (!rhs_var || !is_buffer_backed_variable(rhs_var))
+  return false;
+
+   /* Split the array copy into individual element copies to reduce
+* register pressure
+*/
+   ir_dereference *rhs_deref = ir->rhs->as_dereference();
+   if (!rhs_deref)
+  return false;
+
+   ir_dereference *lhs_deref = ir->lhs->as_dereference();
+   if (!lhs_deref)
+  return false;
+
+   assert(lhs_deref->type->length == rhs_deref->type->length);
+   mem_ctx = ralloc_parent(shader->ir);
+
+   for (unsigned i = 0; i < lhs_deref->type->length; i++) {
+  ir_dereference *lhs_i =
+ new(mem_ctx) ir_dereference_array(lhs_deref->clone(mem_ctx, NULL),
+   new(mem_ctx) ir_constant(i));
+
+  ir_dereference *rhs_i =
+ new(mem_ctx) ir_dereference_array(rhs_deref->clone(mem_ctx, NULL),
+   new(mem_ctx) ir_constant(i));
+  ir->insert_after(assign(lhs_i, rhs_i));
+   }
+
+   ir->remove();
+   progress = true;
+   return true;
+}
 
 ir_visitor_status
 lower_ubo_reference_visitor::visit_enter(ir_assignment *ir)
 {
+   /* Array copies could involve large amounts of load/store
+* operations. To improve register pressure we want to special-case
+* these and split array copies into individual element copies.
+* This way we avoid emitting all the loads for the RHS first and
+* all the writes for the LHS second and register usage is more
+* efficient.
+*/
+   if (check_for_buffer_array_copy(ir))
+  return visit_continue_with_parent;
+
check_ssbo_unsized_array_length_assignment(ir);
check_for_ssbo_store(ir);
return rvalue_visit(ir);
-- 
1.9.1

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Re: [Mesa-dev] [PATCH] glsl: split ssbo array copies into element copies

[Iago Toral]

On Fri, 2015-11-20 at 11:09 -0800, Jordan Justen wrote:
> On 2015-11-20 06:48:27, Iago Toral Quiroga wrote:
> > Improves register pressure, since otherwise we end up emitting
> > loads for all the elements in the RHS and them emitting
> > stores for all elements in the LHS.
> > 
> > Fixes the following piglit test:
> > tests/spec/arb_shader_storage_buffer_object/execution/large-field-copy.shader_test
> > ---
> > 
> > Jordan, this fixes the link failure for the the test you provided. Needs 
> > more
> > testing and I have to check if I need to do something for structs that 
> > contain
> > arrays too, etc I'll do that on Monday unless someone else comes with a 
> > better
> > idea to fix this.
> > 
> >  src/glsl/lower_ubo_reference.cpp | 61 
> > 
> >  1 file changed, 61 insertions(+)
> > 
> > diff --git a/src/glsl/lower_ubo_reference.cpp 
> > b/src/glsl/lower_ubo_reference.cpp
> > index b74aa3d..7d48960 100644
> > --- a/src/glsl/lower_ubo_reference.cpp
> > +++ b/src/glsl/lower_ubo_reference.cpp
> > @@ -154,6 +154,7 @@ public:
> > ir_call *ssbo_load(const struct glsl_type *type,
> >ir_rvalue *offset);
> >  
> > +   bool check_for_ssbo_array_copy(ir_assignment *ir);
> > void check_for_ssbo_store(ir_assignment *ir);
> > void write_to_memory(ir_dereference *deref,
> >  ir_variable *var,
> > @@ -1133,9 +1134,69 @@ 
> > lower_ubo_reference_visitor::check_for_ssbo_store(ir_assignment *ir)
> >  }
> >  
> >  
> > +bool
> > +lower_ubo_reference_visitor::check_for_ssbo_array_copy(ir_assignment *ir)
> > +{
> > +   if (!ir || !ir->lhs || !ir->rhs)
> > +  return false;
> > +
> > +   ir_dereference *rhs_deref = ir->rhs->as_dereference();
> > +   if (!rhs_deref)
> > +  return false;
> > +
> > +   ir_dereference *lhs_deref = ir->lhs->as_dereference();
> > +   if (!lhs_deref)
> > +  return false;
> > +
> > +   /* LHS and RHS must be SSBO variables */
> 
> Must they? In fact, the issue that prompted this was a copy from an
> SSBO to a CS shared variable in the ES3.1 CTS. Maybe just the source
> or dest being an SSBO is good enough?

Actually, I think we need to do this when the variable in the RHS is
backed by a buffer (if it is only the lhs, then we are fine because the
thing that creates the problem here is the lifespan of the loads until
we hit the writes), but not just with ssbos, but with any type of
variable that can be lowered to loads, so ubos, ssbos and shared
variables.

> Also, I just re-sent a piglit patch. In this case I just focused on
> testing that the shader linked. I tried the 'array' version with this
> patch, and it hit an assertion in nir_validate.

Yeah, I fixed this locally. This is because I was not reporting progress
properly, so the new nodes with the individual copies were not always
lowered.

> The copy 'struct' version still fails to register allocate.

Yes, I'll fix that too.

> -Jordan
> 
> > +   ir_variable *lhs_var = ir->lhs->variable_referenced();
> > +   if (!lhs_var || !lhs_var->is_in_shader_storage_block())
> > +  return false;
> > +
> > +   ir_variable *rhs_var = ir->rhs->variable_referenced();
> > +   if (!rhs_var || !rhs_var->is_in_shader_storage_block())
> > +  return false;
> > +
> > +   /* LHS and RHS must be variable dereferences.
> > +* FIXME: arrays of arrays?
> > +*/
> > +   if (!ir->lhs->as_dereference_variable() ||
> > +   !ir->rhs->as_dereference_variable())
> > +  return false;
> > +
> > +   /* LHS and RHS must be arrays */
> > +   if (!rhs_var->type->is_array() || !lhs_var->type->is_array())
> > +  return false;
> > +
> > +   assert(lhs_deref->type->length == rhs_deref->type->length);
> > +
> > +   for (unsigned i = 0; i < lhs_deref->type->length; i++) {
> > +  ir_dereference *lhs_i =
> > + new(mem_ctx) ir_dereference_array(lhs_deref->clone(mem_ctx, NULL),
> > +   new(mem_ctx) ir_constant(i));
> > +
> > +  ir_dereference *rhs_i =
> > + new(mem_ctx) ir_dereference_array(rhs_deref->clone(mem_ctx, NULL),
> > +   new(mem_ctx) ir_constant(i));
> > +  ir->insert_after(assign(lhs_i, rhs_i));
> > +   }
> > +
> > +   ir->remove();
> > +   return true;
> > +}
> > +
> >  ir_visitor_status
> >  lower_ubo_reference_visitor::visit_enter(ir_assignment *ir)
> >  {
> > +   /* Array copies could involve large amounts of SSBO load/store
> > +* operations. To improve register pressure we want to special-case
> > +* this and split the array copy into many individual element copies.
> > +* This way we avoid emitting all the loads for the RHS first and
> > +* all the writes for the LHS second.
> > +*/
> > +   if (check_for_ssbo_array_copy(ir))
> > +  return visit_continue_with_parent;
> > +
> > check_ssbo_unsized_array_length_assignment(ir);
> > check_for_ssbo_store(ir);
> > return rvalue_visit(ir);
> > -- 
> > 1.9.1

Re: [Mesa-dev] [PATCH] glsl: implement recent spec update to SSO validation

[Tapani Pälli]

Hi;

On 11/23/2015 02:24 PM, Timothy Arceri wrote:

From: Timothy Arceri 

Enables 200+ dEQP SSO tests to proceed passed validation,
while not regressing ES31-CTS.sepshaderobjs.PipelineApi.

Cc: Tapani Pälli 
Cc: Gregory Hainaut 
---
  src/mesa/main/pipelineobj.c | 25 -
  1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/src/mesa/main/pipelineobj.c b/src/mesa/main/pipelineobj.c
index 90dff13..99e1491 100644
--- a/src/mesa/main/pipelineobj.c
+++ b/src/mesa/main/pipelineobj.c
@@ -646,7 +646,7 @@ _mesa_GetProgramPipelineiv(GLuint pipeline, GLenum pname, 
GLint *params)
return;
 case GL_VALIDATE_STATUS:
/* If pipeline is not bound, return initial value 0. */
-  *params = (ctx->_Shader->Name != pipe->Name) ? 0 : pipe->Validated;
+  *params = pipe->Validated;


I agree with the added check below but I feel worried with this change 
as the test is testing explicitly if pipeline was bound before the call, 
here it just happens to be empty as well.


I guess my main worry is that we don't seem to be implementing following:

"If pipeline is a name that has been generated (without subsequent 
deletion) by GenProgramPipelines, but refers to a program pipeline 
object that has not been previously bound, the GL first creates a new 
state vector in the same manner as when BindProgramPipeline creates a 
new program pipeline object."


So we don't realy create 'new state vector' for a new program pipeline 
object but try to return same values as one would have?




return;
 case GL_VERTEX_SHADER:
*params = pipe->CurrentProgram[MESA_SHADER_VERTEX]
@@ -858,6 +858,29 @@ _mesa_validate_program_pipeline(struct gl_context* ctx,
}
 }

+   /* Section 11.1.3.11 (Validation) of the OpenGL 4.5 spec says:
+*
+*"An INVALID_OPERATION error is generated by any command that trans-
+*fers vertices to the GL or launches compute work if the current set
+*of active program objects cannot be executed, for reasons including:
+*
+*   ...
+*
+*   - There is no current program object specified by UseProgram,
+* there is a current program pipeline object, and that object is
+* empty (no executable code is installed for any stage).
+*/
+   bool program_empty = true;
+   for (i = 0; i < MESA_SHADER_STAGES; i++) {
+  if (pipe->CurrentProgram[i]) {
+ program_empty = false;
+ break;
+  }
+   }
+   if(program_empty) {
+  goto err;
+   }
+
 /* Section 2.11.11 (Shader Execution), subheading "Validation," of the
  * OpenGL 4.1 spec says:
  *



// Tapani
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Re: [Mesa-dev] [PATCH 1/7] glsl: move and reused code to find first and last shaders

[Juha-Pekka Heikkila]

Reviewed-by: Juha-Pekka Heikkila 

On 21.11.2015 10:02, Timothy Arceri wrote:

From: Timothy Arceri 

---
  src/glsl/linker.cpp | 30 --
  1 file changed, 12 insertions(+), 18 deletions(-)

diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index 331d9a2..eac2536 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -4139,11 +4139,18 @@ link_shaders(struct gl_context *ctx, struct 
gl_shader_program *prog)
 if (!prog->LinkStatus)
goto done;

-   unsigned prev;
+   unsigned first, last, prev;

-   for (prev = 0; prev <= MESA_SHADER_FRAGMENT; prev++) {
-  if (prog->_LinkedShaders[prev] != NULL)
- break;
+   first = MESA_SHADER_STAGES;
+   last = 0;
+
+   /* Determine first and last stage. */
+   for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
+  if (!prog->_LinkedShaders[i])
+ continue;
+  if (first == MESA_SHADER_STAGES)
+ first = i;
+  last = i;
 }

 check_explicit_uniform_locations(ctx, prog);
@@ -4157,6 +4164,7 @@ link_shaders(struct gl_context *ctx, struct 
gl_shader_program *prog)
 /* Validate the inputs of each stage with the output of the preceding
  * stage.
  */
+   prev = first;
 for (unsigned i = prev + 1; i <= MESA_SHADER_FRAGMENT; i++) {
if (prog->_LinkedShaders[i] == NULL)
   continue;
@@ -4260,20 +4268,6 @@ link_shaders(struct gl_context *ctx, struct 
gl_shader_program *prog)
goto done;
 }

-   unsigned first, last;
-
-   first = MESA_SHADER_STAGES;
-   last = 0;
-
-   /* Determine first and last stage. */
-   for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
-  if (!prog->_LinkedShaders[i])
- continue;
-  if (first == MESA_SHADER_STAGES)
- first = i;
-  last = i;
-   }
-
 if (num_tfeedback_decls != 0) {
/* From GL_EXT_transform_feedback:
 *   A program will fail to link if:



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Re: [Mesa-dev] [Mesa-stable] [PATCH] configure.ac: use pkg-config for libelf

[Emil Velikov]

On 23 November 2015 at 03:24, Jonathan Gray  wrote:
> Use PKG_CHECK_MODULES to get the flags to link libelf.
>
> Signed-off-by: Jonathan Gray 
> Cc: "11.0 11.1" 
> ---
>  configure.ac   | 4 +---
>  src/gallium/drivers/radeon/Makefile.am | 2 +-
>  src/gallium/targets/opencl/Makefile.am | 2 +-
>  3 files changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/configure.ac b/configure.ac
> index 72a2ec1..afee3ed 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -1712,7 +1712,7 @@ AC_ARG_WITH([clang-libdir],
> [CLANG_LIBDIR=''])
>
>  PKG_CHECK_EXISTS([libclc], [have_libclc=yes], [have_libclc=no])
> -AC_CHECK_LIB([elf], [elf_memory], [have_libelf=yes;ELF_LIB=-lelf])
> +PKG_CHECK_MODULES([LIBELF], [libelf], [have_libelf=yes], [have_libelf=no])
>
There are (at least) two providers/projects for libelf one of which
iirc does not provide a .pc file. We might need to keep the check_lib
as a fall back. Don't know which one is required/compatible with
radeon and opencl.

Tom, Marek any ideas ?

Thanks
Emil
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Re: [Mesa-dev] [PATCH 2/7] glsl: only call dead code pass when new inputs/outputs demoted

[Juha-Pekka Heikkila]

Reviewed-by: Juha-Pekka Heikkila 

On 21.11.2015 10:02, Timothy Arceri wrote:

From: Timothy Arceri 

This will help avoid eliminating inputs/outputs needed by SSOs.

Cc: Gregory Hainaut 
---
  src/glsl/linker.cpp | 24 ++--
  1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index eac2536..5ff433c 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -4327,13 +4327,14 @@ link_shaders(struct gl_context *ctx, struct 
gl_shader_program *prog)
do_dead_builtin_varyings(ctx, sh, NULL,
 num_tfeedback_decls, tfeedback_decls);

-  if (!prog->SeparateShader)
+  if (!prog->SeparateShader) {
   demote_shader_inputs_and_outputs(sh, ir_var_shader_out);
-
-  /* Eliminate code that is now dead due to unused outputs being demoted.
-   */
-  while (do_dead_code(sh->ir, false))
- ;
+ /* Eliminate code that is now dead due to unused outputs being
+  * demoted.
+  */
+ while (do_dead_code(sh->ir, false))
+;
+  }
 }
 else if (first == MESA_SHADER_FRAGMENT) {
/* If the program only contains a fragment shader...
@@ -4350,11 +4351,14 @@ link_shaders(struct gl_context *ctx, struct 
gl_shader_program *prog)
 0 /* num_tfeedback_decls */,
 NULL /* tfeedback_decls */))
  goto done;
-  } else
+  } else {
   demote_shader_inputs_and_outputs(sh, ir_var_shader_in);
-
-  while (do_dead_code(sh->ir, false))
- ;
+ /* Eliminate code that is now dead due to unused inputs being
+  * demoted.
+  */
+ while (do_dead_code(sh->ir, false))
+;
+  }
 }

 next = last;



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Re: [Mesa-dev] [PATCH] glsl: implement recent spec update to SSO validation

[Gregory Hainaut]

It is a different issue and it seems I already did it (or someone else
patched it).

You can see those lines in the code.
   /* Object is created by any Pipeline call but glGenProgramPipelines,
* glIsProgramPipeline and GetProgramPipelineInfoLog
*/
   pipe->EverBound = GL_TRUE;

The trick is that object is created by GenProgramPipelines (unlike the
spec said). Only a flag is updated to mark the object as created. And
normally validated must be 0 after the init (rzalloc?).





On 11/23/15, Tapani Pälli  wrote:
> Hi;
>
> On 11/23/2015 02:24 PM, Timothy Arceri wrote:
>> From: Timothy Arceri 
>>
>> Enables 200+ dEQP SSO tests to proceed passed validation,
>> while not regressing ES31-CTS.sepshaderobjs.PipelineApi.
>>
>> Cc: Tapani Pälli 
>> Cc: Gregory Hainaut 
>> ---
>>   src/mesa/main/pipelineobj.c | 25 -
>>   1 file changed, 24 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/mesa/main/pipelineobj.c b/src/mesa/main/pipelineobj.c
>> index 90dff13..99e1491 100644
>> --- a/src/mesa/main/pipelineobj.c
>> +++ b/src/mesa/main/pipelineobj.c
>> @@ -646,7 +646,7 @@ _mesa_GetProgramPipelineiv(GLuint pipeline, GLenum
>> pname, GLint *params)
>> return;
>>  case GL_VALIDATE_STATUS:
>> /* If pipeline is not bound, return initial value 0. */
>> -  *params = (ctx->_Shader->Name != pipe->Name) ? 0 :
>> pipe->Validated;
>> +  *params = pipe->Validated;
>
> I agree with the added check below but I feel worried with this change
> as the test is testing explicitly if pipeline was bound before the call,
> here it just happens to be empty as well.
>
> I guess my main worry is that we don't seem to be implementing following:
>
> "If pipeline is a name that has been generated (without subsequent
> deletion) by GenProgramPipelines, but refers to a program pipeline
> object that has not been previously bound, the GL first creates a new
> state vector in the same manner as when BindProgramPipeline creates a
> new program pipeline object."
>
> So we don't realy create 'new state vector' for a new program pipeline
> object but try to return same values as one would have?
>
>
>> return;
>>  case GL_VERTEX_SHADER:
>> *params = pipe->CurrentProgram[MESA_SHADER_VERTEX]
>> @@ -858,6 +858,29 @@ _mesa_validate_program_pipeline(struct gl_context*
>> ctx,
>> }
>>  }
>>
>> +   /* Section 11.1.3.11 (Validation) of the OpenGL 4.5 spec says:
>> +*
>> +*"An INVALID_OPERATION error is generated by any command that
>> trans-
>> +*fers vertices to the GL or launches compute work if the current
>> set
>> +*of active program objects cannot be executed, for reasons
>> including:
>> +*
>> +*   ...
>> +*
>> +*   - There is no current program object specified by
>> UseProgram,
>> +* there is a current program pipeline object, and that object
>> is
>> +* empty (no executable code is installed for any stage).
>> +*/
>> +   bool program_empty = true;
>> +   for (i = 0; i < MESA_SHADER_STAGES; i++) {
>> +  if (pipe->CurrentProgram[i]) {
>> + program_empty = false;
>> + break;
>> +  }
>> +   }
>> +   if(program_empty) {
>> +  goto err;
>> +   }
>> +
>>  /* Section 2.11.11 (Shader Execution), subheading "Validation," of
>> the
>>   * OpenGL 4.1 spec says:
>>   *
>>
>
> // Tapani
>
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Re: [Mesa-dev] [PATCH] configure.ac: use pkg-config for libelf

[Jan Vesely]

On Mon, 2015-11-23 at 14:24 +1100, Jonathan Gray wrote:
> Use PKG_CHECK_MODULES to get the flags to link libelf.

This has been discussed before, and it does not work with elfutils:
http://lists.freedesktop.org/archives/mesa-dev/2014-October/069748.html

Jan

> 
> Signed-off-by: Jonathan Gray 
> Cc: "11.0 11.1" 
> ---
>  configure.ac   | 4 +---
>  src/gallium/drivers/radeon/Makefile.am | 2 +-
>  src/gallium/targets/opencl/Makefile.am | 2 +-
>  3 files changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/configure.ac b/configure.ac
> index 72a2ec1..afee3ed 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -1712,7 +1712,7 @@ AC_ARG_WITH([clang-libdir],
> [CLANG_LIBDIR=''])
>  
>  PKG_CHECK_EXISTS([libclc], [have_libclc=yes], [have_libclc=no])
> -AC_CHECK_LIB([elf], [elf_memory], [have_libelf=yes;ELF_LIB=-lelf])
> +PKG_CHECK_MODULES([LIBELF], [libelf], [have_libelf=yes],
> [have_libelf=no])
>  
>  if test "x$enable_opencl" = xyes; then
>  if test -z "$with_gallium_drivers"; then
> @@ -2293,8 +2293,6 @@ if test "x$USE_VC4_SIMULATOR" = xyes -a
> "x$HAVE_GALLIUM_ILO" = xyes; then
>  AC_MSG_ERROR([VC4 simulator on x86 replaces i965 driver build,
> so ilo must be disabled.])
>  fi
>  
> -AC_SUBST([ELF_LIB])
> -
>  AM_CONDITIONAL(HAVE_LIBDRM, test "x$have_libdrm" = xyes)
>  AM_CONDITIONAL(HAVE_X11_DRIVER, test "x$enable_xlib_glx" = xyes)
>  AM_CONDITIONAL(HAVE_OSMESA, test "x$enable_osmesa" = xyes)
> diff --git a/src/gallium/drivers/radeon/Makefile.am
> b/src/gallium/drivers/radeon/Makefile.am
> index 13d8976..fa2b5a6 100644
> --- a/src/gallium/drivers/radeon/Makefile.am
> +++ b/src/gallium/drivers/radeon/Makefile.am
> @@ -24,7 +24,7 @@ libradeon_la_SOURCES += \
>  libradeon_la_LIBADD = \
>   $(CLOCK_LIB) \
>   $(LLVM_LIBS) \
> - $(ELF_LIB)
> + $(LIBELF_LIBS)
>  
>  libradeon_la_LDFLAGS = \
>   $(LLVM_LDFLAGS)
> diff --git a/src/gallium/targets/opencl/Makefile.am
> b/src/gallium/targets/opencl/Makefile.am
> index 08f95e8..99532f0 100644
> --- a/src/gallium/targets/opencl/Makefile.am
> +++ b/src/gallium/targets/opencl/Makefile.am
> @@ -19,7 +19,7 @@ lib@OPENCL_LIBNAME@_la_LIBADD = \
>   $(top_builddir)/src/gallium/state_trackers/clover/libclover.
> la \
>   $(top_builddir)/src/gallium/auxiliary/libgallium.la \
>   $(top_builddir)/src/util/libmesautil.la \
> - $(ELF_LIB) \
> + $(LIBELF_LIBS) \
>   $(DLOPEN_LIBS) \
>   -lclangCodeGen \
>   -lclangFrontendTool \


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Re: [Mesa-dev] [PATCH] configure.ac: use pkg-config for libelf

[Jonathan Gray]

On Mon, Nov 23, 2015 at 07:52:44AM -0600, Jan Vesely wrote:
> On Mon, 2015-11-23 at 14:24 +1100, Jonathan Gray wrote:
> > Use PKG_CHECK_MODULES to get the flags to link libelf.
> 
> This has been discussed before, and it does not work with elfutils:
> http://lists.freedesktop.org/archives/mesa-dev/2014-October/069748.html
> 
> Jan

Back to
export LDFLAGS=-L/usr/local/lib
export CPPFLAGS="-I/usr/local/include -I/usr/local/include/libelf"

to make mesa build when linking libelf here on OpenBSD then...

$ pkg-config --cflags libelf
  
-I/usr/local/include/libelf -I/usr/local/include

$ pkg-config --libs libelf   
-L/usr/local/lib -lelf
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Re: [Mesa-dev] [PATCH 1/7] i965/fs_surface_builder: Explicitly handle FORMAT_NONE in num_image_coordinates

[Francisco Jerez]

Jason Ekstrand  writes:

> On Fri, Nov 20, 2015 at 5:49 AM, Francisco Jerez  
> wrote:
>> Chad Versace  writes:
>>
>>> On Wed 04 Nov 2015, Jason Ekstrand wrote:
 Previously, we were relying on has_matching_typed_format returning true for
 MESA_FORMAT_NONE which, in turn, relied on _mesa_get_format_bytes returning
 1 for MESA_FORMAT_NONE.  All of this is extremely non-obvious.  Instead,
 this commit makes us handle it explicitly.
 ---
  src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp | 1 +
  1 file changed, 1 insertion(+)

 diff --git a/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp 
 b/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp
 index 534d849..31ecb5b 100644
 --- a/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp
 +++ b/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp
 @@ -409,6 +409,7 @@ namespace {
* reads want the array index to be at the Z component.
*/
   const bool array_index_at_z =
 +format != MESA_FORMAT_NONE &&
  !image_format_info::has_matching_typed_format(
 bld.shader->devinfo, format);
   const unsigned zero_dims =
>>>
>>>
>>> Knowing nothing about the implicit assumptions you discovered that
>>> relied on _mesa_get_format_bytes(MESA_FORMAT_NONE) => 1, the patch is
>>> still looks like an improvement to me.
>>>
>> It didn't.  It relied on _mesa_get_format_bytes(MESA_FORMAT_NONE) not
>> being greater than 4, which seems sensible anyway.
>
> I can change the commit message to say
>
> Previously, we were relying on has_matching_typed_format returning true for
> MESA_FORMAT_NONE which, in turn, relied on _mesa_get_format_bytes returning
> a value <= 4 for MESA_FORMAT_NONE.  While reliable, this is extremely
> non-obvious.  Instead,
> this commit makes us handle it explicitly.

has_matching_typed_format(MESA_FORMAT_NONE) returned true by design,
GL_NONE/MESA_FORMAT_NONE represents a shader-unspecified format
throughout the image load/store code, and in Gen hardware that
necessarily implies typed (since otherwise we would need to know the
format for the compiler to be able to generate appropriate format
conversion code, but we don't).  Its semantics are blurred quite a bit
in this series though: All instances of MESA_FORMAT_NONE are replaced
with BRW_SURFACEFORMAT_RAW, which is already used in the image surface
state setup code to represent an *untyped* format (that's what a RAW
surface format means on Gen hardware), i.e. a set of formats fully
disjoint from what MESA_FORMAT_NONE used to represent.

For that reason 'has_matching_typed_format(MESA_FORMAT_NONE) = true'
makes sense to me, but 'has_matching_typed_format(BRW_SURFACEFORMAT_RAW)
= true' and the identification of MESA_FORMAT_NONE with
BRW_SURFACEFORMAT_RAW does not.

I believe this confusion may not have led to any actual bugs though,
because BRW_SURFACEFORMAT_RAW was only used in the state upload code and
was never actually visible to the compiler.  Likewise MESA_FORMAT_NONE
was never visible to the state upload code because an image unit with
invalid format would have been caught by the _mesa_is_image_unit_valid()
check before the translation to native formats.  Seems rather
disquieting still...

>
>>> Acked-by: Chad Versace 
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[Mesa-dev] [PATCH 3/8] st/va: move MPEG12 functions into separate file

[Christian König]

From: Christian König 

Signed-off-by: Christian König 
---
 src/gallium/state_trackers/va/Makefile.sources |  1 +
 src/gallium/state_trackers/va/picture.c| 57 +++---
 src/gallium/state_trackers/va/picture_mpeg12.c | 80 ++
 src/gallium/state_trackers/va/va_private.h |  3 +
 4 files changed, 92 insertions(+), 49 deletions(-)
 create mode 100644 src/gallium/state_trackers/va/picture_mpeg12.c

diff --git a/src/gallium/state_trackers/va/Makefile.sources 
b/src/gallium/state_trackers/va/Makefile.sources
index dd0cef5..e0ab43f 100644
--- a/src/gallium/state_trackers/va/Makefile.sources
+++ b/src/gallium/state_trackers/va/Makefile.sources
@@ -5,6 +5,7 @@ C_SOURCES := \
display.c \
image.c \
picture.c \
+   picture_mpeg12.c \
postproc.c \
subpicture.c \
surface.c \
diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index 23a1ffa..67b7acb 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -75,9 +75,9 @@ vlVaBeginPicture(VADriverContextP ctx, VAContextID 
context_id, VASurfaceID rende
return VA_STATUS_SUCCESS;
 }
 
-static void
-getReferenceFrame(vlVaDriver *drv, VASurfaceID surface_id,
-  struct pipe_video_buffer **ref_frame)
+void
+vlVaGetReferenceFrame(vlVaDriver *drv, VASurfaceID surface_id,
+  struct pipe_video_buffer **ref_frame)
 {
vlVaSurface *surf = handle_table_get(drv->htab, surface_id);
if (surf)
@@ -89,7 +89,6 @@ getReferenceFrame(vlVaDriver *drv, VASurfaceID surface_id,
 static void
 handlePictureParameterBuffer(vlVaDriver *drv, vlVaContext *context, vlVaBuffer 
*buf)
 {
-   VAPictureParameterBufferMPEG2 *mpeg2;
VAPictureParameterBufferH264 *h264;
VAPictureParameterBufferVC1 * vc1;
VAPictureParameterBufferMPEG4 *mpeg4;
@@ -102,36 +101,7 @@ handlePictureParameterBuffer(vlVaDriver *drv, vlVaContext 
*context, vlVaBuffer *
 
switch (u_reduce_video_profile(context->decoder->profile)) {
case PIPE_VIDEO_FORMAT_MPEG12:
-  assert(buf->size >= sizeof(VAPictureParameterBufferMPEG2) && 
buf->num_elements == 1);
-  mpeg2 = buf->data;
-  /*horizontal_size;*/
-  /*vertical_size;*/
-  getReferenceFrame(drv, mpeg2->forward_reference_picture, 
>desc.mpeg12.ref[0]);
-  getReferenceFrame(drv, mpeg2->backward_reference_picture, 
>desc.mpeg12.ref[1]);
-  context->desc.mpeg12.picture_coding_type = mpeg2->picture_coding_type;
-  context->desc.mpeg12.f_code[0][0] = ((mpeg2->f_code >> 12) & 0xf) - 1;
-  context->desc.mpeg12.f_code[0][1] = ((mpeg2->f_code >> 8) & 0xf) - 1;
-  context->desc.mpeg12.f_code[1][0] = ((mpeg2->f_code >> 4) & 0xf) - 1;
-  context->desc.mpeg12.f_code[1][1] = (mpeg2->f_code & 0xf) - 1;
-  context->desc.mpeg12.intra_dc_precision =
- mpeg2->picture_coding_extension.bits.intra_dc_precision;
-  context->desc.mpeg12.picture_structure =
- mpeg2->picture_coding_extension.bits.picture_structure;
-  context->desc.mpeg12.top_field_first =
- mpeg2->picture_coding_extension.bits.top_field_first;
-  context->desc.mpeg12.frame_pred_frame_dct =
- mpeg2->picture_coding_extension.bits.frame_pred_frame_dct;
-  context->desc.mpeg12.concealment_motion_vectors =
- mpeg2->picture_coding_extension.bits.concealment_motion_vectors;
-  context->desc.mpeg12.q_scale_type =
- mpeg2->picture_coding_extension.bits.q_scale_type;
-  context->desc.mpeg12.intra_vlc_format =
- mpeg2->picture_coding_extension.bits.intra_vlc_format;
-  context->desc.mpeg12.alternate_scan =
- mpeg2->picture_coding_extension.bits.alternate_scan;
-  /*repeat_first_field*/
-  /*progressive_frame*/
-  /*is_first_field*/
+  vlVaHandlePictureParameterBufferMPEG12(drv, context, buf);
   break;
 
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
@@ -199,8 +169,8 @@ handlePictureParameterBuffer(vlVaDriver *drv, vlVaContext 
*context, vlVaBuffer *
case PIPE_VIDEO_FORMAT_VC1:
   assert(buf->size >= sizeof(VAPictureParameterBufferVC1) && 
buf->num_elements == 1);
   vc1 = buf->data;
-  getReferenceFrame(drv, vc1->forward_reference_picture, 
>desc.vc1.ref[0]);
-  getReferenceFrame(drv, vc1->backward_reference_picture, 
>desc.vc1.ref[1]);
+  vlVaGetReferenceFrame(drv, vc1->forward_reference_picture, 
>desc.vc1.ref[0]);
+  vlVaGetReferenceFrame(drv, vc1->backward_reference_picture, 
>desc.vc1.ref[1]);
   context->desc.vc1.picture_type = vc1->picture_fields.bits.picture_type;
   context->desc.vc1.frame_coding_mode = 
vc1->picture_fields.bits.frame_coding_mode;
   context->desc.vc1.postprocflag = vc1->post_processing != 0;
@@ -433,7 +403,7 @@ handlePictureParameterBuffer(vlVaDriver *drv, vlVaContext 
*context, vlVaBuffer *
  if (index == 0x7F)
 continue;
 
-

[Mesa-dev] [PATCH 5/8] st/va: move VC-1 functions into separate file

[Christian König]

From: Christian König 

Signed-off-by: Christian König 
---
 src/gallium/state_trackers/va/Makefile.sources |  1 +
 src/gallium/state_trackers/va/picture.c| 36 +-
 src/gallium/state_trackers/va/picture_vc1.c| 67 ++
 src/gallium/state_trackers/va/va_private.h |  1 +
 4 files changed, 70 insertions(+), 35 deletions(-)
 create mode 100644 src/gallium/state_trackers/va/picture_vc1.c

diff --git a/src/gallium/state_trackers/va/Makefile.sources 
b/src/gallium/state_trackers/va/Makefile.sources
index 77663a1..4e42d5a 100644
--- a/src/gallium/state_trackers/va/Makefile.sources
+++ b/src/gallium/state_trackers/va/Makefile.sources
@@ -7,6 +7,7 @@ C_SOURCES := \
picture.c \
picture_mpeg12.c \
picture_h264.c \
+   picture_vc1.c \
postproc.c \
subpicture.c \
surface.c \
diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index 46ca5e8..24f26ed 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -89,7 +89,6 @@ vlVaGetReferenceFrame(vlVaDriver *drv, VASurfaceID surface_id,
 static void
 handlePictureParameterBuffer(vlVaDriver *drv, vlVaContext *context, vlVaBuffer 
*buf)
 {
-   VAPictureParameterBufferVC1 * vc1;
VAPictureParameterBufferMPEG4 *mpeg4;
VAPictureParameterBufferHEVC *hevc;
vlVaSurface *surf_forward;
@@ -108,40 +107,7 @@ handlePictureParameterBuffer(vlVaDriver *drv, vlVaContext 
*context, vlVaBuffer *
   break;
 
case PIPE_VIDEO_FORMAT_VC1:
-  assert(buf->size >= sizeof(VAPictureParameterBufferVC1) && 
buf->num_elements == 1);
-  vc1 = buf->data;
-  vlVaGetReferenceFrame(drv, vc1->forward_reference_picture, 
>desc.vc1.ref[0]);
-  vlVaGetReferenceFrame(drv, vc1->backward_reference_picture, 
>desc.vc1.ref[1]);
-  context->desc.vc1.picture_type = vc1->picture_fields.bits.picture_type;
-  context->desc.vc1.frame_coding_mode = 
vc1->picture_fields.bits.frame_coding_mode;
-  context->desc.vc1.postprocflag = vc1->post_processing != 0;
-  context->desc.vc1.pulldown = vc1->sequence_fields.bits.pulldown;
-  context->desc.vc1.interlace = vc1->sequence_fields.bits.interlace;
-  context->desc.vc1.tfcntrflag = vc1->sequence_fields.bits.tfcntrflag;
-  context->desc.vc1.finterpflag = vc1->sequence_fields.bits.finterpflag;
-  context->desc.vc1.psf = vc1->sequence_fields.bits.psf;
-  context->desc.vc1.dquant = vc1->pic_quantizer_fields.bits.dquant;
-  context->desc.vc1.panscan_flag = 
vc1->entrypoint_fields.bits.panscan_flag;
-  context->desc.vc1.refdist_flag =
- vc1->reference_fields.bits.reference_distance_flag;
-  context->desc.vc1.quantizer = vc1->pic_quantizer_fields.bits.quantizer;
-  context->desc.vc1.extended_mv = vc1->mv_fields.bits.extended_mv_flag;
-  context->desc.vc1.extended_dmv = vc1->mv_fields.bits.extended_dmv_flag;
-  context->desc.vc1.overlap = vc1->sequence_fields.bits.overlap;
-  context->desc.vc1.vstransform =
- vc1->transform_fields.bits.variable_sized_transform_flag;
-  context->desc.vc1.loopfilter = vc1->entrypoint_fields.bits.loopfilter;
-  context->desc.vc1.fastuvmc = vc1->fast_uvmc_flag;
-  context->desc.vc1.range_mapy_flag = 
vc1->range_mapping_fields.bits.luma_flag;
-  context->desc.vc1.range_mapy = vc1->range_mapping_fields.bits.luma;
-  context->desc.vc1.range_mapuv_flag = 
vc1->range_mapping_fields.bits.chroma_flag;
-  context->desc.vc1.range_mapuv = vc1->range_mapping_fields.bits.chroma;
-  context->desc.vc1.multires = vc1->sequence_fields.bits.multires;
-  context->desc.vc1.syncmarker = vc1->sequence_fields.bits.syncmarker;
-  context->desc.vc1.rangered = vc1->sequence_fields.bits.rangered;
-  context->desc.vc1.maxbframes = vc1->sequence_fields.bits.max_b_frames;
-  context->desc.vc1.deblockEnable = vc1->post_processing != 0;
-  context->desc.vc1.pquant = 
vc1->pic_quantizer_fields.bits.pic_quantizer_scale;
+  vlVaHandlePictureParameterBufferVC1(drv, context, buf);
   break;
 
case PIPE_VIDEO_FORMAT_MPEG4:
diff --git a/src/gallium/state_trackers/va/picture_vc1.c 
b/src/gallium/state_trackers/va/picture_vc1.c
new file mode 100644
index 000..f95fd83
--- /dev/null
+++ b/src/gallium/state_trackers/va/picture_vc1.c
@@ -0,0 +1,67 @@
+/**
+ *
+ * Copyright 2014 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the 

[Mesa-dev] [PATCH 4/8] st/va: move H264 functions into separate file

[Christian König]

From: Christian König 

Signed-off-by: Christian König 
---
 src/gallium/state_trackers/va/Makefile.sources |   1 +
 src/gallium/state_trackers/va/picture.c|  76 +
 src/gallium/state_trackers/va/picture_h264.c   | 113 +
 src/gallium/state_trackers/va/va_private.h |   3 +
 4 files changed, 121 insertions(+), 72 deletions(-)
 create mode 100644 src/gallium/state_trackers/va/picture_h264.c

diff --git a/src/gallium/state_trackers/va/Makefile.sources 
b/src/gallium/state_trackers/va/Makefile.sources
index e0ab43f..77663a1 100644
--- a/src/gallium/state_trackers/va/Makefile.sources
+++ b/src/gallium/state_trackers/va/Makefile.sources
@@ -6,6 +6,7 @@ C_SOURCES := \
image.c \
picture.c \
picture_mpeg12.c \
+   picture_h264.c \
postproc.c \
subpicture.c \
surface.c \
diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index 67b7acb..46ca5e8 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -89,7 +89,6 @@ vlVaGetReferenceFrame(vlVaDriver *drv, VASurfaceID surface_id,
 static void
 handlePictureParameterBuffer(vlVaDriver *drv, vlVaContext *context, vlVaBuffer 
*buf)
 {
-   VAPictureParameterBufferH264 *h264;
VAPictureParameterBufferVC1 * vc1;
VAPictureParameterBufferMPEG4 *mpeg4;
VAPictureParameterBufferHEVC *hevc;
@@ -105,65 +104,7 @@ handlePictureParameterBuffer(vlVaDriver *drv, vlVaContext 
*context, vlVaBuffer *
   break;
 
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
-  assert(buf->size >= sizeof(VAPictureParameterBufferH264) && 
buf->num_elements == 1);
-  h264 = buf->data;
-  /*CurrPic*/
-  context->desc.h264.field_order_cnt[0] = h264->CurrPic.TopFieldOrderCnt;
-  context->desc.h264.field_order_cnt[1] = 
h264->CurrPic.BottomFieldOrderCnt;
-  /*ReferenceFrames[16]*/
-  /*picture_width_in_mbs_minus1*/
-  /*picture_height_in_mbs_minus1*/
-  /*bit_depth_luma_minus8*/
-  /*bit_depth_chroma_minus8*/
-  context->desc.h264.num_ref_frames = h264->num_ref_frames;
-  /*chroma_format_idc*/
-  /*residual_colour_transform_flag*/
-  /*gaps_in_frame_num_value_allowed_flag*/
-  context->desc.h264.pps->sps->frame_mbs_only_flag =
- h264->seq_fields.bits.frame_mbs_only_flag;
-  context->desc.h264.pps->sps->mb_adaptive_frame_field_flag =
- h264->seq_fields.bits.mb_adaptive_frame_field_flag;
-  context->desc.h264.pps->sps->direct_8x8_inference_flag =
- h264->seq_fields.bits.direct_8x8_inference_flag;
-  /*MinLumaBiPredSize8x8*/
-  context->desc.h264.pps->sps->log2_max_frame_num_minus4 =
- h264->seq_fields.bits.log2_max_frame_num_minus4;
-  context->desc.h264.pps->sps->pic_order_cnt_type =
- h264->seq_fields.bits.pic_order_cnt_type;
-  context->desc.h264.pps->sps->log2_max_pic_order_cnt_lsb_minus4 =
- h264->seq_fields.bits.log2_max_pic_order_cnt_lsb_minus4;
-  context->desc.h264.pps->sps->delta_pic_order_always_zero_flag =
- h264->seq_fields.bits.delta_pic_order_always_zero_flag;
-  /*num_slice_groups_minus1*/
-  /*slice_group_map_type*/
-  /*slice_group_change_rate_minus1*/
-  context->desc.h264.pps->pic_init_qp_minus26 =
- h264->pic_init_qp_minus26;
-  /*pic_init_qs_minus26*/
-  context->desc.h264.pps->chroma_qp_index_offset =
- h264->chroma_qp_index_offset;
-  context->desc.h264.pps->second_chroma_qp_index_offset =
- h264->second_chroma_qp_index_offset;
-  context->desc.h264.pps->entropy_coding_mode_flag =
- h264->pic_fields.bits.entropy_coding_mode_flag;
-  context->desc.h264.pps->weighted_pred_flag =
- h264->pic_fields.bits.weighted_pred_flag;
-  context->desc.h264.pps->weighted_bipred_idc =
- h264->pic_fields.bits.weighted_bipred_idc;
-  context->desc.h264.pps->transform_8x8_mode_flag =
- h264->pic_fields.bits.transform_8x8_mode_flag;
-  context->desc.h264.field_pic_flag =
- h264->pic_fields.bits.field_pic_flag;
-  context->desc.h264.pps->constrained_intra_pred_flag =
- h264->pic_fields.bits.constrained_intra_pred_flag;
-  context->desc.h264.pps->bottom_field_pic_order_in_frame_present_flag =
- h264->pic_fields.bits.pic_order_present_flag;
-  context->desc.h264.pps->deblocking_filter_control_present_flag =
- h264->pic_fields.bits.deblocking_filter_control_present_flag;
-  context->desc.h264.pps->redundant_pic_cnt_present_flag =
- h264->pic_fields.bits.redundant_pic_cnt_present_flag;
-  /*reference_pic_flag*/
-  context->desc.h264.frame_num = h264->frame_num;
+  vlVaHandlePictureParameterBufferH264(drv, context, buf);
   break;
 
case PIPE_VIDEO_FORMAT_VC1:
@@ -428,7 +369,6 @@ handlePictureParameterBuffer(vlVaDriver *drv, vlVaContext 
*context, 

[Mesa-dev] [PATCH] st/va: disable MPEG4 by default

[Christian König]

From: Christian König 

The workarounds are to hacky to enable them by default
and otherwise MPEG4 doesn't work reliable.

Signed-off-by: Christian König 
---
 src/gallium/state_trackers/va/config.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/gallium/state_trackers/va/config.c 
b/src/gallium/state_trackers/va/config.c
index a545a18..9ca0aa8 100644
--- a/src/gallium/state_trackers/va/config.c
+++ b/src/gallium/state_trackers/va/config.c
@@ -28,10 +28,14 @@
 
 #include "pipe/p_screen.h"
 
+#include "util/u_video.h"
+
 #include "vl/vl_winsys.h"
 
 #include "va_private.h"
 
+DEBUG_GET_ONCE_BOOL_OPTION(mpeg4, "VAAPI_MPEG4_ENABLED", false)
+
 VAStatus
 vlVaQueryConfigProfiles(VADriverContextP ctx, VAProfile *profile_list, int 
*num_profiles)
 {
@@ -45,12 +49,16 @@ vlVaQueryConfigProfiles(VADriverContextP ctx, VAProfile 
*profile_list, int *num_
*num_profiles = 0;
 
pscreen = VL_VA_PSCREEN(ctx);
-   for (p = PIPE_VIDEO_PROFILE_MPEG2_SIMPLE; p <= 
PIPE_VIDEO_PROFILE_HEVC_MAIN_444; ++p)
+   for (p = PIPE_VIDEO_PROFILE_MPEG2_SIMPLE; p <= 
PIPE_VIDEO_PROFILE_HEVC_MAIN_444; ++p) {
+  if (u_reduce_video_profile(p) == PIPE_VIDEO_FORMAT_MPEG4 && 
!debug_get_option_mpeg4())
+ continue;
+
   if (pscreen->get_video_param(pscreen, p, 
PIPE_VIDEO_ENTRYPOINT_BITSTREAM, PIPE_VIDEO_CAP_SUPPORTED)) {
  vap = PipeToProfile(p);
  if (vap != VAProfileNone)
 profile_list[(*num_profiles)++] = vap;
   }
+   }
 
/* Support postprocessing through vl_compositor */
profile_list[(*num_profiles)++] = VAProfileNone;
-- 
2.5.0

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[Mesa-dev] [PATCH 1/8] st/va: fix post process dirty area handling

[Christian König]

From: Christian König 

The dirty area in this call isn't related to the screen at all.

Signed-off-by: Christian König 
---
 src/gallium/state_trackers/va/picture.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index a37a9b7..d0aa2d8 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -722,7 +722,6 @@ handleVAProcPipelineParameterBufferType(vlVaDriver *drv, 
vlVaContext *context, v
 {
struct u_rect src_rect;
struct u_rect dst_rect;
-   struct u_rect *dirty_area;
vlVaSurface *src_surface;
VAProcPipelineParameterBuffer *pipeline_param;
struct pipe_surface **surfaces;
@@ -763,12 +762,10 @@ handleVAProcPipelineParameterBufferType(vlVaDriver *drv, 
vlVaContext *context, v
dst_rect.x1 = pipeline_param->output_region->x + 
pipeline_param->output_region->width;
dst_rect.y1 = pipeline_param->output_region->y + 
pipeline_param->output_region->height;
 
-   dirty_area = drv->vscreen->get_dirty_area(drv->vscreen);
-
vl_compositor_clear_layers(>cstate);
vl_compositor_set_buffer_layer(>cstate, >compositor, 0, 
src_surface->buffer, _rect, NULL, VL_COMPOSITOR_WEAVE);
vl_compositor_set_layer_dst_area(>cstate, 0, _rect);
-   vl_compositor_render(>cstate, >compositor, psurf, dirty_area, 
true);
+   vl_compositor_render(>cstate, >compositor, psurf, NULL, true);
 
screen->fence_reference(screen, _surface->fence, NULL);
drv->pipe->flush(drv->pipe, _surface->fence, 0);
-- 
2.5.0

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[Mesa-dev] [PATCH 7/8] st/va: move HEVC functions into separate file

[Christian König]

From: Christian König 

Signed-off-by: Christian König 
---
 src/gallium/state_trackers/va/Makefile.sources |   1 +
 src/gallium/state_trackers/va/picture.c| 174 +
 src/gallium/state_trackers/va/picture_hevc.c   | 159 ++
 src/gallium/state_trackers/va/va_private.h |   3 +
 4 files changed, 167 insertions(+), 170 deletions(-)
 create mode 100644 src/gallium/state_trackers/va/picture_hevc.c

diff --git a/src/gallium/state_trackers/va/Makefile.sources 
b/src/gallium/state_trackers/va/Makefile.sources
index 74cc34e..daebf01 100644
--- a/src/gallium/state_trackers/va/Makefile.sources
+++ b/src/gallium/state_trackers/va/Makefile.sources
@@ -8,6 +8,7 @@ C_SOURCES := \
picture_mpeg12.c \
picture_mpeg4.c \
picture_h264.c \
+   picture_hevc.c \
picture_vc1.c \
postproc.c \
subpicture.c \
diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index fc10bf4..ce75e2d 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -89,9 +89,6 @@ vlVaGetReferenceFrame(vlVaDriver *drv, VASurfaceID surface_id,
 static void
 handlePictureParameterBuffer(vlVaDriver *drv, vlVaContext *context, vlVaBuffer 
*buf)
 {
-   VAPictureParameterBufferHEVC *hevc;
-   unsigned int i;
-
switch (u_reduce_video_profile(context->decoder->profile)) {
case PIPE_VIDEO_FORMAT_MPEG12:
   vlVaHandlePictureParameterBufferMPEG12(drv, context, buf);
@@ -110,154 +107,7 @@ handlePictureParameterBuffer(vlVaDriver *drv, vlVaContext 
*context, vlVaBuffer *
   break;
 
   case PIPE_VIDEO_FORMAT_HEVC:
-  assert(buf->size >= sizeof(VAPictureParameterBufferHEVC) && 
buf->num_elements == 1);
-  hevc = buf->data;
-  context->desc.h265.pps->sps->chroma_format_idc = 
hevc->pic_fields.bits.chroma_format_idc;
-  context->desc.h265.pps->sps->separate_colour_plane_flag =
- hevc->pic_fields.bits.separate_colour_plane_flag;
-  context->desc.h265.pps->sps->pic_width_in_luma_samples = 
hevc->pic_width_in_luma_samples;
-  context->desc.h265.pps->sps->pic_height_in_luma_samples = 
hevc->pic_height_in_luma_samples;
-  context->desc.h265.pps->sps->bit_depth_luma_minus8 = 
hevc->bit_depth_luma_minus8;
-  context->desc.h265.pps->sps->bit_depth_chroma_minus8 = 
hevc->bit_depth_chroma_minus8;
-  context->desc.h265.pps->sps->log2_max_pic_order_cnt_lsb_minus4 =
- hevc->log2_max_pic_order_cnt_lsb_minus4;
-  context->desc.h265.pps->sps->sps_max_dec_pic_buffering_minus1 =
- hevc->sps_max_dec_pic_buffering_minus1;
-  context->desc.h265.pps->sps->log2_min_luma_coding_block_size_minus3 =
- hevc->log2_min_luma_coding_block_size_minus3;
-  context->desc.h265.pps->sps->log2_diff_max_min_luma_coding_block_size =
- hevc->log2_diff_max_min_luma_coding_block_size;
-  context->desc.h265.pps->sps->log2_min_transform_block_size_minus2 =
- hevc->log2_min_transform_block_size_minus2;
-  context->desc.h265.pps->sps->log2_diff_max_min_transform_block_size =
- hevc->log2_diff_max_min_transform_block_size;
-  context->desc.h265.pps->sps->max_transform_hierarchy_depth_inter =
- hevc->max_transform_hierarchy_depth_inter;
-  context->desc.h265.pps->sps->max_transform_hierarchy_depth_intra =
- hevc->max_transform_hierarchy_depth_intra;
-  context->desc.h265.pps->sps->scaling_list_enabled_flag =
- hevc->pic_fields.bits.scaling_list_enabled_flag;
-  context->desc.h265.pps->sps->amp_enabled_flag = 
hevc->pic_fields.bits.amp_enabled_flag;
-  context->desc.h265.pps->sps->sample_adaptive_offset_enabled_flag =
- hevc->slice_parsing_fields.bits.sample_adaptive_offset_enabled_flag;
-  context->desc.h265.pps->sps->pcm_enabled_flag = 
hevc->pic_fields.bits.pcm_enabled_flag;
-  if (hevc->pic_fields.bits.pcm_enabled_flag == 1) {
- context->desc.h265.pps->sps->pcm_sample_bit_depth_luma_minus1 =
-hevc->pcm_sample_bit_depth_luma_minus1;
- context->desc.h265.pps->sps->pcm_sample_bit_depth_chroma_minus1 =
-hevc->pcm_sample_bit_depth_chroma_minus1;
- 
context->desc.h265.pps->sps->log2_min_pcm_luma_coding_block_size_minus3 =
-hevc->log2_min_pcm_luma_coding_block_size_minus3;
- 
context->desc.h265.pps->sps->log2_diff_max_min_pcm_luma_coding_block_size =
-hevc->log2_diff_max_min_pcm_luma_coding_block_size;
- context->desc.h265.pps->sps->pcm_loop_filter_disabled_flag =
-hevc->pic_fields.bits.pcm_loop_filter_disabled_flag;
-  }
-  context->desc.h265.pps->sps->num_short_term_ref_pic_sets = 
hevc->num_short_term_ref_pic_sets;
-  context->desc.h265.pps->sps->long_term_ref_pics_present_flag =
- hevc->slice_parsing_fields.bits.long_term_ref_pics_present_flag;
-  

[Mesa-dev] [PATCH 8/8] st/va: fix indentation

[Christian König]

From: Christian König 

Signed-off-by: Christian König 
---
 src/gallium/state_trackers/va/picture.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index ce75e2d..25d2940 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -192,19 +192,19 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
format = u_reduce_video_profile(context->decoder->profile);
switch (format) {
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
- if (bufHasStartcode(buf, 0x01, 24))
-break;
+  if (bufHasStartcode(buf, 0x01, 24))
+ break;
 
- buffers[num_buffers] = (void *const)_code_h264;
- sizes[num_buffers++] = sizeof(start_code_h264);
+  buffers[num_buffers] = (void *const)_code_h264;
+  sizes[num_buffers++] = sizeof(start_code_h264);
   break;
case PIPE_VIDEO_FORMAT_HEVC:
   if (bufHasStartcode(buf, 0x01, 24))
  break;
 
- buffers[num_buffers] = (void *const)_code_h265;
- sizes[num_buffers++] = sizeof(start_code_h265);
- break;
+  buffers[num_buffers] = (void *const)_code_h265;
+  sizes[num_buffers++] = sizeof(start_code_h265);
+  break;
case PIPE_VIDEO_FORMAT_VC1:
   if (bufHasStartcode(buf, 0x010d, 32) ||
   bufHasStartcode(buf, 0x010c, 32) ||
-- 
2.5.0

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[Mesa-dev] [PATCH 2/8] st/va: move post processing function into own file

[Christian König]

From: Christian König 

Signed-off-by: Christian König 
---
 src/gallium/state_trackers/va/Makefile.sources |  1 +
 src/gallium/state_trackers/va/picture.c| 58 +---
 src/gallium/state_trackers/va/postproc.c   | 94 ++
 src/gallium/state_trackers/va/va_private.h |  4 ++
 4 files changed, 100 insertions(+), 57 deletions(-)
 create mode 100644 src/gallium/state_trackers/va/postproc.c

diff --git a/src/gallium/state_trackers/va/Makefile.sources 
b/src/gallium/state_trackers/va/Makefile.sources
index d281cde..dd0cef5 100644
--- a/src/gallium/state_trackers/va/Makefile.sources
+++ b/src/gallium/state_trackers/va/Makefile.sources
@@ -5,6 +5,7 @@ C_SOURCES := \
display.c \
image.c \
picture.c \
+   postproc.c \
subpicture.c \
surface.c \
va_private.h
diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index d0aa2d8..23a1ffa 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -717,62 +717,6 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
   num_buffers, (const void * const*)buffers, sizes);
 }
 
-static VAStatus
-handleVAProcPipelineParameterBufferType(vlVaDriver *drv, vlVaContext *context, 
vlVaBuffer *buf)
-{
-   struct u_rect src_rect;
-   struct u_rect dst_rect;
-   vlVaSurface *src_surface;
-   VAProcPipelineParameterBuffer *pipeline_param;
-   struct pipe_surface **surfaces;
-   struct pipe_screen *screen;
-   struct pipe_surface *psurf;
-
-   if (!drv || !context)
-  return VA_STATUS_ERROR_INVALID_CONTEXT;
-
-   if (!buf || !buf->data)
-  return VA_STATUS_ERROR_INVALID_BUFFER;
-
-   if (!context->target)
-  return VA_STATUS_ERROR_INVALID_SURFACE;
-
-   pipeline_param = (VAProcPipelineParameterBuffer *)buf->data;
-
-   src_surface = handle_table_get(drv->htab, pipeline_param->surface);
-   if (!src_surface || !src_surface->buffer)
-  return VA_STATUS_ERROR_INVALID_SURFACE;
-
-   surfaces = context->target->get_surfaces(context->target);
-
-   if (!surfaces || !surfaces[0])
-  return VA_STATUS_ERROR_INVALID_SURFACE;
-
-   screen = drv->pipe->screen;
-
-   psurf = surfaces[0];
-
-   src_rect.x0 = pipeline_param->surface_region->x;
-   src_rect.y0 = pipeline_param->surface_region->y;
-   src_rect.x1 = pipeline_param->surface_region->x + 
pipeline_param->surface_region->width;
-   src_rect.y1 = pipeline_param->surface_region->y + 
pipeline_param->surface_region->height;
-
-   dst_rect.x0 = pipeline_param->output_region->x;
-   dst_rect.y0 = pipeline_param->output_region->y;
-   dst_rect.x1 = pipeline_param->output_region->x + 
pipeline_param->output_region->width;
-   dst_rect.y1 = pipeline_param->output_region->y + 
pipeline_param->output_region->height;
-
-   vl_compositor_clear_layers(>cstate);
-   vl_compositor_set_buffer_layer(>cstate, >compositor, 0, 
src_surface->buffer, _rect, NULL, VL_COMPOSITOR_WEAVE);
-   vl_compositor_set_layer_dst_area(>cstate, 0, _rect);
-   vl_compositor_render(>cstate, >compositor, psurf, NULL, true);
-
-   screen->fence_reference(screen, _surface->fence, NULL);
-   drv->pipe->flush(drv->pipe, _surface->fence, 0);
-
-   return VA_STATUS_SUCCESS;
-}
-
 VAStatus
 vlVaRenderPicture(VADriverContextP ctx, VAContextID context_id, VABufferID 
*buffers, int num_buffers)
 {
@@ -815,7 +759,7 @@ vlVaRenderPicture(VADriverContextP ctx, VAContextID 
context_id, VABufferID *buff
  handleVASliceDataBufferType(context, buf);
  break;
   case VAProcPipelineParameterBufferType:
- vaStatus = handleVAProcPipelineParameterBufferType(drv, context, buf);
+ vaStatus = vlVaHandleVAProcPipelineParameterBufferType(drv, context, 
buf);
  break;
 
   default:
diff --git a/src/gallium/state_trackers/va/postproc.c 
b/src/gallium/state_trackers/va/postproc.c
new file mode 100644
index 000..657095b
--- /dev/null
+++ b/src/gallium/state_trackers/va/postproc.c
@@ -0,0 +1,94 @@
+/**
+ *
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT 

[Mesa-dev] [PATCH 6/8] st/va: move MPEG4 functions into separate file

[Christian König]

From: Christian König 

Signed-off-by: Christian König 
---
 src/gallium/state_trackers/va/Makefile.sources |   1 +
 src/gallium/state_trackers/va/picture.c| 186 +-
 src/gallium/state_trackers/va/picture_mpeg4.c  | 209 +
 src/gallium/state_trackers/va/va_private.h |   4 +
 4 files changed, 220 insertions(+), 180 deletions(-)
 create mode 100644 src/gallium/state_trackers/va/picture_mpeg4.c

diff --git a/src/gallium/state_trackers/va/Makefile.sources 
b/src/gallium/state_trackers/va/Makefile.sources
index 4e42d5a..74cc34e 100644
--- a/src/gallium/state_trackers/va/Makefile.sources
+++ b/src/gallium/state_trackers/va/Makefile.sources
@@ -6,6 +6,7 @@ C_SOURCES := \
image.c \
picture.c \
picture_mpeg12.c \
+   picture_mpeg4.c \
picture_h264.c \
picture_vc1.c \
postproc.c \
diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index 24f26ed..fc10bf4 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -89,13 +89,8 @@ vlVaGetReferenceFrame(vlVaDriver *drv, VASurfaceID 
surface_id,
 static void
 handlePictureParameterBuffer(vlVaDriver *drv, vlVaContext *context, vlVaBuffer 
*buf)
 {
-   VAPictureParameterBufferMPEG4 *mpeg4;
VAPictureParameterBufferHEVC *hevc;
-   vlVaSurface *surf_forward;
-   vlVaSurface *surf_backward;
unsigned int i;
-   static const uint8_t default_intra_quant_matrix[64] = { 0 };
-   static const uint8_t default_non_intra_quant_matrix[64] = { 0 };
 
switch (u_reduce_video_profile(context->decoder->profile)) {
case PIPE_VIDEO_FORMAT_MPEG12:
@@ -111,69 +106,7 @@ handlePictureParameterBuffer(vlVaDriver *drv, vlVaContext 
*context, vlVaBuffer *
   break;
 
case PIPE_VIDEO_FORMAT_MPEG4:
-  assert(buf->size >= sizeof(VAPictureParameterBufferMPEG4) && 
buf->num_elements == 1);
-  mpeg4 = buf->data;
-
-  context->mpeg4.pps = *mpeg4;
-
-  /* vop_width */
-  /* vop_height */
-  /* forward_reference_picture */
-  /* backward_reference_picture */
-  context->desc.mpeg4.short_video_header =
-mpeg4->vol_fields.bits.short_video_header;
-  /* chroma_format */
-  context->desc.mpeg4.interlaced = mpeg4->vol_fields.bits.interlaced;
-  /* obmc_disable */
-  /* sprite_enable */
-  /* sprite_warping_accuracy */
-  context->desc.mpeg4.quant_type = mpeg4->vol_fields.bits.quant_type;
-  context->desc.mpeg4.quarter_sample = 
mpeg4->vol_fields.bits.quarter_sample;
-  /* data_partitioned */
-  /* reversible_vlc */
-  context->desc.mpeg4.resync_marker_disable =
-mpeg4->vol_fields.bits.resync_marker_disable;
-  /* no_of_sprite_warping_points */
-  /* sprite_trajectory_du */
-  /* sprite_trajectory_dv */
-  /* quant_precision */
-  context->desc.mpeg4.vop_coding_type = 
mpeg4->vop_fields.bits.vop_coding_type;
-  /* backward_reference_vop_coding_type */
-  /* vop_rounding_type */
-  /* intra_dc_vlc_thr */
-  context->desc.mpeg4.top_field_first =
-mpeg4->vop_fields.bits.top_field_first;
-  context->desc.mpeg4.alternate_vertical_scan_flag =
-mpeg4->vop_fields.bits.alternate_vertical_scan_flag;
-  context->desc.mpeg4.vop_fcode_forward = mpeg4->vop_fcode_forward;
-  context->desc.mpeg4.vop_fcode_backward = mpeg4->vop_fcode_backward;
-  context->desc.mpeg4.vop_time_increment_resolution =
-mpeg4->vop_time_increment_resolution;
-  /* num_gobs_in_vop */
-  /* num_macroblocks_in_gob */
-  context->desc.mpeg4.trb[0] = mpeg4->TRB;
-  context->desc.mpeg4.trb[1] = mpeg4->TRB;
-  context->desc.mpeg4.trd[0] = mpeg4->TRD;
-  context->desc.mpeg4.trd[1] = mpeg4->TRD;
-
-  /* default [non-]intra quant matrix because mpv does not set these
- matrices */
-  if (!context->desc.mpeg4.intra_matrix)
- context->desc.mpeg4.intra_matrix = default_intra_quant_matrix;
-  if (!context->desc.mpeg4.non_intra_matrix)
- context->desc.mpeg4.non_intra_matrix = default_non_intra_quant_matrix;
-
-  surf_forward = handle_table_get(drv->htab, 
mpeg4->forward_reference_picture);
-  if (surf_forward)
- context->desc.mpeg4.ref[0] = surf_forward->buffer;
-  surf_backward = handle_table_get(drv->htab, 
mpeg4->backward_reference_picture);
-  if (surf_backward)
- context->desc.mpeg4.ref[1] = surf_backward->buffer;
-
-  context->mpeg4.vti_bits = 0;
-  for (i = context->desc.mpeg4.vop_time_increment_resolution; i > 0; i /= 
2)
- ++context->mpeg4.vti_bits;
-
+  vlVaHandlePictureParameterBufferMPEG4(drv, context, buf);
   break;
 
   case PIPE_VIDEO_FORMAT_HEVC:
@@ -335,7 +268,6 @@ handlePictureParameterBuffer(vlVaDriver *drv, vlVaContext 
*context, vlVaBuffer *
 static void
 handleIQMatrixBuffer(vlVaContext 

Re: [Mesa-dev] [PATCH] configure.ac: use pkg-config for libelf

[Jan Vesely]

On Tue, 2015-11-24 at 01:07 +1100, Jonathan Gray wrote:
> On Mon, Nov 23, 2015 at 07:52:44AM -0600, Jan Vesely wrote:
> > On Mon, 2015-11-23 at 14:24 +1100, Jonathan Gray wrote:
> > > Use PKG_CHECK_MODULES to get the flags to link libelf.
> > 
> > This has been discussed before, and it does not work with elfutils:
> > http://lists.freedesktop.org/archives/mesa-dev/2014-October/069748.
> > html
> > 
> > Jan
> 
> Back to
> export LDFLAGS=-L/usr/local/lib
> export CPPFLAGS="-I/usr/local/include -I/usr/local/include/libelf"
> 
> to make mesa build when linking libelf here on OpenBSD then...
> 
> $ pkg-config --cflags
> libelf   
>    
> -I/usr/local/include/libelf -I/usr/local/include
> 
> $ pkg-config --libs libelf   
> -L/usr/local/lib -lelf

I'm no autotools expert, but maybe we can combine both approaches; try
pkg-config first, if it fails, fall back to the old way.

Jan

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Re: [Mesa-dev] [PATCH 09/13] i965: Drop #include of main/glheader.h.

[Matt Turner]

On Mon, Nov 23, 2015 at 1:57 PM, Ian Romanick  wrote:
> Have you built this series with debug and release builds?  There have
> been cases in the past where removing or changing headers worked fine in
> one but not the other.

Yes.
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Re: [Mesa-dev] [PATCH] glsl: implement recent spec update to SSO validation

[Ian Romanick]

On 11/23/2015 01:51 PM, Ian Romanick wrote:
> On 11/23/2015 04:24 AM, Timothy Arceri wrote:
>> From: Timothy Arceri 
>>
>> Enables 200+ dEQP SSO tests to proceed passed validation,
>  ^^ past?
> 
>> while not regressing ES31-CTS.sepshaderobjs.PipelineApi.
>>
>> Cc: Tapani Pälli 
>> Cc: Gregory Hainaut 
>> ---
>>  src/mesa/main/pipelineobj.c | 25 -
>>  1 file changed, 24 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/mesa/main/pipelineobj.c b/src/mesa/main/pipelineobj.c
>> index 90dff13..99e1491 100644
>> --- a/src/mesa/main/pipelineobj.c
>> +++ b/src/mesa/main/pipelineobj.c
>> @@ -646,7 +646,7 @@ _mesa_GetProgramPipelineiv(GLuint pipeline, GLenum 
>> pname, GLint *params)
>>return;
>> case GL_VALIDATE_STATUS:
>>/* If pipeline is not bound, return initial value 0. */
>> -  *params = (ctx->_Shader->Name != pipe->Name) ? 0 : pipe->Validated;
>> +  *params = pipe->Validated;
> 
> I too have a minor problem with this change.  I don't see anything in
> the commit message or the comment below that motivates this change.  I
> have no way to determine whether it's correct or not based on the
> available information.
> 
> Now I have to do some archaeology... looking back at ba02f7a3, where
> this code and comment were originally added, I think it's at least
> possible that both ways are wrong.  The spec text quoted in the older
> commit says, emphasis mine,
> 
> "If pipeline is a name that has been generated (without subsequent
> deletion) by GenProgramPipelines, but refers to a program pipeline
> object that has not been *previously bound*, the GL first creates a
> new state vector in the same manner as when BindProgramPipeline
> creates a new program pipeline object."
> 
> But the existing code checks that the pipeline is *currently bound*,
> which is quite different from "previously bound."  I have to combine
> that with the rest of the discussion (about the other part of this
> commit) to understand why this change is correct.
> 
> This should be a separate commit.  It should be a revert of ba02f7a3
> with suitable justification.  If my understanding is correct, that
> justification should be:
> 
> The commit checked whether the pipeline was currently bound instead
> of checking whether it had ever been bound.  The previous setting
> of Validated during object creation makes this unnecessary.  The
> real problem was that Validated was not properly set to false
> elsewhere in the code.  This is fixed by a later patch.
> 
> Yeah?
> 
> If that's the case and the two nits below get fixed, the resulting two
> patches will be
> 
> Reviewed-by: Ian Romanick 

Also!

Cc: "11.1" 

>>return;
>> case GL_VERTEX_SHADER:
>>*params = pipe->CurrentProgram[MESA_SHADER_VERTEX]
>> @@ -858,6 +858,29 @@ _mesa_validate_program_pipeline(struct gl_context* ctx,
>>}
>> }
>>  
>> +   /* Section 11.1.3.11 (Validation) of the OpenGL 4.5 spec says:
>> +*
>> +*"An INVALID_OPERATION error is generated by any command that trans-
>> +*fers vertices to the GL or launches compute work if the current set
>> +*of active program objects cannot be executed, for reasons 
>> including:
>> +*
>> +*   ...
>> +*
>> +*   - There is no current program object specified by UseProgram,
>> +* there is a current program pipeline object, and that object is
>> +* empty (no executable code is installed for any stage).
>> +*/
>> +   bool program_empty = true;
> 
> Mixing declarations and code.  I'm preemptively complaining on Vinson's
> behalf. :)
> 
>> +   for (i = 0; i < MESA_SHADER_STAGES; i++) {
>> +  if (pipe->CurrentProgram[i]) {
>> + program_empty = false;
>> + break;
>> +  }
>> +   }
> 
> Blank line here.
> 
>> +   if(program_empty) {
> ^ space here
> 
>> +  goto err;
>> +   }
>> +
>> /* Section 2.11.11 (Shader Execution), subheading "Validation," of the
>>  * OpenGL 4.1 spec says:
>>  *
> 
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Re: [Mesa-dev] [PATCH] i965: Use ull immediates in brw_inst_bits

[Ian Romanick]

On 11/23/2015 02:01 PM, Ian Romanick wrote:
> On 11/23/2015 10:54 AM, Jason Ekstrand wrote:
>> This fixes a regression introduced in b1a83b5d1 that caused basically all
>> shaders to fail to compile on 32-bit platforms.
> 
> Here's the part from the b1a83b5d1 commit message that makes me sad:
> 
> v2 (Iago)
>  - Replace ~0 by ~0ull
>  - Removed unnecessary parenthesis
> 
> This patch is
> 
> Reviewed-by: Ian Romanick 

Also!

Cc: "11.1" 

>> Reported-by: Mark Janes 
>> Cc: Matt Turner 
>> ---
>>  src/mesa/drivers/dri/i965/brw_inst.h | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_inst.h 
>> b/src/mesa/drivers/dri/i965/brw_inst.h
>> index b2afe17..cd9f6ef 100644
>> --- a/src/mesa/drivers/dri/i965/brw_inst.h
>> +++ b/src/mesa/drivers/dri/i965/brw_inst.h
>> @@ -694,7 +694,7 @@ brw_inst_bits(const brw_inst *inst, unsigned high, 
>> unsigned low)
>> high %= 64;
>> low %= 64;
>>  
>> -   const uint64_t mask = (~0ul >> (64 - (high - low + 1)));
>> +   const uint64_t mask = (~0ull >> (64 - (high - low + 1)));
>>  
>> return (inst->data[word] >> low) & mask;
>>  }
>> @@ -713,7 +713,7 @@ brw_inst_set_bits(brw_inst *inst, unsigned high, 
>> unsigned low, uint64_t value)
>> high %= 64;
>> low %= 64;
>>  
>> -   const uint64_t mask = (~0ul >> (64 - (high - low + 1))) << low;
>> +   const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low;
>>  
>> /* Make sure the supplied value actually fits in the given bitfield. */
>> assert((value & (mask >> low)) == value);
>>
> 

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[Mesa-dev] [PATCH 2/2] r600: add missing register to initial state

[Dave Airlie]

From: Dave Airlie 

We really should initialise HS/LS_2 and SQ_LDS_ALLOC exists
on all evergreen not just cayman, so we should initialise
it as well.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/evergreen_compute.c |  2 +-
 src/gallium/drivers/r600/evergreen_state.c   | 19 ++-
 src/gallium/drivers/r600/evergreend.h|  1 -
 3 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_compute.c 
b/src/gallium/drivers/r600/evergreen_compute.c
index 5743e3f..010d109 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -402,7 +402,7 @@ static void evergreen_emit_direct_dispatch(
assert(lds_size <= 8160);
}
 
-   radeon_compute_set_context_reg(cs, CM_R_0288E8_SQ_LDS_ALLOC,
+   radeon_compute_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC,
lds_size | (num_waves << 14));
 
/* Dispatch packet */
diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 684eee7..5333761 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2266,7 +2266,7 @@ static void cayman_init_atom_start_cs(struct r600_context 
*rctx)
struct r600_command_buffer *cb = >start_cs_cmd;
int tmp, i;
 
-   r600_init_command_buffer(cb, 320);
+   r600_init_command_buffer(cb, 326);
 
/* This must be first. */
r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
@@ -2324,8 +2324,8 @@ static void cayman_init_atom_start_cs(struct r600_context 
*rctx)
r600_store_value(cb, 0x76543210); /* 
CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
r600_store_value(cb, 0xfedcba98); /* 
CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
 
-   r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
-   r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
+   r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
+   r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
 
 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
@@ -2375,6 +2375,9 @@ static void cayman_init_atom_start_cs(struct r600_context 
*rctx)
r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, 
S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, 
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, 
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
+   r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, 
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
+   r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, 
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
+
r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
 
/* to avoid GPU doing any preloading of constant from random address */
@@ -2545,7 +2548,7 @@ void evergreen_init_atom_start_cs(struct r600_context 
*rctx)
return;
}
 
-   r600_init_command_buffer(cb, 320);
+   r600_init_command_buffer(cb, 330);
 
/* This must be first. */
r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
@@ -2817,6 +2820,8 @@ void evergreen_init_atom_start_cs(struct r600_context 
*rctx)
r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, 
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, 
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
+   r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, 
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
+   r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, 
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
 
/* to avoid GPU doing any preloading of constant from random address */
r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
@@ -2851,7 +2856,11 @@ void evergreen_init_atom_start_cs(struct r600_context 
*rctx)
r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
-   r600_store_context_reg(cb, R_0288EC_SQ_LDS_ALLOC_PS, 0);
+
+   r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
+   r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
+   r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
+
r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0);
 
eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
diff --git a/src/gallium/drivers/r600/evergreend.h 

[Mesa-dev] [PATCH 1/2] r600: define registers required for tessellation

[Dave Airlie]

From: Dave Airlie 

This adds the defines for a bunch of registers and shader
values that are required to implement tessellation.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/evergreend.h | 123 +++---
 src/gallium/drivers/r600/r600_sq.h|   8 +++
 2 files changed, 108 insertions(+), 23 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreend.h 
b/src/gallium/drivers/r600/evergreend.h
index 25237c6..dbee9d5 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -463,6 +463,39 @@
 #define R_0286EC_SPI_COMPUTE_NUM_THREAD_X0x0286EC
 #define R_0286F0_SPI_COMPUTE_NUM_THREAD_Y0x0286F0
 #define R_0286F4_SPI_COMPUTE_NUM_THREAD_Z0x0286F4
+#define R_028B6C_VGT_TF_PARAM0x028B6C
+#define   S_028B6C_TYPE(x)(((x) & 
0x03) << 0)
+#define   G_028B6C_TYPE(x)(((x) >> 
0) & 0x03)
+#define   C_028B6C_TYPE   
0xFFFC
+#define V_028B6C_TESS_ISOLINE   0x00
+#define V_028B6C_TESS_TRIANGLE  0x01
+#define V_028B6C_TESS_QUAD  0x02
+#define   S_028B6C_PARTITIONING(x)(((x) & 
0x07) << 2)
+#define   G_028B6C_PARTITIONING(x)(((x) >> 
2) & 0x07)
+#define   C_028B6C_PARTITIONING   
0xFFE3
+#define V_028B6C_PART_INTEGER   0x00
+#define V_028B6C_PART_POW2  0x01
+#define V_028B6C_PART_FRAC_ODD  0x02
+#define V_028B6C_PART_FRAC_EVEN 0x03
+#define   S_028B6C_TOPOLOGY(x)(((x) & 
0x07) << 5)
+#define   G_028B6C_TOPOLOGY(x)(((x) >> 
5) & 0x07)
+#define   C_028B6C_TOPOLOGY   
0xFF1F
+#define V_028B6C_OUTPUT_POINT   0x00
+#define V_028B6C_OUTPUT_LINE0x01
+#define V_028B6C_OUTPUT_TRIANGLE_CW 0x02
+#define V_028B6C_OUTPUT_TRIANGLE_CCW0x03
+#define   S_028B6C_RESERVED_REDUC_AXIS(x) (((x) & 
0x1) << 8)
+#define   G_028B6C_RESERVED_REDUC_AXIS(x) (((x) >> 
8) & 0x1)
+#define   C_028B6C_RESERVED_REDUC_AXIS
0xFEFF
+#define   S_028B6C_BUFFER_ACCESS_MODE(x)  (((x) & 
0x1) << 9)
+#define   G_028B6C_BUFFER_ACCESS_MODE(x)  (((x) >> 
9) & 0x1)
+#define   C_028B6C_BUFFER_ACCESS_MODE 
0xFDFF
+#define V_028B6C_PATCH_MAJOR0x00
+#define V_028B6C_TF_MAJOR   0x01
+#define   S_028B6C_NUM_DS_WAVES_PER_SIMD  (((x) & 
0xf) << 10)
+#define   G_028B6C_NUM_DS_WAVES_PER_SIMD  (((x) >> 
10) & 0xF)
+#define   C_028B6C_NUM_DS_WAVES_PER_SIMD  
0xC3FF
+
 #define R_028B74_VGT_DISPATCH_INITIATOR  0x028B74
 
 #define R_028800_DB_DEPTH_CONTROL0x028800
@@ -1260,6 +1293,16 @@
 #define R_00A430_TD_GS_SAMPLER0_BORDER_GREEN 0x00A430
 #define R_00A434_TD_GS_SAMPLER0_BORDER_BLUE  0x00A434
 #define R_00A438_TD_GS_SAMPLER0_BORDER_ALPHA 0x00A438
+#define R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX   0x00A43C
+#define R_00A440_TD_HS_SAMPLER0_BORDER_COLOR_RED 0x00A440
+#define R_00A444_TD_HS_SAMPLER0_BORDER_COLOR_GREEN   0x00A444
+#define R_00A448_TD_HS_SAMPLER0_BORDER_COLOR_BLUE0x00A448
+#define R_00A44C_TD_HS_SAMPLER0_BORDER_COLOR_ALPHA   0x00A44C
+#define R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX   0x00A450
+#define R_00A454_TD_LS_SAMPLER0_BORDER_COLOR_RED 0x00A454
+#define R_00A458_TD_LS_SAMPLER0_BORDER_COLOR_GREEN   0x00A458
+#define R_00A45C_TD_LS_SAMPLER0_BORDER_COLOR_BLUE0x00A45C
+#define R_00A460_TD_LS_SAMPLER0_BORDER_COLOR_ALPHA   0x00A460
 #define R_00A464_TD_CS_SAMPLER0_BORDER_INDEX 0x00A464
 #define R_00A468_TD_CS_SAMPLER0_BORDER_RED   0x00A468
 #define R_00A46C_TD_CS_SAMPLER0_BORDER_GREEN 0x00A46C
@@ -1383,7 +1426,7 @@
 #define V_008958_DI_PT_TRISTRIP0x0006
 #define V_008958_DI_PT_UNUSED_00x0007
 #define V_008958_DI_PT_UNUSED_10x0008
-#define V_008958_DI_PT_UNUSED_20x0009
+#define V_008958_DI_PT_PATCH   0x0009
 #define V_008958_DI_PT_LINELIST_ADJ

Re: [Mesa-dev] [PATCH] i965: Use ull immediates in brw_inst_bits

[Ian Romanick]

On 11/23/2015 10:54 AM, Jason Ekstrand wrote:
> This fixes a regression introduced in b1a83b5d1 that caused basically all
> shaders to fail to compile on 32-bit platforms.

Here's the part from the b1a83b5d1 commit message that makes me sad:

v2 (Iago)
 - Replace ~0 by ~0ull
 - Removed unnecessary parenthesis

This patch is

Reviewed-by: Ian Romanick 

> Reported-by: Mark Janes 
> Cc: Matt Turner 
> ---
>  src/mesa/drivers/dri/i965/brw_inst.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_inst.h 
> b/src/mesa/drivers/dri/i965/brw_inst.h
> index b2afe17..cd9f6ef 100644
> --- a/src/mesa/drivers/dri/i965/brw_inst.h
> +++ b/src/mesa/drivers/dri/i965/brw_inst.h
> @@ -694,7 +694,7 @@ brw_inst_bits(const brw_inst *inst, unsigned high, 
> unsigned low)
> high %= 64;
> low %= 64;
>  
> -   const uint64_t mask = (~0ul >> (64 - (high - low + 1)));
> +   const uint64_t mask = (~0ull >> (64 - (high - low + 1)));
>  
> return (inst->data[word] >> low) & mask;
>  }
> @@ -713,7 +713,7 @@ brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned 
> low, uint64_t value)
> high %= 64;
> low %= 64;
>  
> -   const uint64_t mask = (~0ul >> (64 - (high - low + 1))) << low;
> +   const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low;
>  
> /* Make sure the supplied value actually fits in the given bitfield. */
> assert((value & (mask >> low)) == value);
> 

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[Mesa-dev] [PATCH 13/13] i965: Clean up #includes in the compiler.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_blorp.cpp  |  1 -
 src/mesa/drivers/dri/i965/brw_blorp.h|  1 -
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp |  1 -
 src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h|  1 -
 src/mesa/drivers/dri/i965/brw_context.h  |  6 --
 src/mesa/drivers/dri/i965/brw_cs.c   |  1 +
 src/mesa/drivers/dri/i965/brw_disasm.c   |  3 ---
 src/mesa/drivers/dri/i965/brw_eu.h   |  2 --
 src/mesa/drivers/dri/i965/brw_fs.cpp | 13 -
 src/mesa/drivers/dri/i965/brw_fs.h   | 20 
 .../drivers/dri/i965/brw_fs_channel_expressions.cpp  |  2 --
 .../drivers/dri/i965/brw_fs_cmod_propagation.cpp |  2 +-
 .../drivers/dri/i965/brw_fs_combine_constants.cpp|  1 -
 .../drivers/dri/i965/brw_fs_copy_propagation.cpp |  1 +
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp   |  2 --
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp |  4 
 src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp|  3 +--
 .../drivers/dri/i965/brw_fs_vector_splitting.cpp |  4 +---
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 18 --
 src/mesa/drivers/dri/i965/brw_gs.c   |  1 +
 src/mesa/drivers/dri/i965/brw_link.cpp   |  7 +++
 src/mesa/drivers/dri/i965/brw_nir.c  |  1 -
 src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp   |  1 -
 src/mesa/drivers/dri/i965/brw_program.c  |  3 ---
 .../drivers/dri/i965/brw_schedule_instructions.cpp   |  2 --
 src/mesa/drivers/dri/i965/brw_shader.cpp |  9 +++--
 src/mesa/drivers/dri/i965/brw_shader.h   |  7 ++-
 src/mesa/drivers/dri/i965/brw_surface_formats.c  |  2 --
 src/mesa/drivers/dri/i965/brw_util.c |  4 
 src/mesa/drivers/dri/i965/brw_util.h |  2 --
 src/mesa/drivers/dri/i965/brw_vec4.cpp   |  7 ---
 src/mesa/drivers/dri/i965/brw_vec4.h | 14 +-
 .../drivers/dri/i965/brw_vec4_cmod_propagation.cpp   |  1 +
 .../drivers/dri/i965/brw_vec4_copy_propagation.cpp   |  4 +---
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp |  1 +
 src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp|  1 -
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp   |  1 -
 src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp  |  2 --
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp   |  3 +--
 src/mesa/drivers/dri/i965/brw_vs.h   |  3 ---
 src/mesa/drivers/dri/i965/brw_vue_map.c  |  1 -
 src/mesa/drivers/dri/i965/brw_wm.h   |  1 -
 src/mesa/drivers/dri/i965/brw_wm_iz.cpp  |  2 +-
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  1 +
 src/mesa/drivers/dri/i965/gen6_blorp.cpp |  2 --
 src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp|  1 +
 src/mesa/drivers/dri/i965/gen7_blorp.cpp |  2 --
 src/mesa/drivers/dri/i965/gen7_cs_state.c|  2 ++
 src/mesa/drivers/dri/i965/gen7_wm_surface_state.c|  1 +
 src/mesa/drivers/dri/i965/gen8_surface_state.c   |  1 +
 src/mesa/drivers/dri/i965/intel_debug.c  |  1 -
 src/mesa/drivers/dri/i965/intel_extensions.c |  2 --
 src/mesa/drivers/dri/i965/intel_resolve_map.c|  1 -
 .../drivers/dri/i965/test_vec4_copy_propagation.cpp  |  1 +
 .../drivers/dri/i965/test_vec4_register_coalesce.cpp |  1 +
 55 files changed, 28 insertions(+), 154 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 577b71e..1bc6d15 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -26,7 +26,6 @@
 #include "intel_fbo.h"
 
 #include "brw_blorp.h"
-#include "brw_defines.h"
 #include "brw_state.h"
 
 #define FILE_DEBUG_FLAG DEBUG_BLORP
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index ae494f9..a04a1df 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -25,7 +25,6 @@
 
 #include 
 
-#include "brw_context.h"
 #include "brw_reg.h"
 #include "intel_mipmap_tree.h"
 
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index cb3c6f7..6439fbf 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -23,7 +23,6 @@
 
 #include "main/teximage.h"
 #include "main/fbobject.h"
-#include "main/renderbuffer.h"
 
 #include "intel_fbo.h"
 
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h 
b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
index 8e44eb4..14a8e50 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
@@ -24,7 +24,6 @@
 #ifndef BRW_BLORP_BLIT_EU_H
 #define BRW_BLORP_BLIT_EU_H
 
-#include "brw_context.h"
 #include "brw_fs.h"
 
 class 

[Mesa-dev] [PATCH 04/13] i965: Remove unneeded forward declarations.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_gs.h   | 2 --
 src/mesa/drivers/dri/i965/intel_asm_annotation.h | 3 ---
 src/mesa/drivers/dri/i965/intel_fbo.h| 1 -
 src/mesa/drivers/dri/i965/intel_tex.h| 2 --
 4 files changed, 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_gs.h 
b/src/mesa/drivers/dri/i965/brw_gs.h
index 9879f3d..0c49bb6 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.h
+++ b/src/mesa/drivers/dri/i965/brw_gs.h
@@ -33,9 +33,7 @@
 extern "C" {
 #endif
 
-struct gl_context;
 struct gl_shader_program;
-struct gl_program;
 
 void
 brw_upload_gs_prog(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/intel_asm_annotation.h 
b/src/mesa/drivers/dri/i965/intel_asm_annotation.h
index 662a4b4..5faf6c6 100644
--- a/src/mesa/drivers/dri/i965/intel_asm_annotation.h
+++ b/src/mesa/drivers/dri/i965/intel_asm_annotation.h
@@ -28,9 +28,6 @@
 extern "C" {
 #endif
 
-struct bblock_t;
-struct brw_context;
-struct gl_program;
 struct backend_instruction;
 struct cfg_t;
 
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.h 
b/src/mesa/drivers/dri/i965/intel_fbo.h
index 5ba4c8f..89894cd 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.h
+++ b/src/mesa/drivers/dri/i965/intel_fbo.h
@@ -39,7 +39,6 @@ extern "C" {
 #endif
 
 struct intel_mipmap_tree;
-struct intel_texture_image;
 
 /**
  * Intel renderbuffer, derived from gl_renderbuffer.
diff --git a/src/mesa/drivers/dri/i965/intel_tex.h 
b/src/mesa/drivers/dri/i965/intel_tex.h
index dc83d08..35d0a64 100644
--- a/src/mesa/drivers/dri/i965/intel_tex.h
+++ b/src/mesa/drivers/dri/i965/intel_tex.h
@@ -30,8 +30,6 @@
 #include "main/formats.h"
 #include "brw_context.h"
 
-struct intel_renderbuffer;
-
 void intelInitTextureFuncs(struct dd_function_table *functions);
 
 void intelInitTextureImageFuncs(struct dd_function_table *functions);
-- 
2.4.9

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[Mesa-dev] [PATCH 07/13] i965: Mark functions called from C as extern "C".

[Matt Turner]

These functions' prototypes are marked with extern "C", which apparently
overrides a lack of extern "C" at the definition site if the prototype
has been seen first.
---
 src/mesa/drivers/dri/i965/brw_link.cpp   | 2 +-
 src/mesa/drivers/dri/i965/brw_shader.cpp | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 14421d4..b3a9747 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -198,7 +198,7 @@ process_glsl_ir(gl_shader_stage stage,
}
 }
 
-GLboolean
+extern "C" GLboolean
 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 {
struct brw_context *brw = brw_context(ctx);
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 6040c88..81f413e 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -143,7 +143,7 @@ brw_compiler_create(void *mem_ctx, const struct 
brw_device_info *devinfo)
return compiler;
 }
 
-struct gl_shader *
+extern "C" struct gl_shader *
 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 {
struct brw_shader *shader;
@@ -159,7 +159,7 @@ brw_new_shader(struct gl_context *ctx, GLuint name, GLuint 
type)
return >base;
 }
 
-void
+extern "C" void
 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
   unsigned surf_index)
 {
-- 
2.4.9

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Re: [Mesa-dev] [PATCH 8/8] st/va: fix indentation

[Leo Liu]

the patch series
Reviewed-by: Leo Liu 


On 11/23/2015 09:37 AM, Christian König wrote:

From: Christian König 

Signed-off-by: Christian König 
---
  src/gallium/state_trackers/va/picture.c | 14 +++---
  1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index ce75e2d..25d2940 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -192,19 +192,19 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
 format = u_reduce_video_profile(context->decoder->profile);
 switch (format) {
 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
- if (bufHasStartcode(buf, 0x01, 24))
-break;
+  if (bufHasStartcode(buf, 0x01, 24))
+ break;
  
- buffers[num_buffers] = (void *const)_code_h264;

- sizes[num_buffers++] = sizeof(start_code_h264);
+  buffers[num_buffers] = (void *const)_code_h264;
+  sizes[num_buffers++] = sizeof(start_code_h264);
break;
 case PIPE_VIDEO_FORMAT_HEVC:
if (bufHasStartcode(buf, 0x01, 24))
   break;
  
- buffers[num_buffers] = (void *const)_code_h265;

- sizes[num_buffers++] = sizeof(start_code_h265);
- break;
+  buffers[num_buffers] = (void *const)_code_h265;
+  sizes[num_buffers++] = sizeof(start_code_h265);
+  break;
 case PIPE_VIDEO_FORMAT_VC1:
if (bufHasStartcode(buf, 0x010d, 32) ||
bufHasStartcode(buf, 0x010c, 32) ||


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Re: [Mesa-dev] [PATCH] i965: Use ull immediates in brw_inst_bits

[Jason Ekstrand]

On Mon, Nov 23, 2015 at 10:54 AM, Jason Ekstrand  wrote:
> This fixes a regression introduced in b1a83b5d1 that caused basically all
> shaders to fail to compile on 32-bit platforms.
>
> Reported-by: Mark Janes 
> Cc: Matt Turner 
> ---
>  src/mesa/drivers/dri/i965/brw_inst.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_inst.h 
> b/src/mesa/drivers/dri/i965/brw_inst.h
> index b2afe17..cd9f6ef 100644
> --- a/src/mesa/drivers/dri/i965/brw_inst.h
> +++ b/src/mesa/drivers/dri/i965/brw_inst.h
> @@ -694,7 +694,7 @@ brw_inst_bits(const brw_inst *inst, unsigned high, 
> unsigned low)
> high %= 64;
> low %= 64;
>
> -   const uint64_t mask = (~0ul >> (64 - (high - low + 1)));
> +   const uint64_t mask = (~0ull >> (64 - (high - low + 1)));
>
> return (inst->data[word] >> low) & mask;
>  }
> @@ -713,7 +713,7 @@ brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned 
> low, uint64_t value)
> high %= 64;
> low %= 64;
>
> -   const uint64_t mask = (~0ul >> (64 - (high - low + 1))) << low;
> +   const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low;
>
> /* Make sure the supplied value actually fits in the given bitfield. */
> assert((value & (mask >> low)) == value);
> --
> 2.5.0.400.gff86faf
>
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Re: [Mesa-dev] [PATCH 09/13] i965: Drop #include of main/glheader.h.

[Ian Romanick]

On 11/23/2015 02:09 PM, Matt Turner wrote:
> On Mon, Nov 23, 2015 at 1:57 PM, Ian Romanick  wrote:
>> Have you built this series with debug and release builds?  There have
>> been cases in the past where removing or changing headers worked fine in
>> one but not the other.
> 
> Yes.

Cool.  This series is

Reviewed-by: Ian Romanick 

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[Mesa-dev] [PATCH 08/13] i965: Push down inclusion of brw_program.h.

[Matt Turner]

We were including it in headers, which then caused it to be included in
tons of places it wasn't needed.
---
 src/mesa/drivers/dri/i965/brw_cs.c   | 1 +
 src/mesa/drivers/dri/i965/brw_cs.h   | 2 --
 src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp   | 1 +
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 1 +
 src/mesa/drivers/dri/i965/brw_gs.c   | 1 +
 src/mesa/drivers/dri/i965/brw_gs.h   | 1 -
 src/mesa/drivers/dri/i965/brw_link.cpp   | 1 +
 src/mesa/drivers/dri/i965/brw_program.c  | 1 +
 src/mesa/drivers/dri/i965/brw_program.h  | 2 ++
 src/mesa/drivers/dri/i965/brw_state_cache.c  | 1 +
 src/mesa/drivers/dri/i965/brw_vec4.h | 1 -
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 1 +
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp   | 1 +
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp   | 1 +
 src/mesa/drivers/dri/i965/brw_vs.c   | 1 +
 src/mesa/drivers/dri/i965/brw_wm.c   | 1 +
 src/mesa/drivers/dri/i965/brw_wm.h   | 1 -
 18 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_cs.c 
b/src/mesa/drivers/dri/i965/brw_cs.c
index 263d224..a34c320 100644
--- a/src/mesa/drivers/dri/i965/brw_cs.c
+++ b/src/mesa/drivers/dri/i965/brw_cs.c
@@ -31,6 +31,7 @@
 #include "brw_state.h"
 #include "intel_batchbuffer.h"
 #include "brw_nir.h"
+#include "brw_program.h"
 
 static void
 assign_cs_binding_table_offsets(const struct brw_device_info *devinfo,
diff --git a/src/mesa/drivers/dri/i965/brw_cs.h 
b/src/mesa/drivers/dri/i965/brw_cs.h
index 899e340..9ce39fb 100644
--- a/src/mesa/drivers/dri/i965/brw_cs.h
+++ b/src/mesa/drivers/dri/i965/brw_cs.h
@@ -25,8 +25,6 @@
 #ifndef BRW_CS_H
 #define BRW_CS_H
 
-#include "brw_program.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 9343dda..4acac7d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -46,6 +46,7 @@
 #include "brw_nir.h"
 #include "brw_vec4_gs_visitor.h"
 #include "brw_cfg.h"
+#include "brw_program.h"
 #include "brw_dead_control_flow.h"
 #include "main/uniforms.h"
 #include "brw_fs_live_variables.h"
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 6493e05..48cb13d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -32,6 +32,7 @@
 #include "brw_eu.h"
 #include "brw_fs.h"
 #include "brw_cfg.h"
+#include "brw_program.h"
 
 static enum brw_reg_file
 brw_file_from_reg(fs_reg *reg)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 1e39b39..993367e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -30,6 +30,7 @@
 #include "brw_fs_surface_builder.h"
 #include "brw_vec4_gs_visitor.h"
 #include "brw_nir.h"
+#include "brw_program.h"
 
 using namespace brw;
 using namespace brw::surface_access;
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c 
b/src/mesa/drivers/dri/i965/brw_gs.c
index 149b43b..136be68 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -33,6 +33,7 @@
 #include "brw_state.h"
 #include "brw_ff_gs.h"
 #include "brw_nir.h"
+#include "brw_program.h"
 
 static void
 assign_gs_binding_table_offsets(const struct brw_device_info *devinfo,
diff --git a/src/mesa/drivers/dri/i965/brw_gs.h 
b/src/mesa/drivers/dri/i965/brw_gs.h
index 0c49bb6..13d6be8 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.h
+++ b/src/mesa/drivers/dri/i965/brw_gs.h
@@ -27,7 +27,6 @@
 #include 
 
 #include "brw_context.h"
-#include "brw_program.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index b3a9747..db0c22e 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -28,6 +28,7 @@
 #include "brw_fs.h"
 #include "brw_cfg.h"
 #include "brw_nir.h"
+#include "brw_program.h"
 #include "glsl/ir_optimization.h"
 #include "glsl/glsl_parser_extras.h"
 #include "main/shaderapi.h"
diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index f137c87..0c7692e 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -41,6 +41,7 @@
 #include "util/ralloc.h"
 #include "glsl/ir.h"
 
+#include "brw_program.h"
 #include "brw_context.h"
 #include "brw_shader.h"
 #include "brw_nir.h"
diff --git a/src/mesa/drivers/dri/i965/brw_program.h 
b/src/mesa/drivers/dri/i965/brw_program.h
index f8cf2b0..339b8e1 100644
--- a/src/mesa/drivers/dri/i965/brw_program.h
+++ b/src/mesa/drivers/dri/i965/brw_program.h
@@ -30,6 +30,8 @@
 extern "C" {
 #endif
 
+struct brw_context;
+
 void 

[Mesa-dev] [PATCH 06/13] i965: Push down inclusion of vbo/vbo.h.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_draw.h  | 1 -
 src/mesa/drivers/dri/i965/brw_primitive_restart.c | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.h 
b/src/mesa/drivers/dri/i965/brw_draw.h
index 695973b..23d98ef 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.h
+++ b/src/mesa/drivers/dri/i965/brw_draw.h
@@ -27,7 +27,6 @@
 #define BRW_DRAW_H
 
 #include "main/mtypes.h"   /* for struct gl_context... */
-#include "vbo/vbo.h"
 
 struct brw_context;
 
diff --git a/src/mesa/drivers/dri/i965/brw_primitive_restart.c 
b/src/mesa/drivers/dri/i965/brw_primitive_restart.c
index c8d9002..0c3db6b 100644
--- a/src/mesa/drivers/dri/i965/brw_primitive_restart.c
+++ b/src/mesa/drivers/dri/i965/brw_primitive_restart.c
@@ -28,6 +28,7 @@
 #include "main/imports.h"
 #include "main/bufferobj.h"
 #include "main/varray.h"
+#include "vbo/vbo.h"
 
 #include "brw_context.h"
 #include "brw_defines.h"
-- 
2.4.9

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[Mesa-dev] [PATCH 02/13] i965: Remove useless gen6_blorp.h/gen7_blorp.h headers.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/Makefile.sources |  2 --
 src/mesa/drivers/dri/i965/brw_blorp.cpp|  2 --
 src/mesa/drivers/dri/i965/brw_blorp.h  |  7 +
 src/mesa/drivers/dri/i965/gen6_blorp.cpp   |  1 -
 src/mesa/drivers/dri/i965/gen6_blorp.h | 41 --
 src/mesa/drivers/dri/i965/gen7_blorp.cpp   |  1 -
 src/mesa/drivers/dri/i965/gen7_blorp.h | 41 --
 7 files changed, 7 insertions(+), 88 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_blorp.h
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_blorp.h

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 5a88d66..5e805fa 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -162,7 +162,6 @@ i965_FILES = \
brw_wm_state.c \
brw_wm_surface_state.c \
gen6_blorp.cpp \
-   gen6_blorp.h \
gen6_cc.c \
gen6_clip_state.c \
gen6_depth_state.c \
@@ -180,7 +179,6 @@ i965_FILES = \
gen6_vs_state.c \
gen6_wm_state.c \
gen7_blorp.cpp \
-   gen7_blorp.h \
gen7_cs_state.c \
gen7_disable.c \
gen7_gs_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index df2969d..577b71e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -28,8 +28,6 @@
 #include "brw_blorp.h"
 #include "brw_defines.h"
 #include "brw_state.h"
-#include "gen6_blorp.h"
-#include "gen7_blorp.h"
 
 #define FILE_DEBUG_FLAG DEBUG_BLORP
 
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index dd28d81..ae494f9 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -238,6 +238,13 @@ public:
 void
 brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params);
 
+void
+gen6_blorp_exec(struct brw_context *brw,
+const brw_blorp_params *params);
+
+void
+gen7_blorp_exec(struct brw_context *brw,
+const brw_blorp_params *params);
 
 /**
  * Parameters for a HiZ or depth resolve operation.
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 74f3a70..23fea5a 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -32,7 +32,6 @@
 #include "brw_state.h"
 
 #include "brw_blorp.h"
-#include "gen6_blorp.h"
 
 /**
  * \name Constants for BLORP VBO
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.h 
b/src/mesa/drivers/dri/i965/gen6_blorp.h
deleted file mode 100644
index 1b273a4..000
--- a/src/mesa/drivers/dri/i965/gen6_blorp.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright © 2011 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#pragma once
-
-#include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct intel_mipmap_tree;
-
-#ifdef __cplusplus
-}
-
-void
-gen6_blorp_exec(struct brw_context *brw,
-const brw_blorp_params *params);
-
-#endif
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index f90e78e..4c6ab0c 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -32,7 +32,6 @@
 #include "brw_state.h"
 
 #include "brw_blorp.h"
-#include "gen7_blorp.h"
 
 
 /* 3DSTATE_URB_VS
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.h 
b/src/mesa/drivers/dri/i965/gen7_blorp.h
deleted file mode 100644
index 6443430..000
--- a/src/mesa/drivers/dri/i965/gen7_blorp.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright © 2011 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in 

[Mesa-dev] [PATCH 05/13] i965: Remove duplicate #includes.

[Matt Turner]

Added in commits 36fd65381 and 337dad8ce even though the existing
include was in view.
---
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index c439da2..1e39b39 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -30,8 +30,6 @@
 #include "brw_fs_surface_builder.h"
 #include "brw_vec4_gs_visitor.h"
 #include "brw_nir.h"
-#include "brw_fs_surface_builder.h"
-#include "brw_vec4_gs_visitor.h"
 
 using namespace brw;
 using namespace brw::surface_access;
-- 
2.4.9

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[Mesa-dev] [PATCH 12/13] i965: Move brw_new_shader and brw_link_shader prototypes from brw_wm.h.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_shader.h | 3 +++
 src/mesa/drivers/dri/i965/brw_wm.h | 3 ---
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_shader.h 
b/src/mesa/drivers/dri/i965/brw_shader.h
index d78e552..5c226ec 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -286,6 +286,9 @@ bool brw_cs_precompile(struct gl_context *ctx,
struct gl_shader_program *shader_prog,
struct gl_program *prog);
 
+GLboolean brw_link_shader(struct gl_context *ctx, struct gl_shader_program 
*prog);
+struct gl_shader *brw_new_shader(struct gl_context *ctx, GLuint name, GLuint 
type);
+
 int type_size_scalar(const struct glsl_type *type);
 int type_size_vec4(const struct glsl_type *type);
 int type_size_vec4_times_4(const struct glsl_type *type);
diff --git a/src/mesa/drivers/dri/i965/brw_wm.h 
b/src/mesa/drivers/dri/i965/brw_wm.h
index 35dfa4c..579ac67 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -60,9 +60,6 @@
 extern "C" {
 #endif
 
-GLboolean brw_link_shader(struct gl_context *ctx, struct gl_shader_program 
*prog);
-struct gl_shader *brw_new_shader(struct gl_context *ctx, GLuint name, GLuint 
type);
-
 bool brw_color_buffer_write_enabled(struct brw_context *brw);
 bool brw_codegen_wm_prog(struct brw_context *brw,
  struct gl_shader_program *prog,
-- 
2.4.9

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[Mesa-dev] [PATCH 11/13] i965: Compile brw_cs_fill_local_id_payload() as C.

[Matt Turner]

It's only called from C, it compiles as C, so just compile it as C.

Notice the missing extern "C" on the definition of the function, which
would screw things up if the prototype wasn't parsed before the
definition.
---
 src/mesa/drivers/dri/i965/brw_cs.c   | 36 
 src/mesa/drivers/dri/i965/brw_fs.cpp | 36 
 2 files changed, 36 insertions(+), 36 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_cs.c 
b/src/mesa/drivers/dri/i965/brw_cs.c
index a34c320..9c92faa 100644
--- a/src/mesa/drivers/dri/i965/brw_cs.c
+++ b/src/mesa/drivers/dri/i965/brw_cs.c
@@ -33,6 +33,42 @@
 #include "brw_nir.h"
 #include "brw_program.h"
 
+void
+brw_cs_fill_local_id_payload(const struct brw_cs_prog_data *prog_data,
+ void *buffer, uint32_t threads, uint32_t stride)
+{
+   if (prog_data->local_invocation_id_regs == 0)
+  return;
+
+   /* 'stride' should be an integer number of registers, that is, a multiple
+* of 32 bytes.
+*/
+   assert(stride % 32 == 0);
+
+   unsigned x = 0, y = 0, z = 0;
+   for (unsigned t = 0; t < threads; t++) {
+  uint32_t *param = (uint32_t *) buffer + stride * t / 4;
+
+  for (unsigned i = 0; i < prog_data->simd_size; i++) {
+ param[0 * prog_data->simd_size + i] = x;
+ param[1 * prog_data->simd_size + i] = y;
+ param[2 * prog_data->simd_size + i] = z;
+
+ x++;
+ if (x == prog_data->local_size[0]) {
+x = 0;
+y++;
+if (y == prog_data->local_size[1]) {
+   y = 0;
+   z++;
+   if (z == prog_data->local_size[2])
+  z = 0;
+}
+ }
+  }
+   }
+}
+
 static void
 assign_cs_binding_table_offsets(const struct brw_device_info *devinfo,
 const struct gl_shader_program *shader_prog,
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 4acac7d..99b0998 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -5518,42 +5518,6 @@ brw_compile_fs(const struct brw_compiler *compiler, void 
*log_data,
return g.get_assembly(final_assembly_size);
 }
 
-void
-brw_cs_fill_local_id_payload(const struct brw_cs_prog_data *prog_data,
- void *buffer, uint32_t threads, uint32_t stride)
-{
-   if (prog_data->local_invocation_id_regs == 0)
-  return;
-
-   /* 'stride' should be an integer number of registers, that is, a multiple
-* of 32 bytes.
-*/
-   assert(stride % 32 == 0);
-
-   unsigned x = 0, y = 0, z = 0;
-   for (unsigned t = 0; t < threads; t++) {
-  uint32_t *param = (uint32_t *) buffer + stride * t / 4;
-
-  for (unsigned i = 0; i < prog_data->simd_size; i++) {
- param[0 * prog_data->simd_size + i] = x;
- param[1 * prog_data->simd_size + i] = y;
- param[2 * prog_data->simd_size + i] = z;
-
- x++;
- if (x == prog_data->local_size[0]) {
-x = 0;
-y++;
-if (y == prog_data->local_size[1]) {
-   y = 0;
-   z++;
-   if (z == prog_data->local_size[2])
-  z = 0;
-}
- }
-  }
-   }
-}
-
 fs_reg *
 fs_visitor::emit_cs_local_invocation_id_setup()
 {
-- 
2.4.9

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[Mesa-dev] [PATCH 09/13] i965: Drop #include of main/glheader.h.

[Matt Turner]

It's never used.
---
 src/mesa/drivers/dri/i965/brw_clear.c  | 1 -
 src/mesa/drivers/dri/i965/brw_clip.c   | 1 -
 src/mesa/drivers/dri/i965/brw_clip_line.c  | 1 -
 src/mesa/drivers/dri/i965/brw_clip_point.c | 1 -
 src/mesa/drivers/dri/i965/brw_clip_tri.c   | 1 -
 src/mesa/drivers/dri/i965/brw_clip_unfilled.c  | 1 -
 src/mesa/drivers/dri/i965/brw_clip_util.c  | 1 -
 src/mesa/drivers/dri/i965/brw_compute.c| 1 -
 src/mesa/drivers/dri/i965/brw_curbe.c  | 1 -
 src/mesa/drivers/dri/i965/brw_draw.c   | 1 -
 src/mesa/drivers/dri/i965/brw_draw_upload.c| 1 -
 src/mesa/drivers/dri/i965/brw_ff_gs.c  | 1 -
 src/mesa/drivers/dri/i965/brw_ff_gs_emit.c | 1 -
 src/mesa/drivers/dri/i965/brw_sf.c | 1 -
 src/mesa/drivers/dri/i965/brw_sf_emit.c| 1 -
 src/mesa/drivers/dri/i965/brw_tex.c| 1 -
 src/mesa/drivers/dri/i965/gen8_draw_upload.c   | 1 -
 src/mesa/drivers/dri/i965/intel_pixel_bitmap.c | 1 -
 src/mesa/drivers/dri/i965/intel_pixel_copy.c   | 1 -
 src/mesa/drivers/dri/i965/intel_pixel_draw.c   | 1 -
 src/mesa/drivers/dri/i965/intel_pixel_read.c   | 1 -
 src/mesa/drivers/dri/i965/intel_screen.c   | 1 -
 src/mesa/drivers/dri/i965/intel_state.c| 1 -
 src/mesa/drivers/dri/i965/intel_tex_image.c| 1 -
 24 files changed, 24 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
b/src/mesa/drivers/dri/i965/brw_clear.c
index b011955..841ba5d 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -24,7 +24,6 @@
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "main/glheader.h"
 #include "main/mtypes.h"
 #include "main/condrender.h"
 #include "swrast/swrast.h"
diff --git a/src/mesa/drivers/dri/i965/brw_clip.c 
b/src/mesa/drivers/dri/i965/brw_clip.c
index 2d5abc7..9db35ce 100644
--- a/src/mesa/drivers/dri/i965/brw_clip.c
+++ b/src/mesa/drivers/dri/i965/brw_clip.c
@@ -29,7 +29,6 @@
   *   Keith Whitwell 
   */
 
-#include "main/glheader.h"
 #include "main/macros.h"
 #include "main/enums.h"
 
diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c 
b/src/mesa/drivers/dri/i965/brw_clip_line.c
index 8e34f7c..d59e884 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_line.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_line.c
@@ -29,7 +29,6 @@
   *   Keith Whitwell 
   */
 
-#include "main/glheader.h"
 #include "main/macros.h"
 #include "main/enums.h"
 #include "program/program.h"
diff --git a/src/mesa/drivers/dri/i965/brw_clip_point.c 
b/src/mesa/drivers/dri/i965/brw_clip_point.c
index 81487d3..5cf2f5e 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_point.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_point.c
@@ -29,7 +29,6 @@
   *   Keith Whitwell 
   */
 
-#include "main/glheader.h"
 #include "main/macros.h"
 #include "main/enums.h"
 #include "program/program.h"
diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c 
b/src/mesa/drivers/dri/i965/brw_clip_tri.c
index cca7eb1..38ab007 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_tri.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c
@@ -29,7 +29,6 @@
   *   Keith Whitwell 
   */
 
-#include "main/glheader.h"
 #include "main/macros.h"
 #include "main/enums.h"
 #include "program/program.h"
diff --git a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c 
b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
index 9a4d2a9..214a346 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
@@ -29,7 +29,6 @@
   *   Keith Whitwell 
   */
 
-#include "main/glheader.h"
 #include "main/macros.h"
 #include "main/enums.h"
 #include "program/program.h"
diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c 
b/src/mesa/drivers/dri/i965/brw_clip_util.c
index 73ba85e..713d445 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_util.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_util.c
@@ -30,7 +30,6 @@
   */
 
 
-#include "main/glheader.h"
 #include "main/macros.h"
 #include "main/enums.h"
 #include "program/program.h"
diff --git a/src/mesa/drivers/dri/i965/brw_compute.c 
b/src/mesa/drivers/dri/i965/brw_compute.c
index fe991a4..d9f181a 100644
--- a/src/mesa/drivers/dri/i965/brw_compute.c
+++ b/src/mesa/drivers/dri/i965/brw_compute.c
@@ -24,7 +24,6 @@
 #include 
 
 #include "main/condrender.h"
-#include "main/glheader.h"
 #include "main/mtypes.h"
 #include "main/state.h"
 #include "brw_context.h"
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c 
b/src/mesa/drivers/dri/i965/brw_curbe.c
index a149ce3..b777bce 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -50,7 +50,6 @@
  */
 
 
-#include "main/glheader.h"
 #include "main/context.h"
 #include "main/macros.h"
 #include "main/enums.h"
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index bff484f..f250208 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ 

[Mesa-dev] [PATCH 01/13] util: Include assert.h in macros.h.

[Matt Turner]

---
 src/util/macros.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/util/macros.h b/src/util/macros.h
index 84e4f18..5014b91 100644
--- a/src/util/macros.h
+++ b/src/util/macros.h
@@ -24,6 +24,8 @@
 #ifndef UTIL_MACROS_H
 #define UTIL_MACROS_H
 
+#include 
+
 /* Compute the size of an array */
 #ifndef ARRAY_SIZE
 #  define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))
-- 
2.4.9

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[Mesa-dev] [PATCH 10/13] i965: Move MRF macros from brw_inst.h to brw_eu.h.

[Matt Turner]

brw_inst.h is only for the brw_inst/brw_compact_inst functions.
---
 src/mesa/drivers/dri/i965/brw_eu.h| 9 +
 src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 1 +
 src/mesa/drivers/dri/i965/brw_inst.h  | 9 -
 3 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_eu.h 
b/src/mesa/drivers/dri/i965/brw_eu.h
index 829e393..81d4ef9 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -543,6 +543,15 @@ is_3src(enum opcode opcode)
return opcode_descs[opcode].nsrc == 3;
 }
 
+/** Maximum SEND message length */
+#define BRW_MAX_MSG_LENGTH 15
+
+/** First MRF register used by pull loads */
+#define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
+
+/** First MRF register used by spills */
+#define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 1b61f9f..ef59c24 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -25,6 +25,7 @@
  *
  */
 
+#include "brw_eu.h"
 #include "brw_fs.h"
 #include "brw_cfg.h"
 #include "glsl/nir/glsl_types.h"
diff --git a/src/mesa/drivers/dri/i965/brw_inst.h 
b/src/mesa/drivers/dri/i965/brw_inst.h
index cd9f6ef..0e5f613 100644
--- a/src/mesa/drivers/dri/i965/brw_inst.h
+++ b/src/mesa/drivers/dri/i965/brw_inst.h
@@ -39,15 +39,6 @@
 extern "C" {
 #endif
 
-/** Maximum SEND message length */
-#define BRW_MAX_MSG_LENGTH 15
-
-/** First MRF register used by pull loads */
-#define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
-
-/** First MRF register used by spills */
-#define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)
-
 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
 typedef struct brw_inst {
uint64_t data[2];
-- 
2.4.9

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[Mesa-dev] [PATCH 03/13] i965: Mark count_trailing_one_bits() static.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index ba11d3d..cb3c6f7 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1344,7 +1344,7 @@ brw_blorp_blit_program::single_to_blend()
  * count_trailing_one_bits(7) == 3
  * count_trailing_one_bits(11) == 2
  */
-inline int count_trailing_one_bits(unsigned value)
+static inline int count_trailing_one_bits(unsigned value)
 {
 #ifdef HAVE___BUILTIN_CTZ
return __builtin_ctz(~value);
-- 
2.4.9

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Re: [Mesa-dev] [PATCH 09/13] i965: Drop #include of main/glheader.h.

[Ian Romanick]

Have you built this series with debug and release builds?  There have
been cases in the past where removing or changing headers worked fine in
one but not the other.

On 11/23/2015 01:55 PM, Matt Turner wrote:
> It's never used.
> ---
>  src/mesa/drivers/dri/i965/brw_clear.c  | 1 -
>  src/mesa/drivers/dri/i965/brw_clip.c   | 1 -
>  src/mesa/drivers/dri/i965/brw_clip_line.c  | 1 -
>  src/mesa/drivers/dri/i965/brw_clip_point.c | 1 -
>  src/mesa/drivers/dri/i965/brw_clip_tri.c   | 1 -
>  src/mesa/drivers/dri/i965/brw_clip_unfilled.c  | 1 -
>  src/mesa/drivers/dri/i965/brw_clip_util.c  | 1 -
>  src/mesa/drivers/dri/i965/brw_compute.c| 1 -
>  src/mesa/drivers/dri/i965/brw_curbe.c  | 1 -
>  src/mesa/drivers/dri/i965/brw_draw.c   | 1 -
>  src/mesa/drivers/dri/i965/brw_draw_upload.c| 1 -
>  src/mesa/drivers/dri/i965/brw_ff_gs.c  | 1 -
>  src/mesa/drivers/dri/i965/brw_ff_gs_emit.c | 1 -
>  src/mesa/drivers/dri/i965/brw_sf.c | 1 -
>  src/mesa/drivers/dri/i965/brw_sf_emit.c| 1 -
>  src/mesa/drivers/dri/i965/brw_tex.c| 1 -
>  src/mesa/drivers/dri/i965/gen8_draw_upload.c   | 1 -
>  src/mesa/drivers/dri/i965/intel_pixel_bitmap.c | 1 -
>  src/mesa/drivers/dri/i965/intel_pixel_copy.c   | 1 -
>  src/mesa/drivers/dri/i965/intel_pixel_draw.c   | 1 -
>  src/mesa/drivers/dri/i965/intel_pixel_read.c   | 1 -
>  src/mesa/drivers/dri/i965/intel_screen.c   | 1 -
>  src/mesa/drivers/dri/i965/intel_state.c| 1 -
>  src/mesa/drivers/dri/i965/intel_tex_image.c| 1 -
>  24 files changed, 24 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
> b/src/mesa/drivers/dri/i965/brw_clear.c
> index b011955..841ba5d 100644
> --- a/src/mesa/drivers/dri/i965/brw_clear.c
> +++ b/src/mesa/drivers/dri/i965/brw_clear.c
> @@ -24,7 +24,6 @@
>   * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>   */
>  
> -#include "main/glheader.h"
>  #include "main/mtypes.h"
>  #include "main/condrender.h"
>  #include "swrast/swrast.h"
> diff --git a/src/mesa/drivers/dri/i965/brw_clip.c 
> b/src/mesa/drivers/dri/i965/brw_clip.c
> index 2d5abc7..9db35ce 100644
> --- a/src/mesa/drivers/dri/i965/brw_clip.c
> +++ b/src/mesa/drivers/dri/i965/brw_clip.c
> @@ -29,7 +29,6 @@
>*   Keith Whitwell 
>*/
>  
> -#include "main/glheader.h"
>  #include "main/macros.h"
>  #include "main/enums.h"
>  
> diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c 
> b/src/mesa/drivers/dri/i965/brw_clip_line.c
> index 8e34f7c..d59e884 100644
> --- a/src/mesa/drivers/dri/i965/brw_clip_line.c
> +++ b/src/mesa/drivers/dri/i965/brw_clip_line.c
> @@ -29,7 +29,6 @@
>*   Keith Whitwell 
>*/
>  
> -#include "main/glheader.h"
>  #include "main/macros.h"
>  #include "main/enums.h"
>  #include "program/program.h"
> diff --git a/src/mesa/drivers/dri/i965/brw_clip_point.c 
> b/src/mesa/drivers/dri/i965/brw_clip_point.c
> index 81487d3..5cf2f5e 100644
> --- a/src/mesa/drivers/dri/i965/brw_clip_point.c
> +++ b/src/mesa/drivers/dri/i965/brw_clip_point.c
> @@ -29,7 +29,6 @@
>*   Keith Whitwell 
>*/
>  
> -#include "main/glheader.h"
>  #include "main/macros.h"
>  #include "main/enums.h"
>  #include "program/program.h"
> diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c 
> b/src/mesa/drivers/dri/i965/brw_clip_tri.c
> index cca7eb1..38ab007 100644
> --- a/src/mesa/drivers/dri/i965/brw_clip_tri.c
> +++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c
> @@ -29,7 +29,6 @@
>*   Keith Whitwell 
>*/
>  
> -#include "main/glheader.h"
>  #include "main/macros.h"
>  #include "main/enums.h"
>  #include "program/program.h"
> diff --git a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c 
> b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
> index 9a4d2a9..214a346 100644
> --- a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
> +++ b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
> @@ -29,7 +29,6 @@
>*   Keith Whitwell 
>*/
>  
> -#include "main/glheader.h"
>  #include "main/macros.h"
>  #include "main/enums.h"
>  #include "program/program.h"
> diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c 
> b/src/mesa/drivers/dri/i965/brw_clip_util.c
> index 73ba85e..713d445 100644
> --- a/src/mesa/drivers/dri/i965/brw_clip_util.c
> +++ b/src/mesa/drivers/dri/i965/brw_clip_util.c
> @@ -30,7 +30,6 @@
>*/
>  
>  
> -#include "main/glheader.h"
>  #include "main/macros.h"
>  #include "main/enums.h"
>  #include "program/program.h"
> diff --git a/src/mesa/drivers/dri/i965/brw_compute.c 
> b/src/mesa/drivers/dri/i965/brw_compute.c
> index fe991a4..d9f181a 100644
> --- a/src/mesa/drivers/dri/i965/brw_compute.c
> +++ b/src/mesa/drivers/dri/i965/brw_compute.c
> @@ -24,7 +24,6 @@
>  #include 
>  
>  #include "main/condrender.h"
> -#include "main/glheader.h"
>  #include "main/mtypes.h"
>  #include "main/state.h"
>  #include "brw_context.h"
> diff --git 

Re: [Mesa-dev] [PATCH 3/7] i965/vec4: Use a stride of 1 and byte offsets for UBOs

[Matt Turner]

On Mon, Nov 23, 2015 at 6:11 PM, Jason Ekstrand  wrote:
> ---
>  src/mesa/drivers/dri/i965/brw_vec4_nir.cpp   | 16 +++-
>  src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp   | 13 +++--
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  5 +
>  3 files changed, 7 insertions(+), 27 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index 8453dc2..16d3a06 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -786,20 +786,10 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr 
> *instr)
>unsigned const_offset = instr->const_index[0];
>src_reg offset;
>
> -  if (devinfo->gen <= 6) {
> - if (!has_indirect)  {
> -offset = brw_imm_ud(const_offset & ~15);
> - } else {
> -offset = get_nir_src(instr->src[1], nir_type_int, 1);
> - }
> +  if (!has_indirect)  {
> + offset = brw_imm_ud(const_offset & ~15);
>} else {
> - if (!has_indirect)  {
> -offset = brw_imm_ud(const_offset / 16);
> - } else {
> -offset = src_reg(this, glsl_type::uint_type);
> -emit(SHR(dst_reg(offset), get_nir_src(instr->src[1], 
> nir_type_int, 1),
> - brw_imm_ud(4u)));
> - }
> + offset = get_nir_src(instr->src[1], nir_type_int, 1);
>}
>
>src_reg packed_consts = src_reg(this, glsl_type::vec4_type);
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> index 71ec9da..51e6227 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> @@ -1473,23 +1473,16 @@ vec4_visitor::get_pull_constant_offset(bblock_t * 
> block, vec4_instruction *inst,
>
>emit_before(block, inst, ADD(dst_reg(index), *reladdr,
> brw_imm_d(reg_offset)));
> -
> -  /* Pre-gen7, the message header uses byte offsets instead of vec4
> -   * (16-byte) offset units.
> -   */
> -  if (devinfo->gen < 7) {
> - emit_before(block, inst, MUL(dst_reg(index), index, brw_imm_d(16)));
> -  }
> +  emit_before(block, inst, MUL(dst_reg(index), index, brw_imm_d(16)));
>
>return index;
> } else if (devinfo->gen >= 8) {
>/* Store the offset in a GRF so we can send-from-GRF. */
>src_reg offset = src_reg(this, glsl_type::int_type);
> -  emit_before(block, inst, MOV(dst_reg(offset), brw_imm_d(reg_offset)));
> +  emit_before(block, inst, MOV(dst_reg(offset), brw_imm_d(reg_offset * 
> 16)));
>return offset;
> } else {
> -  int message_header_scale = devinfo->gen < 7 ? 16 : 1;
> -  return brw_imm_d(reg_offset * message_header_scale);
> +  return brw_imm_d(reg_offset * 16);
> }
>  }
>
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index 7cb7dd5..c016667 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -403,12 +403,9 @@ brw_create_constant_surface(struct brw_context *brw,
> uint32_t *out_offset,
>  bool dword_pitch)

dword_pitch looks like it's now dead? (Yay!)

>  {
> -   uint32_t stride = dword_pitch ? 1 : 16;
> -   uint32_t elements = ALIGN(size, stride) / stride;
> -
> brw->vtbl.emit_buffer_surface_state(brw, out_offset, bo, offset,
> BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
> -   elements, stride, false);
> +   size, 1, false);
>  }
>
>  /**
> --
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Re: [Mesa-dev] [PATCH 5/7] i965/nir: Add a nir_lower_uniforms helper

[Matt Turner]

On Mon, Nov 23, 2015 at 6:11 PM, Jason Ekstrand  wrote:
> This matches what we're already doing for inputs and outputs
> ---
>  src/mesa/drivers/dri/i965/brw_nir.c | 9 +
>  1 file changed, 9 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_nir.c 
> b/src/mesa/drivers/dri/i965/brw_nir.c
> index 91358d8..e602df7 100644
> --- a/src/mesa/drivers/dri/i965/brw_nir.c
> +++ b/src/mesa/drivers/dri/i965/brw_nir.c
> @@ -171,6 +171,14 @@ brw_nir_lower_outputs(nir_shader *nir, bool is_scalar)
> }
>  }
>
> +static void
> +brw_nir_lower_uniforms(nir_shader *nir, bool is_scalar)
> +{
> +   nir_assign_var_locations(>uniforms,
> +>num_uniforms,
> +is_scalar ? type_size_scalar : type_size_vec4);
> +}
> +
>  static bool
>  should_clone_nir()
>  {
> @@ -298,6 +306,7 @@ brw_lower_nir(nir_shader *nir,
>
> OPT_V(brw_nir_lower_inputs, devinfo, is_scalar);
> OPT_V(brw_nir_lower_outputs, is_scalar);
> +   OPT_V(brw_nir_lower_uniforms, is_scalar);
> nir_assign_var_locations(>uniforms,
>  >num_uniforms,
>  is_scalar ? type_size_scalar : type_size_vec4);

Did you mean to delete this?
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Re: [Mesa-dev] [PATCH 2/2] glsl: implement recent spec update to SSO validation

[Tapani Pälli]

Reviewed-by: Tapani Pälli 

On 11/24/2015 03:08 AM, Timothy Arceri wrote:

From: Timothy Arceri 

Enables 200+ dEQP SSO tests to proceed past validation,
and fixes a ES31-CTS.sepshaderobjs.PipelineApi subtest.

V2: split out change that reverts a previous patch into its own commit,
move variable declaration to top of function, and fix some formatting
all suggested by Ian.

Reviewed-by: Ian Romanick 
Cc: "11.1" 
---
  src/mesa/main/pipelineobj.c | 24 
  1 file changed, 24 insertions(+)

diff --git a/src/mesa/main/pipelineobj.c b/src/mesa/main/pipelineobj.c
index f079c50..0439129 100644
--- a/src/mesa/main/pipelineobj.c
+++ b/src/mesa/main/pipelineobj.c
@@ -761,6 +761,7 @@ _mesa_validate_program_pipeline(struct gl_context* ctx,
  GLboolean IsBound)
  {
 unsigned i;
+   bool program_empty = true;
  
 pipe->Validated = GL_FALSE;
  
@@ -857,6 +858,29 @@ _mesa_validate_program_pipeline(struct gl_context* ctx,

}
 }
  
+   /* Section 11.1.3.11 (Validation) of the OpenGL 4.5 spec says:

+*
+*"An INVALID_OPERATION error is generated by any command that trans-
+*fers vertices to the GL or launches compute work if the current set
+*of active program objects cannot be executed, for reasons including:
+*
+*   ...
+*
+*   - There is no current program object specified by UseProgram,
+* there is a current program pipeline object, and that object is
+* empty (no executable code is installed for any stage).
+*/
+   for (i = 0; i < MESA_SHADER_STAGES; i++) {
+  if (pipe->CurrentProgram[i]) {
+ program_empty = false;
+ break;
+  }
+   }
+
+   if (program_empty) {
+  goto err;
+   }
+
 /* Section 2.11.11 (Shader Execution), subheading "Validation," of the
  * OpenGL 4.1 spec says:
  *


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Re: [Mesa-dev] [PATCH] swrast: Fix the coordinates passed to _mesa_regions_overlap()

[Matt Turner]

On Mon, Nov 23, 2015 at 5:35 PM, Anuj Phogat  wrote:
> Cc: "11.1" 
> Signed-off-by: Anuj Phogat 
> ---
>  src/mesa/swrast/s_copypix.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/swrast/s_copypix.c b/src/mesa/swrast/s_copypix.c
> index 0dbccc0..31e1d3d 100644
> --- a/src/mesa/swrast/s_copypix.c
> +++ b/src/mesa/swrast/s_copypix.c
> @@ -53,8 +53,10 @@ regions_overlap(GLint srcx, GLint srcy,
>  GLfloat zoomX, GLfloat zoomY)
>  {
> if (zoomX == 1.0F && zoomY == 1.0F) {
> -  return _mesa_regions_overlap(srcx, srcy, srcx + width, srcy + height,
> -   dstx, dsty, dstx + width, dsty + height);
> +  return _mesa_regions_overlap(srcx, srcy,
> +   srcx + width - 1, srcy + height - 1,
> +   dstx, dsty,
> +   dstx + width - 1, dsty + height - 1);
> }

What problem is this fixing? Reading the implementation of
_mesa_regions_overlap(), it seems that the arguments are inclusive, so
subtracting 1 shouldn't be necessary (or correct).

The other two call sites (src/mesa/drivers/dri/i965/intel_blit.c and
src/mesa/state_tracker/st_cb_drawpixels.c) also don't seem to subtract
1.
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Re: [Mesa-dev] [PATCH 4/7] i965/nir: Remove unused indirect handling

[Matt Turner]

On Mon, Nov 23, 2015 at 6:11 PM, Jason Ekstrand  wrote:
> The one and only place where the FS backend allows reladdr is on uniforms.
> For locals, inputs, and outputs, we lower it away before the backend ever
> sees it.  This commit gets rid of the dead indirect handling code.
> ---
>  src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 44 
> 
>  1 file changed, 11 insertions(+), 33 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
> b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> index 062ae08..39111ba 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> @@ -1076,28 +1076,6 @@ fs_visitor::nir_emit_undef(const fs_builder , 
> nir_ssa_undef_instr *instr)
> instr->def.num_components);
>  }
>
> -static fs_reg
> -fs_reg_for_nir_reg(fs_visitor *v, nir_register *nir_reg,
> -   unsigned base_offset, nir_src *indirect)
> -{
> -   fs_reg reg;
> -
> -   assert(!nir_reg->is_global);
> -
> -   reg = v->nir_locals[nir_reg->index];
> -
> -   reg = offset(reg, v->bld, base_offset * nir_reg->num_components);
> -   if (indirect) {
> -  int multiplier = nir_reg->num_components * (v->dispatch_width / 8);
> -
> -  reg.reladdr = new(v->mem_ctx) fs_reg(v->vgrf(glsl_type::int_type));
> -  v->bld.MUL(*reg.reladdr, v->get_nir_src(*indirect),
> - brw_imm_d(multiplier));
> -   }
> -
> -   return reg;
> -}
> -
>  fs_reg
>  fs_visitor::get_nir_src(nir_src src)
>  {
> @@ -1105,8 +1083,10 @@ fs_visitor::get_nir_src(nir_src src)
> if (src.is_ssa) {
>reg = nir_ssa_values[src.ssa->index];
> } else {
> -  reg = fs_reg_for_nir_reg(this, src.reg.reg, src.reg.base_offset,
> -   src.reg.indirect);
> +  /* We don't handle indirects on locals */
> +  assert(src.reg.indirect == NULL);
> +  reg = offset(nir_locals[src.reg.reg->index], bld,
> +   src.reg.base_offset * src.reg.reg->num_components);
> }
>
> /* to avoid floating-point denorm flushing problems, set the type by
> @@ -1123,10 +1103,12 @@ fs_visitor::get_nir_dest(nir_dest dest)
>nir_ssa_values[dest.ssa.index] = bld.vgrf(BRW_REGISTER_TYPE_F,
>  dest.ssa.num_components);
>return nir_ssa_values[dest.ssa.index];
> +   } else {
> +  /* We don't handle indirects on locals */
> +  assert(dest.reg.indirect == NULL);
> +  return offset(nir_locals[dest.reg.reg->index], bld,
> +dest.reg.base_offset * dest.reg.reg->num_components);
> }
> -
> -   return fs_reg_for_nir_reg(this, dest.reg.reg, dest.reg.base_offset,
> - dest.reg.indirect);
>  }
>
>  fs_reg
> @@ -2422,7 +2404,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
> nir_intrinsic_instr *instr
> }
>
> case nir_intrinsic_load_input_indirect:
> -  has_indirect = true;
> +  assert(!"Not allowed");

unreachable

>/* fallthrough */
> case nir_intrinsic_load_input: {
>unsigned index = 0;
> @@ -2434,8 +2416,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
> nir_intrinsic_instr *instr
>  src = offset(retype(nir_inputs, dest.type), bld,
>   instr->const_index[0] + index);
>   }
> - if (has_indirect)
> -src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[0]));
>   index++;
>
>   bld.MOV(dest, src);
> @@ -2508,7 +2488,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
> nir_intrinsic_instr *instr
> }
>
> case nir_intrinsic_store_output_indirect:
> -  has_indirect = true;
> +  assert(!"Not allowed");

unreachable

>/* fallthrough */
> case nir_intrinsic_store_output: {
>fs_reg src = get_nir_src(instr->src[0]);
> @@ -2516,8 +2496,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
> nir_intrinsic_instr *instr
>for (unsigned j = 0; j < instr->num_components; j++) {
>   fs_reg new_dest = offset(retype(nir_outputs, src.type), bld,
>instr->const_index[0] + index);
> - if (has_indirect)
> -src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[1]));
>   index++;
>   bld.MOV(new_dest, src);
>   src = offset(src, bld, 1);
> --
> 2.5.0.400.gff86faf
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Re: [Mesa-dev] [PATCH 2/7] i965/fs: Use a stride of 1 and byte offsets for UBOs

[Matt Turner]

On Mon, Nov 23, 2015 at 6:11 PM, Jason Ekstrand  wrote:
> ---
>  src/mesa/drivers/dri/i965/brw_fs.cpp | 16 
>  src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 11 ---
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  2 +-
>  3 files changed, 13 insertions(+), 16 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index 777cee5..9e2b1fa2 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -187,7 +187,7 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder 
> ,
>  * the redundant ones.
>  */
> fs_reg vec4_offset = vgrf(glsl_type::int_type);
> -   bld.ADD(vec4_offset, varying_offset, brw_imm_ud(const_offset & ~3));
> +   bld.ADD(vec4_offset, varying_offset, brw_imm_ud(const_offset & ~0xf));
>
> int scale = 1;
> if (devinfo->gen == 4 && bld.dispatch_width() == 8) {
> @@ -219,7 +219,7 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder 
> ,
>   inst->mlen = 1 + bld.dispatch_width() / 8;
> }
>
> -   bld.MOV(dst, offset(vec4_result, bld, (const_offset & 3) * scale));
> +   bld.MOV(dst, offset(vec4_result, bld, ((const_offset & 0xf) / 4) * 
> scale));
>  }
>
>  /**
> @@ -1999,10 +1999,12 @@ fs_visitor::demote_pull_constants()
>
>   /* Generate a pull load into dst. */
>   if (inst->src[i].reladdr) {
> +fs_reg indirect = ibld.vgrf(BRW_REGISTER_TYPE_D);
> +ibld.MUL(indirect, *inst->src[i].reladdr, brw_imm_d(4));
>  VARYING_PULL_CONSTANT_LOAD(ibld, dst,
> brw_imm_ud(index),
> -   *inst->src[i].reladdr,
> -   pull_index);
> +   indirect,
> +   pull_index * 4);
>  inst->src[i].reladdr = NULL;
>  inst->src[i].stride = 1;
>   } else {
> @@ -3038,13 +3040,11 @@ fs_visitor::lower_uniform_pull_constant_loads()
>   continue;
>
>if (devinfo->gen >= 7) {
> - /* The offset arg before was a vec4-aligned byte offset.  We need to
> -  * turn it into a dword offset.
> -  */
> + /* The offset arg is a vec4-aligned immediate byte offset. */
>   fs_reg const_offset_reg = inst->src[1];
>   assert(const_offset_reg.file == IMM &&
>  const_offset_reg.type == BRW_REGISTER_TYPE_UD);
> - const_offset_reg.ud /= 4;
> + assert(const_offset_reg.ud % 16 == 0);
>
>   fs_reg payload, offset;
>   if (devinfo->gen >= 9) {
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
> b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> index c439da2..062ae08 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> @@ -2343,16 +2343,13 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
> nir_intrinsic_instr *instr
>}
>
>if (has_indirect) {
> - /* Turn the byte offset into a dword offset. */
> - fs_reg base_offset = vgrf(glsl_type::int_type);
> - bld.SHR(base_offset, retype(get_nir_src(instr->src[1]),
> - BRW_REGISTER_TYPE_D),
> - brw_imm_d(2));
> + fs_reg base_offset = retype(get_nir_src(instr->src[1]),
> + BRW_REGISTER_TYPE_D);
>
> - unsigned vec4_offset = instr->const_index[0] / 4;
> + unsigned vec4_offset = instr->const_index[0];
>   for (int i = 0; i < instr->num_components; i++)
>  VARYING_PULL_CONSTANT_LOAD(bld, offset(dest, bld, i), surf_index,
> -   base_offset, vec4_offset + i);
> +   base_offset, vec4_offset + i * 4);
>} else {
>   fs_reg packed_consts = vgrf(glsl_type::float_type);
>   packed_consts.type = dest.type;
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index f88f8d5..7cb7dd5 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -403,7 +403,7 @@ brw_create_constant_surface(struct brw_context *brw,
> uint32_t *out_offset,
>  bool dword_pitch)
>  {
> -   uint32_t stride = dword_pitch ? 4 : 16;
> +   uint32_t stride = dword_pitch ? 1 : 16;

I've thought dword_pitch was a bad name for a long time, but this
really seals it.

> uint32_t elements = ALIGN(size, stride) / stride;
>
> brw->vtbl.emit_buffer_surface_state(brw, out_offset, bo, offset,
> --
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Re: [Mesa-dev] [PATCH 1/2] Revert "mesa: return initial value for VALIDATE_STATUS if pipe not bound"

[Tapani Pälli]

Reviewed-by: Tapani Pälli 

On 11/24/2015 03:08 AM, Timothy Arceri wrote:

From: Timothy Arceri 

This reverts commit ba02f7a3b6a0e4314753a8e5080db61241563f9c.

The commit checked whether the pipeline was currently bound instead
of checking whether it had ever been bound.  The previous setting
of Validated during object creation makes this unnecessary.  The
real problem was that Validated was not properly set to false
elsewhere in the code.  This is fixed by a later patch.

Reviewed-by: Ian Romanick 
Cc: Tapani Pälli 
Cc: "11.1" 
---
  src/mesa/main/pipelineobj.c | 3 +--
  1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mesa/main/pipelineobj.c b/src/mesa/main/pipelineobj.c
index 90dff13..f079c50 100644
--- a/src/mesa/main/pipelineobj.c
+++ b/src/mesa/main/pipelineobj.c
@@ -645,8 +645,7 @@ _mesa_GetProgramPipelineiv(GLuint pipeline, GLenum pname, 
GLint *params)
*params = pipe->InfoLog ? strlen(pipe->InfoLog) + 1 : 0;
return;
 case GL_VALIDATE_STATUS:
-  /* If pipeline is not bound, return initial value 0. */
-  *params = (ctx->_Shader->Name != pipe->Name) ? 0 : pipe->Validated;
+  *params = pipe->Validated;
return;
 case GL_VERTEX_SHADER:
*params = pipe->CurrentProgram[MESA_SHADER_VERTEX]


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Re: [Mesa-dev] [PATCH 1/2] targets/nine: remove vc4 target

[Eric Anholt]

Emil Velikov  writes:

> On 23 November 2015 at 18:36, Emil Velikov  wrote:
>> Any nir powered targets outside of DRI have been broken for a little
>> while now (due to unresolved symbols).
> PEBKAC things link fine.

Either way, I'm happy to simplify things.  I have a hard time imagining
any use for nine+vc4.

Reviewed-by: Eric Anholt 


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Re: [Mesa-dev] [PATCH 5/7] i965/nir: Add a nir_lower_uniforms helper

[Jason Ekstrand]

On Nov 23, 2015 20:50, "Matt Turner"  wrote:
>
> On Mon, Nov 23, 2015 at 6:11 PM, Jason Ekstrand 
wrote:
> > This matches what we're already doing for inputs and outputs
> > ---
> >  src/mesa/drivers/dri/i965/brw_nir.c | 9 +
> >  1 file changed, 9 insertions(+)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_nir.c
b/src/mesa/drivers/dri/i965/brw_nir.c
> > index 91358d8..e602df7 100644
> > --- a/src/mesa/drivers/dri/i965/brw_nir.c
> > +++ b/src/mesa/drivers/dri/i965/brw_nir.c
> > @@ -171,6 +171,14 @@ brw_nir_lower_outputs(nir_shader *nir, bool
is_scalar)
> > }
> >  }
> >
> > +static void
> > +brw_nir_lower_uniforms(nir_shader *nir, bool is_scalar)
> > +{
> > +   nir_assign_var_locations(>uniforms,
> > +>num_uniforms,
> > +is_scalar ? type_size_scalar :
type_size_vec4);
> > +}
> > +
> >  static bool
> >  should_clone_nir()
> >  {
> > @@ -298,6 +306,7 @@ brw_lower_nir(nir_shader *nir,
> >
> > OPT_V(brw_nir_lower_inputs, devinfo, is_scalar);
> > OPT_V(brw_nir_lower_outputs, is_scalar);
> > +   OPT_V(brw_nir_lower_uniforms, is_scalar);
> > nir_assign_var_locations(>uniforms,
> >  >num_uniforms,
> >  is_scalar ? type_size_scalar :
type_size_vec4);
>
> Did you mean to delete this?

Yes, yes I did. I'll get that fixed.
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Re: [Mesa-dev] [PATCH 4/7] i965/nir: Remove unused indirect handling

[Jason Ekstrand]

On Nov 23, 2015 20:51, "Matt Turner"  wrote:
>
> On Mon, Nov 23, 2015 at 6:11 PM, Jason Ekstrand 
wrote:
> > The one and only place where the FS backend allows reladdr is on
uniforms.
> > For locals, inputs, and outputs, we lower it away before the backend
ever
> > sees it.  This commit gets rid of the dead indirect handling code.
> > ---
> >  src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 44

> >  1 file changed, 11 insertions(+), 33 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> > index 062ae08..39111ba 100644
> > --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> > +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> > @@ -1076,28 +1076,6 @@ fs_visitor::nir_emit_undef(const fs_builder
, nir_ssa_undef_instr *instr)
> >
 instr->def.num_components);
> >  }
> >
> > -static fs_reg
> > -fs_reg_for_nir_reg(fs_visitor *v, nir_register *nir_reg,
> > -   unsigned base_offset, nir_src *indirect)
> > -{
> > -   fs_reg reg;
> > -
> > -   assert(!nir_reg->is_global);
> > -
> > -   reg = v->nir_locals[nir_reg->index];
> > -
> > -   reg = offset(reg, v->bld, base_offset * nir_reg->num_components);
> > -   if (indirect) {
> > -  int multiplier = nir_reg->num_components * (v->dispatch_width /
8);
> > -
> > -  reg.reladdr = new(v->mem_ctx)
fs_reg(v->vgrf(glsl_type::int_type));
> > -  v->bld.MUL(*reg.reladdr, v->get_nir_src(*indirect),
> > - brw_imm_d(multiplier));
> > -   }
> > -
> > -   return reg;
> > -}
> > -
> >  fs_reg
> >  fs_visitor::get_nir_src(nir_src src)
> >  {
> > @@ -1105,8 +1083,10 @@ fs_visitor::get_nir_src(nir_src src)
> > if (src.is_ssa) {
> >reg = nir_ssa_values[src.ssa->index];
> > } else {
> > -  reg = fs_reg_for_nir_reg(this, src.reg.reg, src.reg.base_offset,
> > -   src.reg.indirect);
> > +  /* We don't handle indirects on locals */
> > +  assert(src.reg.indirect == NULL);
> > +  reg = offset(nir_locals[src.reg.reg->index], bld,
> > +   src.reg.base_offset * src.reg.reg->num_components);
> > }
> >
> > /* to avoid floating-point denorm flushing problems, set the type by
> > @@ -1123,10 +1103,12 @@ fs_visitor::get_nir_dest(nir_dest dest)
> >nir_ssa_values[dest.ssa.index] = bld.vgrf(BRW_REGISTER_TYPE_F,
> >
dest.ssa.num_components);
> >return nir_ssa_values[dest.ssa.index];
> > +   } else {
> > +  /* We don't handle indirects on locals */
> > +  assert(dest.reg.indirect == NULL);
> > +  return offset(nir_locals[dest.reg.reg->index], bld,
> > +dest.reg.base_offset *
dest.reg.reg->num_components);
> > }
> > -
> > -   return fs_reg_for_nir_reg(this, dest.reg.reg, dest.reg.base_offset,
> > - dest.reg.indirect);
> >  }
> >
> >  fs_reg
> > @@ -2422,7 +2404,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder
, nir_intrinsic_instr *instr
> > }
> >
> > case nir_intrinsic_load_input_indirect:
> > -  has_indirect = true;
> > +  assert(!"Not allowed");
>
> unreachable
>
> >/* fallthrough */
> > case nir_intrinsic_load_input: {
> >unsigned index = 0;
> > @@ -2434,8 +2416,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder
, nir_intrinsic_instr *instr
> >  src = offset(retype(nir_inputs, dest.type), bld,
> >   instr->const_index[0] + index);
> >   }
> > - if (has_indirect)
> > -src.reladdr = new(mem_ctx)
fs_reg(get_nir_src(instr->src[0]));
> >   index++;
> >
> >   bld.MOV(dest, src);
> > @@ -2508,7 +2488,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder
, nir_intrinsic_instr *instr
> > }
> >
> > case nir_intrinsic_store_output_indirect:
> > -  has_indirect = true;
> > +  assert(!"Not allowed");
>
> unreachable

Sure.

> >/* fallthrough */
> > case nir_intrinsic_store_output: {
> >fs_reg src = get_nir_src(instr->src[0]);
> > @@ -2516,8 +2496,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder
, nir_intrinsic_instr *instr
> >for (unsigned j = 0; j < instr->num_components; j++) {
> >   fs_reg new_dest = offset(retype(nir_outputs, src.type), bld,
> >instr->const_index[0] + index);
> > - if (has_indirect)
> > -src.reladdr = new(mem_ctx)
fs_reg(get_nir_src(instr->src[1]));
> >   index++;
> >   bld.MOV(new_dest, src);
> >   src = offset(src, bld, 1);
> > --
> > 2.5.0.400.gff86faf
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Re: [Mesa-dev] Mesa (master): gallium/util: remove the fake format helpers for bptc and etc2

[Michel Dänzer]

On 24.11.2015 01:21, Ilia Mirkin wrote:
> Module: Mesa
> Branch: master
> Commit: 1c7d0a6aa4f5cb38af7e281e1e5437cd1a20f781
> URL:
> http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c7d0a6aa4f5cb38af7e281e1e5437cd1a20f781
> 
> Author: Ilia Mirkin 
> Date:   Sat Nov 21 10:44:00 2015 -0500
> 
> gallium/util: remove the fake format helpers for bptc and etc2
> 
> This was a silly hack that kept growing and growing. Instead, just write
> NULLs for those functions. No need to have helpers that just assert(0)
> when you call them.
> 
> Signed-off-by: Ilia Mirkin 
> Reviewed-by: Marek Olšák 
> Reviewed-by: Roland Scheidegger 

This change broke make check, specifically llvmpipe's lp_test_format:


lp_test_format: 
../../../../src/gallium/auxiliary/gallivm/lp_bld_format_aos.c:732: 
lp_build_fetch_rgba_aos: Assertion `0' failed.

Program received signal SIGABRT, Aborted.
0x7460f107 in __GI_raise (sig=sig@entry=6) at 
../nptl/sysdeps/unix/sysv/linux/raise.c:56
56  ../nptl/sysdeps/unix/sysv/linux/raise.c: No such file or directory.
(gdb) bt
#0  0x7460f107 in __GI_raise (sig=sig@entry=6) at 
../nptl/sysdeps/unix/sysv/linux/raise.c:56
#1  0x746104e8 in __GI_abort () at abort.c:89
#2  0x74608226 in __assert_fail_base (fmt=0x7473ed08 "%s%s%s:%u: 
%s%sAssertion `%s' failed.\n%n", assertion=assertion@entry=0x5703cb "0", 
file=file@entry=0x573748 
"../../../../src/gallium/auxiliary/gallivm/lp_bld_format_aos.c", 
line=line@entry=732, 
function=function@entry=0x5739f0 <__PRETTY_FUNCTION__.10335> 
"lp_build_fetch_rgba_aos") at assert.c:92
#3  0x746082d2 in __GI___assert_fail 
(assertion=assertion@entry=0x5703cb "0", file=file@entry=0x573748 
"../../../../src/gallium/auxiliary/gallivm/lp_bld_format_aos.c", 
line=line@entry=732, 
function=0x5739f0 <__PRETTY_FUNCTION__.10335> "lp_build_fetch_rgba_aos") at 
assert.c:101
#4  0x004dcd20 in lp_build_fetch_rgba_aos 
(gallivm=gallivm@entry=0x80ae40, format_desc=format_desc@entry=0x79b500 
, type=..., type@entry=..., 
aligned=aligned@entry=1 '\001', base_ptr=base_ptr@entry=0x83d430, 
offset=offset@entry=0x818330, i=0x833050, j=0x8326c0, cache=0x821790) at 
../../../../src/gallium/auxiliary/gallivm/lp_bld_format_aos.c:732
#5  0x00405d3e in add_fetch_rgba_test (gallivm=gallivm@entry=0x80ae40, 
desc=desc@entry=0x79b500 , type=..., 
verbose=0) at ../../../../../src/gallium/drivers/llvmpipe/lp_test_format.c:124
#6  0x00405eaf in test_format_float (verbose=0, desc=0x79b500 
, fp=0x0) at 
../../../../../src/gallium/drivers/llvmpipe/lp_test_format.c:153
#7  test_one (verbose=0, format_desc=0x79b500 
, fp=0x0) at 
../../../../../src/gallium/drivers/llvmpipe/lp_test_format.c:336
#8  test_all (verbose=verbose@entry=0, fp=fp@entry=0x0) at 
../../../../../src/gallium/drivers/llvmpipe/lp_test_format.c:385
#9  0x00406c8a in test_some (verbose=verbose@entry=0, fp=fp@entry=0x0, 
n=n@entry=1000) at 
../../../../../src/gallium/drivers/llvmpipe/lp_test_format.c:401
#10 0x00405a33 in main (argc=1, argv=0x7fffe708) at 
../../../../../src/gallium/drivers/llvmpipe/lp_test_main.c:410
(gdb) bt full
#0  0x7460f107 in __GI_raise (sig=sig@entry=6) at 
../nptl/sysdeps/unix/sysv/linux/raise.c:56
resultvar = 0
pid = 22140
selftid = 22140
#1  0x746104e8 in __GI_abort () at abort.c:89
save_stage = 2
act = {__sigaction_handler = {sa_handler = 0x7fffea42, sa_sigaction 
= 0x7fffea42}, sa_mask = {__val = {140737294610881, 5715784, 732, 4, 
140737488347168, 128849010864, 140737322476013, 4294967296, 0, 0, 0, 
21474836480, 140737294610407, 
  140737488347320, 140737354092544, 140737294626056}}, sa_flags = 
5702603, sa_restorer = 0x5739f0 <__PRETTY_FUNCTION__.10335>}
sigs = {__val = {32, 0 }}
#2  0x74608226 in __assert_fail_base (fmt=0x7473ed08 "%s%s%s:%u: 
%s%sAssertion `%s' failed.\n%n", assertion=assertion@entry=0x5703cb "0", 
file=file@entry=0x573748 
"../../../../src/gallium/auxiliary/gallivm/lp_bld_format_aos.c", 
line=line@entry=732, 
function=function@entry=0x5739f0 <__PRETTY_FUNCTION__.10335> 
"lp_build_fetch_rgba_aos") at assert.c:92
str = 0x868eb0 "\260\065\213"
total = 4096
#3  0x746082d2 in __GI___assert_fail 
(assertion=assertion@entry=0x5703cb "0", file=file@entry=0x573748 
"../../../../src/gallium/auxiliary/gallivm/lp_bld_format_aos.c", 
line=line@entry=732, 
function=0x5739f0 <__PRETTY_FUNCTION__.10335> "lp_build_fetch_rgba_aos") at 
assert.c:101
No locals.
#4  0x004dcd20 in lp_build_fetch_rgba_aos 
(gallivm=gallivm@entry=0x80ae40, format_desc=format_desc@entry=0x79b500 
, type=..., type@entry=..., 
aligned=aligned@entry=1 '\001', base_ptr=base_ptr@entry=0x83d430, 
offset=offset@entry=0x818330, i=0x833050, j=0x8326c0, cache=0x821790) at 

Re: [Mesa-dev] [PATCH v2 07/42] i965: Implement programming of the L3 configuration.

[Jordan Justen]

On 2015-11-17 21:54:39, Jordan Justen wrote:
> From: Francisco Jerez 
> 
> ---
>  src/mesa/drivers/dri/i965/gen7_l3_state.c | 95 
> +++
>  1 file changed, 95 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c 
> b/src/mesa/drivers/dri/i965/gen7_l3_state.c
> index 8f9ba5b..48bca29 100644
> --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
> @@ -161,3 +161,98 @@ get_l3_way_size(const struct brw_device_info *devinfo)
> else
>return 2 << devinfo->gt;
>  }
> +
> +/**
> + * Program the hardware to use the specified L3 configuration.
> + */
> +static void
> +setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg)
> +{
> +   const bool has_dc = cfg->n[L3P_DC] || cfg->n[L3P_ALL];
> +   const bool has_is = cfg->n[L3P_IS] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
> +   const bool has_c = cfg->n[L3P_C] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
> +   const bool has_t = cfg->n[L3P_T] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
> +   const bool has_slm = cfg->n[L3P_SLM];
> +
> +   /* According to the hardware docs, the L3 partitioning can only be changed
> +* while the pipeline is completely drained and the caches are flushed,
> +* what involves a first PIPE_CONTROL flush which stalls the pipeline and
> +* initiates invalidation of the relevant caches...
> +*/
> +   brw_emit_pipe_control_flush(brw,
> +   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
> +   PIPE_CONTROL_CONST_CACHE_INVALIDATE |
> +   PIPE_CONTROL_INSTRUCTION_INVALIDATE |
> +   PIPE_CONTROL_DATA_CACHE_INVALIDATE |
> +   PIPE_CONTROL_NO_WRITE |
> +   PIPE_CONTROL_CS_STALL);
> +
> +   /* ...followed by a second stalling flush which guarantees that
> +* invalidation is complete when the L3 configuration registers are
> +* modified.
> +*/
> +   brw_emit_pipe_control_flush(brw,
> +   PIPE_CONTROL_DATA_CACHE_INVALIDATE |
> +   PIPE_CONTROL_NO_WRITE |
> +   PIPE_CONTROL_CS_STALL);

On Ivy Bridge, these two pipe control calls are causing the simulator
to complain. The message seems to indicate that, essentially the
gen8_add_cs_stall_workaround_bits workaround is not being applied.

Looking at the IVB PRM, vol 2, part 1, "1.10.4.1 PIPE_CONTROL" under
bit20 for "CS Stall" is does seem to indicate that CS Stall also
requires 1 of several other bits to be added.

For example, adding PIPE_CONTROL_STALL_AT_SCOREBOARD to this call, and
the one below makes the simulator happy. But, perhaps
gen8_add_cs_stall_workaround_bits should be applied to SNB - HSW as
well?

-Jordan

> +
> +   if (brw->gen >= 8) {
> +  assert(!cfg->n[L3P_IS] && !cfg->n[L3P_C] && !cfg->n[L3P_T]);
> +
> +  BEGIN_BATCH(3);
> +  OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
> +
> +  /* Set up the L3 partitioning. */
> +  OUT_BATCH(GEN8_L3CNTLREG);
> +  OUT_BATCH((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
> +SET_FIELD(cfg->n[L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
> +SET_FIELD(cfg->n[L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
> +SET_FIELD(cfg->n[L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
> +SET_FIELD(cfg->n[L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
> +
> +  ADVANCE_BATCH();
> +
> +   } else {
> +  assert(!cfg->n[L3P_ALL]);
> +
> +  /* When enabled SLM only uses a portion of the L3 on half of the banks,
> +   * the matching space on the remaining banks has to be allocated to a
> +   * client (URB for all validated configurations) set to the
> +   * lower-bandwidth 2-bank address hashing mode.
> +   */
> +  const bool urb_low_bw = has_slm && !brw->is_baytrail;
> +  assert(!urb_low_bw || cfg->n[L3P_URB] == cfg->n[L3P_SLM]);
> +
> +  /* Minimum number of ways that can be allocated to the URB. */
> +  const unsigned n0_urb = (brw->is_baytrail ? 32 : 0);
> +  assert(cfg->n[L3P_URB] >= n0_urb);
> +
> +  BEGIN_BATCH(7);
> +  OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2));
> +
> +  /* Demote any clients with no ways assigned to LLC. */
> +  OUT_BATCH(GEN7_L3SQCREG1);
> +  OUT_BATCH((brw->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
> + brw->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
> + IVB_L3SQCREG1_SQGHPCI_DEFAULT) |
> +(has_dc ? 0 : GEN7_L3SQCREG1_CONV_DC_UC) |
> +(has_is ? 0 : GEN7_L3SQCREG1_CONV_IS_UC) |
> +(has_c ? 0 : GEN7_L3SQCREG1_CONV_C_UC) |
> +(has_t ? 0 : GEN7_L3SQCREG1_CONV_T_UC));
> +
> +  /* Set up the L3 partitioning. */
> +  OUT_BATCH(GEN7_L3CNTLREG2);
> +  OUT_BATCH((has_slm ? GEN7_L3CNTLREG2_SLM_ENABLE : 0) |
> +SET_FIELD(cfg->n[L3P_URB] - 

Re: [Mesa-dev] [PATCH 1/2] r600: define registers required for tessellation

[Glenn Kennard]

On Mon, 23 Nov 2015 23:46:24 +0100, Dave Airlie  wrote:


From: Dave Airlie 

This adds the defines for a bunch of registers and shader
values that are required to implement tessellation.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/evergreend.h | 123 +++---
 src/gallium/drivers/r600/r600_sq.h|   8 +++
 2 files changed, 108 insertions(+), 23 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreend.h 
b/src/gallium/drivers/r600/evergreend.h
index 25237c6..dbee9d5 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -463,6 +463,39 @@
 #define R_0286EC_SPI_COMPUTE_NUM_THREAD_X0x0286EC
 #define R_0286F0_SPI_COMPUTE_NUM_THREAD_Y0x0286F0
 #define R_0286F4_SPI_COMPUTE_NUM_THREAD_Z0x0286F4
+#define R_028B6C_VGT_TF_PARAM0x028B6C
+#define   S_028B6C_TYPE(x)(((x) & 0x03) 
<< 0)
+#define   G_028B6C_TYPE(x)(((x) >> 0) 
& 0x03)
+#define   C_028B6C_TYPE   
0xFFFC
+#define V_028B6C_TESS_ISOLINE   0x00
+#define V_028B6C_TESS_TRIANGLE  0x01
+#define V_028B6C_TESS_QUAD  0x02
+#define   S_028B6C_PARTITIONING(x)(((x) & 0x07) 
<< 2)
+#define   G_028B6C_PARTITIONING(x)(((x) >> 2) 
& 0x07)
+#define   C_028B6C_PARTITIONING   
0xFFE3
+#define V_028B6C_PART_INTEGER   0x00
+#define V_028B6C_PART_POW2  0x01
+#define V_028B6C_PART_FRAC_ODD  0x02
+#define V_028B6C_PART_FRAC_EVEN 0x03
+#define   S_028B6C_TOPOLOGY(x)(((x) & 0x07) 
<< 5)
+#define   G_028B6C_TOPOLOGY(x)(((x) >> 5) 
& 0x07)
+#define   C_028B6C_TOPOLOGY   
0xFF1F
+#define V_028B6C_OUTPUT_POINT   0x00
+#define V_028B6C_OUTPUT_LINE0x01
+#define V_028B6C_OUTPUT_TRIANGLE_CW 0x02
+#define V_028B6C_OUTPUT_TRIANGLE_CCW0x03
+#define   S_028B6C_RESERVED_REDUC_AXIS(x) (((x) & 0x1) 
<< 8)
+#define   G_028B6C_RESERVED_REDUC_AXIS(x) (((x) >> 8) 
& 0x1)
+#define   C_028B6C_RESERVED_REDUC_AXIS
0xFEFF
+#define   S_028B6C_BUFFER_ACCESS_MODE(x)  (((x) & 0x1) 
<< 9)
+#define   G_028B6C_BUFFER_ACCESS_MODE(x)  (((x) >> 9) 
& 0x1)
+#define   C_028B6C_BUFFER_ACCESS_MODE 
0xFDFF
+#define V_028B6C_PATCH_MAJOR0x00
+#define V_028B6C_TF_MAJOR   0x01
+#define   S_028B6C_NUM_DS_WAVES_PER_SIMD  (((x) & 0xf) 
<< 10)
+#define   G_028B6C_NUM_DS_WAVES_PER_SIMD  (((x) >> 10) 
& 0xF)
+#define   C_028B6C_NUM_DS_WAVES_PER_SIMD  
0xC3FF
+
 #define R_028B74_VGT_DISPATCH_INITIATOR  0x028B74
#define R_028800_DB_DEPTH_CONTROL0x028800
@@ -1260,6 +1293,16 @@
 #define R_00A430_TD_GS_SAMPLER0_BORDER_GREEN 0x00A430
 #define R_00A434_TD_GS_SAMPLER0_BORDER_BLUE  0x00A434
 #define R_00A438_TD_GS_SAMPLER0_BORDER_ALPHA 0x00A438
+#define R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX   0x00A43C
+#define R_00A440_TD_HS_SAMPLER0_BORDER_COLOR_RED 0x00A440
+#define R_00A444_TD_HS_SAMPLER0_BORDER_COLOR_GREEN   0x00A444
+#define R_00A448_TD_HS_SAMPLER0_BORDER_COLOR_BLUE0x00A448
+#define R_00A44C_TD_HS_SAMPLER0_BORDER_COLOR_ALPHA   0x00A44C
+#define R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX   0x00A450
+#define R_00A454_TD_LS_SAMPLER0_BORDER_COLOR_RED 0x00A454
+#define R_00A458_TD_LS_SAMPLER0_BORDER_COLOR_GREEN   0x00A458
+#define R_00A45C_TD_LS_SAMPLER0_BORDER_COLOR_BLUE0x00A45C
+#define R_00A460_TD_LS_SAMPLER0_BORDER_COLOR_ALPHA   0x00A460
 #define R_00A464_TD_CS_SAMPLER0_BORDER_INDEX 0x00A464
 #define R_00A468_TD_CS_SAMPLER0_BORDER_RED   0x00A468
 #define R_00A46C_TD_CS_SAMPLER0_BORDER_GREEN 0x00A46C
@@ -1383,7 +1426,7 @@
 #define V_008958_DI_PT_TRISTRIP0x0006
 #define V_008958_DI_PT_UNUSED_00x0007
 #define V_008958_DI_PT_UNUSED_10x0008
-#define V_008958_DI_PT_UNUSED_20x0009
+#define V_008958_DI_PT_PATCH   

[Mesa-dev] [PATCH 1/2] Revert "mesa: return initial value for VALIDATE_STATUS if pipe not bound"

[Timothy Arceri]

From: Timothy Arceri 

This reverts commit ba02f7a3b6a0e4314753a8e5080db61241563f9c.

The commit checked whether the pipeline was currently bound instead
of checking whether it had ever been bound.  The previous setting
of Validated during object creation makes this unnecessary.  The
real problem was that Validated was not properly set to false
elsewhere in the code.  This is fixed by a later patch.

Reviewed-by: Ian Romanick 
Cc: Tapani Pälli 
Cc: "11.1" 
---
 src/mesa/main/pipelineobj.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mesa/main/pipelineobj.c b/src/mesa/main/pipelineobj.c
index 90dff13..f079c50 100644
--- a/src/mesa/main/pipelineobj.c
+++ b/src/mesa/main/pipelineobj.c
@@ -645,8 +645,7 @@ _mesa_GetProgramPipelineiv(GLuint pipeline, GLenum pname, 
GLint *params)
   *params = pipe->InfoLog ? strlen(pipe->InfoLog) + 1 : 0;
   return;
case GL_VALIDATE_STATUS:
-  /* If pipeline is not bound, return initial value 0. */
-  *params = (ctx->_Shader->Name != pipe->Name) ? 0 : pipe->Validated;
+  *params = pipe->Validated;
   return;
case GL_VERTEX_SHADER:
   *params = pipe->CurrentProgram[MESA_SHADER_VERTEX]
-- 
2.4.3

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Re: [Mesa-dev] [PATCH 2/2] r600: add missing register to initial state

[Glenn Kennard]

On Mon, 23 Nov 2015 23:46:25 +0100, Dave Airlie  wrote:


From: Dave Airlie 

We really should initialise HS/LS_2 and SQ_LDS_ALLOC exists
on all evergreen not just cayman, so we should initialise
it as well.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/evergreen_compute.c |  2 +-
 src/gallium/drivers/r600/evergreen_state.c   | 19 ++-
 src/gallium/drivers/r600/evergreend.h|  1 -
 3 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_compute.c  
b/src/gallium/drivers/r600/evergreen_compute.c

index 5743e3f..010d109 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -402,7 +402,7 @@ static void evergreen_emit_direct_dispatch(
assert(lds_size <= 8160);
}
-   radeon_compute_set_context_reg(cs, CM_R_0288E8_SQ_LDS_ALLOC,
+   radeon_compute_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC,
lds_size | (num_waves << 14));
/* Dispatch packet */
diff --git a/src/gallium/drivers/r600/evergreen_state.c  
b/src/gallium/drivers/r600/evergreen_state.c

index 684eee7..5333761 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2266,7 +2266,7 @@ static void cayman_init_atom_start_cs(struct  
r600_context *rctx)

struct r600_command_buffer *cb = >start_cs_cmd;
int tmp, i;
-   r600_init_command_buffer(cb, 320);
+   r600_init_command_buffer(cb, 326);
/* This must be first. */
r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
@@ -2324,8 +2324,8 @@ static void cayman_init_atom_start_cs(struct  
r600_context *rctx)
 	r600_store_value(cb, 0x76543210); /*  
CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
 	r600_store_value(cb, 0xfedcba98); /*  
CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */

-   r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
-   r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
+   r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
+   r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
@@ -2375,6 +2375,9 @@ static void cayman_init_atom_start_cs(struct  
r600_context *rctx)
 	r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS,  
S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
 	r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS,  
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
 	r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES,  
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
+	r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS,  
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
+	r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS,  
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));

+
r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
/* to avoid GPU doing any preloading of constant from random address */
@@ -2545,7 +2548,7 @@ void evergreen_init_atom_start_cs(struct  
r600_context *rctx)

return;
}
-   r600_init_command_buffer(cb, 320);
+   r600_init_command_buffer(cb, 330);
/* This must be first. */
r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
@@ -2817,6 +2820,8 @@ void evergreen_init_atom_start_cs(struct  
r600_context *rctx)
 	r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS,  
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
 	r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES,  
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));

r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
+	r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS,  
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
+	r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS,  
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));

/* to avoid GPU doing any preloading of constant from random address */
 	r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0,  
16);
@@ -2851,7 +2856,11 @@ void evergreen_init_atom_start_cs(struct  
r600_context *rctx)

r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
-   r600_store_context_reg(cb, R_0288EC_SQ_LDS_ALLOC_PS, 0);
+
+   r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
+   r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
+   r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
+
r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0);
eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
diff --git a/src/gallium/drivers/r600/evergreend.h  

[Mesa-dev] [PATCH 2/2] glsl: implement recent spec update to SSO validation

[Timothy Arceri]

From: Timothy Arceri 

Enables 200+ dEQP SSO tests to proceed past validation,
and fixes a ES31-CTS.sepshaderobjs.PipelineApi subtest.

V2: split out change that reverts a previous patch into its own commit,
move variable declaration to top of function, and fix some formatting
all suggested by Ian.

Reviewed-by: Ian Romanick 
Cc: "11.1" 
---
 src/mesa/main/pipelineobj.c | 24 
 1 file changed, 24 insertions(+)

diff --git a/src/mesa/main/pipelineobj.c b/src/mesa/main/pipelineobj.c
index f079c50..0439129 100644
--- a/src/mesa/main/pipelineobj.c
+++ b/src/mesa/main/pipelineobj.c
@@ -761,6 +761,7 @@ _mesa_validate_program_pipeline(struct gl_context* ctx,
 GLboolean IsBound)
 {
unsigned i;
+   bool program_empty = true;
 
pipe->Validated = GL_FALSE;
 
@@ -857,6 +858,29 @@ _mesa_validate_program_pipeline(struct gl_context* ctx,
   }
}
 
+   /* Section 11.1.3.11 (Validation) of the OpenGL 4.5 spec says:
+*
+*"An INVALID_OPERATION error is generated by any command that trans-
+*fers vertices to the GL or launches compute work if the current set
+*of active program objects cannot be executed, for reasons including:
+*
+*   ...
+*
+*   - There is no current program object specified by UseProgram,
+* there is a current program pipeline object, and that object is
+* empty (no executable code is installed for any stage).
+*/
+   for (i = 0; i < MESA_SHADER_STAGES; i++) {
+  if (pipe->CurrentProgram[i]) {
+ program_empty = false;
+ break;
+  }
+   }
+
+   if (program_empty) {
+  goto err;
+   }
+
/* Section 2.11.11 (Shader Execution), subheading "Validation," of the
 * OpenGL 4.1 spec says:
 *
-- 
2.4.3

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[Mesa-dev] [PATCH] swrast: Fix the coordinates passed to _mesa_regions_overlap()

[Anuj Phogat]

Cc: "11.1" 
Signed-off-by: Anuj Phogat 
---
 src/mesa/swrast/s_copypix.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mesa/swrast/s_copypix.c b/src/mesa/swrast/s_copypix.c
index 0dbccc0..31e1d3d 100644
--- a/src/mesa/swrast/s_copypix.c
+++ b/src/mesa/swrast/s_copypix.c
@@ -53,8 +53,10 @@ regions_overlap(GLint srcx, GLint srcy,
 GLfloat zoomX, GLfloat zoomY)
 {
if (zoomX == 1.0F && zoomY == 1.0F) {
-  return _mesa_regions_overlap(srcx, srcy, srcx + width, srcy + height,
-   dstx, dsty, dstx + width, dsty + height);
+  return _mesa_regions_overlap(srcx, srcy,
+   srcx + width - 1, srcy + height - 1,
+   dstx, dsty,
+   dstx + width - 1, dsty + height - 1);
}
else {
   /* add one pixel of slop when zooming, just to be safe */
-- 
2.4.3

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Re: [Mesa-dev] [PATCH 5/7] glsl: add always_active_io attribute to ir_variable

[Timothy Arceri]

On Sat, 2015-11-21 at 19:02 +1100, Timothy Arceri wrote:
> From: Gregory Hainaut 
> 
> The value will be set in separate-shader program when an input/output
> must remains active. e.g. when deadcode removal isn't allowed because
> it will create interface location/name-matching mismatch.
> 
> v3:
> * Rename the attribute
> * Use ir_variable directly instead of ir_variable_refcount_visitor
> * Move the foreach IR code in the linker file
> 
> v4:
> * Fix variable name in assert
> 
> v5 (by Timothy Arceri):
> * Rename functions and reword comments
> * Don't set alway active on builtins
> 
> Signed-off-by: Gregory Hainaut 
> Reviewed-by: Timothy Arceri 
> ---
>  src/glsl/ir.cpp |  1 +
>  src/glsl/ir.h   |  7 ++
>  src/glsl/linker.cpp | 72
> +
>  3 files changed, 80 insertions(+)
> 
> diff --git a/src/glsl/ir.cpp b/src/glsl/ir.cpp
> index ca520f5..f989e9b 100644
> --- a/src/glsl/ir.cpp
> +++ b/src/glsl/ir.cpp
> @@ -1669,6 +1669,7 @@ ir_variable::ir_variable(const struct glsl_type *type,
> const char *name,
> this->data.pixel_center_integer = false;
> this->data.depth_layout = ir_depth_layout_none;
> this->data.used = false;
> +   this->data.always_active_io = false;
> this->data.read_only = false;
> this->data.centroid = false;
> this->data.sample = false;
> diff --git a/src/glsl/ir.h b/src/glsl/ir.h
> index 386c993..6eb703b 100644
> --- a/src/glsl/ir.h
> +++ b/src/glsl/ir.h
> @@ -659,6 +659,13 @@ public:
>unsigned assigned:1;
>  
>/**
> +   * When separate shader programs are enabled, only input/outputs
> between
> +   * the stages of a multi-stage separate program can be safely removed
> +   * from the shader interface. Other input/outputs must remains
> active.
> +   */
> +  unsigned always_active_io:1;
> +
> +  /**
> * Enum indicating how the variable was declared.  See
> * ir_var_declaration_type.
> *
> diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
> index 1db7b7a..9b6efa9 100644
> --- a/src/glsl/linker.cpp
> +++ b/src/glsl/linker.cpp
> @@ -3988,6 +3988,75 @@ split_ubos_and_ssbos(void *mem_ctx,
> assert(*num_ubos + *num_ssbos == num_blocks);
>  }
>  
> +static void
> +set_always_active_io(exec_list *ir, ir_variable_mode io_mode)
> +{
> +   assert(io_mode == ir_var_shader_in || io_mode == ir_var_shader_out);
> +
> +   foreach_in_list(ir_instruction, node, ir) {
> +  ir_variable *const var = node->as_variable();
> +
> +  /* Don't set alway active on builtins */
> +  if (var == NULL || var->data.mode != io_mode ||
> +  var->data.how_declared == ir_var_declared_implicitly)
> + continue;

Note: I've changed this locally for clarity to:

  if (var == NULL || var->data.mode != io_mode)
 continue;

  /* Don't set alway active on builtins that haven't been redeclared */
  if(var->data.how_declared == ir_var_declared_implicitly)
 continue;


> +
> +  var->data.always_active_io = true;
> +   }
> +}
> +
> +/**
> + * When separate shader programs are enabled, only input/outputs between
> + * the stages of a multi-stage separate program can be safely removed
> + * from the shader interface. Other input/outputs must remains active.
> + */
> +static void
> +disable_varying_optimizations_for_sso(struct gl_shader_program *prog)
> +{
> +   unsigned first, last;
> +   assert(prog->SeparateShader);
> +
> +   first = MESA_SHADER_STAGES;
> +   last = 0;
> +
> +   /* Determine first and last stage. Excluding the compute stage */
> +   for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
> +  if (!prog->_LinkedShaders[i])
> + continue;
> +  if (first == MESA_SHADER_STAGES)
> + first = i;
> +  last = i;
> +   }
> +
> +   if (first == MESA_SHADER_STAGES)
> +  return;
> +
> +   for (unsigned stage = 0; stage < MESA_SHADER_STAGES; stage++) {
> +  gl_shader *sh = prog->_LinkedShaders[stage];
> +  if (!sh)
> + continue;
> +
> +  if (first == last) {
> + /* For a single shader program only allow inputs to the vertex
> shader
> +  * and outputs from the fragment shader to be removed.
> +  */
> + if (stage != MESA_SHADER_VERTEX)
> +set_always_active_io(sh->ir, ir_var_shader_in);
> + if (stage != MESA_SHADER_FRAGMENT)
> +set_always_active_io(sh->ir, ir_var_shader_out);
> +  } else {
> + /* For multi-stage separate shader programs only allow inputs and
> +  * outputs between the shader stages to be removed as well as
> inputs
> +  * to the vertex shader and outputs from the fragment shader.
> +  */
> + if (stage == first && stage != MESA_SHADER_VERTEX)
> +set_always_active_io(sh->ir, ir_var_shader_in);
> + else if (stage == last && stage != 

Re: [Mesa-dev] [Mesa-announce] Mesa 11.1.0 release candidate 1

[Thierry Vignaud]

On 21 November 2015 at 15:28, Emil Velikov  wrote:
> The first release candidate for Mesa 11.1.0 is now available.
>
> The plan is to have one release candidate every Friday, until the final
> release on December 11th 2015.
>
> As a reminder, with the 11.1 branch now created, patches nominated with:
>
> CC: 
>
> will now be candidates only for the new 11.1 branch. To nominate patches
> for the older 11.0 branch as well, please use:
>
> CC: "11.0 11.1" 
>
> The expectation is that the 11.0 branch will remain alive with bi-weekly
> releases until after 11.1.1 release.

It failed to build when we tried it yesterday on Mageia.
See
http://pkgsubmit.mageia.org/uploads/failure/cauldron/core/release/20151122205943.tv.valstar.4312/log/mesa-11.1.0~rc1-1.mga6/build.0.20151122210002.log

  CC   libloader_la-loader.lo
In file included from loader.c:93:0:
pci_id_driver_map.h:16:34: fatal error: pci_ids/i915_pci_ids.h: No
such file or directory
compilation terminated.
Makefile:628: recipe for target 'libloader_la-loader.lo' failed
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[Mesa-dev] [PATCH 2/7] i965/fs: Use a stride of 1 and byte offsets for UBOs

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_fs.cpp | 16 
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 11 ---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  2 +-
 3 files changed, 13 insertions(+), 16 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 777cee5..9e2b1fa2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -187,7 +187,7 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder 
,
 * the redundant ones.
 */
fs_reg vec4_offset = vgrf(glsl_type::int_type);
-   bld.ADD(vec4_offset, varying_offset, brw_imm_ud(const_offset & ~3));
+   bld.ADD(vec4_offset, varying_offset, brw_imm_ud(const_offset & ~0xf));
 
int scale = 1;
if (devinfo->gen == 4 && bld.dispatch_width() == 8) {
@@ -219,7 +219,7 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder 
,
  inst->mlen = 1 + bld.dispatch_width() / 8;
}
 
-   bld.MOV(dst, offset(vec4_result, bld, (const_offset & 3) * scale));
+   bld.MOV(dst, offset(vec4_result, bld, ((const_offset & 0xf) / 4) * scale));
 }
 
 /**
@@ -1999,10 +1999,12 @@ fs_visitor::demote_pull_constants()
 
  /* Generate a pull load into dst. */
  if (inst->src[i].reladdr) {
+fs_reg indirect = ibld.vgrf(BRW_REGISTER_TYPE_D);
+ibld.MUL(indirect, *inst->src[i].reladdr, brw_imm_d(4));
 VARYING_PULL_CONSTANT_LOAD(ibld, dst,
brw_imm_ud(index),
-   *inst->src[i].reladdr,
-   pull_index);
+   indirect,
+   pull_index * 4);
 inst->src[i].reladdr = NULL;
 inst->src[i].stride = 1;
  } else {
@@ -3038,13 +3040,11 @@ fs_visitor::lower_uniform_pull_constant_loads()
  continue;
 
   if (devinfo->gen >= 7) {
- /* The offset arg before was a vec4-aligned byte offset.  We need to
-  * turn it into a dword offset.
-  */
+ /* The offset arg is a vec4-aligned immediate byte offset. */
  fs_reg const_offset_reg = inst->src[1];
  assert(const_offset_reg.file == IMM &&
 const_offset_reg.type == BRW_REGISTER_TYPE_UD);
- const_offset_reg.ud /= 4;
+ assert(const_offset_reg.ud % 16 == 0);
 
  fs_reg payload, offset;
  if (devinfo->gen >= 9) {
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index c439da2..062ae08 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -2343,16 +2343,13 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
nir_intrinsic_instr *instr
   }
 
   if (has_indirect) {
- /* Turn the byte offset into a dword offset. */
- fs_reg base_offset = vgrf(glsl_type::int_type);
- bld.SHR(base_offset, retype(get_nir_src(instr->src[1]),
- BRW_REGISTER_TYPE_D),
- brw_imm_d(2));
+ fs_reg base_offset = retype(get_nir_src(instr->src[1]),
+ BRW_REGISTER_TYPE_D);
 
- unsigned vec4_offset = instr->const_index[0] / 4;
+ unsigned vec4_offset = instr->const_index[0];
  for (int i = 0; i < instr->num_components; i++)
 VARYING_PULL_CONSTANT_LOAD(bld, offset(dest, bld, i), surf_index,
-   base_offset, vec4_offset + i);
+   base_offset, vec4_offset + i * 4);
   } else {
  fs_reg packed_consts = vgrf(glsl_type::float_type);
  packed_consts.type = dest.type;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index f88f8d5..7cb7dd5 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -403,7 +403,7 @@ brw_create_constant_surface(struct brw_context *brw,
uint32_t *out_offset,
 bool dword_pitch)
 {
-   uint32_t stride = dword_pitch ? 4 : 16;
+   uint32_t stride = dword_pitch ? 1 : 16;
uint32_t elements = ALIGN(size, stride) / stride;
 
brw->vtbl.emit_buffer_surface_state(brw, out_offset, bo, offset,
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 4/7] i965/nir: Remove unused indirect handling

[Jason Ekstrand]

The one and only place where the FS backend allows reladdr is on uniforms.
For locals, inputs, and outputs, we lower it away before the backend ever
sees it.  This commit gets rid of the dead indirect handling code.
---
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 44 
 1 file changed, 11 insertions(+), 33 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 062ae08..39111ba 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -1076,28 +1076,6 @@ fs_visitor::nir_emit_undef(const fs_builder , 
nir_ssa_undef_instr *instr)
instr->def.num_components);
 }
 
-static fs_reg
-fs_reg_for_nir_reg(fs_visitor *v, nir_register *nir_reg,
-   unsigned base_offset, nir_src *indirect)
-{
-   fs_reg reg;
-
-   assert(!nir_reg->is_global);
-
-   reg = v->nir_locals[nir_reg->index];
-
-   reg = offset(reg, v->bld, base_offset * nir_reg->num_components);
-   if (indirect) {
-  int multiplier = nir_reg->num_components * (v->dispatch_width / 8);
-
-  reg.reladdr = new(v->mem_ctx) fs_reg(v->vgrf(glsl_type::int_type));
-  v->bld.MUL(*reg.reladdr, v->get_nir_src(*indirect),
- brw_imm_d(multiplier));
-   }
-
-   return reg;
-}
-
 fs_reg
 fs_visitor::get_nir_src(nir_src src)
 {
@@ -1105,8 +1083,10 @@ fs_visitor::get_nir_src(nir_src src)
if (src.is_ssa) {
   reg = nir_ssa_values[src.ssa->index];
} else {
-  reg = fs_reg_for_nir_reg(this, src.reg.reg, src.reg.base_offset,
-   src.reg.indirect);
+  /* We don't handle indirects on locals */
+  assert(src.reg.indirect == NULL);
+  reg = offset(nir_locals[src.reg.reg->index], bld,
+   src.reg.base_offset * src.reg.reg->num_components);
}
 
/* to avoid floating-point denorm flushing problems, set the type by
@@ -1123,10 +1103,12 @@ fs_visitor::get_nir_dest(nir_dest dest)
   nir_ssa_values[dest.ssa.index] = bld.vgrf(BRW_REGISTER_TYPE_F,
 dest.ssa.num_components);
   return nir_ssa_values[dest.ssa.index];
+   } else {
+  /* We don't handle indirects on locals */
+  assert(dest.reg.indirect == NULL);
+  return offset(nir_locals[dest.reg.reg->index], bld,
+dest.reg.base_offset * dest.reg.reg->num_components);
}
-
-   return fs_reg_for_nir_reg(this, dest.reg.reg, dest.reg.base_offset,
- dest.reg.indirect);
 }
 
 fs_reg
@@ -2422,7 +2404,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
nir_intrinsic_instr *instr
}
 
case nir_intrinsic_load_input_indirect:
-  has_indirect = true;
+  assert(!"Not allowed");
   /* fallthrough */
case nir_intrinsic_load_input: {
   unsigned index = 0;
@@ -2434,8 +2416,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
nir_intrinsic_instr *instr
 src = offset(retype(nir_inputs, dest.type), bld,
  instr->const_index[0] + index);
  }
- if (has_indirect)
-src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[0]));
  index++;
 
  bld.MOV(dest, src);
@@ -2508,7 +2488,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
nir_intrinsic_instr *instr
}
 
case nir_intrinsic_store_output_indirect:
-  has_indirect = true;
+  assert(!"Not allowed");
   /* fallthrough */
case nir_intrinsic_store_output: {
   fs_reg src = get_nir_src(instr->src[0]);
@@ -2516,8 +2496,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
nir_intrinsic_instr *instr
   for (unsigned j = 0; j < instr->num_components; j++) {
  fs_reg new_dest = offset(retype(nir_outputs, src.type), bld,
   instr->const_index[0] + index);
- if (has_indirect)
-src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[1]));
  index++;
  bld.MOV(new_dest, src);
  src = offset(src, bld, 1);
-- 
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[Mesa-dev] [PATCH 6/7] i965/fs: Make uniform offsets be in terms of bytes

[Jason Ekstrand]

This commit pushes makes uniform offsets be terms of bytes starting with
nir_lower_io.  They get converted to be in terms of floats when we cram
them in the UNIFORM register file but reladdr remains in terms of bytes all
the way down to the point where we lower it to a pull constant load.
---
 src/mesa/drivers/dri/i965/brw_fs.cpp |  4 +---
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 10 +++---
 src/mesa/drivers/dri/i965/brw_nir.c  | 17 ++---
 3 files changed, 22 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 9e2b1fa2..9fbf199 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1999,11 +1999,9 @@ fs_visitor::demote_pull_constants()
 
  /* Generate a pull load into dst. */
  if (inst->src[i].reladdr) {
-fs_reg indirect = ibld.vgrf(BRW_REGISTER_TYPE_D);
-ibld.MUL(indirect, *inst->src[i].reladdr, brw_imm_d(4));
 VARYING_PULL_CONSTANT_LOAD(ibld, dst,
brw_imm_ud(index),
-   indirect,
+   *inst->src[i].reladdr,
pull_index * 4);
 inst->src[i].reladdr = NULL;
 inst->src[i].stride = 1;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 39111ba..6ab9c1e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -1145,7 +1145,7 @@ fs_visitor::get_nir_image_deref(const nir_deref_var 
*deref)
 bld.MOV(tmp, get_nir_src(deref_array->indirect));
  }
 
- bld.MUL(tmp, tmp, brw_imm_ud(element_size));
+ bld.MUL(tmp, tmp, brw_imm_ud(element_size * 4));
  if (image.reladdr)
 bld.ADD(*image.reladdr, *image.reladdr, tmp);
  else
@@ -2280,8 +2280,12 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
nir_intrinsic_instr *instr
   has_indirect = true;
   /* fallthrough */
case nir_intrinsic_load_uniform: {
-  fs_reg uniform_reg(UNIFORM, instr->const_index[0]);
-  uniform_reg.reg_offset = instr->const_index[1];
+  /* Offsets are in bytes but they should always be multiples of 4 */
+  assert(instr->const_index[0] % 4 == 0);
+  assert(instr->const_index[1] % 4 == 0);
+
+  fs_reg uniform_reg(UNIFORM, instr->const_index[0] / 4);
+  uniform_reg.reg_offset = instr->const_index[1] / 4;
 
   for (unsigned j = 0; j < instr->num_components; j++) {
  fs_reg src = offset(retype(uniform_reg, dest.type), bld, j);
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c 
b/src/mesa/drivers/dri/i965/brw_nir.c
index e602df7..a33fb31 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -171,12 +171,23 @@ brw_nir_lower_outputs(nir_shader *nir, bool is_scalar)
}
 }
 
+static int
+type_size_scalar_bytes(const struct glsl_type *type)
+{
+   return type_size_scalar(type) * 4;
+}
+
 static void
 brw_nir_lower_uniforms(nir_shader *nir, bool is_scalar)
 {
-   nir_assign_var_locations(>uniforms,
->num_uniforms,
-is_scalar ? type_size_scalar : type_size_vec4);
+   if (is_scalar) {
+  nir_assign_var_locations(>uniforms, >num_uniforms,
+   type_size_scalar_bytes);
+  nir_lower_io(nir, nir_var_uniform, type_size_scalar_bytes);
+   } else {
+  nir_assign_var_locations(>uniforms, >num_uniforms,
+   type_size_vec4);
+   }
 }
 
 static bool
-- 
2.5.0.400.gff86faf

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