Re: [Mesa-dev] [RFC PATCH] egl/android: Dequeue buffers inside EGL calls

[Tomasz Figa]

On Mon, Apr 3, 2017 at 2:42 PM, Tapani Pälli  wrote:
>
>
> On 04/02/2017 08:12 PM, Tomasz Figa wrote:
>>
>> Sorry for replying to myself, just got enlightened...
>>
>> On Mon, Apr 3, 2017 at 2:07 AM, Tomasz Figa  wrote:
>>>
>>> Hi Mauro,
>>>
>>> On Mon, Apr 3, 2017 at 1:38 AM, Mauro Rossi 
>>> wrote:



 2017-03-30 16:17 GMT+02:00 Emil Velikov :
>
>
> On 30 March 2017 at 11:55, Tomasz Figa  wrote:
>>
>> Android buffer queues can be abandoned, which results in failing to
>> dequeue next buffer. Currently this would fail somewhere deep within
>> the DRI stack calling loader's getBuffers*(), without any error
>> reporting to the client app. However Android framework code relies on
>> proper signaling of this event, so we move buffer dequeue to
>> createWindowSurface() and swapBuffers() call, which can generate
>> proper
>> EGL errors. To keep the performance benefits of delayed buffer
>> handling,
>> if any, fence wait and DRI image creation is kept delayed until
>> getBuffers*() is called by the DRI driver.
>>
> Thank you Tomasz.
>
> I'm fairly confident that this should resolve the crash [in
> swap_buffers] that Mauro was seeing.
> Mauro can you give it a test ?



 After applying last version of Tomasz patch,
 I could not boot nougat-x86, the same way as per Tapani get_back_bo()
 throwing and EGL_BAD_ALLOC
 which is a show stopper for surfaceflinger
>>>
>>>
>>> Hmm, must be something I missed in the code, because with my patch
>>> applied, there should be no condition that could make get_back_bo()
>>> fail, unless previous swap_buffers() failed in droid_dequeue_buffer()
>>> or there is something wrong with the first buffer being dequeued in
>>> create_surface(). Would you be able to check where exactly
>>> get_back_bo() fails with your setup?
>>
>>
>> Ah, wait, I just realized that get_back_bo() is valid only when the
>> image loader is used, which is only on DMA-buf FD-based systems. No
>> wonder that it fails on android-x86.
>>
>> Tapani, would you be able to give a bit more details on the crash
>> being observed without that call? AFAICT, without my patch, even with
>> the call, the code is still not fully correct, because on the first
>> call to swap_buffers() without any rendering the dri2_surf->buffer
>> would be NULL and get_back_bo() would simply fail (but not crash
>> indeed). With my patch, it won't fail, because there is always a
>> buffer dequeued, so it should be the closest to correct behavior.
>
>
> Reason why that crash started to happen (observed only in one app so far!)
> were changes done in 'EGL/Android: Add EGL_EXT_buffer_age extension'. That
> patch adds 'age' for buffers and modifies droid_swap_buffers to set back
> buffer age to value 1. My original patch was to set the age only if there is
> a back buffer but then discussed with Emil and decided to unify approach
> with other backends and call get_back_bo.
>
> You are right that in the crash case dri2_surf->buffer is NULL as well.
>
> for long time flow looks like this:
>
> 01-01 00:00:54.087  2771  2791 D EGL-DRI2: droid_swap_buffers:
> dri2_surf->buffer 0xc8c88788 dri2_surf->back 0xca35ede8
> 01-01 00:00:54.104  2771  2791 D EGL-DRI2: droid_swap_buffers:
> dri2_surf->buffer 0xc8e84e08 dri2_surf->back 0xca35edd8
> 01-01 00:00:54.120 2771 2791 D EGL-DRI2: droid_swap_buffers:
> dri2_surf->buffer 0xc8c885a8 dri2_surf->back 0xca35ede0
>
> then all of sudden there is a frame where buffer and back are 0:
>
> 01-01 00:00:55.386  2771  2791 D EGL-DRI2: droid_swap_buffers:
> dri2_surf->buffer 0xc8c885a8 dri2_surf->back 0xca35ede0
> 01-01 00:00:55.390  2771  2831 D EGL-DRI2: droid_swap_buffers:
> dri2_surf->buffer 0xc8c8b2a8 dri2_surf->back 0xca360098
> 01-01 00:00:55.391  2771  2831 D EGL-DRI2: droid_swap_buffers:
> dri2_surf->buffer 0x0 dri2_surf->back 0x0

I guess it means that there was no rendering happening between the two
swaps above, so my patch should take care of this case indeed and the
call to get_back_bo() is not needed anymore (actually it should have
been update_buffers(), not get_back_bo()).

Thanks for really helpful explanation.

Best regards,
Tomasz
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Re: [Mesa-dev] [RFC PATCH] egl/android: Dequeue buffers inside EGL calls

[Tapani Pälli]

On 04/02/2017 08:12 PM, Tomasz Figa wrote:

Sorry for replying to myself, just got enlightened...

On Mon, Apr 3, 2017 at 2:07 AM, Tomasz Figa  wrote:

Hi Mauro,

On Mon, Apr 3, 2017 at 1:38 AM, Mauro Rossi  wrote:



2017-03-30 16:17 GMT+02:00 Emil Velikov :


On 30 March 2017 at 11:55, Tomasz Figa  wrote:

Android buffer queues can be abandoned, which results in failing to
dequeue next buffer. Currently this would fail somewhere deep within
the DRI stack calling loader's getBuffers*(), without any error
reporting to the client app. However Android framework code relies on
proper signaling of this event, so we move buffer dequeue to
createWindowSurface() and swapBuffers() call, which can generate proper
EGL errors. To keep the performance benefits of delayed buffer handling,
if any, fence wait and DRI image creation is kept delayed until
getBuffers*() is called by the DRI driver.


Thank you Tomasz.

I'm fairly confident that this should resolve the crash [in
swap_buffers] that Mauro was seeing.
Mauro can you give it a test ?



After applying last version of Tomasz patch,
I could not boot nougat-x86, the same way as per Tapani get_back_bo()
throwing and EGL_BAD_ALLOC
which is a show stopper for surfaceflinger


Hmm, must be something I missed in the code, because with my patch
applied, there should be no condition that could make get_back_bo()
fail, unless previous swap_buffers() failed in droid_dequeue_buffer()
or there is something wrong with the first buffer being dequeued in
create_surface(). Would you be able to check where exactly
get_back_bo() fails with your setup?


Ah, wait, I just realized that get_back_bo() is valid only when the
image loader is used, which is only on DMA-buf FD-based systems. No
wonder that it fails on android-x86.

Tapani, would you be able to give a bit more details on the crash
being observed without that call? AFAICT, without my patch, even with
the call, the code is still not fully correct, because on the first
call to swap_buffers() without any rendering the dri2_surf->buffer
would be NULL and get_back_bo() would simply fail (but not crash
indeed). With my patch, it won't fail, because there is always a
buffer dequeued, so it should be the closest to correct behavior.


Reason why that crash started to happen (observed only in one app so 
far!) were changes done in 'EGL/Android: Add EGL_EXT_buffer_age 
extension'. That patch adds 'age' for buffers and modifies 
droid_swap_buffers to set back buffer age to value 1. My original patch 
was to set the age only if there is a back buffer but then discussed 
with Emil and decided to unify approach with other backends and call 
get_back_bo.


You are right that in the crash case dri2_surf->buffer is NULL as well.

for long time flow looks like this:

01-01 00:00:54.087  2771  2791 D EGL-DRI2: droid_swap_buffers: 
dri2_surf->buffer 0xc8c88788 dri2_surf->back 0xca35ede8
01-01 00:00:54.104  2771  2791 D EGL-DRI2: droid_swap_buffers: 
dri2_surf->buffer 0xc8e84e08 dri2_surf->back 0xca35edd8
01-01 00:00:54.120  2771  2791 D EGL-DRI2: droid_swap_buffers: 
dri2_surf->buffer 0xc8c885a8 dri2_surf->back 0xca35ede0


then all of sudden there is a frame where buffer and back are 0:

01-01 00:00:55.386  2771  2791 D EGL-DRI2: droid_swap_buffers: 
dri2_surf->buffer 0xc8c885a8 dri2_surf->back 0xca35ede0
01-01 00:00:55.390  2771  2831 D EGL-DRI2: droid_swap_buffers: 
dri2_surf->buffer 0xc8c8b2a8 dri2_surf->back 0xca360098
01-01 00:00:55.391  2771  2831 D EGL-DRI2: droid_swap_buffers: 
dri2_surf->buffer 0x0 dri2_surf->back 0x0
01-01 00:00:55.395  1943  2088 D EGL-DRI2: droid_swap_buffers: 
dri2_surf->buffer 0x7c449f5ed610 dri2_surf->back 0x7c44b2cfc010


then we crash:

01-01 00:00:56.101  2836  2836 F DEBUG   : backtrace:
01-01 00:00:56.101  2836  2836 F DEBUG   : #00 pc 00014046 
/system/lib/egl/libGLES_mesa.so (droid_swap_buffers+166)
01-01 00:00:56.101  2836  2836 F DEBUG   : #01 pc 00011832 
/system/lib/egl/libGLES_mesa.so (dri2_swap_buffers+50)
01-01 00:00:56.101  2836  2836 F DEBUG   : #02 pc 58c2 
/system/lib/egl/libGLES_mesa.so (eglSwapBuffers+386)
01-01 00:00:56.101  2836  2836 F DEBUG   : #03 pc 00011329 
/system/lib/libEGL.so (eglSwapBuffersWithDamageKHR+553)
01-01 00:00:56.101  2836  2836 F DEBUG   : #04 pc 000118e7 
/system/lib/libEGL.so (eglSwapBuffers+55)
01-01 00:00:56.101  2836  2836 F DEBUG   : #05 pc 000754dc 
/system/lib/libandroid_runtime.so
01-01 00:00:56.101  2836  2836 F DEBUG   : #06 pc 0249217c 
/system/framework/x86/boot-framework.oat (offset 0x1584000) 
(com.google.android.gles_jni.EGLImpl.eglSwapBuffers+168)
01-01 00:00:56.101  2836  2836 F DEBUG   : #07 pc 01cc8dec 
/system/framework/x86/boot-framework.oat (offset 0x1584000) 
(android.opengl.GLSurfaceView$EglHelper.swap+72)
01-01 00:00:56.101  2836  2836 F DEBUG   : #08 pc 01cc9ebe 
/system/framework/x86/boot-framework.oat (offset 

[Mesa-dev] [PATCH] radv/winsys: only workout color/depth levels if we have color/depth

[Dave Airlie]

From: Dave Airlie 

This fixes an old bug that seems to get triggered by
dEQP-VK.memory.requirements.image.sparse_tiling_optimal

We return early when allocating S8_UINT due to there being
no color or depth, and end up with image size of 0.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 48 --
 1 file changed, 26 insertions(+), 22 deletions(-)

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
index 0433952..53ca6ff 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
@@ -481,28 +481,32 @@ static int radv_amdgpu_winsys_surface_init(struct 
radeon_winsys *_ws,
surf->htile_size = surf->htile_slice_size = 0;
surf->htile_alignment = 1;
 
-   /* Calculate texture layout information. */
-   for (level = 0; level <= surf->last_level; level++) {
-   r = radv_compute_level(ws->addrlib, surf, false, level, type, 
compressed,
-  , , 
, );
-   if (r)
-   return r;
-
-   if (level == 0) {
-   surf->bo_alignment = AddrSurfInfoOut.baseAlign;
-   surf->pipe_config = 
AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
-   radv_set_micro_tile_mode(surf, >info);
-
-   /* For 2D modes only. */
-   if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) 
{
-   surf->bankw = 
AddrSurfInfoOut.pTileInfo->bankWidth;
-   surf->bankh = 
AddrSurfInfoOut.pTileInfo->bankHeight;
-   surf->mtilea = 
AddrSurfInfoOut.pTileInfo->macroAspectRatio;
-   surf->tile_split = 
AddrSurfInfoOut.pTileInfo->tileSplitBytes;
-   surf->num_banks = 
AddrSurfInfoOut.pTileInfo->banks;
-   surf->macro_tile_index = 
AddrSurfInfoOut.macroModeIndex;
-   } else {
-   surf->macro_tile_index = 0;
+   if (AddrSurfInfoIn.flags.color || AddrSurfInfoIn.flags.depth) {
+   /* Calculate texture layout information. */
+   for (level = 0; level <= surf->last_level; level++) {
+   r = radv_compute_level(ws->addrlib, surf, false, level, 
type, compressed,
+  , 
, , );
+   if (r) {
+   assert(0);
+   return r;
+   }
+
+   if (level == 0) {
+   surf->bo_alignment = AddrSurfInfoOut.baseAlign;
+   surf->pipe_config = 
AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
+   radv_set_micro_tile_mode(surf, >info);
+   
+   /* For 2D modes only. */
+   if (AddrSurfInfoOut.tileMode >= 
ADDR_TM_2D_TILED_THIN1) {
+   surf->bankw = 
AddrSurfInfoOut.pTileInfo->bankWidth;
+   surf->bankh = 
AddrSurfInfoOut.pTileInfo->bankHeight;
+   surf->mtilea = 
AddrSurfInfoOut.pTileInfo->macroAspectRatio;
+   surf->tile_split = 
AddrSurfInfoOut.pTileInfo->tileSplitBytes;
+   surf->num_banks = 
AddrSurfInfoOut.pTileInfo->banks;
+   surf->macro_tile_index = 
AddrSurfInfoOut.macroModeIndex;
+   } else {
+   surf->macro_tile_index = 0;
+   }
}
}
}
-- 
2.9.3

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Re: [Mesa-dev] [RFC PATCH] egl/android: Dequeue buffers inside EGL calls

[Tapani Pälli]

On 04/02/2017 07:38 PM, Mauro Rossi wrote:



2017-03-30 16:17 GMT+02:00 Emil Velikov >:

On 30 March 2017 at 11:55, Tomasz Figa > wrote:
> Android buffer queues can be abandoned, which results in failing to
> dequeue next buffer. Currently this would fail somewhere deep within
> the DRI stack calling loader's getBuffers*(), without any error
> reporting to the client app. However Android framework code relies on
> proper signaling of this event, so we move buffer dequeue to
> createWindowSurface() and swapBuffers() call, which can generate
proper
> EGL errors. To keep the performance benefits of delayed buffer
handling,
> if any, fence wait and DRI image creation is kept delayed until
> getBuffers*() is called by the DRI driver.
>
Thank you Tomasz.

I'm fairly confident that this should resolve the crash [in
swap_buffers] that Mauro was seeing.
Mauro can you give it a test ?


After applying last version of Tomasz patch,
I could not boot nougat-x86, the same way as per Tapani get_back_bo()
throwing and EGL_BAD_ALLOC
which is a show stopper for surfaceflinger

So I reverted [1] and now I can boot and I also see the black wallpaper
like Tapani.
dumpsys SurfaceFlinger output shows a buffer allocated,
but for some reason both HWC and GLES composition (used in nougat-x86)
show black wallpaper.


h/w composer state:
  h/w composer not present and enabled
Allocated buffers:
...
0x7b60f301e380: 29440.00 KiB | 2880 (2944) x 2560 |5 |
0x0900 | com.android.systemui.ImageWallpaper
...
Total allocated (estimate): 54728.50 KB




Not that huge of an expert on the Android specifics, so just a
humble request:
Can we seek the code resuffle (droid_{alloc,free}_local_buffer,
other?) separate from the functionality changes ?

-Emil


I'd also kindly request to confirm the test environment used to verify
Tomasz patch v2,
which in my understanding has been the following, common between
ChomiumOS and Android-IA:

  * minigbm based gralloc
  * dma FDs for buffers
  * kernel based explicit fences with FDs
  * HWC2 for compositing
  * (?) Render nodes - but I don't know if/when they are used

In android-x86 (nougat-x86) situation is the following:

  * drm_gralloc based gralloc
  * buffer handles
  * Not 100% sure about sync/fences, but I don't recall about using
explicit fences with FDs
  * GLES for compositing
  * we don't use render nodes

Pardon me if this seems a long checklist or if it's not 100% accurate,
but I would assume that this patch should just work Out-Of-The-Box with
android-x86 (nougat-x86)
even if most of CrOS/Android-IA optimizations are not (yet) used there.

Is this assumption correct?

In this moment the only way to boot nougat-x86 is to revert [1]
but besides this and black wallpaper, which both require investigation,
I've not seen any particular regression.

Thanks for feeedbacks
Mauro

PS: Question for Tapani: if you apply Tomasz patch and revert [1], do
you still see the segfault in Android-IA?


No, that patch is not needed anymore as it seems now there is always a 
back buffer available when coming to droid_swap_buffers. I tested with 
the 3DMark app that caused that crash.




[1]
 
https://cgit.freedesktop.org/mesa/mesa/commit/?id=4d4558411db166d2d66f8cec9cb581149dbe1597






// Tapani
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Re: [Mesa-dev] [PATCH] travis: remove r600 as it requires llvm 3.8

[Christian Gmeiner]

Hi,

2017-04-02 22:44 GMT+02:00 Rhys Kidd :
> On 2 April 2017 at 08:42, Christian Gmeiner 
> wrote:
>>
>> At the moment travis ci failes with the following error:
>>
>> checking for RADEON... yes
>> checking for RADEON... yes
>> configure: error: LLVM 3.8.0 or newer is required for r600
>> make: *** No targets specified and no makefile found.  Stop.
>>
>> Signed-off-by: Christian Gmeiner 
>
>
> NACK.
>
> I'll send out to the mailing list shortly a patch that enables LLVM 3.8+ on
> Travis-CI's Trusty-based environment that we use.
>
> Allows r600g to remain and should theoretically allow radeonsi to be tested
> as well. Possibly the vulkan drivers and swr too without a great deal
> further work.
>

Great - thanks!

greets
--
Christian Gmeiner, MSc

https://www.youtube.com/user/AloryOFFICIAL
https://soundcloud.com/christian-gmeiner
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[Mesa-dev] [PATCH] st/omx/dec: Properly undefine DEBUG macro

[Shaleen Jain]

---
 src/gallium/state_trackers/omx/vid_dec.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/state_trackers/omx/vid_dec.c 
b/src/gallium/state_trackers/omx/vid_dec.c
index 9a6efb8e28..94664eba04 100644
--- a/src/gallium/state_trackers/omx/vid_dec.c
+++ b/src/gallium/state_trackers/omx/vid_dec.c
@@ -37,7 +37,7 @@
 #include 
 
 /* bellagio defines a DEBUG macro that we don't want */
-#ifndef DEBUG
+#ifdef DEBUG
 #include 
 #undef DEBUG
 #else
-- 
2.12.1

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Re: [Mesa-dev] [PATCH 2/2] st/shader_cache: Fix memory leak

[Brian Paul]

On Sun, Apr 2, 2017 at 11:31 AM, Bartosz Tomczyk <
bartosz.tomczy...@gmail.com> wrote:

> ---
>  src/mesa/state_tracker/st_shader_cache.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/src/mesa/state_tracker/st_shader_cache.c
> b/src/mesa/state_tracker/st_shader_cache.c
> index e8c7289ec6..5dbcb74f73 100644
> --- a/src/mesa/state_tracker/st_shader_cache.c
> +++ b/src/mesa/state_tracker/st_shader_cache.c
> @@ -135,6 +135,8 @@ st_store_tgsi_in_disk_cache(struct st_context *st,
> struct gl_program *prog,
>_mesa_shader_stage_to_string(prog->info.stage), sha1_buf);
> }
>
> +   if(blob->data)
> +  free(blob->data);
>

free() should accept NULL, so the conditional shouldn't be needed.

-Brian



> free(blob);
>  }
>
> --
> 2.12.2
>
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[Mesa-dev] [PATCH 1/2] radv/ac: round cube array coordinate before fixup.

[Dave Airlie]

From: Dave Airlie 

This fixes:
dEQP-VK.glsl.texture_functions.texture.samplercubearray*

Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_nir_to_llvm.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 6985371..adba539 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4237,6 +4237,8 @@ static void visit_tex(struct nir_to_llvm_context *ctx, 
nir_tex_instr *instr)
}
 
if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
+   if (instr->is_array && instr->op != nir_texop_lod)
+   coords[3] = apply_round_slice(ctx, coords[3]);
for (chan = 0; chan < instr->coord_components; chan++)
coords[chan] = to_float(ctx, coords[chan]);
if (instr->coord_components == 3)
@@ -4264,7 +4266,9 @@ static void visit_tex(struct nir_to_llvm_context *ctx, 
nir_tex_instr *instr)
}
if (instr->coord_components > 2) {
/* This seems like a bit of a hack - but it passes 
Vulkan CTS with it */
-   if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && 
instr->op != nir_texop_txf) {
+   if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
+   instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
+   instr->op != nir_texop_txf) {
coords[2] = apply_round_slice(ctx, coords[2]);
}
address[count++] = coords[2];
-- 
2.7.4

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[Mesa-dev] [PATCH 2/2] radv/ac: fix texture derivative ordering

[Dave Airlie]

From: Dave Airlie 

The ordering NIR gives us is correct for the hw, this fixes:
dEQP-VK.glsl.texture_functions.texturegrad.* (mainly trigged
on isampler/usampler 3d textures.).

Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_nir_to_llvm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index adba539..75aacde 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4231,8 +4231,8 @@ static void visit_tex(struct nir_to_llvm_context *ctx, 
nir_tex_instr *instr)
}
 
for (unsigned i = 0; i < num_deriv_comp; i++) {
-   derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, 
ddx, i));
-   derivs[i * 2 + 1] = to_float(ctx, 
llvm_extract_elem(ctx, ddy, i));
+   derivs[i] = to_float(ctx, llvm_extract_elem(ctx, ddx, 
i));
+   derivs[num_deriv_comp + i] = to_float(ctx, 
llvm_extract_elem(ctx, ddy, i));
}
}
 
-- 
2.7.4

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[Mesa-dev] [PATCH 2/2] radv: fix interp at sample code.

[Dave Airlie]

From: Dave Airlie 

Interp at sample needs to use the center, since the sample
positions it retrieves are relative to the center.

This fixes a bunch of CTS tests with multisample_interpolation.

Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_nir_to_llvm.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index aabcabe..6985371 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3556,12 +3556,10 @@ static LLVMValueRef visit_interp(struct 
nir_to_llvm_context *ctx,
location = INTERP_CENTROID;
break;
case nir_intrinsic_interp_var_at_sample:
-   location = INTERP_SAMPLE;
-   src0 = get_src(ctx, instr->src[0]);
-   break;
case nir_intrinsic_interp_var_at_offset:
location = INTERP_CENTER;
src0 = get_src(ctx, instr->src[0]);
+   break;
default:
break;
}
-- 
2.7.4

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[Mesa-dev] [PATCH 1/2] radv: overhaul fragment shader sample positions.

[Dave Airlie]

From: Dave Airlie 

The current code was broken, and I decided to redesign it instead.

This puts the sample positions for all samples into the queue
constant descriptor buffer after all the spill/ring descriptors.

It then uses a single offset register to point how far into the
samples the samples for num_samples are. This saves one user sgpr
and means we only generate the sample position data in the rare
single case where we need it currently.

This doesn't fix the failing CTS tests without the followup
fix.

Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_nir_to_llvm.c  | 31 +++-
 src/amd/common/ac_nir_to_llvm.h  |  4 ++-
 src/amd/vulkan/radv_cmd_buffer.c | 61 
 src/amd/vulkan/radv_device.c | 40 ++
 src/amd/vulkan/radv_private.h|  2 ++
 5 files changed, 87 insertions(+), 51 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 520e4cf..aabcabe 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -109,7 +109,7 @@ struct nir_to_llvm_context {
LLVMValueRef hs_ring_tess_factor;
 
LLVMValueRef prim_mask;
-   LLVMValueRef sample_positions;
+   LLVMValueRef sample_pos_offset;
LLVMValueRef persp_sample, persp_center, persp_centroid;
LLVMValueRef linear_sample, linear_center, linear_centroid;
LLVMValueRef front_face;
@@ -573,6 +573,7 @@ static void create_function(struct nir_to_llvm_context *ctx)
ctx->stage == MESA_SHADER_VERTEX ||
ctx->stage == MESA_SHADER_TESS_CTRL ||
ctx->stage == MESA_SHADER_TESS_EVAL ||
+   ctx->stage == MESA_SHADER_FRAGMENT ||
ctx->is_gs_copy_shader)
need_ring_offsets = true;
 
@@ -584,7 +585,7 @@ static void create_function(struct nir_to_llvm_context *ctx)
need_push_constants = false;
 
if (need_ring_offsets && !ctx->options->supports_spill) {
-   arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address 
of rings */
+   arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* address 
of rings */
}
 
/* 1 for each descriptor set */
@@ -679,7 +680,7 @@ static void create_function(struct nir_to_llvm_context *ctx)
arg_types[arg_idx++] = ctx->i32; // GS instance id
break;
case MESA_SHADER_FRAGMENT:
-   arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample 
positions */
+   arg_types[arg_idx++] = ctx->i32; /* sample position offset */
user_sgpr_count = arg_idx;
arg_types[arg_idx++] = ctx->i32; /* prim mask */
sgpr_count = arg_idx;
@@ -735,7 +736,7 @@ static void create_function(struct nir_to_llvm_context *ctx)
   
LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
   NULL, 0, 
AC_FUNC_ATTR_READNONE);
ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, 
ctx->ring_offsets,
-
const_array(ctx->v16i8, 8), "");
+
const_array(ctx->v16i8, 16), "");
} else
ctx->ring_offsets = LLVMGetParam(ctx->main_function, 
arg_idx++);
}
@@ -844,9 +845,9 @@ static void create_function(struct nir_to_llvm_context *ctx)
ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, 
arg_idx++);
break;
case MESA_SHADER_FRAGMENT:
-   set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, 
user_sgpr_idx, 2);
-   user_sgpr_idx += 2;
-   ctx->sample_positions = LLVMGetParam(ctx->main_function, 
arg_idx++);
+   set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, 
user_sgpr_idx, 1);
+   user_sgpr_idx += 1;
+   ctx->sample_pos_offset = LLVMGetParam(ctx->main_function, 
arg_idx++);
ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
@@ -3518,15 +3519,17 @@ static LLVMValueRef lookup_interp_param(struct 
nir_to_llvm_context *ctx,
 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
 LLVMValueRef sample_id)
 {
-   /* offset = sample_id * 8  (8 = 2 floats containing samplepos.xy) */
-   LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, 
LLVMConstInt(ctx->i32, 8, false), "");
-   LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, 
LLVMConstInt(ctx->i32, 4, false), "");
-   LLVMValueRef result[2];
+   LLVMValueRef result;
+   

Re: [Mesa-dev] [PATCH] mesa/glthread: Call unmarshal_batch directly in glthread_finish

[Timothy Arceri]

Trailing whitespace and style issue with else fixed and pushed. Thanks!

On 31/03/17 17:22, Nicolai Hähnle wrote:

On 30.03.2017 22:31, Bartosz Tomczyk wrote:

Call it directly when batch queue is empty. This avoids costly thread
synchronisation. This commit improves performance of games that have
previously regressed with mesa_glthread=true.


Reviewed-by: Nicolai Hähnle 


---
 src/mesa/main/glthread.c | 47
++-
 1 file changed, 34 insertions(+), 13 deletions(-)

diff --git a/src/mesa/main/glthread.c b/src/mesa/main/glthread.c
index 06115b916d..4fcd322163 100644
--- a/src/mesa/main/glthread.c
+++ b/src/mesa/main/glthread.c
@@ -194,16 +194,12 @@ _mesa_glthread_restore_dispatch(struct
gl_context *ctx)
}
 }

-void
-_mesa_glthread_flush_batch(struct gl_context *ctx)
+static void
+_mesa_glthread_flush_batch_locked(struct gl_context *ctx)
 {
struct glthread_state *glthread = ctx->GLThread;
-   struct glthread_batch *batch;
-
-   if (!glthread)
-  return;
-
-   batch = glthread->batch;
+   struct glthread_batch *batch = glthread->batch;
+
if (!batch->used)
   return;

@@ -223,10 +219,26 @@ _mesa_glthread_flush_batch(struct gl_context *ctx)
   return;
}

-   pthread_mutex_lock(>mutex);
*glthread->batch_queue_tail = batch;
glthread->batch_queue_tail = >next;
pthread_cond_broadcast(>new_work);
+}
+
+void
+_mesa_glthread_flush_batch(struct gl_context *ctx)
+{
+   struct glthread_state *glthread = ctx->GLThread;
+   struct glthread_batch *batch;
+
+   if (!glthread)
+  return;
+
+   batch = glthread->batch;
+   if (!batch->used)
+  return;
+
+   pthread_mutex_lock(>mutex);
+   _mesa_glthread_flush_batch_locked(ctx);
pthread_mutex_unlock(>mutex);
 }

@@ -252,12 +264,21 @@ _mesa_glthread_finish(struct gl_context *ctx)
if (pthread_self() == glthread->thread)
   return;

-   _mesa_glthread_flush_batch(ctx);
-
pthread_mutex_lock(>mutex);

-   while (glthread->batch_queue || glthread->busy)
-  pthread_cond_wait(>work_done, >mutex);
+   if (!(glthread->batch_queue || glthread->busy)) {
+  if (glthread->batch && glthread->batch->used) {
+ struct _glapi_table *dispatch = _glapi_get_dispatch();
+ glthread_unmarshal_batch(ctx, glthread->batch);
+ _glapi_set_dispatch(dispatch);
+ glthread_allocate_batch(ctx);
+  }
+   }
+   else {
+  _mesa_glthread_flush_batch_locked(ctx);
+  while (glthread->batch_queue || glthread->busy)
+ pthread_cond_wait(>work_done, >mutex);
+   }

pthread_mutex_unlock(>mutex);
 }





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Re: [Mesa-dev] [PATCH 2/3] radeonsi: remove most uses of lp_build_const*

[Timothy Arceri]

That changes to the param in si_llvm_pack_two_int16() and 
si_llvm_pack_two_int32_as_int16() should probably have been split out.


Anyway with or without that change series is:

Reviewed-by: Timothy Arceri 
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Re: [Mesa-dev] [PATCH 2/3] radeonsi: remove most uses of lp_build_const*

[Timothy Arceri]

The changes to the param in si_llvm_pack_two_int16() and 
si_llvm_pack_two_int32_as_int16() should probably have been split out.


Anyway with or without that change series is:

Reviewed-by: Timothy Arceri 
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[Mesa-dev] [PATCH 1/3] radeonsi: clean up 'radeon_bld' references

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_shader.c | 108 ++-
 1 file changed, 48 insertions(+), 60 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 3876010..2da00f9 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -293,37 +293,35 @@ get_tcs_out_current_patch_data_offset(struct 
si_shader_context *ctx)
LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
 
return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
LLVMBuildMul(gallivm->builder, patch_stride,
 rel_patch_id, ""),
"");
 }
 
 static LLVMValueRef get_instance_index_for_fetch(
-   struct si_shader_context *radeon_bld,
+   struct si_shader_context *ctx,
unsigned param_start_instance, unsigned divisor)
 {
-   struct si_shader_context *ctx =
-   si_shader_context(_bld->bld_base);
-   struct gallivm_state *gallivm = radeon_bld->bld_base.base.gallivm;
+   struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
 
-   LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
+   LLVMValueRef result = LLVMGetParam(ctx->main_fn,
   ctx->param_instance_id);
 
/* The division must be done before START_INSTANCE is added. */
if (divisor > 1)
result = LLVMBuildUDiv(gallivm->builder, result,
lp_build_const_int32(gallivm, divisor), "");
 
return LLVMBuildAdd(gallivm->builder, result,
-   LLVMGetParam(radeon_bld->main_fn, 
param_start_instance), "");
+   LLVMGetParam(ctx->main_fn, param_start_instance), 
"");
 }
 
 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
  * to float. */
 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
LLVMValueRef vec4,
unsigned double_index)
 {
LLVMBuilderRef builder = ctx->gallivm.builder;
LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->gallivm.context);
@@ -1279,30 +1277,28 @@ static void interp_fs_input(struct si_shader_context 
*ctx,
} else {
result[chan] = ac_build_fs_interp_mov(>ac,
lp_build_const_int32(gallivm, 2), /* P0 
*/
llvm_chan, attr_number, prim_mask);
}
}
}
 }
 
 static void declare_input_fs(
-   struct si_shader_context *radeon_bld,
+   struct si_shader_context *ctx,
unsigned input_index,
const struct tgsi_full_declaration *decl,
LLVMValueRef out[4])
 {
-   struct lp_build_context *base = _bld->bld_base.base;
-   struct si_shader_context *ctx =
-   si_shader_context(_bld->bld_base);
+   struct lp_build_context *base = >bld_base.base;
struct si_shader *shader = ctx->shader;
-   LLVMValueRef main_fn = radeon_bld->main_fn;
+   LLVMValueRef main_fn = ctx->main_fn;
LLVMValueRef interp_param = NULL;
int interp_param_idx;
 
/* Get colors from input VGPRs (set by the prolog). */
if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
unsigned i = decl->Semantic.Index;
unsigned colors_read = shader->selector->info.colors_read;
unsigned mask = colors_read >> (i * 4);
unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
  (i ? util_bitcount(colors_read & 0xf) : 0);
@@ -1328,171 +1324,165 @@ static void declare_input_fs(
interp_param = NULL; /* load the constant color */
 
interp_fs_input(ctx, input_index, decl->Semantic.Name,
decl->Semantic.Index, shader->selector->info.num_inputs,
shader->selector->info.colors_read, interp_param,
LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
[0]);
 }
 
-static LLVMValueRef get_sample_id(struct si_shader_context *radeon_bld)
+static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
 {
-   return unpack_param(si_shader_context(_bld->bld_base),
-   SI_PARAM_ANCILLARY, 8, 4);
+   return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
 }
 
 
 /**
  * Load a dword from a constant buffer.
  */
 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
  LLVMValueRef resource,
  LLVMValueRef offset)
 {

[Mesa-dev] [PATCH 3/3] radeonsi: use i32_0 and i32_1 more

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_shader.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index e514d61..21efd9a 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -794,21 +794,21 @@ static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
if (reg.Indirect.ArrayID)
param_base = array_first[reg.Indirect.ArrayID];
else
param_base = reg.Register.Index;
 
param_index = get_indirect_index(ctx, ,
 reg.Register.Index - 
param_base);
 
} else {
param_base = reg.Register.Index;
-   param_index = LLVMConstInt(ctx->i32, 0, 0);
+   param_index = ctx->i32_0;
}
 
param_index_base = si_shader_io_get_unique_index(name[param_base],
 index[param_base]);
 
param_index = LLVMBuildAdd(gallivm->builder, param_index,
   LLVMConstInt(ctx->i32, param_index_base, 0),
   "");
 
return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
@@ -876,21 +876,21 @@ static LLVMValueRef lds_load(struct lp_build_tgsi_context 
*bld_base,
  TGSI_NUM_CHANNELS);
}
 
dw_addr = lp_build_add(_base->uint_bld, dw_addr,
LLVMConstInt(ctx->i32, swizzle, 0));
 
value = ac_build_indexed_load(>ac, ctx->lds, dw_addr, false);
if (tgsi_type_is_64bit(type)) {
LLVMValueRef value2;
dw_addr = lp_build_add(_base->uint_bld, dw_addr,
-  LLVMConstInt(ctx->i32, 1, 0));
+  ctx->i32_1);
value2 = ac_build_indexed_load(>ac, ctx->lds, dw_addr, 
false);
return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
}
 
return LLVMBuildBitCast(gallivm->builder, value,
tgsi2llvmtype(bld_base, type), "");
 }
 
 /**
  * Store to LDS.
@@ -1864,21 +1864,21 @@ static void si_llvm_init_export_args(struct 
lp_build_tgsi_context *bld_base,
  si_llvm_pack_two_int16(ctx, val+2));
break;
}
 
case V_028714_SPI_SHADER_SINT16_ABGR: {
LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
LLVMValueRef max_alpha =
-   !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 1, 0);
+   !is_int10 ? max_rgb : ctx->i32_1;
LLVMValueRef min_alpha =
!is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
 
/* Clamp. */
for (chan = 0; chan < 4; chan++) {
val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, 
values[chan]);
val[chan] = lp_build_emit_llvm_binary(bld_base,
TGSI_OPCODE_IMIN,
val[chan], chan == 3 ? max_alpha : 
max_rgb);
val[chan] = lp_build_emit_llvm_binary(bld_base,
@@ -2058,21 +2058,21 @@ static void emit_streamout_output(struct 
si_shader_context *ctx,
for (int j = 0; j < num_comps; j++) {
vdata = LLVMBuildInsertElement(builder, vdata, out[j],
   LLVMConstInt(ctx->i32, 
j, 0), "");
}
break;
}
 
ac_build_buffer_store_dword(>ac, so_buffers[buf_idx],
vdata, num_comps,
so_write_offsets[buf_idx],
-   LLVMConstInt(ctx->i32, 0, 0),
+   ctx->i32_0,
stream_out->dst_offset * 4, 1, 1, true, 
false);
 }
 
 /**
  * Write streamout data to buffers for vertex stream @p stream (different
  * vertex streams can occur for GS copy shaders).
  */
 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
   struct si_shader_output_values *outputs,
   unsigned noutput, unsigned stream)
@@ -2498,21 +2498,21 @@ static void si_write_tess_factors(struct 
lp_build_tgsi_context *bld_base,
byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
  LLVMConstInt(ctx->i32, 4 * stride, 0), "");
 

[Mesa-dev] [PATCH 2/3] radeonsi: remove most uses of lp_build_const*

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_shader.c   | 270 ++---
 src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c  |   2 +-
 .../drivers/radeonsi/si_shader_tgsi_setup.c|  24 +-
 3 files changed, 145 insertions(+), 151 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 2da00f9..e514d61 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -166,26 +166,26 @@ static LLVMValueRef unpack_param(struct si_shader_context 
*ctx,
struct gallivm_state *gallivm = >gallivm;
LLVMValueRef value = LLVMGetParam(ctx->main_fn,
  param);
 
if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
value = bitcast(>bld_base,
TGSI_TYPE_UNSIGNED, value);
 
if (rshift)
value = LLVMBuildLShr(gallivm->builder, value,
- lp_build_const_int32(gallivm, rshift), 
"");
+ LLVMConstInt(ctx->i32, rshift, 0), "");
 
if (rshift + bitwidth < 32) {
unsigned mask = (1 << bitwidth) - 1;
value = LLVMBuildAnd(gallivm->builder, value,
-lp_build_const_int32(gallivm, mask), "");
+LLVMConstInt(ctx->i32, mask, 0), "");
}
 
return value;
 }
 
 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
 {
switch (ctx->type) {
case PIPE_SHADER_TESS_CTRL:
return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
@@ -304,21 +304,21 @@ static LLVMValueRef get_instance_index_for_fetch(
unsigned param_start_instance, unsigned divisor)
 {
struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
 
LLVMValueRef result = LLVMGetParam(ctx->main_fn,
   ctx->param_instance_id);
 
/* The division must be done before START_INSTANCE is added. */
if (divisor > 1)
result = LLVMBuildUDiv(gallivm->builder, result,
-   lp_build_const_int32(gallivm, divisor), "");
+   LLVMConstInt(ctx->i32, divisor, 0), "");
 
return LLVMBuildAdd(gallivm->builder, result,
LLVMGetParam(ctx->main_fn, param_start_instance), 
"");
 }
 
 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
  * to float. */
 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
LLVMValueRef vec4,
unsigned double_index)
@@ -348,21 +348,21 @@ static void declare_input_vs(
 
LLVMValueRef t_list_ptr;
LLVMValueRef t_offset;
LLVMValueRef t_list;
LLVMValueRef vertex_index;
LLVMValueRef input[3];
 
/* Load the T list */
t_list_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_VERTEX_BUFFERS);
 
-   t_offset = lp_build_const_int32(gallivm, input_index);
+   t_offset = LLVMConstInt(ctx->i32, input_index, 0);
 
t_list = ac_build_indexed_load_const(>ac, t_list_ptr, t_offset);
 
vertex_index = LLVMGetParam(ctx->main_fn,
ctx->param_vertex_index0 +
input_index);
 
fix_fetch = ctx->shader->key.mono.vs.fix_fetch[input_index];
 
/* Do multiple loads for special formats. */
@@ -393,21 +393,21 @@ static void declare_input_vs(
for (unsigned i = 0; i < num_fetches; i++) {
LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 
0);
 
input[i] = ac_build_buffer_load_format(>ac, t_list,
   vertex_index, voffset,
   true);
}
 
/* Break up the vec4 into individual components */
for (chan = 0; chan < 4; chan++) {
-   LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
+   LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
out[chan] = LLVMBuildExtractElement(gallivm->builder,
input[0], llvm_chan, "");
}
 
switch (fix_fetch) {
case SI_FIX_FETCH_A2_SNORM:
case SI_FIX_FETCH_A2_SSCALED:
case SI_FIX_FETCH_A2_SINT: {
/* The hardware returns an unsigned value; convert it to a
 * signed one.
@@ -573,21 +573,21 @@ static LLVMValueRef get_primitive_id(struct 
lp_build_tgsi_context *bld_base,
 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
   const struct tgsi_ind_register *ind,
   int 

[Mesa-dev] [PATCH] radeonsi: fix broken texture filtering on SIK-CIK since GFX9 changes

[Marek Olšák]

From: Marek Olšák 

Don't clear state[7] on SI-CIK, and only do the meta stuff on VI+.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100531
---
 src/gallium/drivers/radeonsi/si_descriptors.c | 32 ++-
 1 file changed, 17 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 2b91158..8f5a16b 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -397,40 +397,42 @@ void si_set_mutable_tex_desc_fields(struct si_screen 
*sscreen,
if (sscreen->b.chip_class >= GFX9) {
/* Only stencil_offset needs to be added here. */
if (is_stencil)
va += tex->surface.u.gfx9.stencil_offset;
else
va += tex->surface.u.gfx9.surf_offset;
} else {
va += base_level_info->offset;
}
 
-   if (vi_dcc_enabled(tex, first_level)) {
-   meta_va = (!tex->dcc_separate_buffer ? 
tex->resource.gpu_address : 0) +
- tex->dcc_offset;
-
-   if (sscreen->b.chip_class <= VI)
-   meta_va += base_level_info->dcc_offset;
-   } else if (tex->tc_compatible_htile && !is_stencil) {
-   meta_va = tex->htile_buffer->gpu_address;
-   }
-
state[0] = va >> 8;
state[1] &= C_008F14_BASE_ADDRESS_HI;
state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
 
-   state[6] &= C_008F28_COMPRESSION_EN;
-   state[7] = 0;
+   if (sscreen->b.chip_class >= VI) {
+   state[6] &= C_008F28_COMPRESSION_EN;
+   state[7] = 0;
 
-   if (meta_va) {
-   state[6] |= S_008F28_COMPRESSION_EN(1);
-   state[7] = meta_va >> 8;
+   if (vi_dcc_enabled(tex, first_level)) {
+   meta_va = (!tex->dcc_separate_buffer ? 
tex->resource.gpu_address : 0) +
+ tex->dcc_offset;
+
+   if (sscreen->b.chip_class <= VI)
+   meta_va += base_level_info->dcc_offset;
+   } else if (tex->tc_compatible_htile && !is_stencil) {
+   meta_va = tex->htile_buffer->gpu_address;
+   }
+
+   if (meta_va) {
+   state[6] |= S_008F28_COMPRESSION_EN(1);
+   state[7] = meta_va >> 8;
+   }
}
 
if (sscreen->b.chip_class >= GFX9) {
state[3] &= C_008F1C_SW_MODE;
state[4] &= C_008F20_PITCH_GFX9;
 
if (is_stencil) {
state[3] |= 
S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
state[4] |= 
S_008F20_PITCH_GFX9(tex->surface.u.gfx9.stencil.epitch);
} else {
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 19/19] radeonsi: enable ARB_shader_ballot

[Marek Olšák]

For the series:

Reviewed-by: Marek Olšák 

Marek

On Fri, Mar 31, 2017 at 7:14 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> Require LLVM 5.0 or later because LLVM 4.0 is easily fooled into
> putting the lane select of llvm.amdgcn.readlane into a VGPR and then
> fails to continue to compile.
> ---
>  docs/features.txt  | 2 +-
>  docs/relnotes/17.1.0.html  | 1 +
>  src/gallium/drivers/radeonsi/si_pipe.c | 4 +++-
>  3 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/docs/features.txt b/docs/features.txt
> index 1e145e1..662fbd2 100644
> --- a/docs/features.txt
> +++ b/docs/features.txt
> @@ -285,21 +285,21 @@ Khronos, ARB, and OES extensions that are not part of 
> any OpenGL or OpenGL ES ve
>GL_ARB_gl_spirv   not started
>GL_ARB_gpu_shader_int64   DONE (i965/gen8+, 
> nvc0, radeonsi, softpipe, llvmpipe)
>GL_ARB_indirect_parametersDONE (nvc0, radeonsi)
>GL_ARB_parallel_shader_compilenot started, but 
> Chia-I Wu did some related work in 2014
>GL_ARB_pipeline_statistics_query  DONE (i965, nvc0, 
> radeonsi, softpipe, swr)
>GL_ARB_post_depth_coverageDONE (i965)
>GL_ARB_robustness_isolation   not started
>GL_ARB_sample_locations   not started
>GL_ARB_seamless_cubemap_per_texture   DONE (i965, nvc0, 
> radeonsi, r600, softpipe, swr)
>GL_ARB_shader_atomic_counter_ops  DONE (i965/gen7+, 
> nvc0, radeonsi, softpipe)
> -  GL_ARB_shader_ballot  not started
> +  GL_ARB_shader_ballot  DONE (radeonsi)
>GL_ARB_shader_clock   DONE (i965/gen7+, 
> radeonsi)
>GL_ARB_shader_draw_parameters DONE (i965, nvc0, 
> radeonsi)
>GL_ARB_shader_group_vote  DONE (nvc0, radeonsi)
>GL_ARB_shader_stencil_export  DONE (i965/gen9+, 
> radeonsi, softpipe, llvmpipe, swr)
>GL_ARB_shader_viewport_layer_arrayDONE (i965/gen6+)
>GL_ARB_sparse_buffer  not started
>GL_ARB_sparse_texture not started
>GL_ARB_sparse_texture2not started
>GL_ARB_sparse_texture_clamp   not started
>GL_ARB_texture_filter_minmax  not started
> diff --git a/docs/relnotes/17.1.0.html b/docs/relnotes/17.1.0.html
> index a11a37f..27595f5 100644
> --- a/docs/relnotes/17.1.0.html
> +++ b/docs/relnotes/17.1.0.html
> @@ -38,20 +38,21 @@ TBD.
>
>
>  New features
>
>  
>  Note: some of the new features are only available with certain drivers.
>  
>
>  
>  GL_ARB_gpu_shader_int64 on i965/gen8+, nvc0, radeonsi, softpipe, 
> llvmpipe
> +GL_ARB_shader_ballot on radeonsi
>  GL_ARB_shader_clock on radeonsi
>  GL_ARB_shader_group_vote on radeonsi
>  GL_ARB_transform_feedback2 on i965/gen6
>  GL_ARB_transform_feedback_overflow_query on i965/gen6+
>  Geometry shaders enabled on swr
>  
>
>  Bug fixes
>
>  
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
> b/src/gallium/drivers/radeonsi/si_pipe.c
> index 9388eb9..e647d3e 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -420,20 +420,23 @@ static int si_get_param(struct pipe_screen* pscreen, 
> enum pipe_cap param)
> return 1;
>
> case PIPE_CAP_INT64:
> case PIPE_CAP_INT64_DIVMOD:
> case PIPE_CAP_TGSI_CLOCK:
> return HAVE_LLVM >= 0x0309;
>
> case PIPE_CAP_TGSI_VOTE:
> return HAVE_LLVM >= 0x0400;
>
> +   case PIPE_CAP_TGSI_BALLOT:
> +   return HAVE_LLVM >= 0x0500;
> +
> case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
> return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
>
> case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
> return (sscreen->b.info.drm_major == 2 &&
> sscreen->b.info.drm_minor >= 43) ||
>sscreen->b.info.drm_major == 3;
>
> case PIPE_CAP_TEXTURE_MULTISAMPLE:
> /* 2D tiling on CIK is supported since DRM 2.35.0 */
> @@ -481,21 +484,20 @@ static int si_get_param(struct pipe_screen* pscreen, 
> enum pipe_cap param)
> case PIPE_CAP_USER_VERTEX_BUFFERS:
> case PIPE_CAP_FAKE_SW_MSAA:
> case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
> case PIPE_CAP_VERTEXID_NOBASE:
> case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
> case PIPE_CAP_MAX_WINDOW_RECTANGLES:
> case PIPE_CAP_NATIVE_FENCE_FD:
> case PIPE_CAP_TGSI_FS_FBFETCH:
> case 

Re: [Mesa-dev] [PATCH 1/2] glsl/shader_cache: Fix memory leak

[Timothy Arceri]

On 03/04/17 09:52, Timothy Arceri wrote:



On 03/04/17 03:31, Bartosz Tomczyk wrote:

---
 src/compiler/glsl/shader_cache.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/compiler/glsl/shader_cache.cpp
b/src/compiler/glsl/shader_cache.cpp
index ea1bc01f02..8c42a95664 100644
--- a/src/compiler/glsl/shader_cache.cpp
+++ b/src/compiler/glsl/shader_cache.cpp
@@ -1273,6 +1273,8 @@ shader_cache_write_program_metadata(struct
gl_context *ctx,

disk_cache_put(cache, prog->data->sha1, metadata->data,
metadata->size);

+   if(metadata->data)
+  free(metadata->data);
free(metadata);


Thanks. This was my mistake in df1d5fc44218834 when changing from using
ralloc.

I think I would rather see a new helper added to blob.h

static inline void
blob_destroy(struct blob *blob)
{
   free(metadata->data);
   free(metadata);
}




Oh and please update blob_test.c to use the new helper also.
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Re: [Mesa-dev] [PATCH 1/2] glsl/shader_cache: Fix memory leak

[Timothy Arceri]

On 03/04/17 03:31, Bartosz Tomczyk wrote:

---
 src/compiler/glsl/shader_cache.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/compiler/glsl/shader_cache.cpp 
b/src/compiler/glsl/shader_cache.cpp
index ea1bc01f02..8c42a95664 100644
--- a/src/compiler/glsl/shader_cache.cpp
+++ b/src/compiler/glsl/shader_cache.cpp
@@ -1273,6 +1273,8 @@ shader_cache_write_program_metadata(struct gl_context 
*ctx,

disk_cache_put(cache, prog->data->sha1, metadata->data, metadata->size);

+   if(metadata->data)
+  free(metadata->data);
free(metadata);


Thanks. This was my mistake in df1d5fc44218834 when changing from using 
ralloc.


I think I would rather see a new helper added to blob.h

static inline void
blob_destroy(struct blob *blob)
{
   free(metadata->data);
   free(metadata);
}




if (ctx->_Shader->Flags & GLSL_CACHE_INFO) {


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Re: [Mesa-dev] [PATCH] amd/addrlib: fix optimized build warnings

[Marek Olšák]

Pushed. Thanks.

Marek

On Sun, Apr 2, 2017 at 7:22 PM, Grazvydas Ignotas  wrote:
> All the -Wunused-but-set-variable ones.
> Found a way to do it with a oneliner.
>
> Signed-off-by: Grazvydas Ignotas 
> ---
> no commit access (currently pending)
>
>  src/amd/addrlib/core/addrcommon.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/amd/addrlib/core/addrcommon.h 
> b/src/amd/addrlib/core/addrcommon.h
> index 3911d79..66424a8 100644
> --- a/src/amd/addrlib/core/addrcommon.h
> +++ b/src/amd/addrlib/core/addrcommon.h
> @@ -66,11 +66,11 @@
>  // Debug assertions used in AddrLib
>  
> 
>  #if defined(_WIN32) && (_MSC_VER >= 1400)
>  #define ADDR_ANALYSIS_ASSUME(expr) __analysis_assume(expr)
>  #else
> -#define ADDR_ANALYSIS_ASSUME(expr) do { } while (0)
> +#define ADDR_ANALYSIS_ASSUME(expr) do { (void)(expr); } while (0)
>  #endif
>
>  #if DEBUG
>  #define ADDR_ASSERT(__e)\
>  do {\
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH] radeonsi: use unreachable to fix a warning

[Marek Olšák]

Pushed. Thanks.

Marek

On Sun, Apr 2, 2017 at 7:22 PM, Grazvydas Ignotas  wrote:
> si_state.c: In function ‘si_make_texture_descriptor’:
> si_state.c:3240:25: warning: ‘num_format’ may be used uninitialized
> si_state.c:3240:12: warning: ‘data_format’ may be used uninitialized
>
> Signed-off-by: Grazvydas Ignotas 
> ---
> no commit access (currently pending)
>
>  src/gallium/drivers/radeonsi/si_state.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state.c 
> b/src/gallium/drivers/radeonsi/si_state.c
> index 35fadec..4a6b615 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -3252,11 +3252,11 @@ si_make_texture_descriptor(struct si_screen *screen,
> break;
> case 8:
> num_format = V_008F14_IMG_FMASK_32_8_8;
> break;
> default:
> -   assert(0);
> +   unreachable("invalid nr_samples");
> }
> } else {
> switch (res->nr_samples) {
> case 2:
> data_format = 
> V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
> @@ -3266,11 +3266,11 @@ si_make_texture_descriptor(struct si_screen *screen,
> break;
> case 8:
> data_format = 
> V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
> break;
> default:
> -   assert(0);
> +   unreachable("invalid nr_samples");
> }
> num_format = V_008F14_IMG_NUM_FORMAT_UINT;
> }
>
> fmask_state[0] = va >> 8;
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH] gallium: fix some math formulas to display better

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Sun, Apr 2, 2017 at 6:02 PM, Ilia Mirkin  wrote:
> Signed-off-by: Ilia Mirkin 
> ---
>  src/gallium/docs/source/tgsi.rst | 32 
>  1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/src/gallium/docs/source/tgsi.rst 
> b/src/gallium/docs/source/tgsi.rst
> index 05b06ce..ca31924 100644
> --- a/src/gallium/docs/source/tgsi.rst
> +++ b/src/gallium/docs/source/tgsi.rst
> @@ -1204,13 +1204,13 @@ Support for these opcodes indicated by 
> PIPE_SHADER_CAP_INTEGERS (all of them?)
>
>  .. math::
>
> -  dst.x = src0.x \ src1.x
> +  dst.x = \frac{src0.x}{src1.x}
>
> -  dst.y = src0.y \ src1.y
> +  dst.y = \frac{src0.y}{src1.y}
>
> -  dst.z = src0.z \ src1.z
> +  dst.z = \frac{src0.z}{src1.z}
>
> -  dst.w = src0.w \ src1.w
> +  dst.w = \frac{src0.w}{src1.w}
>
>
>  .. opcode:: UDIV - Unsigned Integer Division
> @@ -1219,13 +1219,13 @@ Support for these opcodes indicated by 
> PIPE_SHADER_CAP_INTEGERS (all of them?)
>
>  .. math::
>
> -  dst.x = src0.x \ src1.x
> +  dst.x = \frac{src0.x}{src1.x}
>
> -  dst.y = src0.y \ src1.y
> +  dst.y = \frac{src0.y}{src1.y}
>
> -  dst.z = src0.z \ src1.z
> +  dst.z = \frac{src0.z}{src1.z}
>
> -  dst.w = src0.w \ src1.w
> +  dst.w = \frac{src0.w}{src1.w}
>
>
>  .. opcode:: UMOD - Unsigned Integer Remainder
> @@ -1234,13 +1234,13 @@ Support for these opcodes indicated by 
> PIPE_SHADER_CAP_INTEGERS (all of them?)
>
>  .. math::
>
> -  dst.x = src0.x \ src1.x
> +  dst.x = src0.x \bmod src1.x
>
> -  dst.y = src0.y \ src1.y
> +  dst.y = src0.y \bmod src1.y
>
> -  dst.z = src0.z \ src1.z
> +  dst.z = src0.z \bmod src1.z
>
> -  dst.w = src0.w \ src1.w
> +  dst.w = src0.w \bmod src1.w
>
>
>  .. opcode:: NOT - Bitwise Not
> @@ -2259,17 +2259,17 @@ two-component vectors with 64-bits in each component.
>
>  .. math::
>
> -  dst.xy = src0.xy \ src1.xy
> +  dst.xy = \frac{src0.xy}{src1.xy}
>
> -  dst.zw = src0.zw \ src1.zw
> +  dst.zw = \frac{src0.zw}{src1.zw}
>
>  .. opcode:: U64DIV - 64-bit Unsigned Integer Division
>
>  .. math::
>
> -  dst.xy = src0.xy \ src1.xy
> +  dst.xy = \frac{src0.xy}{src1.xy}
>
> -  dst.zw = src0.zw \ src1.zw
> +  dst.zw = \frac{src0.zw}{src1.zw}
>
>  .. opcode:: U64MOD - 64-bit Unsigned Integer Remainder
>
> --
> 2.10.2
>
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Re: [Mesa-dev] [PATCH v3 1/2] st/mesa: add st_convert_image()

[Marek Olšák]

For the series:

Reviewed-by: Marek Olšák 

Marek

On Fri, Mar 31, 2017 at 12:48 PM, Samuel Pitoiset
 wrote:
> Should be used by the state tracker when glGetImageHandleARB()
> is called in order to create a pipe_image_view template.
>
> v3: - move the comment to *.c
> v2: - make 'st' const
> - describe the function
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/mesa/state_tracker/st_atom_image.c | 106 
> ++---
>  src/mesa/state_tracker/st_texture.h|   4 ++
>  2 files changed, 63 insertions(+), 47 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_atom_image.c 
> b/src/mesa/state_tracker/st_atom_image.c
> index 5dd2cd64f9..6295e8d2cd 100644
> --- a/src/mesa/state_tracker/st_atom_image.c
> +++ b/src/mesa/state_tracker/st_atom_image.c
> @@ -44,6 +44,64 @@
>  #include "st_program.h"
>  #include "st_format.h"
>
> +/**
> + * Convert a gl_image_unit object to a pipe_image_view object.
> + */
> +void
> +st_convert_image(const struct st_context *st, const struct gl_image_unit *u,
> + struct pipe_image_view *img)
> +{
> +   struct st_texture_object *stObj = st_texture_object(u->TexObj);
> +
> +   img->resource = stObj->pt;
> +   img->format = st_mesa_format_to_pipe_format(st, u->_ActualFormat);
> +
> +   switch (u->Access) {
> +   case GL_READ_ONLY:
> +  img->access = PIPE_IMAGE_ACCESS_READ;
> +  break;
> +   case GL_WRITE_ONLY:
> +  img->access = PIPE_IMAGE_ACCESS_WRITE;
> +  break;
> +   case GL_READ_WRITE:
> +  img->access = PIPE_IMAGE_ACCESS_READ_WRITE;
> +  break;
> +   default:
> +  unreachable("bad gl_image_unit::Access");
> +   }
> +
> +   if (stObj->pt->target == PIPE_BUFFER) {
> +  unsigned base, size;
> +
> +  base = stObj->base.BufferOffset;
> +  assert(base < stObj->pt->width0);
> +  size = MIN2(stObj->pt->width0 - base, 
> (unsigned)stObj->base.BufferSize);
> +
> +  img->u.buf.offset = base;
> +  img->u.buf.size = size;
> +   } else {
> +  img->u.tex.level = u->Level + stObj->base.MinLevel;
> +  if (stObj->pt->target == PIPE_TEXTURE_3D) {
> + if (u->Layered) {
> +img->u.tex.first_layer = 0;
> +img->u.tex.last_layer = u_minify(stObj->pt->depth0, 
> img->u.tex.level) - 1;
> + } else {
> +img->u.tex.first_layer = u->_Layer;
> +img->u.tex.last_layer = u->_Layer;
> + }
> +  } else {
> + img->u.tex.first_layer = u->_Layer + stObj->base.MinLayer;
> + img->u.tex.last_layer = u->_Layer + stObj->base.MinLayer;
> + if (u->Layered && img->resource->array_size > 1) {
> +if (stObj->base.Immutable)
> +   img->u.tex.last_layer += stObj->base.NumLayers - 1;
> +else
> +   img->u.tex.last_layer += img->resource->array_size - 1;
> + }
> +  }
> +   }
> +}
> +
>  static void
>  st_bind_images(struct st_context *st, struct gl_program *prog,
> enum pipe_shader_type shader_type)
> @@ -70,53 +128,7 @@ st_bind_images(struct st_context *st, struct gl_program 
> *prog,
>   continue;
>}
>
> -  img->resource = stObj->pt;
> -  img->format = st_mesa_format_to_pipe_format(st, u->_ActualFormat);
> -
> -  switch (u->Access) {
> -  case GL_READ_ONLY:
> - img->access = PIPE_IMAGE_ACCESS_READ;
> - break;
> -  case GL_WRITE_ONLY:
> - img->access = PIPE_IMAGE_ACCESS_WRITE;
> - break;
> -  case GL_READ_WRITE:
> - img->access = PIPE_IMAGE_ACCESS_READ_WRITE;
> - break;
> -  default:
> - unreachable("bad gl_image_unit::Access");
> -  }
> -
> -  if (stObj->pt->target == PIPE_BUFFER) {
> - unsigned base, size;
> -
> - base = stObj->base.BufferOffset;
> - assert(base < stObj->pt->width0);
> - size = MIN2(stObj->pt->width0 - base, 
> (unsigned)stObj->base.BufferSize);
> -
> - img->u.buf.offset = base;
> - img->u.buf.size = size;
> -  } else {
> - img->u.tex.level = u->Level + stObj->base.MinLevel;
> - if (stObj->pt->target == PIPE_TEXTURE_3D) {
> -if (u->Layered) {
> -   img->u.tex.first_layer = 0;
> -   img->u.tex.last_layer = u_minify(stObj->pt->depth0, 
> img->u.tex.level) - 1;
> -} else {
> -   img->u.tex.first_layer = u->_Layer;
> -   img->u.tex.last_layer = u->_Layer;
> -}
> - } else {
> -img->u.tex.first_layer = u->_Layer + stObj->base.MinLayer;
> -img->u.tex.last_layer = u->_Layer + stObj->base.MinLayer;
> -if (u->Layered && img->resource->array_size > 1) {
> -   if (stObj->base.Immutable)
> -  img->u.tex.last_layer += stObj->base.NumLayers - 1;
> -   else
> -  img->u.tex.last_layer += img->resource->array_size - 1;
> -   

Re: [Mesa-dev] [PATCH 4/5] r600g: use a clever alignment for index buffer uploads

[Marek Olšák]

Pushed, thanks.

Marek

On Sat, Apr 1, 2017 at 10:55 AM, Constantine Kharlamov
 wrote:
> Thank you, please, could you push them too? I don't have commit access.
>
> On 28.03.2017 22:36, Marek Olšák wrote:
>> Actually nevermind.
>>
>> Patches 1-3:
>> Reviewed-by: Marek Olšák 
>>
>> Patches 4-5:
>> These have no effect, because r600g hw doesn't use TC for index fetches.
>>
>> Marek
>>
>>
>> On Tue, Mar 28, 2017 at 9:33 PM, Marek Olšák  wrote:
>>> BTW, I don't know if tcc_cache_line_size has the correct value for
>>> pre-GCN chips.
>>>
>>> Marek
>>>
>>> On Sun, Mar 26, 2017 at 5:36 PM, Constantine Kharlamov
>>>  wrote:
 Stolen from radeonsi

 Signed-off-by: Constantine Kharlamov 
 ---
  src/gallium/drivers/r600/r600_state_common.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

 diff --git a/src/gallium/drivers/r600/r600_state_common.c 
 b/src/gallium/drivers/r600/r600_state_common.c
 index 961e04e9db..5293c4034f 100644
 --- a/src/gallium/drivers/r600/r600_state_common.c
 +++ b/src/gallium/drivers/r600/r600_state_common.c
 @@ -1766,7 +1766,8 @@ static void r600_draw_vbo(struct pipe_context *ctx, 
 const struct pipe_draw_info
  info->instance_count > 1 
 ||
  info->count*ib.index_size 
 > 20)) {
 u_upload_data(ctx->stream_uploader, 0,
 -  info->count * ib.index_size, 256,
 + info->count * ib.index_size,
 + 
 rctx->screen->b.info.tcc_cache_line_size,
   ib.user_buffer, , 
 );
 ib.user_buffer = NULL;
 }
 --
 2.12.0

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Re: [Mesa-dev] [PATCH] radv: Rework guard band calculation.

[Dave Airlie]

On 2 April 2017 at 22:43, Bas Nieuwenhuizen  wrote:
> We want the guardband_x/y to be the largerst scalars such that each
> viewport scaled by that amount is still a subrange of [-32767, 32767].
>
> The old code has a couple of issues:
> 1) It used scissor instead of viewport_scissor, potentially taking into
>account a viewport that is too small and therefore selecting a scale
>that is too large.
> 2) Merging the viewports isn't ideal, as for example viewports with
>boundaries [0,1] and [1000, 1001] would allow a guardband scale of ~30k,
>while their union [0, 1001] only allows a scale of ~32.
>
> The new code just determines the guardband per viewport and takes the minimum.
>
> Signed-off-by: Bas Nieuwenhuizen 

I'm not sure I understand guardband enough to say I know what this is doing,

Acked-by: Dave Airlie 

> ---
>  src/amd/vulkan/si_cmd_buffer.c | 52 
> ++
>  1 file changed, 12 insertions(+), 40 deletions(-)
>
> diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
> index e176abe3869..bbcaf1009bd 100644
> --- a/src/amd/vulkan/si_cmd_buffer.c
> +++ b/src/amd/vulkan/si_cmd_buffer.c
> @@ -504,22 +504,6 @@ get_viewport_xform(const VkViewport *viewport,
> translate[2] = n;
>  }
>
> -static void
> -get_viewport_xform_scissor(const VkRect2D *scissor,
> -   float scale[2], float translate[2])
> -{
> -   float x = scissor->offset.x;
> -   float y = scissor->offset.y;
> -   float half_width = 0.5f * scissor->extent.width;
> -   float half_height = 0.5f * scissor->extent.height;
> -
> -   scale[0] = half_width;
> -   translate[0] = half_width + x;
> -   scale[1] = half_height;
> -   translate[1] = half_height + y;
> -
> -}
> -
>  void
>  si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
>int count, const VkViewport *viewports)
> @@ -579,26 +563,13 @@ static VkRect2D si_intersect_scissor(const VkRect2D *a, 
> const VkRect2D *b) {
> return ret;
>  }
>
> -static VkRect2D si_union_scissor(const VkRect2D *a, const VkRect2D *b) {
> -   VkRect2D ret;
> -   ret.offset.x = MIN2(a->offset.x, b->offset.x);
> -   ret.offset.y = MIN2(a->offset.y, b->offset.y);
> -   ret.extent.width = MAX2(a->offset.x + a->extent.width,
> -   b->offset.x + b->extent.width) - ret.offset.x;
> -   ret.extent.height = MAX2(a->offset.y + a->extent.height,
> -b->offset.y + b->extent.height) - 
> ret.offset.y;
> -   return ret;
> -}
> -
> -
>  void
>  si_write_scissors(struct radeon_winsys_cs *cs, int first,
>int count, const VkRect2D *scissors,
>const VkViewport *viewports, bool can_use_guardband)
>  {
> int i;
> -   VkRect2D merged;
> -   float scale[2], translate[2], guardband_x = 1.0, guardband_y = 1.0;
> +   float scale[3], translate[3], guardband_x = INFINITY, guardband_y = 
> INFINITY;
> const float max_range = 32767.0f;
> assert(count);
>
> @@ -607,10 +578,14 @@ si_write_scissors(struct radeon_winsys_cs *cs, int 
> first,
> VkRect2D viewport_scissor = 
> si_scissor_from_viewport(viewports + i);
> VkRect2D scissor = si_intersect_scissor([i], 
> _scissor);
>
> -   if (i)
> -   merged = si_union_scissor(, );
> -   else
> -   merged = scissor;
> +   get_viewport_xform(viewports + i, scale, translate);
> +   if (scale[0] < 0.5)
> +   scale[0] = 0.5;
> +   if (scale[1] < 0.5)
> +   scale[1] = 0.5;
> +
> +   guardband_x = MIN2(guardband_x, (max_range - 
> abs(translate[0])) / scale[0]);
> +   guardband_y = MIN2(guardband_y, (max_range - 
> abs(translate[1])) / scale[1]);
>
> radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
> S_028250_TL_Y(scissor.offset.y) |
> @@ -618,12 +593,9 @@ si_write_scissors(struct radeon_winsys_cs *cs, int first,
> radeon_emit(cs, S_028254_BR_X(scissor.offset.x + 
> scissor.extent.width) |
> S_028254_BR_Y(scissor.offset.y + 
> scissor.extent.height));
> }
> -
> -   get_viewport_xform_scissor(, scale, translate);
> -
> -   if (can_use_guardband) {
> -   guardband_x = (max_range - abs(translate[0])) / scale[0];
> -   guardband_y = (max_range - abs(translate[1])) / scale[1];
> +   if (!can_use_guardband) {
> +   guardband_x = 1.0;
> +   guardband_y = 1.0;
> }
>
> radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
> --
> 2.12.1
>
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Re: [Mesa-dev] [PATCH] travis: remove r600 as it requires llvm 3.8

[Dave Airlie]

On 3 April 2017 at 06:44, Rhys Kidd  wrote:
> On 2 April 2017 at 08:42, Christian Gmeiner 
> wrote:
>>
>> At the moment travis ci failes with the following error:
>>
>> checking for RADEON... yes
>> checking for RADEON... yes
>> configure: error: LLVM 3.8.0 or newer is required for r600
>> make: *** No targets specified and no makefile found.  Stop.
>>
>> Signed-off-by: Christian Gmeiner 
>
>
> NACK.
>
> I'll send out to the mailing list shortly a patch that enables LLVM 3.8+ on
> Travis-CI's Trusty-based environment that we use.
>
> Allows r600g to remain and should theoretically allow radeonsi to be tested
> as well. Possibly the vulkan drivers and swr too without a great deal
> further work.

FYI, radv is llvm 3.9+.

Dave.
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[Mesa-dev] [PATCH] travis: Support LLVM 3.8+ on Trusty-based Travis-CI via apt-get not apt addon

[Rhys Kidd]

Per comments by Travis-CI, the apt addon is only really needed for the
container-based Precise builds, as they don't yet support Trusty on that 
platform.

Mesa currently uses Trusty fully-virtualized environment (due to sudo: 
required).

See further:
https://docs.travis-ci.com/user/trusty-ci-environment/#Fully-virtualized-via-sudo%3A-required
https://github.com/travis-ci/apt-source-whitelist/pull/205#issuecomment-216054237

Signed-off-by: Rhys Kidd 
---
 .travis.yml | 20 +++-
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index a3b094f..aa212b1 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -1,6 +1,6 @@
 language: c
 
-sudo: true
+sudo: required
 dist: trusty
 
 cache:
@@ -15,11 +15,9 @@ addons:
   - libexpat1-dev
   - libxcb-dri2-0-dev
   - libx11-xcb-dev
-  - llvm-3.5-dev
-  # llvm-config is not in the dev package?
-  - llvm-3.5
-  # LLVM packaging is broken and misses this dep.
+  # LLVM packaging is broken and misses these dependencies
   - libedit-dev
+  - libelf-dev
   - scons
 
 env:
@@ -36,6 +34,9 @@ env:
 - XCBPROTO_VERSION=xcb-proto-1.11
 - LIBXCB_VERSION=libxcb-1.11
 - LIBXSHMFENCE_VERSION=libxshmfence-1.2
+- LLVM_VERSION=3.9
+- LLVM_PACKAGE="llvm-${LLVM_VERSION} llvm-${LLVM_VERSION}-dev"
+- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
 - PKG_CONFIG_PATH=$HOME/prefix/lib/pkgconfig
 - MAKEFLAGS=-j2
   matrix:
@@ -99,6 +100,15 @@ install:
   - tar -jxvf $LIBXSHMFENCE_VERSION.tar.bz2
   - (cd $LIBXSHMFENCE_VERSION && ./configure --prefix=$HOME/prefix && make 
install)
 
+  # Install LLVM directly via apt-get (not Travis-CI's apt addon)
+  # See 
https://github.com/travis-ci/apt-source-whitelist/pull/205#issuecomment-216054237
+
+  - wget -nv -O - http://llvm.org/apt/llvm-snapshot.gpg.key | sudo apt-key add 
-
+  - sudo apt-add-repository -y 'deb http://llvm.org/apt/trusty 
llvm-toolchain-trusty-3.9 main'
+  - sudo apt-add-repository -y 'deb http://llvm.org/apt/trusty 
llvm-toolchain-trusty main'
+  - sudo apt-get update -qq
+  - sudo apt-get install -qq -y $LLVM_PACKAGE
+
 script:
   - if test "x$BUILD" = xmake; then
   ./autogen.sh --enable-debug
-- 
2.9.3

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Re: [Mesa-dev] [PATCH] travis: remove r600 as it requires llvm 3.8

[Rhys Kidd]

On 2 April 2017 at 08:42, Christian Gmeiner 
wrote:

> At the moment travis ci failes with the following error:
>
> checking for RADEON... yes
> checking for RADEON... yes
> configure: error: LLVM 3.8.0 or newer is required for r600
> make: *** No targets specified and no makefile found.  Stop.
>
> Signed-off-by: Christian Gmeiner 
>

NACK.

I'll send out to the mailing list shortly a patch that enables LLVM 3.8+ on
Travis-CI's Trusty-based environment that we use.

Allows r600g to remain and should theoretically allow radeonsi to be tested
as well. Possibly the vulkan drivers and swr too without a great deal
further work.


> ---
>  .travis.yml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/.travis.yml b/.travis.yml
> index a3b094f..b94d421 100644
> --- a/.travis.yml
> +++ b/.travis.yml
> @@ -104,7 +104,7 @@ script:
>./autogen.sh --enable-debug
>  --with-egl-platforms=x11,drm
>  --with-dri-drivers=i915,i965,radeon,r200,swrast,nouveau
> ---with-gallium-drivers=i915,nouveau,r300,r600,freedreno,
> svga,swrast,vc4,virgl,etnaviv,imx
> +--with-gallium-drivers=i915,nouveau,r300,freedreno,svga,
> swrast,vc4,virgl,etnaviv,imx
>  --disable-llvm-shared-libs
>  ;
>make && make check;
> --
> 2.9.3
>
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Re: [Mesa-dev] [PATCH 1/2] glsl/shader_cache: Fix memory leak

[Grazvydas Ignotas]

On Sun, Apr 2, 2017 at 8:31 PM, Bartosz Tomczyk  wrote:

> ---
>  src/compiler/glsl/shader_cache.cpp | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/src/compiler/glsl/shader_cache.cpp
> b/src/compiler/glsl/shader_cache.cpp
> index ea1bc01f02..8c42a95664 100644
> --- a/src/compiler/glsl/shader_cache.cpp
> +++ b/src/compiler/glsl/shader_cache.cpp
> @@ -1273,6 +1273,8 @@ shader_cache_write_program_metadata(struct
> gl_context *ctx,
>
> disk_cache_put(cache, prog->data->sha1, metadata->data,
> metadata->size);
>
> +   if(metadata->data)
> +  free(metadata->data);
>

Please add a space after 'if' to match the style of all other code or drop
the NULL check altogether as free(NULL) is fine. With that:
Reviewed-by: Grazvydas Ignotas 
for both patches.
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[Mesa-dev] [PATCH 9/9] gallium: decrease the size of pipe_draw_info - 88 -> 80 bytes

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/auxiliary/indices/u_primconvert.c | 10 --
 src/gallium/include/pipe/p_state.h|  2 +-
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/gallium/auxiliary/indices/u_primconvert.c 
b/src/gallium/auxiliary/indices/u_primconvert.c
index 2bdfade..1ffca4b 100644
--- a/src/gallium/auxiliary/indices/u_primconvert.c
+++ b/src/gallium/auxiliary/indices/u_primconvert.c
@@ -121,39 +121,45 @@ util_primconvert_draw_vbo(struct primconvert_context *pc,
util_draw_init_info(_info);
new_info.indexed = true;
new_info.min_index = info->min_index;
new_info.max_index = info->max_index;
new_info.index_bias = info->index_bias;
new_info.start_instance = info->start_instance;
new_info.instance_count = info->instance_count;
new_info.primitive_restart = info->primitive_restart;
new_info.restart_index = info->restart_index;
if (info->indexed) {
+  enum pipe_prim_type mode = 0;
+
   u_index_translator(pc->primtypes_mask,
  info->mode, pc->saved_ib.index_size, info->count,
  pc->api_pv, pc->api_pv,
  info->primitive_restart ? PR_ENABLE : PR_DISABLE,
- _info.mode, _ib.index_size, _info.count,
+ , _ib.index_size, _info.count,
  _func);
+  new_info.mode = mode;
   src = ib->user_buffer;
   if (!src) {
  src = pipe_buffer_map(pc->pipe, ib->buffer,
PIPE_TRANSFER_READ, _transfer);
   }
   src = (const uint8_t *)src + ib->offset;
}
else {
+  enum pipe_prim_type mode = 0;
+
   u_index_generator(pc->primtypes_mask,
 info->mode, info->start, info->count,
 pc->api_pv, pc->api_pv,
-_info.mode, _ib.index_size, _info.count,
+, _ib.index_size, _info.count,
 _func);
+  new_info.mode = mode;
}
 
u_upload_alloc(pc->pipe->stream_uploader, 0, new_ib.index_size * 
new_info.count, 4,
   _ib.offset, _ib.buffer, );
 
if (info->indexed) {
   trans_func(src, info->start, info->count, new_info.count, 
info->restart_index, dst);
}
else {
   gen_func(info->start, new_info.count, dst);
diff --git a/src/gallium/include/pipe/p_state.h 
b/src/gallium/include/pipe/p_state.h
index d68a4d4..eeabf8b 100644
--- a/src/gallium/include/pipe/p_state.h
+++ b/src/gallium/include/pipe/p_state.h
@@ -634,21 +634,21 @@ struct pipe_index_buffer
const void *user_buffer;  /**< pointer to a user buffer if buffer == NULL */
 };
 
 
 /**
  * Information to describe a draw_vbo call.
  */
 struct pipe_draw_info
 {
boolean indexed;  /**< use index buffer */
-   enum pipe_prim_type mode;  /**< the mode of the primitive */
+   enum pipe_prim_type mode:8;  /**< the mode of the primitive */
boolean primitive_restart;
ubyte vertices_per_patch; /**< the number of vertices per patch */
 
unsigned start;  /**< the index of the first vertex */
unsigned count;  /**< number of vertices */
 
unsigned start_instance; /**< first instance id */
unsigned instance_count; /**< number of instances */
 
unsigned drawid; /**< id of this draw in a multidraw */
-- 
2.7.4

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[Mesa-dev] [PATCH 1/9] gallium: decrease the size of pipe_rasterizer_state - 36 -> 32 bytes

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/include/pipe/p_state.h | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/gallium/include/pipe/p_state.h 
b/src/gallium/include/pipe/p_state.h
index ce19b92..5d995dc 100644
--- a/src/gallium/include/pipe/p_state.h
+++ b/src/gallium/include/pipe/p_state.h
@@ -151,21 +151,27 @@ struct pipe_rasterizer_state
 * This applies to both user clip planes and shader clip distances.
 * Note that if the bound shader exports any clip distances, these
 * replace all user clip planes, and clip half-spaces enabled here
 * but not written by the shader count as disabled.
 */
unsigned clip_plane_enable:PIPE_MAX_CLIP_PLANES;
 
unsigned line_stipple_factor:8;  /**< [1..256] actually */
unsigned line_stipple_pattern:16;
 
-   uint32_t sprite_coord_enable; /* referring to 32 TEXCOORD/GENERIC inputs */
+   /**
+* Replace the given TEXCOORD inputs with point coordinates, max. 8 inputs.
+* If TEXCOORD (including PCOORD) are unsupported, replace GENERIC inputs
+* instead. Max. 9 inputs: 8x GENERIC to emulate TEXCOORD, and 1x GENERIC
+* to emulate PCOORD.
+*/
+   uint16_t sprite_coord_enable; /* 0-7: TEXCOORD/GENERIC, 8: PCOORD */
 
float line_width;
float point_size;   /**< used when no per-vertex size */
float offset_units;
float offset_scale;
float offset_clamp;
 };
 
 
 struct pipe_poly_stipple
-- 
2.7.4

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[Mesa-dev] [PATCH 7/9] gallium: decrease the size of pipe_resource - 64 -> 48 bytes

[Marek Olšák]

From: Marek Olšák 

Some other changes needed here.
---
 src/gallium/auxiliary/rbug/rbug_texture.c  |  4 ++--
 src/gallium/auxiliary/rbug/rbug_texture.h  |  4 ++--
 src/gallium/auxiliary/vl/vl_video_buffer.h |  2 +-
 src/gallium/drivers/rbug/rbug_core.c   |  2 +-
 src/gallium/include/pipe/p_state.h | 10 +-
 src/gallium/state_trackers/vdpau/surface.c |  8 +---
 src/mesa/state_tracker/st_cb_texture.c | 15 ++-
 src/mesa/state_tracker/st_texture.c| 17 +
 src/mesa/state_tracker/st_texture.h| 14 +++---
 9 files changed, 42 insertions(+), 34 deletions(-)

diff --git a/src/gallium/auxiliary/rbug/rbug_texture.c 
b/src/gallium/auxiliary/rbug/rbug_texture.c
index ca05147..3ee5e14 100644
--- a/src/gallium/auxiliary/rbug/rbug_texture.c
+++ b/src/gallium/auxiliary/rbug/rbug_texture.c
@@ -276,23 +276,23 @@ int rbug_send_texture_list_reply(struct rbug_connection 
*__con,
FREE(__data);
return __ret;
 }
 
 int rbug_send_texture_info_reply(struct rbug_connection *__con,
  uint32_t serial,
  uint32_t target,
  uint32_t format,
  uint32_t *width,
  uint32_t width_len,
- uint32_t *height,
+ uint16_t *height,
  uint32_t height_len,
- uint32_t *depth,
+ uint16_t *depth,
  uint32_t depth_len,
  uint32_t blockw,
  uint32_t blockh,
  uint32_t blocksize,
  uint32_t last_level,
  uint32_t nr_samples,
  uint32_t tex_usage,
  uint32_t *__serial)
 {
uint32_t __len = 0;
diff --git a/src/gallium/auxiliary/rbug/rbug_texture.h 
b/src/gallium/auxiliary/rbug/rbug_texture.h
index 59c9140..269e596 100644
--- a/src/gallium/auxiliary/rbug/rbug_texture.h
+++ b/src/gallium/auxiliary/rbug/rbug_texture.h
@@ -159,23 +159,23 @@ int rbug_send_texture_list_reply(struct rbug_connection 
*__con,
  rbug_texture_t *textures,
  uint32_t textures_len,
  uint32_t *__serial);
 
 int rbug_send_texture_info_reply(struct rbug_connection *__con,
  uint32_t serial,
  uint32_t target,
  uint32_t format,
  uint32_t *width,
  uint32_t width_len,
- uint32_t *height,
+ uint16_t *height,
  uint32_t height_len,
- uint32_t *depth,
+ uint16_t *depth,
  uint32_t depth_len,
  uint32_t blockw,
  uint32_t blockh,
  uint32_t blocksize,
  uint32_t last_level,
  uint32_t nr_samples,
  uint32_t tex_usage,
  uint32_t *__serial);
 
 int rbug_send_texture_read_reply(struct rbug_connection *__con,
diff --git a/src/gallium/auxiliary/vl/vl_video_buffer.h 
b/src/gallium/auxiliary/vl/vl_video_buffer.h
index 8a1c077..1dc47c8 100644
--- a/src/gallium/auxiliary/vl/vl_video_buffer.h
+++ b/src/gallium/auxiliary/vl/vl_video_buffer.h
@@ -42,21 +42,21 @@ struct vl_video_buffer
 {
struct pipe_video_buffer base;
unsigned num_planes;
struct pipe_resource *resources[VL_NUM_COMPONENTS];
struct pipe_sampler_view *sampler_view_planes[VL_NUM_COMPONENTS];
struct pipe_sampler_view *sampler_view_components[VL_NUM_COMPONENTS];
struct pipe_surface  *surfaces[VL_MAX_SURFACES];
 };
 
 static inline void
-vl_video_buffer_adjust_size(unsigned *width, unsigned *height, unsigned plane,
+vl_video_buffer_adjust_size(unsigned *width, uint16_t *height, unsigned plane,
 enum pipe_video_chroma_format chroma_format,
 bool interlaced)
 {
if (interlaced) {
   *height /= 2;
}
if (plane > 0) {
   if (chroma_format == PIPE_VIDEO_CHROMA_FORMAT_420) {
  *width /= 2;
  *height /= 2;
diff --git a/src/gallium/drivers/rbug/rbug_core.c 
b/src/gallium/drivers/rbug/rbug_core.c
index 64c2d63..82bcef8 100644
--- a/src/gallium/drivers/rbug/rbug_core.c
+++ b/src/gallium/drivers/rbug/rbug_core.c
@@ -198,21 +198,21 @@ rbug_texture_list(struct rbug_rbug 

[Mesa-dev] [PATCH 3/9] gallium: decrease the size of pipe_framebuffer_state - 96 -> 80 bytes

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/include/pipe/p_state.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/include/pipe/p_state.h 
b/src/gallium/include/pipe/p_state.h
index 54bcf07..62f5192 100644
--- a/src/gallium/include/pipe/p_state.h
+++ b/src/gallium/include/pipe/p_state.h
@@ -348,26 +348,26 @@ struct pipe_stencil_ref
 
 
 /**
  * Note that pipe_surfaces are "texture views for rendering"
  * and so in the case of ARB_framebuffer_no_attachment there
  * is no pipe_surface state available such that we may
  * extract the number of samples and layers.
  */
 struct pipe_framebuffer_state
 {
-   unsigned width, height;
-   unsigned samples; /**< Number of samples in a no-attachment framebuffer */
-   unsigned layers;  /**< Number of layers  in a no-attachment framebuffer */
+   uint16_t width, height;
+   uint16_t layers;  /**< Number of layers  in a no-attachment framebuffer */
+   ubyte samples; /**< Number of samples in a no-attachment framebuffer */
 
/** multiple color buffers for multiple render targets */
-   unsigned nr_cbufs;
+   ubyte nr_cbufs;
struct pipe_surface *cbufs[PIPE_MAX_COLOR_BUFS];
 
struct pipe_surface *zsbuf;  /**< Z/stencil buffer */
 };
 
 
 /**
  * Texture sampler state.
  */
 struct pipe_sampler_state
-- 
2.7.4

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[Mesa-dev] [PATCH 6/9] gallium: decrease the size of pipe_box - 24 -> 16 bytes

[Marek Olšák]

From: Marek Olšák 

Also:

pipe_transfer: 48 -> 40 bytes.
pipe_blit_info = 176 -> 160 bytes.
---
 src/gallium/include/pipe/p_state.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/include/pipe/p_state.h 
b/src/gallium/include/pipe/p_state.h
index 392bb8b..6a147ef 100644
--- a/src/gallium/include/pipe/p_state.h
+++ b/src/gallium/include/pipe/p_state.h
@@ -472,25 +472,25 @@ struct pipe_image_view
} u;
 };
 
 
 /**
  * Subregion of 1D/2D/3D image resource.
  */
 struct pipe_box
 {
int x;
-   int y;
-   int z;
+   int16_t y;
+   int16_t z;
int width;
-   int height;
-   int depth;
+   int16_t height;
+   int16_t depth;
 };
 
 
 /**
  * A memory object/resource such as a vertex buffer or texture.
  */
 struct pipe_resource
 {
struct pipe_reference reference;
struct pipe_screen *screen; /**< screen that this texture belongs to */
-- 
2.7.4

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[Mesa-dev] [PATCH 5/9] gallium: decrease the size of pipe_sampler_view - 48 -> 32 bytes

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/include/pipe/p_state.h | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/gallium/include/pipe/p_state.h 
b/src/gallium/include/pipe/p_state.h
index a4692b6..392bb8b 100644
--- a/src/gallium/include/pipe/p_state.h
+++ b/src/gallium/include/pipe/p_state.h
@@ -419,40 +419,40 @@ struct pipe_surface
union pipe_surface_desc u;
 };
 
 
 /**
  * A view into a texture that can be bound to a shader stage.
  */
 struct pipe_sampler_view
 {
struct pipe_reference reference;
-   enum pipe_texture_target target; /**< PIPE_TEXTURE_x */
-   enum pipe_format format;  /**< typed PIPE_FORMAT_x */
+   enum pipe_format format:16;  /**< typed PIPE_FORMAT_x */
+   enum pipe_texture_target target:4; /**< PIPE_TEXTURE_x */
+   unsigned swizzle_r:3; /**< PIPE_SWIZZLE_x for red component */
+   unsigned swizzle_g:3; /**< PIPE_SWIZZLE_x for green component */
+   unsigned swizzle_b:3; /**< PIPE_SWIZZLE_x for blue component */
+   unsigned swizzle_a:3; /**< PIPE_SWIZZLE_x for alpha component */
struct pipe_resource *texture; /**< texture into which this is a view  */
struct pipe_context *context; /**< context this view belongs to */
union {
   struct {
  unsigned first_layer:16;  /**< first layer to use for array textures 
*/
  unsigned last_layer:16;   /**< last layer to use for array textures */
  unsigned first_level:8;   /**< first mipmap level to use */
  unsigned last_level:8;/**< last mipmap level to use */
   } tex;
   struct {
  unsigned offset;   /**< offset in bytes */
  unsigned size; /**< size of the readable sub-range in bytes */
   } buf;
} u;
-   unsigned swizzle_r:3; /**< PIPE_SWIZZLE_x for red component */
-   unsigned swizzle_g:3; /**< PIPE_SWIZZLE_x for green component */
-   unsigned swizzle_b:3; /**< PIPE_SWIZZLE_x for blue component */
-   unsigned swizzle_a:3; /**< PIPE_SWIZZLE_x for alpha component */
 };
 
 
 /**
  * A description of a buffer or texture image that can be bound to a shader
  * stage.
  */
 struct pipe_image_view
 {
struct pipe_resource *resource; /**< resource into which this is a view  */
-- 
2.7.4

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[Mesa-dev] [PATCH 8/9] gallium: decrease the size of pipe_vertex_element - 16 -> 8 bytes

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/include/pipe/p_state.h | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/gallium/include/pipe/p_state.h 
b/src/gallium/include/pipe/p_state.h
index ae7f1c3..d68a4d4 100644
--- a/src/gallium/include/pipe/p_state.h
+++ b/src/gallium/include/pipe/p_state.h
@@ -599,33 +599,33 @@ struct pipe_stream_output_target
unsigned buffer_size;/**< how much data is allowed to be written */
 };
 
 
 /**
  * Information to describe a vertex attribute (position, color, etc)
  */
 struct pipe_vertex_element
 {
/** Offset of this attribute, in bytes, from the start of the vertex */
-   unsigned src_offset;
-
-   /** Instance data rate divisor. 0 means this is per-vertex data,
-*  n means per-instance data used for n consecutive instances (n > 0).
-*/
-   unsigned instance_divisor;
+   unsigned src_offset:16;
 
/** Which vertex_buffer (as given to pipe->set_vertex_buffer()) does
 * this attribute live in?
 */
-   unsigned vertex_buffer_index;
+   unsigned vertex_buffer_index:5;
 
-   enum pipe_format src_format;
+   enum pipe_format src_format:11;
+
+   /** Instance data rate divisor. 0 means this is per-vertex data,
+*  n means per-instance data used for n consecutive instances (n > 0).
+*/
+   unsigned instance_divisor;
 };
 
 
 /**
  * An index buffer.  When an index buffer is bound, all indices to vertices
  * will be looked up in the buffer.
  */
 struct pipe_index_buffer
 {
unsigned index_size;  /**< size of an index, in bytes */
-- 
2.7.4

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[Mesa-dev] [PATCH 4/9] gallium: decrease the size of pipe_surface - 48 -> 40 bytes

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/include/pipe/p_state.h | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/gallium/include/pipe/p_state.h 
b/src/gallium/include/pipe/p_state.h
index 62f5192..a4692b6 100644
--- a/src/gallium/include/pipe/p_state.h
+++ b/src/gallium/include/pipe/p_state.h
@@ -400,29 +400,28 @@ union pipe_surface_desc {
} buf;
 };
 
 /**
  * A view into a texture that can be bound to a color render target /
  * depth stencil attachment point.
  */
 struct pipe_surface
 {
struct pipe_reference reference;
+   enum pipe_format format:16;
+   unsigned writable:1;  /**< writable shader resource */
struct pipe_resource *texture; /**< resource into which this is a view  */
struct pipe_context *context; /**< context this surface belongs to */
-   enum pipe_format format;
 
/* XXX width/height should be removed */
-   unsigned width;   /**< logical width in pixels */
-   unsigned height;  /**< logical height in pixels */
-
-   unsigned writable:1;  /**< writable shader resource */
+   uint16_t width;   /**< logical width in pixels */
+   uint16_t height;  /**< logical height in pixels */
 
union pipe_surface_desc u;
 };
 
 
 /**
  * A view into a texture that can be bound to a shader stage.
  */
 struct pipe_sampler_view
 {
-- 
2.7.4

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[Mesa-dev] [PATCH 2/9] gallium: decrease the size of pipe_stream_output_info - 532 -> 268 bytes

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_pipe_common.h | 2 +-
 src/gallium/drivers/radeon/r600_streamout.c   | 2 +-
 src/gallium/include/pipe/p_state.h| 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 70b2836..fbd0ac7 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -479,21 +479,21 @@ struct r600_streamout {
 
unsignedenabled_mask;
unsignednum_targets;
struct r600_so_target   *targets[PIPE_MAX_SO_BUFFERS];
 
unsignedappend_bitmask;
boolsuspended;
 
/* External state which comes from the vertex shader,
 * it must be set explicitly when binding a shader. */
-   unsigned*stride_in_dw;
+   uint16_t*stride_in_dw;
unsignedenabled_stream_buffers_mask; /* stream0 
buffers0-3 in 4 LSB */
 
/* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
unsignedhw_enabled_mask;
 
/* The state of VGT_STRMOUT_(CONFIG|EN). */
struct r600_atomenable_atom;
boolstreamout_enabled;
boolprims_gen_query_enabled;
int num_prims_gen_queries;
diff --git a/src/gallium/drivers/radeon/r600_streamout.c 
b/src/gallium/drivers/radeon/r600_streamout.c
index b5296aa..a18089a 100644
--- a/src/gallium/drivers/radeon/r600_streamout.c
+++ b/src/gallium/drivers/radeon/r600_streamout.c
@@ -180,21 +180,21 @@ static void r600_flush_vgt_streamout(struct 
r600_common_context *rctx)
radeon_emit(cs, 0);
radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* reference value */
radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* mask */
radeon_emit(cs, 4); /* poll interval */
 }
 
 static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct 
r600_atom *atom)
 {
struct radeon_winsys_cs *cs = rctx->gfx.cs;
struct r600_so_target **t = rctx->streamout.targets;
-   unsigned *stride_in_dw = rctx->streamout.stride_in_dw;
+   uint16_t *stride_in_dw = rctx->streamout.stride_in_dw;
unsigned i, update_flags = 0;
 
r600_flush_vgt_streamout(rctx);
 
for (i = 0; i < rctx->streamout.num_targets; i++) {
if (!t[i])
continue;
 
t[i]->stride_in_dw = stride_in_dw[i];
 
diff --git a/src/gallium/include/pipe/p_state.h 
b/src/gallium/include/pipe/p_state.h
index 5d995dc..54bcf07 100644
--- a/src/gallium/include/pipe/p_state.h
+++ b/src/gallium/include/pipe/p_state.h
@@ -199,36 +199,36 @@ struct pipe_scissor_state
 struct pipe_clip_state
 {
float ucp[PIPE_MAX_CLIP_PLANES][4];
 };
 
 /**
  * A single output for vertex transform feedback.
  */
 struct pipe_stream_output
 {
-   unsigned register_index:8;  /**< 0 to PIPE_MAX_SHADER_OUTPUTS */
+   unsigned register_index:6;  /**< 0 to 63 (OUT index) */
unsigned start_component:2; /** 0 to 3 */
unsigned num_components:3;  /** 1 to 4 */
unsigned output_buffer:3;   /**< 0 to PIPE_MAX_SO_BUFFERS */
unsigned dst_offset:16; /**< offset into the buffer in dwords */
unsigned stream:2;  /**< 0 to 3 */
 };
 
 /**
  * Stream output for vertex transform feedback.
  */
 struct pipe_stream_output_info
 {
unsigned num_outputs;
/** stride for an entire vertex for each buffer in dwords */
-   unsigned stride[PIPE_MAX_SO_BUFFERS];
+   uint16_t stride[PIPE_MAX_SO_BUFFERS];
 
/**
 * Array of stream outputs, in the order they are to be written in.
 * Selected components are tightly packed into the output buffer.
 */
struct pipe_stream_output output[PIPE_MAX_SO_OUTPUTS];
 };
 
 /**
  * The 'type' parameter identifies whether the shader state contains TGSI
-- 
2.7.4

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Re: [Mesa-dev] [RFC PATCH] egl/android: Dequeue buffers inside EGL calls

[Mauro Rossi]

2017-03-31 13:05 GMT+02:00 Tapani Pälli :

>
>
> On 03/31/2017 10:12 AM, Tapani Pälli wrote:
>
>>
>>
>> On 03/31/2017 09:06 AM, Tapani Pälli wrote:
>>
>>>
>>>
>>> On 03/31/2017 08:24 AM, Rob Clark wrote:
>>>
 On Fri, Mar 31, 2017 at 12:22 AM, Tapani Pälli
  wrote:

>
>
> On 03/30/2017 05:57 PM, Emil Velikov wrote:
>
>>
>> On 30 March 2017 at 15:30, Tomasz Figa  wrote:
>>
>>>
>>> On Thu, Mar 30, 2017 at 11:17 PM, Emil Velikov
>>> 
>>> wrote:
>>>


 On 30 March 2017 at 11:55, Tomasz Figa  wrote:

>
> Android buffer queues can be abandoned, which results in failing to
> dequeue next buffer. Currently this would fail somewhere deep
> within
> the DRI stack calling loader's getBuffers*(), without any error
> reporting to the client app. However Android framework code
> relies on
> proper signaling of this event, so we move buffer dequeue to
> createWindowSurface() and swapBuffers() call, which can generate
> proper
> EGL errors. To keep the performance benefits of delayed buffer
> handling,
> if any, fence wait and DRI image creation is kept delayed until
> getBuffers*() is called by the DRI driver.
>
> Thank you Tomasz.

 I'm fairly confident that this should resolve the crash [in
 swap_buffers] that Mauro was seeing.
 Mauro can you give it a test ?

>>>
>>>
>>> Ah, I actually noticed a problem with existing code, supposedly fixed
>>> by [1], but I'm afraid it's still wrong.
>>>
>>> Current swap_buffers calls get_back_bo(), but doesn't call
>>> update_buffers(), which is the function that should be called before
>>> to actually dequeue a buffer from Android's buffer queue. Given that,
>>> get_back_bo() would simply fail with !dri2_surf->buffer, because no
>>> buffer was dequeued.
>>>
>>> Right - I was wondering why we don't hit that on EGL/GBM or
>> EGL/Wayland.
>> From a quick look - may be because EGL/Android drops the dpy mutex in
>> droid_window_enqueue_buffer().
>>
>> My patch removes update_buffers() and changes the buffer
>>> management so
>>> that there is always a buffer dequeued, starting from surface
>>> creation, unless there was an error somewhere.
>>>
>>> Of the top of your head - is there something stopping us from using
>> the same method on $other platforms?
>>
>> [1]
>>> https://cgit.freedesktop.org/mesa/mesa/commit/src/egl/driver
>>> s/dri2/platform_android.c?id=4d4558411db166d2d66f8cec9cb5811
>>> 49dbe1597
>>>
>>>
>>>
>>>

 Not that huge of an expert on the Android specifics, so just a
 humble
 request:
 Can we seek the code resuffle (droid_{alloc,free}_local_buffer,

>>>
>> Oops silly typo - s/seek/split/.
>>
>> other?) separate from the functionality changes ?

>>>
>>>
>>> Sure. Thanks for suggestion.
>>>
>>> Please give it a day or two for others to comment.
>>
>
>
> I'm trying to debug why this causes our homescreen (wallpaper) to be
> black.
> Otherwise I haven't seen any issues with these changes.
>
>
 wallpaper seems to be a special sorta hell..  I wonder if there is
 somehow some sort of interaction with what I fixed / worked-around in
 a5e733c6b52e93de3000647d075f5ca2f55fcb71 ??

 Maybe at least try commenting out the temp-pbuffer thing to get max
 texture size, and see if that "fixes" things

>>>
>>> Can you give more details, I still live in la la land and don't know
>>> about 'temp-pbuffer thing'?
>>>
>>>
>> aa I did not recall the problem, you mean the 'dummy pbuffer' in
>> SurfaceFlinger .. yes I will check if this is related.
>>
>>
> If I take away that dummy pbuffer usage (which is useless anyway), couple
> of errors disappear from the log. They are:
>
> SurfaceFlinger: releasePendingBuffer failed: Unknown error -1 (1)
> SurfaceFlinger: releasePendingBuffer failed: Unknown error -1 (1)
>
> but otherwise the desktop still stays black, live wallpapers seem to work
> so there is something special about this default wallpaper. Will continue
> digging ..
>
> // Tapani
>


Hi,

about the black wallpaper the only sign found in logcat is the following:

- beginning of main
04-02 15:09:43.148
...
04-02 15:10:41.710  1414  1414 E Layer   :
[com.android.systemui.ImageWallpaper] rejecting buffer: bufWidth=1024,
bufHeight=768, front.active.{w=1, h=1}
...
04-02 15:10:41.726  1414  1414 E Layer   :
[com.android.systemui.ImageWallpaper] rejecting buffer: bufWidth=1024,
bufHeight=768, front.active.{w=1, h=1}

Are the expected width and 

[Mesa-dev] [PATCH 1/4] r600g: remove duplicate memset by using a pointer, and constify args

[Constantine Kharlamov]

Signed-off-by: Constantine Kharlamov 
---
 src/gallium/drivers/r600/r600_state_common.c | 41 +---
 1 file changed, 19 insertions(+), 22 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_state_common.c 
b/src/gallium/drivers/r600/r600_state_common.c
index 096caed8d3..d125146907 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -712,49 +712,47 @@ static void r600_update_compressed_colortex_mask(struct 
r600_samplerview_state *
 }
 
 /* Compute the key for the hw shader variant */
-static inline union r600_shader_key r600_shader_selector_key(struct 
pipe_context * ctx,
-   struct r600_pipe_shader_selector * sel)
+static inline void r600_shader_selector_key(const struct pipe_context *ctx,
+   const struct r600_pipe_shader_selector *sel,
+   union r600_shader_key *key)
 {
-   struct r600_context *rctx = (struct r600_context *)ctx;
-   union r600_shader_key key;
-   memset(, 0, sizeof(key));
+   const struct r600_context *rctx = (struct r600_context *)ctx;
+   memset(key, 0, sizeof(*key));
 
switch (sel->type) {
case PIPE_SHADER_VERTEX: {
-   key.vs.as_ls = (rctx->tes_shader != NULL);
-   if (!key.vs.as_ls)
-   key.vs.as_es = (rctx->gs_shader != NULL);
+   key->vs.as_ls = (rctx->tes_shader != NULL);
+   if (!key->vs.as_ls)
+   key->vs.as_es = (rctx->gs_shader != NULL);
 
if (rctx->ps_shader->current->shader.gs_prim_id_input && 
!rctx->gs_shader) {
-   key.vs.as_gs_a = true;
-   key.vs.prim_id_out = 
rctx->ps_shader->current->shader.input[rctx->ps_shader->current->shader.ps_prim_id_input].spi_sid;
+   key->vs.as_gs_a = true;
+   key->vs.prim_id_out = 
rctx->ps_shader->current->shader.input[rctx->ps_shader->current->shader.ps_prim_id_input].spi_sid;
}
break;
}
case PIPE_SHADER_GEOMETRY:
break;
case PIPE_SHADER_FRAGMENT: {
-   key.ps.color_two_side = rctx->rasterizer && 
rctx->rasterizer->two_side;
-   key.ps.alpha_to_one = rctx->alpha_to_one &&
+   key->ps.color_two_side = rctx->rasterizer && 
rctx->rasterizer->two_side;
+   key->ps.alpha_to_one = rctx->alpha_to_one &&
  rctx->rasterizer && 
rctx->rasterizer->multisample_enable &&
  !rctx->framebuffer.cb0_is_integer;
-   key.ps.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
+   key->ps.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
/* Dual-source blending only makes sense with nr_cbufs == 1. */
-   if (key.ps.nr_cbufs == 1 && rctx->dual_src_blend)
-   key.ps.nr_cbufs = 2;
+   if (key->ps.nr_cbufs == 1 && rctx->dual_src_blend)
+   key->ps.nr_cbufs = 2;
break;
}
case PIPE_SHADER_TESS_EVAL:
-   key.tes.as_es = (rctx->gs_shader != NULL);
+   key->tes.as_es = (rctx->gs_shader != NULL);
break;
case PIPE_SHADER_TESS_CTRL:
-   key.tcs.prim_mode = 
rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
+   key->tcs.prim_mode = 
rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
break;
default:
assert(0);
}
-
-   return key;
 }
 
 /* Select the hw shader variant depending on the current state.
@@ -767,8 +765,7 @@ static int r600_shader_select(struct pipe_context *ctx,
struct r600_pipe_shader * shader = NULL;
int r;
 
-   memset(, 0, sizeof(key));
-   key = r600_shader_selector_key(ctx, sel);
+   r600_shader_selector_key(ctx, sel, );
 
/* Check if we don't need to change anything.
 * This path is also used for most shaders that don't need multiple
@@ -812,7 +809,7 @@ static int r600_shader_select(struct pipe_context *ctx,
if (sel->type == PIPE_SHADER_FRAGMENT &&
sel->num_shaders == 0) {
sel->nr_ps_max_color_exports = 
shader->shader.nr_ps_max_color_exports;
-   key = r600_shader_selector_key(ctx, sel);
+   r600_shader_selector_key(ctx, sel, );
}
 
memcpy(>key, , sizeof(key));
-- 
2.12.0

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[Mesa-dev] [PATCH 3/4] r600g: extract a code into a r600_emit_rasterizer_prim_state()

[Constantine Kharlamov]

Also change gs_output_prim type: unsigned → pipe_prim_type. The idea of
the code is mostly taken from radeonsi. The new code operating on
prev/curr rast_primitives saves ≈15 reloads of PA_SC_LINE_STIPPLE per
frame in Kane

Signed-off-by: Constantine Kharlamov 
---
 src/gallium/drivers/r600/r600_hw_context.c   |  2 ++
 src/gallium/drivers/r600/r600_pipe.h |  8 +++---
 src/gallium/drivers/r600/r600_state_common.c | 37 +++-
 3 files changed, 33 insertions(+), 14 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_hw_context.c 
b/src/gallium/drivers/r600/r600_hw_context.c
index 4663d99c0b..4511ce0c01 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -369,6 +369,8 @@ void r600_begin_new_cs(struct r600_context *ctx)
/* Re-emit the draw state. */
ctx->last_primitive_type = -1;
ctx->last_start_instance = -1;
+   ctx->last_rast_prim  = -1;
+   ctx->current_rast_prim   = -1;
 
assert(!ctx->b.gfx.cs->prev_dw);
ctx->b.initial_gfx_cs_size = ctx->b.gfx.cs->current.cdw;
diff --git a/src/gallium/drivers/r600/r600_pipe.h 
b/src/gallium/drivers/r600/r600_pipe.h
index a05d543f0d..86634b8681 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -322,9 +322,9 @@ struct r600_pipe_shader_selector {
enum pipe_shader_type   type;
 
/* geometry shader properties */
-   unsignedgs_output_prim;
-   unsignedgs_max_out_vertices;
-   unsignedgs_num_invocations;
+   enum pipe_prim_type gs_output_prim;
+   unsignedgs_max_out_vertices;
+   unsignedgs_num_invocations;
 
/* TCS/VS */
uint64_tlds_patch_outputs_written_mask;
@@ -512,6 +512,8 @@ struct r600_context {
 
/* Last draw state (-1 = unset). */
enum pipe_prim_type last_primitive_type; /* Last primitive 
type used in draw_vbo. */
+   enum pipe_prim_type current_rast_prim; /* primitive type 
after TES, GS */
+   enum pipe_prim_type last_rast_prim;
unsignedlast_start_instance;
 
void*sb_context;
diff --git a/src/gallium/drivers/r600/r600_state_common.c 
b/src/gallium/drivers/r600/r600_state_common.c
index d125146907..e4d1660933 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1666,6 +1666,27 @@ void r600_emit_clip_misc_state(struct r600_context 
*rctx, struct r600_atom *atom
   
S_028AB4_REUSE_OFF(state->vs_out_viewport));
 }
 
+/* rast_prim is the primitive type after GS. */
+static inline void r600_emit_rasterizer_prim_state(struct r600_context *rctx)
+{
+   struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
+   unsigned ls_mask = 0;
+   enum pipe_prim_type rast_prim = rctx->current_rast_prim;
+   if (rast_prim == rctx->last_rast_prim)
+   return;
+
+   if (rast_prim == PIPE_PRIM_LINES)
+   ls_mask = 1;
+   else if (rast_prim == PIPE_PRIM_LINE_STRIP ||
+rast_prim == PIPE_PRIM_LINE_LOOP)
+   ls_mask = 2;
+
+   radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
+  S_028A0C_AUTO_RESET_CNTL(ls_mask) |
+  (rctx->rasterizer ? 
rctx->rasterizer->pa_sc_line_stipple : 0));
+   rctx->last_rast_prim = rast_prim;
+}
+
 static void r600_draw_vbo(struct pipe_context *ctx, const struct 
pipe_draw_info *info)
 {
struct r600_context *rctx = (struct r600_context *)ctx;
@@ -1704,6 +1725,10 @@ static void r600_draw_vbo(struct pipe_context *ctx, 
const struct pipe_draw_info
return;
}
 
+   rctx->current_rast_prim = (rctx->gs_shader)? 
rctx->gs_shader->gs_output_prim
+   : (rctx->tes_shader)? 
rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE]
+   : info->mode;
+
if (info->indexed) {
/* Initialize the index buffer struct. */
pipe_resource_reference(, rctx->index_buffer.buffer);
@@ -1863,17 +1888,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, 
const struct pipe_draw_info
 
/* Update the primitive type. */
if (rctx->last_primitive_type != info->mode) {
-   unsigned ls_mask = 0;
-
-   if (info->mode == PIPE_PRIM_LINES)
-   ls_mask = 1;
-   else if (info->mode == PIPE_PRIM_LINE_STRIP ||
-info->mode == PIPE_PRIM_LINE_LOOP)
-   ls_mask = 2;
-
-   radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
-  S_028A0C_AUTO_RESET_CNTL(ls_mask) |
-  (rctx->rasterizer ? 
rctx->rasterizer->pa_sc_line_stipple : 0));
+  

[Mesa-dev] [PATCH 0/4] r600_state_common small improvements

[Constantine Kharlamov]

The patches are based on top of the other 3 reviewed but not yet pushed from
"Small r600_draw_vbo optimizations". Here, amongst all, I replaced some
"unsigned"s with the enums they represent. It helps understanding the code, and
even allowed to remove a short comment with the sole purpose of just describing
the acc. enum.

Piglit-tested with tests/gpu.py in gbm mode, no changes.

P.S. I don't have commit access.

Constantine Kharlamov (4):
  r600g: remove duplicate memset by using a pointer, and constify args
  r600g/radeonsi: use the correct types (taken from pipe_draw_info)
  r600g: extract a code into a r600_emit_rasterizer_prim_state()
  r600g: check rasterizer primitive states like in radeonsi

 src/gallium/drivers/r600/r600_hw_context.c   |  2 +
 src/gallium/drivers/r600/r600_pipe.h | 16 +++---
 src/gallium/drivers/r600/r600_state_common.c | 83 +---
 src/gallium/drivers/radeonsi/si_pipe.h   |  2 +-
 src/gallium/drivers/radeonsi/si_state_draw.c |  5 +-
 5 files changed, 65 insertions(+), 43 deletions(-)

-- 
2.12.0

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[Mesa-dev] [PATCH 4/4] r600g: check rasterizer primitive states like in radeonsi

[Constantine Kharlamov]

Specifically, non-line primitives skipped, and defaulting to reset on
each packet.

The skip of non-line primitives saves ≈110 resetting of
PA_SC_LINE_STIPPLE register per frame in Kane

Signed-off-by: Constantine Kharlamov 
---
 src/gallium/drivers/r600/r600_state_common.c | 21 +
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_state_common.c 
b/src/gallium/drivers/r600/r600_state_common.c
index e4d1660933..4de2a7344b 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1670,19 +1670,24 @@ void r600_emit_clip_misc_state(struct r600_context 
*rctx, struct r600_atom *atom
 static inline void r600_emit_rasterizer_prim_state(struct r600_context *rctx)
 {
struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
-   unsigned ls_mask = 0;
enum pipe_prim_type rast_prim = rctx->current_rast_prim;
-   if (rast_prim == rctx->last_rast_prim)
+
+   /* Skip this if not rendering lines. */
+   if (rast_prim != PIPE_PRIM_LINES &&
+   rast_prim != PIPE_PRIM_LINE_LOOP &&
+   rast_prim != PIPE_PRIM_LINE_STRIP &&
+   rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
+   rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
return;
 
-   if (rast_prim == PIPE_PRIM_LINES)
-   ls_mask = 1;
-   else if (rast_prim == PIPE_PRIM_LINE_STRIP ||
-rast_prim == PIPE_PRIM_LINE_LOOP)
-   ls_mask = 2;
+   if (rast_prim == rctx->last_rast_prim)
+   return;
 
+   /* For lines, reset the stipple pattern at each primitive. Otherwise,
+* reset the stipple pattern at each packet (line strips, line loops).
+*/
radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
-  S_028A0C_AUTO_RESET_CNTL(ls_mask) |
+  S_028A0C_AUTO_RESET_CNTL(rast_prim == 
PIPE_PRIM_LINES ? 1 : 2) |
   (rctx->rasterizer ? 
rctx->rasterizer->pa_sc_line_stipple : 0));
rctx->last_rast_prim = rast_prim;
 }
-- 
2.12.0

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[Mesa-dev] [PATCH 2/4] r600g/radeonsi: use the correct types (taken from pipe_draw_info)

[Constantine Kharlamov]

Note: si_shader.h has also "type" variable that should be changed to
"enum pipe_prim_type", however it triggers a bunch of warnings about
unhandled switches, so due not knowing the correct way to handle them, I
decided to leave it as is.

Signed-off-by: Constantine Kharlamov 
---
 src/gallium/drivers/r600/r600_pipe.h | 8 
 src/gallium/drivers/radeonsi/si_pipe.h   | 2 +-
 src/gallium/drivers/radeonsi/si_state_draw.c | 5 +++--
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_pipe.h 
b/src/gallium/drivers/r600/r600_pipe.h
index a7b7276732..a05d543f0d 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -29,6 +29,7 @@
 #include "radeon/r600_pipe_common.h"
 #include "radeon/r600_cs.h"
 #include "r600_public.h"
+#include "pipe/p_defines.h"
 
 #include "util/u_suballoc.h"
 #include "util/list.h"
@@ -318,8 +319,7 @@ struct r600_pipe_shader_selector {
 
unsignednum_shaders;
 
-   /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
-   unsignedtype;
+   enum pipe_shader_type   type;
 
/* geometry shader properties */
unsignedgs_output_prim;
@@ -511,8 +511,8 @@ struct r600_context {
struct pipe_index_bufferindex_buffer;
 
/* Last draw state (-1 = unset). */
-   int last_primitive_type; /* Last primitive 
type used in draw_vbo. */
-   int last_start_instance;
+   enum pipe_prim_type last_primitive_type; /* Last primitive 
type used in draw_vbo. */
+   unsignedlast_start_instance;
 
void*sb_context;
struct r600_isa *isa;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
b/src/gallium/drivers/radeonsi/si_pipe.h
index 9225899047..daf29325f7 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -348,7 +348,7 @@ struct si_context {
int last_multi_vgt_param;
int last_rast_prim;
unsignedlast_sc_line_stipple;
-   int current_rast_prim; /* primitive type after TES, 
GS */
+   enum pipe_prim_type current_rast_prim; /* primitive type after TES, 
GS */
boolgs_tri_strip_adj_fix;
 
/* Scratch buffer */
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c 
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 1f219f8ae6..2c4e3715e4 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -468,7 +468,7 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context 
*sctx,
 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
 {
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
-   unsigned rast_prim = sctx->current_rast_prim;
+   enum pipe_prim_type rast_prim = sctx->current_rast_prim;
struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
 
/* Skip this if not rendering lines. */
@@ -1091,7 +1091,8 @@ void si_draw_vbo(struct pipe_context *ctx, const struct 
pipe_draw_info *info)
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
const struct pipe_index_buffer *ib = >index_buffer;
struct pipe_index_buffer ib_tmp; /* for index buffer uploads only */
-   unsigned mask, dirty_tex_counter, rast_prim;
+   unsigned mask, dirty_tex_counter;
+   enum pipe_prim_type rast_prim;
 
if (likely(!info->indirect)) {
/* SI-CI treat instance_count==0 as instance_count==1. There is
-- 
2.12.0

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[Mesa-dev] [PATCH 2/2] st/shader_cache: Fix memory leak

[Bartosz Tomczyk]

---
 src/mesa/state_tracker/st_shader_cache.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/state_tracker/st_shader_cache.c 
b/src/mesa/state_tracker/st_shader_cache.c
index e8c7289ec6..5dbcb74f73 100644
--- a/src/mesa/state_tracker/st_shader_cache.c
+++ b/src/mesa/state_tracker/st_shader_cache.c
@@ -135,6 +135,8 @@ st_store_tgsi_in_disk_cache(struct st_context *st, struct 
gl_program *prog,
   _mesa_shader_stage_to_string(prog->info.stage), sha1_buf);
}
 
+   if(blob->data)
+  free(blob->data);
free(blob);
 }
 
-- 
2.12.2

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[Mesa-dev] [PATCH 1/2] glsl/shader_cache: Fix memory leak

[Bartosz Tomczyk]

---
 src/compiler/glsl/shader_cache.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/compiler/glsl/shader_cache.cpp 
b/src/compiler/glsl/shader_cache.cpp
index ea1bc01f02..8c42a95664 100644
--- a/src/compiler/glsl/shader_cache.cpp
+++ b/src/compiler/glsl/shader_cache.cpp
@@ -1273,6 +1273,8 @@ shader_cache_write_program_metadata(struct gl_context 
*ctx,
 
disk_cache_put(cache, prog->data->sha1, metadata->data, metadata->size);
 
+   if(metadata->data)
+  free(metadata->data);
free(metadata);
 
if (ctx->_Shader->Flags & GLSL_CACHE_INFO) {
-- 
2.12.2

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[Mesa-dev] [PATCH] amd/addrlib: fix optimized build warnings

[Grazvydas Ignotas]

All the -Wunused-but-set-variable ones.
Found a way to do it with a oneliner.

Signed-off-by: Grazvydas Ignotas 
---
no commit access (currently pending)

 src/amd/addrlib/core/addrcommon.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/addrlib/core/addrcommon.h 
b/src/amd/addrlib/core/addrcommon.h
index 3911d79..66424a8 100644
--- a/src/amd/addrlib/core/addrcommon.h
+++ b/src/amd/addrlib/core/addrcommon.h
@@ -66,11 +66,11 @@
 // Debug assertions used in AddrLib
 

 #if defined(_WIN32) && (_MSC_VER >= 1400)
 #define ADDR_ANALYSIS_ASSUME(expr) __analysis_assume(expr)
 #else
-#define ADDR_ANALYSIS_ASSUME(expr) do { } while (0)
+#define ADDR_ANALYSIS_ASSUME(expr) do { (void)(expr); } while (0)
 #endif
 
 #if DEBUG
 #define ADDR_ASSERT(__e)\
 do {\
-- 
2.7.4

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[Mesa-dev] [PATCH] radeonsi: use unreachable to fix a warning

[Grazvydas Ignotas]

si_state.c: In function ‘si_make_texture_descriptor’:
si_state.c:3240:25: warning: ‘num_format’ may be used uninitialized
si_state.c:3240:12: warning: ‘data_format’ may be used uninitialized

Signed-off-by: Grazvydas Ignotas 
---
no commit access (currently pending)

 src/gallium/drivers/radeonsi/si_state.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 35fadec..4a6b615 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3252,11 +3252,11 @@ si_make_texture_descriptor(struct si_screen *screen,
break;
case 8:
num_format = V_008F14_IMG_FMASK_32_8_8;
break;
default:
-   assert(0);
+   unreachable("invalid nr_samples");
}
} else {
switch (res->nr_samples) {
case 2:
data_format = 
V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
@@ -3266,11 +3266,11 @@ si_make_texture_descriptor(struct si_screen *screen,
break;
case 8:
data_format = 
V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
break;
default:
-   assert(0);
+   unreachable("invalid nr_samples");
}
num_format = V_008F14_IMG_NUM_FORMAT_UINT;
}
 
fmask_state[0] = va >> 8;
-- 
2.7.4

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Re: [Mesa-dev] [RFC PATCH] egl/android: Dequeue buffers inside EGL calls

[Tomasz Figa]

Sorry for replying to myself, just got enlightened...

On Mon, Apr 3, 2017 at 2:07 AM, Tomasz Figa  wrote:
> Hi Mauro,
>
> On Mon, Apr 3, 2017 at 1:38 AM, Mauro Rossi  wrote:
>>
>>
>> 2017-03-30 16:17 GMT+02:00 Emil Velikov :
>>>
>>> On 30 March 2017 at 11:55, Tomasz Figa  wrote:
>>> > Android buffer queues can be abandoned, which results in failing to
>>> > dequeue next buffer. Currently this would fail somewhere deep within
>>> > the DRI stack calling loader's getBuffers*(), without any error
>>> > reporting to the client app. However Android framework code relies on
>>> > proper signaling of this event, so we move buffer dequeue to
>>> > createWindowSurface() and swapBuffers() call, which can generate proper
>>> > EGL errors. To keep the performance benefits of delayed buffer handling,
>>> > if any, fence wait and DRI image creation is kept delayed until
>>> > getBuffers*() is called by the DRI driver.
>>> >
>>> Thank you Tomasz.
>>>
>>> I'm fairly confident that this should resolve the crash [in
>>> swap_buffers] that Mauro was seeing.
>>> Mauro can you give it a test ?
>>
>>
>> After applying last version of Tomasz patch,
>> I could not boot nougat-x86, the same way as per Tapani get_back_bo()
>> throwing and EGL_BAD_ALLOC
>> which is a show stopper for surfaceflinger
>
> Hmm, must be something I missed in the code, because with my patch
> applied, there should be no condition that could make get_back_bo()
> fail, unless previous swap_buffers() failed in droid_dequeue_buffer()
> or there is something wrong with the first buffer being dequeued in
> create_surface(). Would you be able to check where exactly
> get_back_bo() fails with your setup?

Ah, wait, I just realized that get_back_bo() is valid only when the
image loader is used, which is only on DMA-buf FD-based systems. No
wonder that it fails on android-x86.

Tapani, would you be able to give a bit more details on the crash
being observed without that call? AFAICT, without my patch, even with
the call, the code is still not fully correct, because on the first
call to swap_buffers() without any rendering the dri2_surf->buffer
would be NULL and get_back_bo() would simply fail (but not crash
indeed). With my patch, it won't fail, because there is always a
buffer dequeued, so it should be the closest to correct behavior.

Best regards,
Tomasz
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Re: [Mesa-dev] [RFC PATCH] egl/android: Dequeue buffers inside EGL calls

[Tomasz Figa]

Hi Mauro,

On Mon, Apr 3, 2017 at 1:38 AM, Mauro Rossi  wrote:
>
>
> 2017-03-30 16:17 GMT+02:00 Emil Velikov :
>>
>> On 30 March 2017 at 11:55, Tomasz Figa  wrote:
>> > Android buffer queues can be abandoned, which results in failing to
>> > dequeue next buffer. Currently this would fail somewhere deep within
>> > the DRI stack calling loader's getBuffers*(), without any error
>> > reporting to the client app. However Android framework code relies on
>> > proper signaling of this event, so we move buffer dequeue to
>> > createWindowSurface() and swapBuffers() call, which can generate proper
>> > EGL errors. To keep the performance benefits of delayed buffer handling,
>> > if any, fence wait and DRI image creation is kept delayed until
>> > getBuffers*() is called by the DRI driver.
>> >
>> Thank you Tomasz.
>>
>> I'm fairly confident that this should resolve the crash [in
>> swap_buffers] that Mauro was seeing.
>> Mauro can you give it a test ?
>
>
> After applying last version of Tomasz patch,
> I could not boot nougat-x86, the same way as per Tapani get_back_bo()
> throwing and EGL_BAD_ALLOC
> which is a show stopper for surfaceflinger

Hmm, must be something I missed in the code, because with my patch
applied, there should be no condition that could make get_back_bo()
fail, unless previous swap_buffers() failed in droid_dequeue_buffer()
or there is something wrong with the first buffer being dequeued in
create_surface(). Would you be able to check where exactly
get_back_bo() fails with your setup?

>
> So I reverted [1] and now I can boot and I also see the black wallpaper like
> Tapani.
> dumpsys SurfaceFlinger output shows a buffer allocated,
> but for some reason both HWC and GLES composition (used in nougat-x86) show
> black wallpaper.
>
> 
> h/w composer state:
>   h/w composer not present and enabled
> Allocated buffers:
> ...
> 0x7b60f301e380: 29440.00 KiB | 2880 (2944) x 2560 |5 | 0x0900 |
> com.android.systemui.ImageWallpaper
> ...
> Total allocated (estimate): 54728.50 KB
> 
>
>>
>>
>> Not that huge of an expert on the Android specifics, so just a humble
>> request:
>> Can we seek the code resuffle (droid_{alloc,free}_local_buffer,
>> other?) separate from the functionality changes ?
>>
>> -Emil
>
>
> I'd also kindly request to confirm the test environment used to verify
> Tomasz patch v2,
> which in my understanding has been the following, common between ChomiumOS
> and Android-IA:
>
> minigbm based gralloc

On ChromeOS it's still a drm_gralloc-based gralloc, but heavily
rewritten to use DMA-buf FDs and satisfy some other requirements for
production.

> dma FDs for buffers
> kernel based explicit fences with FDs

There is no support for explicit fences in Mesa at the moment, at
least in Android EGL backend. It always waits synchronously on the
acquire fence and returns -1 as release fence FD.

> HWC2 for compositing
> (?) Render nodes - but I don't know if/when they are used

We don't use control nodes from the Android running in ChromeOS at
all. We use the most suitable render node (i.e. i965 on Intel
platforms) for allocating buffers and rendering.

>
> In android-x86 (nougat-x86) situation is the following:
>
> drm_gralloc based gralloc
> buffer handles
> Not 100% sure about sync/fences, but I don't recall about using explicit
> fences with FDs
> GLES for compositing
> we don't use render nodes
>
> Pardon me if this seems a long checklist or if it's not 100% accurate,
> but I would assume that this patch should just work Out-Of-The-Box with
> android-x86 (nougat-x86)
> even if most of CrOS/Android-IA optimizations are not (yet) used there.
>
> Is this assumption correct?

Yeah, I believe so. Although I might have missed something within the
BO name/handle code path, as it can be quite tricky.

>
> In this moment the only way to boot nougat-x86 is to revert [1]
> but besides this and black wallpaper, which both require investigation,
> I've not seen any particular regression.

Thanks for testing!

Best regards,
Tomasz
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Re: [Mesa-dev] [RFC PATCH] egl/android: Dequeue buffers inside EGL calls

[Mauro Rossi]

2017-03-30 16:17 GMT+02:00 Emil Velikov :

> On 30 March 2017 at 11:55, Tomasz Figa  wrote:
> > Android buffer queues can be abandoned, which results in failing to
> > dequeue next buffer. Currently this would fail somewhere deep within
> > the DRI stack calling loader's getBuffers*(), without any error
> > reporting to the client app. However Android framework code relies on
> > proper signaling of this event, so we move buffer dequeue to
> > createWindowSurface() and swapBuffers() call, which can generate proper
> > EGL errors. To keep the performance benefits of delayed buffer handling,
> > if any, fence wait and DRI image creation is kept delayed until
> > getBuffers*() is called by the DRI driver.
> >
> Thank you Tomasz.
>
> I'm fairly confident that this should resolve the crash [in
> swap_buffers] that Mauro was seeing.
> Mauro can you give it a test ?
>

After applying last version of Tomasz patch,
I could not boot nougat-x86, the same way as per Tapani get_back_bo()
throwing and EGL_BAD_ALLOC
which is a show stopper for surfaceflinger

So I reverted [1] and now I can boot and I also see the black wallpaper
like Tapani.
dumpsys SurfaceFlinger output shows a buffer allocated,
but for some reason both HWC and GLES composition (used in nougat-x86) show
black wallpaper.


h/w composer state:
  h/w composer not present and enabled
Allocated buffers:
...
0x7b60f301e380: 29440.00 KiB | 2880 (2944) x 2560 |5 | 0x0900 |
com.android.systemui.ImageWallpaper
...
Total allocated (estimate): 54728.50 KB



>
> Not that huge of an expert on the Android specifics, so just a humble
> request:
> Can we seek the code resuffle (droid_{alloc,free}_local_buffer,
> other?) separate from the functionality changes ?
>
> -Emil
>

I'd also kindly request to confirm the test environment used to verify
Tomasz patch v2,
which in my understanding has been the following, common between ChomiumOS
and Android-IA:

   - minigbm based gralloc
   - dma FDs for buffers
   - kernel based explicit fences with FDs
   - HWC2 for compositing
   - (?) Render nodes - but I don't know if/when they are used

In android-x86 (nougat-x86) situation is the following:

   - drm_gralloc based gralloc
   - buffer handles
   - Not 100% sure about sync/fences, but I don't recall about using
   explicit fences with FDs
   - GLES for compositing
   - we don't use render nodes

Pardon me if this seems a long checklist or if it's not 100% accurate,
but I would assume that this patch should just work Out-Of-The-Box with
android-x86 (nougat-x86)
even if most of CrOS/Android-IA optimizations are not (yet) used there.

Is this assumption correct?

In this moment the only way to boot nougat-x86 is to revert [1]
but besides this and black wallpaper, which both require investigation,
I've not seen any particular regression.

Thanks for feeedbacks
Mauro

PS: Question for Tapani: if you apply Tomasz patch and revert [1], do you
still see the segfault in Android-IA?

[1]  https://cgit.freedesktop.org/mesa/mesa/commit/?id=
4d4558411db166d2d66f8cec9cb581149dbe1597
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[Mesa-dev] [PATCH] gallium: fix some math formulas to display better

[Ilia Mirkin]

Signed-off-by: Ilia Mirkin 
---
 src/gallium/docs/source/tgsi.rst | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
index 05b06ce..ca31924 100644
--- a/src/gallium/docs/source/tgsi.rst
+++ b/src/gallium/docs/source/tgsi.rst
@@ -1204,13 +1204,13 @@ Support for these opcodes indicated by 
PIPE_SHADER_CAP_INTEGERS (all of them?)
 
 .. math::
 
-  dst.x = src0.x \ src1.x
+  dst.x = \frac{src0.x}{src1.x}
 
-  dst.y = src0.y \ src1.y
+  dst.y = \frac{src0.y}{src1.y}
 
-  dst.z = src0.z \ src1.z
+  dst.z = \frac{src0.z}{src1.z}
 
-  dst.w = src0.w \ src1.w
+  dst.w = \frac{src0.w}{src1.w}
 
 
 .. opcode:: UDIV - Unsigned Integer Division
@@ -1219,13 +1219,13 @@ Support for these opcodes indicated by 
PIPE_SHADER_CAP_INTEGERS (all of them?)
 
 .. math::
 
-  dst.x = src0.x \ src1.x
+  dst.x = \frac{src0.x}{src1.x}
 
-  dst.y = src0.y \ src1.y
+  dst.y = \frac{src0.y}{src1.y}
 
-  dst.z = src0.z \ src1.z
+  dst.z = \frac{src0.z}{src1.z}
 
-  dst.w = src0.w \ src1.w
+  dst.w = \frac{src0.w}{src1.w}
 
 
 .. opcode:: UMOD - Unsigned Integer Remainder
@@ -1234,13 +1234,13 @@ Support for these opcodes indicated by 
PIPE_SHADER_CAP_INTEGERS (all of them?)
 
 .. math::
 
-  dst.x = src0.x \ src1.x
+  dst.x = src0.x \bmod src1.x
 
-  dst.y = src0.y \ src1.y
+  dst.y = src0.y \bmod src1.y
 
-  dst.z = src0.z \ src1.z
+  dst.z = src0.z \bmod src1.z
 
-  dst.w = src0.w \ src1.w
+  dst.w = src0.w \bmod src1.w
 
 
 .. opcode:: NOT - Bitwise Not
@@ -2259,17 +2259,17 @@ two-component vectors with 64-bits in each component.
 
 .. math::
 
-  dst.xy = src0.xy \ src1.xy
+  dst.xy = \frac{src0.xy}{src1.xy}
 
-  dst.zw = src0.zw \ src1.zw
+  dst.zw = \frac{src0.zw}{src1.zw}
 
 .. opcode:: U64DIV - 64-bit Unsigned Integer Division
 
 .. math::
 
-  dst.xy = src0.xy \ src1.xy
+  dst.xy = \frac{src0.xy}{src1.xy}
 
-  dst.zw = src0.zw \ src1.zw
+  dst.zw = \frac{src0.zw}{src1.zw}
 
 .. opcode:: U64MOD - 64-bit Unsigned Integer Remainder
 
-- 
2.10.2

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[Mesa-dev] [Bug 100402] [d3d9 bisected] Diablo III fails to start after commit 0630d3600bfb770cf3b23761c45b3add3b277c6b

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100402

--- Comment #2 from Ilia Mirkin  ---
Please retest with
https://cgit.freedesktop.org/mesa/mesa/commit/?id=7a0c1eee0c25e343d8c276e4471e4a113d61f233
and let me know if that's fixed now.

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[Mesa-dev] [PATCH 2/2] aubinator/gen_decoder/i965: decode instructions from dword 0

[Lionel Landwerlin]

Some packets like 3DSTATE_VF_STATISTICS, 3DSTATE_DRAWING_RECTANGLE,
3DPRIMITIVE, PIPELINE_SELECT, etc... have configurable fields in
dword0, we probably want to print those.

Signed-off-by: Lionel Landwerlin 
---
 src/intel/common/gen_decoder.c| 21 +
 src/intel/common/gen_decoder.h|  2 +-
 src/intel/tools/aubinator.c   |  5 ++---
 src/mesa/drivers/dri/i965/intel_batchbuffer.c |  8 
 4 files changed, 24 insertions(+), 12 deletions(-)

diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 9b587c344d..6cc6896b05 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -817,10 +817,23 @@ print_dword_header(FILE *outfile,
offset + 4 * iter->dword, iter->p[iter->dword], iter->dword);
 }
 
+static bool
+is_header_field(struct gen_group *group, struct gen_field *field)
+{
+   uint32_t bits;
+
+   if (field->start > 32)
+  return false;
+
+   bits = (1U << (field->end - field->start + 1)) - 1;
+   bits <<= field->start;
+
+   return (group->opcode_mask & bits) != 0;
+}
+
 void
 gen_print_group(FILE *outfile, struct gen_group *group,
-uint64_t offset, const uint32_t *p,
-int starting_dword, bool color)
+uint64_t offset, const uint32_t *p, bool color)
 {
struct gen_field_iterator iter;
int last_dword = 0;
@@ -831,13 +844,13 @@ gen_print_group(FILE *outfile, struct gen_group *group,
  print_dword_header(outfile, , offset);
  last_dword = iter.dword;
   }
-  if (iter.dword >= starting_dword) {
+  if (!is_header_field(group, iter.field)) {
  fprintf(outfile, "%s: %s\n", iter.name, iter.value);
  if (iter.struct_desc) {
 uint64_t struct_offset = offset + 4 * iter.dword;
 print_dword_header(outfile, , struct_offset);
 gen_print_group(outfile, iter.struct_desc, struct_offset,
-[iter.dword], 0, color);
+[iter.dword], color);
  }
   }
}
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index ab01d6dd8b..be37e8a542 100644
--- a/src/intel/common/gen_decoder.h
+++ b/src/intel/common/gen_decoder.h
@@ -134,6 +134,6 @@ bool gen_field_iterator_next(struct gen_field_iterator 
*iter);
 void gen_print_group(FILE *out,
  struct gen_group *group,
  uint64_t offset, const uint32_t *p,
- int starting_dword, bool color);
+ bool color);
 
 #endif /* GEN_DECODER_H */
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 322f0df523..cae578baba 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -99,8 +99,7 @@ static void
 decode_group(struct gen_group *strct, const uint32_t *p, int starting_dword)
 {
uint64_t offset = option_print_offsets ? (void *) p - gtt : 0;
-   gen_print_group(outfile, strct, offset, p, starting_dword,
-   option_color == COLOR_ALWAYS);
+   gen_print_group(outfile, strct, offset, p, option_color == COLOR_ALWAYS);
 }
 
 static void
@@ -722,7 +721,7 @@ parse_commands(struct gen_spec *spec, uint32_t *cmds, int 
size, int engine)
   gen_group_get_name(inst), reset_color);
 
   if (option_full_decode) {
- decode_group(inst, p, 1);
+ decode_group(inst, p, 0);
 
  for (i = 0; i < ARRAY_LENGTH(custom_handlers); i++) {
 if (gen_group_get_opcode(inst) == custom_handlers[i].opcode)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 4c3b7dcc41..54bab9efb0 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -180,7 +180,7 @@ decode_struct(struct brw_context *brw, struct gen_spec 
*spec,
 
fprintf(stderr, "%s\n", struct_name);
gen_print_group(stderr, group, gtt_offset + offset,
-   [offset / 4], 0, color);
+   [offset / 4], color);
 }
 
 static void
@@ -197,7 +197,7 @@ decode_structs(struct brw_context *brw, struct gen_spec 
*spec,
for (int i = 0; i < entries; i++) {
   fprintf(stderr, "%s %d\n", struct_name, i);
   gen_print_group(stderr, group, gtt_offset + offset,
-  [(offset + i * struct_size) / 4], 0, color);
+  [(offset + i * struct_size) / 4], color);
}
 }
 
@@ -239,7 +239,7 @@ do_batch_dump(struct brw_context *brw)
   fprintf(stderr, "%s0x%08"PRIx64":  0x%08x:  %-80s%s\n", header_color,
   offset, p[0], gen_group_get_name(inst), reset_color);
 
-  gen_print_group(stderr, inst, offset, p, 1, color);
+  gen_print_group(stderr, inst, offset, p, color);
 
   switch (gen_group_get_opcode(inst) >> 16) {
   case _3DSTATE_PIPELINED_POINTERS:
@@ -261,7 +261,7 @@ 

[Mesa-dev] [PATCH 1/2] intel: gen_decoder: store pointer to current decoded field in iterator

[Lionel Landwerlin]

Signed-off-by: Lionel Landwerlin 
---
 src/intel/common/gen_decoder.c | 50 +-
 src/intel/common/gen_decoder.h |  1 +
 2 files changed, 26 insertions(+), 25 deletions(-)

diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 7b04ac051b..9b587c344d 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -723,7 +723,6 @@ gen_get_enum_name(struct gen_enum *e, uint64_t value)
 bool
 gen_field_iterator_next(struct gen_field_iterator *iter)
 {
-   struct gen_field *f;
union {
   uint64_t qw;
   float f;
@@ -732,39 +731,38 @@ gen_field_iterator_next(struct gen_field_iterator *iter)
if (iter->i == iter->group->nfields)
   return false;
 
-   f = iter->group->fields[iter->i++];
-   iter->name = f->name;
-   iter->dword = f->start / 32;
+   iter->field = iter->group->fields[iter->i++];
+   iter->name = iter->field->name;
+   iter->dword = iter->field->start / 32;
iter->struct_desc = NULL;
 
-   if ((f->end - f->start) > 32)
+   if ((iter->field->end - iter->field->start) > 32)
   v.qw = ((uint64_t) iter->p[iter->dword+1] << 32) | iter->p[iter->dword];
else
   v.qw = iter->p[iter->dword];
 
const char *enum_name = NULL;
 
-   switch (f->type.kind) {
+   switch (iter->field->type.kind) {
case GEN_TYPE_UNKNOWN:
case GEN_TYPE_INT: {
-  uint64_t value = field(v.qw, f->start, f->end);
-  snprintf(iter->value, sizeof(iter->value),
-   "%"PRId64, value);
-  enum_name = gen_get_enum_name(>inline_enum, value);
+  uint64_t value = field(v.qw, iter->field->start, iter->field->end);
+  snprintf(iter->value, sizeof(iter->value), "%"PRId64, value);
+  enum_name = gen_get_enum_name(>field->inline_enum, value);
   break;
}
case GEN_TYPE_UINT: {
-  uint64_t value = field(v.qw, f->start, f->end);
-  snprintf(iter->value, sizeof(iter->value),
-   "%"PRIu64, value);
-  enum_name = gen_get_enum_name(>inline_enum, value);
+  uint64_t value = field(v.qw, iter->field->start, iter->field->end);
+  snprintf(iter->value, sizeof(iter->value), "%"PRIu64, value);
+  enum_name = gen_get_enum_name(>field->inline_enum, value);
   break;
}
case GEN_TYPE_BOOL: {
   const char *true_string =
  iter->print_colors ? "\e[0;35mtrue\e[0m" : "true";
-  snprintf(iter->value, sizeof(iter->value),
-   "%s", field(v.qw, f->start, f->end) ? true_string : "false");
+  snprintf(iter->value, sizeof(iter->value), "%s",
+   field(v.qw, iter->field->start, iter->field->end) ?
+   true_string : "false");
   break;
}
case GEN_TYPE_FLOAT:
@@ -772,18 +770,20 @@ gen_field_iterator_next(struct gen_field_iterator *iter)
   break;
case GEN_TYPE_ADDRESS:
case GEN_TYPE_OFFSET:
-  snprintf(iter->value, sizeof(iter->value),
-   "0x%08"PRIx64, field_address(v.qw, f->start, f->end));
+  snprintf(iter->value, sizeof(iter->value), "0x%08"PRIx64,
+   field_address(v.qw, iter->field->start, iter->field->end));
   break;
case GEN_TYPE_STRUCT:
-  snprintf(iter->value, sizeof(iter->value),
-   "", f->type.gen_struct->name);
+  snprintf(iter->value, sizeof(iter->value), "",
+   iter->field->type.gen_struct->name);
   iter->struct_desc =
- gen_spec_find_struct(iter->group->spec, f->type.gen_struct->name);
+ gen_spec_find_struct(iter->group->spec,
+  iter->field->type.gen_struct->name);
   break;
case GEN_TYPE_UFIXED:
-  snprintf(iter->value, sizeof(iter->value),
-   "%f", (float) field(v.qw, f->start, f->end) / (1 << f->type.f));
+  snprintf(iter->value, sizeof(iter->value), "%f",
+   (float) field(v.qw, iter->field->start,
+ iter->field->end) / (1 << iter->field->type.f));
   break;
case GEN_TYPE_SFIXED:
   /* FIXME: Sign extend extracted field. */
@@ -792,10 +792,10 @@ gen_field_iterator_next(struct gen_field_iterator *iter)
case GEN_TYPE_MBO:
break;
case GEN_TYPE_ENUM: {
-  uint64_t value = field(v.qw, f->start, f->end);
+  uint64_t value = field(v.qw, iter->field->start, iter->field->end);
   snprintf(iter->value, sizeof(iter->value),
"%"PRId64, value);
-  enum_name = gen_get_enum_name(f->type.gen_enum, value);
+  enum_name = gen_get_enum_name(iter->field->type.gen_enum, value);
   break;
}
}
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index 1c41de80a4..ab01d6dd8b 100644
--- a/src/intel/common/gen_decoder.h
+++ b/src/intel/common/gen_decoder.h
@@ -58,6 +58,7 @@ struct gen_field_iterator {
const uint32_t *p;
int dword; /**< current field starts at [dword] */
int i;
+   struct gen_field *field;
bool print_colors;
 };
 
-- 
2.11.0

Re: [Mesa-dev] [PATCH 0/5] anv: Add support for VK_KHR_incremental_present

[Lionel Landwerlin]

This series is :

Reviewed-by: Lionel Landwerlin 

On 01/04/17 06:37, Jason Ekstrand wrote:

I've had these patches lying around for a while now waiting for the extension
to go public.  It went public, so here they are.  This series adds all of the
core window system bits for doing a trivial implementation on X11 and a real
implementation on Wayland.

I believe I've kept radv building with these patches but it would be nice if
Dave or Bas could double-check.  Most of the work is in the core, so it should
be trivial to hook up.

Cc: Dave Airlie 

Jason Ekstrand (5):
   vulkan/wsi: Fix some line wrapping
   vulkan: Bump the header and XML to the latest public version
   vulkan/wsi: Plumb present regions through the common code
   vulkan/wsi/wayland: Pass damage through to the compositor
   anv: Implement VK_KHR_incremental_present

  include/vulkan/vulkan.h |  171 +++--
  src/amd/vulkan/radv_wsi.c   |3 +-
  src/intel/vulkan/anv_device.c   |6 +-
  src/intel/vulkan/anv_entrypoints_gen.py |1 +
  src/intel/vulkan/anv_wsi.c  |   11 +-
  src/vulkan/registry/vk.xml  | 1098 ++-
  src/vulkan/wsi/wsi_common.h |8 +-
  src/vulkan/wsi/wsi_common_wayland.c |   19 +-
  src/vulkan/wsi/wsi_common_x11.c |3 +-
  9 files changed, 799 insertions(+), 521 deletions(-)



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[Mesa-dev] [PATCH] radv: Rework guard band calculation.

[Bas Nieuwenhuizen]

We want the guardband_x/y to be the largerst scalars such that each
viewport scaled by that amount is still a subrange of [-32767, 32767].

The old code has a couple of issues:
1) It used scissor instead of viewport_scissor, potentially taking into
   account a viewport that is too small and therefore selecting a scale
   that is too large.
2) Merging the viewports isn't ideal, as for example viewports with
   boundaries [0,1] and [1000, 1001] would allow a guardband scale of ~30k,
   while their union [0, 1001] only allows a scale of ~32.

The new code just determines the guardband per viewport and takes the minimum.

Signed-off-by: Bas Nieuwenhuizen 
---
 src/amd/vulkan/si_cmd_buffer.c | 52 ++
 1 file changed, 12 insertions(+), 40 deletions(-)

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index e176abe3869..bbcaf1009bd 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -504,22 +504,6 @@ get_viewport_xform(const VkViewport *viewport,
translate[2] = n;
 }
 
-static void
-get_viewport_xform_scissor(const VkRect2D *scissor,
-   float scale[2], float translate[2])
-{
-   float x = scissor->offset.x;
-   float y = scissor->offset.y;
-   float half_width = 0.5f * scissor->extent.width;
-   float half_height = 0.5f * scissor->extent.height;
-
-   scale[0] = half_width;
-   translate[0] = half_width + x;
-   scale[1] = half_height;
-   translate[1] = half_height + y;
-
-}
-
 void
 si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
   int count, const VkViewport *viewports)
@@ -579,26 +563,13 @@ static VkRect2D si_intersect_scissor(const VkRect2D *a, 
const VkRect2D *b) {
return ret;
 }
 
-static VkRect2D si_union_scissor(const VkRect2D *a, const VkRect2D *b) {
-   VkRect2D ret;
-   ret.offset.x = MIN2(a->offset.x, b->offset.x);
-   ret.offset.y = MIN2(a->offset.y, b->offset.y);
-   ret.extent.width = MAX2(a->offset.x + a->extent.width,
-   b->offset.x + b->extent.width) - ret.offset.x;
-   ret.extent.height = MAX2(a->offset.y + a->extent.height,
-b->offset.y + b->extent.height) - ret.offset.y;
-   return ret;
-}
-
-
 void
 si_write_scissors(struct radeon_winsys_cs *cs, int first,
   int count, const VkRect2D *scissors,
   const VkViewport *viewports, bool can_use_guardband)
 {
int i;
-   VkRect2D merged;
-   float scale[2], translate[2], guardband_x = 1.0, guardband_y = 1.0;
+   float scale[3], translate[3], guardband_x = INFINITY, guardband_y = 
INFINITY;
const float max_range = 32767.0f;
assert(count);
 
@@ -607,10 +578,14 @@ si_write_scissors(struct radeon_winsys_cs *cs, int first,
VkRect2D viewport_scissor = si_scissor_from_viewport(viewports 
+ i);
VkRect2D scissor = si_intersect_scissor([i], 
_scissor);
 
-   if (i)
-   merged = si_union_scissor(, );
-   else
-   merged = scissor;
+   get_viewport_xform(viewports + i, scale, translate);
+   if (scale[0] < 0.5)
+   scale[0] = 0.5;
+   if (scale[1] < 0.5)
+   scale[1] = 0.5;
+
+   guardband_x = MIN2(guardband_x, (max_range - abs(translate[0])) 
/ scale[0]);
+   guardband_y = MIN2(guardband_y, (max_range - abs(translate[1])) 
/ scale[1]);
 
radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
S_028250_TL_Y(scissor.offset.y) |
@@ -618,12 +593,9 @@ si_write_scissors(struct radeon_winsys_cs *cs, int first,
radeon_emit(cs, S_028254_BR_X(scissor.offset.x + 
scissor.extent.width) |
S_028254_BR_Y(scissor.offset.y + 
scissor.extent.height));
}
-
-   get_viewport_xform_scissor(, scale, translate);
-
-   if (can_use_guardband) {
-   guardband_x = (max_range - abs(translate[0])) / scale[0];
-   guardband_y = (max_range - abs(translate[1])) / scale[1];
+   if (!can_use_guardband) {
+   guardband_x = 1.0;
+   guardband_y = 1.0;
}
 
radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
-- 
2.12.1

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[Mesa-dev] [PATCH] travis: remove r600 as it requires llvm 3.8

[Christian Gmeiner]

At the moment travis ci failes with the following error:

checking for RADEON... yes
checking for RADEON... yes
configure: error: LLVM 3.8.0 or newer is required for r600
make: *** No targets specified and no makefile found.  Stop.

Signed-off-by: Christian Gmeiner 
---
 .travis.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.travis.yml b/.travis.yml
index a3b094f..b94d421 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -104,7 +104,7 @@ script:
   ./autogen.sh --enable-debug
 --with-egl-platforms=x11,drm
 --with-dri-drivers=i915,i965,radeon,r200,swrast,nouveau
-
--with-gallium-drivers=i915,nouveau,r300,r600,freedreno,svga,swrast,vc4,virgl,etnaviv,imx
+
--with-gallium-drivers=i915,nouveau,r300,freedreno,svga,swrast,vc4,virgl,etnaviv,imx
 --disable-llvm-shared-libs
 ;
   make && make check;
-- 
2.9.3

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Re: [Mesa-dev] [PATCH] radv: fix order of the guardband register emission.

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 


On Sun, Apr 2, 2017 at 6:47 AM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> y is vert, x is horiz.
>
> Noticed in visual inspection compared to radeonsi.
>
> Signed-off-by: Dave Airlie 
> ---
>  src/amd/vulkan/si_cmd_buffer.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
> index e847dcf..e176abe 100644
> --- a/src/amd/vulkan/si_cmd_buffer.c
> +++ b/src/amd/vulkan/si_cmd_buffer.c
> @@ -627,10 +627,10 @@ si_write_scissors(struct radeon_winsys_cs *cs, int 
> first,
> }
>
> radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
> -   radeon_emit(cs, fui(guardband_x));
> -   radeon_emit(cs, fui(1.0));
> radeon_emit(cs, fui(guardband_y));
> radeon_emit(cs, fui(1.0));
> +   radeon_emit(cs, fui(guardband_x));
> +   radeon_emit(cs, fui(1.0));
>  }
>
>  static inline unsigned
> --
> 2.9.3
>
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