Re: [Mesa-dev] [PATCH 07/12] i965/cnl: Restore lossless compression for sRGB formats

[Ben Widawsky]

On 17-04-15 18:27:33, Jason Ekstrand wrote:

On April 14, 2017 5:37:55 PM Anuj Phogat  wrote:


From: Ben Widawsky 

This support was removed on gen9 (it worked before then) and was brought back
for gen10.

Signed-off-by: Ben Widawsky 
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

index 467ada5..c8014b9 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -207,7 +207,7 @@ 
intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw,

   if (!brw->format_supported_as_render_target[mt->format])
  return false;

-   if (brw->gen >= 9) {
+   if (brw->gen == 9) {
  mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
  const uint32_t brw_format = brw_isl_format_for_mesa_format(linear_format);
  return isl_format_supports_ccs_e(>screen->devinfo, brw_format);


I thought sRGB was supported for CCS_E on CNL.  If so, we should 
update the table in isl_format_supports_ccs_e().  Also, I believe sRGB 
is supported for CCS_D even on sky lake, you just can't sample from 
it.




The patch predates ISL... yes, we should. Anuj, would you mind doing this?


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[Mesa-dev] [Bug 100690] [Regression, bisected] TotalWar: Warhammer corrupted graphics

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100690

Kenneth Graunke  changed:

   What|Removed |Added

 Attachment #131008|0   |1
is obsolete||

--- Comment #4 from Kenneth Graunke  ---
Created attachment 131012
  --> https://bugs.freedesktop.org/attachment.cgi?id=131012=edit
Patch to drop format-based completeness checks

Whoops, sorry...failed to git commit --amend before uploading the patch, so
that patch wouldn't compile.  Here's the one I actually tested.

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Re: [Mesa-dev] [PATCH 11/12] i965/cnl: Properly handle l3 configuration

[Francisco Jerez]

Ben Widawsky  writes:

> On 17-04-18 18:18:39, Francisco Jerez wrote:
>
> Most, if not all of the unrelated changes that snuck in were due to rebase.
> Anuj, would you mind fixing those? I tried my best to address the rest, but 
> I'm
> admittedly stumbling my way through some of the l3 programming.
>
>>Anuj Phogat  writes:
>>
>>> From: Ben Widawsky 
>>>
>>> V2: Squash the changes in one patch and rebased on master (Anuj).
>>>
>>> Signed-off-by: Ben Widawsky 
>>> Signed-off-by: Anuj Phogat 
>>> ---
>>>  src/intel/common/gen_l3_config.c | 43 
>>> ++--
>>>  1 file changed, 37 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/src/intel/common/gen_l3_config.c 
>>> b/src/intel/common/gen_l3_config.c
>>> index 4fe3503..f3e8793 100644
>>> --- a/src/intel/common/gen_l3_config.c
>>> +++ b/src/intel/common/gen_l3_config.c
>>> @@ -102,6 +102,26 @@ static const struct gen_l3_config chv_l3_configs[] = {
>>>  };
>>>
>>>  /**
>>> + * On CNL, RO clients are merged and shared with read/write space. As a 
>>> result
>>> + * we have fewer allocation parameters.
>>
>>The two sentences above make it sound like RO clients haven't been part
>>of the same partition until CNL.  They have.  I'd drop this.
>>
>
> So the difference I was trying to spell out is that the previous "IS" "C" and
> "T" fields do not exist in a programmable way.
>

I'm fine with spelling that out, but it isn't part of the list of
hardware changes introduced in CNL which is what the comment makes it
sound like.  AFAIA the RO clients have been merged together since as far
back as BDW, so the comment (with s/CNL/BDW/) probably belongs somewhere
close to the BDW L3 config table if you really want to document it
explicitly in some place.

>>> Also, programming does not require any
>>> + * back scaling. Programming simply works in 2k increments and is scaled 
>>> by the
>>> + * hardware.
>>
>>That's basically the case (up to the specific scale factor) on all
>>hardware, I'd drop this too.
>>
>
> I personally think the existing code isn't as self-documenting to me as it is 
> to
> you, and so I was trying to spell it out. I was trying to document, not show
> differentiation. In either event, I don't care if we keep this or leave it.
>

As for the previous sentence I don't have any objection against
documenting this piece of information, my complaint was just that in its
current form and context it seems very likely to be misinterpreted [and
misleading docs may be the only thing worse than no docs ;)].

>>> + */
>>> +static const struct gen_l3_config cnl_l3_configs[] = {
>>> +   /* SLM URB Rest  DC  RO */
>>
>>s/Rest/ALL/ (these are L3 partition enum labels), and align to the
>>column boundaries below.
>>
>
> Sure.
>
>>> +   {{  0, 64, 64,  0,  0 }},
>>> +   {{  0, 64,  0, 16, 48 }},
>>> +   {{  0, 48,  0, 16, 64 }},
>>> +   {{  0, 32,  0,  0, 96 }},
>>> +   {{  0, 32, 96,  0,  0 }},
>>> +   {{  0, 32,  0, 16, 80 }},
>>> +   {{ 32, 16, 80,  0,  0 }},
>>> +   {{ 32, 16,  0, 64, 16 }},
>>> +   {{ 32,  0, 96,  0,  0 }},
>>> +   {{ 0 }}
>>> +};
>>> +
>>> +/**
>>>   * Return a zero-terminated array of validated L3 configurations for the
>>>   * specified device.
>>>   */
>>> @@ -116,9 +136,11 @@ get_l3_configs(const struct gen_device_info *devinfo)
>>>return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
>>>
>>> case 9:
>>> -   case 10:
>>>return chv_l3_configs;
>>>
>>> +   case 10:
>>> +  return cnl_l3_configs;
>>> +
>>> default:
>>>unreachable("Not implemented");
>>> }
>>> @@ -258,13 +280,19 @@ get_l3_way_size(const struct gen_device_info *devinfo)
>>> if (devinfo->is_baytrail)
>>>return 2;
>>>
>>> -   else if (devinfo->gt == 1 ||
>>> -devinfo->is_cherryview ||
>>> -devinfo->is_broxton)
>>
>>Unrelated change sneaked in.
>>
>
> See above reply (not sure how this got in other than rebase).
>
>>> +   /* Way size is actually 6 * num_slices, because it's 2k per bank, and
>>> +* normally 3 banks per slice. However, on CNL+ this information isn't
>>> +* needed to setup the URB/l3 configuration. We fudge the answer here
>>> +* and then use the scaling to fix it up later.
>>> +*/
>>
>>The comment makes it sound like you're lying to the caller and returning
>>a bogus way size you're going to fix up later.  That's not the case
>>though, the value you're returning below is accurate for all CNL
>>configs.  6 * num_slices OTOH *would* be inaccurate.  I'd drop the
>>comment.
>>
>
> Anuj, would you mind doing what Curro asks?
>
>>> +   if (devinfo->gen >= 10)
>>> +  return 2 * devinfo->l3_banks;
>>> +
>>
>>It would be nice if we could use the 'l3_banks' devinfo field you just
>>added on previous gens too in order to simplify things.  I'm okay if you
>>don't feel like doing the clean up right away but maybe add a short
>>FINISHME 

Re: [Mesa-dev] [PATCH 11/12] i965/cnl: Properly handle l3 configuration

[Ben Widawsky]

On 17-04-18 18:18:39, Francisco Jerez wrote:

Most, if not all of the unrelated changes that snuck in were due to rebase.
Anuj, would you mind fixing those? I tried my best to address the rest, but I'm
admittedly stumbling my way through some of the l3 programming.


Anuj Phogat  writes:


From: Ben Widawsky 

V2: Squash the changes in one patch and rebased on master (Anuj).

Signed-off-by: Ben Widawsky 
Signed-off-by: Anuj Phogat 
---
 src/intel/common/gen_l3_config.c | 43 ++--
 1 file changed, 37 insertions(+), 6 deletions(-)

diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index 4fe3503..f3e8793 100644
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -102,6 +102,26 @@ static const struct gen_l3_config chv_l3_configs[] = {
 };

 /**
+ * On CNL, RO clients are merged and shared with read/write space. As a result
+ * we have fewer allocation parameters.


The two sentences above make it sound like RO clients haven't been part
of the same partition until CNL.  They have.  I'd drop this.



So the difference I was trying to spell out is that the previous "IS" "C" and
"T" fields do not exist in a programmable way.


Also, programming does not require any
+ * back scaling. Programming simply works in 2k increments and is scaled by the
+ * hardware.


That's basically the case (up to the specific scale factor) on all
hardware, I'd drop this too.



I personally think the existing code isn't as self-documenting to me as it is to
you, and so I was trying to spell it out. I was trying to document, not show
differentiation. In either event, I don't care if we keep this or leave it.


+ */
+static const struct gen_l3_config cnl_l3_configs[] = {
+   /* SLM URB Rest  DC  RO */


s/Rest/ALL/ (these are L3 partition enum labels), and align to the
column boundaries below.



Sure.


+   {{  0, 64, 64,  0,  0 }},
+   {{  0, 64,  0, 16, 48 }},
+   {{  0, 48,  0, 16, 64 }},
+   {{  0, 32,  0,  0, 96 }},
+   {{  0, 32, 96,  0,  0 }},
+   {{  0, 32,  0, 16, 80 }},
+   {{ 32, 16, 80,  0,  0 }},
+   {{ 32, 16,  0, 64, 16 }},
+   {{ 32,  0, 96,  0,  0 }},
+   {{ 0 }}
+};
+
+/**
  * Return a zero-terminated array of validated L3 configurations for the
  * specified device.
  */
@@ -116,9 +136,11 @@ get_l3_configs(const struct gen_device_info *devinfo)
   return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);

case 9:
-   case 10:
   return chv_l3_configs;

+   case 10:
+  return cnl_l3_configs;
+
default:
   unreachable("Not implemented");
}
@@ -258,13 +280,19 @@ get_l3_way_size(const struct gen_device_info *devinfo)
if (devinfo->is_baytrail)
   return 2;

-   else if (devinfo->gt == 1 ||
-devinfo->is_cherryview ||
-devinfo->is_broxton)


Unrelated change sneaked in.



See above reply (not sure how this got in other than rebase).


+   /* Way size is actually 6 * num_slices, because it's 2k per bank, and
+* normally 3 banks per slice. However, on CNL+ this information isn't
+* needed to setup the URB/l3 configuration. We fudge the answer here
+* and then use the scaling to fix it up later.
+*/


The comment makes it sound like you're lying to the caller and returning
a bogus way size you're going to fix up later.  That's not the case
though, the value you're returning below is accurate for all CNL
configs.  6 * num_slices OTOH *would* be inaccurate.  I'd drop the
comment.



Anuj, would you mind doing what Curro asks?


+   if (devinfo->gen >= 10)
+  return 2 * devinfo->l3_banks;
+


It would be nice if we could use the 'l3_banks' devinfo field you just
added on previous gens too in order to simplify things.  I'm okay if you
don't feel like doing the clean up right away but maybe add a short
FINISHME comment next to its definition in gen_device_info.h so we don't
forget about this (hopefully temporary) inconsistency.


+   /* XXX: Cherryview and Broxton are always gt1 */
+   if (devinfo->gt == 1)


Unrelated change.


   return 4;

-   else
-  return 8 * devinfo->num_slices;
+   return 8 * devinfo->num_slices;


Unrelated change.



I think here too it must have been a rebase change.


 }

 /**
@@ -274,6 +302,9 @@ get_l3_way_size(const struct gen_device_info *devinfo)
 static unsigned
 get_urb_size_scale(const struct gen_device_info *devinfo)
 {
+   if (devinfo->gen == 10)
+  return devinfo->l3_banks;
+


This seems bogus, AFAICT URB programming is done in size per slice units
(just like it was the case on previous gens), not in size per L3 bank
units.



We have parts which have different l3 banks per slice, and those seemed to need
to be programmed differently which is how I got to this. Tell us what you'd
recommend instead, and Anuj can try to run with that.

Thanks.


return (devinfo->gen >= 8 ? devinfo->num_slices : 1);
 }

Re: [Mesa-dev] [PATCH 3/3] r600g: remove unused sbcl env. variable

[Constantine Kharlamov]

Thank you, and congratulations on the new card :)

On 25.04.2017 04:26, Dieter Nützel wrote:
> For the series:
> 
> Tested-by: Dieter Nützel 
> 
> On Turks XT (6670).
> 
> radeonsi (2/3) NOT yet (only compile),
> my RX 580, 8 GB, Nitro+
> is coming on Friday/Saturday, Yea ;-)
> 
> Dieter
> 
> Am 23.04.2017 23:36, schrieb Constantine Kharlamov:
>> sb-based optimization was only used for older LLVM, whose support was removed
>> in 100796c15c3a1467d03abc424e6f1494da02f376 "gallium/radeon: drop support for
>> LLVM 3.5". Since then sbcl variable doesn't do anything.
>>
>> Signed-off-by: Constantine Kharlamov 
>> ---
>>  src/gallium/drivers/r600/r600_pipe.c   | 1 -
>>  src/gallium/drivers/r600/sb/notes.markdown | 1 -
>>  2 files changed, 2 deletions(-)
>>
>> diff --git a/src/gallium/drivers/r600/r600_pipe.c
>> b/src/gallium/drivers/r600/r600_pipe.c
>> index 12bf5517a9..a7b28a2d57 100644
>> --- a/src/gallium/drivers/r600/r600_pipe.c
>> +++ b/src/gallium/drivers/r600/r600_pipe.c
>> @@ -47,7 +47,6 @@ static const struct debug_named_value r600_debug_options[] 
>> = {
>>
>>  /* shader backend */
>>  { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
>> -{ "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
>>  { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print
>> the dumps)" },
>>  { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
>>  { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization 
>> passes" },
>> diff --git a/src/gallium/drivers/r600/sb/notes.markdown
>> b/src/gallium/drivers/r600/sb/notes.markdown
>> index 63c010883d..e48135c69c 100644
>> --- a/src/gallium/drivers/r600/sb/notes.markdown
>> +++ b/src/gallium/drivers/r600/sb/notes.markdown
>> @@ -13,7 +13,6 @@ Debugging
>>  There are new flags:
>>
>>  -   **nosb** - Disable sb backend for graphics shaders
>> --   **sbcl** - Enable optimization of compute shaders (experimental)
>>  -   **sbdry** - Dry run, optimize but use source bytecode -
>>  useful if you only want to check shader dumps
>>  without the risk of lockups and other problems
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Re: [Mesa-dev] [PATCH 2/2] radeonsi: disable primitive restart for non-strip prims based on app list

[Michel Dänzer]

On 25/04/17 01:43 AM, Nicolai Hähnle wrote:
> On 24.04.2017 18:32, Marek Olšák wrote:
>> On Mon, Apr 24, 2017 at 5:34 PM, Nicolai Hähnle 
>> wrote:
>>> On 24.04.2017 15:22, Marek Olšák wrote:

 From: Marek Olšák 
>>>
>>>
>>> I don't like it. This kind of app-specific override is what drirc was
>>> meant
>>> to provide. Having separate places for it is confusing.
>>
>> The question is: would other drivers want this code in st_draw_vbo?
>> For threaded gallium, we shouldn't put more stuff into st_draw_vbo.
>>
>> Alternatively, it can be a flag for pipe_screen::context_create to
>> enable this behavior in radeonsi and keep the list in drirc.
> 
> Is there a particular reason we can't let radeonsi (and other gallium
> drivers) access drirc directly?

Yeah, something like that would be a better approach. This patch is too
hackish.


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Re: [Mesa-dev] [PATCH] st/glsl_to_tgsi: drop the merge_registers() pass

[Ilia Mirkin]

It would kill nv30, I believe.

On Apr 24, 2017 10:30 PM, "Roland Scheidegger"  wrote:

> Am 24.04.2017 um 23:12 schrieb Rob Clark:
> > so I guess this is likely to hurt pipe drivers that don't (yet?)
> > have a real compiler backend.  (Ie. etnaviv and freedreno/a2xx.)  So
> > maybe it should be optional.
> I suppose softpipe, too? Though that's fine, noone cares if it gets a
> bit slower. Might even be nicer for debugging purposes...
>
> Roland
>
>
>
> > Also I wonder about the pre-llvm radeon gen's, since sb uses the
> > actual instruction encoding for IR between tgsi->sb and backend opt
> > passes..  iirc they have had problems when the tgsi code uses too
> > many registers.
> >
> > BR, -R
> >
> > On Mon, Apr 24, 2017 at 5:01 PM, Samuel Pitoiset
> >  wrote:
> >> The main goal of this pass to merge temporary registers in order to
> >> reduce the total number of registers and also to produce optimal
> >> TGSI code.
> >>
> >> In fact, compilers seem to be confused when temporary variables are
> >> already merged, maybe because it's done too early in the process.
> >>
> >> Removing the pass, reduce both the register pressure and the code
> >> size (TGSI is no longer optimized, but who cares?). shader-db
> >> results with RadeonSI and Nouveau are interesting.
> >>
> >> Nouveau:
> >>
> >> total instructions in shared programs : 3931608 -> 3929463
> >> (-0.05%) total gprs used in shared programs: 481255 -> 479014
> >> (-0.47%) total local used in shared programs   : 27481 -> 27381
> >> (-0.36%) total bytes used in shared programs   : 36031256 ->
> >> 36011120 (-0.06%)
> >>
> >> localgpr   inst  bytes helped  14
> >> 147113091309 hurt   1  88
> >> 384 384
> >>
> >> RadeonSI:
> >>
> >> PERCENTAGE DELTASShaders SGPRs VGPRs SpillSGPR
> >> SpillVGPR  PrivVGPR   Scratch  CodeSize  MaxWaves Waits
> >> 
> --
> >>
> >>
> All affected4906   -0.31 %   -0.40 %   -2.93 %  -20.00 %
> .  -20.00 %   -0.18 %0.19 % .
> >> 
> --
> >>
> >>
> Total  47109   -0.04 %   -0.05 %   -1.97 %   -7.14 %
> .   -0.30 %   -0.03 %0.02 % .
> >>
> >> Found by luck while fixing an issue in the TGSI dead code
> >> elimination pass which affects tex instructions with bindless
> >> samplers.
> >>
> >> Signed-off-by: Samuel Pitoiset  ---
> >> src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 62
> >> -- 1 file changed, 62 deletions(-)
> >>
> >> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> >> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index
> >> de7fe7837a..d033bdcc5a 100644 ---
> >> a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++
> >> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -565,7 +565,6 @@
> >> public: int eliminate_dead_code(void);
> >>
> >> void merge_two_dsts(void); -   void merge_registers(void); void
> >> renumber_registers(void);
> >>
> >> void emit_block_mov(ir_assignment *ir, const struct glsl_type
> >> *type, @@ -5262,66 +5261,6 @@
> >> glsl_to_tgsi_visitor::merge_two_dsts(void) } }
> >>
> >> -/* Merges temporary registers together where possible to reduce
> >> the number of - * registers needed to run a program. - * - *
> >> Produces optimal code only after copy propagation and dead code
> >> elimination - * have been run. */ -void
> >> -glsl_to_tgsi_visitor::merge_registers(void) -{ -   int *last_reads
> >> = rzalloc_array(mem_ctx, int, this->next_temp); -   int
> >> *first_writes = rzalloc_array(mem_ctx, int, this->next_temp); -
> >> struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct
> >> rename_reg_pair, this->next_temp); -   int i, j; -   int
> >> num_renames = 0; - -   /* Read the indices of the last read and
> >> first write to each temp register -* into an array so that we
> >> don't have to traverse the instruction list as -* much. */ -
> >> for (i = 0; i < this->next_temp; i++) { -  last_reads[i] = -1;
> >> -  first_writes[i] = -1; -   } -
> >> get_last_temp_read_first_temp_write(last_reads, first_writes); - -
> >> /* Start looking for registers with non-overlapping usages that can
> >> be -* merged together. */ -   for (i = 0; i < this->next_temp;
> >> i++) { -  /* Don't touch unused registers. */ -  if
> >> (last_reads[i] < 0 || first_writes[i] < 0) continue; - -  for
> >> (j = 0; j < this->next_temp; j++) { - /* Don't touch unused
> >> registers. */ - if (last_reads[j] < 0 || first_writes[j] <
> >> 0) continue; - - /* We can merge the two registers if the
> >> first write to j is after or -  * in the same instruction
> >> as the last read from i.  Note that the -  

Re: [Mesa-dev] [PATCH] st/glsl_to_tgsi: drop the merge_registers() pass

[Roland Scheidegger]

Am 24.04.2017 um 23:12 schrieb Rob Clark:
> so I guess this is likely to hurt pipe drivers that don't (yet?)
> have a real compiler backend.  (Ie. etnaviv and freedreno/a2xx.)  So
> maybe it should be optional.
I suppose softpipe, too? Though that's fine, noone cares if it gets a
bit slower. Might even be nicer for debugging purposes...

Roland



> Also I wonder about the pre-llvm radeon gen's, since sb uses the 
> actual instruction encoding for IR between tgsi->sb and backend opt 
> passes..  iirc they have had problems when the tgsi code uses too
> many registers.
> 
> BR, -R
> 
> On Mon, Apr 24, 2017 at 5:01 PM, Samuel Pitoiset 
>  wrote:
>> The main goal of this pass to merge temporary registers in order to
>> reduce the total number of registers and also to produce optimal
>> TGSI code.
>> 
>> In fact, compilers seem to be confused when temporary variables are
>> already merged, maybe because it's done too early in the process.
>> 
>> Removing the pass, reduce both the register pressure and the code 
>> size (TGSI is no longer optimized, but who cares?). shader-db
>> results with RadeonSI and Nouveau are interesting.
>> 
>> Nouveau:
>> 
>> total instructions in shared programs : 3931608 -> 3929463
>> (-0.05%) total gprs used in shared programs: 481255 -> 479014
>> (-0.47%) total local used in shared programs   : 27481 -> 27381
>> (-0.36%) total bytes used in shared programs   : 36031256 ->
>> 36011120 (-0.06%)
>> 
>> localgpr   inst  bytes helped  14
>> 147113091309 hurt   1  88
>> 384 384
>> 
>> RadeonSI:
>> 
>> PERCENTAGE DELTASShaders SGPRs VGPRs SpillSGPR
>> SpillVGPR  PrivVGPR   Scratch  CodeSize  MaxWaves Waits 
>> --
>>
>> 
All affected4906   -0.31 %   -0.40 %   -2.93 %  -20.00 %
.  -20.00 %   -0.18 %0.19 % .
>> --
>>
>> 
Total  47109   -0.04 %   -0.05 %   -1.97 %   -7.14 %
.   -0.30 %   -0.03 %0.02 % .
>> 
>> Found by luck while fixing an issue in the TGSI dead code
>> elimination pass which affects tex instructions with bindless
>> samplers.
>> 
>> Signed-off-by: Samuel Pitoiset  --- 
>> src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 62
>> -- 1 file changed, 62 deletions(-)
>> 
>> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
>> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index
>> de7fe7837a..d033bdcc5a 100644 ---
>> a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++
>> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -565,7 +565,6 @@
>> public: int eliminate_dead_code(void);
>> 
>> void merge_two_dsts(void); -   void merge_registers(void); void
>> renumber_registers(void);
>> 
>> void emit_block_mov(ir_assignment *ir, const struct glsl_type
>> *type, @@ -5262,66 +5261,6 @@
>> glsl_to_tgsi_visitor::merge_two_dsts(void) } }
>> 
>> -/* Merges temporary registers together where possible to reduce
>> the number of - * registers needed to run a program. - * - *
>> Produces optimal code only after copy propagation and dead code
>> elimination - * have been run. */ -void 
>> -glsl_to_tgsi_visitor::merge_registers(void) -{ -   int *last_reads
>> = rzalloc_array(mem_ctx, int, this->next_temp); -   int
>> *first_writes = rzalloc_array(mem_ctx, int, this->next_temp); -
>> struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct
>> rename_reg_pair, this->next_temp); -   int i, j; -   int
>> num_renames = 0; - -   /* Read the indices of the last read and
>> first write to each temp register -* into an array so that we
>> don't have to traverse the instruction list as -* much. */ -
>> for (i = 0; i < this->next_temp; i++) { -  last_reads[i] = -1; 
>> -  first_writes[i] = -1; -   } -
>> get_last_temp_read_first_temp_write(last_reads, first_writes); - -
>> /* Start looking for registers with non-overlapping usages that can
>> be -* merged together. */ -   for (i = 0; i < this->next_temp;
>> i++) { -  /* Don't touch unused registers. */ -  if
>> (last_reads[i] < 0 || first_writes[i] < 0) continue; - -  for
>> (j = 0; j < this->next_temp; j++) { - /* Don't touch unused
>> registers. */ - if (last_reads[j] < 0 || first_writes[j] <
>> 0) continue; - - /* We can merge the two registers if the
>> first write to j is after or -  * in the same instruction
>> as the last read from i.  Note that the -  * register at
>> index i will always be used earlier or at the same time -
>> * as the register at index j. */ - if (first_writes[i] <=
>> first_writes[j] && - last_reads[i] <= first_writes[j])
>> { -renames[num_renames].old_reg = j; -
>> 

Re: [Mesa-dev] r600g: Support spilling temp arrays

[Dieter Nützel]

Am 10.03.2017 01:44, schrieb Dieter Nützel:

Hello Glenn,

I've tested this on r600g, Turks XT / HD6670, 2 GB (same as you have?).
It was hard work to apply this on master. Do you have a rebase handy?

But works so far.

Am 05.03.2017 18:26, schrieb Glenn Kennard:

This patch series implements support for spilling temporary arrays on
R6xx/R7xx/Evergreen/NI if hardware GPR limits are exceeded. It opts 
for a
simple pessimistic scheme of spilling the largest arrays until things 
fit.


This fixes some subset of issues where "GPR limit exceeded" or "TGSI
translation error" is printed to the console.


LS2015 - Landwirtschafts-Simulator 2015 / FarmingSimulator 2015
https://www.farming-simulator.com
under 'wine' changed ouput from:

EE r600_shader.c:158 r600_pipe_shader_create - translation from TGSI 
failed !

EE r600_state_common.c:765 r600_shader_select - Failed to build shader
variant (type=0) -12
EE r600_shader.c:2523 r600_shader_from_tgsi - GPR limit exceeded -
shader requires 167 registers

to:
EE r600_shader.c:183 r600_pipe_shader_create - translation from TGSI 
failed !

EE r600_state_common.c:799 r600_shader_select - Failed to build shader
variant (type=0) -12
EE r600_shader.c:3862 r600_shader_from_tgsi - GPR limit exceeded -
shader requires -10 registers


Exercises left to reader:
* Test on R600/R700, I suspect R600 in particular might need some 
additional

  fixups for write masking in tgsi_src().
* Implement support for spilling regular TGSI temps. Most of the
  infrastructure needed is in this patch series so should be 
straightforward.

  This would fix the remaining GPR limit exceeded issues.


Our children can't wait for this...;-)))

Tested-by: Dieter Nützel 
GREAT work!


Hello Glenn,

any progress?
Maybe a rebase for current git?
My times on r600g come to an end...
RX 580, 8 GB, Nitro+ is coming on Friday/Saturday, Yea ;-)

Thanks and greetings!

Dieter
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Re: [Mesa-dev] [PATCH 3/3 v2] r600g: get rid of dummy pixel shader

[Dieter Nützel]

Am 12.04.2017 22:06, schrieb Dave Airlie:
On 13 April 2017 at 06:03, Markus Trippelsdorf  
wrote:

On 2017.04.12 at 20:45 +0100, Emil Velikov wrote:
On 12 April 2017 at 20:34, Constantine Kharlamov  
wrote:


>> I suspect this breaks because r600 more often fails to
>> compile some shaders,
>> and the hw requires a fragment shader and we use the empty one as a
>> fallback in that case.
>
> Ok, that wasn't obvious, I running the system with the patchset on HD5730, 
including
> piglit testing — so far is fine.
>
If in doubt ask the bug reporter(s) to test a patch on their 
machines.


Well, the question is why bother with this legacy code at all?
I would expect a much more conservative approach. Except for essential
patches to keep the hardware running, everything else should be
rejected. Nobody is expecting new features for this ancient hardware
anyway.


I do have 90% of GL4.3 for evergreen and newer done in a branch,

It's just a lack of time to fix the last few hangs and motivate myself
to get it posted/reviewied.

Then of course getting sb support.

Dave.


Hello Dave,

can you please send the link to your latest work on this?
So someone (we) can have a look and learn/maybe fix it.
Maybe Elie step in and offer fp64 for r600g if he has some time left.
My times on r600g come to an end...
RX 580, 8 GB, Nitro+ is coming on Friday/Saturday, Yea ;-)

Then I have to decide if I hold the Turks XT (6670) or to comp it.

Greetings around the world!

Dieter
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Re: [Mesa-dev] [PATCH v5 0/3] asynchronous pbo transfer with glthread

[Dieter Nützel]

Am 21.04.2017 12:11, schrieb Marek Olšák:

FWIW, I think this series can land, because glthread is not enabled by
default, and the libX11 issue is unrelated.

Marek



Gregory?

For the series:

Tested-by: Dieter Nützel 

On Turks XT (6670).

Dieter


On Apr 21, 2017 4:22 AM, "Michel Dänzer"  wrote:


On 21/04/17 09:01 AM, Marek Olšák wrote:

On Thu, Apr 20, 2017 at 9:44 PM, gregory hainaut
 wrote:

On Thu, 20 Apr 2017 20:01:00 +0200
Marek Olšák  wrote:


On Thu, Apr 20, 2017 at 6:53 PM, gregory hainaut
 wrote:

On Thu, 20 Apr 2017 11:57:08 +0200
Marek Olšák  wrote:


On Thu, Apr 20, 2017 at 10:28 AM, gregory hainaut
 wrote:

On Thu, 20 Apr 2017 12:29:11 +0900
Michel Dänzer  wrote:


On 20/04/17 01:54 AM, Gregory Hainaut wrote:

Hello,

Please find the latest version that include a small fix for

hash deletion. I

think the series is good now. Please review/ack it.


I'm afraid I have to NACK it. As discussed in the v4 cover

letter

thread, Mesa's glthread cannot make any libX11 API calls.




Hello Michel,

Just to be sure we are on the same line, let's me do a

summary.


PCSX2 does the following bad pattern
1/ no call to XInitThread
2/ XGetGeometry to get the size of the surface
3/ glDrawArray into the default framebuffer 0 (the window,

I'm not sure how to call it)

=> which seem to call DRI2GetBuffersWithFormat under the

hood. I guess to get the

associated buffer of the window.


So far it was (kind of) working fine because PCSX2 does tons

of PBO transfer. So glthread

was mostly synchronous.

This series removes the (useless) PBO transfer

synchronization. So now glthread is really

asynchronous and the above bad pattern crash as expected.

I didn't add any libX11 API call on the patches. And I don't

think we can remvove the DRI stuff.


Hum, I don't know what will be the impact on the perf but

potentially we can force a synchronization

when there is a draw to framebuffer 0.


Can you send us the backtrace when DRI2GetBuffersWithFormat is

called

by glDrawArrays?

Marek


Hello Marek, Michel,

Here the full backtrace.

#0  DRI2GetBuffersWithFormat (dpy=0xc6307e48,

drawable=104857784, width=0xdef348c0, height=0xdef348c4,
attachments=0xdcc15c88, count=1, outCount=0xdcc15c74) at dri2.c:464

#1  0xf05bac45 in dri2GetBuffersWithFormat

(driDrawable=0xdef348a8, width=0xdef348c0, height=0xdef348c4,
attachments=0xdcc15c88, count=1, out_count=0xdcc15c74,
loaderPrivate=0xdefc6ef0) at dri2_glx.c:894

#2  0xe3ec3111 in dri2_drawable_get_buffers (count=
pointer>, atts=0xdef252f8, drawable=0xdefc7b08) at dri2.c:285

#3  dri2_allocate_textures (ctx=0xdef15928,

drawable=0xdefc7b08, statts=0xdef252f8, statts_count=2) at
dri2.c:480

#4  0xe3ebcbb0 in dri_st_framebuffer_validate

(stctx=0xdef4ab10, stfbi=0xdefc7b08, statts=0xdef252f8, count=2,
out=0xdcc15d78) at dri_drawable.c:83

#5  0xe3d37afc in st_framebuffer_validate

(stfb=stfb@entry=0xdef24f58, st=st@entry=0xdef4ab10) at
state_tracker/st_manager.c:189

Note "print stfb->Base->Name" give me 0
#6  0xe3d38649 in st_manager_validate_framebuffers

(st=0xdef4ab10) at state_tracker/st_manager.c:869

#7  0xe3cd0580 in st_validate_state (st=0xdef4ab10,

pipeline=ST_PIPELINE_RENDER) at state_tracker/st_atom.c:174

#8  0xe3cf935d in st_draw_vbo (ctx=0xdef7f8f8,

prims=0xdcc15f40, nr_prims=1, ib=0x0, index_bounds_valid=1 '\001',
min_index=39911, max_index=39914, tfb_vertcount=0x0, stream=0,
indirect=0x0) at state_tracker/st_draw.c:191

#9  0xe3caf35e in vbo_draw_arrays (baseInstance=0,

numInstances=1, count=4, start=39911, mode=5, ctx=0xdef7f8f8) at
vbo/vbo_exec_array.c:427

#10 vbo_exec_DrawArrays (mode=5, start=39911, count=4) at

vbo/vbo_exec_array.c:575

#11 0xe3be4f07 in _mesa_unmarshal_DrawArrays (ctx=0xdef7f8f8,

cmd=0xc41574b0) at main/marshal_generated.c:26644

#12 _mesa_unmarshal_dispatch_cmd (ctx=0xdef7f8f8,

cmd=0xc41574b0) at main/marshal_generated.c:42457

#13 0xe3ba8af0 in glthread_unmarshal_batch (release_batch=true,

batch=0xc4157410, ctx=0xdef7f8f8) at main/glthread.c:64

#14 glthread_worker (data=0xdef7f8f8) at main/glthread.c:110



If this DRI2GetBuffersWithFormat call results in libX11 API

calls on the

glthread, that's a bug which needs to be fixed, either by

moving the

DRI2GetBuffersWithFormat call to the main thread or (if

possible) by

changing DRI2GetBuffersWithFormat to use XCB directly.


First, we need to understand why it's happening. Does the app

use the

front buffer? Does it ever call glDrawBuffer(GL_FRONT) or
glReadBuffer(GL_FRONT)?


Hello Marek,

No, I don't use the front buffer. I don't call glDrawBuffer for

the FB 0. So I think,

it should use GL_BACK.
Hum except if some 3rparty libs do something in my back.

In case it have any impact, I'm using either glXSwapIntervalEXT

or glXSwapIntervalMESA (if the former wasn't found)

to control 

Re: [Mesa-dev] [PATCH 3/3] r600g: remove unused sbcl env. variable

[Dieter Nützel]

For the series:

Tested-by: Dieter Nützel 

On Turks XT (6670).

radeonsi (2/3) NOT yet (only compile),
my RX 580, 8 GB, Nitro+
is coming on Friday/Saturday, Yea ;-)

Dieter

Am 23.04.2017 23:36, schrieb Constantine Kharlamov:
sb-based optimization was only used for older LLVM, whose support was 
removed
in 100796c15c3a1467d03abc424e6f1494da02f376 "gallium/radeon: drop 
support for

LLVM 3.5". Since then sbcl variable doesn't do anything.

Signed-off-by: Constantine Kharlamov 
---
 src/gallium/drivers/r600/r600_pipe.c   | 1 -
 src/gallium/drivers/r600/sb/notes.markdown | 1 -
 2 files changed, 2 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index 12bf5517a9..a7b28a2d57 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -47,7 +47,6 @@ static const struct debug_named_value 
r600_debug_options[] = {


/* shader backend */
{ "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
-   { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
{ "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print
the dumps)" },
 	{ "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" 
},
 	{ "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization 
passes" },

diff --git a/src/gallium/drivers/r600/sb/notes.markdown
b/src/gallium/drivers/r600/sb/notes.markdown
index 63c010883d..e48135c69c 100644
--- a/src/gallium/drivers/r600/sb/notes.markdown
+++ b/src/gallium/drivers/r600/sb/notes.markdown
@@ -13,7 +13,6 @@ Debugging
 There are new flags:

 -   **nosb** - Disable sb backend for graphics shaders
--   **sbcl** - Enable optimization of compute shaders 
(experimental)

 -   **sbdry** - Dry run, optimize but use source bytecode -
 useful if you only want to check shader dumps
 without the risk of lockups and other problems

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[Mesa-dev] [Bug 100690] [Regression, bisected] TotalWar: Warhammer corrupted graphics

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100690

--- Comment #3 from Kenneth Graunke  ---
Created attachment 131008
  --> https://bugs.freedesktop.org/attachment.cgi?id=131008=edit
Proposed patch (git am)

I suggested two options at Khronos: ignore min/mag filters (it makes no sense
to consider them), or...more likely...ignore format-based completeness rules.

Here's a patch that implements the latter.  If you're able to test it, could
you see if it fixes "Total War: WARHAMMER" rendering for you?  Thanks!

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[Mesa-dev] [Bug 100690] [Regression, bisected] TotalWar: Warhammer corrupted graphics

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100690

--- Comment #2 from Kenneth Graunke  ---
Thank you for finding and reporting this!

The game appears to be calling glCopyImageSubData() on a RGBA_UINT32 texture,
with only one miplevel, with min/mag filters set to GL_NEAREST_MIPMAP_LINEAR
and GL_LINEAR.  Mipmap completeness isn't the problem - it's that we started
paying attention to the min/mag filters and noticed that linear-filtering +
integer formats = incomplete textures.  See GL 4.5 Section 8.17:

   "A texture is complete unless any of the following conditions hold true:

* Any of:
   – The internal format of the texture is integer (see table 8.12).
   – The internal format is STENCIL_INDEX.
   – The internal format is DEPTH_STENCIL, and the value of
 DEPTH_STENCIL_TEXTURE_MODE for the texture is STENCIL_INDEX.

and either the magnification filter is not NEAREST, or the minification
filter
is neither NEAREST nor NEAREST_MIPMAP_NEAREST."

Arguably, this could be considered an application bug.  However, the GL 4.5
conformance suite mandated that this very case should work until about a week
before you reported this bug.  So, all the major drivers allowed this case.

I'm reopening the discussion at Khronos (internal bugzilla 16224) based on this
information.  I strongly suspect that they'll say this should be allowed (at
which point my patch is wrong), but I'm not certain exactly what cases will be
allowed yet.

In the meantime, I'm happy to have my patch reverted in Mesa.

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[Mesa-dev] [Bug 100690] [Regression, bisected] TotalWar: Warhammer corrupted graphics

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100690

--- Comment #1 from talonz  ---
I am also having this problem 
latest mesa-git & llvm-svn 
rx480

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Re: [Mesa-dev] [PATCH] autogen.sh: set default sendemail.to

[Dylan Baker]

I agree with Jason, autogen.sh shouldn't be doing anything except configuring
autotools. Perhaps a "initial-configuration.sh" script would be more
appropriate.

Just my two cents and not a hard NAK.

Dylan

Quoting Jason Ekstrand (2017-04-24 12:29:32)
> This seems like something that would be more appropriate to put on a 
> "getting started" page than autogen.sh.  The very last thing I (as a user 
> of it) would expect autogen.sh to do is monkey with my git config; local or 
> otherwise.
> 
> 
> On April 24, 2017 6:16:14 PM Emil Velikov  wrote:
> 
> > From: Emil Velikov 
> >
> > To ease patch submission process a tiny bit.
> >
> > Cc: Ben Widawsky 
> > Suggested-by: Ben Widawsky 
> > Signed-off-by: Emil Velikov 
> > ---
> >  autogen.sh | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/autogen.sh b/autogen.sh
> > index c8960971d24..d178880b407 100755
> > --- a/autogen.sh
> > +++ b/autogen.sh
> > @@ -6,6 +6,9 @@ test -z "$srcdir" && srcdir=.
> >  ORIGDIR=`pwd`
> >  cd "$srcdir"
> >
> > +git config --local --get sendemail.to >/dev/null ||
> > +git config --local sendemail.to "mesa-dev@lists.freedesktop.org" 
> > 2>/dev/null
> > +
> >  autoreconf --force --verbose --install || exit 1
> >  cd "$ORIGDIR" || exit $?
> >
> > --
> > 2.12.2
> >
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> 
> 
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Re: [Mesa-dev] [PATCH 1/2] mesa: create locked version of HashWalk

[Michael Schellenberger Costa]

Him Tim,

I hadnt had my morning coffee butdidnt you do it the other way around?

It looks like, that "_mesa_HashWalk" ist he locked and "_mesa_HashWalkLocked" 
the unlocked version.

Michael

-Ursprüngliche Nachricht-
Von: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] Im Auftrag von 
Timothy Arceri
Gesendet: Montag, 24. April 2017 07:59
An: mesa-dev@lists.freedesktop.org
Cc: Timothy Arceri 
Betreff: [Mesa-dev] [PATCH 1/2] mesa: create locked version of HashWalk

---
 src/mesa/main/hash.c | 34 ++
 src/mesa/main/hash.h |  5 +
 2 files changed, 31 insertions(+), 8 deletions(-)

diff --git a/src/mesa/main/hash.c b/src/mesa/main/hash.c index b7a7bd9..a3772bd 
100644
--- a/src/mesa/main/hash.c
+++ b/src/mesa/main/hash.c
@@ -404,40 +404,58 @@ _mesa_HashDeleteAll(struct _mesa_HashTable *table,  }
 
 
 /**
  * Walk over all entries in a hash table, calling callback function for each.
  * \param table  the hash table to walk
  * \param callback  the callback function
  * \param userData  arbitrary pointer to pass along to the callback
  *  (this is typically a struct gl_context pointer)
  */
+static void
+hash_walk_unlocked(const struct _mesa_HashTable *table,
+   void (*callback)(GLuint key, void *data, void *userData),
+   void *userData)
+{
+   assert(table);
+   assert(callback);
+
+   struct hash_entry *entry;
+   hash_table_foreach(table->ht, entry) {
+  callback((uintptr_t)entry->key, entry->data, userData);
+   }
+   if (table->deleted_key_data)
+  callback(DELETED_KEY_VALUE, table->deleted_key_data, userData); }
+
+
 void
 _mesa_HashWalk(const struct _mesa_HashTable *table,
void (*callback)(GLuint key, void *data, void *userData),
void *userData)
 {
/* cast-away const */
struct _mesa_HashTable *table2 = (struct _mesa_HashTable *) table;
-   struct hash_entry *entry;
 
-   assert(table);
-   assert(callback);
mtx_lock(>Mutex);
-   hash_table_foreach(table->ht, entry) {
-  callback((uintptr_t)entry->key, entry->data, userData);
-   }
-   if (table->deleted_key_data)
-  callback(DELETED_KEY_VALUE, table->deleted_key_data, userData);
+   hash_walk_unlocked(table, callback, userData);
mtx_unlock(>Mutex);
 }
 
+void
+_mesa_HashWalkLocked(const struct _mesa_HashTable *table,
+   void (*callback)(GLuint key, void *data, void *userData),
+   void *userData)
+{
+   hash_walk_unlocked(table, callback, userData); }
+
 static void
 debug_print_entry(GLuint key, void *data, void *userData)  {
_mesa_debug(NULL, "%u %p\n", key, data);  }
 
 /**
  * Dump contents of hash table for debugging.
  *
  * \param table the hash table.
diff --git a/src/mesa/main/hash.h b/src/mesa/main/hash.h index 52a6c5d..9eb0f0e 
100644
--- a/src/mesa/main/hash.h
+++ b/src/mesa/main/hash.h
@@ -59,20 +59,25 @@ extern void _mesa_HashRemoveLocked(struct _mesa_HashTable 
*table, GLuint key);  extern void  _mesa_HashDeleteAll(struct _mesa_HashTable 
*table,
 void (*callback)(GLuint key, void *data, void *userData),
 void *userData);
 
 extern void
 _mesa_HashWalk(const struct _mesa_HashTable *table,
void (*callback)(GLuint key, void *data, void *userData),
void *userData);
 
+extern void
+_mesa_HashWalkLocked(const struct _mesa_HashTable *table,
+ void (*callback)(GLuint key, void *data, void *userData),
+ void *userData);
+
 extern void _mesa_HashPrint(const struct _mesa_HashTable *table);
 
 extern GLuint _mesa_HashFindFreeKeyBlock(struct _mesa_HashTable *table, GLuint 
numKeys);
 
 extern GLuint
 _mesa_HashNumEntries(const struct _mesa_HashTable *table);
 
 extern void _mesa_test_hash_functions(void);
 
 
--
2.9.3

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Re: [Mesa-dev] [PATCH 4/4] mesa: tidy up left over APPLE_vertex_array_object semantics

[Timothy Arceri]

On 25/04/17 01:30, Nicolai Hähnle wrote:

On 24.04.2017 12:28, Timothy Arceri wrote:



On 24/04/17 20:13, Nicolai Hähnle wrote:

On 24.04.2017 07:28, Timothy Arceri wrote:

---
 src/mesa/main/arrayobj.c | 11 +--
 src/mesa/main/attrib.c   | 23 +++
 src/mesa/main/mtypes.h   | 16 
 src/mesa/main/varray.c   |  2 +-
 4 files changed, 9 insertions(+), 43 deletions(-)

diff --git a/src/mesa/main/arrayobj.c b/src/mesa/main/arrayobj.c
index c52a07b..82c00fb 100644
--- a/src/mesa/main/arrayobj.c
+++ b/src/mesa/main/arrayobj.c
@@ -443,30 +443,21 @@ _mesa_BindVertexArray( GLuint id )
}
else {
   /* non-default array object */
   newObj = _mesa_lookup_vao(ctx, id);
   if (!newObj) {
  _mesa_error(ctx, GL_INVALID_OPERATION,
  "glBindVertexArray(non-gen name)");
  return;
   }

-  if (!newObj->EverBound) {
- /* The "Interactions with APPLE_vertex_array_object"
section of the
-  * GL_ARB_vertex_array_object spec says:
-  *
-  * "The first bind call, either BindVertexArray or
-  * BindVertexArrayAPPLE, determines the semantic of the
object."
-  */
- newObj->ARBsemantics = GL_TRUE;
- newObj->EverBound = GL_TRUE;
-  }
+  newObj->EverBound = GL_TRUE;
}

if (ctx->Array.DrawMethod == DRAW_ARRAYS) {
   /* The _DrawArrays pointer is pointing at the VAO being
unbound and
* that VAO may be in the process of being deleted. If it's
not going
* to be deleted, this will have no effect, because the
pointer needs
* to be updated by the VBO module anyway.
*
* Before the VBO module can update the pointer, we have to
set it
* to NULL for drivers not to set up arrays which are not bound,
diff --git a/src/mesa/main/attrib.c b/src/mesa/main/attrib.c
index 87d3276..dbcfb4e 100644
--- a/src/mesa/main/attrib.c
+++ b/src/mesa/main/attrib.c
@@ -1472,23 +1472,20 @@ copy_pixelstore(struct gl_context *ctx,
 static void
 copy_array_object(struct gl_context *ctx,
   struct gl_vertex_array_object *dest,
   struct gl_vertex_array_object *src)
 {
GLuint i;

/* skip Name */
/* skip RefCount */

-   /* In theory must be the same anyway, but on recreate make sure
it matches */
-   dest->ARBsemantics = src->ARBsemantics;
-
for (i = 0; i < ARRAY_SIZE(src->VertexAttrib); i++) {
   _mesa_copy_client_array(ctx, >_VertexAttrib[i],
>_VertexAttrib[i]);
   _mesa_copy_vertex_attrib_array(ctx, >VertexAttrib[i],
>VertexAttrib[i]);
   _mesa_copy_vertex_buffer_binding(ctx, >BufferBinding[i],
>BufferBinding[i]);
}

/* _Enabled must be the same than on push */
dest->_Enabled = src->_Enabled;
/* The bitmask of bound VBOs needs to match the VertexBinding
array */
dest->VertexAttribBufferMask = src->VertexAttribBufferMask;
@@ -1550,56 +1547,50 @@ save_array_attrib(struct gl_context *ctx,
 }

 /**
  * Restore the content of src to dest.
  */
 static void
 restore_array_attrib(struct gl_context *ctx,
  struct gl_array_attrib *dest,
  struct gl_array_attrib *src)
 {
+   bool is_vao_name_zero = src->VAO->Name == 0;
+
/* The ARB_vertex_array_object spec says:
 *
 * "BindVertexArray fails and an INVALID_OPERATION error is
generated
 * if array is not a name returned from a previous call to
 * GenVertexArrays, or if such a name has since been deleted
with
 * DeleteVertexArrays."
 *
 * Therefore popping a deleted VAO cannot magically recreate it.
-*
-* The semantics of objects created using
APPLE_vertex_array_objects behave
-* differently.  These objects expect to be recreated by pop.  
Alas.

 */
-   const bool arb_vao = (src->VAO->Name != 0
- && src->VAO->ARBsemantics);
-
-   if (arb_vao && !_mesa_IsVertexArray(src->VAO->Name))
+   if (!is_vao_name_zero && !_mesa_IsVertexArray(src->VAO->Name))
   return;

_mesa_BindVertexArray(src->VAO->Name);

/* Restore or recreate the buffer objects by the names ... */
-   if (!arb_vao
-   || src->ArrayBufferObj->Name == 0
-   || _mesa_IsBuffer(src->ArrayBufferObj->Name)) {
+   if (is_vao_name_zero || src->ArrayBufferObj->Name == 0 ||
+   _mesa_IsBuffer(src->ArrayBufferObj->Name)) {
   /* ... and restore its content */
   copy_array_attrib(ctx, dest, src, false);

   _mesa_BindBuffer(GL_ARRAY_BUFFER_ARB,
   src->ArrayBufferObj->Name);
} else {
   copy_array_attrib(ctx, dest, src, true);
}

-   if (!arb_vao
-   || src->VAO->IndexBufferObj->Name == 0
-   || _mesa_IsBuffer(src->VAO->IndexBufferObj->Name))
+   if (is_vao_name_zero || src->VAO->IndexBufferObj->Name == 0 ||
+   _mesa_IsBuffer(src->VAO->IndexBufferObj->Name))
   _mesa_BindBuffer(GL_ELEMENT_ARRAY_BUFFER_ARB,
   src->VAO->IndexBufferObj->Name);
 }

 /**
  * 

Re: [Mesa-dev] [PATCH 3/4] glsl: Merge if-simplification and conditional discard optimization

[Matt Turner]

On Thu, Apr 6, 2017 at 12:49 PM, Thomas Helland
 wrote:
> The conditional discard pass follows the same pattern, so merge the
> two, and avoid running the visitor two times.
> ---
>  src/compiler/Makefile.sources |  1 -
>  src/compiler/glsl/glsl_parser_extras.cpp  |  1 -
>  src/compiler/glsl/ir_optimization.h   |  1 -
>  src/compiler/glsl/opt_conditional_discard.cpp | 88 
> ---
>  src/compiler/glsl/opt_if_simplification.cpp   | 50 +++
>  5 files changed, 39 insertions(+), 102 deletions(-)
>  delete mode 100644 src/compiler/glsl/opt_conditional_discard.cpp
>
> diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
> index 5197c31bb3..817ab3a755 100644
> --- a/src/compiler/Makefile.sources
> +++ b/src/compiler/Makefile.sources
> @@ -114,7 +114,6 @@ LIBGLSL_FILES = \
> glsl/lower_ubo_reference.cpp \
> glsl/opt_algebraic.cpp \
> glsl/opt_array_splitting.cpp \
> -   glsl/opt_conditional_discard.cpp \
> glsl/opt_constant_folding.cpp \
> glsl/opt_constant_propagation.cpp \
> glsl/opt_constant_variable.cpp \
> diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
> b/src/compiler/glsl/glsl_parser_extras.cpp
> index 307e0d6215..fe25c23ccc 100644
> --- a/src/compiler/glsl/glsl_parser_extras.cpp
> +++ b/src/compiler/glsl/glsl_parser_extras.cpp
> @@ -2139,7 +2139,6 @@ do_common_optimization(exec_list *ir, bool linked,
> }
> propagate_invariance(ir);
> OPT(do_if_simplification, ir);
> -   OPT(opt_conditional_discard, ir);
> OPT(do_copy_propagation, ir);
> OPT(do_copy_propagation_elements, ir);
>
> diff --git a/src/compiler/glsl/ir_optimization.h 
> b/src/compiler/glsl/ir_optimization.h
> index 5d57ca85fd..022b7ab12f 100644
> --- a/src/compiler/glsl/ir_optimization.h
> +++ b/src/compiler/glsl/ir_optimization.h
> @@ -93,7 +93,6 @@ bool ir_constant_fold(ir_rvalue **rvalue);
>  bool do_rebalance_tree(exec_list *instructions);
>  bool do_algebraic(exec_list *instructions, bool native_integers,
>const struct gl_shader_compiler_options *options);
> -bool opt_conditional_discard(exec_list *instructions);
>  bool do_constant_folding(exec_list *instructions);
>  bool do_constant_variable(exec_list *instructions);
>  bool do_constant_variable_unlinked(exec_list *instructions);
> diff --git a/src/compiler/glsl/opt_conditional_discard.cpp 
> b/src/compiler/glsl/opt_conditional_discard.cpp
> deleted file mode 100644
> index 6d8a23460d..00
> --- a/src/compiler/glsl/opt_conditional_discard.cpp
> +++ /dev/null
> @@ -1,88 +0,0 @@
> -/*
> - * Copyright © 2014 Intel Corporation
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the "Software"),
> - * to deal in the Software without restriction, including without limitation
> - * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> - * and/or sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice (including the next
> - * paragraph) shall be included in all copies or substantial portions of the
> - * Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> - * DEALINGS IN THE SOFTWARE.
> - */
> -
> -/**
> - * \file opt_conditional_discard.cpp
> - *
> - * Replace
> - *
> - *if (cond) discard;
> - *
> - * with
> - *
> - *(discard )
> - */
> -
> -#include "compiler/glsl_types.h"
> -#include "ir.h"
> -
> -namespace {
> -
> -class opt_conditional_discard_visitor : public ir_hierarchical_visitor {
> -public:
> -   opt_conditional_discard_visitor()
> -   {
> -  progress = false;
> -   }
> -
> -   ir_visitor_status visit_leave(ir_if *);
> -
> -   bool progress;
> -};
> -
> -} /* anonymous namespace */
> -
> -bool
> -opt_conditional_discard(exec_list *instructions)
> -{
> -   opt_conditional_discard_visitor v;
> -   v.run(instructions);
> -   return v.progress;
> -}
> -
> -ir_visitor_status
> -opt_conditional_discard_visitor::visit_leave(ir_if *ir)
> -{
> -   /* Look for "if (...) discard" with no else clause or extra statements. */
> -   if (ir->then_instructions.is_empty() ||
> -   !ir->then_instructions.get_head_raw()->next->is_tail_sentinel() ||
> -   !((ir_instruction *) 
> ir->then_instructions.get_head_raw())->as_discard() ||
> -   !ir->else_instructions.is_empty())
> -   

Re: [Mesa-dev] [PATCH 1/4] mesa: only lock framebuffer in compat profile

[Timothy Arceri]

On 24/04/17 22:51, Fredrik Höglund wrote:

On Monday 24 April 2017, Timothy Arceri wrote:

 From the EXT_framebuffer_object spec:

"Framebuffer objects created with the commands defined
by the  GL_EXT_framebuffer_object extension are defined
to be shared, while FBOs created with commands defined
by the OpenGL core or GL_ARB_framebuffer_object
extension are defined *not* to be shared.  However, the
following functions are viewed as aliases (in particular
the opcodes for X are also the same) between the functions
of GL_EXT_framebuffer_object and
GL_ARB_framebuffer_object:

   ...

Since the above pairs are aliases, the functions of a
pair are equivalent.  Note that the functions
BindFramebuffer and BindFramebufferEXT are not aliases
and neither are the functions BindRenderbuffer and
BindRenderbufferEXT.  Because object creation  occurs
when the framebuffer object is bound for the first time,
a framebuffer object can be shared across contexts only
if it was first bound with BindFramebufferEXT.
Framebuffers first bound with BindFramebuffer may not
be shared across contexts.  Framebuffer objects created
with BindFramebufferEXT may subsequently be bound using
BindFramebuffer.  Framebuffer objects created with
BindFramebuffer may be bound with BindFramebufferEXT
provided they are bound to the same context they were
created on."

So in theory we could have a flag that is set by the bind
functions to decide if to lock or not. However we only
expose GL_EXT_framebuffer_object in compat profile so this
change just uses that to decide if we should lock or not.
---
  src/mesa/main/fbobject.c| 45 ++
  src/mesa/main/framebuffer.c | 60 +++--
  2 files changed, 76 insertions(+), 29 deletions(-)

diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index d486d01..0f2298d 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -145,22 +145,28 @@ _mesa_lookup_renderbuffer_err(struct gl_context *ctx, 
GLuint id,
   * Helper routine for getting a gl_framebuffer.
   */
  struct gl_framebuffer *
  _mesa_lookup_framebuffer(struct gl_context *ctx, GLuint id)
  {
 struct gl_framebuffer *fb;
  
 if (id == 0)

return NULL;
  
-   fb = (struct gl_framebuffer *)

-  _mesa_HashLookup(ctx->Shared->FrameBuffers, id);
+   if (ctx->API != API_OPENGL_COMPAT) {
+  fb = (struct gl_framebuffer *)
+ _mesa_HashLookupLocked(ctx->Shared->FrameBuffers, id);


Aside from the issue of mixed core/compatibility share groups, the hash
table is still in gl_shared_state, so it can still be accessed by multiple
threads simultaneously.


Hmm. This is a good point. I think I'll try this again using the bind 
functions to tell the difference as intended and use a hash in the ctx 
rather than shared state for the ARB version.


Thanks.




+   } else {
+  fb = (struct gl_framebuffer *)
+ _mesa_HashLookup(ctx->Shared->FrameBuffers, id);
+   }
+
 return fb;
  }
  
  
  /**

   * A convenience function for direct state access that throws
   * GL_INVALID_OPERATION if the framebuffer doesn't exist.
   */
  struct gl_framebuffer *
  _mesa_lookup_framebuffer_err(struct gl_context *ctx, GLuint id,
@@ -542,21 +548,22 @@ set_renderbuffer_attachment(struct gl_context *ctx,
   * Attach a renderbuffer object to a framebuffer object.
   */
  void
  _mesa_FramebufferRenderbuffer_sw(struct gl_context *ctx,
   struct gl_framebuffer *fb,
   GLenum attachment,
   struct gl_renderbuffer *rb)
  {
 struct gl_renderbuffer_attachment *att;
  
-   mtx_lock(>Mutex);

+   if (ctx->API == API_OPENGL_COMPAT)
+  mtx_lock(>Mutex);
  
 att = get_attachment(ctx, fb, attachment, NULL);

 assert(att);
 if (rb) {
set_renderbuffer_attachment(ctx, att, rb);
if (attachment == GL_DEPTH_STENCIL_ATTACHMENT) {
   /* do stencil attachment here (depth already done above) */
   att = get_attachment(ctx, fb, GL_STENCIL_ATTACHMENT_EXT, NULL);
   assert(att);
   set_renderbuffer_attachment(ctx, att, rb);
@@ -568,21 +575,22 @@ _mesa_FramebufferRenderbuffer_sw(struct gl_context *ctx,
if (attachment == GL_DEPTH_STENCIL_ATTACHMENT) {
   /* detach stencil (depth was detached above) */
   att = get_attachment(ctx, fb, GL_STENCIL_ATTACHMENT_EXT, NULL);
   assert(att);
   remove_attachment(ctx, att);
}
 }
  
 invalidate_framebuffer(fb);
  
-   mtx_unlock(>Mutex);

+   if (ctx->API == API_OPENGL_COMPAT)
+  mtx_unlock(>Mutex);
  }
  
  
  /**

   * Fallback for ctx->Driver.ValidateFramebuffer()
   * Check if the renderbuffer's formats are supported by the software
   * renderer.
   * Drivers should probably override this.
   */
  void
@@ -2583,21 

[Mesa-dev] [PATCH] gallium: remove u_caps.c/h interface

[Samuel Pitoiset]

No longer used.

Signed-off-by: Samuel Pitoiset 
---
 src/gallium/auxiliary/Makefile.sources |   2 -
 src/gallium/auxiliary/util/u_caps.c| 267 -
 src/gallium/auxiliary/util/u_caps.h|  71 -
 3 files changed, 340 deletions(-)
 delete mode 100644 src/gallium/auxiliary/util/u_caps.c
 delete mode 100644 src/gallium/auxiliary/util/u_caps.h

diff --git a/src/gallium/auxiliary/Makefile.sources 
b/src/gallium/auxiliary/Makefile.sources
index c3a3af9fbc..dbdb3ca815 100644
--- a/src/gallium/auxiliary/Makefile.sources
+++ b/src/gallium/auxiliary/Makefile.sources
@@ -192,8 +192,6 @@ C_SOURCES := \
util/u_box.h \
util/u_cache.c \
util/u_cache.h \
-   util/u_caps.c \
-   util/u_caps.h \
util/u_cpu_detect.c \
util/u_cpu_detect.h \
util/u_debug.c \
diff --git a/src/gallium/auxiliary/util/u_caps.c 
b/src/gallium/auxiliary/util/u_caps.c
deleted file mode 100644
index cd005d68b3..00
--- a/src/gallium/auxiliary/util/u_caps.c
+++ /dev/null
@@ -1,267 +0,0 @@
-/**
- *
- * Copyright 2010 Vmware, Inc.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **/
-
-#include "pipe/p_screen.h"
-#include "util/u_format.h"
-#include "util/u_debug.h"
-#include "u_caps.h"
-
-/**
- * Iterates over a list of caps checks as defined in u_caps.h. Should
- * all checks pass returns TRUE and out is set to the last element of
- * the list (TERMINATE). Should any check fail returns FALSE and set
- * out to the index of the start of the first failing check.
- */
-boolean
-util_check_caps_out(struct pipe_screen *screen, const unsigned *list, int *out)
-{
-   int i, tmpi;
-   float tmpf;
-
-   for (i = 0; list[i];) {
-  switch(list[i++]) {
-  case UTIL_CAPS_CHECK_CAP:
- if (!screen->get_param(screen, list[i++])) {
-*out = i - 2;
-return FALSE;
- }
- break;
-  case UTIL_CAPS_CHECK_INT:
- tmpi = screen->get_param(screen, list[i++]);
- if (tmpi < (int)list[i++]) {
-*out = i - 3;
-return FALSE;
- }
- break;
-  case UTIL_CAPS_CHECK_FLOAT:
- tmpf = screen->get_paramf(screen, list[i++]);
- if (tmpf < (float)list[i++]) {
-*out = i - 3;
-return FALSE;
- }
- break;
-  case UTIL_CAPS_CHECK_FORMAT:
- if (!screen->is_format_supported(screen,
-  list[i++],
-  PIPE_TEXTURE_2D,
-  0,
-  PIPE_BIND_SAMPLER_VIEW)) {
-*out = i - 2;
-return FALSE;
- }
- break;
-  case UTIL_CAPS_CHECK_SHADER:
- tmpi = screen->get_shader_param(screen, list[i] >> 24, list[i] & ((1 
<< 24) - 1));
- ++i;
- if (tmpi < (int)list[i++]) {
-*out = i - 3;
-return FALSE;
- }
- break;
-  case UTIL_CAPS_CHECK_UNIMPLEMENTED:
- *out = i - 1;
- return FALSE;
-  default:
- assert(!"Unsupported check");
- return FALSE;
-  }
-   }
-
-   *out = i;
-   return TRUE;
-}
-
-/**
- * Iterates over a list of caps checks as defined in u_caps.h.
- * Returns TRUE if all caps checks pass returns FALSE otherwise.
- */
-boolean
-util_check_caps(struct pipe_screen *screen, const unsigned *list)
-{
-   int out;
-   return util_check_caps_out(screen, list, );
-}
-
-
-/*
- * Below follows some demo lists.
- *
- * None of these lists are exhausting lists of what is
- * actually needed to support said API and more here for
- * as example on how to uses the above functions. 

Re: [Mesa-dev] [PATCH v02 06/37] genxml: Add alias for MOCS.

[Rafael Antognolli]

On Mon, Apr 24, 2017 at 03:59:07PM -0700, Kenneth Graunke wrote:
> On Monday, April 24, 2017 3:19:01 PM PDT Rafael Antognolli wrote:
> > Use an alias, so we can set the same value as the #define's.
> > 
> > Signed-off-by: Rafael Antognolli 
> > ---
> >  src/intel/genxml/gen8.xml | 1 +
> >  src/intel/genxml/gen9.xml | 1 +
> >  2 files changed, 2 insertions(+)
> > 
> > diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
> > index 408d241..2908082 100644
> > --- a/src/intel/genxml/gen8.xml
> > +++ b/src/intel/genxml/gen8.xml
> > @@ -2064,6 +2064,7 @@
> >  
> >  
> >   > type="MEMORY_OBJECT_CONTROL_STATE"/>
> > +
> >   > type="bool"/>
> >   > end="52" type="bool"/>
> >   > type="address"/>
> > diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
> > index 59daa31..09b9464 100644
> > --- a/src/intel/genxml/gen9.xml
> > +++ b/src/intel/genxml/gen9.xml
> > @@ -2246,6 +2246,7 @@
> >  
> >  
> >   > type="MEMORY_OBJECT_CONTROL_STATE"/>
> > +
> >   > type="bool"/>
> >   > end="52" type="bool"/>
> >   > type="address"/>
> > 
> 
> This seems a bit strange...we're only changing this in the stream out
> packets, and only on Gen8-9?

I only changed this where we were actually going to use it. I don't know
why, but we don't set MOCS for gen7 on stream out packets (or maybe it
was just 0). I'll double check this, and see what we are supposed to
set.

> I've wondered whether we should just use a uint everywhere.  On Gen9+
> it's just an index into the kernel tables, with no hardware-mandated
> meaning.  On earlier platforms, it changed for every piece of hardware.
> 
> I feel like a macro to construct MOCS values on earlier platforms
> would work as well as genxml.  *shrug*

Either way works for me.
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Re: [Mesa-dev] [PATCH v02 10/37] genxml: Rename "Function Enable" to "Enable".

[Kenneth Graunke]

On Monday, April 24, 2017 3:19:05 PM PDT Rafael Antognolli wrote:
> Rename that field name on genxml for:
>- 3DSTATE_GS - gen6+
>- 3DSTATE_DS - gen7+
>- 3DSTATE_HS - gen7+
> 
> Signed-off-by: Rafael Antognolli 
> ---
>  src/intel/genxml/gen6.xml| 2 +-
>  src/intel/genxml/gen7.xml| 6 +++---
>  src/intel/genxml/gen75.xml   | 6 +++---
>  src/intel/genxml/gen8.xml| 6 +++---
>  src/intel/genxml/gen9.xml| 6 +++---
>  src/intel/vulkan/genX_pipeline.c | 6 +++---
>  6 files changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
> index 2173dbf..2cb9419 100644
> --- a/src/intel/genxml/gen6.xml
> +++ b/src/intel/genxml/gen6.xml
> @@ -1014,7 +1014,7 @@
>  
>   type="bool"/>
>   type="uint"/>
> -
> +
>
>  
>
> diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
> index 6af1cbe..b4407d4 100644
> --- a/src/intel/genxml/gen7.xml
> +++ b/src/intel/genxml/gen7.xml
> @@ -1101,7 +1101,7 @@
>  
>   type="bool"/>
>  
> -
> +
>
>  
>
> @@ -1162,7 +1162,7 @@
>
>  
>  
> -
> +
>  
>
>  
> @@ -1199,7 +1199,7 @@
>   type="bool"/>
>  
>  
> -
> +
>  
>  
>  
> diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
> index 793f733..8c8b776 100644
> --- a/src/intel/genxml/gen75.xml
> +++ b/src/intel/genxml/gen75.xml
> @@ -1292,7 +1292,7 @@
>  
>   type="bool"/>
>  
> -
> +
>
>  
>
> @@ -1440,7 +1440,7 @@
>
>  
>  
> -
> +
>  
>
>
> @@ -1484,7 +1484,7 @@
>   type="bool"/>
>  
>  
> -
> +
>  
>  
>  
> diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
> index a6c6d9d..f49c4a3 100644
> --- a/src/intel/genxml/gen8.xml
> +++ b/src/intel/genxml/gen8.xml
> @@ -1350,7 +1350,7 @@
>  
>   type="bool"/>
>  
> -
> +
>   type="uint"/>
>   type="uint"/>
>   end="271" type="uint"/>
> @@ -1506,7 +1506,7 @@
>
>  
>  
> -
> +
>  
>
>
> @@ -1555,7 +1555,7 @@
>  
>   type="bool"/>
>  
> -
> +
>  
>  
>  
> diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
> index 45eb454..178cf73 100644
> --- a/src/intel/genxml/gen9.xml
> +++ b/src/intel/genxml/gen9.xml
> @@ -1412,7 +1412,7 @@
>  
>   type="bool"/>
>  
> -
> +
>   type="uint"/>
>   type="uint"/>
>   end="271" type="uint"/>
> @@ -1611,7 +1611,7 @@
>
>  
>  
> -
> +
>  
>
>
> @@ -1661,7 +1661,7 @@
>  
>   type="bool"/>
>  
> -
> +
>  
>  
>  
> diff --git a/src/intel/vulkan/genX_pipeline.c 
> b/src/intel/vulkan/genX_pipeline.c
> index 74d6f9a..2b38c34 100644
> --- a/src/intel/vulkan/genX_pipeline.c
> +++ b/src/intel/vulkan/genX_pipeline.c
> @@ -1192,7 +1192,7 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline)
> const struct brw_tes_prog_data *tes_prog_data = 
> get_tes_prog_data(pipeline);
>  
> anv_batch_emit(>batch, GENX(3DSTATE_HS), hs) {
> -  hs.FunctionEnable = true;
> +  hs.Enable = true;
>hs.StatisticsEnable = true;
>hs.KernelStartPointer = tcs_bin->kernel.offset;
>  
> @@ -1222,7 +1222,7 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline)
> }
>  
> anv_batch_emit(>batch, GENX(3DSTATE_DS), ds) {
> -  ds.FunctionEnable = true;
> +  ds.Enable = true;
>ds.StatisticsEnable = true;
>ds.KernelStartPointer = tes_bin->kernel.offset;
>  
> @@ -1275,7 +1275,7 @@ emit_3dstate_gs(struct anv_pipeline *pipeline)
> const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
>  
> anv_batch_emit(>batch, GENX(3DSTATE_GS), gs) {
> -  gs.FunctionEnable  = true;
> +  gs.Enable  = true;
>gs.StatisticsEnable= true;
>gs.KernelStartPointer  = gs_bin->kernel.offset;
>gs.DispatchMode= gs_prog_data->base.dispatch_mode;
> 

Let's keep the spacing lined up here.

Patches 3-5, 8-12 are:
Reviewed-by: Kenneth Graunke 



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Re: [Mesa-dev] [PATCH v02 06/37] genxml: Add alias for MOCS.

[Kenneth Graunke]

On Monday, April 24, 2017 3:19:01 PM PDT Rafael Antognolli wrote:
> Use an alias, so we can set the same value as the #define's.
> 
> Signed-off-by: Rafael Antognolli 
> ---
>  src/intel/genxml/gen8.xml | 1 +
>  src/intel/genxml/gen9.xml | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
> index 408d241..2908082 100644
> --- a/src/intel/genxml/gen8.xml
> +++ b/src/intel/genxml/gen8.xml
> @@ -2064,6 +2064,7 @@
>  
>  
>   type="MEMORY_OBJECT_CONTROL_STATE"/>
> +
>   type="bool"/>
>   end="52" type="bool"/>
>  
> diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
> index 59daa31..09b9464 100644
> --- a/src/intel/genxml/gen9.xml
> +++ b/src/intel/genxml/gen9.xml
> @@ -2246,6 +2246,7 @@
>  
>  
>   type="MEMORY_OBJECT_CONTROL_STATE"/>
> +
>   type="bool"/>
>   end="52" type="bool"/>
>  
> 

This seems a bit strange...we're only changing this in the stream out
packets, and only on Gen8-9?

I've wondered whether we should just use a uint everywhere.  On Gen9+
it's just an index into the kernel tables, with no hardware-mandated
meaning.  On earlier platforms, it changed for every piece of hardware.

I feel like a macro to construct MOCS values on earlier platforms
would work as well as genxml.  *shrug*


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Re: [Mesa-dev] [PATCH] docs: add release calendar page and references to it

[Eric Engestrom]

On Monday, 2017-04-24 17:22:19 +0100, Emil Velikov wrote:
> From: Emil Velikov 
> 
> Add a page that has information which release is expected when and
> associated information.
> 
> Reference to it from the "Releasing process" and "Release notes" pages.
> 
> Cc: Andres Gomez 
> Signed-off-by: Emil Velikov 

LGTM:
Reviewed-by: Eric Engestrom 

This looks very error-prone though; did you generate it by hand, or did
you write a script for it?


> ---
>  docs/contents.html |   1 +
>  docs/release-calendar.html | 102 
> +
>  docs/releasing.html|   3 ++
>  docs/relnotes/17.0.4.html  |   7 
>  docs/relnotes/17.1.0.html  |   3 +-
>  5 files changed, 115 insertions(+), 1 deletion(-)
>  create mode 100644 docs/release-calendar.html
> 
> diff --git a/docs/contents.html b/docs/contents.html
> index 90a1a00dea0..d5455421091 100644
> --- a/docs/contents.html
> +++ b/docs/contents.html
> @@ -84,6 +84,7 @@
>  Coding Style
>  Submitting patches
>  Releasing process
> +Release calendar
>  Source Documentation
>  GL Dispatch
>  
> diff --git a/docs/release-calendar.html b/docs/release-calendar.html
> new file mode 100644
> index 000..caaf753c9e2
> --- /dev/null
> +++ b/docs/release-calendar.html
> @@ -0,0 +1,102 @@
> + "http://www.w3.org/TR/html4/loose.dtd;>
> +
> +
> +  
> +  Releasing process
> +  
> +
> +
> +
> +
> +  The Mesa 3D Graphics Library
> +
> +
> +
> +
> +
> +Overview
> +
> +
> +Mesa provides feature/development and stable releases.
> +
> +
> +The table below lists the date and release manager that is expected to do the
> +specific release.
> +
> +Take a look  target="_parent">here
> +if you'd like to nominate a patch in the next stable release.
> +
> +
> +Calendar
> +
> +
> +
> +
> +Mesa version
> +Release date
> +Release manager
> +Notes
> +
> +
> +development
> +stable
> +
> +
> +
> +17.0.5
> +2017-04-28
> +Emil Velikov
> +
> +
> +
> +17.1.0-rc3
> +
> +2017-04-28
> +Emil Velikov
> +
> +
> +
> +17.1.0-rc4
> +
> +2017-05-05
> +Emil Velikov
> +May be promoted to 17.1.0 final
> +
> +
> +
> +17.0.6
> +2017-05-12
> +Emil Velikov
> +
> +
> +
> +17.1.1
> +2017-05-19
> +Emil Velikov
> +
> +
> +
> +17.0.7
> +2017-05-26
> +Emil Velikov
> +Final planned release for the 17.0 series
> +
> +
> +
> +17.1.2
> +2017-06-02
> +Emil Velikov
> +
> +
> +
> +
> +17.1.3
> +2017-06-16
> +Emil Velikov
> +
> +
> +
> +
> +
> +
> +
> diff --git a/docs/releasing.html b/docs/releasing.html
> index fc7f2a5aff9..15df022e5f6 100644
> --- a/docs/releasing.html
> +++ b/docs/releasing.html
> @@ -53,6 +53,9 @@ For example:
>  
>  Releases should happen on Fridays. Delays can occur although those should be 
> keep
>  to a minimum.
> +
> +See our calendar for the
> +date and other details for individual releases.
>  
>  
>  Feature releases
> diff --git a/docs/relnotes/17.0.4.html b/docs/relnotes/17.0.4.html
> index 2e2ca9ba649..16629d1bacc 100644
> --- a/docs/relnotes/17.0.4.html
> +++ b/docs/relnotes/17.0.4.html
> @@ -36,6 +36,13 @@ 
> c4c34ba05d48f76b45bc05bc4b6e9242077f403d63c4f0c355c7b07786de233e  
> mesa-17.0.4.ta
>  
>  
>  
> +Next release
> +
> +Mesa 17.0.5 is expected in approximatelly two weeks. See the release
> +calendar
> +for details.
> +
> +
>  New features
>  None
>  
> diff --git a/docs/relnotes/17.1.0.html b/docs/relnotes/17.1.0.html
> index e7cfe38fac4..4f89c56ffe6 100644
> --- a/docs/relnotes/17.1.0.html
> +++ b/docs/relnotes/17.1.0.html
> @@ -19,7 +19,8 @@
>  
>  Mesa 17.1.0 is a new development release.
>  People who are concerned with stability and reliability should stick
> -with a previous release or wait for Mesa 17.1.1.
> +with a previous release or wait for
> +Mesa 17.1.1.
>  
>  
>  Mesa 17.1.0 implements the OpenGL 4.5 API, but the version reported by
> -- 
> 2.12.2
> 
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[Mesa-dev] [PATCH 3/4] radeonsi: disable the TGSI merge registers pass

[Samuel Pitoiset]

47109 shaders in 29632 tests
Totals:
SGPRS: 1917364 -> 1916620 (-0.04 %)
VGPRS: 1165802 -> 1165202 (-0.05 %)
Spilled SGPRs: 1880 -> 1843 (-1.97 %)
Spilled VGPRs: 70 -> 65 (-7.14 %)
Private memory VGPRs: 1184 -> 1184 (0.00 %)
Scratch size: 1312 -> 1308 (-0.30 %) dwords per thread
Code Size: 60211356 -> 60192268 (-0.03 %) bytes
LDS: 1077 -> 1077 (0.00 %) blocks
Max Waves: 428597 -> 428674 (0.02 %)
Wait states: 0 -> 0 (0.00 %)

Totals from affected shaders:
SGPRS: 238173 -> 237429 (-0.31 %)
VGPRS: 149556 -> 148956 (-0.40 %)
Spilled SGPRs: 1263 -> 1226 (-2.93 %)
Spilled VGPRs: 25 -> 20 (-20.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 20 -> 16 (-20.00 %) dwords per thread
Code Size: 10457904 -> 10438816 (-0.18 %) bytes
LDS: 50 -> 50 (0.00 %) blocks
Max Waves: 41283 -> 41360 (0.19 %)
Wait states: 0 -> 0 (0.00 %)

Signed-off-by: Samuel Pitoiset 
---
 src/gallium/drivers/radeonsi/si_pipe.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 2a11607c90..cfbcbe2b74 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -680,6 +680,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
case PIPE_SHADER_CAP_INTEGERS:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
+   case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 1;
 
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
@@ -693,7 +694,6 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
case PIPE_SHADER_CAP_SUPPORTED_IRS:
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
-   case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
}
return 0;
-- 
2.12.2

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[Mesa-dev] [PATCH 2/4] st/glsl_to_tgsi: disable the merge registers pass conditionally

[Samuel Pitoiset]

The main goal of this pass to merge temporary registers in order
to reduce the total number of registers and also to produce
optimal TGSI code.

In fact, compilers seem to be confused when temporary variables
are already merged, maybe because it's done too early in the
process.

Skipping the pass, reduce both the register pressure and the code
size, at least for Nouveau and RadeonSI because they have a real
backend compiler.

Found by luck while fixing an issue in the TGSI dead code elimination
pass which affects tex instructions with bindless samplers.

Signed-off-by: Samuel Pitoiset 
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index de7fe7837a..8ca90f6c43 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -6639,6 +6639,7 @@ get_mesa_program_tgsi(struct gl_context *ctx,
  >Const.ShaderCompilerOptions[shader->Stage];
struct pipe_screen *pscreen = ctx->st->pipe->screen;
enum pipe_shader_type ptarget = st_shader_stage_to_ptarget(shader->Stage);
+   unsigned skip_merge_registers;
 
validate_ir_tree(shader->ir);
 
@@ -6660,6 +6661,9 @@ get_mesa_program_tgsi(struct gl_context *ctx,
PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED);
v->has_tex_txf_lz = pscreen->get_param(pscreen,
   PIPE_CAP_TGSI_TEX_TXF_LZ);
+   skip_merge_registers =
+  pscreen->get_shader_param(pscreen, ptarget,
+PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS);
 
_mesa_generate_parameters_list_for_uniforms(shader_program, shader,
prog->Parameters);
@@ -6712,7 +6716,8 @@ get_mesa_program_tgsi(struct gl_context *ctx,
while (v->eliminate_dead_code());
 
v->merge_two_dsts();
-   v->merge_registers();
+   if (!skip_merge_registers)
+  v->merge_registers();
v->renumber_registers();
 
/* Write the END instruction. */
-- 
2.12.2

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[Mesa-dev] [PATCH 4/4] nv50, nvc0: disable the TGSI merge registers pass

[Samuel Pitoiset]

shader-db results on GK106 (Thanks Karol):

total instructions in shared programs : 3931608 -> 3929463 (-0.05%)
total gprs used in shared programs: 481255 -> 479014 (-0.47%)
total local used in shared programs   : 27481 -> 27381 (-0.36%)
total bytes used in shared programs   : 36031256 -> 36011120 (-0.06%)

localgpr   inst  bytes
helped  14147113091309
  hurt   1  88 384 384

Signed-off-by: Samuel Pitoiset 
---
 src/gallium/drivers/nouveau/nv50/nv50_screen.c | 3 ++-
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 3c35cf46d5..82e666a39e 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -341,6 +341,8 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
   return 0; /* please inline, or provide function declarations */
case PIPE_SHADER_CAP_INTEGERS:
   return 1;
+   case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
+  return 1;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
   /* The chip could handle more sampler views than samplers */
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
@@ -357,7 +359,6 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_SUPPORTED_IRS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
-   case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
   return 0;
default:
   NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 01c260292f..ad99e17eaf 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -387,10 +387,11 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
   return 1;
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
   return 1;
+   case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
+  return 1;
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
-   case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
   return 0;
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
   return NVC0_MAX_BUFFERS;
-- 
2.12.2

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[Mesa-dev] [PATCH 1/4] gallium: add PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/gallium/auxiliary/gallivm/lp_bld_limits.h| 1 +
 src/gallium/auxiliary/tgsi/tgsi_exec.h   | 1 +
 src/gallium/docs/source/screen.rst   | 3 +++
 src/gallium/drivers/etnaviv/etnaviv_screen.c | 1 +
 src/gallium/drivers/freedreno/freedreno_screen.c | 1 +
 src/gallium/drivers/nouveau/nv30/nv30_screen.c   | 2 ++
 src/gallium/drivers/nouveau/nv50/nv50_screen.c   | 1 +
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c   | 1 +
 src/gallium/drivers/r300/r300_screen.c   | 2 ++
 src/gallium/drivers/r600/r600_pipe.c | 1 +
 src/gallium/drivers/radeonsi/si_pipe.c   | 1 +
 src/gallium/drivers/svga/svga_screen.c   | 3 +++
 src/gallium/drivers/vc4/vc4_screen.c | 1 +
 src/gallium/drivers/virgl/virgl_screen.c | 1 +
 src/gallium/include/pipe/p_defines.h | 1 +
 15 files changed, 21 insertions(+)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_limits.h 
b/src/gallium/auxiliary/gallivm/lp_bld_limits.h
index b8c5c800e6..354e2a46b1 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_limits.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_limits.h
@@ -135,6 +135,7 @@ gallivm_get_shader_param(enum pipe_shader_cap param)
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
+   case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
   return 0;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
   return 32;
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h 
b/src/gallium/auxiliary/tgsi/tgsi_exec.h
index 5708a5061a..9d7e65f2c5 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h
@@ -527,6 +527,7 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param)
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
+   case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
   return 0;
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
   return PIPE_MAX_SHADER_BUFFERS;
diff --git a/src/gallium/docs/source/screen.rst 
b/src/gallium/docs/source/screen.rst
index bb2803a40c..de9de05b40 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -489,6 +489,9 @@ to be 0.
   cost than this value should be lowered by the state tracker for better
   performance. This is a tunable for the GLSL compiler and the behavior is
   specific to the compiler.
+* ``PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS``: Whether the merge registers
+  TGSI pass is skipped. This might reduce code size and register pressure if
+  the underlying driver has a real backend compiler.
 
 
 .. _pipe_compute_cap:
diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c 
b/src/gallium/drivers/etnaviv/etnaviv_screen.c
index 626f7c7789..13e20e07da 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
@@ -438,6 +438,7 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
+   case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
   return 0;
}
 
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c 
b/src/gallium/drivers/freedreno/freedreno_screen.c
index 9b3ca4d51b..93b434b0ba 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -520,6 +520,7 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
+   case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
}
debug_printf("unknown shader param %d\n", param);
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c 
b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
index 24b6b60bc6..363ac312a9 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
@@ -313,6 +313,7 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
   case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
   case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
   case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
+  case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
  return 0;
   default:
  debug_printf("unknown vertex shader param %d\n", param);
@@ -360,6 +361,7 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
   case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
   case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
   case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
+  case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
  return 0;
   default:
  debug_printf("unknown fragment shader param %d\n", param);
diff --git 

Re: [Mesa-dev] [PATCH 2/2] radeonsi: disable primitive restart for non-strip prims based on app list

[Kenneth Graunke]

On Monday, April 24, 2017 6:22:41 AM PDT Marek Olšák wrote:
> From: Marek Olšák 
> 
> ---
>  src/gallium/drivers/radeonsi/si_pipe.c   | 20 +
>  src/gallium/drivers/radeonsi/si_pipe.h   |  1 +
>  src/gallium/drivers/radeonsi/si_state_draw.c | 45 
> 
>  3 files changed, 54 insertions(+), 12 deletions(-)
> 
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
> b/src/gallium/drivers/radeonsi/si_pipe.c
> index 1a83564..53a8201 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -29,20 +29,29 @@
>  #include "radeon/radeon_uvd.h"
>  #include "util/u_memory.h"
>  #include "util/u_suballoc.h"
>  #include "util/u_tests.h"
>  #include "vl/vl_decoder.h"
>  #include "../ddebug/dd_util.h"
>  
>  #define SI_LLVM_DEFAULT_FEATURES \
>   "+DumpCode,+vgpr-spilling,-fp32-denormals,-xnack"
>  
> +/* DX10/11 apply primitive restart to strip primitive types only. */
> +static const char *apps_with_prim_restart_dx_behavior[] = {
> + "DeusExMD",
> + "DirtRally",
> + "HitmanPro",
> + "MadMax",
> + "TotalWarhammer",
> +};
> +

Hi Marek,

You seem to be adding driver workarounds for an incomplete list of Feral
Interactive's titles.  Presumably, if you're going to go this route, you
may need to add more of them.  Or, perhaps this is something they can
fix in their translator layer, so they only enable it when they want it?

I've copied Marc and Alex from Feral in case they want to weigh in.

--Ken


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[Mesa-dev] [PATCH v02 00/37] Updated series to convert part of the state emitting code to genxml.

[Rafael Antognolli]

v2:
   - Included Louis patch that adds gen4, gen4.5 and gen5 xml's
   - Merged code for gen4-5 for emit vertices and some other brw_*
 functions
   - Addressed Ken's comments about updating gen4 and gen5 xml.
   - Included suggestion from Kristian about functions to return struct
 brw_address.
   - Moved xml commits to the beginning of the series.
   - Did a couple code cleanups for "TODO's" that I had left in the
 code.

I'm working on this series in this branch:
https://github.com/rantogno/mesa/tree/wip/brwxml

Kenneth Graunke (4):
  genxml: Make "Reorder Mode" fields consistent.
  i965: Add genxml related plumbing in a new genX_state_upload.c file.
  i965: Get real per-gen atom lists
  i965: Port Gen6+ DEPTH_STENCIL state to genxml.

Louis-Francis Ratté-Boulianne (1):
  genxml: Fill out Gen4, Gen45 and Gen5 XML

Rafael Antognolli (32):
  genxml: Fix gen4-5 xml to make it compile correctly.
  genxml: Rename clip enable property.
  genxml: Update xml for 3DSTATE_SF.
  genxml: Add missing field values to 3DSTATE_SBE.
  genxml: Add alias for MOCS.
  genxml: 3DSTATE_VS rename Function Enable to Enable.
  genxml: Clip guardbands are float, not int.
  genxml: Rename "Function Enable" to "Enable".
  genxml: Normalize xml for 3DSTATE_MULTISAMPLE.
  genxml: Normalize xml for 3DSTATE_CC_STATE_POINTERS.
  i965: Split out enum from brw_eu_defines.h
  anv: Use BRW_BARYCENTRIC_NONPERSPECTIVE_BITS from common header.
  genxml: Add rules to build gen4, gen45 and ge5.
  i965: Port Gen6+ 3DSTATE_CLIP state to genxml.
  i965: Port Gen8+ 3DSTATE_RASTER state to genxml.
  i965: Port gen6+ 3DSTATE_SF to genxml.
  i965: Port Gen7+ 3DSTATE_SBE state to genxml.
  i965: Remove calculate_attr_overrides.
  i965: Port gen7+ 3DSTATE_SOL to genxml.
  i965: Port gen7+ 3DSTATE_PS to genxml.
  i965: Port gen6+ 3DSTATE_WM to genxml.
  i965: Port gen8+ 3DSTATE_PS_EXTRA to genxml.
  i965: Port gen6+ 3DSTATE_VS to genxml.
  i965: Port gen6+ state emitting code to genxml.
  i965: Port gen6+ blend state code to genxml.
  i965: Port gen7+ 3DSTATE_TE to genxml.
  i965: Port gen6+ 3DSTATE_SCISSOR_STATE_POINTERS to use genxml.
  i965: Port push constant code to genxml.
  i965: Port gen4+ emit vertices code to genxml.
  i965: Port gen6+ multisample state emitting code to genxml.
  i965: Port gen6+ 3DSTATE_CC_STATE_POINTERS state to genxml.
  i965: Port gen4+ state emitting code to genxml.

 src/intel/Makefile.sources |1 +-
 src/intel/blorp/blorp_genX_exec.h  |   10 +-
 src/intel/compiler/brw_defines_common.h|   46 +-
 src/intel/compiler/brw_eu_defines.h|   22 +-
 src/intel/genxml/gen4.xml  | 1121 +--
 src/intel/genxml/gen45.xml | 1174 +--
 src/intel/genxml/gen5.xml  | 1287 ++-
 src/intel/genxml/gen6.xml  |   42 +-
 src/intel/genxml/gen7.xml  |   24 +-
 src/intel/genxml/gen75.xml |   12 +-
 src/intel/genxml/gen8.xml  |   11 +-
 src/intel/genxml/gen9.xml  |   16 +-
 src/intel/vulkan/gen8_cmd_buffer.c |2 +-
 src/intel/vulkan/genX_pipeline.c   |   19 +-
 src/mesa/drivers/dri/i965/Makefile.am  |   12 +-
 src/mesa/drivers/dri/i965/Makefile.sources |   48 +-
 src/mesa/drivers/dri/i965/brw_context.h|   15 +-
 src/mesa/drivers/dri/i965/brw_draw.h   |2 +-
 src/mesa/drivers/dri/i965/brw_draw_upload.c| 1123 +---
 src/mesa/drivers/dri/i965/brw_misc_state.c |  147 +-
 src/mesa/drivers/dri/i965/brw_state.h  |  101 +-
 src/mesa/drivers/dri/i965/brw_state_upload.c   |  385 +-
 src/mesa/drivers/dri/i965/brw_util.h   |   25 +-
 src/mesa/drivers/dri/i965/gen6_cc.c|  306 +-
 src/mesa/drivers/dri/i965/gen6_clip_state.c|  139 +-
 src/mesa/drivers/dri/i965/gen6_depthstencil.c  |  114 +-
 src/mesa/drivers/dri/i965/gen6_gs_state.c  |  162 +-
 src/mesa/drivers/dri/i965/gen6_multisample_state.c |6 +-
 src/mesa/drivers/dri/i965/gen6_sf_state.c  |  455 +-
 src/mesa/drivers/dri/i965/gen6_viewport_state.c|  207 +-
 src/mesa/drivers/dri/i965/gen6_vs_state.c  |  183 +-
 src/mesa/drivers/dri/i965/gen6_wm_state.c  |  289 +-
 src/mesa/drivers/dri/i965/gen7_ds_state.c  |  126 +-
 src/mesa/drivers/dri/i965/gen7_gs_state.c  |  168 +-
 src/mesa/drivers/dri/i965/gen7_hs_state.c  |  123 +-
 src/mesa/drivers/dri/i965/gen7_sf_state.c  |  265 +-
 src/mesa/drivers/dri/i965/gen7_sol_state.c |  307 +-
 src/mesa/drivers/dri/i965/gen7_te_state.c  |   67 +-
 src/mesa/drivers/dri/i965/gen7_viewport_state.c|  100 +-
 src/mesa/drivers/dri/i965/gen7_vs_state.c  |   87 +-
 src/mesa/drivers/dri/i965/gen7_wm_state.c  |  283 +-
 src/mesa/drivers/dri/i965/gen8_blend_state.c

[Mesa-dev] [PATCH v02 18/37] i965: Port Gen6+ DEPTH_STENCIL state to genxml.

[Rafael Antognolli]

From: Kenneth Graunke 

This emits 3DSTATE_WM_DEPTH_STENCIL on Gen8+ or DEPTH_STENCIL_STATE
(and the relevant pointer packets) on Gen6-7.5 from a single function.

Signed-off-by: Kenneth Graunke 
Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/Makefile.sources|   2 +-
 src/mesa/drivers/dri/i965/brw_state.h |   2 +-
 src/mesa/drivers/dri/i965/gen6_depthstencil.c | 114 +--
 src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c | 118 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 107 +-
 5 files changed, 103 insertions(+), 240 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_depthstencil.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 41f4d83..b085251 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -80,7 +80,6 @@ i965_FILES = \
gen6_clip_state.c \
gen6_constant_state.c \
gen6_depth_state.c \
-   gen6_depthstencil.c \
gen6_gs_state.c \
gen6_multisample_state.c \
gen6_queryobj.c \
@@ -119,7 +118,6 @@ i965_FILES = \
gen8_surface_state.c \
gen8_viewport_state.c \
gen8_vs_state.c \
-   gen8_wm_depth_stencil.c \
hsw_queryobj.c \
hsw_sol.c \
intel_batchbuffer.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 6403570..7b6d718 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -112,7 +112,6 @@ extern const struct brw_tracked_state gen6_blend_state;
 extern const struct brw_tracked_state gen6_clip_state;
 extern const struct brw_tracked_state gen6_sf_and_clip_viewports;
 extern const struct brw_tracked_state gen6_color_calc_state;
-extern const struct brw_tracked_state gen6_depth_stencil_state;
 extern const struct brw_tracked_state gen6_gs_state;
 extern const struct brw_tracked_state gen6_gs_push_constants;
 extern const struct brw_tracked_state gen6_gs_binding_table;
@@ -157,7 +156,6 @@ extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
 extern const struct brw_tracked_state gen8_ps_state;
-extern const struct brw_tracked_state gen8_wm_depth_stencil;
 extern const struct brw_tracked_state gen8_wm_state;
 extern const struct brw_tracked_state gen8_raster_state;
 extern const struct brw_tracked_state gen8_sbe_state;
diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c 
b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
deleted file mode 100644
index 0f9626c..000
--- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *Eric Anholt 
- *
- */
-
-#include "intel_batchbuffer.h"
-#include "intel_fbo.h"
-#include "brw_context.h"
-#include "brw_defines.h"
-#include "brw_state.h"
-
-static void
-gen6_upload_depth_stencil_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   struct gen6_depth_stencil_state *ds;
-   struct intel_renderbuffer *depth_irb;
-
-   /* _NEW_BUFFERS */
-   depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
-
-   ds = brw_state_batch(brw, sizeof(*ds), 64,
-   >cc.depth_stencil_state_offset);
-   memset(ds, 0, sizeof(*ds));
-
-   /* _NEW_STENCIL | _NEW_BUFFERS */
-   if (ctx->Stencil._Enabled) {
-  int back = ctx->Stencil._BackFace;
-
-  ds->ds0.stencil_enable = 1;
-  ds->ds0.stencil_func =
-

[Mesa-dev] [PATCH v02 20/37] i965: Port Gen8+ 3DSTATE_RASTER state to genxml.

[Rafael Antognolli]

Emits 3DSTATE_RASTER from genX_state_upload.c using pack structs from
genxml.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/brw_state.h |   1 +-
 src/mesa/drivers/dri/i965/gen8_sf_state.c | 125 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 125 ++-
 3 files changed, 124 insertions(+), 127 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index c26be41..3a10a8a 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -156,7 +156,6 @@ extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
 extern const struct brw_tracked_state gen8_ps_state;
 extern const struct brw_tracked_state gen8_wm_state;
-extern const struct brw_tracked_state gen8_raster_state;
 extern const struct brw_tracked_state gen8_sbe_state;
 extern const struct brw_tracked_state gen8_sf_state;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
diff --git a/src/mesa/drivers/dri/i965/gen8_sf_state.c 
b/src/mesa/drivers/dri/i965/gen8_sf_state.c
index 41e94fb..d47adcd 100644
--- a/src/mesa/drivers/dri/i965/gen8_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sf_state.c
@@ -224,128 +224,3 @@ const struct brw_tracked_state gen8_sf_state = {
},
.emit = upload_sf,
 };
-
-static void
-upload_raster(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   uint32_t dw1 = 0;
-
-   /* _NEW_BUFFERS */
-   bool render_to_fbo = _mesa_is_user_fbo(brw->ctx.DrawBuffer);
-
-   /* _NEW_POLYGON */
-   if (ctx->Polygon._FrontBit == render_to_fbo)
-  dw1 |= GEN8_RASTER_FRONT_WINDING_CCW;
-
-   if (ctx->Polygon.CullFlag) {
-  switch (ctx->Polygon.CullFaceMode) {
-  case GL_FRONT:
- dw1 |= GEN8_RASTER_CULL_FRONT;
- break;
-  case GL_BACK:
- dw1 |= GEN8_RASTER_CULL_BACK;
- break;
-  case GL_FRONT_AND_BACK:
- dw1 |= GEN8_RASTER_CULL_BOTH;
- break;
-  default:
- unreachable("not reached");
-  }
-   } else {
-  dw1 |= GEN8_RASTER_CULL_NONE;
-   }
-
-   /* _NEW_POINT */
-   if (ctx->Point.SmoothFlag)
-  dw1 |= GEN8_RASTER_SMOOTH_POINT_ENABLE;
-
-   if (_mesa_is_multisample_enabled(ctx))
-  dw1 |= GEN8_RASTER_API_MULTISAMPLE_ENABLE;
-
-   if (ctx->Polygon.OffsetFill)
-  dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID;
-
-   if (ctx->Polygon.OffsetLine)
-  dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME;
-
-   if (ctx->Polygon.OffsetPoint)
-  dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT;
-
-   switch (ctx->Polygon.FrontMode) {
-   case GL_FILL:
-  dw1 |= GEN6_SF_FRONT_SOLID;
-  break;
-   case GL_LINE:
-  dw1 |= GEN6_SF_FRONT_WIREFRAME;
-  break;
-   case GL_POINT:
-  dw1 |= GEN6_SF_FRONT_POINT;
-  break;
-
-   default:
-  unreachable("not reached");
-   }
-
-   switch (ctx->Polygon.BackMode) {
-   case GL_FILL:
-  dw1 |= GEN6_SF_BACK_SOLID;
-  break;
-   case GL_LINE:
-  dw1 |= GEN6_SF_BACK_WIREFRAME;
-  break;
-   case GL_POINT:
-  dw1 |= GEN6_SF_BACK_POINT;
-  break;
-   default:
-  unreachable("not reached");
-   }
-
-   /* _NEW_LINE */
-   if (ctx->Line.SmoothFlag)
-  dw1 |= GEN8_RASTER_LINE_AA_ENABLE;
-
-   /* _NEW_SCISSOR */
-   if (ctx->Scissor.EnableFlags)
-  dw1 |= GEN8_RASTER_SCISSOR_ENABLE;
-
-   /* _NEW_TRANSFORM */
-   if (!ctx->Transform.DepthClamp) {
-  if (brw->gen >= 9) {
- dw1 |= GEN9_RASTER_VIEWPORT_Z_NEAR_CLIP_TEST_ENABLE |
-GEN9_RASTER_VIEWPORT_Z_FAR_CLIP_TEST_ENABLE;
-  } else {
- dw1 |= GEN8_RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE;
-  }
-   }
-
-   /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
-   if (ctx->IntelConservativeRasterization) {
-  if (brw->gen >= 9)
- dw1 |= GEN9_RASTER_CONSERVATIVE_RASTERIZATION_ENABLE;
-   }
-
-   BEGIN_BATCH(5);
-   OUT_BATCH(_3DSTATE_RASTER << 16 | (5 - 2));
-   OUT_BATCH(dw1);
-   OUT_BATCH_F(ctx->Polygon.OffsetUnits * 2); /* constant.  copied from gen4 */
-   OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */
-   OUT_BATCH_F(ctx->Polygon.OffsetClamp); /* global depth offset clamp */
-   ADVANCE_BATCH();
-}
-
-const struct brw_tracked_state gen8_raster_state = {
-   .dirty = {
-  .mesa  = _NEW_BUFFERS |
-   _NEW_LINE |
-   _NEW_MULTISAMPLE |
-   _NEW_POINT |
-   _NEW_POLYGON |
-   _NEW_SCISSOR |
-   _NEW_TRANSFORM,
-  .brw   = BRW_NEW_BLORP |
-   BRW_NEW_CONTEXT |
-   BRW_NEW_CONSERVATIVE_RASTERIZATION,
-   },
-   .emit = upload_raster,
-};
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 7532085..948782a 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -343,10 +343,133 @@ static const struct brw_tracked_state 

[Mesa-dev] [PATCH v02 02/37] genxml: Fix gen4-5 xml to make it compile correctly.

[Rafael Antognolli]

Set the type of some fields, instead of prefix. Also fix the
SAMPLER_BORDER_COLOR_STATE fields of gen5.xml.

Signed-off-by: Rafael Antognolli 
---
 src/intel/genxml/gen4.xml  | 13 +-
 src/intel/genxml/gen45.xml | 12 -
 src/intel/genxml/gen5.xml  | 52 +++
 3 files changed, 39 insertions(+), 38 deletions(-)

diff --git a/src/intel/genxml/gen4.xml b/src/intel/genxml/gen4.xml
index 1cdae22..0ea66e5 100644
--- a/src/intel/genxml/gen4.xml
+++ b/src/intel/genxml/gen4.xml
@@ -375,12 +375,12 @@
   
   
 
-
-
-
-
-
-
+
+
+
+
+
+
   
   
   
@@ -708,6 +708,7 @@
 
 
 
+
   
 
   
diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml
index 1bf6840..bff32f9 100644
--- a/src/intel/genxml/gen45.xml
+++ b/src/intel/genxml/gen45.xml
@@ -376,12 +376,12 @@
   
   
 
-
-
-
-
-
-
+
+
+
+
+
+
   
   
   
diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
index db0ae46..fc6f248 100644
--- a/src/intel/genxml/gen5.xml
+++ b/src/intel/genxml/gen5.xml
@@ -374,12 +374,12 @@
   
   
 
-
-
-
-
-
-
+
+
+
+
+
+
   
   
   
@@ -497,30 +497,30 @@
 
 
 
-
-
-
-
+
+
+
+
 
-
-
-
-
+
+
+
+
 
-
-
-
-
+
+
+
+
 
-
-
-
-
+
+
+
+
 
-
-
-
-
+
+
+
+
   
 
   
-- 
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[Mesa-dev] [PATCH v02 13/37] i965: Split out enum from brw_eu_defines.h

[Rafael Antognolli]

We need to use some enums inside genX_state_upload.c, but including the
whole header will cause several conflicts between things defined in this
header and the genxml auto-generated headers.

So create a separate header that is included both by brw_eu_defines.h
and genX_state_upload.c.

Signed-off-by: Rafael Antognolli 
---
 src/intel/Makefile.sources  |  1 +-
 src/intel/compiler/brw_defines_common.h | 46 ++-
 src/intel/compiler/brw_eu_defines.h | 22 +
 3 files changed, 48 insertions(+), 21 deletions(-)
 create mode 100644 src/intel/compiler/brw_defines_common.h

diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index 0d44661..2af5a7a 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -27,6 +27,7 @@ COMPILER_FILES = \
compiler/brw_compiler.h \
compiler/brw_dead_control_flow.cpp \
compiler/brw_dead_control_flow.h \
+   compiler/brw_defines_common.h \
compiler/brw_disasm.c \
compiler/brw_eu.c \
compiler/brw_eu_compact.c \
diff --git a/src/intel/compiler/brw_defines_common.h 
b/src/intel/compiler/brw_defines_common.h
new file mode 100644
index 000..fdae125
--- /dev/null
+++ b/src/intel/compiler/brw_defines_common.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef BRW_DEFINES_COMMON_H
+#endif // BRW_DEFINES_COMMON_H
+
+enum brw_pixel_shader_computed_depth_mode {
+   BRW_PSCDEPTH_OFF   = 0, /* PS does not compute depth */
+   BRW_PSCDEPTH_ON= 1, /* PS computes depth; no guarantee about value */
+   BRW_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >= source depth */
+   BRW_PSCDEPTH_ON_LE = 3, /* PS guarantees output depth <= source depth */
+};
+
+enum brw_barycentric_mode {
+   BRW_BARYCENTRIC_PERSPECTIVE_PIXEL   = 0,
+   BRW_BARYCENTRIC_PERSPECTIVE_CENTROID= 1,
+   BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE  = 2,
+   BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL= 3,
+   BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID = 4,
+   BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE   = 5,
+   BRW_BARYCENTRIC_MODE_COUNT  = 6
+};
+#define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
+   ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
+(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
+(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
diff --git a/src/intel/compiler/brw_eu_defines.h 
b/src/intel/compiler/brw_eu_defines.h
index 13a70f6..51f9cbc 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -33,6 +33,7 @@
 #define BRW_EU_DEFINES_H
 
 #include "util/macros.h"
+#include "brw_defines_common.h"
 
 /* The following hunk, up-to "Execution Unit" is used by both the
  * intel/compiler and i965 codebase. */
@@ -72,27 +73,6 @@
 #define _3DPRIM_TRIFAN_NOSTIPPLE  0x16
 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
 
-enum brw_barycentric_mode {
-   BRW_BARYCENTRIC_PERSPECTIVE_PIXEL   = 0,
-   BRW_BARYCENTRIC_PERSPECTIVE_CENTROID= 1,
-   BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE  = 2,
-   BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL= 3,
-   BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID = 4,
-   BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE   = 5,
-   BRW_BARYCENTRIC_MODE_COUNT  = 6
-};
-#define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
-   ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
-(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
-(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
-
-enum brw_pixel_shader_computed_depth_mode {
-   BRW_PSCDEPTH_OFF   = 0, /* PS does not compute depth */
-   BRW_PSCDEPTH_ON= 1, /* PS computes depth; no guarantee about value */
-   BRW_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >= source depth */
-   BRW_PSCDEPTH_ON_LE = 3, /* PS guarantees output depth <= source depth */
-};
-
 /* Bitfields for 

[Mesa-dev] [PATCH v02 17/37] genxml: Add rules to build gen4, gen45 and ge5.

[Rafael Antognolli]

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/Makefile.am  | 12 
 src/mesa/drivers/dri/i965/Makefile.sources |  9 +
 src/mesa/drivers/dri/i965/brw_state.h  |  1 +
 3 files changed, 22 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/Makefile.am 
b/src/mesa/drivers/dri/i965/Makefile.am
index 4e9b062..762aefc 100644
--- a/src/mesa/drivers/dri/i965/Makefile.am
+++ b/src/mesa/drivers/dri/i965/Makefile.am
@@ -46,12 +46,24 @@ AM_CFLAGS = \
 AM_CXXFLAGS = $(AM_CFLAGS)
 
 I965_PERGEN_LIBS = \
+   libi965_gen4.la \
+   libi965_gen45.la \
+   libi965_gen5.la \
libi965_gen6.la \
libi965_gen7.la \
libi965_gen75.la \
libi965_gen8.la \
libi965_gen9.la
 
+libi965_gen4_la_SOURCES = $(i965_gen4_FILES)
+libi965_gen4_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=40
+
+libi965_gen45_la_SOURCES = $(i965_gen45_FILES)
+libi965_gen45_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=45
+
+libi965_gen5_la_SOURCES = $(i965_gen5_FILES)
+libi965_gen5_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=50
+
 libi965_gen6_la_SOURCES = $(i965_gen6_FILES)
 libi965_gen6_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=60
 
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index db55a3f..41f4d83 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -160,6 +160,15 @@ i965_FILES = \
intel_upload.c \
libdrm_macros.h
 
+i965_gen4_FILES = \
+   genX_state_upload.c
+
+i965_gen45_FILES = \
+   genX_state_upload.c
+
+i965_gen5_FILES = \
+   genX_state_upload.c
+
 i965_gen6_FILES = \
genX_blorp_exec.c \
genX_state_upload.c
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 008326a..6403570 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -446,6 +446,7 @@ void brw_copy_pipeline_atoms(struct brw_context *brw,
  const struct brw_tracked_state **atoms,
  int num_atoms);
 void gen4_init_atoms(struct brw_context *brw);
+void gen45_init_atoms(struct brw_context *brw);
 void gen5_init_atoms(struct brw_context *brw);
 void gen6_init_atoms(struct brw_context *brw);
 void gen7_init_atoms(struct brw_context *brw);
-- 
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[Mesa-dev] [PATCH v02 27/37] i965: Port gen8+ 3DSTATE_PS_EXTRA to genxml.

[Rafael Antognolli]

Emit 3DSTATE_PS_EXTRA on Gen8+ using brw_batch_emit helper, that uses
pack structs from genxml.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/Makefile.sources|   1 +-
 src/mesa/drivers/dri/i965/brw_state.h |  10 +-
 src/mesa/drivers/dri/i965/gen8_ps_state.c | 138 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c |  95 -
 4 files changed, 94 insertions(+), 150 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_ps_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index da09df8..7f25ae1 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -109,7 +109,6 @@ i965_FILES = \
gen8_gs_state.c \
gen8_hs_state.c \
gen8_multisample_state.c \
-   gen8_ps_state.c \
gen8_surface_state.c \
gen8_viewport_state.c \
gen8_vs_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 5010237..a87bf3a 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -146,7 +146,6 @@ extern const struct brw_tracked_state gen8_index_buffer;
 extern const struct brw_tracked_state gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_ps_blend;
-extern const struct brw_tracked_state gen8_ps_extra;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
@@ -284,15 +283,6 @@ void brw_update_renderbuffer_surfaces(struct brw_context 
*brw,
 void gen7_check_surface_setup(uint32_t *surf, bool is_render_target);
 void gen7_init_vtable_surface_functions(struct brw_context *brw);
 
-/* gen8_ps_state.c */
-void gen8_upload_ps_state(struct brw_context *brw,
-  const struct brw_stage_state *stage_state,
-  const struct brw_wm_prog_data *prog_data,
-  uint32_t fast_clear_op);
-
-void gen8_upload_ps_extra(struct brw_context *brw,
-  const struct brw_wm_prog_data *prog_data);
-
 /* gen8_surface_state.c */
 
 void gen8_init_vtable_surface_functions(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c 
b/src/mesa/drivers/dri/i965/gen8_ps_state.c
deleted file mode 100644
index 1a4a680..000
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Copyright © 2012 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include 
-#include "program/program.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "brw_wm.h"
-#include "intel_batchbuffer.h"
-
-void
-gen8_upload_ps_extra(struct brw_context *brw,
- const struct brw_wm_prog_data *prog_data)
-{
-   struct gl_context *ctx = >ctx;
-   uint32_t dw1 = 0;
-
-   dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
-   dw1 |= prog_data->computed_depth_mode << GEN8_PSX_COMPUTED_DEPTH_MODE_SHIFT;
-
-   if (prog_data->uses_kill)
-  dw1 |= GEN8_PSX_KILL_ENABLE;
-
-   if (prog_data->num_varying_inputs != 0)
-  dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
-
-   if (prog_data->uses_src_depth)
-  dw1 |= GEN8_PSX_USES_SOURCE_DEPTH;
-
-   if (prog_data->uses_src_w)
-  dw1 |= GEN8_PSX_USES_SOURCE_W;
-
-   if (prog_data->persample_dispatch)
-  dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
-
-   /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
-   if (prog_data->uses_sample_mask) {
-  if (brw->gen >= 9) {
- if (prog_data->post_depth_coverage)
-dw1 |= BRW_PCICMS_DEPTH << 
GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT;
- else if (prog_data->inner_coverage && 
ctx->IntelConservativeRasterization)
-  

[Mesa-dev] [PATCH v02 21/37] i965: Port gen6+ 3DSTATE_SF to genxml.

[Rafael Antognolli]

Emit sf state on Gen6+ using brw_batch_emit helper, using pack structs
from genxml.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/brw_state.h |   3 +-
 src/mesa/drivers/dri/i965/brw_util.h  |  25 +-
 src/mesa/drivers/dri/i965/gen6_sf_state.c | 190 +
 src/mesa/drivers/dri/i965/gen7_sf_state.c | 156 +---
 src/mesa/drivers/dri/i965/gen8_sf_state.c |  73 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 428 ++-
 6 files changed, 439 insertions(+), 436 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 3a10a8a..594757c 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -119,7 +119,6 @@ extern const struct brw_tracked_state 
gen6_renderbuffer_surfaces;
 extern const struct brw_tracked_state gen6_sampler_state;
 extern const struct brw_tracked_state gen6_scissor_state;
 extern const struct brw_tracked_state gen6_sol_surface;
-extern const struct brw_tracked_state gen6_sf_state;
 extern const struct brw_tracked_state gen6_sf_vp;
 extern const struct brw_tracked_state gen6_urb;
 extern const struct brw_tracked_state gen6_viewport_state;
@@ -137,7 +136,6 @@ extern const struct brw_tracked_state gen7_ps_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
 extern const struct brw_tracked_state gen7_sbe_state;
 extern const struct brw_tracked_state gen7_sf_clip_viewport;
-extern const struct brw_tracked_state gen7_sf_state;
 extern const struct brw_tracked_state gen7_sol_state;
 extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
@@ -157,7 +155,6 @@ extern const struct brw_tracked_state gen8_ps_extra;
 extern const struct brw_tracked_state gen8_ps_state;
 extern const struct brw_tracked_state gen8_wm_state;
 extern const struct brw_tracked_state gen8_sbe_state;
-extern const struct brw_tracked_state gen8_sf_state;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
diff --git a/src/mesa/drivers/dri/i965/brw_util.h 
b/src/mesa/drivers/dri/i965/brw_util.h
index 3e9a6ee..7395d34 100644
--- a/src/mesa/drivers/dri/i965/brw_util.h
+++ b/src/mesa/drivers/dri/i965/brw_util.h
@@ -40,8 +40,8 @@ extern GLuint brw_translate_blend_factor( GLenum factor );
 extern GLuint brw_translate_blend_equation( GLenum mode );
 extern GLenum brw_fix_xRGB_alpha(GLenum function);
 
-static inline uint32_t
-brw_get_line_width(struct brw_context *brw)
+static inline float
+brw_get_line_width_float(struct brw_context *brw)
 {
/* From the OpenGL 4.4 spec:
 *
@@ -52,14 +52,9 @@ brw_get_line_width(struct brw_context *brw)
float line_width =
   CLAMP(!_mesa_is_multisample_enabled(>ctx) && 
!brw->ctx.Line.SmoothFlag
 ? roundf(brw->ctx.Line.Width) : brw->ctx.Line.Width,
-0.0f, brw->ctx.Const.MaxLineWidth);
-   uint32_t line_width_u3_7 = U_FIXED(line_width, 7);
+0.125f, brw->ctx.Const.MaxLineWidth);
 
-   /* Line width of 0 is not allowed when MSAA enabled */
-   if (_mesa_is_multisample_enabled(>ctx)) {
-  if (line_width_u3_7 == 0)
- line_width_u3_7 = 1;
-   } else if (brw->ctx.Line.SmoothFlag && line_width < 1.5f) {
+   if (!_mesa_is_multisample_enabled(>ctx) && brw->ctx.Line.SmoothFlag && 
line_width < 1.5f) {
   /* For 1 pixel line thickness or less, the general
* anti-aliasing algorithm gives up, and a garbage line is
* generated.  Setting a Line Width of 0.0 specifies the
@@ -71,10 +66,18 @@ brw_get_line_width(struct brw_context *brw)
* bspec section 6.3.12.1 Zero-Width (Cosmetic) Line
* Rasterization.
*/
-  line_width_u3_7 = 0;
+  line_width = 0.0f;
}
 
-   return line_width_u3_7;
+   return line_width;
+}
+
+static inline uint32_t
+brw_get_line_width(struct brw_context *brw)
+{
+   float line_width = brw_get_line_width_float(brw);
+
+   return U_FIXED(line_width, 7);
 }
 
 #endif
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c 
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index dd54779..45b5769 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -263,193 +263,3 @@ calculate_attr_overrides(const struct brw_context *brw,
 */
*urb_entry_read_length = ALIGN(max_source_attr + 1, 2) / 2;
 }
-
-
-static void
-upload_sf_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   /* BRW_NEW_FS_PROG_DATA */
-   const struct brw_wm_prog_data *wm_prog_data =
-  brw_wm_prog_data(brw->wm.base.prog_data);
-   uint32_t num_outputs = wm_prog_data->num_varying_inputs;
-   uint32_t dw1, dw2, dw3, dw4;
-   uint32_t point_sprite_enables;
-   int i;
-   /* _NEW_BUFFER */
-   bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
-   const bool 

[Mesa-dev] [PATCH v02 34/37] i965: Port gen4+ emit vertices code to genxml.

[Rafael Antognolli]

Some code that was placed in brw_draw_upload.c and exported to be used
by gen8+ was also moved to genX_state_upload, and the respective symbols
are not exported anymore.

v2:
   - Remove code from brw_draw_upload too
   - Emit vertices for gen4-5 too.
   - Use helper to setup brw_address (Kristian)
   - Use macros for MOCS values.
   - Do not use #ifndef NDEBUG on code that is actually used (Ken)

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/brw_context.h   |6 +-
 src/mesa/drivers/dri/i965/brw_draw.h  |2 +-
 src/mesa/drivers/dri/i965/brw_draw_upload.c   | 1123 +
 src/mesa/drivers/dri/i965/brw_state.h |2 +-
 src/mesa/drivers/dri/i965/gen8_draw_upload.c  |  330 +-
 src/mesa/drivers/dri/i965/genX_state_upload.c | 1241 +-
 6 files changed, 1236 insertions(+), 1468 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index c7d6e49..8bd8863 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1396,10 +1396,6 @@ void brw_upload_cs_urb_state(struct brw_context *brw);
 /* brw_vs.c */
 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx);
 
-/* brw_draw_upload.c */
-unsigned brw_get_vertex_surface_type(struct brw_context *brw,
- const struct gl_vertex_array *glarray);
-
 static inline unsigned
 brw_get_index_type(unsigned index_size)
 {
@@ -1409,8 +1405,6 @@ brw_get_index_type(unsigned index_size)
return (index_size >> 1) << 8;
 }
 
-void brw_prepare_vertices(struct brw_context *brw);
-
 /* brw_wm_surface_state.c */
 void brw_init_surface_formats(struct brw_context *brw);
 void brw_create_constant_surface(struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/brw_draw.h 
b/src/mesa/drivers/dri/i965/brw_draw.h
index 3b99915..7fbe363 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.h
+++ b/src/mesa/drivers/dri/i965/brw_draw.h
@@ -58,8 +58,6 @@ void brw_draw_prims(struct gl_context *ctx,
 void brw_draw_init( struct brw_context *brw );
 void brw_draw_destroy( struct brw_context *brw );
 
-void brw_prepare_shader_draw_parameters(struct brw_context *);
-
 /* brw_primitive_restart.c */
 GLboolean
 brw_handle_primitive_restart(struct gl_context *ctx,
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c 
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 7846293..2fb4d5d 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -37,1129 +37,6 @@
 #include "intel_batchbuffer.h"
 #include "intel_buffer_objects.h"
 
-static const GLuint double_types_float[5] = {
-   0,
-   ISL_FORMAT_R64_FLOAT,
-   ISL_FORMAT_R64G64_FLOAT,
-   ISL_FORMAT_R64G64B64_FLOAT,
-   ISL_FORMAT_R64G64B64A64_FLOAT
-};
-
-static const GLuint double_types_passthru[5] = {
-   0,
-   ISL_FORMAT_R64_PASSTHRU,
-   ISL_FORMAT_R64G64_PASSTHRU,
-   ISL_FORMAT_R64G64B64_PASSTHRU,
-   ISL_FORMAT_R64G64B64A64_PASSTHRU
-};
-
-static const GLuint float_types[5] = {
-   0,
-   ISL_FORMAT_R32_FLOAT,
-   ISL_FORMAT_R32G32_FLOAT,
-   ISL_FORMAT_R32G32B32_FLOAT,
-   ISL_FORMAT_R32G32B32A32_FLOAT
-};
-
-static const GLuint half_float_types[5] = {
-   0,
-   ISL_FORMAT_R16_FLOAT,
-   ISL_FORMAT_R16G16_FLOAT,
-   ISL_FORMAT_R16G16B16_FLOAT,
-   ISL_FORMAT_R16G16B16A16_FLOAT
-};
-
-static const GLuint fixed_point_types[5] = {
-   0,
-   ISL_FORMAT_R32_SFIXED,
-   ISL_FORMAT_R32G32_SFIXED,
-   ISL_FORMAT_R32G32B32_SFIXED,
-   ISL_FORMAT_R32G32B32A32_SFIXED,
-};
-
-static const GLuint uint_types_direct[5] = {
-   0,
-   ISL_FORMAT_R32_UINT,
-   ISL_FORMAT_R32G32_UINT,
-   ISL_FORMAT_R32G32B32_UINT,
-   ISL_FORMAT_R32G32B32A32_UINT
-};
-
-static const GLuint uint_types_norm[5] = {
-   0,
-   ISL_FORMAT_R32_UNORM,
-   ISL_FORMAT_R32G32_UNORM,
-   ISL_FORMAT_R32G32B32_UNORM,
-   ISL_FORMAT_R32G32B32A32_UNORM
-};
-
-static const GLuint uint_types_scale[5] = {
-   0,
-   ISL_FORMAT_R32_USCALED,
-   ISL_FORMAT_R32G32_USCALED,
-   ISL_FORMAT_R32G32B32_USCALED,
-   ISL_FORMAT_R32G32B32A32_USCALED
-};
-
-static const GLuint int_types_direct[5] = {
-   0,
-   ISL_FORMAT_R32_SINT,
-   ISL_FORMAT_R32G32_SINT,
-   ISL_FORMAT_R32G32B32_SINT,
-   ISL_FORMAT_R32G32B32A32_SINT
-};
-
-static const GLuint int_types_norm[5] = {
-   0,
-   ISL_FORMAT_R32_SNORM,
-   ISL_FORMAT_R32G32_SNORM,
-   ISL_FORMAT_R32G32B32_SNORM,
-   ISL_FORMAT_R32G32B32A32_SNORM
-};
-
-static const GLuint int_types_scale[5] = {
-   0,
-   ISL_FORMAT_R32_SSCALED,
-   ISL_FORMAT_R32G32_SSCALED,
-   ISL_FORMAT_R32G32B32_SSCALED,
-   ISL_FORMAT_R32G32B32A32_SSCALED
-};
-
-static const GLuint ushort_types_direct[5] = {
-   0,
-   ISL_FORMAT_R16_UINT,
-   ISL_FORMAT_R16G16_UINT,
-   ISL_FORMAT_R16G16B16_UINT,
-   ISL_FORMAT_R16G16B16A16_UINT
-};
-
-static const GLuint ushort_types_norm[5] = {
-   0,
-   ISL_FORMAT_R16_UNORM,
-   ISL_FORMAT_R16G16_UNORM,
-   ISL_FORMAT_R16G16B16_UNORM,
-   

[Mesa-dev] [PATCH v02 19/37] i965: Port Gen6+ 3DSTATE_CLIP state to genxml.

[Rafael Antognolli]

Emit clip state on Gen6+ using brw_batch_emit helper, using pack structs
from genxml.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/brw_state.h |   1 +-
 src/mesa/drivers/dri/i965/gen6_clip_state.c   | 139 +--
 src/mesa/drivers/dri/i965/genX_state_upload.c | 143 ++-
 3 files changed, 140 insertions(+), 143 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 7b6d718..c26be41 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -109,7 +109,6 @@ extern const struct brw_tracked_state brw_cs_state;
 extern const struct brw_tracked_state gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
 extern const struct brw_tracked_state gen6_blend_state;
-extern const struct brw_tracked_state gen6_clip_state;
 extern const struct brw_tracked_state gen6_sf_and_clip_viewports;
 extern const struct brw_tracked_state gen6_color_calc_state;
 extern const struct brw_tracked_state gen6_gs_state;
diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c 
b/src/mesa/drivers/dri/i965/gen6_clip_state.c
index 23d969b..2fffb67 100644
--- a/src/mesa/drivers/dri/i965/gen6_clip_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c
@@ -88,142 +88,3 @@ brw_is_drawing_lines(const struct brw_context *brw)
return false;
 }
 
-static void
-upload_clip_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   /* BRW_NEW_META_IN_PROGRESS */
-   uint32_t dw1 = brw->meta_in_progress ? 0 : GEN6_CLIP_STATISTICS_ENABLE;
-   uint32_t dw2 = 0;
-
-   /* _NEW_BUFFERS */
-   struct gl_framebuffer *fb = ctx->DrawBuffer;
-
-   /* BRW_NEW_FS_PROG_DATA */
-   if (brw_wm_prog_data(brw->wm.base.prog_data)->barycentric_interp_modes &
-   BRW_BARYCENTRIC_NONPERSPECTIVE_BITS) {
-  dw2 |= GEN6_CLIP_NON_PERSPECTIVE_BARYCENTRIC_ENABLE;
-   }
-
-   /* BRW_NEW_VS_PROG_DATA */
-   dw1 |= brw_vue_prog_data(brw->vs.base.prog_data)->cull_distance_mask;
-
-   if (brw->gen >= 7)
-  dw1 |= GEN7_CLIP_EARLY_CULL;
-
-   if (brw->gen == 7) {
-  /* _NEW_POLYGON */
-  if (ctx->Polygon._FrontBit == _mesa_is_user_fbo(fb))
- dw1 |= GEN7_CLIP_WINDING_CCW;
-
-  if (ctx->Polygon.CullFlag) {
- switch (ctx->Polygon.CullFaceMode) {
- case GL_FRONT:
-dw1 |= GEN7_CLIP_CULLMODE_FRONT;
-break;
- case GL_BACK:
-dw1 |= GEN7_CLIP_CULLMODE_BACK;
-break;
- case GL_FRONT_AND_BACK:
-dw1 |= GEN7_CLIP_CULLMODE_BOTH;
-break;
- default:
-unreachable("Should not get here: invalid CullFlag");
- }
-  } else {
- dw1 |= GEN7_CLIP_CULLMODE_NONE;
-  }
-   }
-
-   if (brw->gen < 8 && !ctx->Transform.DepthClamp)
-  dw2 |= GEN6_CLIP_Z_TEST;
-
-   /* _NEW_LIGHT */
-   if (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION) {
-  dw2 |=
-(0 << GEN6_CLIP_TRI_PROVOKE_SHIFT) |
-(1 << GEN6_CLIP_TRIFAN_PROVOKE_SHIFT) |
-(0 << GEN6_CLIP_LINE_PROVOKE_SHIFT);
-   } else {
-  dw2 |=
-(2 << GEN6_CLIP_TRI_PROVOKE_SHIFT) |
-(2 << GEN6_CLIP_TRIFAN_PROVOKE_SHIFT) |
-(1 << GEN6_CLIP_LINE_PROVOKE_SHIFT);
-   }
-
-   /* _NEW_TRANSFORM */
-   dw2 |= (ctx->Transform.ClipPlanesEnabled <<
-   GEN6_USER_CLIP_CLIP_DISTANCES_SHIFT);
-
-   /* Have the hardware use the user clip distance clip test enable bitmask
-* specified here in 3DSTATE_CLIP rather than the one in 3DSTATE_VS/DS/GS.
-* We already listen to _NEW_TRANSFORM here, but the other atoms don't
-* need to other than this.
-*/
-   if (brw->gen >= 8)
-  dw1 |= GEN8_CLIP_FORCE_USER_CLIP_DISTANCE_BITMASK;
-
-   if (ctx->Transform.ClipDepthMode == GL_ZERO_TO_ONE)
-  dw2 |= GEN6_CLIP_API_D3D;
-   else
-  dw2 |= GEN6_CLIP_API_OGL;
-
-   dw2 |= GEN6_CLIP_GB_TEST;
-
-   /* BRW_NEW_VIEWPORT_COUNT */
-   const unsigned viewport_count = brw->clip.viewport_count;
-
-   /* BRW_NEW_RASTERIZER_DISCARD */
-   if (ctx->RasterDiscard) {
-  dw2 |= GEN6_CLIP_MODE_REJECT_ALL;
-  if (brw->gen == 6) {
- perf_debug("Rasterizer discard is currently implemented via the "
-"clipper; having the GS not write primitives would "
-"likely be faster.\n");
-  }
-   }
-
-   uint32_t enable;
-   if (brw->primitive == _3DPRIM_RECTLIST)
-  enable = 0;
-   else
-  enable = GEN6_CLIP_ENABLE;
-
-   /* _NEW_POLYGON,
-* BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
-*/
-   if (!brw_is_drawing_points(brw) && !brw_is_drawing_lines(brw))
-  dw2 |= GEN6_CLIP_XY_TEST;
-
-   BEGIN_BATCH(4);
-   OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2));
-   OUT_BATCH(dw1);
-   OUT_BATCH(enable |
-GEN6_CLIP_MODE_NORMAL |
-dw2);
-   OUT_BATCH(U_FIXED(0.125, 3) << GEN6_CLIP_MIN_POINT_WIDTH_SHIFT |
- 

[Mesa-dev] [PATCH v02 36/37] i965: Port gen6+ 3DSTATE_CC_STATE_POINTERS state to genxml.

[Rafael Antognolli]

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/Makefile.sources|  1 +-
 src/mesa/drivers/dri/i965/brw_state.h |  1 +-
 src/mesa/drivers/dri/i965/gen6_cc.c   | 90 +
 src/mesa/drivers/dri/i965/genX_state_upload.c | 53 +++-
 4 files changed, 50 insertions(+), 95 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_cc.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index b52b08b..098ceba 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -76,7 +76,6 @@ i965_FILES = \
brw_wm.h \
brw_wm_state.c \
brw_wm_surface_state.c \
-   gen6_cc.c \
gen6_clip_state.c \
gen6_constant_state.c \
gen6_depth_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 2b5b1c4..29e83cb 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -107,7 +107,6 @@ extern const struct brw_tracked_state brw_index_buffer;
 extern const struct brw_tracked_state brw_cs_state;
 extern const struct brw_tracked_state gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
-extern const struct brw_tracked_state gen6_color_calc_state;
 extern const struct brw_tracked_state gen6_gs_binding_table;
 extern const struct brw_tracked_state gen6_renderbuffer_surfaces;
 extern const struct brw_tracked_state gen6_sampler_state;
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c 
b/src/mesa/drivers/dri/i965/gen6_cc.c
deleted file mode 100644
index 688362f..000
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *Eric Anholt 
- *
- */
-
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "brw_util.h"
-#include "intel_batchbuffer.h"
-#include "main/macros.h"
-#include "main/enums.h"
-#include "main/glformats.h"
-#include "main/stencil.h"
-
-static void
-gen6_upload_color_calc_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   struct gen6_color_calc_state *cc;
-
-   cc = brw_state_batch(brw, sizeof(*cc), 64, >cc.state_offset);
-   memset(cc, 0, sizeof(*cc));
-
-   /* _NEW_COLOR */
-   cc->cc0.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8;
-   UNCLAMPED_FLOAT_TO_UBYTE(cc->cc1.alpha_ref_fi.ui, ctx->Color.AlphaRef);
-
-   if (brw->gen < 9) {
-  /* _NEW_STENCIL */
-  cc->cc0.stencil_ref = _mesa_get_stencil_ref(ctx, 0);
-  cc->cc0.bf_stencil_ref =
- _mesa_get_stencil_ref(ctx, ctx->Stencil._BackFace);
-   }
-
-   /* _NEW_COLOR */
-   cc->constant_r = ctx->Color.BlendColorUnclamped[0];
-   cc->constant_g = ctx->Color.BlendColorUnclamped[1];
-   cc->constant_b = ctx->Color.BlendColorUnclamped[2];
-   cc->constant_a = ctx->Color.BlendColorUnclamped[3];
-
-   /* Point the GPU at the new indirect state. */
-   if (brw->gen == 6) {
-  BEGIN_BATCH(4);
-  OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  OUT_BATCH(brw->cc.state_offset | 1);
-  ADVANCE_BATCH();
-   } else {
-  BEGIN_BATCH(2);
-  OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
-  OUT_BATCH(brw->cc.state_offset | 1);
-  ADVANCE_BATCH();
-   }
-}
-
-const struct brw_tracked_state gen6_color_calc_state = {
-   .dirty = {
-  .mesa = _NEW_COLOR |
-  _NEW_STENCIL,
-  .brw = BRW_NEW_BATCH |
- BRW_NEW_BLORP |
- BRW_NEW_CC_STATE |
- BRW_NEW_STATE_BASE_ADDRESS,
-   },
-   .emit = gen6_upload_color_calc_state,
-};
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 

[Mesa-dev] [PATCH v02 03/37] genxml: Rename clip enable property.

[Rafael Antognolli]

There are two variants:
   - Clip Enable
   - CLIP Enable (on gen6)

Rename everything to Clip Enable.

Signed-off-by: Rafael Antognolli 
Reviewed-by: Kenneth Graunke 
---
 src/intel/genxml/gen4.xml  | 2 +-
 src/intel/genxml/gen45.xml | 2 +-
 src/intel/genxml/gen5.xml  | 2 +-
 src/intel/genxml/gen6.xml  | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/intel/genxml/gen4.xml b/src/intel/genxml/gen4.xml
index 0ea66e5..d3a2f92 100644
--- a/src/intel/genxml/gen4.xml
+++ b/src/intel/genxml/gen4.xml
@@ -968,7 +968,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml
index bff32f9..547e278 100644
--- a/src/intel/genxml/gen45.xml
+++ b/src/intel/genxml/gen45.xml
@@ -935,7 +935,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
index fc6f248..0b84650 100644
--- a/src/intel/genxml/gen5.xml
+++ b/src/intel/genxml/gen5.xml
@@ -1091,7 +1091,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 3059bfc..094887a 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -806,7 +806,7 @@
 
 
 
-
+
 
   
   
-- 
git-series 0.9.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v02 28/37] i965: Port gen6+ 3DSTATE_VS to genxml.

[Rafael Antognolli]

Emit 3DSTATE_VS on Gen6+ using brw_batch_emit helper, that uses pack
structs from genxml.

v2:
   - Use render_bo helper to setup brw_address (Kristian)

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/Makefile.sources|   2 +-
 src/mesa/drivers/dri/i965/brw_state.h |   3 +-
 src/mesa/drivers/dri/i965/gen6_vs_state.c | 113 +---
 src/mesa/drivers/dri/i965/gen7_vs_state.c |  87 +---
 src/mesa/drivers/dri/i965/gen8_vs_state.c |  96 +
 src/mesa/drivers/dri/i965/genX_state_upload.c | 106 +-
 6 files changed, 103 insertions(+), 304 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_vs_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_vs_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 7f25ae1..95d29ac 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -100,7 +100,6 @@ i965_FILES = \
gen7_te_state.c \
gen7_urb.c \
gen7_viewport_state.c \
-   gen7_vs_state.c \
gen7_wm_surface_state.c \
gen8_blend_state.c \
gen8_depth_state.c \
@@ -111,7 +110,6 @@ i965_FILES = \
gen8_multisample_state.c \
gen8_surface_state.c \
gen8_viewport_state.c \
-   gen8_vs_state.c \
hsw_queryobj.c \
hsw_sol.c \
intel_batchbuffer.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index a87bf3a..72d63f6 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -123,7 +123,6 @@ extern const struct brw_tracked_state gen6_sf_vp;
 extern const struct brw_tracked_state gen6_urb;
 extern const struct brw_tracked_state gen6_viewport_state;
 extern const struct brw_tracked_state gen6_vs_push_constants;
-extern const struct brw_tracked_state gen6_vs_state;
 extern const struct brw_tracked_state gen6_wm_push_constants;
 extern const struct brw_tracked_state gen7_depthbuffer;
 extern const struct brw_tracked_state gen7_ds_state;
@@ -136,7 +135,6 @@ extern const struct brw_tracked_state gen7_sf_clip_viewport;
 extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
-extern const struct brw_tracked_state gen7_vs_state;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_blend_state;
 extern const struct brw_tracked_state gen8_ds_state;
@@ -149,7 +147,6 @@ extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
-extern const struct brw_tracked_state gen8_vs_state;
 extern const struct brw_tracked_state brw_cs_work_groups_surface;
 
 static inline bool
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c 
b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 17b8118..b2d2306 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -68,116 +68,3 @@ const struct brw_tracked_state gen6_vs_push_constants = {
},
.emit = gen6_upload_vs_push_constants,
 };
-
-static void
-upload_vs_state(struct brw_context *brw)
-{
-   const struct gen_device_info *devinfo = >screen->devinfo;
-   const struct brw_stage_state *stage_state = >vs.base;
-   const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
-   const struct brw_vue_prog_data *vue_prog_data =
-  brw_vue_prog_data(stage_state->prog_data);
-   uint32_t floating_point_mode = 0;
-
-   /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
-* 3DSTATE_VS, Dword 5.0 "VS Function Enable":
-*
-*   [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
-*   command that causes the VS Function Enable to toggle. Pipeline
-*   flush can be executed by sending a PIPE_CONTROL command with CS
-*   stall bit set and a post sync operation.
-*
-* We've already done such a flush at the start of state upload, so we
-* don't need to do another one here.
-*/
-
-   if (stage_state->push_const_size == 0) {
-  /* Disable the push constant buffers. */
-  BEGIN_BATCH(5);
-  OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  ADVANCE_BATCH();
-   } else {
-  BEGIN_BATCH(5);
-  OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 |
-   GEN6_CONSTANT_BUFFER_0_ENABLE |
-   (5 - 2));
-  /* Pointer to the VS constant buffer.  Covered by the set of
-   * state flags from gen6_upload_vs_constants
-   */
-  OUT_BATCH(stage_state->push_const_offset +
-   stage_state->push_const_size - 1);
-  

[Mesa-dev] [PATCH v02 14/37] anv: Use BRW_BARYCENTRIC_NONPERSPECTIVE_BITS from common header.

[Rafael Antognolli]

In a previous patch some enums were split out from brw_eu_defines.h, so
they could be used by genxml based code. anv can also benefit from this.

Signed-off-by: Rafael Antognolli 
---
 src/intel/vulkan/genX_pipeline.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index a6b4134..cf444c9 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -28,6 +28,7 @@
 
 #include "common/gen_l3_config.h"
 #include "common/gen_sample_positions.h"
+#include "compiler/brw_defines_common.h"
 #include "vk_format_info.h"
 
 static uint32_t
@@ -1059,7 +1060,8 @@ emit_3dstate_clip(struct anv_pipeline *pipeline,
   }
 #else
   clip.NonPerspectiveBarycentricEnable = wm_prog_data ?
- (wm_prog_data->barycentric_interp_modes & 0x38) != 0 : 0;
+ (wm_prog_data->barycentric_interp_modes &
+  BRW_BARYCENTRIC_NONPERSPECTIVE_BITS) != 0 : 0;
 #endif
}
 }
-- 
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[Mesa-dev] [PATCH v02 15/37] i965: Add genxml related plumbing in a new genX_state_upload.c file.

[Rafael Antognolli]

From: Kenneth Graunke 

Signed-off-by: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/Makefile.sources|  15 ++-
 src/mesa/drivers/dri/i965/genX_state_upload.c | 109 +++-
 2 files changed, 119 insertions(+), 5 deletions(-)
 create mode 100644 src/mesa/drivers/dri/i965/genX_state_upload.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index aef1a7a..db55a3f 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -161,19 +161,24 @@ i965_FILES = \
libdrm_macros.h
 
 i965_gen6_FILES = \
-   genX_blorp_exec.c
+   genX_blorp_exec.c \
+   genX_state_upload.c
 
 i965_gen7_FILES = \
-   genX_blorp_exec.c
+   genX_blorp_exec.c \
+   genX_state_upload.c
 
 i965_gen75_FILES = \
-   genX_blorp_exec.c
+   genX_blorp_exec.c \
+   genX_state_upload.c
 
 i965_gen8_FILES = \
-   genX_blorp_exec.c
+   genX_blorp_exec.c \
+   genX_state_upload.c
 
 i965_gen9_FILES = \
-   genX_blorp_exec.c
+   genX_blorp_exec.c \
+   genX_state_upload.c
 
 i965_oa_GENERATED_FILES = \
brw_oa_hsw.h \
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
new file mode 100644
index 000..25bf4b6
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include 
+
+#include "common/gen_device_info.h"
+#include "genxml/gen_macros.h"
+
+#include "brw_context.h"
+#include "brw_state.h"
+
+#include "intel_batchbuffer.h"
+
+UNUSED static void *
+emit_dwords(struct brw_context *brw, unsigned n)
+{
+   intel_batchbuffer_begin(brw, n, RENDER_RING);
+   uint32_t *map = brw->batch.map_next;
+   brw->batch.map_next += n;
+   intel_batchbuffer_advance(brw);
+   return map;
+}
+
+struct brw_address {
+   struct brw_bo *bo;
+   uint32_t read_domains;
+   uint32_t write_domain;
+   uint32_t offset;
+};
+
+static uint64_t
+emit_reloc(struct brw_context *brw,
+   void *location, struct brw_address address, uint32_t delta)
+{
+   uint32_t offset = (char *) location - (char *) brw->batch.map;
+
+   return brw_emit_reloc(>batch, offset, address.bo,
+ address.offset + delta,
+ address.read_domains,
+ address.write_domain);
+}
+
+#define __gen_address_type struct brw_address
+#define __gen_user_data struct brw_context
+
+static uint64_t
+__gen_combine_address(struct brw_context *brw, void *location,
+  struct brw_address address, uint32_t delta)
+{
+   if (address.bo == NULL) {
+  return address.offset + delta;
+   } else {
+  return emit_reloc(brw, location, address, delta);
+   }
+}
+
+#include "genxml/genX_pack.h"
+
+#define _brw_cmd_length(cmd) cmd ## _length
+#define _brw_cmd_length_bias(cmd) cmd ## _length_bias
+#define _brw_cmd_header(cmd) cmd ## _header
+#define _brw_cmd_pack(cmd) cmd ## _pack
+
+#define brw_batch_emit(brw, cmd, name)  \
+   for (struct cmd name = { _brw_cmd_header(cmd) }, \
+*_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
+__builtin_expect(_dst != NULL, 1);  \
+_brw_cmd_pack(cmd)(brw, (void *)_dst, ),   \
+_dst = NULL)
+
+#define brw_batch_emitn(brw, cmd, n) ({\
+  uint32_t *_dw = emit_dwords(brw, n); \
+  struct cmd template = {  \
+ _brw_cmd_header(cmd), \
+ .DWordLength = n - _brw_cmd_length_bias(cmd), \
+  };   \
+  _brw_cmd_pack(cmd)(brw, _dw, ); \
+  _dw + 1; /* Array starts at dw[1] */ \
+   })
+
+#define 

[Mesa-dev] [PATCH v02 06/37] genxml: Add alias for MOCS.

[Rafael Antognolli]

Use an alias, so we can set the same value as the #define's.

Signed-off-by: Rafael Antognolli 
---
 src/intel/genxml/gen8.xml | 1 +
 src/intel/genxml/gen9.xml | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 408d241..2908082 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -2064,6 +2064,7 @@
 
 
 
+
 
 
 
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 59daa31..09b9464 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2246,6 +2246,7 @@
 
 
 
+
 
 
 
-- 
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[Mesa-dev] [PATCH v02 25/37] i965: Port gen7+ 3DSTATE_PS to genxml.

[Rafael Antognolli]

Emit 3DSTATE_PS on Gen7+ using brw_batch_emit helper, that uses pack
structs from genxml.

v2:
   - Use render_bo helper to setup brw_address (Kristian)

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/brw_state.h |   2 +-
 src/mesa/drivers/dri/i965/gen7_wm_state.c | 137 +---
 src/mesa/drivers/dri/i965/gen8_ps_state.c | 114 +
 src/mesa/drivers/dri/i965/genX_state_upload.c | 133 +-
 4 files changed, 131 insertions(+), 255 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 94f758b..c55c175 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -132,7 +132,6 @@ extern const struct brw_tracked_state gen7_gs_state;
 extern const struct brw_tracked_state gen7_tcs_push_constants;
 extern const struct brw_tracked_state gen7_hs_state;
 extern const struct brw_tracked_state gen7_l3_state;
-extern const struct brw_tracked_state gen7_ps_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
 extern const struct brw_tracked_state gen7_sf_clip_viewport;
 extern const struct brw_tracked_state gen7_te_state;
@@ -150,7 +149,6 @@ extern const struct brw_tracked_state 
gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
-extern const struct brw_tracked_state gen8_ps_state;
 extern const struct brw_tracked_state gen8_wm_state;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c 
b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 1c33db4..c9c36ae 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -144,140 +144,3 @@ const struct brw_tracked_state gen7_wm_state = {
},
.emit = upload_wm_state,
 };
-
-static void
-gen7_upload_ps_state(struct brw_context *brw,
- const struct brw_stage_state *stage_state,
- const struct brw_wm_prog_data *prog_data,
- bool enable_dual_src_blend, unsigned sample_mask,
- unsigned fast_clear_op)
-{
-   const struct gen_device_info *devinfo = >screen->devinfo;
-   uint32_t dw2, dw4, dw5, ksp0, ksp2;
-   const int max_threads_shift = brw->is_haswell ?
-  HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
-
-   dw2 = dw4 = dw5 = ksp2 = 0;
-
-   const unsigned sampler_count =
-  DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
-   dw2 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT);
-
-   dw2 |= ((prog_data->base.binding_table.size_bytes / 4) <<
-   GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
-
-   if (prog_data->base.use_alt_mode)
-  dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
-
-   /* Haswell requires the sample mask to be set in this packet as well as
-* in 3DSTATE_SAMPLE_MASK; the values should match. */
-   /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
-   if (brw->is_haswell)
-  dw4 |= SET_FIELD(sample_mask, HSW_PS_SAMPLE_MASK);
-
-   dw4 |= (devinfo->max_wm_threads - 1) << max_threads_shift;
-
-   if (prog_data->base.nr_params > 0)
-  dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
-
-   /* From the IVB PRM, volume 2 part 1, page 287:
-* "This bit is inserted in the PS payload header and made available to
-* the DataPort (either via the message header or via header bypass) to
-* indicate that oMask data (one or two phases) is included in Render
-* Target Write messages. If present, the oMask data is used to mask off
-* samples."
-*/
-   if (prog_data->uses_omask)
-  dw4 |= GEN7_PS_OMASK_TO_RENDER_TARGET;
-
-   /* From the IVB PRM, volume 2 part 1, page 287:
-* "If the PS kernel does not need the Position XY Offsets to
-* compute a Position Value, then this field should be programmed
-* to POSOFFSET_NONE."
-* "SW Recommendation: If the PS kernel needs the Position Offsets
-* to compute a Position XY value, this field should match Position
-* ZW Interpolation Mode to ensure a consistent position.xyzw
-* computation."
-* We only require XY sample offsets. So, this recommendation doesn't
-* look useful at the moment. We might need this in future.
-*/
-   if (prog_data->uses_pos_offset)
-  dw4 |= GEN7_PS_POSOFFSET_SAMPLE;
-   else
-  dw4 |= GEN7_PS_POSOFFSET_NONE;
-
-   /* The hardware wedges if you have this bit set but don't turn on any dual
-* source blend factors.
-*/
-   if (enable_dual_src_blend)
-  dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
-
-   /* BRW_NEW_FS_PROG_DATA */
-   if (prog_data->num_varying_inputs != 0)
-  dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
-
-   dw4 |= fast_clear_op;
-
-   if (prog_data->dispatch_16)
-  dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
-
-   if 

[Mesa-dev] [PATCH v02 05/37] genxml: Add missing field values to 3DSTATE_SBE.

[Rafael Antognolli]

Fill out "Attribute Active Component Format" possible values.

Signed-off-by: Rafael Antognolli 
---
 src/intel/genxml/gen9.xml | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index ee7056b..59daa31 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2173,7 +2173,12 @@
 
 
 
-  
+  
+ 
+ 
+ 
+ 
+  
 
   
 
-- 
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[Mesa-dev] [PATCH v02 22/37] i965: Port Gen7+ 3DSTATE_SBE state to genxml.

[Rafael Antognolli]

Emit 3DSTATE_SBE on Gen7+ using brw_batch_emit helper, that uses pack
structs from genxml.

v2:
   - Use ACTIVE_COMPONENT_XYZW from gen9.xml.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/Makefile.sources|   2 +-
 src/mesa/drivers/dri/i965/brw_state.h |   2 +-
 src/mesa/drivers/dri/i965/gen7_sf_state.c | 109 +--
 src/mesa/drivers/dri/i965/gen8_sf_state.c | 153 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 129 +++-
 5 files changed, 121 insertions(+), 274 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_sf_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_sf_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index b085251..81759ed 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -97,7 +97,6 @@ i965_FILES = \
gen7_hs_state.c \
gen7_l3_state.c \
gen7_misc_state.c \
-   gen7_sf_state.c \
gen7_sol_state.c \
gen7_te_state.c \
gen7_urb.c \
@@ -113,7 +112,6 @@ i965_FILES = \
gen8_hs_state.c \
gen8_multisample_state.c \
gen8_ps_state.c \
-   gen8_sf_state.c \
gen8_sol_state.c \
gen8_surface_state.c \
gen8_viewport_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 594757c..bc68c2c 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -134,7 +134,6 @@ extern const struct brw_tracked_state gen7_hs_state;
 extern const struct brw_tracked_state gen7_l3_state;
 extern const struct brw_tracked_state gen7_ps_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
-extern const struct brw_tracked_state gen7_sbe_state;
 extern const struct brw_tracked_state gen7_sf_clip_viewport;
 extern const struct brw_tracked_state gen7_sol_state;
 extern const struct brw_tracked_state gen7_te_state;
@@ -154,7 +153,6 @@ extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
 extern const struct brw_tracked_state gen8_ps_state;
 extern const struct brw_tracked_state gen8_wm_state;
-extern const struct brw_tracked_state gen8_sbe_state;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c 
b/src/mesa/drivers/dri/i965/gen7_sf_state.c
deleted file mode 100644
index 7ab8a99..000
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright © 2011 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "brw_util.h"
-#include "main/macros.h"
-#include "main/fbobject.h"
-#include "main/framebuffer.h"
-#include "intel_batchbuffer.h"
-
-static void
-upload_sbe_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   /* BRW_NEW_FS_PROG_DATA */
-   const struct brw_wm_prog_data *wm_prog_data =
-  brw_wm_prog_data(brw->wm.base.prog_data);
-   uint32_t num_outputs = wm_prog_data->num_varying_inputs;
-   uint32_t dw1;
-   uint32_t point_sprite_enables;
-   int i;
-   uint16_t attr_overrides[16];
-   /* _NEW_BUFFERS */
-   bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
-   uint32_t point_sprite_origin;
-
-   /* FINISHME: Attribute Swizzle Control Mode? */
-   dw1 = GEN7_SBE_SWIZZLE_ENABLE | num_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT;
-
-   /* _NEW_POINT
-*
-* Window coordinates in an FBO are inverted, which means point
-* sprite origin must be inverted.
-*/
-   if ((ctx->Point.SpriteOrigin == GL_LOWER_LEFT) != 

[Mesa-dev] [PATCH v02 26/37] i965: Port gen6+ 3DSTATE_WM to genxml.

[Rafael Antognolli]

Emit 3DSTATE_WM on Gen6+ using brw_batch_emit helper, that uses pack
structs from genxml.

v2:
   - Use render_bo helper to setup brw_address (Kristian)
   - Remove TODO and use BRW_PSCDEPTH_OFF.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/Makefile.sources|   1 +-
 src/mesa/drivers/dri/i965/brw_state.h |  14 +-
 src/mesa/drivers/dri/i965/gen6_wm_state.c | 219 +---
 src/mesa/drivers/dri/i965/gen7_wm_state.c | 146 +-
 src/mesa/drivers/dri/i965/gen8_ps_state.c |  49 +
 src/mesa/drivers/dri/i965/genX_state_upload.c | 192 -
 6 files changed, 189 insertions(+), 432 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_wm_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index bfcf57c..da09df8 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -101,7 +101,6 @@ i965_FILES = \
gen7_urb.c \
gen7_viewport_state.c \
gen7_vs_state.c \
-   gen7_wm_state.c \
gen7_wm_surface_state.c \
gen8_blend_state.c \
gen8_depth_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index c55c175..5010237 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -125,7 +125,6 @@ extern const struct brw_tracked_state gen6_viewport_state;
 extern const struct brw_tracked_state gen6_vs_push_constants;
 extern const struct brw_tracked_state gen6_vs_state;
 extern const struct brw_tracked_state gen6_wm_push_constants;
-extern const struct brw_tracked_state gen6_wm_state;
 extern const struct brw_tracked_state gen7_depthbuffer;
 extern const struct brw_tracked_state gen7_ds_state;
 extern const struct brw_tracked_state gen7_gs_state;
@@ -138,7 +137,6 @@ extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state gen7_vs_state;
-extern const struct brw_tracked_state gen7_wm_state;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_blend_state;
 extern const struct brw_tracked_state gen8_ds_state;
@@ -149,7 +147,6 @@ extern const struct brw_tracked_state 
gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
-extern const struct brw_tracked_state gen8_wm_state;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
@@ -320,17 +317,6 @@ void brw_emit_sampler_state(struct brw_context *brw,
 bool non_normalized_coordinates,
 uint32_t border_color_offset);
 
-/* gen6_wm_state.c */
-void
-gen6_upload_wm_state(struct brw_context *brw,
- const struct brw_wm_prog_data *prog_data,
- const struct brw_stage_state *stage_state,
- bool multisampled_fbo,
- bool dual_source_blend_enable, bool kill_enable,
- bool color_buffer_write_enable, bool msaa_enabled,
- bool line_stipple_enable, bool polygon_stipple_enable,
- bool statistic_enable);
-
 /* gen6_surface_state.c */
 void gen6_init_vtable_surface_functions(struct brw_context *brw);
 
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c 
b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index aabae70..9da1bdd 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -68,222 +68,3 @@ const struct brw_tracked_state gen6_wm_push_constants = {
},
.emit = gen6_upload_wm_push_constants,
 };
-
-void
-gen6_upload_wm_state(struct brw_context *brw,
- const struct brw_wm_prog_data *prog_data,
- const struct brw_stage_state *stage_state,
- bool multisampled_fbo,
- bool dual_source_blend_enable, bool kill_enable,
- bool color_buffer_write_enable, bool msaa_enabled,
- bool line_stipple_enable, bool polygon_stipple_enable,
- bool statistic_enable)
-{
-   const struct gen_device_info *devinfo = >screen->devinfo;
-   uint32_t dw2, dw4, dw5, dw6, ksp0, ksp2;
-
-   /* We can't fold this into gen6_upload_wm_push_constants(), because
-* according to the SNB PRM, vol 2 part 1 section 7.2.2
-* (3DSTATE_CONSTANT_PS [DevSNB]):
-*
-* "[DevSNB]: This packet must be followed by WM_STATE."
-*/
-   if (prog_data->base.nr_params == 0) {
-  /* Disable the push constant buffers. */
-  BEGIN_BATCH(5);
-  

[Mesa-dev] [PATCH v02 11/37] genxml: Normalize xml for 3DSTATE_MULTISAMPLE.

[Rafael Antognolli]

Name the options to "Pixel Location":
   - PIXLOC_CENTER -> CENTER
   - PIXLOC_UL_CORNER -> UL_CORNER

Signed-off-by: Rafael Antognolli 
---
 src/intel/blorp/blorp_genX_exec.h | 4 +---
 src/intel/genxml/gen6.xml | 4 ++--
 src/intel/genxml/gen7.xml | 4 ++--
 src/intel/genxml/gen75.xml| 4 ++--
 src/intel/vulkan/genX_pipeline.c  | 3 +--
 5 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index bc829d0..be22be0 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1188,9 +1188,7 @@ blorp_emit_3dstate_multisample(struct blorp_batch *batch,
*should not have any effect by setting or not setting this bit.
*/
   ms.PixelPositionOffsetEnable  = false;
-  ms.PixelLocation  = CENTER;
 #elif GEN_GEN >= 7
-  ms.PixelLocation  = PIXLOC_CENTER;
 
   switch (params->num_samples) {
   case 1:
@@ -1209,9 +1207,9 @@ blorp_emit_3dstate_multisample(struct blorp_batch *batch,
  break;
   }
 #else
-  ms.PixelLocation  = PIXLOC_CENTER;
   GEN_SAMPLE_POS_4X(ms.Sample);
 #endif
+  ms.PixelLocation  = CENTER;
}
 }
 
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 2cb9419..a8ce7e0 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1089,8 +1089,8 @@
 
 
 
-  
-  
+  
+  
 
 
   
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index b4407d4..8530ed9 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1262,8 +1262,8 @@
 
 
 
-  
-  
+  
+  
 
 
   
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 8c8b776..07eafee 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -1548,8 +1548,8 @@
 
 
 
-  
-  
+  
+  
 
 
   
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 2b38c34..a6b4134 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -549,6 +549,7 @@ emit_ms_state(struct anv_pipeline *pipeline,
anv_batch_emit(>batch, GENX(3DSTATE_MULTISAMPLE), ms) {
   ms.NumberofMultisamples   = log2_samples;
 
+  ms.PixelLocation  = CENTER;
 #if GEN_GEN >= 8
   /* The PRM says that this bit is valid only for DX9:
*
@@ -556,9 +557,7 @@ emit_ms_state(struct anv_pipeline *pipeline,
*should not have any effect by setting or not setting this bit.
*/
   ms.PixelPositionOffsetEnable  = false;
-  ms.PixelLocation  = CENTER;
 #else
-  ms.PixelLocation  = PIXLOC_CENTER;
 
   switch (samples) {
   case 1:
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH v02 30/37] i965: Port gen6+ blend state code to genxml.

[Rafael Antognolli]

Upload blend states using GENX(BLEND_STATE_ENTRY_pack), generated from
genxml.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/Makefile.sources|   1 +-
 src/mesa/drivers/dri/i965/brw_state.h |   3 +-
 src/mesa/drivers/dri/i965/gen6_cc.c   | 216 +
 src/mesa/drivers/dri/i965/gen8_blend_state.c  | 298 +-
 src/mesa/drivers/dri/i965/genX_state_upload.c | 336 ++-
 5 files changed, 332 insertions(+), 522 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_blend_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 3f0c66a..0c67170 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -99,7 +99,6 @@ i965_FILES = \
gen7_te_state.c \
gen7_urb.c \
gen7_wm_surface_state.c \
-   gen8_blend_state.c \
gen8_depth_state.c \
gen8_draw_upload.c \
gen8_multisample_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index b6e8abc..cf043a0 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -108,7 +108,6 @@ extern const struct brw_tracked_state brw_index_buffer;
 extern const struct brw_tracked_state brw_cs_state;
 extern const struct brw_tracked_state gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
-extern const struct brw_tracked_state gen6_blend_state;
 extern const struct brw_tracked_state gen6_color_calc_state;
 extern const struct brw_tracked_state gen6_gs_push_constants;
 extern const struct brw_tracked_state gen6_gs_binding_table;
@@ -130,11 +129,9 @@ extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state haswell_cut_index;
-extern const struct brw_tracked_state gen8_blend_state;
 extern const struct brw_tracked_state gen8_index_buffer;
 extern const struct brw_tracked_state gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
-extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
 extern const struct brw_tracked_state brw_cs_work_groups_surface;
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c 
b/src/mesa/drivers/dri/i965/gen6_cc.c
index 0e0d05e..688362f 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -36,222 +36,6 @@
 #include "main/stencil.h"
 
 static void
-gen6_upload_blend_state(struct brw_context *brw)
-{
-   bool is_buffer_zero_integer_format = false;
-   struct gl_context *ctx = >ctx;
-   struct gen6_blend_state *blend;
-   int b;
-   int nr_draw_buffers = ctx->DrawBuffer->_NumColorDrawBuffers;
-   int size;
-
-   /* We need at least one BLEND_STATE written, because we might do
-* thread dispatch even if _NumColorDrawBuffers is 0 (for example
-* for computed depth or alpha test), which will do an FB write
-* with render target 0, which will reference BLEND_STATE[0] for
-* alpha test enable.
-*/
-   if (nr_draw_buffers == 0)
-  nr_draw_buffers = 1;
-
-   size = sizeof(*blend) * nr_draw_buffers;
-   blend = brw_state_batch(brw, size, 64, >cc.blend_state_offset);
-
-   memset(blend, 0, size);
-
-   for (b = 0; b < nr_draw_buffers; b++) {
-  /* _NEW_BUFFERS */
-  struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[b];
-  GLenum rb_type;
-  bool integer;
-
-  if (rb)
-rb_type = _mesa_get_format_datatype(rb->Format);
-  else
-rb_type = GL_UNSIGNED_NORMALIZED;
-
-  /* Used for implementing the following bit of GL_EXT_texture_integer:
-   * "Per-fragment operations that require floating-point color
-   *  components, including multisample alpha operations, alpha test,
-   *  blending, and dithering, have no effect when the corresponding
-   *  colors are written to an integer color buffer."
-  */
-  integer = (rb_type == GL_INT || rb_type == GL_UNSIGNED_INT);
-
-  if(b == 0 && integer)
- is_buffer_zero_integer_format = true;
-
-  /* _NEW_COLOR */
-  if (ctx->Color.ColorLogicOpEnabled) {
-/* Floating point RTs should have no effect from LogicOp,
- * except for disabling of blending, but other types should.
- *
- * However, from the Sandy Bridge PRM, Vol 2 Par 1, Section 8.1.11,
- * "Logic Ops",
- *
- * "Logic Ops are only supported on *_UNORM surfaces (excluding
- *  _SRGB variants), otherwise Logic Ops must be DISABLED."
- */
- WARN_ONCE(ctx->Color.LogicOp != GL_COPY &&
-   rb_type != GL_UNSIGNED_NORMALIZED &&
-   

[Mesa-dev] [PATCH v02 32/37] i965: Port gen6+ 3DSTATE_SCISSOR_STATE_POINTERS to use genxml.

[Rafael Antognolli]

Emit 3DSTATE_SCISSOR_STATE_POINTERS using brw_batch_emit, and pack the
scissor states using GENX(SCISSOR_RECT_pack), generated from genxml.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/brw_state.h |  1 +-
 src/mesa/drivers/dri/i965/genX_state_upload.c | 89 +++-
 2 files changed, 86 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 322d767..6adcf46 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -114,7 +114,6 @@ extern const struct brw_tracked_state gen6_gs_binding_table;
 extern const struct brw_tracked_state gen6_multisample_state;
 extern const struct brw_tracked_state gen6_renderbuffer_surfaces;
 extern const struct brw_tracked_state gen6_sampler_state;
-extern const struct brw_tracked_state gen6_scissor_state;
 extern const struct brw_tracked_state gen6_sol_surface;
 extern const struct brw_tracked_state gen6_sf_vp;
 extern const struct brw_tracked_state gen6_urb;
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 45b02a6..3ad9707 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -1651,6 +1651,89 @@ static const struct brw_tracked_state genX(blend_state) 
= {
.emit = genX(upload_blend_state),
 };
 
+/* -- */
+
+static void
+genX(upload_scissor_state)(struct brw_context *brw)
+{
+   struct gl_context *ctx = >ctx;
+   const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
+   struct GENX(SCISSOR_RECT) scissor;
+   uint32_t scissor_state_offset;
+   const unsigned int fb_width= _mesa_geometric_width(ctx->DrawBuffer);
+   const unsigned int fb_height = _mesa_geometric_height(ctx->DrawBuffer);
+   uint32_t *scissor_map;
+
+   /* BRW_NEW_VIEWPORT_COUNT */
+   const unsigned viewport_count = brw->clip.viewport_count;
+
+   scissor_map = brw_state_batch(
+  brw, GENX(SCISSOR_RECT_length) * sizeof(uint32_t) * viewport_count,
+  32, _state_offset);
+
+   /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
+
+   /* The scissor only needs to handle the intersection of drawable and
+* scissor rect.  Clipping to the boundaries of static shared buffers
+* for front/back/depth is covered by looping over cliprects in brw_draw.c.
+*
+* Note that the hardware's coordinates are inclusive, while Mesa's min is
+* inclusive but max is exclusive.
+*/
+   for (unsigned i = 0; i < viewport_count; i++) {
+  int bbox[4];
+
+  bbox[0] = MAX2(ctx->ViewportArray[i].X, 0);
+  bbox[1] = MIN2(bbox[0] + ctx->ViewportArray[i].Width, fb_width);
+  bbox[2] = MAX2(ctx->ViewportArray[i].Y, 0);
+  bbox[3] = MIN2(bbox[2] + ctx->ViewportArray[i].Height, fb_height);
+  _mesa_intersect_scissor_bounding_box(ctx, i, bbox);
+
+  if (bbox[0] == bbox[1] || bbox[2] == bbox[3]) {
+ /* If the scissor was out of bounds and got clamped to 0 width/height
+  * at the bounds, the subtraction of 1 from maximums could produce a
+  * negative number and thus not clip anything.  Instead, just provide
+  * a min > max scissor inside the bounds, which produces the expected
+  * no rendering.
+  */
+ scissor.ScissorRectangleXMin = 1;
+ scissor.ScissorRectangleXMax = 0;
+ scissor.ScissorRectangleYMin = 1;
+ scissor.ScissorRectangleYMax = 0;
+  } else if (render_to_fbo) {
+ /* texmemory: Y=0=bottom */
+ scissor.ScissorRectangleXMin = bbox[0];
+ scissor.ScissorRectangleXMax = bbox[1] - 1;
+ scissor.ScissorRectangleYMin = bbox[2];
+ scissor.ScissorRectangleYMax = bbox[3] - 1;
+  } else {
+ /* memory: Y=0=top */
+ scissor.ScissorRectangleXMin = bbox[0];
+ scissor.ScissorRectangleXMax = bbox[1] - 1;
+ scissor.ScissorRectangleYMin = fb_height - bbox[3];
+ scissor.ScissorRectangleYMax = fb_height - bbox[2] - 1;
+  }
+
+  GENX(SCISSOR_RECT_pack)(NULL, scissor_map + i * 2, );
+   }
+
+   brw_batch_emit(brw, GENX(3DSTATE_SCISSOR_STATE_POINTERS), ptr) {
+  ptr.ScissorRectPointer = scissor_state_offset;
+   }
+}
+
+static const struct brw_tracked_state genX(scissor_state) = {
+   .dirty = {
+  .mesa = _NEW_BUFFERS |
+  _NEW_SCISSOR |
+  _NEW_VIEWPORT,
+  .brw = BRW_NEW_BATCH |
+ BRW_NEW_BLORP |
+ BRW_NEW_VIEWPORT_COUNT,
+   },
+   .emit = genX(upload_scissor_state),
+};
+
 #endif
 
 /* -- */
@@ -2771,7 +2854,7 @@ genX(init_atoms)(struct brw_context *brw)
   (sf_state),
   (wm_state),
 
-  _scissor_state,
+  (scissor_state),
 
   _binding_table_pointers,
 
@@ -2861,7 +2944,7 @@ genX(init_atoms)(struct 

[Mesa-dev] [PATCH v02 04/37] genxml: Update xml for 3DSTATE_SF.

[Rafael Antognolli]

- Normalize "Anti-Aliasing Enable"
 - Add "Multisample Rasterization Mode" constants
 - Rename "Use Point Width on Vertex" to "Vertex"
 - Rename "Use Point Width from State" to "State"

Signed-off-by: Rafael Antognolli 
---
 src/intel/genxml/gen6.xml | 15 ++-
 src/intel/genxml/gen7.xml |  7 ++-
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 094887a..8ead41f 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1215,7 +1215,7 @@
   
   
 
-
+
 
   
   
@@ -1230,7 +1230,12 @@
   
 
 
-
+
+  
+  
+  
+  
+
 
 
   
@@ -1253,9 +1258,9 @@
   
   
 
-
-  
-  
+
+  
+  
 
 
 
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 867a1d4..440258a 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1602,7 +1602,12 @@
   
 
 
-
+
+  
+  
+  
+  
+   
 
 
   
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH v02 29/37] i965: Port gen6+ state emitting code to genxml.

[Rafael Antognolli]

Ported in this patch:
   - 3DSTATE_DS
   - 3DSTATE_GS
   - 3DSTATE_HS
   - 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/Makefile.sources  |   6 +-
 src/mesa/drivers/dri/i965/brw_state.h   |  18 +-
 src/mesa/drivers/dri/i965/gen6_gs_state.c   | 129 +-
 src/mesa/drivers/dri/i965/gen6_viewport_state.c | 147 +--
 src/mesa/drivers/dri/i965/gen7_ds_state.c   |  69 +---
 src/mesa/drivers/dri/i965/gen7_gs_state.c   | 168 +--
 src/mesa/drivers/dri/i965/gen7_hs_state.c   |  63 +--
 src/mesa/drivers/dri/i965/gen7_viewport_state.c | 100 +
 src/mesa/drivers/dri/i965/gen8_ds_state.c   | 116 +
 src/mesa/drivers/dri/i965/gen8_gs_state.c   | 146 +-
 src/mesa/drivers/dri/i965/gen8_hs_state.c   |  93 +---
 src/mesa/drivers/dri/i965/gen8_viewport_state.c | 120 +-
 src/mesa/drivers/dri/i965/genX_state_upload.c   | 453 -
 13 files changed, 446 insertions(+), 1182 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_gs_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_viewport_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_ds_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_gs_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_hs_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_viewport_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 95d29ac..3f0c66a 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -92,24 +92,18 @@ i965_FILES = \
gen6_wm_state.c \
gen7_cs_state.c \
gen7_ds_state.c \
-   gen7_gs_state.c \
gen7_hs_state.c \
gen7_l3_state.c \
gen7_misc_state.c \
gen7_sol_state.c \
gen7_te_state.c \
gen7_urb.c \
-   gen7_viewport_state.c \
gen7_wm_surface_state.c \
gen8_blend_state.c \
gen8_depth_state.c \
gen8_draw_upload.c \
-   gen8_ds_state.c \
-   gen8_gs_state.c \
-   gen8_hs_state.c \
gen8_multisample_state.c \
gen8_surface_state.c \
-   gen8_viewport_state.c \
hsw_queryobj.c \
hsw_sol.c \
intel_batchbuffer.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 72d63f6..b6e8abc 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -109,9 +109,7 @@ extern const struct brw_tracked_state brw_cs_state;
 extern const struct brw_tracked_state gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
 extern const struct brw_tracked_state gen6_blend_state;
-extern const struct brw_tracked_state gen6_sf_and_clip_viewports;
 extern const struct brw_tracked_state gen6_color_calc_state;
-extern const struct brw_tracked_state gen6_gs_state;
 extern const struct brw_tracked_state gen6_gs_push_constants;
 extern const struct brw_tracked_state gen6_gs_binding_table;
 extern const struct brw_tracked_state gen6_multisample_state;
@@ -125,26 +123,18 @@ extern const struct brw_tracked_state gen6_viewport_state;
 extern const struct brw_tracked_state gen6_vs_push_constants;
 extern const struct brw_tracked_state gen6_wm_push_constants;
 extern const struct brw_tracked_state gen7_depthbuffer;
-extern const struct brw_tracked_state gen7_ds_state;
-extern const struct brw_tracked_state gen7_gs_state;
 extern const struct brw_tracked_state gen7_tcs_push_constants;
-extern const struct brw_tracked_state gen7_hs_state;
 extern const struct brw_tracked_state gen7_l3_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
-extern const struct brw_tracked_state gen7_sf_clip_viewport;
 extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_blend_state;
-extern const struct brw_tracked_state gen8_ds_state;
-extern const struct brw_tracked_state gen8_gs_state;
-extern const struct brw_tracked_state gen8_hs_state;
 extern const struct brw_tracked_state gen8_index_buffer;
 extern const struct brw_tracked_state gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_ps_blend;
-extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
 extern const struct brw_tracked_state brw_cs_work_groups_surface;
@@ -383,12 +373,6 @@ use_state_point_size(const struct brw_context *brw)
   (brw->vue_map_geom_out.slots_valid & VARYING_BIT_PSIZ) == 0;
 }
 
-void brw_calculate_guardband_size(const struct gen_device_info *devinfo,

[Mesa-dev] [PATCH v02 33/37] i965: Port push constant code to genxml.

[Rafael Antognolli]

The following states are ported on this patch:
   - gen6_gs_push_constants
   - gen6_vs_push_constants
   - gen6_wm_push_constants
   - gen7_tes_push_constants

v2:
   - Use helper to setup brw_address (Kristian)

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/Makefile.sources|   4 +-
 src/mesa/drivers/dri/i965/brw_state.h |   5 +-
 src/mesa/drivers/dri/i965/gen6_gs_state.c |  33 +---
 src/mesa/drivers/dri/i965/gen6_vs_state.c |  70 +--
 src/mesa/drivers/dri/i965/gen6_wm_state.c |  70 +--
 src/mesa/drivers/dri/i965/gen7_ds_state.c |  57 +-
 src/mesa/drivers/dri/i965/gen7_hs_state.c |  60 +-
 src/mesa/drivers/dri/i965/genX_state_upload.c | 229 +--
 8 files changed, 216 insertions(+), 312 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_vs_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_wm_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_ds_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_hs_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 0123913..b52b08b 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -88,11 +88,7 @@ i965_FILES = \
gen6_sol.c \
gen6_urb.c \
gen6_viewport_state.c \
-   gen6_vs_state.c \
-   gen6_wm_state.c \
gen7_cs_state.c \
-   gen7_ds_state.c \
-   gen7_hs_state.c \
gen7_l3_state.c \
gen7_misc_state.c \
gen7_sol_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 6adcf46..084f97f 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -109,7 +109,6 @@ extern const struct brw_tracked_state brw_cs_state;
 extern const struct brw_tracked_state gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
 extern const struct brw_tracked_state gen6_color_calc_state;
-extern const struct brw_tracked_state gen6_gs_push_constants;
 extern const struct brw_tracked_state gen6_gs_binding_table;
 extern const struct brw_tracked_state gen6_multisample_state;
 extern const struct brw_tracked_state gen6_renderbuffer_surfaces;
@@ -118,13 +117,9 @@ extern const struct brw_tracked_state gen6_sol_surface;
 extern const struct brw_tracked_state gen6_sf_vp;
 extern const struct brw_tracked_state gen6_urb;
 extern const struct brw_tracked_state gen6_viewport_state;
-extern const struct brw_tracked_state gen6_vs_push_constants;
-extern const struct brw_tracked_state gen6_wm_push_constants;
 extern const struct brw_tracked_state gen7_depthbuffer;
-extern const struct brw_tracked_state gen7_tcs_push_constants;
 extern const struct brw_tracked_state gen7_l3_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
-extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_index_buffer;
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c 
b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index 6a9e951..6450c76 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -31,39 +31,6 @@
 #include "intel_batchbuffer.h"
 #include "main/shaderapi.h"
 
-static void
-gen6_upload_gs_push_constants(struct brw_context *brw)
-{
-   struct brw_stage_state *stage_state = >gs.base;
-
-   /* BRW_NEW_GEOMETRY_PROGRAM */
-   const struct brw_program *gp = brw_program_const(brw->geometry_program);
-
-   if (gp) {
-  /* BRW_NEW_GS_PROG_DATA */
-  struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
-
-  _mesa_shader_write_subroutine_indices(>ctx, MESA_SHADER_GEOMETRY);
-  gen6_upload_push_constants(brw, >program, prog_data, stage_state);
-   }
-
-   if (brw->gen >= 7)
-  gen7_upload_constant_state(brw, stage_state, gp, _3DSTATE_CONSTANT_GS);
-}
-
-const struct brw_tracked_state gen6_gs_push_constants = {
-   .dirty = {
-  .mesa  = _NEW_PROGRAM_CONSTANTS |
-   _NEW_TRANSFORM,
-  .brw   = BRW_NEW_BATCH |
-   BRW_NEW_BLORP |
-   BRW_NEW_GEOMETRY_PROGRAM |
-   BRW_NEW_GS_PROG_DATA |
-   BRW_NEW_PUSH_CONSTANT_ALLOCATION,
-   },
-   .emit = gen6_upload_gs_push_constants,
-};
-
 void
 upload_gs_state_for_tf(struct brw_context *brw)
 {
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c 
b/src/mesa/drivers/dri/i965/gen6_vs_state.c
deleted file mode 100644
index b2d2306..000
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),

[Mesa-dev] [PATCH v02 16/37] i965: Get real per-gen atom lists

[Rafael Antognolli]

From: Kenneth Graunke 

Make atoms initalization compile conditionally based on the target
platform.
---
 src/mesa/drivers/dri/i965/brw_state.h |  12 +-
 src/mesa/drivers/dri/i965/brw_state_upload.c  | 385 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 340 +-
 3 files changed, 369 insertions(+), 368 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index ec79a4e..008326a 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -441,6 +441,18 @@ void brw_calculate_guardband_size(const struct 
gen_device_info *devinfo,
   float *xmin, float *xmax,
   float *ymin, float *ymax);
 
+void brw_copy_pipeline_atoms(struct brw_context *brw,
+ enum brw_pipeline pipeline,
+ const struct brw_tracked_state **atoms,
+ int num_atoms);
+void gen4_init_atoms(struct brw_context *brw);
+void gen5_init_atoms(struct brw_context *brw);
+void gen6_init_atoms(struct brw_context *brw);
+void gen7_init_atoms(struct brw_context *brw);
+void gen75_init_atoms(struct brw_context *brw);
+void gen8_init_atoms(struct brw_context *brw);
+void gen9_init_atoms(struct brw_context *brw);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 9c0b82c..6c9c748 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -45,341 +45,6 @@
 #include "brw_cs.h"
 #include "main/framebuffer.h"
 
-static const struct brw_tracked_state *gen4_atoms[] =
-{
-   /* Once all the programs are done, we know how large urb entry
-* sizes need to be and can decide if we need to change the urb
-* layout.
-*/
-   _curbe_offsets,
-   _recalculate_urb_fence,
-
-   _cc_vp,
-   _cc_unit,
-
-   /* Surface state setup.  Must come before the VS/WM unit.  The binding
-* table upload must be last.
-*/
-   _vs_pull_constants,
-   _wm_pull_constants,
-   _renderbuffer_surfaces,
-   _renderbuffer_read_surfaces,
-   _texture_surfaces,
-   _vs_binding_table,
-   _wm_binding_table,
-
-   _fs_samplers,
-   _vs_samplers,
-
-   /* These set up state for brw_psp_urb_cbs */
-   _wm_unit,
-   _sf_vp,
-   _sf_unit,
-   _vs_unit,   /* always required, enabled or not */
-   _clip_unit,
-   _gs_unit,
-
-   /* Command packets:
-*/
-   _invariant_state,
-
-   _binding_table_pointers,
-   _blend_constant_color,
-
-   _depthbuffer,
-
-   _polygon_stipple,
-   _polygon_stipple_offset,
-
-   _line_stipple,
-
-   _psp_urb_cbs,
-
-   _drawing_rect,
-   _indices, /* must come before brw_vertices */
-   _index_buffer,
-   _vertices,
-
-   _constant_buffer
-};
-
-static const struct brw_tracked_state *gen6_atoms[] =
-{
-   _sf_and_clip_viewports,
-
-   /* Command packets: */
-
-   _cc_vp,
-   _viewport_state,   /* must do after *_vp stages */
-
-   _urb,
-   _blend_state,  /* must do before cc unit */
-   _color_calc_state, /* must do before cc unit */
-   _depth_stencil_state,  /* must do before cc unit */
-
-   _vs_push_constants, /* Before vs_state */
-   _gs_push_constants, /* Before gs_state */
-   _wm_push_constants, /* Before wm_state */
-
-   /* Surface state setup.  Must come before the VS/WM unit.  The binding
-* table upload must be last.
-*/
-   _vs_pull_constants,
-   _vs_ubo_surfaces,
-   _gs_pull_constants,
-   _gs_ubo_surfaces,
-   _wm_pull_constants,
-   _wm_ubo_surfaces,
-   _renderbuffer_surfaces,
-   _renderbuffer_read_surfaces,
-   _texture_surfaces,
-   _sol_surface,
-   _vs_binding_table,
-   _gs_binding_table,
-   _wm_binding_table,
-
-   _fs_samplers,
-   _vs_samplers,
-   _gs_samplers,
-   _sampler_state,
-   _multisample_state,
-
-   _vs_state,
-   _gs_state,
-   _clip_state,
-   _sf_state,
-   _wm_state,
-
-   _scissor_state,
-
-   _binding_table_pointers,
-
-   _depthbuffer,
-
-   _polygon_stipple,
-   _polygon_stipple_offset,
-
-   _line_stipple,
-
-   _drawing_rect,
-
-   _indices, /* must come before brw_vertices */
-   _index_buffer,
-   _vertices,
-};
-
-static const struct brw_tracked_state *gen7_render_atoms[] =
-{
-   /* Command packets: */
-
-   _cc_vp,
-   _sf_clip_viewport,
-
-   _l3_state,
-   _push_constant_space,
-   _urb,
-   _blend_state,  /* must do before cc unit */
-   _color_calc_state, /* must do before cc unit */
-   _depth_stencil_state,  /* must do before cc unit */
-
-   _vs_image_surfaces, /* Before vs push/pull constants and binding table 
*/
-   _tcs_image_surfaces, /* Before tcs push/pull constants and binding 
table */
-   _tes_image_surfaces, /* Before tes push/pull constants and binding 
table */
-   _gs_image_surfaces, /* Before gs push/pull constants and binding table 
*/
-   _wm_image_surfaces, /* Before wm push/pull 

[Mesa-dev] [PATCH v02 08/37] genxml: 3DSTATE_VS rename Function Enable to Enable.

[Rafael Antognolli]

Signed-off-by: Rafael Antognolli 
---
 src/intel/blorp/blorp_genX_exec.h | 2 +-
 src/intel/genxml/gen6.xml | 2 +-
 src/intel/genxml/gen7.xml | 2 +-
 src/intel/genxml/gen75.xml| 2 +-
 src/intel/genxml/gen8.xml | 2 +-
 src/intel/genxml/gen9.xml | 2 +-
 src/intel/vulkan/genX_pipeline.c  | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index 0bde2d2..bc829d0 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -432,7 +432,7 @@ blorp_emit_vs_config(struct blorp_batch *batch,
 
blorp_emit(batch, GENX(3DSTATE_VS), vs) {
   if (vs_prog_data) {
- vs.FunctionEnable = true;
+ vs.Enable = true;
 
  vs.KernelStartPointer = params->vs_prog_kernel;
 
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 14d643c..a12e22c 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1391,7 +1391,7 @@
 
 
 
-
+
   
 
   
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index a351486..6af1cbe 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1863,7 +1863,7 @@
 
 
 
-
+
   
 
   
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 9f0486c..793f733 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2191,7 +2191,7 @@
 
 
 
-
+
   
 
   
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 2908082..a6c6d9d 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -2352,7 +2352,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 09b9464..45eb454 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2585,7 +2585,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 2631ed0..74d6f9a 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1132,7 +1132,7 @@ emit_3dstate_vs(struct anv_pipeline *pipeline)
assert(anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX));
 
anv_batch_emit(>batch, GENX(3DSTATE_VS), vs) {
-  vs.FunctionEnable   = true;
+  vs.Enable   = true;
   vs.StatisticsEnable = true;
   vs.KernelStartPointer   = vs_bin->kernel.offset;
 #if GEN_GEN >= 8
-- 
git-series 0.9.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v02 12/37] genxml: Normalize xml for 3DSTATE_CC_STATE_POINTERS.

[Rafael Antognolli]

- "COLOR_CALC_STATE Change" -> "Color Calc State Pointer Valid"
   - "Pointer to COLOR_CALC_STATE" -> "Color Calc State Pointer"
   - "BackFace" -> "Backface"

Signed-off-by: Rafael Antognolli 
---
 src/intel/blorp/blorp_genX_exec.h  | 4 ++--
 src/intel/genxml/gen6.xml  | 4 ++--
 src/intel/genxml/gen8.xml  | 2 +-
 src/intel/vulkan/gen8_cmd_buffer.c | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index be22be0..9e61f69 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1365,10 +1365,10 @@ blorp_exec(struct blorp_batch *batch, const struct 
blorp_params *params)
 */
blorp_emit(batch, GENX(3DSTATE_CC_STATE_POINTERS), cc) {
   cc.BLEND_STATEChange = true;
-  cc.COLOR_CALC_STATEChange = true;
+  cc.ColorCalcStatePointerValid = true;
   cc.DEPTH_STENCIL_STATEChange = true;
   cc.PointertoBLEND_STATE = blend_state_offset;
-  cc.PointertoCOLOR_CALC_STATE = color_calc_state_offset;
+  cc.ColorCalcStatePointer = color_calc_state_offset;
   cc.PointertoDEPTH_STENCIL_STATE = depth_stencil_state_offset;
}
 #else
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index a8ce7e0..cdcead3 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -773,8 +773,8 @@
 
 
 
-
-
+
+
   
 
   
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index f49c4a3..21db782 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -568,7 +568,7 @@
 
   
 
-
+
 
 
   
diff --git a/src/intel/vulkan/gen8_cmd_buffer.c 
b/src/intel/vulkan/gen8_cmd_buffer.c
index c891a76..0e26dda 100644
--- a/src/intel/vulkan/gen8_cmd_buffer.c
+++ b/src/intel/vulkan/gen8_cmd_buffer.c
@@ -467,7 +467,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer 
*cmd_buffer)
  .BlendConstantColorBlue = 
cmd_buffer->state.dynamic.blend_constants[2],
  .BlendConstantColorAlpha = 
cmd_buffer->state.dynamic.blend_constants[3],
  .StencilReferenceValue = d->stencil_reference.front & 0xff,
- .BackFaceStencilReferenceValue = d->stencil_reference.back & 0xff,
+ .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
   };
   GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, );
 
-- 
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[Mesa-dev] [PATCH v02 10/37] genxml: Rename "Function Enable" to "Enable".

[Rafael Antognolli]

Rename that field name on genxml for:
   - 3DSTATE_GS - gen6+
   - 3DSTATE_DS - gen7+
   - 3DSTATE_HS - gen7+

Signed-off-by: Rafael Antognolli 
---
 src/intel/genxml/gen6.xml| 2 +-
 src/intel/genxml/gen7.xml| 6 +++---
 src/intel/genxml/gen75.xml   | 6 +++---
 src/intel/genxml/gen8.xml| 6 +++---
 src/intel/genxml/gen9.xml| 6 +++---
 src/intel/vulkan/genX_pipeline.c | 6 +++---
 6 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 2173dbf..2cb9419 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1014,7 +1014,7 @@
 
 
 
-
+
   
 
   
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 6af1cbe..b4407d4 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1101,7 +1101,7 @@
 
 
 
-
+
   
 
   
@@ -1162,7 +1162,7 @@
   
 
 
-
+
 
   
 
@@ -1199,7 +1199,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 793f733..8c8b776 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -1292,7 +1292,7 @@
 
 
 
-
+
   
 
   
@@ -1440,7 +1440,7 @@
   
 
 
-
+
 
   
   
@@ -1484,7 +1484,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index a6c6d9d..f49c4a3 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -1350,7 +1350,7 @@
 
 
 
-
+
 
 
 
@@ -1506,7 +1506,7 @@
   
 
 
-
+
 
   
   
@@ -1555,7 +1555,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 45eb454..178cf73 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -1412,7 +1412,7 @@
 
 
 
-
+
 
 
 
@@ -1611,7 +1611,7 @@
   
 
 
-
+
 
   
   
@@ -1661,7 +1661,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 74d6f9a..2b38c34 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1192,7 +1192,7 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline)
const struct brw_tes_prog_data *tes_prog_data = get_tes_prog_data(pipeline);
 
anv_batch_emit(>batch, GENX(3DSTATE_HS), hs) {
-  hs.FunctionEnable = true;
+  hs.Enable = true;
   hs.StatisticsEnable = true;
   hs.KernelStartPointer = tcs_bin->kernel.offset;
 
@@ -1222,7 +1222,7 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline)
}
 
anv_batch_emit(>batch, GENX(3DSTATE_DS), ds) {
-  ds.FunctionEnable = true;
+  ds.Enable = true;
   ds.StatisticsEnable = true;
   ds.KernelStartPointer = tes_bin->kernel.offset;
 
@@ -1275,7 +1275,7 @@ emit_3dstate_gs(struct anv_pipeline *pipeline)
const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
 
anv_batch_emit(>batch, GENX(3DSTATE_GS), gs) {
-  gs.FunctionEnable  = true;
+  gs.Enable  = true;
   gs.StatisticsEnable= true;
   gs.KernelStartPointer  = gs_bin->kernel.offset;
   gs.DispatchMode= gs_prog_data->base.dispatch_mode;
-- 
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[Mesa-dev] [PATCH v02 09/37] genxml: Clip guardbands are float, not int.

[Rafael Antognolli]

This makes genxml create the right struct types, and generate the right
batch commands.

Signed-off-by: Rafael Antognolli 
Reviewed-by: Kenneth Graunke 
---
 src/intel/genxml/gen6.xml | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index a12e22c..2173dbf 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -394,10 +394,10 @@
   
 
   
-
-
-
-
+
+
+
+
   
 
   
-- 
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[Mesa-dev] [PATCH v02 31/37] i965: Port gen7+ 3DSTATE_TE to genxml.

[Rafael Antognolli]

Emit 3DSTATE_TE on Gen7+ using brw_batch_emit helper.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/Makefile.sources|  1 +-
 src/mesa/drivers/dri/i965/brw_state.h |  1 +-
 src/mesa/drivers/dri/i965/gen7_te_state.c | 67 +
 src/mesa/drivers/dri/i965/genX_state_upload.c | 40 +++-
 4 files changed, 38 insertions(+), 71 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_te_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 0c67170..0123913 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -96,7 +96,6 @@ i965_FILES = \
gen7_l3_state.c \
gen7_misc_state.c \
gen7_sol_state.c \
-   gen7_te_state.c \
gen7_urb.c \
gen7_wm_surface_state.c \
gen8_depth_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index cf043a0..322d767 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -125,7 +125,6 @@ extern const struct brw_tracked_state gen7_depthbuffer;
 extern const struct brw_tracked_state gen7_tcs_push_constants;
 extern const struct brw_tracked_state gen7_l3_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
-extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state haswell_cut_index;
diff --git a/src/mesa/drivers/dri/i965/gen7_te_state.c 
b/src/mesa/drivers/dri/i965/gen7_te_state.c
deleted file mode 100644
index e56fdcf..000
--- a/src/mesa/drivers/dri/i965/gen7_te_state.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright © 2014 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "intel_batchbuffer.h"
-
-static void
-upload_te_state(struct brw_context *brw)
-{
-   /* BRW_NEW_TESS_PROGRAMS */
-   bool active = brw->tess_eval_program;
-
-   const struct brw_tes_prog_data *tes_prog_data =
-  brw_tes_prog_data(brw->tes.base.prog_data);
-
-   if (active) {
-  BEGIN_BATCH(4);
-  OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
-  OUT_BATCH((tes_prog_data->partitioning << GEN7_TE_PARTITIONING_SHIFT) |
-(tes_prog_data->output_topology << 
GEN7_TE_OUTPUT_TOPOLOGY_SHIFT) |
-(tes_prog_data->domain << GEN7_TE_DOMAIN_SHIFT) |
-GEN7_TE_ENABLE);
-  OUT_BATCH_F(63.0);
-  OUT_BATCH_F(64.0);
-  ADVANCE_BATCH();
-   } else {
-  BEGIN_BATCH(4);
-  OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
-  OUT_BATCH(0);
-  OUT_BATCH_F(0);
-  OUT_BATCH_F(0);
-  ADVANCE_BATCH();
-   }
-}
-
-const struct brw_tracked_state gen7_te_state = {
-   .dirty = {
-  .mesa  = 0,
-  .brw   = BRW_NEW_BLORP |
-   BRW_NEW_CONTEXT |
-   BRW_NEW_TES_PROG_DATA |
-   BRW_NEW_TESS_PROGRAMS,
-   },
-   .emit = upload_te_state,
-};
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 1bdcea5..45b02a6 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -2315,6 +2315,42 @@ static const struct brw_tracked_state genX(ds_state) = {
.emit = genX(upload_ds_state),
 };
 
+/* -- */
+
+static void
+upload_te_state(struct brw_context *brw)
+{
+   /* BRW_NEW_TESS_PROGRAMS */
+   bool active = brw->tess_eval_program;
+
+   const struct brw_tes_prog_data *tes_prog_data =
+  brw_tes_prog_data(brw->tes.base.prog_data);
+
+   if (active) {
+  

[Mesa-dev] [PATCH v02 35/37] i965: Port gen6+ multisample state emitting code to genxml.

[Rafael Antognolli]

Emit 3DSTATE_MULTISAMPLE using brw_batch_emit.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/brw_context.h|   9 +-
 src/mesa/drivers/dri/i965/brw_state.h  |   2 +-
 src/mesa/drivers/dri/i965/gen6_multisample_state.c |   6 +-
 src/mesa/drivers/dri/i965/gen8_multisample_state.c |  18 +--
 src/mesa/drivers/dri/i965/genX_state_upload.c  | 102 +-
 5 files changed, 101 insertions(+), 36 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 8bd8863..cef54b8 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1532,15 +1532,6 @@ brw_blorp_copytexsubimage(struct brw_context *brw,
   int dstX0, int dstY0,
   int width, int height);
 
-/* gen6_multisample_state.c */
-unsigned
-gen6_determine_sample_mask(struct brw_context *brw);
-
-void
-gen6_emit_3dstate_multisample(struct brw_context *brw,
-  unsigned num_samples);
-void
-gen6_emit_3dstate_sample_mask(struct brw_context *brw, unsigned mask);
 void
 gen6_get_sample_position(struct gl_context *ctx,
  struct gl_framebuffer *fb,
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index acb7334..2b5b1c4 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -109,7 +109,6 @@ extern const struct brw_tracked_state 
gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
 extern const struct brw_tracked_state gen6_color_calc_state;
 extern const struct brw_tracked_state gen6_gs_binding_table;
-extern const struct brw_tracked_state gen6_multisample_state;
 extern const struct brw_tracked_state gen6_renderbuffer_surfaces;
 extern const struct brw_tracked_state gen6_sampler_state;
 extern const struct brw_tracked_state gen6_sol_surface;
@@ -122,7 +121,6 @@ extern const struct brw_tracked_state 
gen7_push_constant_space;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_index_buffer;
-extern const struct brw_tracked_state gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_vf_topology;
 extern const struct brw_tracked_state brw_cs_work_groups_surface;
diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c 
b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
index a59ffec..77c5fd6 100644
--- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
@@ -122,7 +122,7 @@ gen6_set_sample_maps(struct gl_context *ctx)
 /**
  * 3DSTATE_MULTISAMPLE
  */
-void
+static void
 gen6_emit_3dstate_multisample(struct brw_context *brw,
   unsigned num_samples)
 {
@@ -160,7 +160,7 @@ gen6_emit_3dstate_multisample(struct brw_context *brw,
ADVANCE_BATCH();
 }
 
-unsigned
+static unsigned
 gen6_determine_sample_mask(struct brw_context *brw)
 {
struct gl_context *ctx = >ctx;
@@ -195,7 +195,7 @@ gen6_determine_sample_mask(struct brw_context *brw)
 /**
  * 3DSTATE_SAMPLE_MASK
  */
-void
+static void
 gen6_emit_3dstate_sample_mask(struct brw_context *brw, unsigned mask)
 {
BEGIN_BATCH(2);
diff --git a/src/mesa/drivers/dri/i965/gen8_multisample_state.c 
b/src/mesa/drivers/dri/i965/gen8_multisample_state.c
index e36d037..7a31a5d 100644
--- a/src/mesa/drivers/dri/i965/gen8_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_multisample_state.c
@@ -69,21 +69,3 @@ gen8_emit_3dstate_sample_pattern(struct brw_context *brw)
OUT_BATCH(brw_multisample_positions_1x_2x);
ADVANCE_BATCH();
 }
-
-
-static void
-upload_multisample_state(struct brw_context *brw)
-{
-   gen8_emit_3dstate_multisample(brw, brw->num_samples);
-   gen6_emit_3dstate_sample_mask(brw, gen6_determine_sample_mask(brw));
-}
-
-const struct brw_tracked_state gen8_multisample_state = {
-   .dirty = {
-  .mesa = _NEW_MULTISAMPLE,
-  .brw = BRW_NEW_BLORP |
- BRW_NEW_CONTEXT |
- BRW_NEW_NUM_SAMPLES,
-   },
-   .emit = upload_multisample_state
-};
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index b7475dc..77c9efc 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -24,6 +24,7 @@
 #include 
 
 #include "common/gen_device_info.h"
+#include "common/gen_sample_positions.h"
 #include "genxml/gen_macros.h"
 
 #include "main/bufferobj.h"
@@ -36,6 +37,7 @@
 #include "brw_defines.h"
 #endif
 #include "brw_draw.h"
+#include "brw_multisample_state.h"
 #include "brw_state.h"
 #include "brw_wm.h"
 #include "brw_util.h"
@@ -3105,6 +3107,98 @@ static const struct brw_tracked_state 
genX(wm_push_constants) = {
.emit = 

[Mesa-dev] [PATCH v02 07/37] genxml: Make "Reorder Mode" fields consistent.

[Rafael Antognolli]

From: Kenneth Graunke 

Both GS and SOL have these fields.  Some were ReorderEnable = true,
some were ReorderMode = REORDER_TRAILING, and some were just TRAILING.

Signed-off-by: Kenneth Graunke 
---
 src/intel/genxml/gen6.xml| 5 -
 src/intel/genxml/gen7.xml| 5 -
 src/intel/vulkan/genX_pipeline.c | 4 
 3 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 8ead41f..14d643c 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1006,7 +1006,10 @@
 
 
 
-
+
+  
+  
+
 
 
 
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 440258a..a351486 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1157,7 +1157,10 @@
 
 
 
-
+
+  
+  
+
 
 
 
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index b00707f..2631ed0 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1300,11 +1300,7 @@ emit_3dstate_gs(struct anv_pipeline *pipeline)
   gs.ControlDataFormat   = gs_prog_data->control_data_format;
   gs.ControlDataHeaderSize   = 
gs_prog_data->control_data_header_size_hwords;
   gs.InstanceControl = MAX2(gs_prog_data->invocations, 1) - 1;
-#if GEN_GEN >= 8 || GEN_IS_HASWELL
   gs.ReorderMode = TRAILING;
-#else
-  gs.ReorderEnable   = true;
-#endif
 
 #if GEN_GEN >= 8
   gs.ExpectedVertexCount = gs_prog_data->vertices_in;
-- 
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[Mesa-dev] [PATCH v02 23/37] i965: Remove calculate_attr_overrides.

[Rafael Antognolli]

This function now lives inside genX_state_upload.c.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/Makefile.sources |   1 +-
 src/mesa/drivers/dri/i965/brw_state.h  |   8 +-
 src/mesa/drivers/dri/i965/gen6_sf_state.c  | 265 +--
 3 files changed, 274 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_sf_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 81759ed..47680a7 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -85,7 +85,6 @@ i965_FILES = \
gen6_queryobj.c \
gen6_sampler_state.c \
gen6_scissor_state.c \
-   gen6_sf_state.c \
gen6_sol.c \
gen6_urb.c \
gen6_viewport_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index bc68c2c..3df975a 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -339,14 +339,6 @@ gen6_upload_wm_state(struct brw_context *brw,
  bool line_stipple_enable, bool polygon_stipple_enable,
  bool statistic_enable);
 
-/* gen6_sf_state.c */
-void
-calculate_attr_overrides(const struct brw_context *brw,
- uint16_t *attr_overrides,
- uint32_t *point_sprite_enables,
- uint32_t *urb_entry_read_length,
- uint32_t *urb_entry_read_offset);
-
 /* gen6_surface_state.c */
 void gen6_init_vtable_surface_functions(struct brw_context *brw);
 
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c 
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
deleted file mode 100644
index 45b5769..000
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *Eric Anholt 
- *
- */
-
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "brw_util.h"
-#include "compiler/nir/nir.h"
-#include "main/macros.h"
-#include "main/fbobject.h"
-#include "main/framebuffer.h"
-#include "intel_batchbuffer.h"
-
-/**
- * Determine the appropriate attribute override value to store into the
- * 3DSTATE_SF structure for a given fragment shader attribute.  The attribute
- * override value contains two pieces of information: the location of the
- * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
- * flag indicating whether to "swizzle" the attribute based on the direction
- * the triangle is facing.
- *
- * If an attribute is "swizzled", then the given VUE location is used for
- * front-facing triangles, and the VUE location that immediately follows is
- * used for back-facing triangles.  We use this to implement the mapping from
- * gl_FrontColor/gl_BackColor to gl_Color.
- *
- * urb_entry_read_offset is the offset into the VUE at which the SF unit is
- * being instructed to begin reading attribute data.  It can be set to a
- * nonzero value to prevent the SF unit from wasting time reading elements of
- * the VUE that are not needed by the fragment shader.  It is measured in
- * 256-bit increments.
- */
-static uint32_t
-get_attr_override(const struct brw_vue_map *vue_map, int urb_entry_read_offset,
-  int fs_attr, bool two_side_color, uint32_t *max_source_attr)
-{
-   /* Find the VUE slot for this attribute. */
-   int slot = vue_map->varying_to_slot[fs_attr];
-
-   /* Viewport and Layer are stored in the VUE header.  We need to override
-* them to zero if earlier stages didn't write them, as GL requires that
-* they read back as zero when not explicitly set.
-*/
-   if (fs_attr == VARYING_SLOT_VIEWPORT || fs_attr == VARYING_SLOT_LAYER) {
-  

[Mesa-dev] [PATCH v02 24/37] i965: Port gen7+ 3DSTATE_SOL to genxml.

[Rafael Antognolli]

Emit 3DSTATE_SOL on Gen7+ using brw_batch_emit helper, that uses pack
structs from genxml.

v2:
   - Add helpers to assign struct brw_address (Kristian)

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/Makefile.sources|   1 +-
 src/mesa/drivers/dri/i965/brw_state.h |   6 +-
 src/mesa/drivers/dri/i965/gen7_sol_state.c| 307 +
 src/mesa/drivers/dri/i965/gen8_sol_state.c|  95 +-
 src/mesa/drivers/dri/i965/genX_state_upload.c | 358 ++-
 5 files changed, 355 insertions(+), 412 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_sol_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 47680a7..bfcf57c 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -111,7 +111,6 @@ i965_FILES = \
gen8_hs_state.c \
gen8_multisample_state.c \
gen8_ps_state.c \
-   gen8_sol_state.c \
gen8_surface_state.c \
gen8_viewport_state.c \
gen8_vs_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 3df975a..94f758b 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -135,7 +135,6 @@ extern const struct brw_tracked_state gen7_l3_state;
 extern const struct brw_tracked_state gen7_ps_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
 extern const struct brw_tracked_state gen7_sf_clip_viewport;
-extern const struct brw_tracked_state gen7_sol_state;
 extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
@@ -299,11 +298,6 @@ void gen8_upload_ps_state(struct brw_context *brw,
 void gen8_upload_ps_extra(struct brw_context *brw,
   const struct brw_wm_prog_data *prog_data);
 
-/* gen7_sol_state.c */
-void gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
-  const struct brw_vue_map *vue_map);
-void gen8_upload_3dstate_so_buffers(struct brw_context *brw);
-
 /* gen8_surface_state.c */
 
 void gen8_init_vtable_surface_functions(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c 
b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index f1bd19c..f54b370 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -35,313 +35,6 @@
 #include "intel_buffer_objects.h"
 #include "main/transformfeedback.h"
 
-static void
-upload_3dstate_so_buffers(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   /* BRW_NEW_TRANSFORM_FEEDBACK */
-   struct gl_transform_feedback_object *xfb_obj =
-  ctx->TransformFeedback.CurrentObject;
-   const struct gl_transform_feedback_info *linked_xfb_info =
-  xfb_obj->program->sh.LinkedTransformFeedback;
-   int i;
-
-   /* Set up the up to 4 output buffers.  These are the ranges defined in the
-* gl_transform_feedback_object.
-*/
-   for (i = 0; i < 4; i++) {
-  struct intel_buffer_object *bufferobj =
-intel_buffer_object(xfb_obj->Buffers[i]);
-  struct brw_bo *bo;
-  uint32_t start, end;
-  uint32_t stride;
-
-  if (!xfb_obj->Buffers[i]) {
-/* The pitch of 0 in this command indicates that the buffer is
- * unbound and won't be written to.
- */
-BEGIN_BATCH(4);
-OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (4 - 2));
-OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT));
-OUT_BATCH(0);
-OUT_BATCH(0);
-ADVANCE_BATCH();
-
-continue;
-  }
-
-  stride = linked_xfb_info->Buffers[i].Stride * 4;
-
-  start = xfb_obj->Offset[i];
-  assert(start % 4 == 0);
-  end = ALIGN(start + xfb_obj->Size[i], 4);
-  bo = intel_bufferobj_buffer(brw, bufferobj, start, end - start);
-  assert(end <= bo->size);
-
-  BEGIN_BATCH(4);
-  OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (4 - 2));
-  OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT) | stride);
-  OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, start);
-  OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, end);
-  ADVANCE_BATCH();
-   }
-}
-
-/**
- * Outputs the 3DSTATE_SO_DECL_LIST command.
- *
- * The data output is a series of 64-bit entries containing a SO_DECL per
- * stream.  We only have one stream of rendering coming out of the GS unit, so
- * we only emit stream 0 (low 16 bits) SO_DECLs.
- */
-void
-gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
- const struct brw_vue_map *vue_map)
-{
-   struct gl_context *ctx = >ctx;
-   /* BRW_NEW_TRANSFORM_FEEDBACK */
-   struct gl_transform_feedback_object *xfb_obj =
-  ctx->TransformFeedback.CurrentObject;
-   const struct gl_transform_feedback_info *linked_xfb_info =
-  

Re: [Mesa-dev] [PATCH 20/35] genxml: Make "Reorder Mode" fields consistent.

[Rafael Antognolli]

On Mon, Apr 24, 2017 at 03:03:56PM -0700, Kenneth Graunke wrote:
> On Wednesday, April 19, 2017 4:56:13 PM PDT Rafael Antognolli wrote:
> > From: Kenneth Graunke 
> > 
> > Both GS and SOL have these fields.  Some were ReorderEnable = true,
> > some were ReorderMode = REORDER_TRAILING, and some were just TRAILING.
> > 
> > Signed-off-by: Kenneth Graunke 
> > ---
> >  src/intel/genxml/gen6.xml| 5 -
> >  src/intel/genxml/gen7.xml| 5 -
> >  src/intel/vulkan/genX_pipeline.c | 4 
> >  3 files changed, 8 insertions(+), 6 deletions(-)
> 
> I'm a little conflicted about this...I had forgotten that the Gen6-7 GS
> doesn't actually do proper "trailing" reordering.  It just...reorders
> them...differently.  So "Reorder Enable" feels kind of appropriate.
> 
> That said, it feels stupid to have ifdefs to set the same exact bit,
> and we call it REORDER_TRAILING in the existing gen7_gs_state.c code.
> We just have a comment pointing out that it's kinda broken.
> 
> So, I suppose it's fine.  I can't really give an R-b for my own patch
> though :)

Heh, you have mine at least:

Reviewed-by: Rafael Antognolli 
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Re: [Mesa-dev] [PATCH 20/35] genxml: Make "Reorder Mode" fields consistent.

[Kenneth Graunke]

On Wednesday, April 19, 2017 4:56:13 PM PDT Rafael Antognolli wrote:
> From: Kenneth Graunke 
> 
> Both GS and SOL have these fields.  Some were ReorderEnable = true,
> some were ReorderMode = REORDER_TRAILING, and some were just TRAILING.
> 
> Signed-off-by: Kenneth Graunke 
> ---
>  src/intel/genxml/gen6.xml| 5 -
>  src/intel/genxml/gen7.xml| 5 -
>  src/intel/vulkan/genX_pipeline.c | 4 
>  3 files changed, 8 insertions(+), 6 deletions(-)

I'm a little conflicted about this...I had forgotten that the Gen6-7 GS
doesn't actually do proper "trailing" reordering.  It just...reorders
them...differently.  So "Reorder Enable" feels kind of appropriate.

That said, it feels stupid to have ifdefs to set the same exact bit,
and we call it REORDER_TRAILING in the existing gen7_gs_state.c code.
We just have a comment pointing out that it's kinda broken.

So, I suppose it's fine.  I can't really give an R-b for my own patch
though :)


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[Mesa-dev] [PATCH 1/4] vc4: Only build the NEON code on arm32.

[Eric Anholt]

NEON is sufficiently different on arm64 that we can't just reuse this
code.  Disable it on arm64 for now.

v2: Use PIPE_ARCH_ARM instead, as __ARM_ARCH may be 8 for a 32-bit build
for a v8 CPU.

Signed-off-by: Eric Anholt 
Cc: 
---
 src/gallium/drivers/vc4/vc4_tiling_lt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/vc4/vc4_tiling_lt.c 
b/src/gallium/drivers/vc4/vc4_tiling_lt.c
index c9cbc65e2dbc..f37a92e9390e 100644
--- a/src/gallium/drivers/vc4/vc4_tiling_lt.c
+++ b/src/gallium/drivers/vc4/vc4_tiling_lt.c
@@ -61,7 +61,7 @@ static void
 vc4_load_utile(void *cpu, void *gpu, uint32_t cpu_stride, uint32_t cpp)
 {
 uint32_t gpu_stride = vc4_utile_stride(cpp);
-#if defined(VC4_BUILD_NEON) && defined(__ARM_ARCH)
+#if defined(VC4_BUILD_NEON) && defined(PIPE_ARCH_ARM)
 if (gpu_stride == 8) {
 __asm__ volatile (
 /* Load from the GPU in one shot, no interleave, to
@@ -118,7 +118,7 @@ vc4_store_utile(void *gpu, void *cpu, uint32_t cpu_stride, 
uint32_t cpp)
 {
 uint32_t gpu_stride = vc4_utile_stride(cpp);
 
-#if defined(VC4_BUILD_NEON) && defined(__ARM_ARCH)
+#if defined(VC4_BUILD_NEON) && defined(PIPE_ARCH_ARM)
 if (gpu_stride == 8) {
 __asm__ volatile (
 /* Load each 8-byte line from cpu-side source,
-- 
2.11.0

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[Mesa-dev] [PATCH 4/4] vc4: Use runtime CPU detection for whether NEON is available.

[Eric Anholt]

This will allow Raspbian's ARMv6 builds to take advantage of the new NEON
code, and could prevent problems if vc4 ends up getting used on a v7 CPU
without NEON.

v2: Drop dead NEON_SUFFIX (noted by Erik Faye-Lund)
---
 src/gallium/drivers/vc4/vc4_screen.c |  3 +++
 src/gallium/drivers/vc4/vc4_tiling.h | 27 +--
 2 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/src/gallium/drivers/vc4/vc4_screen.c 
b/src/gallium/drivers/vc4/vc4_screen.c
index b5b1ced49fd5..ce6a9dbaa6cc 100644
--- a/src/gallium/drivers/vc4/vc4_screen.c
+++ b/src/gallium/drivers/vc4/vc4_screen.c
@@ -27,6 +27,7 @@
 #include "pipe/p_screen.h"
 #include "pipe/p_state.h"
 
+#include "util/u_cpu_detect.h"
 #include "util/u_debug.h"
 #include "util/u_memory.h"
 #include "util/u_format.h"
@@ -628,6 +629,8 @@ vc4_screen_create(int fd)
 if (!vc4_get_chip_info(screen))
 goto fail;
 
+util_cpu_detect();
+
 slab_create_parent(>transfer_pool, sizeof(struct 
vc4_transfer), 16);
 
 vc4_fence_init(screen);
diff --git a/src/gallium/drivers/vc4/vc4_tiling.h 
b/src/gallium/drivers/vc4/vc4_tiling.h
index ba1ad6fb3f7d..3168ec20a606 100644
--- a/src/gallium/drivers/vc4/vc4_tiling.h
+++ b/src/gallium/drivers/vc4/vc4_tiling.h
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include "util/macros.h"
+#include "util/u_cpu_detect.h"
 
 /** Return the width in pixels of a 64-byte microtile. */
 static inline uint32_t
@@ -83,23 +84,18 @@ void vc4_store_tiled_image(void *dst, uint32_t dst_stride,
uint8_t tiling_format, int cpp,
const struct pipe_box *box);
 
-/* If we're building for ARMv7 (Pi 2+), assume it has NEON.  For Raspbian we
- * should extend this to have some runtime detection of being built for ARMv6
- * on a Pi 2+.
- */
-#if defined(__ARM_ARCH) && __ARM_ARCH == 7
-#define NEON_SUFFIX(x) x ## _neon
-#else
-#define NEON_SUFFIX(x) x ## _base
-#endif
-
 static inline void
 vc4_load_lt_image(void *dst, uint32_t dst_stride,
   void *src, uint32_t src_stride,
   int cpp, const struct pipe_box *box)
 {
-NEON_SUFFIX(vc4_load_lt_image)(dst, dst_stride, src, src_stride,
+if (util_cpu_caps.has_neon) {
+vc4_load_lt_image_neon(dst, dst_stride, src, src_stride,
cpp, box);
+} else {
+vc4_load_lt_image_base(dst, dst_stride, src, src_stride,
+   cpp, box);
+}
 }
 
 static inline void
@@ -107,10 +103,13 @@ vc4_store_lt_image(void *dst, uint32_t dst_stride,
void *src, uint32_t src_stride,
int cpp, const struct pipe_box *box)
 {
-NEON_SUFFIX(vc4_store_lt_image)(dst, dst_stride, src, src_stride,
+if (util_cpu_caps.has_neon) {
+vc4_store_lt_image_neon(dst, dst_stride, src, src_stride,
 cpp, box);
+} else {
+vc4_store_lt_image_base(dst, dst_stride, src, src_stride,
+cpp, box);
+}
 }
 
-#undef NEON_SUFFIX
-
 #endif /* VC4_TILING_H */
-- 
2.11.0

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[Mesa-dev] [PATCH 3/4] vc4: Use a wrapper file to set VC4_BUILD_NEON instead of CFLAGS.

[Eric Anholt]

Android.mk was setting the flag across the entire driver, so we didn't
have non-NEON versions getting built.  This was going to be a problem with
the next commit, when I start auto-detecting NEON support and use the
non-NEON version when appropriate.
---

Rob: I'm happy to just drop this patch if you'd rather go the other
route for the Android build.  I do think this makes for a slightly
faster and simpler build, due to not having the intermediate lib.

 src/gallium/drivers/vc4/Android.mk   |  2 --
 src/gallium/drivers/vc4/Makefile.am  |  6 --
 src/gallium/drivers/vc4/Makefile.sources |  1 +
 src/gallium/drivers/vc4/vc4_tiling_lt_neon.c | 30 
 4 files changed, 31 insertions(+), 8 deletions(-)
 create mode 100644 src/gallium/drivers/vc4/vc4_tiling_lt_neon.c

diff --git a/src/gallium/drivers/vc4/Android.mk 
b/src/gallium/drivers/vc4/Android.mk
index fdc06744e5ab..de9d5e3f5b3c 100644
--- a/src/gallium/drivers/vc4/Android.mk
+++ b/src/gallium/drivers/vc4/Android.mk
@@ -25,8 +25,6 @@ include $(LOCAL_PATH)/Makefile.sources
 
 include $(CLEAR_VARS)
 
-LOCAL_CFLAGS_arm := -DVC4_BUILD_NEON
-
 LOCAL_SRC_FILES := \
$(C_SOURCES)
 
diff --git a/src/gallium/drivers/vc4/Makefile.am 
b/src/gallium/drivers/vc4/Makefile.am
index b361a0c588a8..0ed49b128b2d 100644
--- a/src/gallium/drivers/vc4/Makefile.am
+++ b/src/gallium/drivers/vc4/Makefile.am
@@ -41,10 +41,4 @@ libvc4_la_SOURCES = $(C_SOURCES)
 libvc4_la_LIBADD = $(SIM_LIB) $(VC4_LIBS)
 libvc4_la_LDFLAGS = $(SIM_LDFLAGS)
 
-noinst_LTLIBRARIES += libvc4_neon.la
-libvc4_la_LIBADD += libvc4_neon.la
-
-libvc4_neon_la_SOURCES = vc4_tiling_lt.c
-libvc4_neon_la_CFLAGS = $(AM_CFLAGS) -DVC4_BUILD_NEON
-
 EXTRA_DIST = kernel/README
diff --git a/src/gallium/drivers/vc4/Makefile.sources 
b/src/gallium/drivers/vc4/Makefile.sources
index 10de34361260..442d7a561782 100644
--- a/src/gallium/drivers/vc4/Makefile.sources
+++ b/src/gallium/drivers/vc4/Makefile.sources
@@ -56,6 +56,7 @@ C_SOURCES := \
vc4_state.c \
vc4_tiling.c \
vc4_tiling_lt.c \
+   vc4_tiling_lt_neon.c \
vc4_tiling.h \
vc4_uniforms.c \
$()
diff --git a/src/gallium/drivers/vc4/vc4_tiling_lt_neon.c 
b/src/gallium/drivers/vc4/vc4_tiling_lt_neon.c
new file mode 100644
index ..7ba66ae4cdf4
--- /dev/null
+++ b/src/gallium/drivers/vc4/vc4_tiling_lt_neon.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright © 2017 Broadcom
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+/* Wrapper file for building vc4_tiling_lt.c with the "build NEON assembly if
+ * possible" flag set, since Android.mk doesn't have a way to set CFLAGS for a
+ * single file.
+ */
+
+#define VC4_BUILD_NEON
+#include "vc4_tiling_lt.c"
-- 
2.11.0

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[Mesa-dev] [PATCH 2/4] gallium: Enable ARM NEON CPU detection.

[Eric Anholt]

I wrote this code with reference to pixman, though I've only decided to
cover Linux (what I'm testing) and Android (seems obvious enough).  Linux
has getauxval() as a cleaner interface to the /proc entry, but it's more
glibc-specific and I didn't want to add detection for that.

This will be used to enable NEON at runtime on ARMv6 builds of vc4.

v2: Actually initialize the temp vars in the Android path (noticed by
daniels)
v3: Actually pull in the cpufeatures library (change by robher).
Use O_CLOEXEC.  Break out of the loop when we find our feature.
v4: Drop VFP code, which was confused about what it was detecting and not
actually used yet.
---
 src/gallium/auxiliary/Android.mk  |  2 ++
 src/gallium/auxiliary/util/u_cpu_detect.c | 43 +++
 src/gallium/auxiliary/util/u_cpu_detect.h |  1 +
 3 files changed, 46 insertions(+)

diff --git a/src/gallium/auxiliary/Android.mk b/src/gallium/auxiliary/Android.mk
index e8628e43744a..4f6f71bbf6a9 100644
--- a/src/gallium/auxiliary/Android.mk
+++ b/src/gallium/auxiliary/Android.mk
@@ -48,6 +48,8 @@ endif
 LOCAL_MODULE := libmesa_gallium
 LOCAL_STATIC_LIBRARIES += libmesa_nir
 
+LOCAL_WHOLE_STATIC_LIBRARIES += cpufeatures
+
 # generate sources
 LOCAL_MODULE_CLASS := STATIC_LIBRARIES
 intermediates := $(call local-generated-sources-dir)
diff --git a/src/gallium/auxiliary/util/u_cpu_detect.c 
b/src/gallium/auxiliary/util/u_cpu_detect.c
index 845fc6b34d5c..76115bf8d55d 100644
--- a/src/gallium/auxiliary/util/u_cpu_detect.c
+++ b/src/gallium/auxiliary/util/u_cpu_detect.c
@@ -59,12 +59,18 @@
 
 #if defined(PIPE_OS_LINUX)
 #include 
+#include 
+#include 
 #endif
 
 #ifdef PIPE_OS_UNIX
 #include 
 #endif
 
+#if defined(PIPE_OS_ANDROID)
+#include 
+#endif
+
 #if defined(PIPE_OS_WINDOWS)
 #include 
 #if defined(PIPE_CC_MSVC)
@@ -294,6 +300,38 @@ PIPE_ALIGN_STACK static inline boolean sse2_has_daz(void)
 
 #endif /* X86 or X86_64 */
 
+#if defined(PIPE_ARCH_ARM)
+static void
+check_os_arm_support(void)
+{
+#if defined(PIPE_OS_ANDROID)
+   AndroidCpuFamily cpu_family = android_getCpuFamily();
+   uint64_t cpu_features = android_getCpuFeatures();
+
+   if (cpu_family == ANDROID_CPU_FAMILY_ARM) {
+  if (cpu_features & ANDROID_CPU_ARM_FEATURE_NEON)
+ util_cpu_caps.has_neon = 1;
+   }
+#elif defined(PIPE_OS_LINUX)
+Elf32_auxv_t aux;
+int fd;
+
+fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC);
+if (fd >= 0) {
+   while (read(fd, , sizeof(Elf32_auxv_t)) == sizeof(Elf32_auxv_t)) {
+  if (aux.a_type == AT_HWCAP) {
+ uint32_t hwcap = aux.a_un.a_val;
+
+ util_cpu_caps.has_neon = (hwcap >> 12) & 1;
+ break;
+  }
+   }
+   close (fd);
+}
+#endif /* PIPE_OS_LINUX */
+}
+#endif /* PIPE_ARCH_ARM */
+
 void
 util_cpu_detect(void)
 {
@@ -443,6 +481,10 @@ util_cpu_detect(void)
}
 #endif /* PIPE_ARCH_X86 || PIPE_ARCH_X86_64 */
 
+#if defined(PIPE_ARCH_ARM)
+   check_os_arm_support();
+#endif
+
 #if defined(PIPE_ARCH_PPC)
check_os_altivec_support();
 #endif /* PIPE_ARCH_PPC */
@@ -471,6 +513,7 @@ util_cpu_detect(void)
   debug_printf("util_cpu_caps.has_3dnow_ext = %u\n", 
util_cpu_caps.has_3dnow_ext);
   debug_printf("util_cpu_caps.has_xop = %u\n", util_cpu_caps.has_xop);
   debug_printf("util_cpu_caps.has_altivec = %u\n", 
util_cpu_caps.has_altivec);
+  debug_printf("util_cpu_caps.has_neon = %u\n", util_cpu_caps.has_neon);
   debug_printf("util_cpu_caps.has_daz = %u\n", util_cpu_caps.has_daz);
   debug_printf("util_cpu_caps.has_avx512f = %u\n", 
util_cpu_caps.has_avx512f);
   debug_printf("util_cpu_caps.has_avx512dq = %u\n", 
util_cpu_caps.has_avx512dq);
diff --git a/src/gallium/auxiliary/util/u_cpu_detect.h 
b/src/gallium/auxiliary/util/u_cpu_detect.h
index 3bd7294f0759..4a34ac4d9a63 100644
--- a/src/gallium/auxiliary/util/u_cpu_detect.h
+++ b/src/gallium/auxiliary/util/u_cpu_detect.h
@@ -72,6 +72,7 @@ struct util_cpu_caps {
unsigned has_xop:1;
unsigned has_altivec:1;
unsigned has_daz:1;
+   unsigned has_neon:1;
 
unsigned has_avx512f:1;
unsigned has_avx512dq:1;
-- 
2.11.0

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Re: [Mesa-dev] [PATCH] Android: fix r300g only build

[Rob Herring]

On Mon, Apr 24, 2017 at 11:59 AM, Emil Velikov  wrote:
> Hi Rob,
>
> On 24 April 2017 at 17:46, Rob Herring  wrote:
>> If r300g is the only radeon driver built, the Android build fails to
>> build:
>>
>> ninja: error:
>> 'out/target/product/linaro_x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_radeon_intermediates/export_includes',
>> needed by
>> 'out/target/product/linaro_x86_64/obj/SHARED_LIBRARIES/gallium_dri_intermediates/import_includes',
>> missing and no known rule to make it
>>
>> This is because the path to build libmesa_pipe_radeon was only getting
>> added for r600g and radeonsi, but the library dependency was added for
>> all radeon drivers. As libmesa_pipe_radeon is not needed for r300g, drop
>> the library dependency.
>>
> I think we want to move libmesa_amdgpu_addrlib in a similar way. The
> lib is used/required by libmesa_winsys_amdgpu which is a r600/radeonsi
> only.
> Can you please build test that and send a patch (or even squash here
> if you prefer)?

You are right. Looking at this a bit more, I think we want to push all
the "extra" libraries down into the driver makefiles. With that we can
also properly export and import include directories.

> The patch as-is
> Acked-by: Emil Velikov 

This one fixes the build, so can you apply it and I'll send a
follow-up series with further clean-ups. They'll need Mauro's help to
test because I don't have radeonsi building.

Rob
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Re: [Mesa-dev] [PATCH] st/glsl_to_tgsi: drop the merge_registers() pass

[Samuel Pitoiset]

On 04/24/2017 11:22 PM, Rob Clark wrote:

On Mon, Apr 24, 2017 at 5:18 PM, Samuel Pitoiset
 wrote:



On 04/24/2017 11:12 PM, Rob Clark wrote:


so I guess this is likely to hurt pipe drivers that don't (yet?) have
a real compiler backend.  (Ie. etnaviv and freedreno/a2xx.)  So maybe
it should be optional.



I can't say for these drivers, but it seems safer to add an option if this
can hurt them. How about PIPE_SHADER_CAP_TGSI_MERGE_REGISTERS?


so we have already PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY .. not sure
why that is a cap and not a shader-cap, tbh.  I guess I'm ok with
either bikeshed color ;-)


yeah, not sure of the _SHADER_ or not :)



BR,
-R






Also I wonder about the pre-llvm radeon gen's, since sb uses the
actual instruction encoding for IR between tgsi->sb and backend opt
passes..  iirc they have had problems when the tgsi code uses too many
registers.

BR,
-R

On Mon, Apr 24, 2017 at 5:01 PM, Samuel Pitoiset
 wrote:


The main goal of this pass to merge temporary registers in order
to reduce the total number of registers and also to produce
optimal TGSI code.

In fact, compilers seem to be confused when temporary variables
are already merged, maybe because it's done too early in the
process.

Removing the pass, reduce both the register pressure and the code
size (TGSI is no longer optimized, but who cares?).
shader-db results with RadeonSI and Nouveau are interesting.

Nouveau:

total instructions in shared programs : 3931608 -> 3929463 (-0.05%)
total gprs used in shared programs: 481255 -> 479014 (-0.47%)
total local used in shared programs   : 27481 -> 27381 (-0.36%)
total bytes used in shared programs   : 36031256 -> 36011120 (-0.06%)

  localgpr   inst  bytes
  helped  14147113091309
hurt   1  88 384 384

RadeonSI:

PERCENTAGE DELTASShaders SGPRs VGPRs SpillSGPR SpillVGPR
PrivVGPR   Scratch  CodeSize  MaxWaves Waits

--
All affected4906   -0.31 %   -0.40 %   -2.93 %  -20.00 %
.  -20.00 %   -0.18 %0.19 % .

--
Total  47109   -0.04 %   -0.05 %   -1.97 %   -7.14 %
.   -0.30 %   -0.03 %0.02 % .

Found by luck while fixing an issue in the TGSI dead code elimination
pass which affects tex instructions with bindless samplers.

Signed-off-by: Samuel Pitoiset 
---
   src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 62
--
   1 file changed, 62 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index de7fe7837a..d033bdcc5a 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -565,7 +565,6 @@ public:
  int eliminate_dead_code(void);

  void merge_two_dsts(void);
-   void merge_registers(void);
  void renumber_registers(void);

  void emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
@@ -5262,66 +5261,6 @@ glsl_to_tgsi_visitor::merge_two_dsts(void)
  }
   }

-/* Merges temporary registers together where possible to reduce the
number of
- * registers needed to run a program.
- *
- * Produces optimal code only after copy propagation and dead code
elimination
- * have been run. */
-void
-glsl_to_tgsi_visitor::merge_registers(void)
-{
-   int *last_reads = rzalloc_array(mem_ctx, int, this->next_temp);
-   int *first_writes = rzalloc_array(mem_ctx, int, this->next_temp);
-   struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct
rename_reg_pair, this->next_temp);
-   int i, j;
-   int num_renames = 0;
-
-   /* Read the indices of the last read and first write to each temp
register
-* into an array so that we don't have to traverse the instruction
list as
-* much. */
-   for (i = 0; i < this->next_temp; i++) {
-  last_reads[i] = -1;
-  first_writes[i] = -1;
-   }
-   get_last_temp_read_first_temp_write(last_reads, first_writes);
-
-   /* Start looking for registers with non-overlapping usages that can
be
-* merged together. */
-   for (i = 0; i < this->next_temp; i++) {
-  /* Don't touch unused registers. */
-  if (last_reads[i] < 0 || first_writes[i] < 0) continue;
-
-  for (j = 0; j < this->next_temp; j++) {
- /* Don't touch unused registers. */
- if (last_reads[j] < 0 || first_writes[j] < 0) continue;
-
- /* We can merge the two registers if the first write to j is
after or
-  * in the same instruction as the last read from i.  Note that
the
-  * register at index i will always be used earlier or at the
same time
-  * as the register at index j. */

Re: [Mesa-dev] [PATCH] st/glsl_to_tgsi: drop the merge_registers() pass

[Rob Clark]

On Mon, Apr 24, 2017 at 5:18 PM, Samuel Pitoiset
 wrote:
>
>
> On 04/24/2017 11:12 PM, Rob Clark wrote:
>>
>> so I guess this is likely to hurt pipe drivers that don't (yet?) have
>> a real compiler backend.  (Ie. etnaviv and freedreno/a2xx.)  So maybe
>> it should be optional.
>
>
> I can't say for these drivers, but it seems safer to add an option if this
> can hurt them. How about PIPE_SHADER_CAP_TGSI_MERGE_REGISTERS?

so we have already PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY .. not sure
why that is a cap and not a shader-cap, tbh.  I guess I'm ok with
either bikeshed color ;-)

BR,
-R


>
>>
>> Also I wonder about the pre-llvm radeon gen's, since sb uses the
>> actual instruction encoding for IR between tgsi->sb and backend opt
>> passes..  iirc they have had problems when the tgsi code uses too many
>> registers.
>>
>> BR,
>> -R
>>
>> On Mon, Apr 24, 2017 at 5:01 PM, Samuel Pitoiset
>>  wrote:
>>>
>>> The main goal of this pass to merge temporary registers in order
>>> to reduce the total number of registers and also to produce
>>> optimal TGSI code.
>>>
>>> In fact, compilers seem to be confused when temporary variables
>>> are already merged, maybe because it's done too early in the
>>> process.
>>>
>>> Removing the pass, reduce both the register pressure and the code
>>> size (TGSI is no longer optimized, but who cares?).
>>> shader-db results with RadeonSI and Nouveau are interesting.
>>>
>>> Nouveau:
>>>
>>> total instructions in shared programs : 3931608 -> 3929463 (-0.05%)
>>> total gprs used in shared programs: 481255 -> 479014 (-0.47%)
>>> total local used in shared programs   : 27481 -> 27381 (-0.36%)
>>> total bytes used in shared programs   : 36031256 -> 36011120 (-0.06%)
>>>
>>>  localgpr   inst  bytes
>>>  helped  14147113091309
>>>hurt   1  88 384 384
>>>
>>> RadeonSI:
>>>
>>> PERCENTAGE DELTASShaders SGPRs VGPRs SpillSGPR SpillVGPR
>>> PrivVGPR   Scratch  CodeSize  MaxWaves Waits
>>>
>>> --
>>> All affected4906   -0.31 %   -0.40 %   -2.93 %  -20.00 %
>>> .  -20.00 %   -0.18 %0.19 % .
>>>
>>> --
>>> Total  47109   -0.04 %   -0.05 %   -1.97 %   -7.14 %
>>> .   -0.30 %   -0.03 %0.02 % .
>>>
>>> Found by luck while fixing an issue in the TGSI dead code elimination
>>> pass which affects tex instructions with bindless samplers.
>>>
>>> Signed-off-by: Samuel Pitoiset 
>>> ---
>>>   src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 62
>>> --
>>>   1 file changed, 62 deletions(-)
>>>
>>> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
>>> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
>>> index de7fe7837a..d033bdcc5a 100644
>>> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
>>> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
>>> @@ -565,7 +565,6 @@ public:
>>>  int eliminate_dead_code(void);
>>>
>>>  void merge_two_dsts(void);
>>> -   void merge_registers(void);
>>>  void renumber_registers(void);
>>>
>>>  void emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
>>> @@ -5262,66 +5261,6 @@ glsl_to_tgsi_visitor::merge_two_dsts(void)
>>>  }
>>>   }
>>>
>>> -/* Merges temporary registers together where possible to reduce the
>>> number of
>>> - * registers needed to run a program.
>>> - *
>>> - * Produces optimal code only after copy propagation and dead code
>>> elimination
>>> - * have been run. */
>>> -void
>>> -glsl_to_tgsi_visitor::merge_registers(void)
>>> -{
>>> -   int *last_reads = rzalloc_array(mem_ctx, int, this->next_temp);
>>> -   int *first_writes = rzalloc_array(mem_ctx, int, this->next_temp);
>>> -   struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct
>>> rename_reg_pair, this->next_temp);
>>> -   int i, j;
>>> -   int num_renames = 0;
>>> -
>>> -   /* Read the indices of the last read and first write to each temp
>>> register
>>> -* into an array so that we don't have to traverse the instruction
>>> list as
>>> -* much. */
>>> -   for (i = 0; i < this->next_temp; i++) {
>>> -  last_reads[i] = -1;
>>> -  first_writes[i] = -1;
>>> -   }
>>> -   get_last_temp_read_first_temp_write(last_reads, first_writes);
>>> -
>>> -   /* Start looking for registers with non-overlapping usages that can
>>> be
>>> -* merged together. */
>>> -   for (i = 0; i < this->next_temp; i++) {
>>> -  /* Don't touch unused registers. */
>>> -  if (last_reads[i] < 0 || first_writes[i] < 0) continue;
>>> -
>>> -  for (j = 0; j < this->next_temp; j++) {
>>> - /* Don't touch unused registers. */
>>> - if 

Re: [Mesa-dev] [PATCH] st/glsl_to_tgsi: drop the merge_registers() pass

[Samuel Pitoiset]

On 04/24/2017 11:12 PM, Rob Clark wrote:

so I guess this is likely to hurt pipe drivers that don't (yet?) have
a real compiler backend.  (Ie. etnaviv and freedreno/a2xx.)  So maybe
it should be optional.


I can't say for these drivers, but it seems safer to add an option if 
this can hurt them. How about PIPE_SHADER_CAP_TGSI_MERGE_REGISTERS?




Also I wonder about the pre-llvm radeon gen's, since sb uses the
actual instruction encoding for IR between tgsi->sb and backend opt
passes..  iirc they have had problems when the tgsi code uses too many
registers.

BR,
-R

On Mon, Apr 24, 2017 at 5:01 PM, Samuel Pitoiset
 wrote:

The main goal of this pass to merge temporary registers in order
to reduce the total number of registers and also to produce
optimal TGSI code.

In fact, compilers seem to be confused when temporary variables
are already merged, maybe because it's done too early in the
process.

Removing the pass, reduce both the register pressure and the code
size (TGSI is no longer optimized, but who cares?).
shader-db results with RadeonSI and Nouveau are interesting.

Nouveau:

total instructions in shared programs : 3931608 -> 3929463 (-0.05%)
total gprs used in shared programs: 481255 -> 479014 (-0.47%)
total local used in shared programs   : 27481 -> 27381 (-0.36%)
total bytes used in shared programs   : 36031256 -> 36011120 (-0.06%)

 localgpr   inst  bytes
 helped  14147113091309
   hurt   1  88 384 384

RadeonSI:

PERCENTAGE DELTASShaders SGPRs VGPRs SpillSGPR SpillVGPR  PrivVGPR  
 Scratch  CodeSize  MaxWaves Waits
--
All affected4906   -0.31 %   -0.40 %   -2.93 %  -20.00 % .  
-20.00 %   -0.18 %0.19 % .
--
Total  47109   -0.04 %   -0.05 %   -1.97 %   -7.14 % .  
 -0.30 %   -0.03 %0.02 % .

Found by luck while fixing an issue in the TGSI dead code elimination
pass which affects tex instructions with bindless samplers.

Signed-off-by: Samuel Pitoiset 
---
  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 62 --
  1 file changed, 62 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index de7fe7837a..d033bdcc5a 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -565,7 +565,6 @@ public:
 int eliminate_dead_code(void);

 void merge_two_dsts(void);
-   void merge_registers(void);
 void renumber_registers(void);

 void emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
@@ -5262,66 +5261,6 @@ glsl_to_tgsi_visitor::merge_two_dsts(void)
 }
  }

-/* Merges temporary registers together where possible to reduce the number of
- * registers needed to run a program.
- *
- * Produces optimal code only after copy propagation and dead code elimination
- * have been run. */
-void
-glsl_to_tgsi_visitor::merge_registers(void)
-{
-   int *last_reads = rzalloc_array(mem_ctx, int, this->next_temp);
-   int *first_writes = rzalloc_array(mem_ctx, int, this->next_temp);
-   struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct 
rename_reg_pair, this->next_temp);
-   int i, j;
-   int num_renames = 0;
-
-   /* Read the indices of the last read and first write to each temp register
-* into an array so that we don't have to traverse the instruction list as
-* much. */
-   for (i = 0; i < this->next_temp; i++) {
-  last_reads[i] = -1;
-  first_writes[i] = -1;
-   }
-   get_last_temp_read_first_temp_write(last_reads, first_writes);
-
-   /* Start looking for registers with non-overlapping usages that can be
-* merged together. */
-   for (i = 0; i < this->next_temp; i++) {
-  /* Don't touch unused registers. */
-  if (last_reads[i] < 0 || first_writes[i] < 0) continue;
-
-  for (j = 0; j < this->next_temp; j++) {
- /* Don't touch unused registers. */
- if (last_reads[j] < 0 || first_writes[j] < 0) continue;
-
- /* We can merge the two registers if the first write to j is after or
-  * in the same instruction as the last read from i.  Note that the
-  * register at index i will always be used earlier or at the same time
-  * as the register at index j. */
- if (first_writes[i] <= first_writes[j] &&
- last_reads[i] <= first_writes[j]) {
-renames[num_renames].old_reg = j;
-renames[num_renames].new_reg = i;
-num_renames++;
-
-/* Update the first_writes and last_reads arrays with the new
- * values for the merged register 

Re: [Mesa-dev] [PATCH] st/glsl_to_tgsi: drop the merge_registers() pass

[Rob Clark]

so I guess this is likely to hurt pipe drivers that don't (yet?) have
a real compiler backend.  (Ie. etnaviv and freedreno/a2xx.)  So maybe
it should be optional.

Also I wonder about the pre-llvm radeon gen's, since sb uses the
actual instruction encoding for IR between tgsi->sb and backend opt
passes..  iirc they have had problems when the tgsi code uses too many
registers.

BR,
-R

On Mon, Apr 24, 2017 at 5:01 PM, Samuel Pitoiset
 wrote:
> The main goal of this pass to merge temporary registers in order
> to reduce the total number of registers and also to produce
> optimal TGSI code.
>
> In fact, compilers seem to be confused when temporary variables
> are already merged, maybe because it's done too early in the
> process.
>
> Removing the pass, reduce both the register pressure and the code
> size (TGSI is no longer optimized, but who cares?).
> shader-db results with RadeonSI and Nouveau are interesting.
>
> Nouveau:
>
> total instructions in shared programs : 3931608 -> 3929463 (-0.05%)
> total gprs used in shared programs: 481255 -> 479014 (-0.47%)
> total local used in shared programs   : 27481 -> 27381 (-0.36%)
> total bytes used in shared programs   : 36031256 -> 36011120 (-0.06%)
>
> localgpr   inst  bytes
> helped  14147113091309
>   hurt   1  88 384 384
>
> RadeonSI:
>
> PERCENTAGE DELTASShaders SGPRs VGPRs SpillSGPR SpillVGPR  
> PrivVGPR   Scratch  CodeSize  MaxWaves Waits
> --
> All affected4906   -0.31 %   -0.40 %   -2.93 %  -20.00 % .
>   -20.00 %   -0.18 %0.19 % .
> --
> Total  47109   -0.04 %   -0.05 %   -1.97 %   -7.14 % .
>-0.30 %   -0.03 %0.02 % .
>
> Found by luck while fixing an issue in the TGSI dead code elimination
> pass which affects tex instructions with bindless samplers.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 62 
> --
>  1 file changed, 62 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index de7fe7837a..d033bdcc5a 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -565,7 +565,6 @@ public:
> int eliminate_dead_code(void);
>
> void merge_two_dsts(void);
> -   void merge_registers(void);
> void renumber_registers(void);
>
> void emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
> @@ -5262,66 +5261,6 @@ glsl_to_tgsi_visitor::merge_two_dsts(void)
> }
>  }
>
> -/* Merges temporary registers together where possible to reduce the number of
> - * registers needed to run a program.
> - *
> - * Produces optimal code only after copy propagation and dead code 
> elimination
> - * have been run. */
> -void
> -glsl_to_tgsi_visitor::merge_registers(void)
> -{
> -   int *last_reads = rzalloc_array(mem_ctx, int, this->next_temp);
> -   int *first_writes = rzalloc_array(mem_ctx, int, this->next_temp);
> -   struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct 
> rename_reg_pair, this->next_temp);
> -   int i, j;
> -   int num_renames = 0;
> -
> -   /* Read the indices of the last read and first write to each temp register
> -* into an array so that we don't have to traverse the instruction list as
> -* much. */
> -   for (i = 0; i < this->next_temp; i++) {
> -  last_reads[i] = -1;
> -  first_writes[i] = -1;
> -   }
> -   get_last_temp_read_first_temp_write(last_reads, first_writes);
> -
> -   /* Start looking for registers with non-overlapping usages that can be
> -* merged together. */
> -   for (i = 0; i < this->next_temp; i++) {
> -  /* Don't touch unused registers. */
> -  if (last_reads[i] < 0 || first_writes[i] < 0) continue;
> -
> -  for (j = 0; j < this->next_temp; j++) {
> - /* Don't touch unused registers. */
> - if (last_reads[j] < 0 || first_writes[j] < 0) continue;
> -
> - /* We can merge the two registers if the first write to j is after 
> or
> -  * in the same instruction as the last read from i.  Note that the
> -  * register at index i will always be used earlier or at the same 
> time
> -  * as the register at index j. */
> - if (first_writes[i] <= first_writes[j] &&
> - last_reads[i] <= first_writes[j]) {
> -renames[num_renames].old_reg = j;
> -renames[num_renames].new_reg = i;
> -num_renames++;
> -
> -/* Update the first_writes and last_reads arrays with the new
> - * values for the merged 

[Mesa-dev] [PATCH] st/glsl_to_tgsi: drop the merge_registers() pass

[Samuel Pitoiset]

The main goal of this pass to merge temporary registers in order
to reduce the total number of registers and also to produce
optimal TGSI code.

In fact, compilers seem to be confused when temporary variables
are already merged, maybe because it's done too early in the
process.

Removing the pass, reduce both the register pressure and the code
size (TGSI is no longer optimized, but who cares?).
shader-db results with RadeonSI and Nouveau are interesting.

Nouveau:

total instructions in shared programs : 3931608 -> 3929463 (-0.05%)
total gprs used in shared programs: 481255 -> 479014 (-0.47%)
total local used in shared programs   : 27481 -> 27381 (-0.36%)
total bytes used in shared programs   : 36031256 -> 36011120 (-0.06%)

localgpr   inst  bytes
helped  14147113091309
  hurt   1  88 384 384

RadeonSI:

PERCENTAGE DELTASShaders SGPRs VGPRs SpillSGPR SpillVGPR  PrivVGPR  
 Scratch  CodeSize  MaxWaves Waits
--
All affected4906   -0.31 %   -0.40 %   -2.93 %  -20.00 % .  
-20.00 %   -0.18 %0.19 % .
--
Total  47109   -0.04 %   -0.05 %   -1.97 %   -7.14 % .  
 -0.30 %   -0.03 %0.02 % .

Found by luck while fixing an issue in the TGSI dead code elimination
pass which affects tex instructions with bindless samplers.

Signed-off-by: Samuel Pitoiset 
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 62 --
 1 file changed, 62 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index de7fe7837a..d033bdcc5a 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -565,7 +565,6 @@ public:
int eliminate_dead_code(void);
 
void merge_two_dsts(void);
-   void merge_registers(void);
void renumber_registers(void);
 
void emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
@@ -5262,66 +5261,6 @@ glsl_to_tgsi_visitor::merge_two_dsts(void)
}
 }
 
-/* Merges temporary registers together where possible to reduce the number of
- * registers needed to run a program.
- *
- * Produces optimal code only after copy propagation and dead code elimination
- * have been run. */
-void
-glsl_to_tgsi_visitor::merge_registers(void)
-{
-   int *last_reads = rzalloc_array(mem_ctx, int, this->next_temp);
-   int *first_writes = rzalloc_array(mem_ctx, int, this->next_temp);
-   struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct 
rename_reg_pair, this->next_temp);
-   int i, j;
-   int num_renames = 0;
-
-   /* Read the indices of the last read and first write to each temp register
-* into an array so that we don't have to traverse the instruction list as
-* much. */
-   for (i = 0; i < this->next_temp; i++) {
-  last_reads[i] = -1;
-  first_writes[i] = -1;
-   }
-   get_last_temp_read_first_temp_write(last_reads, first_writes);
-
-   /* Start looking for registers with non-overlapping usages that can be
-* merged together. */
-   for (i = 0; i < this->next_temp; i++) {
-  /* Don't touch unused registers. */
-  if (last_reads[i] < 0 || first_writes[i] < 0) continue;
-
-  for (j = 0; j < this->next_temp; j++) {
- /* Don't touch unused registers. */
- if (last_reads[j] < 0 || first_writes[j] < 0) continue;
-
- /* We can merge the two registers if the first write to j is after or
-  * in the same instruction as the last read from i.  Note that the
-  * register at index i will always be used earlier or at the same time
-  * as the register at index j. */
- if (first_writes[i] <= first_writes[j] &&
- last_reads[i] <= first_writes[j]) {
-renames[num_renames].old_reg = j;
-renames[num_renames].new_reg = i;
-num_renames++;
-
-/* Update the first_writes and last_reads arrays with the new
- * values for the merged register index, and mark the newly unused
- * register index as such. */
-assert(last_reads[j] >= last_reads[i]);
-last_reads[i] = last_reads[j];
-first_writes[j] = -1;
-last_reads[j] = -1;
- }
-  }
-   }
-
-   rename_temp_registers(num_renames, renames);
-   ralloc_free(renames);
-   ralloc_free(last_reads);
-   ralloc_free(first_writes);
-}
-
 /* Reassign indices to temporary registers by reusing unused indices created
  * by optimization passes. */
 void
@@ -6712,7 +6651,6 @@ get_mesa_program_tgsi(struct gl_context *ctx,
while (v->eliminate_dead_code());
 
v->merge_two_dsts();
-   

Re: [Mesa-dev] [PATCH] autogen.sh: set default sendemail.to

[Ben Widawsky]

On 17-04-24 21:29:32, Jason Ekstrand wrote:
This seems like something that would be more appropriate to put on a 
"getting started" page than autogen.sh.  The very last thing I (as a 
user of it) would expect autogen.sh to do is monkey with my git 
config; local or otherwise.




"Otherwise" is certainly not okay, but I like this. Feel free to nak of course.

Acked-by: Ben Widawsky 



On April 24, 2017 6:16:14 PM Emil Velikov  wrote:


From: Emil Velikov 

To ease patch submission process a tiny bit.

Cc: Ben Widawsky 
Suggested-by: Ben Widawsky 
Signed-off-by: Emil Velikov 
---
autogen.sh | 3 +++
1 file changed, 3 insertions(+)

diff --git a/autogen.sh b/autogen.sh
index c8960971d24..d178880b407 100755
--- a/autogen.sh
+++ b/autogen.sh
@@ -6,6 +6,9 @@ test -z "$srcdir" && srcdir=.
ORIGDIR=`pwd`
cd "$srcdir"

+git config --local --get sendemail.to >/dev/null ||
+git config --local sendemail.to 
"mesa-dev@lists.freedesktop.org" 2>/dev/null

+
autoreconf --force --verbose --install || exit 1
cd "$ORIGDIR" || exit $?

--
2.12.2

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Re: [Mesa-dev] [RFC PATCH 3/4] ff_fragment_shader: mark impossible switch values with unreachable

[Giuseppe Bilotta]

On Mon, Apr 24, 2017 at 5:06 PM, Brian Paul  wrote:
> On 04/22/2017 03:46 PM, Giuseppe Bilotta wrote:
>>
>> Makes sense. As Gustaw suggests, it _shouldn't_ happen, but there's
>> nothing to lose in being cautious about it 8-). I'll respin this patch
>> with the assert+return here.
>
> I just want to second that.

Unless I did something wrong, a v2 of the patch, with the
assert+return should be floating around in the patchwork now 8-) But
then again, it replaces a lot of the other assert+return with an
unreachable, so you might not like that either 8-P

>  It's really bad when our driver crashes in the
> hands of a customer.  I'd rather have a rendering glitch than a crash.  I'm
> kind of worried about the proliferation of unreachable() in Mesa.

Well, the obvious question would be why such unreachable code actually
gets reached in the first place, but I guess it's not always easy to
get the conditions under which these supposedly invalid codepaths get
reached.

Would it be possible to preserve the assert+return semantics with
something similar to a Linux kernel WARN_ON? (Ideally even with debug
backtrace support, but wrapping it all in a macro would allow this to
be added at a later stage if deemed appropriate/possible).

-- 
Giuseppe "Oblomov" Bilotta
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Re: [Mesa-dev] [PATCH] autogen.sh: set default sendemail.to

[Jason Ekstrand]

This seems like something that would be more appropriate to put on a 
"getting started" page than autogen.sh.  The very last thing I (as a user 
of it) would expect autogen.sh to do is monkey with my git config; local or 
otherwise.



On April 24, 2017 6:16:14 PM Emil Velikov  wrote:


From: Emil Velikov 

To ease patch submission process a tiny bit.

Cc: Ben Widawsky 
Suggested-by: Ben Widawsky 
Signed-off-by: Emil Velikov 
---
 autogen.sh | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/autogen.sh b/autogen.sh
index c8960971d24..d178880b407 100755
--- a/autogen.sh
+++ b/autogen.sh
@@ -6,6 +6,9 @@ test -z "$srcdir" && srcdir=.
 ORIGDIR=`pwd`
 cd "$srcdir"

+git config --local --get sendemail.to >/dev/null ||
+git config --local sendemail.to "mesa-dev@lists.freedesktop.org" 
2>/dev/null

+
 autoreconf --force --verbose --install || exit 1
 cd "$ORIGDIR" || exit $?

--
2.12.2

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Re: [Mesa-dev] [PATCH 2/2] radeonsi: disable primitive restart for non-strip prims based on app list

[Samuel Pitoiset]

On 04/24/2017 06:32 PM, Marek Olšák wrote:

On Mon, Apr 24, 2017 at 5:34 PM, Nicolai Hähnle  wrote:

On 24.04.2017 15:22, Marek Olšák wrote:


From: Marek Olšák 



I don't like it. This kind of app-specific override is what drirc was meant
to provide. Having separate places for it is confusing.


The question is: would other drivers want this code in st_draw_vbo?
For threaded gallium, we shouldn't put more stuff into st_draw_vbo.

Alternatively, it can be a flag for pipe_screen::context_create to
enable this behavior in radeonsi and keep the list in drirc.


I do agree with Nicolai, it would be nice to avoid adding app-specific 
workarounds directly in the driver.


Maybe you can add a new function in pipe_screen, like 
set_context_options() with a new flag or something? There are many 
get_XXX() functions there, maybe it makes sense to add a set_something().




Marek
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Re: [Mesa-dev] [PATCH 1/2] radeonsi: add a HUD query for draw calls with primitive restart

[Samuel Pitoiset]

Reviewed-by: Samuel Pitoiset 

On 04/24/2017 03:22 PM, Marek Olšák wrote:

From: Marek Olšák 

---
  src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
  src/gallium/drivers/radeon/r600_query.c   | 7 +++
  src/gallium/drivers/radeon/r600_query.h   | 1 +
  src/gallium/drivers/radeonsi/si_state_draw.c  | 2 ++
  4 files changed, 11 insertions(+)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index fbd0ac7..3e83d37 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -573,20 +573,21 @@ struct r600_common_context {
unsigned flags; /* flush flags */
  
  	/* Queries. */

/* Maintain the list of active queries for pausing between IBs. */
int num_occlusion_queries;
int num_perfect_occlusion_queries;
struct list_headactive_queries;
unsignednum_cs_dw_queries_suspend;
/* Misc stats. */
unsignednum_draw_calls;
+   unsignednum_prim_restart_calls;
unsignednum_spill_draw_calls;
unsignednum_compute_calls;
unsignednum_spill_compute_calls;
unsignednum_dma_calls;
unsignednum_cp_dma_calls;
unsignednum_vs_flushes;
unsignednum_ps_flushes;
unsignednum_cs_flushes;
unsignednum_fb_cache_flushes;
unsignednum_L2_invalidates;
diff --git a/src/gallium/drivers/radeon/r600_query.c 
b/src/gallium/drivers/radeon/r600_query.c
index 0980eca..cbf4bba 100644
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -90,20 +90,23 @@ static bool r600_query_sw_begin(struct r600_common_context 
*rctx,
struct r600_query_sw *query = (struct r600_query_sw *)rquery;
enum radeon_value_id ws_id;
  
  	switch(query->b.type) {

case PIPE_QUERY_TIMESTAMP_DISJOINT:
case PIPE_QUERY_GPU_FINISHED:
break;
case R600_QUERY_DRAW_CALLS:
query->begin_result = rctx->num_draw_calls;
break;
+   case R600_QUERY_PRIM_RESTART_CALLS:
+   query->begin_result = rctx->num_prim_restart_calls;
+   break;
case R600_QUERY_SPILL_DRAW_CALLS:
query->begin_result = rctx->num_spill_draw_calls;
break;
case R600_QUERY_COMPUTE_CALLS:
query->begin_result = rctx->num_compute_calls;
break;
case R600_QUERY_SPILL_COMPUTE_CALLS:
query->begin_result = rctx->num_spill_compute_calls;
break;
case R600_QUERY_DMA_CALLS:
@@ -214,20 +217,23 @@ static bool r600_query_sw_end(struct r600_common_context 
*rctx,
  
  	switch(query->b.type) {

case PIPE_QUERY_TIMESTAMP_DISJOINT:
break;
case PIPE_QUERY_GPU_FINISHED:
rctx->b.flush(>b, >fence, PIPE_FLUSH_DEFERRED);
break;
case R600_QUERY_DRAW_CALLS:
query->end_result = rctx->num_draw_calls;
break;
+   case R600_QUERY_PRIM_RESTART_CALLS:
+   query->end_result = rctx->num_prim_restart_calls;
+   break;
case R600_QUERY_SPILL_DRAW_CALLS:
query->end_result = rctx->num_spill_draw_calls;
break;
case R600_QUERY_COMPUTE_CALLS:
query->end_result = rctx->num_compute_calls;
break;
case R600_QUERY_SPILL_COMPUTE_CALLS:
query->end_result = rctx->num_spill_compute_calls;
break;
case R600_QUERY_DMA_CALLS:
@@ -1754,20 +1760,21 @@ void r600_query_fix_enabled_rb_mask(struct 
r600_common_screen *rscreen)
XFULL(name_, query_type_, type_, result_type_, ~(unsigned)0)
  
  #define XG(group_, name_, query_type_, type_, result_type_) \

XFULL(name_, query_type_, type_, result_type_, 
R600_QUERY_GROUP_##group_)
  
  static struct pipe_driver_query_info r600_driver_query_list[] = {

X("num-compilations", NUM_COMPILATIONS,   UINT64, 
CUMULATIVE),
X("num-shaders-created",  NUM_SHADERS_CREATED,UINT64, 
CUMULATIVE),
X("num-shader-cache-hits",NUM_SHADER_CACHE_HITS,  UINT64, 
CUMULATIVE),
X("draw-calls",   DRAW_CALLS, UINT64, 
AVERAGE),
+   X("prim-restart-calls",   PRIM_RESTART_CALLS, UINT64, 
AVERAGE),
X("spill-draw-calls", SPILL_DRAW_CALLS,   UINT64, AVERAGE),
X("compute-calls",COMPUTE_CALLS, 

Re: [Mesa-dev] [PATCH 10/14] travis: add "scons swr" to the build matrix

[Kyriazis, George]

As discussed,

If you run scons with a small -j number, it would work (verified by Emil).

With that change

Reviewed-by: George Kyriazis 
>

For the rest of the series, I don’t have enough experience with travis to 
review..

George

On Apr 21, 2017, at 7:08 AM, Emil Velikov 
> wrote:

From: Emil Velikov 
>

Requires GCC 5.0 (due to the C++14 requirement) and LLVM 3.9.

v2: Enable the target, add libedit-dev, rework check target.

Cc: Tim Rowley >
Cc: George Kyriazis 
>
Signed-off-by: Emil Velikov 
>
---
Note!
With this the Travis instance seems to be having Internal Compiler Error
at various stages of the build. Both GCC5 and GCC6 are affected, yet the
Autotools build (coming later) seems unaffected.

Tim, George do you guys have some time to investigate the problem?
Alternatively we'll have to drop the patch for now :-(
---
.travis.yml | 28 
1 file changed, 28 insertions(+)

diff --git a/.travis.yml b/.travis.yml
index 6eb208ace24..aa2a55d7bb4 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -82,6 +82,32 @@ matrix:
- libexpat1-dev
- libx11-xcb-dev
- libelf-dev
+- env:
+- LABEL="scons SWR"
+- BUILD=scons
+- SCONS_TARGET="swr=1"
+- SCONS_CHECK_COMMAND="true"
+- LLVM_VERSION=3.9
+- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
+- OVERRIDE_CC=gcc-5
+- OVERRIDE_CXX=g++-5
+  addons:
+apt:
+  sources:
+- ubuntu-toolchain-r-test
+- llvm-toolchain-trusty-3.9
+  packages:
+- scons
+# LLVM packaging is broken and misses these dependencies
+- libedit-dev
+# From sources above
+- g++-5
+- llvm-3.9-dev
+# Common
+- x11proto-xf86vidmode-dev
+- libexpat1-dev
+- libx11-xcb-dev
+- libelf-dev

install:
  - pip install --user mako
@@ -157,5 +183,7 @@ script:
fi

  - if test "x$BUILD" = xscons; then
+  test $OVERRIDE_CC && export CC=$OVERRIDE_CC;
+  test $OVERRIDE_CXX && export CXX=$OVERRIDE_CXX;
  scons $SCONS_TARGET && eval $SCONS_CHECK_COMMAND;
fi
--
2.12.2


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Re: [Mesa-dev] [PATCH 1/2] i965/vec4: set swizzle when loading an uniform

[Francisco Jerez]

Samuel Iglesias Gonsálvez  writes:

> On Fri, 2017-04-21 at 10:23 -0700, Francisco Jerez wrote:
>> Samuel Iglesias Gonsálvez  writes:
>> 
>> > On Thu, 2017-04-20 at 10:26 -0700, Francisco Jerez wrote:
>> > > Samuel Iglesias Gonsálvez  writes:
>> > > 
>> > > > It was setting XYWZ swizzle to all uniforms, no matter if they
>> > > > were
>> > > > a vector or not.
>> > > > 
>> > > > Signed-off-by: Samuel Iglesias Gonsálvez 
>> > > > Cc: curroje...@riseup.net
>> > > 
>> > > Don't you need to CC mesa-stable here and in the next patch?
>> > > 
>> > 
>> > I considered it but I has doubts about which tag use "17.1.0-rc1"
>> > or
>> > just "17.1.0" or whatever. So my plan is to notify Emil once they
>> > are
>> > merged (and add Cc to stable in the commit log before pushing it to
>> > master).
>> > 
>> > If you are more comfortable with Cc mesa-stable, I will do it next
>> > time
>> > (or if I need to send v2 of this series).
>> > 
>> 
>> I believe Emil will notice them even if you don't put a version
>> tag.  I
>> don't really care how you nominate it for stable as long as it hits
>> the
>> 17.1 branch before the end of the release cycle.  ;)
>> 
>> > > > ---
>> > > >  src/intel/compiler/brw_vec4_nir.cpp | 1 +
>> > > >  1 file changed, 1 insertion(+)
>> > > > 
>> > > > diff --git a/src/intel/compiler/brw_vec4_nir.cpp
>> > > > b/src/intel/compiler/brw_vec4_nir.cpp
>> > > > index a82d52088a8..5f4488c7e86 100644
>> > > > --- a/src/intel/compiler/brw_vec4_nir.cpp
>> > > > +++ b/src/intel/compiler/brw_vec4_nir.cpp
>> > > > @@ -863,6 +863,7 @@
>> > > > vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
>> > > >   unsigned offset = const_offset->u32[0] + shift * 4;
>> > > >   src.offset = ROUND_DOWN_TO(offset, 16);
>> > > >   shift = (offset % 16) / 4;
>> > > > + src.swizzle = brw_swizzle_for_size(instr-
>> > > > > num_components);
>> > > 
>> > > What about the indirect case a few lines below?  Isn't the
>> > > swizzle
>> > > passed
>> > > to the mov indirect instruction still bogus?
>> > > 
>> > 
>> > This is different. It is expecting to have a swizzle of XYZW
>> > because
>> > MOV_INDIRECT will copy all the contents. See assert in
>> > move_uniform_array_access_to_pull_constants()
>> 
>> I believe the ultimate problem here is that the MOV_INDIRECT gets a
>> writemask of XYZW even if you're reading a scalar, so setting the
>> minimal swizzle will lead to a situation in which the resulting
>> swizzle
>> is not the identity so you will run into trouble to turn it into
>> scratch
>> access.  That brings me to the following question which I don't think
>> I
>> can answer by looking at this patch alone: If having an XYZW swizzle
>> is
>> a problem for direct moves (I assume this patch is fixing
>> something?),
>
> The bug is to properly identify DFs and dvecs, instead of considering
> all of them as dvec4 when aligning them for the push constant buffer,
> which is done in next patch.
>

Sorry, I'm not following what you mean with the last paragraph.  What
does this have to do with identifying DFs?

>> how come it is not a problem for indirect moves?
>> 
>
> It is not a problem because the uniforms under indirect moves are moved
> to pull constant buffer in
> move_uniform_array_access_to_pull_constants().
>

Is that really always the case?  Even on Vulkan?

> Those DF pull constants are read with 2 messages, so they don't need to
> be dvec4-aligned like in the case of direct moves on the push constant
> buffer, and the swizzle is actually ignored when loading it to pull
> constant buffer.
>

Is the swizzle actually meant to be ignored or is that a bug of the
move_uniform_array_access_to_pull_constants() pass?  If it is meant to
be ignored why do we set a non-identity swizzle below for shift != 0 in
the indirect path a couple of lines below?

> However, if you prefer to keep consistency between both cases, I can
> apply the shuffle globally and remove the NOOP assert in
> move_uniform_array_access_to_pull_constants(). This change doesn't add
> any regression on piglit.
>
> What do you think?
>

I'm not really that worried about consistency, just trying to understand
what exactly is going on in this patch in order to convince myself that
this is a complete fix.

>> > and the comment in pack_uniform_registers():
>> > 
>> > /* We just mark every register touched by a MOV_INDIRECT as being
>> >  * fully used.  This ensures that it doesn't broken up piecewise by
>> >  * the next part of our packing algorithm.
>> >  */
>> > 
>> 
>> Not sure why this is relevant to the discussion?  The same will be
>> the
>> case if you set the same swizzle as for the direct move.
>> 
>
> Right, I was wrong. Sorry for the noise,
>
> Sam
>
>> > Sam
>> > 
>> > > >   src.swizzle += BRW_SWIZZLE4(shift, shift, shift,
>> > > > shift);
>> > > >  
>> > > >   emit(MOV(dest, src));
>> > > > -- 
>> > > > 2.11.0

[Mesa-dev] [Bug 100613] Regression in Mesa 17 on s390x (zSystems)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100613

--- Comment #14 from Roland Scheidegger  ---
(In reply to Ray Strode [halfline] from comment #13)
> Created attachment 131000 [details] [review]
> patch that didn't help at all
> 
> Hi,
> (In reply to Roland Scheidegger from comment #10)
> > I'm not sure maybe loading as 3x16 plus vector padding, analogous to what is
> > done for 3x32 would work? The code for doing so should work, it's purely not
> > done this way because codegen on x86 produces a (albeit correct) mess - but
> > it might fare better on ppc...
> So to be clear, I don't really grok the code. I did have a go at what I
> thought you meant, using the quick-and-dirty proof-of-concept patch above
> but it failed in the same way as doing the scalar fetch.
This looks good to me. I actually thought the code would be easily switchable,
but I suppose I nuked that when I noticed there's no point on doing 3x16bit
fetches on x86... (The fetch_dst_type.length adjustment seems unnecessary but
harmless.)
So, if that doesn't help, this at least suggests loading 3x16 plus pad is the
same as loading 1x48 plus zext. This is actually good news as it would be
really confusing otherwise... So it just needs a vector_justify somewhere.

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Re: [Mesa-dev] [PATCH 08/14] travis: split out matrix from env

[Emil Velikov]

On 24 April 2017 at 18:15, Eric Engestrom  wrote:
> On Friday, 2017-04-21 13:08:23 +0100, Emil Velikov wrote:
>> From: Emil Velikov 
>>
>> With next commits we'll add a couple of more options.
>>
>> v2: Rework check target.
>>
>> Signed-off-by: Emil Velikov 
>> ---
>>  .travis.yml | 18 +-
>>  1 file changed, 13 insertions(+), 5 deletions(-)
>>
>> diff --git a/.travis.yml b/.travis.yml
>> index a4fe00d8023..d95d4a74650 100644
>> --- a/.travis.yml
>> +++ b/.travis.yml
>> @@ -38,10 +38,18 @@ env:
>>  - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
>>  - PKG_CONFIG_PATH=$HOME/prefix/lib/pkgconfig
>>  - LD_LIBRARY_PATH="$HOME/prefix/lib:$LD_LIBRARY_PATH"
>> -- MAKEFLAGS=-j2
>> -  matrix:
>> -- BUILD=make
>> -- BUILD=scons
>> +
>> +matrix:
>> +  include:
>> +- env:
>> +- LABEL="make"
>> +- BUILD=make
>> +- MAKEFLAGS=-j2
>> +- env:
>> +- LABEL="scons LLVM"
>> +- BUILD=scons
>> +- SCONS_TARGET="llvm=1"
>> +- SCONS_CHECK_COMMAND="scons llvm=1 check"
>>
>>  install:
>>- pip install --user mako
>> @@ -117,5 +125,5 @@ script:
>>  fi
>>
>>- if test "x$BUILD" = xscons; then
>> -  scons llvm=1 && scons llvm=1 check;
>> +  scons $SCONS_TARGET && eval $SCONS_CHECK_COMMAND;
>
> Eval? Why not `scons $SCONS_CHECK` with `SCONS_CHECK="llvm=1 check"`?
> (Sorry if this was discussed on v1, I didn't see it.)
>
It wasn't discussed - simply kept the scons check invocation analogous
to the make one*.
Can add a note/comment, if you prefer.

-Emil

*For the latter we use MAKE_CHECK_COMMAND="make -C src/gtest check &&
make -C src/intel check" since a plain "make check" will compile a lot
of tests that we've already tested in another combo.
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Re: [Mesa-dev] [PATCH 2/2] radeonsi: disable primitive restart for non-strip prims based on app list

[Marek Olšák]

On Mon, Apr 24, 2017 at 6:43 PM, Nicolai Hähnle  wrote:
> On 24.04.2017 18:32, Marek Olšák wrote:
>>
>> On Mon, Apr 24, 2017 at 5:34 PM, Nicolai Hähnle 
>> wrote:
>>>
>>> On 24.04.2017 15:22, Marek Olšák wrote:


 From: Marek Olšák 
>>>
>>>
>>>
>>> I don't like it. This kind of app-specific override is what drirc was
>>> meant
>>> to provide. Having separate places for it is confusing.
>>
>>
>> The question is: would other drivers want this code in st_draw_vbo?
>> For threaded gallium, we shouldn't put more stuff into st_draw_vbo.
>>
>> Alternatively, it can be a flag for pipe_screen::context_create to
>> enable this behavior in radeonsi and keep the list in drirc.
>
>
> Is there a particular reason we can't let radeonsi (and other gallium
> drivers) access drirc directly?

Windows I guess. st/dri provides drirc and is Linux-only.

Marek
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Re: [Mesa-dev] [PATCH 11/14] travis: add "make swr" to the build matrix

[Eric Engestrom]

On Friday, 2017-04-21 13:08:26 +0100, Emil Velikov wrote:
> From: Emil Velikov 
> 
> Signed-off-by: Emil Velikov 
> ---
>  .travis.yml | 39 ---
>  1 file changed, 36 insertions(+), 3 deletions(-)
> 
> diff --git a/.travis.yml b/.travis.yml
> index aa2a55d7bb4..1b0368f0a5e 100644
> --- a/.travis.yml
> +++ b/.travis.yml
> @@ -31,6 +31,9 @@ matrix:
>  - MAKEFLAGS=-j2
>  - LLVM_VERSION=3.9
>  - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
> +- DRI_DRIVERS="i915,i965,radeon,r200,swrast,nouveau"
> +- 
> GALLIUM_DRIVERS="i915,nouveau,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
> +- VULKAN_DRIVERS="radeon"
>addons:
>  apt:
>sources:
> @@ -46,6 +49,34 @@ matrix:
>  - libx11-xcb-dev
>  - libelf-dev
>  - env:
> +# NOTE: Building SWR is 2x (yes two) times slower than all the other
> +# gallium drivers combined.
> +# Start this early so that it doesn't hunder the run time.
> +- LABEL="make Gallium Drivers SWR"
> +- BUILD=make
> +- MAKEFLAGS=-j2
> +- LLVM_VERSION=3.9
> +- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
> +- OVERRIDE_CC=gcc-5
> +- OVERRIDE_CXX=g++-5
> +- DRI_DRIVERS=""
> +- GALLIUM_DRIVERS="swr"
> +- VULKAN_DRIVERS=""
> +  addons:
> +apt:
> +  sources:
> +- ubuntu-toolchain-r-test
> +- llvm-toolchain-trusty-3.9
> +  packages:
> +# From sources above
> +- g++-5
> +- llvm-3.9-dev
> +# Common
> +- x11proto-xf86vidmode-dev
> +- libexpat1-dev
> +- libx11-xcb-dev
> +- libelf-dev
> +- env:
>  - LABEL="scons"
>  - BUILD=scons
>  # Explicitly disable.
> @@ -172,11 +203,13 @@ install:
>  
>  script:
>- if test "x$BUILD" = xmake; then
> +  test $OVERRIDE_CC && export CC=$OVERRIDE_CC;
> +  test $OVERRIDE_CXX && export CXX=$OVERRIDE_CXX;

This will break if/when someone adds flags.
`test -n "$OVERRIDE_CCC"` doesn't have this issue.

>./autogen.sh --enable-debug
>  --with-platforms=x11,drm
> ---with-dri-drivers=i915,i965,radeon,r200,swrast,nouveau
> -
> --with-gallium-drivers=i915,nouveau,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,etnaviv,imx
> ---with-vulkan-drivers=radeon
> +--with-dri-drivers=$DRI_DRIVERS
> +--with-gallium-drivers=$GALLIUM_DRIVERS
> +--with-vulkan-drivers=$VULKAN_DRIVERS
>  --disable-llvm-shared-libs
>  ;
>make && make check;
> -- 
> 2.12.2
> 
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Re: [Mesa-dev] [PATCH 08/14] travis: split out matrix from env

[Eric Engestrom]

On Friday, 2017-04-21 13:08:23 +0100, Emil Velikov wrote:
> From: Emil Velikov 
> 
> With next commits we'll add a couple of more options.
> 
> v2: Rework check target.
> 
> Signed-off-by: Emil Velikov 
> ---
>  .travis.yml | 18 +-
>  1 file changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/.travis.yml b/.travis.yml
> index a4fe00d8023..d95d4a74650 100644
> --- a/.travis.yml
> +++ b/.travis.yml
> @@ -38,10 +38,18 @@ env:
>  - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
>  - PKG_CONFIG_PATH=$HOME/prefix/lib/pkgconfig
>  - LD_LIBRARY_PATH="$HOME/prefix/lib:$LD_LIBRARY_PATH"
> -- MAKEFLAGS=-j2
> -  matrix:
> -- BUILD=make
> -- BUILD=scons
> +
> +matrix:
> +  include:
> +- env:
> +- LABEL="make"
> +- BUILD=make
> +- MAKEFLAGS=-j2
> +- env:
> +- LABEL="scons LLVM"
> +- BUILD=scons
> +- SCONS_TARGET="llvm=1"
> +- SCONS_CHECK_COMMAND="scons llvm=1 check"
>  
>  install:
>- pip install --user mako
> @@ -117,5 +125,5 @@ script:
>  fi
>  
>- if test "x$BUILD" = xscons; then
> -  scons llvm=1 && scons llvm=1 check;
> +  scons $SCONS_TARGET && eval $SCONS_CHECK_COMMAND;

Eval? Why not `scons $SCONS_CHECK` with `SCONS_CHECK="llvm=1 check"`?
(Sorry if this was discussed on v1, I didn't see it.)

>  fi
> -- 
> 2.12.2
> 
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Re: [Mesa-dev] [PATCH 10/14] travis: add "scons swr" to the build matrix

[Emil Velikov]

On 21 April 2017 at 15:06, Kyriazis, George  wrote:
> rasterizer.cpp takes a lot of resources to compile.  Looks like the autotools 
> build runs -j2, which limits the exposure, because of fewer parallel jobs, 
> while scons, by default is more aggressive.
>
> Suggest running scons -j 1 or scons -j 2 for swr.
>
This was it - thanks George.

SCons uses 32 (yes) jobs on the Travis instance, and doing down to 4
fixes the problem.

Any ack or review on the series would be appreciated ;-)

-Emil
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Re: [Mesa-dev] [PATCH] android: radv/ac: Fix nir.h include

[Emil Velikov]

On 22 April 2017 at 20:21, Dave Airlie  wrote:
> On 22 April 2017 at 20:13, Mauro Rossi  wrote:
>> Fixes following building errors due to missing include paths:
>>
>> external/mesa/src/amd/common/ac_shader_info.c:23:10: fatal error: 
>> 'nir/nir.h' file not found
>> #include "nir/nir.h"
>>  ^
>>
>> external/mesa/src/compiler/nir/nir.h:48:10: fatal error: 'nir_opcodes.h' 
>> file not found
>> #include "nir_opcodes.h"
>>  ^
>>
>> Fixes: 224cf29 "radv/ac: add initial pre-pass for shader info gathering"
>
> Acked-by: Dave Airlie 
>
and pushed to master. Thanks gents.

-Emil
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Re: [Mesa-dev] Anti-aliasing problem using OSMesa

[Cherniak, Bruce]

> 
> On Apr 24, 2017, at 10:16 AM, Brian Paul  wrote:
> 
> On 04/21/2017 12:25 AM, green we wrote:
>> I tried to use OSMesa to do offscreen rendering, refer to the osdemo and
>> the tutorial here: http://www.alecjacobson.com/weblog/?p=2827
>> There are obvious serrations on the edge of the model.
>>  I have tried these solution but all failed, can any one gieve me some
>> suggestions? the solution I have tried:
>> 1. Using post processing -- pp_jimenezmlaa
>> the result is not good enough.
>> 
>> 2. Try to using MSAA by FBO, but the multisamled fbo can't be created
>> correctly.
>>   Detail desctription here:
>> http://stackoverflow.com/questions/43532454/osmesa-gl-framebuffer-incomplete-attachment-error-when-create-a-multisampling-fb
> 
> I'm not 100% sure, but I think the Intel "swr" render works with OSMesa and 
> supports MSAA.  That would be the only software driver that would possibly 
> support AA FBOs.

Thanks Brian, you are correct, OpenSWR “swr” does support MSAA and OSMesa.  I 
haven't had opportunity to try them together yet, but this is a mode we will 
definitely support.  MSAA support is something that we added very recently and 
is available in both mesa-master and the 17.1 release branch.  It is disabled 
by default, but you can enable it by exporting “SWR_MSAA_MAX_COUNT=4” 
(1,2,4,8,16 are acceptable).

I’ll be happy to assist if you run into trouble.

>> 
>> 3. Try to modify the sampling function in mesa, according the thread:
>> https://sourceforge.net/p/mesa3d/mailman/message/24438334/ ,  set the
>> stop = 16 and add exit(__LINE__) in the function.
>> but it seems the function is not used anymore.
> 
> It's used, but only by the "legacy" swrast driver, not the llvmpipe, softpipe 
> or swr drivers.  In any case glEnable(GL_POLYGON_SMOOTH) is not a great 
> approach to AA.  And we don't support it with any gallium driver.
> 
> I suspect you're using either softpipe or llvmpipe.  You could try swr by 
> setting GALLIUM_DRIVER=swr, if you build the swr driver.
> 
> -Brian
> 
>> 
>> The mesa swrast AA triangle code is in src/mesa/swrast/s_aatriangle.c
>> and s_aatritemp.h
>> The compute_coverage() functions (different versions for RGB vs. CI
>> mode) basically count how many sub-pixel samples lie inside the
>> triangle for each pixel.  A jittered 4x4 sample pattern is used.  You
>> could probably increase the number of samples to improve AA quality a
>> little.
>> -Brian
>> 
>> Thanks!
>> 
>> wegat...@hotmail.com
>> 
>> 
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>> 
> 
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Re: [Mesa-dev] [PATCH 02/21] anv/cmd_buffer: Use the device allocator for QueueSubmit

[Chad Versace]

On Fri 14 Apr 2017, Jason Ekstrand wrote:
> The command is really operating on a Queue not a command buffer and the
> nearest object to that with an allocator is VkDevice.
> 
> Cc: "17.0" 
> ---
>  src/intel/vulkan/anv_batch_chain.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Chad Versace 
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Re: [Mesa-dev] [PATCH] Android: fix r300g only build

[Emil Velikov]

Hi Rob,

On 24 April 2017 at 17:46, Rob Herring  wrote:
> If r300g is the only radeon driver built, the Android build fails to
> build:
>
> ninja: error:
> 'out/target/product/linaro_x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_radeon_intermediates/export_includes',
> needed by
> 'out/target/product/linaro_x86_64/obj/SHARED_LIBRARIES/gallium_dri_intermediates/import_includes',
> missing and no known rule to make it
>
> This is because the path to build libmesa_pipe_radeon was only getting
> added for r600g and radeonsi, but the library dependency was added for
> all radeon drivers. As libmesa_pipe_radeon is not needed for r300g, drop
> the library dependency.
>
I think we want to move libmesa_amdgpu_addrlib in a similar way. The
lib is used/required by libmesa_winsys_amdgpu which is a r600/radeonsi
only.
Can you please build test that and send a patch (or even squash here
if you prefer)?

The patch as-is
Acked-by: Emil Velikov 

-Emil
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[Mesa-dev] [PATCH] Android: fix r300g only build

[Rob Herring]

If r300g is the only radeon driver built, the Android build fails to
build:

ninja: error:
'out/target/product/linaro_x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_radeon_intermediates/export_includes',
needed by
'out/target/product/linaro_x86_64/obj/SHARED_LIBRARIES/gallium_dri_intermediates/import_includes',
missing and no known rule to make it

This is because the path to build libmesa_pipe_radeon was only getting
added for r600g and radeonsi, but the library dependency was added for
all radeon drivers. As libmesa_pipe_radeon is not needed for r300g, drop
the library dependency.

Cc: Mauro Rossi 
Signed-off-by: Rob Herring 
---
 src/gallium/targets/dri/Android.mk | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/gallium/targets/dri/Android.mk 
b/src/gallium/targets/dri/Android.mk
index 2385e8bf4f95..39d2b6a8983a 100644
--- a/src/gallium/targets/dri/Android.mk
+++ b/src/gallium/targets/dri/Android.mk
@@ -52,23 +52,25 @@ gallium_DRIVERS +=  libmesa_winsys_nouveau 
libmesa_pipe_nouveau
 LOCAL_CFLAGS += -DGALLIUM_NOUVEAU
 LOCAL_SHARED_LIBRARIES += libdrm_nouveau
 endif
+
 ifneq ($(filter r%,$(MESA_GPU_DRIVERS)),)
 ifneq ($(filter r300g,$(MESA_GPU_DRIVERS)),)
 gallium_DRIVERS += libmesa_pipe_r300
 LOCAL_CFLAGS += -DGALLIUM_R300
 endif
 ifneq ($(filter r600g,$(MESA_GPU_DRIVERS)),)
-gallium_DRIVERS += libmesa_pipe_r600
+gallium_DRIVERS += libmesa_pipe_r600 libmesa_pipe_radeon
 LOCAL_CFLAGS += -DGALLIUM_R600
 endif
 ifneq ($(filter radeonsi,$(MESA_GPU_DRIVERS)),)
-gallium_DRIVERS += libmesa_pipe_radeonsi libmesa_winsys_amdgpu 
libmesa_amd_common
+gallium_DRIVERS += libmesa_pipe_radeonsi libmesa_winsys_amdgpu 
libmesa_amd_common libmesa_pipe_radeon
 LOCAL_SHARED_LIBRARIES += libLLVM libdrm_amdgpu
 LOCAL_CFLAGS += -DGALLIUM_RADEONSI
 endif
-gallium_DRIVERS += libmesa_winsys_radeon libmesa_pipe_radeon 
libmesa_amdgpu_addrlib
+gallium_DRIVERS += libmesa_winsys_radeon libmesa_amdgpu_addrlib
 LOCAL_SHARED_LIBRARIES += libdrm_radeon
 endif
+
 ifneq ($(filter swrast,$(MESA_GPU_DRIVERS)),)
 gallium_DRIVERS += libmesa_pipe_softpipe libmesa_winsys_sw_dri
 LOCAL_CFLAGS += -DGALLIUM_SOFTPIPE
-- 
2.11.0

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Re: [Mesa-dev] [PATCH 2/2] radeonsi: disable primitive restart for non-strip prims based on app list

[Nicolai Hähnle]

On 24.04.2017 18:32, Marek Olšák wrote:

On Mon, Apr 24, 2017 at 5:34 PM, Nicolai Hähnle  wrote:

On 24.04.2017 15:22, Marek Olšák wrote:


From: Marek Olšák 



I don't like it. This kind of app-specific override is what drirc was meant
to provide. Having separate places for it is confusing.


The question is: would other drivers want this code in st_draw_vbo?
For threaded gallium, we shouldn't put more stuff into st_draw_vbo.

Alternatively, it can be a flag for pipe_screen::context_create to
enable this behavior in radeonsi and keep the list in drirc.


Is there a particular reason we can't let radeonsi (and other gallium 
drivers) access drirc directly?


Cheers,
Nicolai



Marek




--
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.
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Re: [Mesa-dev] [RFC 00/10] WIP: NIR soft fp64 for ARB_gpu_shader_fp64 on gen6

[tournier.elie]

Hi list,

I'm still interested by a review or some comments/ideas to help me
land this series.
I'm trying to figure out why mul/div and add/sub fail the piglit test.
I already investigated about using "nir_ushr" instead of "nir_ishr". I
also checked if the "nir_bcsel" were done correctly. Without success.

Two sets of eyes and ears are better than one. ;)

Thx


On 12 April 2017 at 23:43, Elie Tournier  wrote:
> I've got this series on my laptop for too long so I send it even if it's 
> still in progress.
> The goal of this work is to enable ARB_gpu_shader_fp64 on gen6.
> Most of the algorithms come from "Berkeley SoftFloat" [1].
> You can find a branch on my github [2].
>
> So far we have:
> Patches 1-5 seems to do the job correctly.
> Patches 6-9 fail the Piglit tests but we handle zero, inf and NaN with 
> success.
> Some tests pass if I increase the tolerance.
>
> All comments and suggestions are very welcome.
>
> [1] http://www.jhauser.us/arithmetic/SoftFloat.html
> [2] https://github.com/Hopetech/mesa/tree/nir_arb_gpu_shader_fp64
>
> Elie Tournier (10):
>   nir/lower_double_ops: lower abs()
>   nir/lower_double_ops: lower neg()
>   nir/lower_double_ops: lower sign()
>   nir/lower_double_ops: lower eq()
>   nir/lower_double_ops: lower lt()
>   nir/lower_double_ops: lower mul()
>   nir/lower_double_ops: lower div()
>   nir/lower_double_ops: lower add()
>   nir/lower_double_ops: lower sub()
>   mesa: enable ARB_gpu_shader_fp64 on Gen6
>
>  src/compiler/nir/nir.h   |   11 +-
>  src/compiler/nir/nir_lower_double_ops.c  | 1713 
> ++
>  src/intel/compiler/brw_nir.c |   11 +-
>  src/mesa/drivers/dri/i965/intel_extensions.c |1 +
>  4 files changed, 1734 insertions(+), 2 deletions(-)
>
> --
> 2.11.0
>
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Re: [Mesa-dev] [PATCH 2/2] radeonsi: disable primitive restart for non-strip prims based on app list

[Marek Olšák]

On Mon, Apr 24, 2017 at 5:34 PM, Nicolai Hähnle  wrote:
> On 24.04.2017 15:22, Marek Olšák wrote:
>>
>> From: Marek Olšák 
>
>
> I don't like it. This kind of app-specific override is what drirc was meant
> to provide. Having separate places for it is confusing.

The question is: would other drivers want this code in st_draw_vbo?
For threaded gallium, we shouldn't put more stuff into st_draw_vbo.

Alternatively, it can be a flag for pipe_screen::context_create to
enable this behavior in radeonsi and keep the list in drirc.

Marek
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[Mesa-dev] [PATCH] docs: add release calendar page and references to it

[Emil Velikov]

From: Emil Velikov 

Add a page that has information which release is expected when and
associated information.

Reference to it from the "Releasing process" and "Release notes" pages.

Cc: Andres Gomez 
Signed-off-by: Emil Velikov 
---
 docs/contents.html |   1 +
 docs/release-calendar.html | 102 +
 docs/releasing.html|   3 ++
 docs/relnotes/17.0.4.html  |   7 
 docs/relnotes/17.1.0.html  |   3 +-
 5 files changed, 115 insertions(+), 1 deletion(-)
 create mode 100644 docs/release-calendar.html

diff --git a/docs/contents.html b/docs/contents.html
index 90a1a00dea0..d5455421091 100644
--- a/docs/contents.html
+++ b/docs/contents.html
@@ -84,6 +84,7 @@
 Coding Style
 Submitting patches
 Releasing process
+Release calendar
 Source Documentation
 GL Dispatch
 
diff --git a/docs/release-calendar.html b/docs/release-calendar.html
new file mode 100644
index 000..caaf753c9e2
--- /dev/null
+++ b/docs/release-calendar.html
@@ -0,0 +1,102 @@
+http://www.w3.org/TR/html4/loose.dtd;>
+
+
+  
+  Releasing process
+  
+
+
+
+
+  The Mesa 3D Graphics Library
+
+
+
+
+
+Overview
+
+
+Mesa provides feature/development and stable releases.
+
+
+The table below lists the date and release manager that is expected to do the
+specific release.
+
+Take a look here
+if you'd like to nominate a patch in the next stable release.
+
+
+Calendar
+
+
+
+
+Mesa version
+Release date
+Release manager
+Notes
+
+
+development
+stable
+
+
+
+17.0.5
+2017-04-28
+Emil Velikov
+
+
+
+17.1.0-rc3
+
+2017-04-28
+Emil Velikov
+
+
+
+17.1.0-rc4
+
+2017-05-05
+Emil Velikov
+May be promoted to 17.1.0 final
+
+
+
+17.0.6
+2017-05-12
+Emil Velikov
+
+
+
+17.1.1
+2017-05-19
+Emil Velikov
+
+
+
+17.0.7
+2017-05-26
+Emil Velikov
+Final planned release for the 17.0 series
+
+
+
+17.1.2
+2017-06-02
+Emil Velikov
+
+
+
+
+17.1.3
+2017-06-16
+Emil Velikov
+
+
+
+
+
+
+
diff --git a/docs/releasing.html b/docs/releasing.html
index fc7f2a5aff9..15df022e5f6 100644
--- a/docs/releasing.html
+++ b/docs/releasing.html
@@ -53,6 +53,9 @@ For example:
 
 Releases should happen on Fridays. Delays can occur although those should be 
keep
 to a minimum.
+
+See our calendar for the
+date and other details for individual releases.
 
 
 Feature releases
diff --git a/docs/relnotes/17.0.4.html b/docs/relnotes/17.0.4.html
index 2e2ca9ba649..16629d1bacc 100644
--- a/docs/relnotes/17.0.4.html
+++ b/docs/relnotes/17.0.4.html
@@ -36,6 +36,13 @@ 
c4c34ba05d48f76b45bc05bc4b6e9242077f403d63c4f0c355c7b07786de233e  mesa-17.0.4.ta
 
 
 
+Next release
+
+Mesa 17.0.5 is expected in approximatelly two weeks. See the release
+calendar
+for details.
+
+
 New features
 None
 
diff --git a/docs/relnotes/17.1.0.html b/docs/relnotes/17.1.0.html
index e7cfe38fac4..4f89c56ffe6 100644
--- a/docs/relnotes/17.1.0.html
+++ b/docs/relnotes/17.1.0.html
@@ -19,7 +19,8 @@
 
 Mesa 17.1.0 is a new development release.
 People who are concerned with stability and reliability should stick
-with a previous release or wait for Mesa 17.1.1.
+with a previous release or wait for
+Mesa 17.1.1.
 
 
 Mesa 17.1.0 implements the OpenGL 4.5 API, but the version reported by
-- 
2.12.2

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