Re: [Mesa-dev] [PATCH 04/11] gallium: Use Array._DrawVAO in st_atom_array.c.
Hi Marek, On Tuesday, 10 April 2018 20:09:06 CEST Marek Olšák wrote: > Generally, if you have to loop over all arrays to find common vertex > buffers, it's better not to do it. The default separate path is going to > perform best, because it's straightforward and interleaved arrays are super > rare. Yes, I know. All the cleanup I did recently is to get rid of all these kind of loops and if needed make them as cheap as possible. best Mathias ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: rename api_validate.{c, h} -> draw_validate.{c, h}
Good Morning,
I was thinking to also basically 'move' vbo/vbo_exec_array.c to main/draw.c as
drawing arrays is today largely independent of the vbo module. Its more the
other way round that the vbo module utilizes the draw code path one notch
below the opengl entry points (... validate, set the Array._DrawVAO 'state'
and execute a draw). By that, the api_validate stuff would have fit into that
potential new main/draw.c.
Brian what do you think?
Anyhow, if we want, we can do this as a followup to all of the VAO cleanup and
on top of this patch, so for this one:
Reviewed-by: Mathias Fröhlich
best
Mathias
On Monday, 23 April 2018 05:47:24 CEST Timothy Arceri wrote:
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65422
> ---
> src/mesa/Makefile.sources | 4 ++--
> src/mesa/main/dlist.c | 2 +-
> src/mesa/main/{api_validate.c => draw_validate.c} | 2 +-
> src/mesa/main/{api_validate.h => draw_validate.h} | 0
> src/mesa/main/drawpix.c | 2 +-
> src/mesa/meson.build | 4 ++--
> src/mesa/vbo/vbo_exec_api.c | 2 +-
> src/mesa/vbo/vbo_exec_array.c | 2 +-
> src/mesa/vbo/vbo_save_api.c | 2 +-
> 9 files changed, 10 insertions(+), 10 deletions(-)
> rename src/mesa/main/{api_validate.c => draw_validate.c} (99%)
> rename src/mesa/main/{api_validate.h => draw_validate.h} (100%)
>
> diff --git a/src/mesa/Makefile.sources b/src/mesa/Makefile.sources
> index c1220b9edc1..08c43195901 100644
> --- a/src/mesa/Makefile.sources
> +++ b/src/mesa/Makefile.sources
> @@ -14,8 +14,6 @@ MAIN_FILES = \
> main/api_exec.h \
> main/api_loopback.c \
> main/api_loopback.h \
> - main/api_validate.c \
> - main/api_validate.h \
> main/arbprogram.c \
> main/arbprogram.h \
> main/arrayobj.c \
> @@ -70,6 +68,8 @@ MAIN_FILES = \
> main/drawpix.h \
> main/drawtex.c \
> main/drawtex.h \
> + main/draw_validate.c \
> + main/draw_validate.h \
> main/enable.c \
> main/enable.h \
> main/enums.c \
> diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
> index 2086611aa39..1b003c81a64 100644
> --- a/src/mesa/main/dlist.c
> +++ b/src/mesa/main/dlist.c
> @@ -35,7 +35,7 @@
> #include "api_arrayelt.h"
> #include "api_exec.h"
> #include "api_loopback.h"
> -#include "api_validate.h"
> +#include "draw_validate.h"
> #include "atifragshader.h"
> #include "config.h"
> #include "bufferobj.h"
> diff --git a/src/mesa/main/api_validate.c b/src/mesa/main/draw_validate.c
> similarity index 99%
> rename from src/mesa/main/api_validate.c
> rename to src/mesa/main/draw_validate.c
> index 7b91fdff55f..bcb2d91306e 100644
> --- a/src/mesa/main/api_validate.c
> +++ b/src/mesa/main/draw_validate.c
> @@ -24,7 +24,7 @@
>
> #include
> #include "glheader.h"
> -#include "api_validate.h"
> +#include "draw_validate.h"
> #include "arrayobj.h"
> #include "bufferobj.h"
> #include "context.h"
> diff --git a/src/mesa/main/api_validate.h b/src/mesa/main/draw_validate.h
> similarity index 100%
> rename from src/mesa/main/api_validate.h
> rename to src/mesa/main/draw_validate.h
> diff --git a/src/mesa/main/drawpix.c b/src/mesa/main/drawpix.c
> index 4bf14fc4f28..2f55dde7b80 100644
> --- a/src/mesa/main/drawpix.c
> +++ b/src/mesa/main/drawpix.c
> @@ -24,7 +24,7 @@
>
> #include "glheader.h"
> #include "imports.h"
> -#include "api_validate.h"
> +#include "draw_validate.h"
> #include "bufferobj.h"
> #include "context.h"
> #include "drawpix.h"
> diff --git a/src/mesa/meson.build b/src/mesa/meson.build
> index 93d197e12ac..3259956ad0b 100644
> --- a/src/mesa/meson.build
> +++ b/src/mesa/meson.build
> @@ -63,8 +63,6 @@ files_libmesa_common = files(
>'main/api_exec.h',
>'main/api_loopback.c',
>'main/api_loopback.h',
> - 'main/api_validate.c',
> - 'main/api_validate.h',
>'main/arbprogram.c',
>'main/arbprogram.h',
>'main/arrayobj.c',
> @@ -119,6 +117,8 @@ files_libmesa_common = files(
>'main/drawpix.h',
>'main/drawtex.c',
>'main/drawtex.h',
> + 'main/draw_validate.c',
> + 'main/draw_validate.h',
>'main/enable.c',
>'main/enable.h',
>'main/enums.h',
> diff --git a/src/mesa/vbo/vbo_exec_api.c b/src/mesa/vbo/vbo_exec_api.c
> index b3971715b57..20148acce32 100644
> --- a/src/mesa/vbo/vbo_exec_api.c
> +++ b/src/mesa/vbo/vbo_exec_api.c
> @@ -40,7 +40,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
> #include "main/state.h"
> #include "main/light.h"
> #include "main/api_arrayelt.h"
> -#include "main/api_validate.h"
> +#include "main/draw_validate.h"
> #include "main/dispatch.h"
> #include "util/bitscan.h"
>
> diff --git a/src/mesa/vbo/vbo_exec_array.c b/src/mesa/vbo/vbo_exec_array.c
> index b3ce138a09e..e74e1bd458c 100644
> --- a/src/mesa/vbo/vbo_exec_array.c
> +++ b/src/mesa/vbo/vbo_exec_array.c
> @@ -31,7 +31,7 @@
> #include "main/glheader.h"
> #
[Mesa-dev] [PATCH 4/4] gallivm: dump bitcode before optimization
From: Roland Scheidegger
If we dump the bitcode for off-line debug purposes, we really want the
pre-optimized bitcode, otherwise it's useless in identifying problems
with IR optimization (if you have a shader which takes an hour to do
IR optimization, it's also nice you don't have to wait that hour...).
Also, print out the function passes for opt which correspond to what
was used for jit compilation (and also the opt level for codegen).
Using opt/llc this way should then pretty much mimic what was done
for jit. (When specifying something like -time-passes
-debug-pass=[Structure|Arguments] (for either opt or llc) that also
gives very useful information in which passes all the time was spent,
and which passes are really run along with the order - llvm will add
passes due to dependencies on its own, and of course -O2 for llc
comes with a ~100 pass list.)
---
src/gallium/auxiliary/gallivm/lp_bld_init.c | 35 +
1 file changed, 21 insertions(+), 14 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c
b/src/gallium/auxiliary/gallivm/lp_bld_init.c
index d0afff1..41d828c 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c
@@ -142,6 +142,10 @@ create_pass_manager(struct gallivm_state *gallivm)
* TODO: Evaluate passes some more - keeping in mind
* both quality of generated code and compile times.
*/
+ /*
+ * NOTE: if you change this, don't forget to change the output
+ * with GALLIVM_DEBUG_DUMP_BC in gallivm_compile_module.
+ */
LLVMAddScalarReplAggregatesPass(gallivm->passmgr);
LLVMAddEarlyCSEPass(gallivm->passmgr);
LLVMAddCFGSimplificationPass(gallivm->passmgr);
@@ -151,7 +155,7 @@ create_pass_manager(struct gallivm_state *gallivm)
* due to licm implying lcssa (since llvm 3.5), which can take forever.
* Even for sane shaders, the cost of licm is rather high (and not just
* due to lcssa, licm itself too), though mostly only in cases when it
- * can actually move things, so having to disable it is a pity.
+ * can actually move things, so having to disable it is a pity.
* LLVMAddLICMPass(gallivm->passmgr);
*/
LLVMAddReassociatePass(gallivm->passmgr);
@@ -597,6 +601,22 @@ gallivm_compile_module(struct gallivm_state *gallivm)
gallivm->builder = NULL;
}
+ /* Dump bitcode to a file */
+ if (gallivm_debug & GALLIVM_DEBUG_DUMP_BC) {
+ char filename[256];
+ assert(gallivm->module_name);
+ util_snprintf(filename, sizeof(filename), "ir_%s.bc",
gallivm->module_name);
+ LLVMWriteBitcodeToFile(gallivm->module, filename);
+ debug_printf("%s written\n", filename);
+ debug_printf("Invoke as \"opt %s %s | llc -O%d %s%s\"\n",
+ gallivm_debug & GALLIVM_DEBUG_NO_OPT ? "-mem2reg" :
+ "-sroa -early-cse -simplifycfg -reassociate "
+ "-mem2reg -constprop -instcombine -gvn",
+ filename, gallivm_debug & GALLIVM_DEBUG_NO_OPT ? 0 : 2,
+ (HAVE_LLVM >= 0x0305) ? "[-mcpu=<-mcpu option>] " : "",
+ "[-mattr=<-mattr option(s)>]");
+ }
+
if (gallivm_debug & GALLIVM_DEBUG_PERF)
time_begin = os_time_get();
@@ -630,19 +650,6 @@ gallivm_compile_module(struct gallivm_state *gallivm)
gallivm->module_name, time_msec);
}
- /* Dump byte code to a file */
- if (gallivm_debug & GALLIVM_DEBUG_DUMP_BC) {
- char filename[256];
- assert(gallivm->module_name);
- util_snprintf(filename, sizeof(filename), "ir_%s.bc",
gallivm->module_name);
- LLVMWriteBitcodeToFile(gallivm->module, filename);
- debug_printf("%s written\n", filename);
- debug_printf("Invoke as \"llc %s%s -o - %s\"\n",
- (HAVE_LLVM >= 0x0305) ? "[-mcpu=<-mcpu option>] " : "",
- "[-mattr=<-mattr option(s)>]",
- filename);
- }
-
if (use_mcjit) {
/* Setting the module's DataLayout to an empty string will cause the
* ExecutionEngine to copy to the DataLayout string from its target
--
2.7.4
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[Mesa-dev] [PATCH 3/4] gallivm: (trivial) do division by 1000 with int64
From: Roland Scheidegger
Conversion to int can otherwise overflow if compile times are over
~71min. (Yes this can happen...)
---
src/gallium/auxiliary/gallivm/lp_bld_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c
b/src/gallium/auxiliary/gallivm/lp_bld_init.c
index abca624..d0afff1 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c
@@ -624,7 +624,7 @@ gallivm_compile_module(struct gallivm_state *gallivm)
if (gallivm_debug & GALLIVM_DEBUG_PERF) {
int64_t time_end = os_time_get();
- int time_msec = (int)(time_end - time_begin) / 1000;
+ int time_msec = (int)((time_end - time_begin) / 1000);
assert(gallivm->module_name);
debug_printf("optimizing module %s took %d msec\n",
gallivm->module_name, time_msec);
--
2.7.4
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[Mesa-dev] [PATCH 2/4] gallivm: remove LICM pass
From: Roland Scheidegger LICM is simply too expensive, even though it presumably can help quite a bit in some cases. It was definitely cheaper in llvm 3.3, though as far as I can tell with llvm 3.3 it failed to do anything in most cases. early-cse also actually seems to cause licm to be able to move things when it previously couldn't, which causes noticeable compile time increases. There's more loop passes in llvm, but I'm not sure which ones are helpful, and I couldn't find anything which would roughly do what the old licm in llvm 3.3 did, so ditch it. --- src/gallium/auxiliary/gallivm/lp_bld_init.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c index 05a74a0..abca624 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_init.c +++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c @@ -145,7 +145,15 @@ create_pass_manager(struct gallivm_state *gallivm) LLVMAddScalarReplAggregatesPass(gallivm->passmgr); LLVMAddEarlyCSEPass(gallivm->passmgr); LLVMAddCFGSimplificationPass(gallivm->passmgr); - LLVMAddLICMPass(gallivm->passmgr); + /* + * FIXME: LICM is potentially quite useful. However, for some + * rather crazy shaders the compile time can reach _hours_ per shader, + * due to licm implying lcssa (since llvm 3.5), which can take forever. + * Even for sane shaders, the cost of licm is rather high (and not just + * due to lcssa, licm itself too), though mostly only in cases when it + * can actually move things, so having to disable it is a pity. + * LLVMAddLICMPass(gallivm->passmgr); + */ LLVMAddReassociatePass(gallivm->passmgr); LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr); LLVMAddConstantPropagationPass(gallivm->passmgr); -- 2.7.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/4] gallivm: add early cse pass
From: Roland Scheidegger
This pass is quite cheap, and can simplify the IR quite a bit for our
generated IR.
In particular on a variety of shaders I've found the time saved by
other passes due to the simplified IR more than makes up for the cost
of this pass, and on top of that the end result is actually better.
The only downside I've found is this enables the LICM pass to move some
things out of the main shader loop (in the case I've seen, instanced
vertex fetch (which is constant within the jit shader) plus the derived
instructions in the shader) which it couldn't do before for some reason.
This would actually be desirable but can increase compile time
considerably (licm seems to have considerable cost when it actually can
move things out of loops, due to alias analysis). But blaming early cse
for this seems inappropriate. (Note that the first two sroa / earlycse
passes are similar to what a standard llvm opt -O1/-O2 pipeline would
do, albeit this has some more passes even before but I don't think
they'd do much for us.)
It also in particular helps some crazy shader used for driver
verification (don't ask...) a lot (about factor of 6 faster in compile
time) (due to simplfiying the ir before LICM is run).
While here, also move licm behind simplifycfg. For some shaders there
seems to be very significant compile time gains (we've seen a factor
of 1 albeit that was a really crazy shader you'd certainly never
see in a real app), beause LICM is quite expensive and there's cases
where running simplifycfg (along with sroa and early-cse) before licm
reduces IR complexity significantly. (I'm not entirely sure if it would
make sense to also run it afterwards.)
---
src/gallium/auxiliary/gallivm/lp_bld_init.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c
b/src/gallium/auxiliary/gallivm/lp_bld_init.c
index ea5489b..05a74a0 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c
@@ -138,13 +138,14 @@ create_pass_manager(struct gallivm_state *gallivm)
}
if ((gallivm_debug & GALLIVM_DEBUG_NO_OPT) == 0) {
- /* These are the passes currently listed in llvm-c/Transforms/Scalar.h,
- * but there are more on SVN.
- * TODO: Add more passes.
+ /*
+ * TODO: Evaluate passes some more - keeping in mind
+ * both quality of generated code and compile times.
*/
LLVMAddScalarReplAggregatesPass(gallivm->passmgr);
- LLVMAddLICMPass(gallivm->passmgr);
+ LLVMAddEarlyCSEPass(gallivm->passmgr);
LLVMAddCFGSimplificationPass(gallivm->passmgr);
+ LLVMAddLICMPass(gallivm->passmgr);
LLVMAddReassociatePass(gallivm->passmgr);
LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr);
LLVMAddConstantPropagationPass(gallivm->passmgr);
--
2.7.4
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[Mesa-dev] [Bug 76694] Inconsistent behaviour of LIBGL_DEBUG
https://bugs.freedesktop.org/show_bug.cgi?id=76694 Timothy Arceri changed: What|Removed |Added Resolution|--- |NOTABUG Status|NEW |RESOLVED --- Comment #1 from Timothy Arceri --- I'm not sure what you want here, so I'm going to close this bug report. If you think it should work differently please send a patch to the list for discussion. Thanks. -- You are receiving this mail because: You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] mesa: rename api_validate.{c, h} -> draw_validate.{c, h}
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65422
---
src/mesa/Makefile.sources | 4 ++--
src/mesa/main/dlist.c | 2 +-
src/mesa/main/{api_validate.c => draw_validate.c} | 2 +-
src/mesa/main/{api_validate.h => draw_validate.h} | 0
src/mesa/main/drawpix.c | 2 +-
src/mesa/meson.build | 4 ++--
src/mesa/vbo/vbo_exec_api.c | 2 +-
src/mesa/vbo/vbo_exec_array.c | 2 +-
src/mesa/vbo/vbo_save_api.c | 2 +-
9 files changed, 10 insertions(+), 10 deletions(-)
rename src/mesa/main/{api_validate.c => draw_validate.c} (99%)
rename src/mesa/main/{api_validate.h => draw_validate.h} (100%)
diff --git a/src/mesa/Makefile.sources b/src/mesa/Makefile.sources
index c1220b9edc1..08c43195901 100644
--- a/src/mesa/Makefile.sources
+++ b/src/mesa/Makefile.sources
@@ -14,8 +14,6 @@ MAIN_FILES = \
main/api_exec.h \
main/api_loopback.c \
main/api_loopback.h \
- main/api_validate.c \
- main/api_validate.h \
main/arbprogram.c \
main/arbprogram.h \
main/arrayobj.c \
@@ -70,6 +68,8 @@ MAIN_FILES = \
main/drawpix.h \
main/drawtex.c \
main/drawtex.h \
+ main/draw_validate.c \
+ main/draw_validate.h \
main/enable.c \
main/enable.h \
main/enums.c \
diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
index 2086611aa39..1b003c81a64 100644
--- a/src/mesa/main/dlist.c
+++ b/src/mesa/main/dlist.c
@@ -35,7 +35,7 @@
#include "api_arrayelt.h"
#include "api_exec.h"
#include "api_loopback.h"
-#include "api_validate.h"
+#include "draw_validate.h"
#include "atifragshader.h"
#include "config.h"
#include "bufferobj.h"
diff --git a/src/mesa/main/api_validate.c b/src/mesa/main/draw_validate.c
similarity index 99%
rename from src/mesa/main/api_validate.c
rename to src/mesa/main/draw_validate.c
index 7b91fdff55f..bcb2d91306e 100644
--- a/src/mesa/main/api_validate.c
+++ b/src/mesa/main/draw_validate.c
@@ -24,7 +24,7 @@
#include
#include "glheader.h"
-#include "api_validate.h"
+#include "draw_validate.h"
#include "arrayobj.h"
#include "bufferobj.h"
#include "context.h"
diff --git a/src/mesa/main/api_validate.h b/src/mesa/main/draw_validate.h
similarity index 100%
rename from src/mesa/main/api_validate.h
rename to src/mesa/main/draw_validate.h
diff --git a/src/mesa/main/drawpix.c b/src/mesa/main/drawpix.c
index 4bf14fc4f28..2f55dde7b80 100644
--- a/src/mesa/main/drawpix.c
+++ b/src/mesa/main/drawpix.c
@@ -24,7 +24,7 @@
#include "glheader.h"
#include "imports.h"
-#include "api_validate.h"
+#include "draw_validate.h"
#include "bufferobj.h"
#include "context.h"
#include "drawpix.h"
diff --git a/src/mesa/meson.build b/src/mesa/meson.build
index 93d197e12ac..3259956ad0b 100644
--- a/src/mesa/meson.build
+++ b/src/mesa/meson.build
@@ -63,8 +63,6 @@ files_libmesa_common = files(
'main/api_exec.h',
'main/api_loopback.c',
'main/api_loopback.h',
- 'main/api_validate.c',
- 'main/api_validate.h',
'main/arbprogram.c',
'main/arbprogram.h',
'main/arrayobj.c',
@@ -119,6 +117,8 @@ files_libmesa_common = files(
'main/drawpix.h',
'main/drawtex.c',
'main/drawtex.h',
+ 'main/draw_validate.c',
+ 'main/draw_validate.h',
'main/enable.c',
'main/enable.h',
'main/enums.h',
diff --git a/src/mesa/vbo/vbo_exec_api.c b/src/mesa/vbo/vbo_exec_api.c
index b3971715b57..20148acce32 100644
--- a/src/mesa/vbo/vbo_exec_api.c
+++ b/src/mesa/vbo/vbo_exec_api.c
@@ -40,7 +40,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "main/state.h"
#include "main/light.h"
#include "main/api_arrayelt.h"
-#include "main/api_validate.h"
+#include "main/draw_validate.h"
#include "main/dispatch.h"
#include "util/bitscan.h"
diff --git a/src/mesa/vbo/vbo_exec_array.c b/src/mesa/vbo/vbo_exec_array.c
index b3ce138a09e..e74e1bd458c 100644
--- a/src/mesa/vbo/vbo_exec_array.c
+++ b/src/mesa/vbo/vbo_exec_array.c
@@ -31,7 +31,7 @@
#include "main/glheader.h"
#include "main/context.h"
#include "main/state.h"
-#include "main/api_validate.h"
+#include "main/draw_validate.h"
#include "main/dispatch.h"
#include "main/varray.h"
#include "main/bufferobj.h"
diff --git a/src/mesa/vbo/vbo_save_api.c b/src/mesa/vbo/vbo_save_api.c
index 71304ede498..3b0c4b77512 100644
--- a/src/mesa/vbo/vbo_save_api.c
+++ b/src/mesa/vbo/vbo_save_api.c
@@ -75,7 +75,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "main/enums.h"
#include "main/eval.h"
#include "main/macros.h"
-#include "main/api_validate.h"
+#include "main/draw_validate.h"
#include "main/api_arrayelt.h"
#include "main/vtxfmt.h"
#include "main/dispatch.h"
--
2.17.0
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[Mesa-dev] [Bug 48837] infinite loop in swrast
https://bugs.freedesktop.org/show_bug.cgi?id=48837 Timothy Arceri changed: What|Removed |Added Component|Mesa core |Drivers/DRI/swrast -- You are receiving this mail because: You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] egl/android: remove flink name support
What's the impact to drm_gralloc?
2018-04-20 5:09 GMT+08:00 Rob Herring :
> Maintaining both flink names and prime fd support which are provided by
> 2 different gralloc implementations is problematic because we have a
> dependency on a specific gralloc implementation header.
>
> This mostly removes the dependency on the gralloc implementation and
> headers. The dependency on GRALLOC_MODULE_PERFORM_GET_DRM_FD remains for
> now, but the definition is added locally to remove the header
> dependency.
>
> Signed-off-by: Rob Herring
> ---
> With this plus Robert's probing patch, we remove any gralloc
> implementation dependency (other than it has to be a pre 1.0
> implementation...).
>
> src/egl/drivers/dri2/egl_dri2.h | 1 -
> src/egl/drivers/dri2/platform_android.c | 172
>
> 2 files changed, 17 insertions(+), 156 deletions(-)
>
> diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
> index cc76c73eab2f..d9e1f466fbeb 100644
> --- a/src/egl/drivers/dri2/egl_dri2.h
> +++ b/src/egl/drivers/dri2/egl_dri2.h
> @@ -61,7 +61,6 @@ struct zwp_linux_dmabuf_v1;
>
> #include
> #include
> -#include
>
> #endif /* HAVE_ANDROID_PLATFORM */
>
> diff --git a/src/egl/drivers/dri2/platform_android.c
> b/src/egl/drivers/dri2/platform_android.c
> index 4f25cb746915..68c85d7f99fa 100644
> --- a/src/egl/drivers/dri2/platform_android.c
> +++ b/src/egl/drivers/dri2/platform_android.c
> @@ -37,7 +37,6 @@
> #include "loader.h"
> #include "egl_dri2.h"
> #include "egl_dri2_fallbacks.h"
> -#include "gralloc_drm.h"
>
> #define ALIGN(val, align) (((val) + (align) - 1) & ~((align) - 1))
>
> @@ -164,12 +163,6 @@ get_native_buffer_fd(struct ANativeWindowBuffer *buf)
> return (handle && handle->numFds) ? handle->data[0] : -1;
> }
>
> -static int
> -get_native_buffer_name(struct ANativeWindowBuffer *buf)
> -{
> - return gralloc_drm_get_gem_handle(buf->handle);
> -}
> -
> static EGLBoolean
> droid_window_dequeue_buffer(struct dri2_egl_surface *dri2_surf)
> {
> @@ -822,50 +815,6 @@ droid_create_image_from_prime_fd(_EGLDisplay *disp,
> _EGLContext *ctx,
> return dri2_create_image_dma_buf(disp, ctx, NULL, attr_list);
> }
>
> -static _EGLImage *
> -droid_create_image_from_name(_EGLDisplay *disp, _EGLContext *ctx,
> - struct ANativeWindowBuffer *buf)
> -{
> - struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
> - struct dri2_egl_image *dri2_img;
> - int name;
> - int format;
> -
> - name = get_native_buffer_name(buf);
> - if (!name) {
> - _eglError(EGL_BAD_PARAMETER, "eglCreateEGLImageKHR");
> - return NULL;
> - }
> -
> - format = get_format(buf->format);
> - if (format == -1)
> - return NULL;
> -
> - dri2_img = calloc(1, sizeof(*dri2_img));
> - if (!dri2_img) {
> - _eglError(EGL_BAD_ALLOC, "droid_create_image_mesa_drm");
> - return NULL;
> - }
> -
> - _eglInitImage(&dri2_img->base, disp);
> -
> - dri2_img->dri_image =
> - dri2_dpy->image->createImageFromName(dri2_dpy->dri_screen,
> - buf->width,
> - buf->height,
> - format,
> - name,
> - buf->stride,
> - dri2_img);
> - if (!dri2_img->dri_image) {
> - free(dri2_img);
> - _eglError(EGL_BAD_ALLOC, "droid_create_image_mesa_drm");
> - return NULL;
> - }
> -
> - return &dri2_img->base;
> -}
> -
> static EGLBoolean
> droid_query_surface(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSurface *surf,
> EGLint attribute, EGLint *value)
> @@ -921,7 +870,7 @@ dri2_create_image_android_native_buffer(_EGLDisplay *disp,
> if (fd >= 0)
>return droid_create_image_from_prime_fd(disp, ctx, buf, fd);
>
> - return droid_create_image_from_name(disp, ctx, buf);
> + return NULL;
> }
>
> static _EGLImage *
> @@ -943,82 +892,6 @@ droid_flush_front_buffer(__DRIdrawable * driDrawable,
> void *loaderPrivate)
> {
> }
>
> -static int
> -droid_get_buffers_parse_attachments(struct dri2_egl_surface *dri2_surf,
> -unsigned int *attachments, int count)
> -{
> - int num_buffers = 0;
> -
> - /* fill dri2_surf->buffers */
> - for (int i = 0; i < count * 2; i += 2) {
> - __DRIbuffer *buf, *local;
> -
> - assert(num_buffers < ARRAY_SIZE(dri2_surf->buffers));
> - buf = &dri2_surf->buffers[num_buffers];
> -
> - switch (attachments[i]) {
> - case __DRI_BUFFER_BACK_LEFT:
> - if (dri2_surf->base.Type == EGL_WINDOW_BIT) {
> -buf->attachment = attachments[i];
> -buf->name = get_native_buffer_name(dri2_surf->buffer);
> -buf->cpp = get_format_bpp(dri2_surf->buffer->format);
> -buf->pitch = dri2_surf->buffer->stride * buf->cpp;
> -
Re: [Mesa-dev] [PATCH 2/2] ac/radv/radeonsi: refactor max simd waves into common code.
Actually as a followup you might want to deduplicate the
wavefrontsPerSimd in radv_device.c too.
On Mon, Apr 23, 2018 at 2:17 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> ---
> src/amd/common/ac_gpu_info.h | 16
> src/amd/vulkan/radv_shader.c | 12 +---
> src/gallium/drivers/radeonsi/si_shader.c | 12 +---
> 3 files changed, 18 insertions(+), 22 deletions(-)
>
> diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
> index 9227ff37799..de566c62fa9 100644
> --- a/src/amd/common/ac_gpu_info.h
> +++ b/src/amd/common/ac_gpu_info.h
> @@ -134,6 +134,22 @@ int ac_get_gs_table_depth(enum chip_class chip_class,
> enum radeon_family family)
> void ac_get_raster_config(struct radeon_info *info,
> uint32_t *raster_config_p,
> uint32_t *raster_config_1_p);
> +
> +static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
> +{
> +
> + switch (family) {
> + /* These always have 8 waves: */
> + case CHIP_POLARIS10:
> + case CHIP_POLARIS11:
> + case CHIP_POLARIS12:
> + case CHIP_VEGAM:
> + return 8;
> + default:
> + return 10;
> + }
> +}
> +
> #ifdef __cplusplus
> }
> #endif
> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
> index 8e8a32f0256..aaa67029755 100644
> --- a/src/amd/vulkan/radv_shader.c
> +++ b/src/amd/vulkan/radv_shader.c
> @@ -615,17 +615,7 @@ generate_shader_stats(struct radv_device *device,
> unsigned max_simd_waves;
> unsigned lds_per_wave = 0;
>
> - switch (device->physical_device->rad_info.family) {
> - /* These always have 8 waves: */
> - case CHIP_POLARIS10:
> - case CHIP_POLARIS11:
> - case CHIP_POLARIS12:
> - case CHIP_VEGAM:
> - max_simd_waves = 8;
> - break;
> - default:
> - max_simd_waves = 10;
> - }
> + max_simd_waves =
> ac_get_max_simd_waves(device->physical_device->rad_info.family);
>
> conf = &variant->config;
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c
> b/src/gallium/drivers/radeonsi/si_shader.c
> index 4eff4f57b97..b866f14623e 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.c
> +++ b/src/gallium/drivers/radeonsi/si_shader.c
> @@ -5459,17 +5459,7 @@ static void si_calculate_max_simd_waves(struct
> si_shader *shader)
> unsigned lds_per_wave = 0;
> unsigned max_simd_waves;
>
> - switch (sscreen->info.family) {
> - /* These always have 8 waves: */
> - case CHIP_POLARIS10:
> - case CHIP_POLARIS11:
> - case CHIP_POLARIS12:
> - case CHIP_VEGAM:
> - max_simd_waves = 8;
> - break;
> - default:
> - max_simd_waves = 10;
> - }
> + max_simd_waves = ac_get_max_simd_waves(sscreen->info.family);
>
> /* Compute LDS usage for PS. */
> switch (shader->selector->type) {
> --
> 2.14.3
>
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Re: [Mesa-dev] [PATCH 5/5] radeonsi: use common gs_table_depth code
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Mon, Apr 23, 2018 at 1:59 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> ---
> src/gallium/drivers/radeonsi/si_pipe.c | 33 ++---
> 1 file changed, 2 insertions(+), 31 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
> b/src/gallium/drivers/radeonsi/si_pipe.c
> index b3ef098b8ea..327dd7c4242 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -661,37 +661,8 @@ static void si_destroy_screen(struct pipe_screen*
> pscreen)
>
> static void si_init_gs_info(struct si_screen *sscreen)
> {
> - /* gs_table_depth is not used by GFX9 */
> - if (sscreen->info.chip_class >= GFX9)
> - return;
> -
> - switch (sscreen->info.family) {
> - case CHIP_OLAND:
> - case CHIP_HAINAN:
> - case CHIP_KAVERI:
> - case CHIP_KABINI:
> - case CHIP_MULLINS:
> - case CHIP_ICELAND:
> - case CHIP_CARRIZO:
> - case CHIP_STONEY:
> - sscreen->gs_table_depth = 16;
> - return;
> - case CHIP_TAHITI:
> - case CHIP_PITCAIRN:
> - case CHIP_VERDE:
> - case CHIP_BONAIRE:
> - case CHIP_HAWAII:
> - case CHIP_TONGA:
> - case CHIP_FIJI:
> - case CHIP_POLARIS10:
> - case CHIP_POLARIS11:
> - case CHIP_POLARIS12:
> - case CHIP_VEGAM:
> - sscreen->gs_table_depth = 32;
> - return;
> - default:
> - unreachable("unknown GPU");
> - }
> + sscreen->gs_table_depth =
> ac_get_gs_table_depth(sscreen->info.chip_class,
> + sscreen->info.family);
> }
>
> static void si_handle_env_var_force_family(struct si_screen *sscreen)
> --
> 2.14.3
>
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Re: [Mesa-dev] [PATCH 2/2] ac/radv/radeonsi: refactor max simd waves into common code.
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Mon, Apr 23, 2018 at 2:17 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> ---
> src/amd/common/ac_gpu_info.h | 16
> src/amd/vulkan/radv_shader.c | 12 +---
> src/gallium/drivers/radeonsi/si_shader.c | 12 +---
> 3 files changed, 18 insertions(+), 22 deletions(-)
>
> diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
> index 9227ff37799..de566c62fa9 100644
> --- a/src/amd/common/ac_gpu_info.h
> +++ b/src/amd/common/ac_gpu_info.h
> @@ -134,6 +134,22 @@ int ac_get_gs_table_depth(enum chip_class chip_class,
> enum radeon_family family)
> void ac_get_raster_config(struct radeon_info *info,
> uint32_t *raster_config_p,
> uint32_t *raster_config_1_p);
> +
> +static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
> +{
> +
> + switch (family) {
> + /* These always have 8 waves: */
> + case CHIP_POLARIS10:
> + case CHIP_POLARIS11:
> + case CHIP_POLARIS12:
> + case CHIP_VEGAM:
> + return 8;
> + default:
> + return 10;
> + }
> +}
> +
> #ifdef __cplusplus
> }
> #endif
> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
> index 8e8a32f0256..aaa67029755 100644
> --- a/src/amd/vulkan/radv_shader.c
> +++ b/src/amd/vulkan/radv_shader.c
> @@ -615,17 +615,7 @@ generate_shader_stats(struct radv_device *device,
> unsigned max_simd_waves;
> unsigned lds_per_wave = 0;
>
> - switch (device->physical_device->rad_info.family) {
> - /* These always have 8 waves: */
> - case CHIP_POLARIS10:
> - case CHIP_POLARIS11:
> - case CHIP_POLARIS12:
> - case CHIP_VEGAM:
> - max_simd_waves = 8;
> - break;
> - default:
> - max_simd_waves = 10;
> - }
> + max_simd_waves =
> ac_get_max_simd_waves(device->physical_device->rad_info.family);
>
> conf = &variant->config;
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c
> b/src/gallium/drivers/radeonsi/si_shader.c
> index 4eff4f57b97..b866f14623e 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.c
> +++ b/src/gallium/drivers/radeonsi/si_shader.c
> @@ -5459,17 +5459,7 @@ static void si_calculate_max_simd_waves(struct
> si_shader *shader)
> unsigned lds_per_wave = 0;
> unsigned max_simd_waves;
>
> - switch (sscreen->info.family) {
> - /* These always have 8 waves: */
> - case CHIP_POLARIS10:
> - case CHIP_POLARIS11:
> - case CHIP_POLARIS12:
> - case CHIP_VEGAM:
> - max_simd_waves = 8;
> - break;
> - default:
> - max_simd_waves = 10;
> - }
> + max_simd_waves = ac_get_max_simd_waves(sscreen->info.family);
>
> /* Compute LDS usage for PS. */
> switch (shader->selector->type) {
> --
> 2.14.3
>
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Re: [Mesa-dev] [PATCH] glsl/glcpp: Handle hex constants with 0X prefix
On 20/04/18 06:08, Vlad Golovkin wrote:
GLSL 4.6 spec describes hex constant as:
hexadecimal-constant:
0x hexadecimal-digit
0X hexadecimal-digit
hexadecimal-constant hexadecimal-digit
Right now if you have a shader with the following structure:
#if 0X1 // or any hex number with the 0X prefix
// some code
#endif
the code between #if and #endif gets removed because the checking is performed
only for "0x" prefix which results in strtoll being called with the base 8 and
after encountering the 'X' char the strtoll returns 0. Letting strtoll detect
the base makes this limitation go away and also makes code easier to read.
The problem is strtoll supports much more than what GLSL allows.
Also added 1 test for uppercase hex prefix.
---
src/compiler/glsl/glcpp/glcpp-parse.y| 9 ++---
src/compiler/glsl/glcpp/tests/149-hex-const-uppercase-prefix.c | 5 +
.../glsl/glcpp/tests/149-hex-const-uppercase-prefix.c.expected | 5 +
3 files changed, 12 insertions(+), 7 deletions(-)
create mode 100644
src/compiler/glsl/glcpp/tests/149-hex-const-uppercase-prefix.c
create mode 100644
src/compiler/glsl/glcpp/tests/149-hex-const-uppercase-prefix.c.expected
diff --git a/src/compiler/glsl/glcpp/glcpp-parse.y
b/src/compiler/glsl/glcpp/glcpp-parse.y
index ccb3aa18d3..d83f99f1c7 100644
--- a/src/compiler/glsl/glcpp/glcpp-parse.y
+++ b/src/compiler/glsl/glcpp/glcpp-parse.y
@@ -462,13 +462,8 @@ control_line_error:
integer_constant:
INTEGER_STRING {
- if (strlen ($1) >= 3 && strncmp ($1, "0x", 2) == 0) {
As per my coment above strtoll supports much more than what GLSL allows.
Please just add strncmp($1, "0X", 2) == 0 to the if above.
That patch would have my r-b. If you send that fixed up patch I can push
it for you. Thanks for looking into this.
- $$ = strtoll ($1 + 2, NULL, 16);
- } else if ($1[0] == '0') {
- $$ = strtoll ($1, NULL, 8);
- } else {
- $$ = strtoll ($1, NULL, 10);
- }
+ /* let strtoll detect the base */
+ $$ = strtoll ($1, NULL, 0);
}
| INTEGER {
$$ = $1;
diff --git a/src/compiler/glsl/glcpp/tests/149-hex-const-uppercase-prefix.c
b/src/compiler/glsl/glcpp/tests/149-hex-const-uppercase-prefix.c
new file mode 100644
index 00..1be9b28eb7
--- /dev/null
+++ b/src/compiler/glsl/glcpp/tests/149-hex-const-uppercase-prefix.c
@@ -0,0 +1,5 @@
+#if 0x1234abcd == 0X1234abcd
+success
+#else
+failure
+#endif
diff --git
a/src/compiler/glsl/glcpp/tests/149-hex-const-uppercase-prefix.c.expected
b/src/compiler/glsl/glcpp/tests/149-hex-const-uppercase-prefix.c.expected
new file mode 100644
index 00..4cf250f6bb
--- /dev/null
+++ b/src/compiler/glsl/glcpp/tests/149-hex-const-uppercase-prefix.c.expected
@@ -0,0 +1,5 @@
+
+success
+
+
+
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Re: [Mesa-dev] [PATCH 2/2] ac/radv/radeonsi: refactor harvest config register getters.
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Mon, Apr 23, 2018 at 2:43 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> This refactors the code out to share it between radv and radeonsi.
> ---
> src/amd/common/ac_gpu_info.c| 113
>
> src/amd/common/ac_gpu_info.h| 4 ++
> src/amd/vulkan/si_cmd_buffer.c | 108 ++
> src/gallium/drivers/radeonsi/si_state.c | 111 ++-
> 4 files changed, 130 insertions(+), 206 deletions(-)
>
> diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
> index 47a87650a6d..031fd183b6f 100644
> --- a/src/amd/common/ac_gpu_info.c
> +++ b/src/amd/common/ac_gpu_info.c
> @@ -647,3 +647,116 @@ ac_get_raster_config(struct radeon_info *info,
> *raster_config_p = raster_config;
> *raster_config_1_p = raster_config_1;
> }
> +
> +void
> +ac_get_harvested_configs(struct radeon_info *info,
> +unsigned raster_config,
> +unsigned *cik_raster_config_1_p,
> +unsigned *raster_config_se)
> +{
> + unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
> + unsigned num_se = MAX2(info->max_se, 1);
> + unsigned rb_mask = info->enabled_rb_mask;
> + unsigned num_rb = MIN2(info->num_render_backends, 16);
> + unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
> + unsigned rb_per_se = num_rb / num_se;
> + unsigned se_mask[4];
> + unsigned se;
> +
> + se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
> + se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
> + se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
> + se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
> +
> + assert(num_se == 1 || num_se == 2 || num_se == 4);
> + assert(sh_per_se == 1 || sh_per_se == 2);
> + assert(rb_per_pkr == 1 || rb_per_pkr == 2);
> +
> +
> + if (info->chip_class >= CIK) {
> + unsigned raster_config_1 = *cik_raster_config_1_p;
> + if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
> +(!se_mask[2] && !se_mask[3]))) {
> + raster_config_1 &= C_028354_SE_PAIR_MAP;
> +
> + if (!se_mask[0] && !se_mask[1]) {
> + raster_config_1 |=
> +
> S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
> + } else {
> + raster_config_1 |=
> +
> S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
> + }
> + *cik_raster_config_1_p = raster_config_1;
> + }
> + }
> +
> + for (se = 0; se < num_se; se++) {
> + unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se *
> rb_per_se);
> + unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
> + int idx = (se / 2) * 2;
> +
> + raster_config_se[se] = raster_config;
> + if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
> + raster_config_se[se] &= C_028350_SE_MAP;
> +
> + if (!se_mask[idx]) {
> + raster_config_se[se] |=
> +
> S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
> + } else {
> + raster_config_se[se] |=
> +
> S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
> + }
> + }
> +
> + pkr0_mask &= rb_mask;
> + pkr1_mask &= rb_mask;
> + if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
> + raster_config_se[se] &= C_028350_PKR_MAP;
> +
> + if (!pkr0_mask) {
> + raster_config_se[se] |=
> +
> S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
> + } else {
> + raster_config_se[se] |=
> +
> S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
> + }
> + }
> +
> + if (rb_per_se >= 2) {
> + unsigned rb0_mask = 1 << (se * rb_per_se);
> + unsigned rb1_mask = rb0_mask << 1;
> +
> + rb0_mask &= rb_mask;
> + rb1_mask &= rb_mask;
> + if (!rb0_mask || !rb1_mask) {
> + raster_config_se[se] &= C_028350_RB_MAP_PKR0;
> +
> + if (!rb0_mask) {
> + raster_config_se[se] |=
> +
> S_028350_RB_MAP_PKR0(V_028350_RAST
Re: [Mesa-dev] [PATCH] nir: Do not use progress for unreachable code in return lowering.
On Mon, Apr 23, 2018 at 2:20 AM, Timothy Arceri wrote:
>
>
> On 23/04/18 03:26, Bas Nieuwenhuizen wrote:
>>
>> We seems to use progress for two cases:
>
>
> seems -> seem
>
>> 1) When we lowered some returns.
>> 2) When we remove unreachable code.
>>
>> If just case 2 happens we assert as state->return_flag has not
>> been allocated yet, but we are still trying to do insert all
>> predicates based on it.
>>
>> This splits the concerns. We only use progress internally for case 1
>> and then keep track of 2 in a separate variable to indicate progress
>> in the return value of the pass.
>>
>> This is slightly better than transforming the assert into
>> if (!state->return_flag) return, as it avoids inserting predicates
>
>
> "as it avoids" -> "as that would avoid" ?
No, the solution I am proposing in this patch avoids, not the
alternative solution of this paragraph. I think your proposed change
would point to the latter. I'll clarify it to clearly point to the
former though.
>
>> even if some other part of the code might need them.
>>
>> Fixes: 6e22ad6edc "nir: return early when lowering a return at the end of
>> a function"
>> CC: 18.1
>
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106174
>
> Reviewed-by: Timothy Arceri
>
> Thanks for fixing!
>
>
>> ---
>> src/compiler/nir/nir_lower_returns.c | 7 ++-
>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/compiler/nir/nir_lower_returns.c
>> b/src/compiler/nir/nir_lower_returns.c
>> index 3ea69e2520..9c4881112e 100644
>> --- a/src/compiler/nir/nir_lower_returns.c
>> +++ b/src/compiler/nir/nir_lower_returns.c
>> @@ -37,6 +37,8 @@ struct lower_returns_state {
>> * needs to be predicated on the return flag variable.
>> */
>> bool has_predicated_return;
>> +
>> + bool removed_unreachable_code;
>> };
>> static bool lower_returns_in_cf_list(struct exec_list *cf_list,
>> @@ -162,8 +164,9 @@ lower_returns_in_block(nir_block *block, struct
>> lower_returns_state *state)
>> */
>>return false;
>> } else {
>> + state->removed_unreachable_code = true;
>>nir_cf_delete(&list);
>> - return true;
>> + return false;
>> }
>> }
>> @@ -262,9 +265,11 @@ nir_lower_returns_impl(nir_function_impl *impl)
>> state.loop = NULL;
>> state.return_flag = NULL;
>> state.has_predicated_return = false;
>> + state.removed_unreachable_code = false;
>> nir_builder_init(&state.builder, impl);
>>bool progress = lower_returns_in_cf_list(&impl->body, &state);
>> + progress = progress || state.removed_unreachable_code;
>>if (progress) {
>> nir_metadata_preserve(impl, nir_metadata_none);
>>
>
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[Mesa-dev] [PATCH 2/2] ac/radv/radeonsi: refactor harvest config register getters.
From: Dave Airlie
This refactors the code out to share it between radv and radeonsi.
---
src/amd/common/ac_gpu_info.c| 113
src/amd/common/ac_gpu_info.h| 4 ++
src/amd/vulkan/si_cmd_buffer.c | 108 ++
src/gallium/drivers/radeonsi/si_state.c | 111 ++-
4 files changed, 130 insertions(+), 206 deletions(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 47a87650a6d..031fd183b6f 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -647,3 +647,116 @@ ac_get_raster_config(struct radeon_info *info,
*raster_config_p = raster_config;
*raster_config_1_p = raster_config_1;
}
+
+void
+ac_get_harvested_configs(struct radeon_info *info,
+unsigned raster_config,
+unsigned *cik_raster_config_1_p,
+unsigned *raster_config_se)
+{
+ unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
+ unsigned num_se = MAX2(info->max_se, 1);
+ unsigned rb_mask = info->enabled_rb_mask;
+ unsigned num_rb = MIN2(info->num_render_backends, 16);
+ unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
+ unsigned rb_per_se = num_rb / num_se;
+ unsigned se_mask[4];
+ unsigned se;
+
+ se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
+ se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
+ se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
+ se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
+
+ assert(num_se == 1 || num_se == 2 || num_se == 4);
+ assert(sh_per_se == 1 || sh_per_se == 2);
+ assert(rb_per_pkr == 1 || rb_per_pkr == 2);
+
+
+ if (info->chip_class >= CIK) {
+ unsigned raster_config_1 = *cik_raster_config_1_p;
+ if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
+(!se_mask[2] && !se_mask[3]))) {
+ raster_config_1 &= C_028354_SE_PAIR_MAP;
+
+ if (!se_mask[0] && !se_mask[1]) {
+ raster_config_1 |=
+
S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
+ } else {
+ raster_config_1 |=
+
S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
+ }
+ *cik_raster_config_1_p = raster_config_1;
+ }
+ }
+
+ for (se = 0; se < num_se; se++) {
+ unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se *
rb_per_se);
+ unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
+ int idx = (se / 2) * 2;
+
+ raster_config_se[se] = raster_config;
+ if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
+ raster_config_se[se] &= C_028350_SE_MAP;
+
+ if (!se_mask[idx]) {
+ raster_config_se[se] |=
+
S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
+ } else {
+ raster_config_se[se] |=
+
S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
+ }
+ }
+
+ pkr0_mask &= rb_mask;
+ pkr1_mask &= rb_mask;
+ if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
+ raster_config_se[se] &= C_028350_PKR_MAP;
+
+ if (!pkr0_mask) {
+ raster_config_se[se] |=
+
S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
+ } else {
+ raster_config_se[se] |=
+
S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
+ }
+ }
+
+ if (rb_per_se >= 2) {
+ unsigned rb0_mask = 1 << (se * rb_per_se);
+ unsigned rb1_mask = rb0_mask << 1;
+
+ rb0_mask &= rb_mask;
+ rb1_mask &= rb_mask;
+ if (!rb0_mask || !rb1_mask) {
+ raster_config_se[se] &= C_028350_RB_MAP_PKR0;
+
+ if (!rb0_mask) {
+ raster_config_se[se] |=
+
S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
+ } else {
+ raster_config_se[se] |=
+
S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
+ }
+ }
+
+ if (rb_per_se
[Mesa-dev] [PATCH 1/2] radv: only set raster_config_1 outside the index registers.
From: Dave Airlie
This follows what radeonsi does.
Ported from radeonsi:
radeonsi: emit PA_SC_RASTER_CONFIG_1 only once
---
src/amd/vulkan/si_cmd_buffer.c | 31 ---
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index b7a2ca244bf..2140368c80d 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -63,19 +63,6 @@ si_write_harvested_raster_configs(struct
radv_physical_device *physical_device,
* fields are for, so I'm leaving them as their default
* values. */
- if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
-(!se_mask[2] && !se_mask[3]))) {
- raster_config_1 &= C_028354_SE_PAIR_MAP;
-
- if (!se_mask[0] && !se_mask[1]) {
- raster_config_1 |=
-
S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
- } else {
- raster_config_1 |=
-
S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
- }
- }
-
for (se = 0; se < num_se; se++) {
unsigned raster_config_se = raster_config;
unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se *
rb_per_se);
@@ -156,8 +143,6 @@ si_write_harvested_raster_configs(struct
radv_physical_device *physical_device,
S_030800_SE_INDEX(se) |
S_030800_SH_BROADCAST_WRITES(1) |
S_030800_INSTANCE_BROADCAST_WRITES(1));
radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
raster_config_se);
- if (physical_device->rad_info.chip_class >= CIK)
- radeon_set_context_reg(cs,
R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
}
/* GRBM_GFX_INDEX has a different offset on SI and CI+ */
@@ -170,6 +155,22 @@ si_write_harvested_raster_configs(struct
radv_physical_device *physical_device,
radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
S_030800_SE_BROADCAST_WRITES(1) |
S_030800_SH_BROADCAST_WRITES(1) |
S_030800_INSTANCE_BROADCAST_WRITES(1));
+
+ if (physical_device->rad_info.chip_class >= CIK) {
+ if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
+(!se_mask[2] && !se_mask[3]))) {
+ raster_config_1 &= C_028354_SE_PAIR_MAP;
+
+ if (!se_mask[0] && !se_mask[1]) {
+ raster_config_1 |=
+
S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
+ } else {
+ raster_config_1 |=
+
S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
+ }
+ }
+ radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
raster_config_1);
+ }
}
static void
--
2.14.3
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[Mesa-dev] [Bug 99179] Mesa freezez the pc when running nativ games for linux
https://bugs.freedesktop.org/show_bug.cgi?id=99179 Timothy Arceri changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #11 from Timothy Arceri --- Assuming it was and closing. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 99125] Log to a file all GALLIUM_HUD infos
https://bugs.freedesktop.org/show_bug.cgi?id=99125 Timothy Arceri changed: What|Removed |Added Resolution|--- |FIXED Status|NEW |RESOLVED -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 92877] Add support for libglvnd
https://bugs.freedesktop.org/show_bug.cgi?id=92877 Timothy Arceri changed: What|Removed |Added Resolution|--- |FIXED Status|NEW |RESOLVED --- Comment #12 from Timothy Arceri --- Closing. We can open a new bug if needed for any further work. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] nir: Do not use progress for unreachable code in return lowering.
On 23/04/18 03:26, Bas Nieuwenhuizen wrote:
We seems to use progress for two cases:
seems -> seem
1) When we lowered some returns.
2) When we remove unreachable code.
If just case 2 happens we assert as state->return_flag has not
been allocated yet, but we are still trying to do insert all
predicates based on it.
This splits the concerns. We only use progress internally for case 1
and then keep track of 2 in a separate variable to indicate progress
in the return value of the pass.
This is slightly better than transforming the assert into
if (!state->return_flag) return, as it avoids inserting predicates
"as it avoids" -> "as that would avoid" ?
even if some other part of the code might need them.
Fixes: 6e22ad6edc "nir: return early when lowering a return at the end of a
function"
CC: 18.1
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106174
Reviewed-by: Timothy Arceri
Thanks for fixing!
---
src/compiler/nir/nir_lower_returns.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir_lower_returns.c
b/src/compiler/nir/nir_lower_returns.c
index 3ea69e2520..9c4881112e 100644
--- a/src/compiler/nir/nir_lower_returns.c
+++ b/src/compiler/nir/nir_lower_returns.c
@@ -37,6 +37,8 @@ struct lower_returns_state {
* needs to be predicated on the return flag variable.
*/
bool has_predicated_return;
+
+ bool removed_unreachable_code;
};
static bool lower_returns_in_cf_list(struct exec_list *cf_list,
@@ -162,8 +164,9 @@ lower_returns_in_block(nir_block *block, struct
lower_returns_state *state)
*/
return false;
} else {
+ state->removed_unreachable_code = true;
nir_cf_delete(&list);
- return true;
+ return false;
}
}
@@ -262,9 +265,11 @@ nir_lower_returns_impl(nir_function_impl *impl)
state.loop = NULL;
state.return_flag = NULL;
state.has_predicated_return = false;
+ state.removed_unreachable_code = false;
nir_builder_init(&state.builder, impl);
bool progress = lower_returns_in_cf_list(&impl->body, &state);
+ progress = progress || state.removed_unreachable_code;
if (progress) {
nir_metadata_preserve(impl, nir_metadata_none);
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[Mesa-dev] [PATCH 2/2] ac/radv/radeonsi: refactor max simd waves into common code.
From: Dave Airlie
---
src/amd/common/ac_gpu_info.h | 16
src/amd/vulkan/radv_shader.c | 12 +---
src/gallium/drivers/radeonsi/si_shader.c | 12 +---
3 files changed, 18 insertions(+), 22 deletions(-)
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 9227ff37799..de566c62fa9 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -134,6 +134,22 @@ int ac_get_gs_table_depth(enum chip_class chip_class, enum
radeon_family family)
void ac_get_raster_config(struct radeon_info *info,
uint32_t *raster_config_p,
uint32_t *raster_config_1_p);
+
+static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
+{
+
+ switch (family) {
+ /* These always have 8 waves: */
+ case CHIP_POLARIS10:
+ case CHIP_POLARIS11:
+ case CHIP_POLARIS12:
+ case CHIP_VEGAM:
+ return 8;
+ default:
+ return 10;
+ }
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 8e8a32f0256..aaa67029755 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -615,17 +615,7 @@ generate_shader_stats(struct radv_device *device,
unsigned max_simd_waves;
unsigned lds_per_wave = 0;
- switch (device->physical_device->rad_info.family) {
- /* These always have 8 waves: */
- case CHIP_POLARIS10:
- case CHIP_POLARIS11:
- case CHIP_POLARIS12:
- case CHIP_VEGAM:
- max_simd_waves = 8;
- break;
- default:
- max_simd_waves = 10;
- }
+ max_simd_waves =
ac_get_max_simd_waves(device->physical_device->rad_info.family);
conf = &variant->config;
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 4eff4f57b97..b866f14623e 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -5459,17 +5459,7 @@ static void si_calculate_max_simd_waves(struct si_shader
*shader)
unsigned lds_per_wave = 0;
unsigned max_simd_waves;
- switch (sscreen->info.family) {
- /* These always have 8 waves: */
- case CHIP_POLARIS10:
- case CHIP_POLARIS11:
- case CHIP_POLARIS12:
- case CHIP_VEGAM:
- max_simd_waves = 8;
- break;
- default:
- max_simd_waves = 10;
- }
+ max_simd_waves = ac_get_max_simd_waves(sscreen->info.family);
/* Compute LDS usage for PS. */
switch (shader->selector->type) {
--
2.14.3
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[Mesa-dev] [PATCH 1/2] ac/radv/radeonsi: refactor raster_config default values getters.
From: Dave Airlie
This just makes this common code between the two drivers.
---
src/amd/common/ac_gpu_info.c| 93 +
src/amd/common/ac_gpu_info.h| 4 +-
src/amd/vulkan/si_cmd_buffer.c | 85 ++
src/gallium/drivers/radeonsi/si_state.c | 84 ++---
4 files changed, 102 insertions(+), 164 deletions(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 12b03c4ea29..47a87650a6d 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -554,3 +554,96 @@ ac_get_gs_table_depth(enum chip_class chip_class, enum
radeon_family family)
unreachable("Unknown GPU");
}
}
+
+void
+ac_get_raster_config(struct radeon_info *info,
+uint32_t *raster_config_p,
+uint32_t *raster_config_1_p)
+{
+ unsigned num_rb = MIN2(info->num_render_backends, 16);
+ unsigned raster_config, raster_config_1;
+ switch (info->family) {
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ raster_config = 0x2a00126a;
+ raster_config_1 = 0x;
+ break;
+ case CHIP_VERDE:
+ raster_config = 0x124a;
+ raster_config_1 = 0x;
+ break;
+ case CHIP_OLAND:
+ raster_config = 0x0082;
+ raster_config_1 = 0x;
+ break;
+ case CHIP_HAINAN:
+ raster_config = 0x;
+ raster_config_1 = 0x;
+ break;
+ case CHIP_BONAIRE:
+ raster_config = 0x1612;
+ raster_config_1 = 0x;
+ break;
+ case CHIP_HAWAII:
+ raster_config = 0x3a00161a;
+ raster_config_1 = 0x002e;
+ break;
+ case CHIP_FIJI:
+ if (info->cik_macrotile_mode_array[0] == 0x00e8) {
+ /* old kernels with old tiling config */
+ raster_config = 0x1612;
+ raster_config_1 = 0x002a;
+ } else {
+ raster_config = 0x3a00161a;
+ raster_config_1 = 0x002e;
+ }
+ break;
+ case CHIP_POLARIS10:
+ raster_config = 0x1612;
+ raster_config_1 = 0x002a;
+ break;
+ case CHIP_POLARIS11:
+ case CHIP_POLARIS12:
+ raster_config = 0x1612;
+ raster_config_1 = 0x;
+ break;
+ case CHIP_VEGAM:
+ raster_config = 0x3a00161a;
+ raster_config_1 = 0x002e;
+ break;
+ case CHIP_TONGA:
+ raster_config = 0x1612;
+ raster_config_1 = 0x002a;
+ break;
+ case CHIP_ICELAND:
+ if (num_rb == 1)
+ raster_config = 0x;
+ else
+ raster_config = 0x0002;
+ raster_config_1 = 0x;
+ break;
+ case CHIP_CARRIZO:
+ raster_config = 0x0002;
+ raster_config_1 = 0x;
+ break;
+ case CHIP_KAVERI:
+ /* KV should be 0x0002, but that causes problems with
radeon */
+ raster_config = 0x; /* 0x0002 */
+ raster_config_1 = 0x;
+ break;
+ case CHIP_KABINI:
+ case CHIP_MULLINS:
+ case CHIP_STONEY:
+ raster_config = 0x;
+ raster_config_1 = 0x;
+ break;
+ default:
+ fprintf(stderr,
+ "ac: Unknown GPU, using 0 for raster_config\n");
+ raster_config = 0x;
+ raster_config_1 = 0x;
+ break;
+ }
+ *raster_config_p = raster_config;
+ *raster_config_1_p = raster_config_1;
+}
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 003d340e0c1..9227ff37799 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -131,7 +131,9 @@ void ac_compute_driver_uuid(char *uuid, size_t size);
void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size);
void ac_print_gpu_info(struct radeon_info *info);
int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family
family);
-
+void ac_get_raster_config(struct radeon_info *info,
+ uint32_t *raster_config_p,
+ uint32_t *raster_config_1_p);
#ifdef __cplusplus
}
#endif
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 80c819af49b..b7a2ca244bf 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -234,88 +234,9 @@ si_set_raster_c
[Mesa-dev] [PATCH 3/5] ac/info: move gs table depth to common code.
From: Dave Airlie
---
src/amd/common/ac_gpu_info.c | 33 +
src/amd/common/ac_gpu_info.h | 1 +
2 files changed, 34 insertions(+)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index ef0364b0534..12b03c4ea29 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -521,3 +521,36 @@ void ac_print_gpu_info(struct radeon_info *info)
G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
}
}
+
+int
+ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
+{
+ if (chip_class >= GFX9)
+ return -1;
+
+ switch (family) {
+ case CHIP_OLAND:
+ case CHIP_HAINAN:
+ case CHIP_KAVERI:
+ case CHIP_KABINI:
+ case CHIP_MULLINS:
+ case CHIP_ICELAND:
+ case CHIP_CARRIZO:
+ case CHIP_STONEY:
+ return 16;
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case CHIP_VERDE:
+ case CHIP_BONAIRE:
+ case CHIP_HAWAII:
+ case CHIP_TONGA:
+ case CHIP_FIJI:
+ case CHIP_POLARIS10:
+ case CHIP_POLARIS11:
+ case CHIP_POLARIS12:
+ case CHIP_VEGAM:
+ return 32;
+ default:
+ unreachable("Unknown GPU");
+ }
+}
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 75cb98020d2..003d340e0c1 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -130,6 +130,7 @@ void ac_compute_driver_uuid(char *uuid, size_t size);
void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size);
void ac_print_gpu_info(struct radeon_info *info);
+int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family
family);
#ifdef __cplusplus
}
--
2.14.3
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[Mesa-dev] [PATCH 5/5] radeonsi: use common gs_table_depth code
From: Dave Airlie
---
src/gallium/drivers/radeonsi/si_pipe.c | 33 ++---
1 file changed, 2 insertions(+), 31 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index b3ef098b8ea..327dd7c4242 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -661,37 +661,8 @@ static void si_destroy_screen(struct pipe_screen* pscreen)
static void si_init_gs_info(struct si_screen *sscreen)
{
- /* gs_table_depth is not used by GFX9 */
- if (sscreen->info.chip_class >= GFX9)
- return;
-
- switch (sscreen->info.family) {
- case CHIP_OLAND:
- case CHIP_HAINAN:
- case CHIP_KAVERI:
- case CHIP_KABINI:
- case CHIP_MULLINS:
- case CHIP_ICELAND:
- case CHIP_CARRIZO:
- case CHIP_STONEY:
- sscreen->gs_table_depth = 16;
- return;
- case CHIP_TAHITI:
- case CHIP_PITCAIRN:
- case CHIP_VERDE:
- case CHIP_BONAIRE:
- case CHIP_HAWAII:
- case CHIP_TONGA:
- case CHIP_FIJI:
- case CHIP_POLARIS10:
- case CHIP_POLARIS11:
- case CHIP_POLARIS12:
- case CHIP_VEGAM:
- sscreen->gs_table_depth = 32;
- return;
- default:
- unreachable("unknown GPU");
- }
+ sscreen->gs_table_depth =
ac_get_gs_table_depth(sscreen->info.chip_class,
+ sscreen->info.family);
}
static void si_handle_env_var_force_family(struct si_screen *sscreen)
--
2.14.3
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[Mesa-dev] [PATCH 4/5] radv: use common gs_table_depth code.
From: Dave Airlie
---
src/amd/vulkan/radv_device.c | 32 ++--
1 file changed, 2 insertions(+), 30 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index c687b23f27d..8837d6cafde 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1353,36 +1353,8 @@ static void radv_bo_list_remove(struct radv_device
*device,
static void
radv_device_init_gs_info(struct radv_device *device)
{
- if (device->physical_device->rad_info.chip_class >= GFX9)
- return;
-
- switch (device->physical_device->rad_info.family) {
- case CHIP_OLAND:
- case CHIP_HAINAN:
- case CHIP_KAVERI:
- case CHIP_KABINI:
- case CHIP_MULLINS:
- case CHIP_ICELAND:
- case CHIP_CARRIZO:
- case CHIP_STONEY:
- device->gs_table_depth = 16;
- return;
- case CHIP_TAHITI:
- case CHIP_PITCAIRN:
- case CHIP_VERDE:
- case CHIP_BONAIRE:
- case CHIP_HAWAII:
- case CHIP_TONGA:
- case CHIP_FIJI:
- case CHIP_POLARIS10:
- case CHIP_POLARIS11:
- case CHIP_POLARIS12:
- case CHIP_VEGAM:
- device->gs_table_depth = 32;
- return;
- default:
- unreachable("unknown GPU");
- }
+ device->gs_table_depth =
ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
+
device->physical_device->rad_info.family);
}
static int radv_get_device_extension_index(const char *name)
--
2.14.3
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[Mesa-dev] [PATCH 1/5] radv/gfx9: don't use gs_table_depth on gfx9.
From: Dave Airlie
Missed this on initial radeonsi port, we shouldn't use this value
on gfx9, but also in gfx8 only for when we have a geom shader.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_device.c | 6 +++---
src/amd/vulkan/radv_pipeline.c | 5 +++--
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index d88d5f06422..c687b23f27d 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1353,6 +1353,9 @@ static void radv_bo_list_remove(struct radv_device
*device,
static void
radv_device_init_gs_info(struct radv_device *device)
{
+ if (device->physical_device->rad_info.chip_class >= GFX9)
+ return;
+
switch (device->physical_device->rad_info.family) {
case CHIP_OLAND:
case CHIP_HAINAN:
@@ -1375,9 +1378,6 @@ radv_device_init_gs_info(struct radv_device *device)
case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGAM:
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_RAVEN:
device->gs_table_depth = 32;
return;
default:
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 20afeda4480..b4e4f3211e2 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3206,8 +3206,9 @@ radv_compute_ia_multi_vgt_param_helpers(struct
radv_pipeline *pipeline,
}
}
/* GS requirement. */
- if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >=
pipeline->device->gs_table_depth - 3)
- ia_multi_vgt_param.partial_es_wave = true;
+ if (radv_pipeline_has_gs(pipeline) &&
device->physical_device->rad_info.chip_class <= VI)
+ if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >=
pipeline->device->gs_table_depth - 3)
+ ia_multi_vgt_param.partial_es_wave = true;
ia_multi_vgt_param.wd_switch_on_eop = false;
if (device->physical_device->rad_info.chip_class >= CIK) {
--
2.14.3
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[Mesa-dev] [PATCH 2/5] radeonsi: don't runtime check gs table info
From: Dave Airlie
We can just unreachable here, this aligns with radv code, makes
it easier to move to common code.
---
src/gallium/drivers/radeonsi/si_pipe.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index f2fdb984139..b3ef098b8ea 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -659,11 +659,11 @@ static void si_destroy_screen(struct pipe_screen* pscreen)
FREE(sscreen);
}
-static bool si_init_gs_info(struct si_screen *sscreen)
+static void si_init_gs_info(struct si_screen *sscreen)
{
/* gs_table_depth is not used by GFX9 */
if (sscreen->info.chip_class >= GFX9)
- return true;
+ return;
switch (sscreen->info.family) {
case CHIP_OLAND:
@@ -675,7 +675,7 @@ static bool si_init_gs_info(struct si_screen *sscreen)
case CHIP_CARRIZO:
case CHIP_STONEY:
sscreen->gs_table_depth = 16;
- return true;
+ return;
case CHIP_TAHITI:
case CHIP_PITCAIRN:
case CHIP_VERDE:
@@ -688,9 +688,9 @@ static bool si_init_gs_info(struct si_screen *sscreen)
case CHIP_POLARIS12:
case CHIP_VEGAM:
sscreen->gs_table_depth = 32;
- return true;
+ return;
default:
- return false;
+ unreachable("unknown GPU");
}
}
@@ -853,8 +853,8 @@ struct pipe_screen *radeonsi_screen_create(struct
radeon_winsys *ws,
(void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
(void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
- if (!si_init_gs_info(sscreen) ||
- !si_init_shader_cache(sscreen)) {
+ si_init_gs_info(sscreen);
+ if (!si_init_shader_cache(sscreen)) {
FREE(sscreen);
return NULL;
}
--
2.14.3
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[Mesa-dev] [Bug 106176] [mesa] git master VERSION not increased when 18.1 was branched off
https://bugs.freedesktop.org/show_bug.cgi?id=106176 --- Comment #3 from LoneVVolf --- Thank you for the fast response. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 106180] [bisected] radv vulkan smoke test black screen (Add support for DRI3 v1.2)
https://bugs.freedesktop.org/show_bug.cgi?id=106180 --- Comment #1 from mercuriete --- not sure if i forget to put this: x11-base/xorg-server-1.19.5-r1 x11-base/xorg-drivers-1.19 I think I am using xorg modesetting. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 106180] [bisected] radv vulkan smoke test black screen (Add support for DRI3 v1.2)
https://bugs.freedesktop.org/show_bug.cgi?id=106180 Bug ID: 106180 Summary: [bisected] radv vulkan smoke test black screen (Add support for DRI3 v1.2) Product: Mesa Version: git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Drivers/Vulkan/radeon Assignee: mesa-dev@lists.freedesktop.org Reporter: mercuri...@yahoo.es QA Contact: mesa-dev@lists.freedesktop.org When doing smoketest with radv driver, the window is black. bisected: git bisect bad c80c08e226033e9e33abdca43e02e7f8c845ae0a is the first bad commit commit c80c08e226033e9e33abdca43e02e7f8c845ae0a Author: Daniel Stone Date: Thu Jun 8 17:24:30 2017 +0100 vulkan/wsi/x11: Add support for DRI3 v1.2 Adds support for multiple planes and buffer modifiers. v4: Rename "has_dri3_v1_1" to "has_dri3_modifiers" v12: Multi-planar/modifier support is now DRI3 v1.2; also update release versions :100644 100644 40e7855994a6e76d744f192694d5060d39327d56 f84903dffebf39694f458d267793e39a03a0cf8d M configure.ac :100644 100644 7658f6e63dae57920fd74a9e445efb07018fd227 34090de45257ea468474af8697760900feb1f341 M meson.build :04 04 14486094f3e8b9102b67a608d31ea5bf43ee5627 4a42c1f98bcdb9b0c95020cc759565f412d77bf7 M src Configuration: distro: gentoo PRIME configuration with intel haswell and amd radeon m265x uname -a Linux localhost.localdomain 4.14.35-gentoo #1 SMP PREEMPT Sun Apr 22 12:00:39 CEST 2018 x86_64 Intel(R) Core(TM) i7-4720HQ CPU @ 2.60GHz GenuineIntel GNU/Linux important lines of lspci: 00:02.0 VGA compatible controller [0300]: Intel Corporation 4th Gen Core Processor Integrated Graphics Controller [8086:0416] (rev 06) 01:00.0 Display controller [0380]: Advanced Micro Devices, Inc. [AMD/ATI] Venus PRO [Radeon HD 8850M / R9 M265X] [1002:6823] dependencies installed: `-- dev-libs/expat-2.2.5 `-- sys-libs/zlib-1.2.11-r1 `-- x11-libs/libX11-1.6.5 `-- x11-libs/libxshmfence-1.2 `-- x11-libs/libXdamage-1.1.4-r1 `-- x11-libs/libXext-1.3.3 `-- x11-libs/libXxf86vm-1.1.4 `-- x11-libs/libxcb-1.13 `-- x11-libs/libXfixes-5.0.3 `-- sys-libs/libunwind-1.2.1 `-- virtual/libelf-3 `-- dev-libs/libclc-0.2.0_pre20170929 `-- media-libs/libomxil-bellagio-0.9.3 `-- x11-misc/xdg-utils-1.1.1-r1 `-- x11-libs/libva-1.7.3 `-- x11-libs/libvdpau-1.1.1 `-- dev-libs/wayland-1.13.0 `-- dev-libs/wayland-protocols-1.11 `-- x11-libs/libXvMC-1.0.10 `-- x11-libs/libdrm-2.4.91 `-- sys-devel/llvm-6.0.0 `-- dev-lang/python-2.7.14-r1 `-- sys-devel/gcc-6.4.0-r1 `-- sys-devel/gettext-0.19.8.1 `-- virtual/pkgconfig-0-r1 `-- dev-util/valgrind-3.13.0 `-- x11-proto/dri2proto-2.8-r2 `-- x11-proto/dri3proto-1.0-r1 `-- x11-proto/presentproto-1.1-r1 `-- x11-proto/glproto-1.4.17-r2 `-- x11-proto/xextproto-7.3.0-r1 `-- x11-proto/xf86driproto-2.1.1-r2 `-- x11-proto/xf86vidmodeproto-2.3.1-r2 `-- dev-python/mako-1.0.6 `-- app-portage/elt-patches-20170815 `-- sys-devel/automake-1.15.1-r2 `-- sys-devel/autoconf-2.69-r4 `-- sys-devel/libtool-2.4.6-r3 -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] 16-bit comparisons in NIR
On Fri, 2018-04-20 at 17:16 -0700, Jason Ekstrand wrote: > On Fri, Apr 20, 2018 at 5:16 AM, Nicolai Hähnle > wrote: > > On 20.04.2018 10:21, Iago Toral wrote: > > > > > Hi, > > > > > > > > > > > > while developing support for Vulkan shaderInt16 on Anvil I came > > > across > > > > > > a feature of NIR that was a bit inconvenient: bools are always > > > 32-bit > > > > > > by design, but the Intel hardware produces 16-bit bool results > > > for 16- > > > > > > bit comparisons, so that creates a problem that manifests like > > > this: > > > > > > > > > > > > vec1 32 ssa_21 = fge ssa_20, ssa_16 > > > > > > vec1 16 ssa_22 = b2f ssa_21 > > I was thinking about this a bit this morning and it gets even more > sticky. What happens if you have > > bool e = (a < b) && (c < d); > > where a and b are 16-bit and c and d are 32-bit? In this case, one > comprison has a 32-bit value and one has a 16-bit value and you have > to pick one for the &&. Good point, yes, it seems we would need to handle this somehow. Topi seems to try and do something about this in the patch he referenced in his reply. Alternatively, we can also run a specific pass to fix this up... > > > Our CMP instruction will produce a 16-bit boolean result for the > > > first > > > > > > NIR instruction (where NIR expects it to be 32-bit), so by the > > > time we > > > > > > emit the second instruction in the driver the bit-size for the > > > operand > > > > > > of b2f provided by NIR no longer matches the reality and we emit > > > > > > incorrect code. > > > > > > > > > > > > This seems to have been a consicious design choice in NIR, and > > > while > > > > > > discussing this with Jason he was unsure how much we wanted to > > > change > > > > > > this or how to do it, given how thoroughly 32-bit bools are > > > baked into > > > > > > NIR and the complexities that modifying this would also bring to > > > our > > > > > > bit-size validation code. > > > > > > > > > > > > I have been considering alternatives that didn't involve changing > > > NIR > > > > > > to support multiple bit-sizes for booleans: > > > > > > > > > > > > 1) Drivers that need to emit smaller booleans could try to fix > > > the > > > > > > generated NIR by correcting the expected bit-sizes for CMP > > > > > > instructions. This would be rather trivial to implement in > > > drivers (and > > > > > > maybe we could even make a generic pass for other drivers to use > > > if > > > > > > they need it) but this will make the validator complain because > > > it > > > > > > won't recognize comparisons with 16-bit bool outputs as valid NIR > > > > > > opcodes. I also found instances where nir_search would complain > > > about > > > > > > mismatching bit-sizes. I haven't looked any further into it yet > > > though, > > > > > > so maybe we can reasonably work around these issues. > > > > > > > > > > > > 2) Drivers could handle this specially when they emit code from > > > NIR. > > > > > > Specifically, when they see a 32-bit boolean source in an > > > instruction, > > > > > > they would have to search for the instruction that produced that > > > source > > > > > > value and check whether it is a 16-bit or a 32-bit boolean to > > > emit > > > > > > proper code for the instruction. > > > > > > > > > > > > 3) Drivers can just convert the 16-bit bool result they generate > > > for > > > > > > 16-bit cmp to the 32-bit bool that NIR expects, and then possibly > > > run > > > > > > an optimization pass to eliminate these extra conversions and fix > > > up > > > > > > the code accordingly. > > > > > > > > > > > > radeonsi(NIR) and radv already use option 3, since GCN hardware > > really wants to treat bools as 1-bit value, so that's what I'd > > suggest. The optimizations that cleanup the conversions happen in > > LLVM for us. > > Is this a GCN thing or an LLVM thing? It would be neat if your > hardware had 1-bit registers. :-) We sort-of do but they're special > flag registers and we have very few of them. > > --Jason > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 106174] vulkan dota2 broken (segfaulting), found bug commit
https://bugs.freedesktop.org/show_bug.cgi?id=106174 --- Comment #2 from Sylvain BERTRAND --- On Sun, Apr 22, 2018 at 05:28:45PM +, bugzilla-dae...@freedesktop.org wrote: > https://bugs.freedesktop.org/show_bug.cgi?id=106174 > > --- Comment #1 from Bas Nieuwenhuizen --- > Yeah, I noticed this too. > > https://patchwork.freedesktop.org/patch/218205/ > > should fix this. Since I'm not into nir, I just reverted the patch. Your patch seems to do what the commit intended to do in the first place, though. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 106174] vulkan dota2 broken (segfaulting), found bug commit
https://bugs.freedesktop.org/show_bug.cgi?id=106174 --- Comment #1 from Bas Nieuwenhuizen --- Yeah, I noticed this too. https://patchwork.freedesktop.org/patch/218205/ should fix this. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] nir: Do not use progress for unreachable code in return lowering.
We seems to use progress for two cases:
1) When we lowered some returns.
2) When we remove unreachable code.
If just case 2 happens we assert as state->return_flag has not
been allocated yet, but we are still trying to do insert all
predicates based on it.
This splits the concerns. We only use progress internally for case 1
and then keep track of 2 in a separate variable to indicate progress
in the return value of the pass.
This is slightly better than transforming the assert into
if (!state->return_flag) return, as it avoids inserting predicates
even if some other part of the code might need them.
Fixes: 6e22ad6edc "nir: return early when lowering a return at the end of a
function"
CC: 18.1
---
src/compiler/nir/nir_lower_returns.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir_lower_returns.c
b/src/compiler/nir/nir_lower_returns.c
index 3ea69e2520..9c4881112e 100644
--- a/src/compiler/nir/nir_lower_returns.c
+++ b/src/compiler/nir/nir_lower_returns.c
@@ -37,6 +37,8 @@ struct lower_returns_state {
* needs to be predicated on the return flag variable.
*/
bool has_predicated_return;
+
+ bool removed_unreachable_code;
};
static bool lower_returns_in_cf_list(struct exec_list *cf_list,
@@ -162,8 +164,9 @@ lower_returns_in_block(nir_block *block, struct
lower_returns_state *state)
*/
return false;
} else {
+ state->removed_unreachable_code = true;
nir_cf_delete(&list);
- return true;
+ return false;
}
}
@@ -262,9 +265,11 @@ nir_lower_returns_impl(nir_function_impl *impl)
state.loop = NULL;
state.return_flag = NULL;
state.has_predicated_return = false;
+ state.removed_unreachable_code = false;
nir_builder_init(&state.builder, impl);
bool progress = lower_returns_in_cf_list(&impl->body, &state);
+ progress = progress || state.removed_unreachable_code;
if (progress) {
nir_metadata_preserve(impl, nir_metadata_none);
--
2.17.0
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[Mesa-dev] [Bug 106176] [mesa] git master VERSION not increased when 18.1 was branched off
https://bugs.freedesktop.org/show_bug.cgi?id=106176 Dylan Baker changed: What|Removed |Added Resolution|--- |FIXED Status|NEW |RESOLVED --- Comment #2 from Dylan Baker --- Apparently I forgot to git push on master as well :/ It's fixed now. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 106176] [mesa] git master VERSION not increased when 18.1 was branched off
https://bugs.freedesktop.org/show_bug.cgi?id=106176 --- Comment #1 from LoneVVolf --- Created attachment 138989 --> https://bugs.freedesktop.org/attachment.cgi?id=138989&action=edit increase number in VERSION-file -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] android: gallium/util: fix u_debug_stack_android build
On Sun, Apr 22, 2018 at 1:11 PM, Mauro Rossi wrote:
> Fix for build errors in src/gallium/auxiliary/util/u_debug_stack_android.cpp
> error: cast to 'void *' from smaller integer type pid_t
>
> Fixes: ff904978a1 ("gallium/util: Android backtrace support")
>
> Cc: "18.1"
> ---
> src/gallium/auxiliary/util/u_debug_stack_android.cpp | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/auxiliary/util/u_debug_stack_android.cpp
> b/src/gallium/auxiliary/util/u_debug_stack_android.cpp
> index b3d56aebe6..11e2d3962b 100644
> --- a/src/gallium/auxiliary/util/u_debug_stack_android.cpp
> +++ b/src/gallium/auxiliary/util/u_debug_stack_android.cpp
> @@ -49,10 +49,10 @@ debug_backtrace_capture(debug_stack_frame *mesa_backtrace,
>backtrace_table = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
> _mesa_key_pointer_equal);
>
> - backtrace_entry = _mesa_hash_table_search(backtrace_table, (void*) tid);
> + backtrace_entry = _mesa_hash_table_search(backtrace_table,
> (void*)(uintptr_t) tid);
> if (!backtrace_entry) {
>backtrace = Backtrace::Create(getpid(), tid);
> - _mesa_hash_table_insert(backtrace_table, (void*) tid, backtrace);
> + _mesa_hash_table_insert(backtrace_table, (void*)(uintptr_t) tid,
> backtrace);
> } else {
>backtrace = (Backtrace *) backtrace_entry->data;
> }
> --
> 2.14.1
>
Sorry, I'm doing ARMv7/32-bit builds so this slipped through.
Reviewed-By: Stefan Schake
Thanks!
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[Mesa-dev] [Bug 106176] [mesa] git master VERSION not increased when 18.1 was branched off
https://bugs.freedesktop.org/show_bug.cgi?id=106176 Bug ID: 106176 Summary: [mesa] git master VERSION not increased when 18.1 was branched off Product: Mesa Version: git Hardware: All OS: All Status: NEW Severity: normal Priority: medium Component: Other Assignee: mesa-dev@lists.freedesktop.org Reporter: lonew...@xs4all.nl QA Contact: mesa-dev@lists.freedesktop.org When 18.1 branchpoint was created in https://cgit.freedesktop.org/mesa/mesa/commit/?id=6754c2e83d79f93b3a4c8c1c55ca4c5e3b965645 the version in trunk file VERSION was not increased. This means trunk and latets rc-candidates now show same version : 18.1.0 . Please increase the number in trunk VERSION to 18.2.0-devel . -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] android: gallium/util: fix u_debug_stack_android build
Fix for build errors in src/gallium/auxiliary/util/u_debug_stack_android.cpp
error: cast to 'void *' from smaller integer type pid_t
Fixes: ff904978a1 ("gallium/util: Android backtrace support")
Cc: "18.1"
---
src/gallium/auxiliary/util/u_debug_stack_android.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_debug_stack_android.cpp
b/src/gallium/auxiliary/util/u_debug_stack_android.cpp
index b3d56aebe6..11e2d3962b 100644
--- a/src/gallium/auxiliary/util/u_debug_stack_android.cpp
+++ b/src/gallium/auxiliary/util/u_debug_stack_android.cpp
@@ -49,10 +49,10 @@ debug_backtrace_capture(debug_stack_frame *mesa_backtrace,
backtrace_table = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
_mesa_key_pointer_equal);
- backtrace_entry = _mesa_hash_table_search(backtrace_table, (void*) tid);
+ backtrace_entry = _mesa_hash_table_search(backtrace_table,
(void*)(uintptr_t) tid);
if (!backtrace_entry) {
backtrace = Backtrace::Create(getpid(), tid);
- _mesa_hash_table_insert(backtrace_table, (void*) tid, backtrace);
+ _mesa_hash_table_insert(backtrace_table, (void*)(uintptr_t) tid,
backtrace);
} else {
backtrace = (Backtrace *) backtrace_entry->data;
}
--
2.14.1
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[Mesa-dev] [Bug 106174] vulkan dota2 broken (segfaulting), found bug commit
https://bugs.freedesktop.org/show_bug.cgi?id=106174 Bug ID: 106174 Summary: vulkan dota2 broken (segfaulting), found bug commit Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: blocker Priority: highest Component: Drivers/Vulkan/radeon Assignee: mesa-dev@lists.freedesktop.org Reporter: sylvain.bertr...@gmail.com QA Contact: mesa-dev@lists.freedesktop.org Did not see my email in the mailing list archive. I secure the report here: After refurbishing my custom gnu/linux distro, dota2 vulkan was broken: could not enter any game without segfaulting. (amd tahiti xt) The segfault commit is: 6e22ad6edc34dc07a08b41a781f1c37ff3c536e7 I did revert this commit on top of 63572091b52ace35b60c46d092183bf818733ee0, dota2 vulkan has been ok so far. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
