[Mesa-dev] [PATCH 2/5] mesa: expose ARB_shader_viewport_layer_array in the compatibility profile

[Marek Olšák]

From: Marek Olšák 

no changes needed for GL compat
---
 src/mesa/main/extensions_table.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index 98d1f381b0e..157e7e57c31 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -119,21 +119,21 @@ EXT(ARB_shader_draw_parameters  , 
ARB_shader_draw_parameters
 EXT(ARB_shader_group_vote   , ARB_shader_group_vote
  , GLL, GLC,  x ,  x , 2013)
 EXT(ARB_shader_image_load_store , ARB_shader_image_load_store  
  , GLL, GLC,  x ,  x , 2011)
 EXT(ARB_shader_image_size   , ARB_shader_image_size
  , GLL, GLC,  x ,  x , 2012)
 EXT(ARB_shader_objects  , dummy_true   
  , GLL, GLC,  x ,  x , 2002)
 EXT(ARB_shader_precision, ARB_shader_precision 
  , GLL, GLC,  x ,  x , 2010)
 EXT(ARB_shader_stencil_export   , ARB_shader_stencil_export
  , GLL, GLC,  x ,  x , 2009)
 EXT(ARB_shader_storage_buffer_object, ARB_shader_storage_buffer_object 
  , GLL, GLC,  x ,  x , 2012)
 EXT(ARB_shader_subroutine   , dummy_true   
  ,  31, GLC,  x ,  x , 2010)
 EXT(ARB_shader_texture_image_samples, ARB_shader_texture_image_samples 
  , GLL, GLC,  x ,  x , 2014)
 EXT(ARB_shader_texture_lod  , ARB_shader_texture_lod   
  , GLL, GLC,  x ,  x , 2009)
-EXT(ARB_shader_viewport_layer_array , ARB_shader_viewport_layer_array  
  ,  x , GLC,  x ,  x , 2015)
+EXT(ARB_shader_viewport_layer_array , ARB_shader_viewport_layer_array  
  , GLL, GLC,  x ,  x , 2015)
 EXT(ARB_shading_language_100, dummy_true   
  , GLL,  x ,  x ,  x , 2003)
 EXT(ARB_shading_language_420pack, ARB_shading_language_420pack 
  , GLL, GLC,  x ,  x , 2011)
 EXT(ARB_shading_language_packing, ARB_shading_language_packing 
  , GLL, GLC,  x ,  x , 2011)
 EXT(ARB_shadow  , ARB_shadow   
  , GLL,  x ,  x ,  x , 2001)
 EXT(ARB_sparse_buffer   , ARB_sparse_buffer
  , GLL, GLC,  x ,  x , 2014)
 EXT(ARB_stencil_texturing   , ARB_stencil_texturing
  , GLL, GLC,  x ,  x , 2012)
 EXT(ARB_sync, ARB_sync 
  , GLL, GLC,  x ,  x , 2003)
 EXT(ARB_tessellation_shader , ARB_tessellation_shader  
  , GLL, GLC,  x ,  x , 2009)
 EXT(ARB_texture_barrier , NV_texture_barrier   
  , GLL, GLC,  x ,  x , 2014)
 EXT(ARB_texture_border_clamp, ARB_texture_border_clamp 
  , GLL,  x ,  x ,  x , 2000)
-- 
2.17.1

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[Mesa-dev] [PATCH 3/5] vbo: fix ARB_multi_draw_indirect for the compatibility profile

[Marek Olšák]

From: Marek Olšák 

---
 src/mesa/vbo/vbo_exec_array.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/vbo/vbo_exec_array.c b/src/mesa/vbo/vbo_exec_array.c
index 58bba208db1..9d3e894c164 100644
--- a/src/mesa/vbo/vbo_exec_array.c
+++ b/src/mesa/vbo/vbo_exec_array.c
@@ -2074,41 +2074,41 @@ vbo_initialize_exec_dispatch(const struct gl_context 
*ctx,
   SET_DrawElementsInstancedBaseVertexBaseInstance(exec,
   
vbo_exec_DrawElementsInstancedBaseVertexBaseInstance);
}
 
if (_mesa_is_desktop_gl(ctx) || _mesa_is_gles31(ctx)) {
   SET_DrawArraysIndirect(exec, vbo_exec_DrawArraysIndirect);
   SET_DrawElementsIndirect(exec, vbo_exec_DrawElementsIndirect);
}
 
if (ctx->API == API_OPENGL_CORE) {
-  SET_MultiDrawArraysIndirect(exec, vbo_exec_MultiDrawArraysIndirect);
-  SET_MultiDrawElementsIndirect(exec, vbo_exec_MultiDrawElementsIndirect);
   SET_MultiDrawArraysIndirectCountARB(exec,
   
vbo_exec_MultiDrawArraysIndirectCount);
   SET_MultiDrawElementsIndirectCountARB(exec,
 
vbo_exec_MultiDrawElementsIndirectCount);
}
 
if (_mesa_is_desktop_gl(ctx) || _mesa_is_gles3(ctx)) {
   SET_DrawArraysInstancedARB(exec, vbo_exec_DrawArraysInstanced);
   SET_DrawElementsInstancedARB(exec, vbo_exec_DrawElementsInstanced);
}
 
if (_mesa_is_desktop_gl(ctx)) {
   SET_DrawTransformFeedback(exec, vbo_exec_DrawTransformFeedback);
   SET_DrawTransformFeedbackStream(exec,
   vbo_exec_DrawTransformFeedbackStream);
   SET_DrawTransformFeedbackInstanced(exec,
  
vbo_exec_DrawTransformFeedbackInstanced);
   SET_DrawTransformFeedbackStreamInstanced(exec,

vbo_exec_DrawTransformFeedbackStreamInstanced);
+  SET_MultiDrawArraysIndirect(exec, vbo_exec_MultiDrawArraysIndirect);
+  SET_MultiDrawElementsIndirect(exec, vbo_exec_MultiDrawElementsIndirect);
}
 }
 
 
 
 /**
  * The following functions are only used for OpenGL ES 1/2 support.
  * And some aren't even supported (yet) in ES 1/2.
  */
 
-- 
2.17.1

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[Mesa-dev] [PATCH 4/5] mesa: expose ARB_indirect_parameters in the compatibility profile

[Marek Olšák]

From: Marek Olšák 

---
 src/mesa/main/extensions_table.h |  2 +-
 src/mesa/vbo/vbo_exec_array.c| 11 ---
 2 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index 157e7e57c31..9d08d2d5531 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -73,21 +73,21 @@ EXT(ARB_framebuffer_no_attachments  , 
ARB_framebuffer_no_attachments
 EXT(ARB_framebuffer_object  , ARB_framebuffer_object   
  , GLL, GLC,  x ,  x , 2005)
 EXT(ARB_framebuffer_sRGB, EXT_framebuffer_sRGB 
  , GLL, GLC,  x ,  x , 1998)
 EXT(ARB_get_program_binary  , dummy_true   
  , GLL, GLC,  x ,  x , 2010)
 EXT(ARB_get_texture_sub_image   , dummy_true   
  , GLL, GLC,  x ,  x , 2014)
 EXT(ARB_gl_spirv, ARB_gl_spirv 
  ,  x,  GLC,  x ,  x , 2016)
 EXT(ARB_gpu_shader5 , ARB_gpu_shader5  
  , GLL, GLC,  x ,  x , 2010)
 EXT(ARB_gpu_shader_fp64 , ARB_gpu_shader_fp64  
  ,  32, GLC,  x ,  x , 2010)
 EXT(ARB_gpu_shader_int64, ARB_gpu_shader_int64 
  ,  x , GLC,  x ,  x , 2015)
 EXT(ARB_half_float_pixel, dummy_true   
  , GLL, GLC,  x ,  x , 2003)
 EXT(ARB_half_float_vertex   , ARB_half_float_vertex
  , GLL, GLC,  x ,  x , 2008)
-EXT(ARB_indirect_parameters , ARB_indirect_parameters  
  ,  x , GLC,  x ,  x , 2013)
+EXT(ARB_indirect_parameters , ARB_indirect_parameters  
  , GLL, GLC,  x ,  x , 2013)
 EXT(ARB_instanced_arrays, ARB_instanced_arrays 
  , GLL, GLC,  x ,  x , 2008)
 EXT(ARB_internalformat_query, ARB_internalformat_query 
  , GLL, GLC,  x ,  x , 2011)
 EXT(ARB_internalformat_query2   , ARB_internalformat_query2
  , GLL, GLC,  x ,  x , 2013)
 EXT(ARB_invalidate_subdata  , dummy_true   
  , GLL, GLC,  x ,  x , 2012)
 EXT(ARB_map_buffer_alignment, dummy_true   
  , GLL, GLC,  x ,  x , 2011)
 EXT(ARB_map_buffer_range, ARB_map_buffer_range 
  , GLL, GLC,  x ,  x , 2008)
 EXT(ARB_multi_bind  , dummy_true   
  , GLL, GLC,  x ,  x , 2013)
 EXT(ARB_multi_draw_indirect , ARB_draw_indirect
  , GLL, GLC,  x ,  x , 2012)
 EXT(ARB_multisample , dummy_true   
  , GLL,  x ,  x ,  x , 1994)
 EXT(ARB_multitexture, dummy_true   
  , GLL,  x ,  x ,  x , 1998)
diff --git a/src/mesa/vbo/vbo_exec_array.c b/src/mesa/vbo/vbo_exec_array.c
index 9d3e894c164..51c000e7bd9 100644
--- a/src/mesa/vbo/vbo_exec_array.c
+++ b/src/mesa/vbo/vbo_exec_array.c
@@ -2073,42 +2073,39 @@ vbo_initialize_exec_dispatch(const struct gl_context 
*ctx,
 
vbo_exec_DrawElementsInstancedBaseInstance);
   SET_DrawElementsInstancedBaseVertexBaseInstance(exec,
   
vbo_exec_DrawElementsInstancedBaseVertexBaseInstance);
}
 
if (_mesa_is_desktop_gl(ctx) || _mesa_is_gles31(ctx)) {
   SET_DrawArraysIndirect(exec, vbo_exec_DrawArraysIndirect);
   SET_DrawElementsIndirect(exec, vbo_exec_DrawElementsIndirect);
}
 
-   if (ctx->API == API_OPENGL_CORE) {
-  SET_MultiDrawArraysIndirectCountARB(exec,
-  
vbo_exec_MultiDrawArraysIndirectCount);
-  SET_MultiDrawElementsIndirectCountARB(exec,
-
vbo_exec_MultiDrawElementsIndirectCount);
-   }
-
if (_mesa_is_desktop_gl(ctx) || _mesa_is_gles3(ctx)) {
   SET_DrawArraysInstancedARB(exec, vbo_exec_DrawArraysInstanced);
   SET_DrawElementsInstancedARB(exec, vbo_exec_DrawElementsInstanced);
}
 
if (_mesa_is_desktop_gl(ctx)) {
   SET_DrawTransformFeedback(exec, vbo_exec_DrawTransformFeedback);
   SET_DrawTransformFeedbackStream(exec,
   vbo_exec_DrawTransformFeedbackStream);
   SET_DrawTransformFeedbackInstanced(exec,
  
vbo_exec_DrawTransformFeedbackInstanced);
   SET_DrawTransformFeedbackStreamInstanced(exec,

vbo_exec_DrawTransformFeedbackStreamInstanced);
   SET_MultiDrawArraysIndirect(exec, vbo_exec_MultiDrawArraysIndirect);
   SET_MultiDrawElementsIndirect(exec, vbo_exec_MultiDrawElementsIndirect);
+  SET_MultiDrawArraysIndirectCountARB(exec,
+ 

[Mesa-dev] [PATCH 5/5] mesa: remove dead code from api_loopback

[Marek Olšák]

From: Marek Olšák 

This should only contain functions not set in vtxfmt.c.
---
 src/mesa/main/api_loopback.c | 17 -
 1 file changed, 17 deletions(-)

diff --git a/src/mesa/main/api_loopback.c b/src/mesa/main/api_loopback.c
index 4eab8118c78..c03c33ee339 100644
--- a/src/mesa/main/api_loopback.c
+++ b/src/mesa/main/api_loopback.c
@@ -1783,29 +1783,12 @@ _mesa_loopback_init_api_table(const struct gl_context 
*ctx,
   SET_VertexAttrib4Niv(dest, _mesa_VertexAttrib4Niv);
   SET_VertexAttrib4Nuiv(dest, _mesa_VertexAttrib4Nuiv);
 
   /* GL_EXT_gpu_shader4, GL 3.0 */
   SET_VertexAttribI1iv(dest, _mesa_VertexAttribI1iv);
   SET_VertexAttribI1uiv(dest, _mesa_VertexAttribI1uiv);
   SET_VertexAttribI4bv(dest, _mesa_VertexAttribI4bv);
   SET_VertexAttribI4sv(dest, _mesa_VertexAttribI4sv);
   SET_VertexAttribI4ubv(dest, _mesa_VertexAttribI4ubv);
   SET_VertexAttribI4usv(dest, _mesa_VertexAttribI4usv);
-
-  /* GL_ARB_bindless_texture */
-  SET_VertexAttribL1ui64ARB(dest, _mesa_VertexAttribL1ui64ARB);
-  SET_VertexAttribL1ui64vARB(dest, _mesa_VertexAttribL1ui64vARB);
-   }
-
-   if (ctx->API == API_OPENGL_CORE) {
-  /* GL 4.1 / GL_ARB_vertex_attrib_64bit */
-  SET_VertexAttribL1d(dest, _mesa_VertexAttribL1d);
-  SET_VertexAttribL2d(dest, _mesa_VertexAttribL2d);
-  SET_VertexAttribL3d(dest, _mesa_VertexAttribL3d);
-  SET_VertexAttribL4d(dest, _mesa_VertexAttribL4d);
-
-  SET_VertexAttribL1dv(dest, _mesa_VertexAttribL1dv);
-  SET_VertexAttribL2dv(dest, _mesa_VertexAttribL2dv);
-  SET_VertexAttribL3dv(dest, _mesa_VertexAttribL3dv);
-  SET_VertexAttribL4dv(dest, _mesa_VertexAttribL4dv);
}
 }
-- 
2.17.1

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[Mesa-dev] [PATCH 1/5] mesa: expose ARB_ES3_1_compatibility in the compatibility profile

[Marek Olšák]

From: Marek Olšák 

no changes needed for GL compat
---
 src/mesa/main/extensions_table.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index e24287b8581..98d1f381b0e 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -21,21 +21,21 @@ EXT(AMD_vertex_shader_viewport_index, 
AMD_vertex_shader_viewport_index
 EXT(ANDROID_extension_pack_es31a, ANDROID_extension_pack_es31a 
  ,  x ,  x ,  x ,  31, 2014)
 
 EXT(ANGLE_texture_compression_dxt3  , ANGLE_texture_compression_dxt
  , GLL, GLC, ES1, ES2, 2011)
 EXT(ANGLE_texture_compression_dxt5  , ANGLE_texture_compression_dxt
  , GLL, GLC, ES1, ES2, 2011)
 
 EXT(APPLE_object_purgeable  , APPLE_object_purgeable   
  , GLL, GLC,  x ,  x , 2006)
 EXT(APPLE_packed_pixels , dummy_true   
  , GLL,  x ,  x ,  x , 2002)
 EXT(APPLE_texture_max_level , dummy_true   
  ,  x ,  x , ES1, ES2, 2009)
 
 EXT(ARB_ES2_compatibility   , ARB_ES2_compatibility
  , GLL, GLC,  x ,  x , 2009)
-EXT(ARB_ES3_1_compatibility , ARB_ES3_1_compatibility  
  ,  x , GLC,  x ,  x , 2014)
+EXT(ARB_ES3_1_compatibility , ARB_ES3_1_compatibility  
  , GLL, GLC,  x ,  x , 2014)
 EXT(ARB_ES3_2_compatibility , ARB_ES3_2_compatibility  
  ,  x , GLC,  x ,  x , 2015)
 EXT(ARB_ES3_compatibility   , ARB_ES3_compatibility
  , GLL, GLC,  x ,  x , 2012)
 EXT(ARB_arrays_of_arrays, ARB_arrays_of_arrays 
  , GLL, GLC,  x ,  x , 2012)
 EXT(ARB_base_instance   , ARB_base_instance
  , GLL, GLC,  x ,  x , 2011)
 EXT(ARB_bindless_texture, ARB_bindless_texture 
  , GLL, GLC,  x ,  x , 2013)
 EXT(ARB_blend_func_extended , ARB_blend_func_extended  
  , GLL, GLC,  x ,  x , 2009)
 EXT(ARB_buffer_storage  , ARB_buffer_storage   
  , GLL, GLC,  x ,  x , 2013)
 EXT(ARB_clear_buffer_object , dummy_true   
  , GLL, GLC,  x ,  x , 2012)
 EXT(ARB_clear_texture   , ARB_clear_texture
  , GLL, GLC,  x ,  x , 2013)
 EXT(ARB_clip_control, ARB_clip_control 
  , GLL, GLC,  x ,  x , 2014)
-- 
2.17.1

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Re: [Mesa-dev] [PATCH 10/11] util/string_buffer: fix warning in tests

[Thomas Helland]

This patch is

Reviewed-by: Thomas Helland 

Den tir. 17. jul. 2018, 01:40 skrev Caio Marcelo de Oliveira Filho <
caio.olive...@intel.com>:

> And also specify the maximum size when writing to static buffers. The
> warning below refers to the case where "str5" could be larger than
> "str5 - str4", then the strcat would have overlapping dst and src.
>
> Compiler doesn't pick up the bound from the snprintf above, so we make
> clear the bounds of str5 by using strncat() instead of strcat().
>
> ../../src/util/tests/string_buffer/string_buffer_test.cpp: In member
> function ‘virtual void string_buffer_string_buffer_tests_Test::TestBody()’:
> ../../src/util/tests/string_buffer/string_buffer_test.cpp:106:10: warning:
> ‘char* strcat(char*, const char*)’ accessing 81 or more bytes at offsets 48
> and 128 may overlap 1 byte at offset 128 [-Wrestrict]
> strcat(str4, str5);
> ~~^~~~
> ---
>  src/util/tests/string_buffer/string_buffer_test.cpp | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/util/tests/string_buffer/string_buffer_test.cpp
> b/src/util/tests/string_buffer/string_buffer_test.cpp
> index 545f607fadd..afb6dfb2a19 100644
> --- a/src/util/tests/string_buffer/string_buffer_test.cpp
> +++ b/src/util/tests/string_buffer/string_buffer_test.cpp
> @@ -95,15 +95,15 @@ TEST_F(string_buffer, string_buffer_tests)
> EXPECT_TRUE(strlen(buf->buf) == 0);
>
> /* Test a string with some formatting */
> -   sprintf(str4, "Testing formatting %d, %f", 100, 1.0);
> +   snprintf(str4, sizeof(str4), "Testing formatting %d, %f", 100, 1.0);
> EXPECT_TRUE(_mesa_string_buffer_printf(buf, "Testing formatting %d,
> %f", 100, 1.0));
> EXPECT_TRUE(strcmp(buf->buf, str4) == 0);
>
> /* Compile a string with some other formatting */
> -   sprintf(str5, "Testing formatting %d, %x", 100, 0xDEADBEAF);
> +   snprintf(str5, sizeof(str5), "Testing formatting %d, %x", 100,
> 0xDEADBEAF);
>
> /* Concatenate str5 to str4 */
> -   strcat(str4, str5);
> +   strncat(str4, str5, sizeof(str5));
>
> /* Now use the formatted append function again */
> EXPECT_TRUE(_mesa_string_buffer_printf(buf, "Testing formatting %d,
> %x", 100, 0xDEADBEAF));
> --
> 2.18.0
>
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[Mesa-dev] [PATCH] gallium: surface remove width/height removal comment

[Dave Airlie]

From: Dave Airlie 

We do need width/height for things, remove the outdated
comment.
---
 src/gallium/include/pipe/p_state.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/gallium/include/pipe/p_state.h 
b/src/gallium/include/pipe/p_state.h
index 809aa087ce0..b55624d698d 100644
--- a/src/gallium/include/pipe/p_state.h
+++ b/src/gallium/include/pipe/p_state.h
@@ -435,7 +435,6 @@ struct pipe_surface
struct pipe_resource *texture; /**< resource into which this is a view  */
struct pipe_context *context; /**< context this surface belongs to */
 
-   /* XXX width/height should be removed */
uint16_t width;   /**< logical width in pixels */
uint16_t height;  /**< logical height in pixels */
 
-- 
2.17.1

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[Mesa-dev] [PATCH] virgl: Fix flush in virgl_encoder_inline_write.

[Lepton Wu]

The current code is buggy: if there are only 12 dwords left in cbuf,
we emit a zero data length command which will be rejected by virglrenderer.
Fix it by calling flush in this case.
---
 src/gallium/drivers/virgl/virgl_encode.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/virgl/virgl_encode.c 
b/src/gallium/drivers/virgl/virgl_encode.c
index 6b800d3d07..e097fa83a9 100644
--- a/src/gallium/drivers/virgl/virgl_encode.c
+++ b/src/gallium/drivers/virgl/virgl_encode.c
@@ -528,7 +528,7 @@ int virgl_encoder_inline_write(struct virgl_context *ctx,
 
left_bytes = size;
while (left_bytes) {
-  if (ctx->cbuf->cdw + 12 > VIRGL_MAX_CMDBUF_DWORDS)
+  if (ctx->cbuf->cdw + 12 >= VIRGL_MAX_CMDBUF_DWORDS)
  ctx->base.flush(>base, NULL, 0);
 
   thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - 12) * 4;
-- 
2.18.0.203.gfac676dfb9-goog

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Re: [Mesa-dev] [PATCH 01/11] spirv: initialize is_vertex_input

[Anuj Phogat]

On Mon, Jul 16, 2018 at 3:38 PM Caio Marcelo de Oliveira Filho
 wrote:
>
> Fixes warning:
>
> ../../src/compiler/spirv/vtn_variables.c: In function ‘var_decoration_cb’:
> ../../src/compiler/spirv/vtn_variables.c:1400:12: warning: ‘is_vertex_input’ 
> may be used uninitialized in this function [-Wmaybe-uninitialized]
>bool is_vertex_input;
> ^~~
>
> The code used to set is_vertex_input in all possible codepaths, but
> after 23edc5b1ef3 "spirv: translate default-block uniforms" the
> compiler isn't sure all codepaths will initialize the variable.
> ---
>  src/compiler/spirv/vtn_variables.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/src/compiler/spirv/vtn_variables.c 
> b/src/compiler/spirv/vtn_variables.c
> index 6bd7aa1b0d5..fbfea6f8cef 100644
> --- a/src/compiler/spirv/vtn_variables.c
> +++ b/src/compiler/spirv/vtn_variables.c
> @@ -1397,10 +1397,9 @@ var_decoration_cb(struct vtn_builder *b, struct 
> vtn_value *val, int member,
>  */
> if (dec->decoration == SpvDecorationLocation) {
>unsigned location = dec->literals[0];
> -  bool is_vertex_input;
> +  bool is_vertex_input = false;
>if (b->shader->info.stage == MESA_SHADER_FRAGMENT &&
>vtn_var->mode == vtn_variable_mode_output) {
> - is_vertex_input = false;
>   location += FRAG_RESULT_DATA0;
>} else if (b->shader->info.stage == MESA_SHADER_VERTEX &&
>   vtn_var->mode == vtn_variable_mode_input) {
> @@ -1408,7 +1407,6 @@ var_decoration_cb(struct vtn_builder *b, struct 
> vtn_value *val, int member,
>   location += VERT_ATTRIB_GENERIC0;
>} else if (vtn_var->mode == vtn_variable_mode_input ||
>   vtn_var->mode == vtn_variable_mode_output) {
> - is_vertex_input = false;
>   location += vtn_var->patch ? VARYING_SLOT_PATCH0 : 
> VARYING_SLOT_VAR0;
>} else if (vtn_var->mode != vtn_variable_mode_uniform) {
>   vtn_warn("Location must be on input, output, uniform, sampler or "
> --
> 2.18.0
>
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For the series:
Reviewed-by: Anuj Phogat 
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[Mesa-dev] [PATCH 1/2] i965/misc: Use depth/stencil surf's tiling on gen4-5

[Nanley Chery]

Make the 3D engine aware of the depth/stencil surface's tiling before
doing any render operations.

Fixes fbe01625f6bf2cef6742e1ff0d3d44a2afec003e
("i965/miptree: Share tiling_flags in miptree_create").

Reported-by: Mark Janes 
---
 src/mesa/drivers/dri/i965/brw_misc_state.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 9a663b1d61c..5cf704ff0e9 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -267,6 +267,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
uint32_t depthbuffer_format = BRW_DEPTHFORMAT_D32_FLOAT;
uint32_t depth_offset = 0;
uint32_t width = 1, height = 1;
+   bool tiled_surface = true;
 
/* If there's a packed depth/stencil bound to stencil only, we need to
 * emit the packed depth/stencil buffer packet.
@@ -282,6 +283,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
   depth_offset = brw->depthstencil.depth_offset;
   width = depth_irb->Base.Base.Width;
   height = depth_irb->Base.Base.Height;
+  tiled_surface = depth_mt->surf.tiling != ISL_TILING_LINEAR;
}
 
const struct gen_device_info *devinfo = >screen->devinfo;
@@ -292,7 +294,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
  (depthbuffer_format << 18) |
  (BRW_TILEWALK_YMAJOR << 26) |
- (1 << 27) |
+ (tiled_surface << 27) |
  (depth_surface_type << 29));
 
if (depth_mt) {
-- 
2.18.0

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[Mesa-dev] [PATCH 2/2] intel/isl/gen4: Make depth/stencil buffers Y-Tiled

[Nanley Chery]

Rendering to a linear depth buffer on gen4 is causing a GPU hang in the
CI system. Until a better explanation is found, assume that errata is
applicable to all gen4 platforms.

Fixes fbe01625f6bf2cef6742e1ff0d3d44a2afec003e
("i965/miptree: Share tiling_flags in miptree_create").

Reported-by: Mark Janes 
---
 src/intel/isl/isl_gen4.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/intel/isl/isl_gen4.c b/src/intel/isl/isl_gen4.c
index 14706c895a5..a212d0ee0af 100644
--- a/src/intel/isl/isl_gen4.c
+++ b/src/intel/isl/isl_gen4.c
@@ -51,8 +51,15 @@ isl_gen4_filter_tiling(const struct isl_device *dev,
   /* From the g35 PRM Vol. 2, 3DSTATE_DEPTH_BUFFER::Tile Walk:
*
*"The Depth Buffer, if tiled, must use Y-Major tiling"
+   *
+   *Errata   DescriptionProject
+   *BWT014   The Depth Buffer Must be Tiled, it cannot be linear. This
+   *field must be set to 1 on DevBW-A.  [DevBW -A,B]
+   *
+   * In testing, the linear configuration doesn't seem to work on gen4.
*/
-  *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_Y0_BIT);
+  *flags &= (ISL_DEV_GEN(dev) == 4 && !ISL_DEV_IS_G4X(dev)) ?
+ISL_TILING_Y0_BIT : (ISL_TILING_Y0_BIT | 
ISL_TILING_LINEAR_BIT);
}
 
if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT |
-- 
2.18.0

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Re: [Mesa-dev] [PATCH] glsl: Allow ES2 function parameters to be hidden by variable declarations.

[Ilia Mirkin]

On Mon, Jul 16, 2018 at 7:51 PM, Eric Anholt  wrote:
> Ilia Mirkin  writes:
>
>> Perhaps use state->es_shader instead of is_version(0, 100)? [Just a
>> drive-by comment, not a real review, sorry]
>
> That doesn't respect the version overrides and such that is_version
> handles.

Under what circumstance would state->es_shader != state->is_version(0,
100)? I can't think of one, but perhaps I'm just insufficiently
creative.

  -ilia
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Re: [Mesa-dev] [PATCH] glsl: Allow ES2 function parameters to be hidden by variable declarations.

[Eric Anholt]

Ilia Mirkin  writes:

> Perhaps use state->es_shader instead of is_version(0, 100)? [Just a
> drive-by comment, not a real review, sorry]

That doesn't respect the version overrides and such that is_version
handles.


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Re: [Mesa-dev] [PATCH] egl: Use the canonical drm-uapi fourcc header to avoid local defines.

[Eric Anholt]

Jason Ekstrand  writes:

> Yes please!  Assuming it builds (i.e., those are actually in drm_fourcc.h),

It does.  The delta to upstream is at:

https://patchwork.freedesktop.org/patch/236876/


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Re: [Mesa-dev] [PATCH] egl: Use the canonical drm-uapi fourcc header to avoid local defines.

[Jason Ekstrand]

Yes please!  Assuming it builds (i.e., those are actually in drm_fourcc.h),

Reviewed-by: Jason Ekstrand 

On Mon, Jul 16, 2018 at 4:00 PM Eric Anholt  wrote:

> We should only use a #define locally once it's been upstreamed, and at
> that point you should just update our drm_fourcc.h.
> ---
>  src/egl/Android.mk  |  1 +
>  src/egl/Makefile.am |  1 +
>  src/egl/SConscript  |  1 +
>  src/egl/drivers/dri2/egl_dri2.c | 28 -
>  src/egl/drivers/dri2/platform_wayland.c |  8 ---
>  src/egl/meson.build |  2 +-
>  6 files changed, 4 insertions(+), 37 deletions(-)
>
> diff --git a/src/egl/Android.mk b/src/egl/Android.mk
> index 8412aeb7984a..11128ded93c8 100644
> --- a/src/egl/Android.mk
> +++ b/src/egl/Android.mk
> @@ -44,6 +44,7 @@ LOCAL_CFLAGS := \
> -DHAVE_ANDROID_PLATFORM
>
>  LOCAL_C_INCLUDES := \
> +   $(MESA_TOP)/include/drm-uapi \
> $(MESA_TOP)/src/egl/main \
> $(MESA_TOP)/src/egl/drivers/dri2
>
> diff --git a/src/egl/Makefile.am b/src/egl/Makefile.am
> index 1a2273b8c316..b43805d991a4 100644
> --- a/src/egl/Makefile.am
> +++ b/src/egl/Makefile.am
> @@ -27,6 +27,7 @@ BUILT_SOURCES =
>
>  AM_CFLAGS = \
> -I$(top_srcdir)/include \
> +   -I$(top_srcdir)/include/drm-uapi \
> -I$(top_srcdir)/src/mapi \
> -I$(top_srcdir)/src/egl/main \
> -I$(top_srcdir)/src/gbm/main \
> diff --git a/src/egl/SConscript b/src/egl/SConscript
> index 927092d22847..153fdc089234 100644
> --- a/src/egl/SConscript
> +++ b/src/egl/SConscript
> @@ -8,6 +8,7 @@ env = env.Clone()
>
>  env.Append(CPPPATH = [
>  '#/include',
> +'#/include/drm-uapi',
>  '#/include/HaikuGL',
>  '#/src/egl/main',
>  '#/src',
> diff --git a/src/egl/drivers/dri2/egl_dri2.c
> b/src/egl/drivers/dri2/egl_dri2.c
> index 27251ed3639d..a2d2d1c86070 100644
> --- a/src/egl/drivers/dri2/egl_dri2.c
> +++ b/src/egl/drivers/dri2/egl_dri2.c
> @@ -65,34 +65,6 @@
>  #include "util/u_vector.h"
>  #include "mapi/glapi/glapi.h"
>
> -/* The kernel header drm_fourcc.h defines the DRM formats below.  We
> duplicate
> - * some of the definitions here so that building Mesa won't bleeding-edge
> - * kernel headers.
> - */
> -#ifndef DRM_FORMAT_R8
> -#define DRM_FORMAT_R8fourcc_code('R', '8', ' ', ' ') /* [7:0]
> R */
> -#endif
> -
> -#ifndef DRM_FORMAT_RG88
> -#define DRM_FORMAT_RG88  fourcc_code('R', 'G', '8', '8') /*
> [15:0] R:G 8:8 little endian */
> -#endif
> -
> -#ifndef DRM_FORMAT_GR88
> -#define DRM_FORMAT_GR88  fourcc_code('G', 'R', '8', '8') /*
> [15:0] G:R 8:8 little endian */
> -#endif
> -
> -#ifndef DRM_FORMAT_R16
> -#define DRM_FORMAT_R16   fourcc_code('R', '1', '6', ' ') /*
> [15:0] R 16 little endian */
> -#endif
> -
> -#ifndef DRM_FORMAT_GR1616
> -#define DRM_FORMAT_GR1616fourcc_code('G', 'R', '3', '2') /*
> [31:0] R:G 16:16 little endian */
> -#endif
> -
> -#ifndef DRM_FORMAT_MOD_INVALID
> -#define DRM_FORMAT_MOD_INVALID ((1ULL<<56) - 1)
> -#endif
> -
>  #define NUM_ATTRIBS 12
>
>  static void
> diff --git a/src/egl/drivers/dri2/platform_wayland.c
> b/src/egl/drivers/dri2/platform_wayland.c
> index 11026f9fbf4b..294a6eddd606 100644
> --- a/src/egl/drivers/dri2/platform_wayland.c
> +++ b/src/egl/drivers/dri2/platform_wayland.c
> @@ -50,14 +50,6 @@
>  #include "wayland-drm-client-protocol.h"
>  #include "linux-dmabuf-unstable-v1-client-protocol.h"
>
> -#ifndef DRM_FORMAT_MOD_INVALID
> -#define DRM_FORMAT_MOD_INVALID ((1ULL << 56) - 1)
> -#endif
> -
> -#ifndef DRM_FORMAT_MOD_LINEAR
> -#define DRM_FORMAT_MOD_LINEAR 0
> -#endif
> -
>  /*
>   * The index of entries in this table is used as a bitmask in
>   * dri2_dpy->formats, which tracks the formats supported by our server.
> diff --git a/src/egl/meson.build b/src/egl/meson.build
> index 5f30bbba89a2..89a84fd89080 100644
> --- a/src/egl/meson.build
> +++ b/src/egl/meson.build
> @@ -24,7 +24,7 @@ inc_egl_dri2 = include_directories('drivers/dri2')
>  c_args_for_egl = []
>  link_for_egl = []
>  deps_for_egl = []
> -incs_for_egl = [inc_include, inc_src, inc_egl]
> +incs_for_egl = [inc_include, inc_drm_uapi, inc_src, inc_egl]
>
>  files_egl = files(
>'main/eglapi.c',
> --
> 2.18.0
>
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[Mesa-dev] [PATCH] egl: Use the canonical drm-uapi fourcc header to avoid local defines.

[Eric Anholt]

We should only use a #define locally once it's been upstreamed, and at
that point you should just update our drm_fourcc.h.
---
 src/egl/Android.mk  |  1 +
 src/egl/Makefile.am |  1 +
 src/egl/SConscript  |  1 +
 src/egl/drivers/dri2/egl_dri2.c | 28 -
 src/egl/drivers/dri2/platform_wayland.c |  8 ---
 src/egl/meson.build |  2 +-
 6 files changed, 4 insertions(+), 37 deletions(-)

diff --git a/src/egl/Android.mk b/src/egl/Android.mk
index 8412aeb7984a..11128ded93c8 100644
--- a/src/egl/Android.mk
+++ b/src/egl/Android.mk
@@ -44,6 +44,7 @@ LOCAL_CFLAGS := \
-DHAVE_ANDROID_PLATFORM
 
 LOCAL_C_INCLUDES := \
+   $(MESA_TOP)/include/drm-uapi \
$(MESA_TOP)/src/egl/main \
$(MESA_TOP)/src/egl/drivers/dri2
 
diff --git a/src/egl/Makefile.am b/src/egl/Makefile.am
index 1a2273b8c316..b43805d991a4 100644
--- a/src/egl/Makefile.am
+++ b/src/egl/Makefile.am
@@ -27,6 +27,7 @@ BUILT_SOURCES =
 
 AM_CFLAGS = \
-I$(top_srcdir)/include \
+   -I$(top_srcdir)/include/drm-uapi \
-I$(top_srcdir)/src/mapi \
-I$(top_srcdir)/src/egl/main \
-I$(top_srcdir)/src/gbm/main \
diff --git a/src/egl/SConscript b/src/egl/SConscript
index 927092d22847..153fdc089234 100644
--- a/src/egl/SConscript
+++ b/src/egl/SConscript
@@ -8,6 +8,7 @@ env = env.Clone()
 
 env.Append(CPPPATH = [
 '#/include',
+'#/include/drm-uapi',
 '#/include/HaikuGL',
 '#/src/egl/main',
 '#/src',
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 27251ed3639d..a2d2d1c86070 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -65,34 +65,6 @@
 #include "util/u_vector.h"
 #include "mapi/glapi/glapi.h"
 
-/* The kernel header drm_fourcc.h defines the DRM formats below.  We duplicate
- * some of the definitions here so that building Mesa won't bleeding-edge
- * kernel headers.
- */
-#ifndef DRM_FORMAT_R8
-#define DRM_FORMAT_R8fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
-#endif
-
-#ifndef DRM_FORMAT_RG88
-#define DRM_FORMAT_RG88  fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 
8:8 little endian */
-#endif
-
-#ifndef DRM_FORMAT_GR88
-#define DRM_FORMAT_GR88  fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 
8:8 little endian */
-#endif
-
-#ifndef DRM_FORMAT_R16
-#define DRM_FORMAT_R16   fourcc_code('R', '1', '6', ' ') /* [15:0] R 
16 little endian */
-#endif
-
-#ifndef DRM_FORMAT_GR1616
-#define DRM_FORMAT_GR1616fourcc_code('G', 'R', '3', '2') /* [31:0] R:G 
16:16 little endian */
-#endif
-
-#ifndef DRM_FORMAT_MOD_INVALID
-#define DRM_FORMAT_MOD_INVALID ((1ULL<<56) - 1)
-#endif
-
 #define NUM_ATTRIBS 12
 
 static void
diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index 11026f9fbf4b..294a6eddd606 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -50,14 +50,6 @@
 #include "wayland-drm-client-protocol.h"
 #include "linux-dmabuf-unstable-v1-client-protocol.h"
 
-#ifndef DRM_FORMAT_MOD_INVALID
-#define DRM_FORMAT_MOD_INVALID ((1ULL << 56) - 1)
-#endif
-
-#ifndef DRM_FORMAT_MOD_LINEAR
-#define DRM_FORMAT_MOD_LINEAR 0
-#endif
-
 /*
  * The index of entries in this table is used as a bitmask in
  * dri2_dpy->formats, which tracks the formats supported by our server.
diff --git a/src/egl/meson.build b/src/egl/meson.build
index 5f30bbba89a2..89a84fd89080 100644
--- a/src/egl/meson.build
+++ b/src/egl/meson.build
@@ -24,7 +24,7 @@ inc_egl_dri2 = include_directories('drivers/dri2')
 c_args_for_egl = []
 link_for_egl = []
 deps_for_egl = []
-incs_for_egl = [inc_include, inc_src, inc_egl]
+incs_for_egl = [inc_include, inc_drm_uapi, inc_src, inc_egl]
 
 files_egl = files(
   'main/eglapi.c',
-- 
2.18.0

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[Mesa-dev] [PATCH 07/11] intel/decoder: use snprintf(..., "%s", ...) instead of strncpy

[Caio Marcelo de Oliveira Filho]

strncpy() doesn't guarantee the terminator NUL, so we would need to
set ourselves. Just use snprintf() instead.

Fixes the warnings

../../src/intel/common/gen_decoder.c: In function ‘iter_decode_field’:
../../src/intel/common/gen_decoder.c:897:7: warning: ‘strncpy’ specified bound 
128 equals destination size [-Wstringop-truncation]
   strncpy(iter->name, iter->field->name, sizeof(iter->name));
   ^~
In function ‘iter_advance_field’,
inlined from ‘gen_field_iterator_next’ at 
../../src/intel/common/gen_decoder.c:1015:9:
../../src/intel/common/gen_decoder.c:844:7: warning: ‘strncpy’ specified bound 
128 equals destination size [-Wstringop-truncation]
   strncpy(iter->name, iter->field->name, sizeof(iter->name));
   ^~
---
 src/intel/common/gen_decoder.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index bb87192d23c..ec0a486b101 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -841,7 +841,7 @@ iter_advance_field(struct gen_field_iterator *iter)
}
 
if (iter->field->name)
-  strncpy(iter->name, iter->field->name, sizeof(iter->name));
+  snprintf(iter->name, sizeof(iter->name), "%s", iter->field->name);
else
   memset(iter->name, 0, sizeof(iter->name));
 
@@ -894,7 +894,7 @@ iter_decode_field(struct gen_field_iterator *iter)
} v;
 
if (iter->field->name)
-  strncpy(iter->name, iter->field->name, sizeof(iter->name));
+  snprintf(iter->name, sizeof(iter->name), "%s", iter->field->name);
else
   memset(iter->name, 0, sizeof(iter->name));
 
-- 
2.18.0

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[Mesa-dev] [PATCH 11/11] intel/blorp: fix uninitialized variable warning

[Caio Marcelo de Oliveira Filho]

Compiler doesn't pick up that level and start_layer will be defined,
so do as was done for num_layers in 4d8b476fa9a "intel/blorp: Fix
compiler warning about num_layers." and always set it.

Fixes warning

../../src/mesa/drivers/dri/i965/brw_blorp.c: In function 
‘brw_blorp_clear_depth_stencil’:
../../src/mesa/drivers/dri/i965/brw_blorp.c:1439:4: warning: ‘start_layer’ may 
be used uninitialized in this function [-Wmaybe-uninitialized]
blorp_clear_depth_stencil(, _surf, _surf,
^
  level, start_layer, num_layers,
  ~~~
  x0, y0, x1, y1,
  ~~~
  (mask & BUFFER_BIT_DEPTH), ctx->Depth.Clear,
  
  stencil_mask, ctx->Stencil.Clear);
  ~
../../src/mesa/drivers/dri/i965/brw_blorp.c:1439:4: warning: ‘level’ may be 
used uninitialized in this function [-Wmaybe-uninitialized]
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 9922c59f6e1..6192ace2253 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1413,10 +1413,10 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw,
  assert(level == irb->mt_level);
  assert(start_layer == irb->mt_layer);
  assert(num_layers == fb->MaxNumLayers ? irb->layer_count : 1);
-  } else {
- level = irb->mt_level;
- start_layer = irb->mt_layer;
   }
+
+  level = irb->mt_level;
+  start_layer = irb->mt_layer;
   num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
 
   stencil_mask = ctx->Stencil.WriteMask[0] & 0xff;
-- 
2.18.0

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[Mesa-dev] [PATCH 08/11] intel/batch-decoder: fix unitialized values warnings

[Caio Marcelo de Oliveira Filho]

Code assumes that all the necessary fields will exist, but compiler
doesn't know about this. Provide zero as default values, like in other
decoding functions.

Fixes warnings

../../src/intel/common/gen_batch_decoder.c: In function 
‘handle_media_interface_descriptor_load’:
../../src/intel/common/gen_batch_decoder.c:347:7: warning: 
‘binding_entry_count’ may be used uninitialized in this function 
[-Wmaybe-uninitialized]
   dump_binding_table(ctx, binding_table_offset, binding_entry_count);
   ^~
../../src/intel/common/gen_batch_decoder.c:347:7: warning: 
‘binding_table_offset’ may be used uninitialized in this function 
[-Wmaybe-uninitialized]

../../src/intel/common/gen_batch_decoder.c:346:7: warning: ‘sampler_count’ may 
be used uninitialized in this function [-Wmaybe-uninitialized]
   dump_samplers(ctx, sampler_offset, sampler_count);
   ^
../../src/intel/common/gen_batch_decoder.c:346:7: warning: ‘sampler_offset’ may 
be used uninitialized in this function [-Wmaybe-uninitialized]

../../src/intel/common/gen_batch_decoder.c:343:7: warning: ‘ksp’ may be used 
uninitialized in this function [-Wmaybe-uninitialized]
   ctx_disassemble_program(ctx, ksp, "compute shader");
   ^~~

../../src/intel/common/gen_batch_decoder.c: In function 
‘decode_dynamic_state_pointers’:
../../src/intel/common/gen_batch_decoder.c:663:54: warning: ‘state_offset’ may 
be used uninitialized in this function [-Wmaybe-uninitialized]
const uint32_t *state_map = ctx->dynamic_base.map + state_offset;
~~^~

../../src/intel/common/gen_batch_decoder.c: In function ‘gen_print_batch’:
../../src/intel/common/gen_batch_decoder.c:856:13: warning: ‘next_batch.map’ 
may be used uninitialized in this function [-Wmaybe-uninitialized]
  if (next_batch.map == NULL) {
 ^
../../src/intel/common/gen_batch_decoder.c:860:13: warning: ‘next_batch.addr’ 
may be used uninitialized in this function [-Wmaybe-uninitialized]
 gen_print_batch(ctx, next_batch.map, next_batch.size,
 ^
 next_batch.addr);
 
---
 src/intel/common/gen_batch_decoder.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/intel/common/gen_batch_decoder.c 
b/src/intel/common/gen_batch_decoder.c
index fe7536da9ec..727cbb80cfb 100644
--- a/src/intel/common/gen_batch_decoder.c
+++ b/src/intel/common/gen_batch_decoder.c
@@ -323,9 +323,9 @@ handle_media_interface_descriptor_load(struct 
gen_batch_decode_ctx *ctx,
   ctx_print_group(ctx, desc, desc_addr, desc_map);
 
   gen_field_iterator_init(, desc, desc_map, 0, false);
-  uint64_t ksp;
-  uint32_t sampler_offset, sampler_count;
-  uint32_t binding_table_offset, binding_entry_count;
+  uint64_t ksp = 0;
+  uint32_t sampler_offset = 0, sampler_count = 0;
+  uint32_t binding_table_offset = 0, binding_entry_count = 0;
   while (gen_field_iterator_next()) {
  if (strcmp(iter.name, "Kernel Start Pointer") == 0) {
 ksp = strtoll(iter.value, NULL, 16);
@@ -648,7 +648,7 @@ decode_dynamic_state_pointers(struct gen_batch_decode_ctx 
*ctx,
struct gen_group *inst = gen_spec_find_instruction(ctx->spec, p);
struct gen_group *state = gen_spec_find_struct(ctx->spec, struct_type);
 
-   uint32_t state_offset;
+   uint32_t state_offset = 0;
 
struct gen_field_iterator iter;
gen_field_iterator_init(, inst, p, 0, false);
@@ -841,7 +841,7 @@ gen_print_batch(struct gen_batch_decode_ctx *ctx,
   }
 
   if (strcmp(inst_name, "MI_BATCH_BUFFER_START") == 0) {
- struct gen_batch_decode_bo next_batch;
+ struct gen_batch_decode_bo next_batch = {};
  bool second_level;
  struct gen_field_iterator iter;
  gen_field_iterator_init(, inst, p, 0, false);
-- 
2.18.0

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[Mesa-dev] [PATCH 05/11] anv: avoid warning when switching in VkStructureType

[Caio Marcelo de Oliveira Filho]

When one of the cases is not part of the enum, the compilar complains:

../../src/intel/vulkan/anv_formats.c: In function 
‘anv_GetPhysicalDeviceFormatProperties2’:
../../src/intel/vulkan/anv_formats.c:728:7: warning: case value ‘101004’ 
not in enumerated type ‘VkStructureType’ {aka ‘enum VkStructureType’} [-Wswitch]
   case VK_STRUCTURE_TYPE_WSI_FORMAT_MODIFIER_PROPERTIES_LIST_MESA:
   ^~~~

Given the switch has an "default:" case, we don't lose anything by
switching on the unsigned value to avoid the warning.
---
 src/intel/vulkan/anv_formats.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 0c5b8d3a2c8..815b320a826 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -724,7 +724,8 @@ void anv_GetPhysicalDeviceFormatProperties2(
  >formatProperties);
 
vk_foreach_struct(ext, pFormatProperties->pNext) {
-  switch (ext->sType) {
+  /* Use unsigned since some cases are not in the VkStructureType enum. */
+  switch ((unsigned)ext->sType) {
   case VK_STRUCTURE_TYPE_WSI_FORMAT_MODIFIER_PROPERTIES_LIST_MESA:
  get_wsi_format_modifier_properties_list(physical_device, format,
  (void *)ext);
-- 
2.18.0

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[Mesa-dev] [PATCH 10/11] util/string_buffer: fix warning in tests

[Caio Marcelo de Oliveira Filho]

And also specify the maximum size when writing to static buffers. The
warning below refers to the case where "str5" could be larger than
"str5 - str4", then the strcat would have overlapping dst and src.

Compiler doesn't pick up the bound from the snprintf above, so we make
clear the bounds of str5 by using strncat() instead of strcat().

../../src/util/tests/string_buffer/string_buffer_test.cpp: In member function 
‘virtual void string_buffer_string_buffer_tests_Test::TestBody()’:
../../src/util/tests/string_buffer/string_buffer_test.cpp:106:10: warning: 
‘char* strcat(char*, const char*)’ accessing 81 or more bytes at offsets 48 and 
128 may overlap 1 byte at offset 128 [-Wrestrict]
strcat(str4, str5);
~~^~~~
---
 src/util/tests/string_buffer/string_buffer_test.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/util/tests/string_buffer/string_buffer_test.cpp 
b/src/util/tests/string_buffer/string_buffer_test.cpp
index 545f607fadd..afb6dfb2a19 100644
--- a/src/util/tests/string_buffer/string_buffer_test.cpp
+++ b/src/util/tests/string_buffer/string_buffer_test.cpp
@@ -95,15 +95,15 @@ TEST_F(string_buffer, string_buffer_tests)
EXPECT_TRUE(strlen(buf->buf) == 0);
 
/* Test a string with some formatting */
-   sprintf(str4, "Testing formatting %d, %f", 100, 1.0);
+   snprintf(str4, sizeof(str4), "Testing formatting %d, %f", 100, 1.0);
EXPECT_TRUE(_mesa_string_buffer_printf(buf, "Testing formatting %d, %f", 
100, 1.0));
EXPECT_TRUE(strcmp(buf->buf, str4) == 0);
 
/* Compile a string with some other formatting */
-   sprintf(str5, "Testing formatting %d, %x", 100, 0xDEADBEAF);
+   snprintf(str5, sizeof(str5), "Testing formatting %d, %x", 100, 0xDEADBEAF);
 
/* Concatenate str5 to str4 */
-   strcat(str4, str5);
+   strncat(str4, str5, sizeof(str5));
 
/* Now use the formatted append function again */
EXPECT_TRUE(_mesa_string_buffer_printf(buf, "Testing formatting %d, %x", 
100, 0xDEADBEAF));
-- 
2.18.0

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[Mesa-dev] [PATCH 01/11] spirv: initialize is_vertex_input

[Caio Marcelo de Oliveira Filho]

Fixes warning:

../../src/compiler/spirv/vtn_variables.c: In function ‘var_decoration_cb’:
../../src/compiler/spirv/vtn_variables.c:1400:12: warning: ‘is_vertex_input’ 
may be used uninitialized in this function [-Wmaybe-uninitialized]
   bool is_vertex_input;
^~~

The code used to set is_vertex_input in all possible codepaths, but
after 23edc5b1ef3 "spirv: translate default-block uniforms" the
compiler isn't sure all codepaths will initialize the variable.
---
 src/compiler/spirv/vtn_variables.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 6bd7aa1b0d5..fbfea6f8cef 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1397,10 +1397,9 @@ var_decoration_cb(struct vtn_builder *b, struct 
vtn_value *val, int member,
 */
if (dec->decoration == SpvDecorationLocation) {
   unsigned location = dec->literals[0];
-  bool is_vertex_input;
+  bool is_vertex_input = false;
   if (b->shader->info.stage == MESA_SHADER_FRAGMENT &&
   vtn_var->mode == vtn_variable_mode_output) {
- is_vertex_input = false;
  location += FRAG_RESULT_DATA0;
   } else if (b->shader->info.stage == MESA_SHADER_VERTEX &&
  vtn_var->mode == vtn_variable_mode_input) {
@@ -1408,7 +1407,6 @@ var_decoration_cb(struct vtn_builder *b, struct vtn_value 
*val, int member,
  location += VERT_ATTRIB_GENERIC0;
   } else if (vtn_var->mode == vtn_variable_mode_input ||
  vtn_var->mode == vtn_variable_mode_output) {
- is_vertex_input = false;
  location += vtn_var->patch ? VARYING_SLOT_PATCH0 : VARYING_SLOT_VAR0;
   } else if (vtn_var->mode != vtn_variable_mode_uniform) {
  vtn_warn("Location must be on input, output, uniform, sampler or "
-- 
2.18.0

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[Mesa-dev] [PATCH 09/11] i965/miptree: avoid uninitialized variable warnings

[Caio Marcelo de Oliveira Filho]

GCC 8.1.1 is having a hard time identifying that the values are
properly initialized when used. In the 'memset_value' case, we pass
the uninitialized value to another function (that will use only if the
conditions match the initialization).

Just give enough hint to the compiler to figure things out. Fixes the
warnings

../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c: In function 
‘intel_miptree_alloc_aux’:
../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1839:18: warning: 
‘memset_value’ may be used uninitialized in this function 
[-Wmaybe-uninitialized]
mt->aux_buf = intel_alloc_aux_buffer(brw, _surf, needs_memset,
  ^~~~
 memset_value);
 ~
../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1698:10: warning: 
‘initial_state’ may be used uninitialized in this function 
[-Wmaybe-uninitialized]
   if (wants_memset)
  ^
../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1772:23: note: 
‘initial_state’ was declared here
enum isl_aux_state initial_state;
   ^
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 7b1f0896ae9..a18d5ac3624 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1772,7 +1772,7 @@ intel_miptree_alloc_aux(struct brw_context *brw,
enum isl_aux_state initial_state;
uint8_t memset_value;
struct isl_surf aux_surf;
-   MAYBE_UNUSED bool aux_surf_ok;
+   MAYBE_UNUSED bool aux_surf_ok = false;
 
switch (mt->aux_usage) {
case ISL_AUX_USAGE_NONE:
@@ -1781,6 +1781,7 @@ intel_miptree_alloc_aux(struct brw_context *brw,
   break;
case ISL_AUX_USAGE_HIZ:
   initial_state = ISL_AUX_STATE_AUX_INVALID;
+  memset_value = 0;
   aux_surf_ok = isl_surf_get_hiz_surf(>isl_dev, >surf, _surf);
   break;
case ISL_AUX_USAGE_MCS:
-- 
2.18.0

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[Mesa-dev] [PATCH 04/11] glsl: remove unnecessary parenthesis from macro

[Caio Marcelo de Oliveira Filho]

The "__inst" will contain the name used for the variable of type
"__type *". Parenthesis is not necessary as the name itself shouldn't
be an expression.

Fixes warning:

In file included from ../../src/mesa/main/mtypes.h:49,
 from ../../src/intel/compiler/brw_compiler.h:30,
 from ../../src/intel/compiler/brw_shader.h:29,
 from ../../src/intel/compiler/brw_fs.h:31,
 from ../../src/intel/compiler/brw_fs_cse.cpp:24:
../../src/intel/compiler/brw_fs_cse.cpp: In member function ‘bool 
fs_visitor::opt_cse_local(bblock_t*)’:
../../src/compiler/glsl/list.h:675:12: warning: unnecessary parentheses in 
declaration of ‘entry’ [-Wparentheses]
__type *(__inst);  \
^
../../src/intel/compiler/brw_fs_cse.cpp:257:10: note: in expansion of macro 
‘foreach_in_list_use_after’
  foreach_in_list_use_after(aeb_entry, entry, ) {
  ^
---
 src/compiler/glsl/list.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/glsl/list.h b/src/compiler/glsl/list.h
index 2bfa2735544..59ed766f2e1 100644
--- a/src/compiler/glsl/list.h
+++ b/src/compiler/glsl/list.h
@@ -672,7 +672,7 @@ inline void exec_node::insert_before(exec_list *before)
 __node = __prev, __prev = (__type *)__prev->prev)
 
 #define foreach_in_list_use_after(__type, __inst, __list) \
-   __type *(__inst);  \
+   __type *__inst;\
for ((__inst) = (__type *)(__list)->head_sentinel.next; \
 !(__inst)->is_tail_sentinel();\
 (__inst) = (__type *)(__inst)->next)
-- 
2.18.0

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[Mesa-dev] [PATCH 06/11] anv: give more room to debug report

[Caio Marcelo de Oliveira Filho]

The error buffer is limited to 256, but the report contains the
filename and possibly other data. So give it more space.

Avoids the warnings

../../src/intel/vulkan/anv_util.c: In function ‘__anv_perf_warn’:
../../src/intel/vulkan/anv_util.c:66:42: warning: ‘%s’ directive output may be 
truncated writing up to 255 bytes into a region of size 254 
[-Wformat-truncation=]
snprintf(report, sizeof(report), "%s: %s", file, buffer);
  ^~ ~~
../../src/intel/vulkan/anv_util.c:66:4: note: ‘snprintf’ output 3 or more bytes 
(assuming 258) into a destination of size 256
snprintf(report, sizeof(report), "%s: %s", file, buffer);
^~~~

../../src/intel/vulkan/anv_util.c: In function ‘__vk_errorf’:
../../src/intel/vulkan/anv_util.c:96:48: warning: ‘%s’ directive output may be 
truncated writing up to 255 bytes into a region of size 252 
[-Wformat-truncation=]
   snprintf(report, sizeof(report), "%s:%d: %s (%s)", file, line, buffer,
^~~~
../../src/intel/vulkan/anv_util.c:96:7: note: ‘snprintf’ output 8 or more bytes 
(assuming 263) into a destination of size 256
   snprintf(report, sizeof(report), "%s:%d: %s (%s)", file, line, buffer,
   ^~
error_str);
~~
---
 src/intel/vulkan/anv_util.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_util.c b/src/intel/vulkan/anv_util.c
index 3c1803aa056..9082707624c 100644
--- a/src/intel/vulkan/anv_util.c
+++ b/src/intel/vulkan/anv_util.c
@@ -57,7 +57,7 @@ __anv_perf_warn(struct anv_instance *instance, const void 
*object,
 {
va_list ap;
char buffer[256];
-   char report[256];
+   char report[512];
 
va_start(ap, format);
vsnprintf(buffer, sizeof(buffer), format, ap);
@@ -84,7 +84,7 @@ __vk_errorf(struct anv_instance *instance, const void *object,
 {
va_list ap;
char buffer[256];
-   char report[256];
+   char report[512];
 
const char *error_str = vk_Result_to_str(error);
 
-- 
2.18.0

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[Mesa-dev] [PATCH 02/11] intel/compiler: silence -Wclass-memaccess warnings

[Caio Marcelo de Oliveira Filho]

G++ 8.1.1 suggests we shouldn't be setting and copying value from
instances of classes directly, so make clear this is what we want to
do.

---

I had mixed feelings about this fix. An alternative would be to
improve how fs_inst, fs_reg and other values are created and copied,
but it didn't seem worth doing that just for the sake of getting rid
of the warning. So, postponing such refactoring to a moment we need to
touch those classes for other reasons.

 src/intel/compiler/brw_fs.cpp   | 6 +++---
 src/intel/compiler/brw_vec4.cpp | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 2b8363ca362..8c8dfb706de 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -49,7 +49,7 @@ void
 fs_inst::init(enum opcode opcode, uint8_t exec_size, const fs_reg ,
   const fs_reg *src, unsigned sources)
 {
-   memset(this, 0, sizeof(*this));
+   memset((void*)this, 0, sizeof(*this));
 
this->src = new fs_reg[MAX2(sources, 3)];
for (unsigned i = 0; i < sources; i++)
@@ -131,7 +131,7 @@ fs_inst::fs_inst(enum opcode opcode, uint8_t exec_width, 
const fs_reg ,
 
 fs_inst::fs_inst(const fs_inst )
 {
-   memcpy(this, , sizeof(that));
+   memcpy((void*)this, , sizeof(that));
 
this->src = new fs_reg[MAX2(that.sources, 3)];
 
@@ -408,7 +408,7 @@ fs_inst::can_change_types() const
 void
 fs_reg::init()
 {
-   memset(this, 0, sizeof(*this));
+   memset((void*)this, 0, sizeof(*this));
type = BRW_REGISTER_TYPE_UD;
stride = 1;
 }
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index e0d6476dea6..4e242e03032 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -41,7 +41,7 @@ namespace brw {
 void
 src_reg::init()
 {
-   memset(this, 0, sizeof(*this));
+   memset((void*)this, 0, sizeof(*this));
this->file = BAD_FILE;
this->type = BRW_REGISTER_TYPE_UD;
 }
@@ -83,7 +83,7 @@ src_reg::src_reg(const dst_reg ) :
 void
 dst_reg::init()
 {
-   memset(this, 0, sizeof(*this));
+   memset((void*)this, 0, sizeof(*this));
this->file = BAD_FILE;
this->type = BRW_REGISTER_TYPE_UD;
this->writemask = WRITEMASK_XYZW;
-- 
2.18.0

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[Mesa-dev] [PATCH 03/11] intel/compiler: fix -Wsign-compare warning

[Caio Marcelo de Oliveira Filho]

Explicitly convert to signed integer. Conversion is valid since is the
same (implicitly) used to initialize the loop. Avoids the warning:

../../src/intel/compiler/brw_fs.cpp: In member function ‘bool 
fs_visitor::lower_simd_width()’:
../../src/intel/compiler/brw_fs.cpp:5761:45: warning: comparison of integer 
expressions of different signedness: ‘int’ and ‘unsigned int’ [-Wsign-compare]
 split_inst.eot = inst->eot && i == n - 1;
   ~~^~~~
---
 src/intel/compiler/brw_fs.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 8c8dfb706de..7ddbd285fe2 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -5758,7 +5758,7 @@ fs_visitor::lower_simd_width()
  */
 fs_inst split_inst = *inst;
 split_inst.exec_size = lower_width;
-split_inst.eot = inst->eot && i == n - 1;
+split_inst.eot = inst->eot && i == int(n - 1);
 
 /* Select the correct channel enables for the i-th group, then
  * transform the sources and destination and emit the lowered
-- 
2.18.0

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Re: [Mesa-dev] [PATCH 3/4] nir: allow nir_intrinsic_load_ubo in opt_peephole_select

[Timothy Arceri]

On 17/07/18 03:41, Eric Anholt wrote:

Timothy Arceri  writes:


This makes this opt behave more like the GLSL IR opt
lower_if_to_cond_assign(). With this we can disable that GLSL IR
opt on drivers with a NIR backend without causing spill
regressions.

shader-db results for radeonsi (RX580):

Totals from affected shaders:
SGPRS: 12200 -> 13072 (7.15 %)
VGPRS: 13496 -> 11840 (-12.27 %)
Spilled SGPRs: 285 -> 290 (1.75 %)
Spilled VGPRs: 115 -> 0 (-100.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 116 -> 0 (-100.00 %) dwords per thread
Code Size: 781304 -> 770168 (-1.43 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 1558 -> 1586 (1.80 %)
Wait states: 0 -> 0 (0.00 %)


Moving UBO loads out of conditionals seems questionable to me, and
I don't think shader-db would represent the effect of this kind of code
transformation well.  I'd love to see some actual performance numbers on
affected applications.

That said, lower_if_to_cond_assign() was already doing this, and I'm
assuming these shader-db stats are just from
with-glsl-optimization-disabled to with-nir-patch. 


No these results are with lower_if_to_cond_assign() still turned on.

The biggest gain seemed to come from a few shaders with a bunch of 
consecutive if's. It enables a chain of phis to be eliminated and 
reduces a bunch of VGPR spilling. Maybe we should look at that more 
closely on its own.


I'll hold onto this patch for now.


So, while we should
probably investigate tuning this, since it lets us dump some GLSL
optimization:

Acked-by: Eric Anholt 


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Re: [Mesa-dev] [PATCH 4/4] winsys/amdgpu: fix VDPAU interop by having one amdgpu_winsys_bo per BO

[Leo Liu]

On 2018-07-16 04:01 PM, Marek Olšák wrote:

From: Marek Olšák 

Dependencies between rings are inserted correctly if a buffer is
represented by only one unique amdgpu_winsys_bo instance.
Use a hash table keyed by amdgpu_bo_handle to have exactly one
amdgpu_winsys_bo per amdgpu_bo_handle.

The series are:
Tested-by: Leo Liu 



v2: return offset and stride properly
---
  src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 36 ---
  src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c |  5 +++
  src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h |  5 +++
  3 files changed, 41 insertions(+), 5 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index d9192c209e2..80563d3df98 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -21,20 +21,21 @@
   * USE OR OTHER DEALINGS IN THE SOFTWARE.
   *
   * The above copyright notice and this permission notice (including the
   * next paragraph) shall be included in all copies or substantial portions
   * of the Software.
   */
  
  #include "amdgpu_cs.h"
  
  #include "util/os_time.h"

+#include "util/u_hash_table.h"
  #include "state_tracker/drm_driver.h"
  #include 
  #include 
  #include 
  #include 
  
  #ifndef AMDGPU_GEM_CREATE_VM_ALWAYS_VALID

  #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
  #endif
  
@@ -172,20 +173,24 @@ void amdgpu_bo_destroy(struct pb_buffer *_buf)
  
 assert(bo->bo && "must not be called for slab entries");
  
 if (ws->debug_all_bos) {

simple_mtx_lock(>global_bo_list_lock);
LIST_DEL(>u.real.global_list_item);
ws->num_buffers--;
simple_mtx_unlock(>global_bo_list_lock);
 }
  
+   simple_mtx_lock(>bo_export_table_lock);

+   util_hash_table_remove(ws->bo_export_table, bo->bo);
+   simple_mtx_unlock(>bo_export_table_lock);
+
 amdgpu_bo_va_op(bo->bo, 0, bo->base.size, bo->va, 0, AMDGPU_VA_OP_UNMAP);
 amdgpu_va_range_free(bo->u.real.va_handle);
 amdgpu_bo_free(bo->bo);
  
 amdgpu_bo_remove_fences(bo);
  
 if (bo->initial_domain & RADEON_DOMAIN_VRAM)

ws->allocated_vram -= align64(bo->base.size, ws->info.gart_page_size);
 else if (bo->initial_domain & RADEON_DOMAIN_GTT)
ws->allocated_gtt -= align64(bo->base.size, ws->info.gart_page_size);
@@ -1278,24 +1283,41 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct 
radeon_winsys *rws,
 case WINSYS_HANDLE_TYPE_SHARED:
type = amdgpu_bo_handle_type_gem_flink_name;
break;
 case WINSYS_HANDLE_TYPE_FD:
type = amdgpu_bo_handle_type_dma_buf_fd;
break;
 default:
return NULL;
 }
  
+   if (stride)

+  *stride = whandle->stride;
+   if (offset)
+  *offset = whandle->offset;
+
 r = amdgpu_bo_import(ws->dev, type, whandle->handle, );
 if (r)
return NULL;
  
+   simple_mtx_lock(>bo_export_table_lock);

+   bo = util_hash_table_get(ws->bo_export_table, result.buf_handle);
+
+   /* If the amdgpu_winsys_bo instance already exists, bump the reference
+* counter and return it.
+*/
+   if (bo) {
+  p_atomic_inc(>base.reference.count);
+  simple_mtx_unlock(>bo_export_table_lock);
+  return >base;
+   }
+
 /* Get initial domains. */
 r = amdgpu_bo_query_info(result.buf_handle, );
 if (r)
goto error;
  
 r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general,

   result.alloc_size, 1 << 20, 0, , _handle,
 AMDGPU_VA_RANGE_HIGH);
 if (r)
goto error;
@@ -1319,49 +1341,49 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct 
radeon_winsys *rws,
 bo->bo = result.buf_handle;
 bo->base.size = result.alloc_size;
 bo->base.vtbl = _winsys_bo_vtbl;
 bo->ws = ws;
 bo->va = va;
 bo->u.real.va_handle = va_handle;
 bo->initial_domain = initial;
 bo->unique_id = __sync_fetch_and_add(>next_bo_unique_id, 1);
 bo->is_shared = true;
  
-   if (stride)

-  *stride = whandle->stride;
-   if (offset)
-  *offset = whandle->offset;
-
 if (bo->initial_domain & RADEON_DOMAIN_VRAM)
ws->allocated_vram += align64(bo->base.size, ws->info.gart_page_size);
 else if (bo->initial_domain & RADEON_DOMAIN_GTT)
ws->allocated_gtt += align64(bo->base.size, ws->info.gart_page_size);
  
 amdgpu_add_buffer_to_global_list(bo);
  
+   util_hash_table_set(ws->bo_export_table, bo->bo, bo);

+   simple_mtx_unlock(>bo_export_table_lock);
+
 return >base;
  
  error:

+   simple_mtx_unlock(>bo_export_table_lock);
 if (bo)
FREE(bo);
 if (va_handle)
amdgpu_va_range_free(va_handle);
 amdgpu_bo_free(result.buf_handle);
 return NULL;
  }
  
  static bool amdgpu_bo_get_handle(struct pb_buffer *buffer,

   unsigned stride, unsigned offset,
   unsigned slice_size,
   

Re: [Mesa-dev] [PATCH] glsl: Allow ES2 function parameters to be hidden by variable declarations.

[Ilia Mirkin]

Perhaps use state->es_shader instead of is_version(0, 100)? [Just a
drive-by comment, not a real review, sorry]

On Mon, Jul 16, 2018 at 5:46 PM, Eric Anholt  wrote:
> This fixes dEQP case:
>
> dEQP-GLES2.functional.shaders.scoping.valid.local_variable_hides_function_parameter_fragment
>
> without breaking
>
> dEQP-GLES3.functional.shaders.scoping.invalid.local_variable_hides_function_parameter_fragment
> ---
>  src/compiler/glsl/ast_to_hir.cpp | 9 +
>  1 file changed, 9 insertions(+)
>
> diff --git a/src/compiler/glsl/ast_to_hir.cpp 
> b/src/compiler/glsl/ast_to_hir.cpp
> index dd60a2a87fd5..28f074ca8a39 100644
> --- a/src/compiler/glsl/ast_to_hir.cpp
> +++ b/src/compiler/glsl/ast_to_hir.cpp
> @@ -6180,10 +6180,19 @@ ast_function_definition::hir(exec_list *instructions,
>}
> }
>
> +   /* On ES2, function parameters may be redeclared to be hidden within the
> +* function.  Do this by creating a new scope inside the function.
> +*/
> +   if (state->is_version(0, 100) && !state->is_version(0, 300))
> +  state->symbols->push_scope();
> +
> /* Convert the body of the function to HIR. */
> this->body->hir(>body, state);
> signature->is_defined = true;
>
> +   if (state->is_version(0, 100) && !state->is_version(0, 300))
> +  state->symbols->pop_scope();
> +
> state->symbols->pop_scope();
>
> assert(state->current_function == signature);
> --
> 2.18.0
>
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[Mesa-dev] [PATCH] glsl: Allow ES2 function parameters to be hidden by variable declarations.

[Eric Anholt]

This fixes dEQP case:

dEQP-GLES2.functional.shaders.scoping.valid.local_variable_hides_function_parameter_fragment

without breaking

dEQP-GLES3.functional.shaders.scoping.invalid.local_variable_hides_function_parameter_fragment
---
 src/compiler/glsl/ast_to_hir.cpp | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index dd60a2a87fd5..28f074ca8a39 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -6180,10 +6180,19 @@ ast_function_definition::hir(exec_list *instructions,
   }
}
 
+   /* On ES2, function parameters may be redeclared to be hidden within the
+* function.  Do this by creating a new scope inside the function.
+*/
+   if (state->is_version(0, 100) && !state->is_version(0, 300))
+  state->symbols->push_scope();
+
/* Convert the body of the function to HIR. */
this->body->hir(>body, state);
signature->is_defined = true;
 
+   if (state->is_version(0, 100) && !state->is_version(0, 300))
+  state->symbols->pop_scope();
+
state->symbols->pop_scope();
 
assert(state->current_function == signature);
-- 
2.18.0

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[Mesa-dev] [PATCH 4/4] winsys/amdgpu: fix VDPAU interop by having one amdgpu_winsys_bo per BO

[Marek Olšák]

From: Marek Olšák 

Dependencies between rings are inserted correctly if a buffer is
represented by only one unique amdgpu_winsys_bo instance.
Use a hash table keyed by amdgpu_bo_handle to have exactly one
amdgpu_winsys_bo per amdgpu_bo_handle.

v2: return offset and stride properly
---
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 36 ---
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c |  5 +++
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h |  5 +++
 3 files changed, 41 insertions(+), 5 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index d9192c209e2..80563d3df98 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -21,20 +21,21 @@
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
  * The above copyright notice and this permission notice (including the
  * next paragraph) shall be included in all copies or substantial portions
  * of the Software.
  */
 
 #include "amdgpu_cs.h"
 
 #include "util/os_time.h"
+#include "util/u_hash_table.h"
 #include "state_tracker/drm_driver.h"
 #include 
 #include 
 #include 
 #include 
 
 #ifndef AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
 #endif
 
@@ -172,20 +173,24 @@ void amdgpu_bo_destroy(struct pb_buffer *_buf)
 
assert(bo->bo && "must not be called for slab entries");
 
if (ws->debug_all_bos) {
   simple_mtx_lock(>global_bo_list_lock);
   LIST_DEL(>u.real.global_list_item);
   ws->num_buffers--;
   simple_mtx_unlock(>global_bo_list_lock);
}
 
+   simple_mtx_lock(>bo_export_table_lock);
+   util_hash_table_remove(ws->bo_export_table, bo->bo);
+   simple_mtx_unlock(>bo_export_table_lock);
+
amdgpu_bo_va_op(bo->bo, 0, bo->base.size, bo->va, 0, AMDGPU_VA_OP_UNMAP);
amdgpu_va_range_free(bo->u.real.va_handle);
amdgpu_bo_free(bo->bo);
 
amdgpu_bo_remove_fences(bo);
 
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
   ws->allocated_vram -= align64(bo->base.size, ws->info.gart_page_size);
else if (bo->initial_domain & RADEON_DOMAIN_GTT)
   ws->allocated_gtt -= align64(bo->base.size, ws->info.gart_page_size);
@@ -1278,24 +1283,41 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct 
radeon_winsys *rws,
case WINSYS_HANDLE_TYPE_SHARED:
   type = amdgpu_bo_handle_type_gem_flink_name;
   break;
case WINSYS_HANDLE_TYPE_FD:
   type = amdgpu_bo_handle_type_dma_buf_fd;
   break;
default:
   return NULL;
}
 
+   if (stride)
+  *stride = whandle->stride;
+   if (offset)
+  *offset = whandle->offset;
+
r = amdgpu_bo_import(ws->dev, type, whandle->handle, );
if (r)
   return NULL;
 
+   simple_mtx_lock(>bo_export_table_lock);
+   bo = util_hash_table_get(ws->bo_export_table, result.buf_handle);
+
+   /* If the amdgpu_winsys_bo instance already exists, bump the reference
+* counter and return it.
+*/
+   if (bo) {
+  p_atomic_inc(>base.reference.count);
+  simple_mtx_unlock(>bo_export_table_lock);
+  return >base;
+   }
+
/* Get initial domains. */
r = amdgpu_bo_query_info(result.buf_handle, );
if (r)
   goto error;
 
r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general,
  result.alloc_size, 1 << 20, 0, , _handle,
 AMDGPU_VA_RANGE_HIGH);
if (r)
   goto error;
@@ -1319,49 +1341,49 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct 
radeon_winsys *rws,
bo->bo = result.buf_handle;
bo->base.size = result.alloc_size;
bo->base.vtbl = _winsys_bo_vtbl;
bo->ws = ws;
bo->va = va;
bo->u.real.va_handle = va_handle;
bo->initial_domain = initial;
bo->unique_id = __sync_fetch_and_add(>next_bo_unique_id, 1);
bo->is_shared = true;
 
-   if (stride)
-  *stride = whandle->stride;
-   if (offset)
-  *offset = whandle->offset;
-
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
   ws->allocated_vram += align64(bo->base.size, ws->info.gart_page_size);
else if (bo->initial_domain & RADEON_DOMAIN_GTT)
   ws->allocated_gtt += align64(bo->base.size, ws->info.gart_page_size);
 
amdgpu_add_buffer_to_global_list(bo);
 
+   util_hash_table_set(ws->bo_export_table, bo->bo, bo);
+   simple_mtx_unlock(>bo_export_table_lock);
+
return >base;
 
 error:
+   simple_mtx_unlock(>bo_export_table_lock);
if (bo)
   FREE(bo);
if (va_handle)
   amdgpu_va_range_free(va_handle);
amdgpu_bo_free(result.buf_handle);
return NULL;
 }
 
 static bool amdgpu_bo_get_handle(struct pb_buffer *buffer,
  unsigned stride, unsigned offset,
  unsigned slice_size,
  struct winsys_handle *whandle)
 {
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(buffer);
+   struct amdgpu_winsys *ws = bo->ws;
enum amdgpu_bo_handle_type type;
int r;
 
/* Don't allow 

Re: [Mesa-dev] [PATCH v2] intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY.

[Kenneth Graunke]

On Thursday, July 12, 2018 5:47:48 AM PDT Sergii Romantsov wrote:
> SNB doesn't have a definition of 3DSTATE_CONSTANT_BODY, thats
> why we got segmentation fault when used INTEL_DEBUG=bat.
> Fixed by adding of 3DSTATE_CONSTANT_BODY into 3DSTATE_CONSTANT
> of VS, GS and PS structures.
> 
> v2: added definition of 3DSTATE_CONSTANT_BODY to the gen6.xml
> 
> Fixes: 169d8e011ae (intel: Fix 3DSTATE_CONSTANT buffer decoding.)
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107190
> Signed-off-by: Sergii Romantsov 
> ---
>  src/intel/genxml/gen6.xml | 38 
> ++-
>  src/mesa/drivers/dri/i965/genX_state_upload.c | 12 -
>  2 files changed, 20 insertions(+), 30 deletions(-)

Reviewed-by: Kenneth Graunke 

and pushed:

To ssh://gitlab.freedesktop.org/mesa/mesa
   4054133dcce..cec540fbc6f  master -> master


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Re: [Mesa-dev] [PATCH v4 2/4] r600 shader: Add extra function to evaluate array index

[Ilia Mirkin]

On Mon, Jul 16, 2018 at 4:26 AM, Gert Wollny  wrote:
> From: Gert Wollny 
>
> The added function evaluates the array index according to the function
>
> idx = floor(ai + 0.5);
>
> Signed-off-by: Gert Wollny 
> ---
>  src/gallium/drivers/r600/r600_shader.c | 34 
> ++
>  1 file changed, 34 insertions(+)
>
> diff --git a/src/gallium/drivers/r600/r600_shader.c 
> b/src/gallium/drivers/r600/r600_shader.c
> index 6655b000aa..e2f44afc05 100644
> --- a/src/gallium/drivers/r600/r600_shader.c
> +++ b/src/gallium/drivers/r600/r600_shader.c
> @@ -7448,6 +7448,40 @@ static int r600_do_buffer_txq(struct r600_shader_ctx 
> *ctx, int reg_idx, int offs
> }
>  }
>
> +/* Evaluate the texture array index according to floor(z+0.5) */
> +static int r600_shader_evaluate_array_index(struct r600_bytecode_alu *alu,
> + 
> int reg, int chan, int rel,
> + 
> struct r600_bytecode *bc)
> +{
> +   int r;
> +
> +   /* evaluate array index according to floor(z+0.5) */
> +   alu->op = ALU_OP2_ADD;
> +   alu->src[1].sel = V_SQ_ALU_SRC_0_5;
> +   alu->dst.sel = reg;
> +   alu->dst.chan = chan;
> +   alu->dst.rel = rel;
> +   alu->dst.write = 1;
> +   alu->last = 1;
> +   r = r600_bytecode_add_alu(bc, alu);
> +   if (r)
> +   return r;
> +
> +   memset(alu, 0, sizeof(struct r600_bytecode_alu));
> +   alu->op = ALU_OP1_FLOOR;
> +   alu->src[0].sel = reg;
> +   alu->src[0].chan = chan;
> +   alu->src[0].rel = rel;
> +   alu->dst.sel = reg;
> +   alu->dst.chan = chan;
> +   alu->dst.rel = rel;
> +   alu->dst.write = 1;
> +   alu->last = 1;
> +   r = r600_bytecode_add_alu(bc, alu);
> +   if (r)
> +   return r;
> +   return 0;

Why not use RNDNE? Then you don't have to add the 0.5...

  -ilia

> +}
>
>  static int tgsi_tex(struct r600_shader_ctx *ctx)
>  {
> --
> 2.16.4
>
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[Mesa-dev] [AppVeyor] mesa master #8305 completed

[AppVeyor]

Build mesa 8305 completed



Commit b3474645d4 by Roland Scheidegger on 7/14/2018 2:49 AM:

nir: fix msvc build\n\nEmpty initializer braces aren't valid c (it's a gnu extension, and\nit's valid in c++).\nHopefully fixes appveyor / msvc build...\n\nFixes a3150c1d06ae7766c3d3fe3b33432e55c3c7527e


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Re: [Mesa-dev] [PATCH 0/9] RadeonSI on AMDGPU: Command submission optimizations

[Marek Olšák]

On Mon, Jul 16, 2018 at 12:06 PM, Michel Dänzer  wrote:
> On 2018-07-13 08:35 PM, Marek Olšák wrote:
>> https://pastebin.com/raw/itNDpPv0
>>
>> Cleanups only: +10.85%
>> Total: +11.8%
>
> Thanks, that's more useful.
>
> If you pass all 3 data files to a single ministat -s invocation, it
> combines all of them in a single graph, and prints information about
> whether or not a difference was detected, and if yes, the interval in
> which the difference lies at 95% confidence.
>
>
> It might be even better to compare the total number of frames rendered
> in a fixed amount of time, with multiple runs for each test
> configuration, in case there is systemic variance between runs (e.g. due
> to ASLR).

While further comparison would be interesting to have, we don't have
the manpower to do further testing (and that includes testing the
effect of the noimport flag). We at least know there is "some" improvement, so
let's move onto something else.

Marek
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[Mesa-dev] [AppVeyor] mesa master #8304 failed

[AppVeyor]

Build mesa 8304 failed


Commit f378fa94b2 by Jason Ekstrand on 7/4/2018 2:18 AM:

nir/worklist: Rework the foreach macro\n\nThis makes the arguments match the (thing, container) pattern used in\nother nir_foreach macros and also renames it to make that a bit more\nclear.\n\nReviewed-by: Caio Marcelo de Oliveira Filho \nReviewed-by: Eric Anholt 


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Re: [Mesa-dev] [PATCH 1/3] nir/worklist: Rework the foreach macro

[Eric Anholt]

Jason Ekstrand  writes:

> This makes the arguments match the (thing, container) pattern used in
> other nir_foreach macros and also renames it to make that a bit more
> clear.

Yay, consistency!

Reviewed-by: Eric Anholt 


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Re: [Mesa-dev] [PATCH 3/4] nir: allow nir_intrinsic_load_ubo in opt_peephole_select

[Eric Anholt]

Timothy Arceri  writes:

> This makes this opt behave more like the GLSL IR opt
> lower_if_to_cond_assign(). With this we can disable that GLSL IR
> opt on drivers with a NIR backend without causing spill
> regressions.
>
> shader-db results for radeonsi (RX580):
>
> Totals from affected shaders:
> SGPRS: 12200 -> 13072 (7.15 %)
> VGPRS: 13496 -> 11840 (-12.27 %)
> Spilled SGPRs: 285 -> 290 (1.75 %)
> Spilled VGPRs: 115 -> 0 (-100.00 %)
> Private memory VGPRs: 0 -> 0 (0.00 %)
> Scratch size: 116 -> 0 (-100.00 %) dwords per thread
> Code Size: 781304 -> 770168 (-1.43 %) bytes
> LDS: 0 -> 0 (0.00 %) blocks
> Max Waves: 1558 -> 1586 (1.80 %)
> Wait states: 0 -> 0 (0.00 %)

Moving UBO loads out of conditionals seems questionable to me, and
I don't think shader-db would represent the effect of this kind of code
transformation well.  I'd love to see some actual performance numbers on
affected applications.

That said, lower_if_to_cond_assign() was already doing this, and I'm
assuming these shader-db stats are just from
with-glsl-optimization-disabled to with-nir-patch.  So, while we should
probably investigate tuning this, since it lets us dump some GLSL
optimization:

Acked-by: Eric Anholt 


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[Mesa-dev] [PATCH 1/4] winsys/amdgpu: shorten bo->ws in amdgpu_bo_destroy

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 19 ++-
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index eba8d6e8b3d..94210ab3df6 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -161,47 +161,48 @@ static void amdgpu_bo_remove_fences(struct 
amdgpu_winsys_bo *bo)
   amdgpu_fence_reference(>fences[i], NULL);
 
FREE(bo->fences);
bo->num_fences = 0;
bo->max_fences = 0;
 }
 
 void amdgpu_bo_destroy(struct pb_buffer *_buf)
 {
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
+   struct amdgpu_winsys *ws = bo->ws;
 
assert(bo->bo && "must not be called for slab entries");
 
-   if (bo->ws->debug_all_bos) {
-  simple_mtx_lock(>ws->global_bo_list_lock);
+   if (ws->debug_all_bos) {
+  simple_mtx_lock(>global_bo_list_lock);
   LIST_DEL(>u.real.global_list_item);
-  bo->ws->num_buffers--;
-  simple_mtx_unlock(>ws->global_bo_list_lock);
+  ws->num_buffers--;
+  simple_mtx_unlock(>global_bo_list_lock);
}
 
amdgpu_bo_va_op(bo->bo, 0, bo->base.size, bo->va, 0, AMDGPU_VA_OP_UNMAP);
amdgpu_va_range_free(bo->u.real.va_handle);
amdgpu_bo_free(bo->bo);
 
amdgpu_bo_remove_fences(bo);
 
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
-  bo->ws->allocated_vram -= align64(bo->base.size, 
bo->ws->info.gart_page_size);
+  ws->allocated_vram -= align64(bo->base.size, ws->info.gart_page_size);
else if (bo->initial_domain & RADEON_DOMAIN_GTT)
-  bo->ws->allocated_gtt -= align64(bo->base.size, 
bo->ws->info.gart_page_size);
+  ws->allocated_gtt -= align64(bo->base.size, ws->info.gart_page_size);
 
if (bo->u.real.map_count >= 1) {
   if (bo->initial_domain & RADEON_DOMAIN_VRAM)
- bo->ws->mapped_vram -= bo->base.size;
+ ws->mapped_vram -= bo->base.size;
   else if (bo->initial_domain & RADEON_DOMAIN_GTT)
- bo->ws->mapped_gtt -= bo->base.size;
-  bo->ws->num_mapped_buffers--;
+ ws->mapped_gtt -= bo->base.size;
+  ws->num_mapped_buffers--;
}
 
FREE(bo);
 }
 
 static void amdgpu_bo_destroy_or_cache(struct pb_buffer *_buf)
 {
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
 
assert(bo->bo); /* slab buffers have a separate vtbl */
-- 
2.17.1

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[Mesa-dev] [PATCH 2/4] winsys/amdgpu: clean up error handling in amdgpu_bo_from_handle

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 36 ++-
 1 file changed, 16 insertions(+), 20 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 94210ab3df6..b7f49a1159f 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -1260,71 +1260,69 @@ no_slab:
bo->u.real.use_reusable_pool = use_reusable_pool;
return >base;
 }
 
 static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws,
struct winsys_handle *whandle,
unsigned *stride,
unsigned *offset)
 {
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
-   struct amdgpu_winsys_bo *bo;
+   struct amdgpu_winsys_bo *bo = NULL;
enum amdgpu_bo_handle_type type;
struct amdgpu_bo_import_result result = {0};
uint64_t va;
-   amdgpu_va_handle va_handle;
+   amdgpu_va_handle va_handle = NULL;
struct amdgpu_bo_info info = {0};
enum radeon_bo_domain initial = 0;
int r;
 
-   /* Initialize the structure. */
-   bo = CALLOC_STRUCT(amdgpu_winsys_bo);
-   if (!bo) {
-  return NULL;
-   }
-
switch (whandle->type) {
case WINSYS_HANDLE_TYPE_SHARED:
   type = amdgpu_bo_handle_type_gem_flink_name;
   break;
case WINSYS_HANDLE_TYPE_FD:
   type = amdgpu_bo_handle_type_dma_buf_fd;
   break;
default:
   return NULL;
}
 
r = amdgpu_bo_import(ws->dev, type, whandle->handle, );
if (r)
-  goto error;
+  return NULL;
 
/* Get initial domains. */
r = amdgpu_bo_query_info(result.buf_handle, );
if (r)
-  goto error_query;
+  goto error;
 
r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general,
  result.alloc_size, 1 << 20, 0, , _handle,
 AMDGPU_VA_RANGE_HIGH);
if (r)
-  goto error_query;
+  goto error;
+
+   bo = CALLOC_STRUCT(amdgpu_winsys_bo);
+   if (!bo)
+  goto error;
 
r = amdgpu_bo_va_op(result.buf_handle, 0, result.alloc_size, va, 0, 
AMDGPU_VA_OP_MAP);
if (r)
-  goto error_va_map;
+  goto error;
 
if (info.preferred_heap & AMDGPU_GEM_DOMAIN_VRAM)
   initial |= RADEON_DOMAIN_VRAM;
if (info.preferred_heap & AMDGPU_GEM_DOMAIN_GTT)
   initial |= RADEON_DOMAIN_GTT;
 
-
+   /* Initialize the structure. */
pipe_reference_init(>base.reference, 1);
bo->base.alignment = info.phys_alignment;
bo->bo = result.buf_handle;
bo->base.size = result.alloc_size;
bo->base.vtbl = _winsys_bo_vtbl;
bo->ws = ws;
bo->va = va;
bo->u.real.va_handle = va_handle;
bo->initial_domain = initial;
bo->unique_id = __sync_fetch_and_add(>next_bo_unique_id, 1);
@@ -1339,28 +1337,26 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct 
radeon_winsys *rws,
   ws->allocated_vram += align64(bo->base.size, ws->info.gart_page_size);
else if (bo->initial_domain & RADEON_DOMAIN_GTT)
   ws->allocated_gtt += align64(bo->base.size, ws->info.gart_page_size);
 
amdgpu_bo_export(bo->bo, amdgpu_bo_handle_type_kms_noimport, 
>u.real.kms_handle);
 
amdgpu_add_buffer_to_global_list(bo);
 
return >base;
 
-error_va_map:
-   amdgpu_va_range_free(va_handle);
-
-error_query:
-   amdgpu_bo_free(result.buf_handle);
-
 error:
-   FREE(bo);
+   if (bo)
+  FREE(bo);
+   if (va_handle)
+  amdgpu_va_range_free(va_handle);
+   amdgpu_bo_free(result.buf_handle);
return NULL;
 }
 
 static bool amdgpu_bo_get_handle(struct pb_buffer *buffer,
  unsigned stride, unsigned offset,
  unsigned slice_size,
  struct winsys_handle *whandle)
 {
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(buffer);
enum amdgpu_bo_handle_type type;
-- 
2.17.1

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[Mesa-dev] [PATCH 3/4] winsys/amdgpu: use a better hash_pointer function

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 13 +
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index cca6a3cc25b..db7a4d7033c 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -24,20 +24,21 @@
  *
  * The above copyright notice and this permission notice (including the
  * next paragraph) shall be included in all copies or substantial portions
  * of the Software.
  */
 
 #include "amdgpu_cs.h"
 #include "amdgpu_public.h"
 
 #include "util/u_hash_table.h"
+#include "util/hash_table.h"
 #include 
 #include 
 #include 
 #include 
 #include "amd/common/sid.h"
 #include "amd/common/gfx9d.h"
 
 #ifndef AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS
 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS   0x1E
 #endif
@@ -180,30 +181,26 @@ static uint64_t amdgpu_query_value(struct radeon_winsys 
*rws,
 static bool amdgpu_read_registers(struct radeon_winsys *rws,
   unsigned reg_offset,
   unsigned num_registers, uint32_t *out)
 {
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 
return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
0x, 0, out) == 0;
 }
 
-static unsigned hash_dev(void *key)
+static unsigned hash_pointer(void *key)
 {
-#if defined(PIPE_ARCH_X86_64)
-   return pointer_to_intptr(key) ^ (pointer_to_intptr(key) >> 32);
-#else
-   return pointer_to_intptr(key);
-#endif
+   return _mesa_hash_pointer(key);
 }
 
-static int compare_dev(void *key1, void *key2)
+static int compare_pointers(void *key1, void *key2)
 {
return key1 != key2;
 }
 
 static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
 {
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
bool destroy;
 
/* When the reference counter drops to zero, remove the device pointer
@@ -245,21 +242,21 @@ amdgpu_winsys_create(int fd, const struct 
pipe_screen_config *config,
/* The DRM driver version of amdgpu is 3.x.x. */
if (version->version_major != 3) {
   drmFreeVersion(version);
   return NULL;
}
drmFreeVersion(version);
 
/* Look up the winsys from the dev table. */
simple_mtx_lock(_tab_mutex);
if (!dev_tab)
-  dev_tab = util_hash_table_create(hash_dev, compare_dev);
+  dev_tab = util_hash_table_create(hash_pointer, compare_pointers);
 
/* Initialize the amdgpu device. This should always return the same pointer
 * for the same fd. */
r = amdgpu_device_initialize(fd, _major, _minor, );
if (r) {
   simple_mtx_unlock(_tab_mutex);
   fprintf(stderr, "amdgpu: amdgpu_device_initialize failed.\n");
   return NULL;
}
 
-- 
2.17.1

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[Mesa-dev] [PATCH 4/4] winsys/amdgpu: fix VDPAU interop by having one amdgpu_winsys_bo per BO

[Marek Olšák]

From: Marek Olšák 

Dependencies between rings are inserted correctly if a buffer is
represented by only one unique amdgpu_winsys_bo instance.
Use a hash table keyed by amdgpu_bo_handle to have exactly one
amdgpu_winsys_bo per amdgpu_bo_handle.
---
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 26 +++
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c |  5 
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h |  5 
 3 files changed, 36 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index b7f49a1159f..3172e9bdde3 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -21,20 +21,21 @@
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
  * The above copyright notice and this permission notice (including the
  * next paragraph) shall be included in all copies or substantial portions
  * of the Software.
  */
 
 #include "amdgpu_cs.h"
 
 #include "util/os_time.h"
+#include "util/u_hash_table.h"
 #include "state_tracker/drm_driver.h"
 #include 
 #include 
 #include 
 #include 
 
 #ifndef AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
 #endif
 
@@ -172,20 +173,24 @@ void amdgpu_bo_destroy(struct pb_buffer *_buf)
 
assert(bo->bo && "must not be called for slab entries");
 
if (ws->debug_all_bos) {
   simple_mtx_lock(>global_bo_list_lock);
   LIST_DEL(>u.real.global_list_item);
   ws->num_buffers--;
   simple_mtx_unlock(>global_bo_list_lock);
}
 
+   simple_mtx_lock(>bo_export_table_lock);
+   util_hash_table_remove(ws->bo_export_table, bo->bo);
+   simple_mtx_unlock(>bo_export_table_lock);
+
amdgpu_bo_va_op(bo->bo, 0, bo->base.size, bo->va, 0, AMDGPU_VA_OP_UNMAP);
amdgpu_va_range_free(bo->u.real.va_handle);
amdgpu_bo_free(bo->bo);
 
amdgpu_bo_remove_fences(bo);
 
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
   ws->allocated_vram -= align64(bo->base.size, ws->info.gart_page_size);
else if (bo->initial_domain & RADEON_DOMAIN_GTT)
   ws->allocated_gtt -= align64(bo->base.size, ws->info.gart_page_size);
@@ -1284,20 +1289,32 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct 
radeon_winsys *rws,
   type = amdgpu_bo_handle_type_dma_buf_fd;
   break;
default:
   return NULL;
}
 
r = amdgpu_bo_import(ws->dev, type, whandle->handle, );
if (r)
   return NULL;
 
+   simple_mtx_lock(>bo_export_table_lock);
+   bo = util_hash_table_get(ws->bo_export_table, result.buf_handle);
+
+   /* If the amdgpu_winsys_bo instance already exists, bump the reference
+* counter and return it.
+*/
+   if (bo) {
+  p_atomic_inc(>base.reference.count);
+  simple_mtx_unlock(>bo_export_table_lock);
+  return >base;
+   }
+
/* Get initial domains. */
r = amdgpu_bo_query_info(result.buf_handle, );
if (r)
   goto error;
 
r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general,
  result.alloc_size, 1 << 20, 0, , _handle,
 AMDGPU_VA_RANGE_HIGH);
if (r)
   goto error;
@@ -1335,37 +1352,42 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct 
radeon_winsys *rws,
 
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
   ws->allocated_vram += align64(bo->base.size, ws->info.gart_page_size);
else if (bo->initial_domain & RADEON_DOMAIN_GTT)
   ws->allocated_gtt += align64(bo->base.size, ws->info.gart_page_size);
 
amdgpu_bo_export(bo->bo, amdgpu_bo_handle_type_kms_noimport, 
>u.real.kms_handle);
 
amdgpu_add_buffer_to_global_list(bo);
 
+   util_hash_table_set(ws->bo_export_table, bo->bo, bo);
+   simple_mtx_unlock(>bo_export_table_lock);
+
return >base;
 
 error:
+   simple_mtx_unlock(>bo_export_table_lock);
if (bo)
   FREE(bo);
if (va_handle)
   amdgpu_va_range_free(va_handle);
amdgpu_bo_free(result.buf_handle);
return NULL;
 }
 
 static bool amdgpu_bo_get_handle(struct pb_buffer *buffer,
  unsigned stride, unsigned offset,
  unsigned slice_size,
  struct winsys_handle *whandle)
 {
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(buffer);
+   struct amdgpu_winsys *ws = bo->ws;
enum amdgpu_bo_handle_type type;
int r;
 
/* Don't allow exports of slab entries and sparse buffers. */
if (!bo->bo)
   return false;
 
bo->u.real.use_reusable_pool = false;
 
switch (whandle->type) {
@@ -1379,20 +1401,24 @@ static bool amdgpu_bo_get_handle(struct pb_buffer 
*buffer,
   type = amdgpu_bo_handle_type_kms;
   break;
default:
   return false;
}
 
r = amdgpu_bo_export(bo->bo, type, >handle);
if (r)
   return false;
 
+   simple_mtx_lock(>bo_export_table_lock);
+   util_hash_table_set(ws->bo_export_table, bo->bo, bo);
+   simple_mtx_unlock(>bo_export_table_lock);
+
whandle->stride = stride;
   

Re: [Mesa-dev] [PATCH v8 33/33] nvir/nir: implement intrinsic shader_clock

[Karol Herbst]

On Mon, Jul 16, 2018 at 5:54 PM, Rhys Perry  wrote:
> The instructions should probably be marked as fixed so they aren't CSE'd.
>

mhh, but then also prevents us from doing DCE :/ I guess we can depend
on nir eliminating such high level instructions, but with TGSI we also
mark that as fixed, so I guess I just go ahead and change that. Thanks
for pointing that out.

> On Fri, Jun 29, 2018 at 11:32 PM, Karol Herbst  wrote:
>> Signed-off-by: Karol Herbst 
>> ---
>>  src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 8 
>>  1 file changed, 8 insertions(+)
>>
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp 
>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
>> index f4875113d00..ed2453136fd 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
>> @@ -2344,6 +2344,14 @@ Converter::visit(nir_intrinsic_instr *insn)
>>bar->subOp = getSubOp(op);
>>break;
>> }
>> +   case nir_intrinsic_shader_clock: {
>> +  const DataType dType = getDType(insn);
>> +  LValues  = convert(>dest);
>> +
>> +  loadImm(newDefs[0], 0u);
>> +  mkOp1v(OP_RDSV, dType, newDefs[1], mkSysVal(SV_CLOCK, 0));
>> +  break;
>> +   }
>> default:
>>ERROR("unknown nir_intrinsic_op %s\n", nir_intrinsic_infos[op].name);
>>return false;
>> --
>> 2.17.1
>>
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Re: [Mesa-dev] [PATCH 0/9] RadeonSI on AMDGPU: Command submission optimizations

[Michel Dänzer]

On 2018-07-13 08:35 PM, Marek Olšák wrote:
> https://pastebin.com/raw/itNDpPv0
> 
> Cleanups only: +10.85%
> Total: +11.8%

Thanks, that's more useful.

If you pass all 3 data files to a single ministat -s invocation, it
combines all of them in a single graph, and prints information about
whether or not a difference was detected, and if yes, the interval in
which the difference lies at 95% confidence.


It might be even better to compare the total number of frames rendered
in a fixed amount of time, with multiple runs for each test
configuration, in case there is systemic variance between runs (e.g. due
to ASLR).


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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Re: [Mesa-dev] [PATCH v8 33/33] nvir/nir: implement intrinsic shader_clock

[Rhys Perry]

The instructions should probably be marked as fixed so they aren't CSE'd.

On Fri, Jun 29, 2018 at 11:32 PM, Karol Herbst  wrote:
> Signed-off-by: Karol Herbst 
> ---
>  src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 8 
>  1 file changed, 8 insertions(+)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
> index f4875113d00..ed2453136fd 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
> @@ -2344,6 +2344,14 @@ Converter::visit(nir_intrinsic_instr *insn)
>bar->subOp = getSubOp(op);
>break;
> }
> +   case nir_intrinsic_shader_clock: {
> +  const DataType dType = getDType(insn);
> +  LValues  = convert(>dest);
> +
> +  loadImm(newDefs[0], 0u);
> +  mkOp1v(OP_RDSV, dType, newDefs[1], mkSysVal(SV_CLOCK, 0));
> +  break;
> +   }
> default:
>ERROR("unknown nir_intrinsic_op %s\n", nir_intrinsic_infos[op].name);
>return false;
> --
> 2.17.1
>
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Re: [Mesa-dev] [PATCH 8/8] nir: specify bit_size when loading system values

[Jason Ekstrand]

On Mon, Jul 16, 2018 at 7:29 AM Karol Herbst  wrote:

> With OpenCL the size of some system value depends on the Physical model
> choosen, so we need a way to load any system value as 32 or 64 bit.
>
> We could probably be a lot smarter and specify which system values might
> be valid as 32 and/or 64 bit, but I get the feeling it isn't really worth
> the effort and we can simply depend on the dest type choosen by the API.
>

I'm not sure what I think about this.  Most system values (other than the
few used by OpenCL) are always 32 bits all the time and back-ends are
likely to depend on this.  At the very least, it might be nice to have some
sort of validation that the bit sizes are correct before we get there.

One solution to this would be to add a dest_bit_size field to
nir_intrinsic_info and use the convention of dest_bit_size == 0 means it
can be anything.  Then nir_builder_opcodes.py can use that to create
functions which either require the bit size or don't.  Also, we could have
the validator properly validate intrinsic destination bit sizes.  It's also
something that we could do somewhat incramentally because defaulting
everything to dest_bit_size = 0 gives the current behavior.

--Jason


> Signed-off-by: Karol Herbst 
> ---
>  src/compiler/nir/nir_builder_opcodes_h.py |  9 ++--
>  src/compiler/nir/nir_lower_alpha_test.c   |  2 +-
>  src/compiler/nir/nir_lower_clip.c |  3 +-
>  src/compiler/nir/nir_lower_subgroups.c|  8 +--
>  src/compiler/nir/nir_lower_system_values.c| 49 +++
>  src/compiler/nir/nir_lower_two_sided_color.c  |  2 +-
>  src/compiler/nir/nir_lower_wpos_center.c  |  2 +-
>  src/compiler/spirv/vtn_subgroup.c |  2 +-
>  src/gallium/auxiliary/nir/tgsi_to_nir.c   |  3 +-
>  src/intel/blorp/blorp_blit.c  |  2 +-
>  src/intel/blorp/blorp_clear.c |  2 +-
>  .../compiler/brw_nir_lower_cs_intrinsics.c|  6 +--
>  src/mesa/drivers/dri/i965/brw_tcs.c   |  2 +-
>  13 files changed, 52 insertions(+), 40 deletions(-)
>
> diff --git a/src/compiler/nir/nir_builder_opcodes_h.py
> b/src/compiler/nir/nir_builder_opcodes_h.py
> index 72cf5b4549d..d16dac6b16e 100644
> --- a/src/compiler/nir/nir_builder_opcodes_h.py
> +++ b/src/compiler/nir/nir_builder_opcodes_h.py
> @@ -44,22 +44,23 @@ nir_${name}(nir_builder *build,
> ${src_decl_list(opcode.num_inputs)})
>
>  /* Generic builder for system values. */
>  static inline nir_ssa_def *
> -nir_load_system_value(nir_builder *build, nir_intrinsic_op op, int index)
> +nir_load_system_value(nir_builder *build, nir_intrinsic_op op, int index,
> +  unsigned bit_size)
>  {
> nir_intrinsic_instr *load = nir_intrinsic_instr_create(build->shader,
> op);
> load->num_components = nir_intrinsic_infos[op].dest_components;
> load->const_index[0] = index;
> nir_ssa_dest_init(>instr, >dest,
> - nir_intrinsic_infos[op].dest_components, 32, NULL);
> + nir_intrinsic_infos[op].dest_components, bit_size,
> NULL);
> nir_builder_instr_insert(build, >instr);
> return >dest.ssa;
>  }
>
>  % for name, opcode in filter(lambda v: v[1].sysval,
> sorted(INTR_OPCODES.iteritems())):
>  static inline nir_ssa_def *
> -nir_${name}(nir_builder *build)
> +nir_${name}(nir_builder *build, unsigned bit_size)
>  {
> -   return nir_load_system_value(build, nir_intrinsic_${name}, 0);
> +   return nir_load_system_value(build, nir_intrinsic_${name}, 0,
> bit_size);
>  }
>  % endfor
>
> diff --git a/src/compiler/nir/nir_lower_alpha_test.c
> b/src/compiler/nir/nir_lower_alpha_test.c
> index ddd815765bd..8341a0246d2 100644
> --- a/src/compiler/nir/nir_lower_alpha_test.c
> +++ b/src/compiler/nir/nir_lower_alpha_test.c
> @@ -95,7 +95,7 @@ nir_lower_alpha_test(nir_shader *shader, enum
> compare_func func,
>
> nir_ssa_def *condition =
>nir_compare_func(, func,
> -   alpha, nir_load_alpha_ref_float());
> +   alpha, nir_load_alpha_ref_float(,
> 32));
>
> nir_intrinsic_instr *discard =
>nir_intrinsic_instr_create(b.shader,
> diff --git a/src/compiler/nir/nir_lower_clip.c
> b/src/compiler/nir/nir_lower_clip.c
> index ea12f51a7bb..b9a91f7d40b 100644
> --- a/src/compiler/nir/nir_lower_clip.c
> +++ b/src/compiler/nir/nir_lower_clip.c
> @@ -174,7 +174,8 @@ lower_clip_vs(nir_function_impl *impl, unsigned
> ucp_enables,
> for (int plane = 0; plane < MAX_CLIP_PLANES; plane++) {
>if (ucp_enables & (1 << plane)) {
>   nir_ssa_def *ucp =
> -nir_load_system_value(, nir_intrinsic_load_user_clip_plane,
> plane);
> +nir_load_system_value(, nir_intrinsic_load_user_clip_plane,
> +  plane, 32);
>
>   /* calculate clipdist[plane] - dot(ucp, cv): */
>   clipdist[plane] = nir_fdot4(, ucp, cv);
> diff --git 

Re: [Mesa-dev] [PATCH 7/8] nir/spirv: cast shift operand to u32

[Jason Ekstrand]

On Mon, Jul 16, 2018 at 8:32 AM Karol Herbst  wrote:

> On Mon, Jul 16, 2018 at 5:24 PM, Jason Ekstrand 
> wrote:
> > Do we need to do something similar for specialization constants?
> >
>
> I don't think so. The problem here wasn't constants, but simply that
> we can end up with non 32 bit shift values inside the SPIR-V, but we
> only support 32 bit shifts in nir. It is legal SPIR-V, so we might
> just want to fix that.
>

Right, but you can have 64 or 16-bit specialization constants as well.


> > On Mon, Jul 16, 2018 at 7:28 AM Karol Herbst  wrote:
> >>
> >> Signed-off-by: Karol Herbst 
> >> ---
> >>  src/compiler/spirv/vtn_alu.c | 10 ++
> >>  1 file changed, 10 insertions(+)
> >>
> >> diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
> >> index 5db6c7f0a87..d6f149d12e9 100644
> >> --- a/src/compiler/spirv/vtn_alu.c
> >> +++ b/src/compiler/spirv/vtn_alu.c
> >> @@ -743,6 +743,16 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
> >>   src[1] = tmp;
> >>}
> >>
> >> +  switch (op) {
> >> +  case nir_op_ishl:
> >> +  case nir_op_ishr:
> >> +  case nir_op_ushr:
> >> + src[1] = nir_u2u32(>nb, src[1]);
> >> + break;
> >> +  default:
> >> + break;
> >> +  }
> >> +
> >>val->ssa->def = nir_build_alu(>nb, op, src[0], src[1], src[2],
> >> src[3]);
> >>break;
> >> } /* default */
> >> --
> >> 2.17.1
> >>
> >> ___
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> >> mesa-dev@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
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Re: [Mesa-dev] [PATCH 7/8] nir/spirv: cast shift operand to u32

[Karol Herbst]

On Mon, Jul 16, 2018 at 5:24 PM, Jason Ekstrand  wrote:
> Do we need to do something similar for specialization constants?
>

I don't think so. The problem here wasn't constants, but simply that
we can end up with non 32 bit shift values inside the SPIR-V, but we
only support 32 bit shifts in nir. It is legal SPIR-V, so we might
just want to fix that.

> On Mon, Jul 16, 2018 at 7:28 AM Karol Herbst  wrote:
>>
>> Signed-off-by: Karol Herbst 
>> ---
>>  src/compiler/spirv/vtn_alu.c | 10 ++
>>  1 file changed, 10 insertions(+)
>>
>> diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
>> index 5db6c7f0a87..d6f149d12e9 100644
>> --- a/src/compiler/spirv/vtn_alu.c
>> +++ b/src/compiler/spirv/vtn_alu.c
>> @@ -743,6 +743,16 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
>>   src[1] = tmp;
>>}
>>
>> +  switch (op) {
>> +  case nir_op_ishl:
>> +  case nir_op_ishr:
>> +  case nir_op_ushr:
>> + src[1] = nir_u2u32(>nb, src[1]);
>> + break;
>> +  default:
>> + break;
>> +  }
>> +
>>val->ssa->def = nir_build_alu(>nb, op, src[0], src[1], src[2],
>> src[3]);
>>break;
>> } /* default */
>> --
>> 2.17.1
>>
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Re: [Mesa-dev] [PATCH v2 6/8] nir/spirv: add OpIsFinite and OpIsNormal

[Jason Ekstrand]

On Mon, Jul 16, 2018 at 7:29 AM Karol Herbst  wrote:

> From: Rob Clark 
>
> v2 (Karol Herbst ):
>make compatible with 64 bit floats
>fix isfinite
>
> Signed-off-by: Karol Herbst 
> ---
>  src/compiler/spirv/vtn_alu.c | 32 
>  1 file changed, 32 insertions(+)
>
> diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
> index 5a0347989e9..5db6c7f0a87 100644
> --- a/src/compiler/spirv/vtn_alu.c
> +++ b/src/compiler/spirv/vtn_alu.c
> @@ -583,6 +583,38 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
>break;
> }
>
> +   case SpvOpIsFinite: {
> +  nir_ssa_def *inf = nir_imm_floatN_t(>nb, INFINITY,
> src[0]->bit_size);
> +  nir_ssa_def *isNumber = nir_feq(>nb, src[0], src[0]);
>

Please use snake_case.


> +  nir_ssa_def *isNotInf = nir_ine(>nb, nir_fabs(>nb, src[0]),
> inf);
>

Same here.


> +  val->ssa->def = nir_iand(>nb, isNumber, isNotInf);
> +  break;
> +   }
> +
> +   case SpvOpIsNormal: {
> +  unsigned bit_size = src[0]->bit_size;
> +
> +  uint32_t m;
> +  if (bit_size == 64)
> + m = 11;
> +  else if (bit_size == 32)
> + m = 8;
> +  else if (bit_size == 16)
> + m = 5;
> +  else
> + assert(!"unknown float type");
> +
> +  nir_ssa_def *shift = nir_imm_int(>nb, bit_size - m - 1);
> +  nir_ssa_def *abs = nir_fabs(>nb, src[0]);
> +  nir_ssa_def *exp = nir_iadd(>nb,
> +  nir_ushr(>nb, abs, shift),
> +  nir_imm_intN_t(>nb, -1, bit_size));
> +  val->ssa->def = nir_ult(>nb,
> +  exp,
> +  nir_imm_intN_t(>nb, (1 << m) - 2,
> bit_size));
> +  break;
> +   }
> +
> case SpvOpFUnordEqual:
> case SpvOpFUnordNotEqual:
> case SpvOpFUnordLessThan:
> --
> 2.17.1
>
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Re: [Mesa-dev] [PATCH 7/8] nir/spirv: cast shift operand to u32

[Jason Ekstrand]

Do we need to do something similar for specialization constants?

On Mon, Jul 16, 2018 at 7:28 AM Karol Herbst  wrote:

> Signed-off-by: Karol Herbst 
> ---
>  src/compiler/spirv/vtn_alu.c | 10 ++
>  1 file changed, 10 insertions(+)
>
> diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
> index 5db6c7f0a87..d6f149d12e9 100644
> --- a/src/compiler/spirv/vtn_alu.c
> +++ b/src/compiler/spirv/vtn_alu.c
> @@ -743,6 +743,16 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
>   src[1] = tmp;
>}
>
> +  switch (op) {
> +  case nir_op_ishl:
> +  case nir_op_ishr:
> +  case nir_op_ushr:
> + src[1] = nir_u2u32(>nb, src[1]);
> + break;
> +  default:
> + break;
> +  }
> +
>val->ssa->def = nir_build_alu(>nb, op, src[0], src[1], src[2],
> src[3]);
>break;
> } /* default */
> --
> 2.17.1
>
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Re: [Mesa-dev] [PATCH 5/8] nir/spirv: print id for unsupported alu opcode

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

On Mon, Jul 16, 2018 at 7:29 AM Karol Herbst  wrote:

> Signed-off-by: Karol Herbst 
> ---
>  src/compiler/spirv/vtn_alu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
> index 0ec0234f531..5a0347989e9 100644
> --- a/src/compiler/spirv/vtn_alu.c
> +++ b/src/compiler/spirv/vtn_alu.c
> @@ -415,7 +415,7 @@ vtn_nir_alu_op_for_spirv_opcode(struct vtn_builder *b,
> case SpvOpDPdyCoarse:   return nir_op_fddy_coarse;
>
> default:
> -  vtn_fail("No NIR equivalent");
> +  vtn_fail("No NIR equivalent: %u", opcode);
> }
>  }
>
> --
> 2.17.1
>
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Re: [Mesa-dev] [PATCH] nir/lower_int64: mark all metadata as dirty

[Jason Ekstrand]

On Mon, Jul 16, 2018 at 7:30 AM Karol Herbst  wrote:

> without this we might end up looping inside the dominator analysis
> infinitly. Hit by some 64 bit int div OpenCL CTS test.
>
> Signed-off-by: Karol Herbst 
> ---
>  src/compiler/nir/nir_lower_int64.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/src/compiler/nir/nir_lower_int64.c
> b/src/compiler/nir/nir_lower_int64.c
> index 22f69ef4a60..09eac8cfc05 100644
> --- a/src/compiler/nir/nir_lower_int64.c
> +++ b/src/compiler/nir/nir_lower_int64.c
> @@ -279,6 +279,8 @@ lower_int64_impl(nir_function_impl *impl,
> nir_lower_int64_options options)
>}
> }
>
> +   impl->valid_metadata = nir_metadata_none;
>

Please use nir_metadata_preserve(impl, nir_metadata_none) instead.


> +
> return progress;
>  }
>
> --
> 2.17.1
>
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Re: [Mesa-dev] [PATCH 3/8] nir/spirv: import OpenCL.std.h

[Jason Ekstrand]

Acked-by: Jason Ekstrand 

On Mon, Jul 16, 2018 at 7:29 AM Karol Herbst  wrote:

> From: Rob Clark 
>
> Lightly edited to be valid 'C' code.
>
> Is there a bug open to fix this upstream?
>
> Signed-off-by: Karol Herbst 
> ---
>  src/compiler/spirv/OpenCL.std.h | 211 
>  1 file changed, 211 insertions(+)
>  create mode 100644 src/compiler/spirv/OpenCL.std.h
>
> diff --git a/src/compiler/spirv/OpenCL.std.h
> b/src/compiler/spirv/OpenCL.std.h
> new file mode 100644
> index 000..1e9e7fc8d8a
> --- /dev/null
> +++ b/src/compiler/spirv/OpenCL.std.h
> @@ -0,0 +1,211 @@
> +/*
> +** Copyright (c) 2015-2017 The Khronos Group Inc.
> +**
> +** Permission is hereby granted, free of charge, to any person obtaining
> a copy
> +** of this software and/or associated documentation files (the
> "Materials"),
> +** to deal in the Materials without restriction, including without
> limitation
> +** the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> +** and/or sell copies of the Materials, and to permit persons to whom the
> +** Materials are furnished to do so, subject to the following conditions:
> +**
> +** The above copyright notice and this permission notice shall be
> included in
> +** all copies or substantial portions of the Materials.
> +**
> +** MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS
> KHRONOS
> +** STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS
> SPECIFICATIONS AND
> +** HEADER INFORMATION ARE LOCATED AT https://www.khronos.org/registry/
> +**
> +** THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS
> +** OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> +** FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> +** THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> +** LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> +** FROM,OUT OF OR IN CONNECTION WITH THE MATERIALS OR THE USE OR OTHER
> DEALINGS
> +** IN THE MATERIALS.
> +*/
> +
> +#ifndef OpenCLstd_H
> +#define OpenCLstd_H
> +
> +enum OpenCLstd {
> +
> +// Section 2.1: Math extended instructions
> +Acos = 0,
> +Acosh = 1,
> +Acospi = 2,
> +Asin = 3,
> +Asinh = 4,
> +Asinpi = 5,
> +Atan = 6,
> +Atan2 = 7,
> +Atanh = 8,
> +Atanpi = 9,
> +Atan2pi = 10,
> +Cbrt = 11,
> +Ceil = 12,
> +Copysign = 13,
> +Cos = 14,
> +Cosh = 15,
> +Cospi = 16,
> +Erfc = 17,
> +Erf = 18,
> +Exp = 19,
> +Exp2 = 20,
> +Exp10 = 21,
> +Expm1 = 22,
> +Fabs = 23,
> +Fdim = 24,
> +Floor = 25,
> +Fma = 26,
> +Fmax = 27,
> +Fmin = 28,
> +Fmod = 29,
> +Fract = 30,
> +Frexp = 31,
> +Hypot = 32,
> +Ilogb = 33,
> +Ldexp = 34,
> +Lgamma = 35,
> +Lgamma_r = 36,
> +Log = 37,
> +Log2 = 38,
> +Log10 = 39,
> +Log1p = 40,
> +Logb = 41,
> +Mad = 42,
> +Maxmag = 43,
> +Minmag = 44,
> +Modf = 45,
> +Nan = 46,
> +Nextafter = 47,
> +Pow = 48,
> +Pown = 49,
> +Powr = 50,
> +Remainder = 51,
> +Remquo = 52,
> +Rint = 53,
> +Rootn = 54,
> +Round = 55,
> +Rsqrt = 56,
> +Sin = 57,
> +Sincos = 58,
> +Sinh = 59,
> +Sinpi = 60,
> +Sqrt = 61,
> +Tan = 62,
> +Tanh = 63,
> +Tanpi = 64,
> +Tgamma = 65,
> +Trunc = 66,
> +Half_cos = 67,
> +Half_divide = 68,
> +Half_exp = 69,
> +Half_exp2 = 70,
> +Half_exp10 = 71,
> +Half_log = 72,
> +Half_log2 = 73,
> +Half_log10 = 74,
> +Half_powr = 75,
> +Half_recip = 76,
> +Half_rsqrt = 77,
> +Half_sin = 78,
> +Half_sqrt = 79,
> +Half_tan = 80,
> +Native_cos = 81,
> +Native_divide = 82,
> +Native_exp = 83,
> +Native_exp2 = 84,
> +Native_exp10 = 85,
> +Native_log = 86,
> +Native_log2 = 87,
> +Native_log10 = 88,
> +Native_powr = 89,
> +Native_recip = 90,
> +Native_rsqrt = 91,
> +Native_sin = 92,
> +Native_sqrt = 93,
> +Native_tan = 94,
> +
> +// Section 2.2: Integer instructions
> +SAbs = 141,
> +SAbs_diff = 142,
> +SAdd_sat = 143,
> +UAdd_sat = 144,
> +SHadd = 145,
> +UHadd = 146,
> +SRhadd = 147,
> +URhadd = 148,
> +SClamp = 149,
> +UClamp = 150,
> +Clz = 151,
> +Ctz = 152,
> +SMad_hi = 153,
> +UMad_sat = 154,
> +SMad_sat = 155,
> +SMax = 156,
> +UMax = 157,
> +SMin = 158,
> +UMin = 159,
> +SMul_hi = 160,
> +Rotate = 161,
> +SSub_sat = 162,
> +USub_sat = 163,
> +U_Upsample = 164,
> +S_Upsample = 165,
> +Popcount = 166,
> +SMad24 = 167,
> +UMad24 = 168,
> +SMul24 = 169,
> +UMul24 = 170,
> +UAbs = 201,
> +UAbs_diff = 202,
> +UMul_hi = 203,
> +UMad_hi = 204,
> +
> +// Section 2.3: Common instructions
> +FClamp = 95,
> +Degrees = 96,
> +

[Mesa-dev] [Bug 107098] Segfault after munmap(kms_sw_dt->ro_mapped)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107098

--- Comment #2 from Jan Palus  ---
Patch sent to mailing list, maybe this way it will get any attention:

https://lists.freedesktop.org/archives/mesa-dev/2018-July/200199.html

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Re: [Mesa-dev] [PATCH v2 2/8] nir: prepare for bumping up max components to 16

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

On Mon, Jul 16, 2018 at 7:29 AM Karol Herbst  wrote:

> OpenCL knows vector of size 8 and 16.
>
> v2: rebased on master (nir_swizzle rework)
> rework more declarations with nir_component_mask_t
> adjust print_var_decl
>
> Reviewed-by: Jason Ekstrand 
> Signed-off-by: Karol Herbst 
> ---
>  src/compiler/nir/nir.c| 14 
>  src/compiler/nir/nir.h| 34 ++-
>  src/compiler/nir/nir_builder.h| 17 ++
>  src/compiler/nir/nir_lower_alu_to_scalar.c|  6 ++--
>  src/compiler/nir/nir_lower_io_to_scalar.c |  4 +--
>  .../nir/nir_lower_load_const_to_scalar.c  |  2 +-
>  src/compiler/nir/nir_opt_constant_folding.c   |  2 +-
>  src/compiler/nir/nir_opt_copy_prop_vars.c |  4 +--
>  src/compiler/nir/nir_print.c  |  9 ++---
>  src/compiler/nir/nir_search.c |  8 ++---
>  src/compiler/nir/nir_validate.c   |  6 ++--
>  src/compiler/spirv/spirv_to_nir.c |  2 +-
>  src/compiler/spirv/vtn_alu.c  |  2 +-
>  13 files changed, 57 insertions(+), 53 deletions(-)
>
> diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
> index ca89a46f7d4..bc7f05b3e86 100644
> --- a/src/compiler/nir/nir.c
> +++ b/src/compiler/nir/nir.c
> @@ -251,7 +251,7 @@ nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src
> *src,
> nir_src_copy(>src, >src, >instr);
> dest->abs = src->abs;
> dest->negate = src->negate;
> -   for (unsigned i = 0; i < 4; i++)
> +   for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++)
>dest->swizzle[i] = src->swizzle[i];
>  }
>
> @@ -421,10 +421,8 @@ alu_src_init(nir_alu_src *src)
>  {
> src_init(>src);
> src->abs = src->negate = false;
> -   src->swizzle[0] = 0;
> -   src->swizzle[1] = 1;
> -   src->swizzle[2] = 2;
> -   src->swizzle[3] = 3;
> +   for (int i = 0; i < NIR_MAX_VEC_COMPONENTS; ++i)
> +  src->swizzle[i] = i;
>  }
>
>  nir_alu_instr *
> @@ -1426,10 +1424,10 @@ nir_ssa_def_rewrite_uses_after(nir_ssa_def *def,
> nir_src new_src,
>nir_if_rewrite_condition(use_src->parent_if, new_src);
>  }
>
> -uint8_t
> +nir_component_mask_t
>  nir_ssa_def_components_read(const nir_ssa_def *def)
>  {
> -   uint8_t read_mask = 0;
> +   nir_component_mask_t read_mask = 0;
> nir_foreach_use(use, def) {
>if (use->parent_instr->type == nir_instr_type_alu) {
>   nir_alu_instr *alu = nir_instr_as_alu(use->parent_instr);
> @@ -1437,7 +1435,7 @@ nir_ssa_def_components_read(const nir_ssa_def *def)
>   int src_idx = alu_src - >src[0];
>   assert(src_idx >= 0 && src_idx <
> nir_op_infos[alu->op].num_inputs);
>
> - for (unsigned c = 0; c < 4; c++) {
> + for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; c++) {
>  if (!nir_alu_instr_channel_used(alu, src_idx, c))
> continue;
>
> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
> index 92ab3a699cc..d3e63be091f 100644
> --- a/src/compiler/nir/nir.h
> +++ b/src/compiler/nir/nir.h
> @@ -57,6 +57,8 @@ extern "C" {
>
>  #define NIR_FALSE 0u
>  #define NIR_TRUE (~0u)
> +#define NIR_MAX_VEC_COMPONENTS 4
> +typedef uint8_t nir_component_mask_t;
>
>  /** Defines a cast function
>   *
> @@ -115,16 +117,16 @@ typedef enum {
>  } nir_rounding_mode;
>
>  typedef union {
> -   float f32[4];
> -   double f64[4];
> -   int8_t i8[4];
> -   uint8_t u8[4];
> -   int16_t i16[4];
> -   uint16_t u16[4];
> -   int32_t i32[4];
> -   uint32_t u32[4];
> -   int64_t i64[4];
> -   uint64_t u64[4];
> +   float f32[NIR_MAX_VEC_COMPONENTS];
> +   double f64[NIR_MAX_VEC_COMPONENTS];
> +   int8_t i8[NIR_MAX_VEC_COMPONENTS];
> +   uint8_t u8[NIR_MAX_VEC_COMPONENTS];
> +   int16_t i16[NIR_MAX_VEC_COMPONENTS];
> +   uint16_t u16[NIR_MAX_VEC_COMPONENTS];
> +   int32_t i32[NIR_MAX_VEC_COMPONENTS];
> +   uint32_t u32[NIR_MAX_VEC_COMPONENTS];
> +   int64_t i64[NIR_MAX_VEC_COMPONENTS];
> +   uint64_t u64[NIR_MAX_VEC_COMPONENTS];
>  } nir_const_value;
>
>  typedef struct nir_constant {
> @@ -135,7 +137,7 @@ typedef struct nir_constant {
>  * by the type associated with the \c nir_variable.  Constants may be
>  * scalars, vectors, or matrices.
>  */
> -   nir_const_value values[4];
> +   nir_const_value values[NIR_MAX_VEC_COMPONENTS];
>
> /* we could get this from the var->type but makes clone *much* easier
> to
>  * not have to care about the type.
> @@ -697,7 +699,7 @@ typedef struct {
>  * a statement like "foo.xzw = bar.zyx" would have a writemask of
> 1101b and
>  * a swizzle of {2, x, 1, 0} where x means "don't care."
>  */
> -   uint8_t swizzle[4];
> +   uint8_t swizzle[NIR_MAX_VEC_COMPONENTS];
>  } nir_alu_src;
>
>  typedef struct {
> @@ -712,7 +714,7 @@ typedef struct {
>
> bool saturate;
>
> -   unsigned write_mask : 4; /* ignored if dest.is_ssa is true */
> +   unsigned write_mask : NIR_MAX_VEC_COMPONENTS; /* ignored if
> dest.is_ssa is true */
>  } 

Re: [Mesa-dev] [PATCH v2 1/8] nir: add builtin builder

[Jason Ekstrand]

On Mon, Jul 16, 2018 at 7:28 AM Karol Herbst  wrote:

> also move some of the GLSL builtins over we will need for implementing
> some OpenCL builtins
>
> v2: replace NIR_IMM_FP by nir_imm_floatN_t in ported code
> fix up changes caused by swizzle rework
>
> Signed-off-by: Karol Herbst 
> ---
>  src/compiler/Makefile.sources  |  2 +
>  src/compiler/nir/meson.build   |  2 +
>  src/compiler/nir/nir_builtin_builder.c | 65 +
>  src/compiler/nir/nir_builtin_builder.h | 79 ++
>  src/compiler/spirv/vtn_glsl450.c   | 58 +--
>  5 files changed, 161 insertions(+), 45 deletions(-)
>  create mode 100644 src/compiler/nir/nir_builtin_builder.c
>  create mode 100644 src/compiler/nir/nir_builtin_builder.h
>
> diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
> index db4dd1e89f4..cc147218c4e 100644
> --- a/src/compiler/Makefile.sources
> +++ b/src/compiler/Makefile.sources
> @@ -203,6 +203,8 @@ NIR_FILES = \
> nir/nir.c \
> nir/nir.h \
> nir/nir_builder.h \
> +   nir/nir_builtin_builder.c \
> +   nir/nir_builtin_builder.h \
> nir/nir_clone.c \
> nir/nir_constant_expressions.h \
> nir/nir_control_flow.c \
> diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
> index 28aa8de7014..a1bb19356ce 100644
> --- a/src/compiler/nir/meson.build
> +++ b/src/compiler/nir/meson.build
> @@ -87,6 +87,8 @@ files_libnir = files(
>'nir.c',
>'nir.h',
>'nir_builder.h',
> +  'nir_builtin_builder.c',
> +  'nir_builtin_builder.h',
>'nir_clone.c',
>'nir_constant_expressions.h',
>'nir_control_flow.c',
> diff --git a/src/compiler/nir/nir_builtin_builder.c
> b/src/compiler/nir/nir_builtin_builder.c
> new file mode 100644
> index 000..252a7691f36
> --- /dev/null
> +++ b/src/compiler/nir/nir_builtin_builder.c
> @@ -0,0 +1,65 @@
> +/*
> + * Copyright © 2018 Red Hat Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without
> limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the
> next
> + * paragraph) shall be included in all copies or substantial portions of
> the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT
> SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "nir.h"
> +#include "nir_builtin_builder.h"
> +
> +nir_ssa_def*
> +nir_cross(nir_builder *b, nir_ssa_def *x, nir_ssa_def *y)
> +{
> +   unsigned yzx[3] = { 1, 2, 0 };
> +   unsigned zxy[3] = { 2, 0, 1 };
> +
> +   return nir_fsub(b, nir_fmul(b, nir_swizzle(b, x, yzx, 3, true),
> +  nir_swizzle(b, y, zxy, 3, true)),
> +  nir_fmul(b, nir_swizzle(b, x, zxy, 3, true),
> +  nir_swizzle(b, y, yzx, 3, true)));
> +}
> +
> +nir_ssa_def*
> +nir_fast_length(nir_builder *b, nir_ssa_def *vec)
> +{
> +   switch (vec->num_components) {
> +   case 1: return nir_fsqrt(b, nir_fmul(b, vec, vec));
> +   case 2: return nir_fsqrt(b, nir_fdot2(b, vec, vec));
> +   case 3: return nir_fsqrt(b, nir_fdot3(b, vec, vec));
> +   case 4: return nir_fsqrt(b, nir_fdot4(b, vec, vec));
> +   default:
> +  unreachable("Invalid number of components");
> +   }
> +}
> +
> +nir_ssa_def*
> +nir_smoothstep(nir_builder *b, nir_ssa_def *edge0, nir_ssa_def *edge1,
> nir_ssa_def *x)
> +{
> +   nir_ssa_def *f2 = nir_imm_floatN_t(b, 2.0, x->bit_size);
> +   nir_ssa_def *f3 = nir_imm_floatN_t(b, 3.0, x->bit_size);
> +
> +   /* t = clamp((x - edge0) / (edge1 - edge0), 0, 1) */
> +   nir_ssa_def *t =
> +  nir_fsat(b, nir_fdiv(b, nir_fsub(b, x, edge0),
> +  nir_fsub(b, edge1, edge0)));
> +
> +   /* result = t * t * (3 - 2 * t) */
> +   return nir_fmul(b, t, nir_fmul(b, t, nir_fsub(b, f3, nir_fmul(b, f2,
> t;
> +}
> diff --git a/src/compiler/nir/nir_builtin_builder.h
> b/src/compiler/nir/nir_builtin_builder.h
> new file mode 100644
> index 000..5b76d012c85
> --- /dev/null
> +++ b/src/compiler/nir/nir_builtin_builder.h
> @@ -0,0 +1,79 @@
> +/*
> + * Copyright © 2018 Red Hat Inc.
> + *
> + * Permission is hereby 

Re: [Mesa-dev] [PATCH v1 0/3] Android kms_swrast support

[Robert Foss]

Hey,


On 2018-07-09 13:01, Robert Foss wrote:

NOTE: This series has not been tested successfully, and I'm seeing a segfault
   during the boot process. Which I'm currently looking into.


Tracking down the segfault I've been seeing through mesa and aosp and 
bootanimation. It occurs when ioctl authentication causes 
DRM_IOCTL_MODE_MAP_DUMB to fail for render nodes.


Disabling the authentication using [1] fixes the problem.

Currently the kms_sw_displaytarget_map() function in mesa will always use 
DRM_IOCTL_MODE_MAP_DUMB.


To avoid having to use [1], dumb buffers must be avoided. Which means looking at 
VGEM. Exactly what this would look like I'm not quite sure of yet.

But I would like some input.

[1] 
https://groups.google.com/a/chromium.org/forum/#!topic/chromium-os-reviews/5nOxn-JXJUk




This series implements kms_swrast support for the Android
platform.

It's available here:
https://gitlab.collabora.com/robertfoss/mesa/tree/kms_swrast_v1
and here with some debug:
https://gitlab.collabora.com/robertfoss/mesa/tree/kms_swrast_v1_debug


Changes since RFC:
   - Dropped "st/dri: Allow kms_swrast to work without a device FD"
   - Removed software renderer fallback from platform_android
   - Fixed various smaller issues


Rob.

Rob Herring (1):
   android: Build kms_swrast for the Android platform

Robert Foss (2):
   egl/android: Add Android property for forcing software rendering
   platform/android: Enable kms_swrast fallback

  src/egl/drivers/dri2/platform_android.c  | 19 ++-
  src/egl/main/egldriver.c | 10 ++
  src/gallium/Android.mk   |  2 +-
  src/gallium/auxiliary/pipe-loader/Android.mk |  1 +
  src/gallium/drivers/softpipe/Android.mk  |  4 +--
  src/gallium/state_trackers/dri/Android.mk|  1 +
  src/gallium/winsys/sw/kms-dri/Android.mk | 33 
  7 files changed, 59 insertions(+), 11 deletions(-)
  create mode 100644 src/gallium/winsys/sw/kms-dri/Android.mk


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[Mesa-dev] [PATCH] nir/lower_int64: mark all metadata as dirty

[Karol Herbst]

without this we might end up looping inside the dominator analysis
infinitly. Hit by some 64 bit int div OpenCL CTS test.

Signed-off-by: Karol Herbst 
---
 src/compiler/nir/nir_lower_int64.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/compiler/nir/nir_lower_int64.c 
b/src/compiler/nir/nir_lower_int64.c
index 22f69ef4a60..09eac8cfc05 100644
--- a/src/compiler/nir/nir_lower_int64.c
+++ b/src/compiler/nir/nir_lower_int64.c
@@ -279,6 +279,8 @@ lower_int64_impl(nir_function_impl *impl, 
nir_lower_int64_options options)
   }
}
 
+   impl->valid_metadata = nir_metadata_none;
+
return progress;
 }
 
-- 
2.17.1

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[Mesa-dev] [PATCH 8/8] nir: specify bit_size when loading system values

[Karol Herbst]

With OpenCL the size of some system value depends on the Physical model
choosen, so we need a way to load any system value as 32 or 64 bit.

We could probably be a lot smarter and specify which system values might
be valid as 32 and/or 64 bit, but I get the feeling it isn't really worth
the effort and we can simply depend on the dest type choosen by the API.

Signed-off-by: Karol Herbst 
---
 src/compiler/nir/nir_builder_opcodes_h.py |  9 ++--
 src/compiler/nir/nir_lower_alpha_test.c   |  2 +-
 src/compiler/nir/nir_lower_clip.c |  3 +-
 src/compiler/nir/nir_lower_subgroups.c|  8 +--
 src/compiler/nir/nir_lower_system_values.c| 49 +++
 src/compiler/nir/nir_lower_two_sided_color.c  |  2 +-
 src/compiler/nir/nir_lower_wpos_center.c  |  2 +-
 src/compiler/spirv/vtn_subgroup.c |  2 +-
 src/gallium/auxiliary/nir/tgsi_to_nir.c   |  3 +-
 src/intel/blorp/blorp_blit.c  |  2 +-
 src/intel/blorp/blorp_clear.c |  2 +-
 .../compiler/brw_nir_lower_cs_intrinsics.c|  6 +--
 src/mesa/drivers/dri/i965/brw_tcs.c   |  2 +-
 13 files changed, 52 insertions(+), 40 deletions(-)

diff --git a/src/compiler/nir/nir_builder_opcodes_h.py 
b/src/compiler/nir/nir_builder_opcodes_h.py
index 72cf5b4549d..d16dac6b16e 100644
--- a/src/compiler/nir/nir_builder_opcodes_h.py
+++ b/src/compiler/nir/nir_builder_opcodes_h.py
@@ -44,22 +44,23 @@ nir_${name}(nir_builder *build, 
${src_decl_list(opcode.num_inputs)})
 
 /* Generic builder for system values. */
 static inline nir_ssa_def *
-nir_load_system_value(nir_builder *build, nir_intrinsic_op op, int index)
+nir_load_system_value(nir_builder *build, nir_intrinsic_op op, int index,
+  unsigned bit_size)
 {
nir_intrinsic_instr *load = nir_intrinsic_instr_create(build->shader, op);
load->num_components = nir_intrinsic_infos[op].dest_components;
load->const_index[0] = index;
nir_ssa_dest_init(>instr, >dest,
- nir_intrinsic_infos[op].dest_components, 32, NULL);
+ nir_intrinsic_infos[op].dest_components, bit_size, NULL);
nir_builder_instr_insert(build, >instr);
return >dest.ssa;
 }
 
 % for name, opcode in filter(lambda v: v[1].sysval, 
sorted(INTR_OPCODES.iteritems())):
 static inline nir_ssa_def *
-nir_${name}(nir_builder *build)
+nir_${name}(nir_builder *build, unsigned bit_size)
 {
-   return nir_load_system_value(build, nir_intrinsic_${name}, 0);
+   return nir_load_system_value(build, nir_intrinsic_${name}, 0, bit_size);
 }
 % endfor
 
diff --git a/src/compiler/nir/nir_lower_alpha_test.c 
b/src/compiler/nir/nir_lower_alpha_test.c
index ddd815765bd..8341a0246d2 100644
--- a/src/compiler/nir/nir_lower_alpha_test.c
+++ b/src/compiler/nir/nir_lower_alpha_test.c
@@ -95,7 +95,7 @@ nir_lower_alpha_test(nir_shader *shader, enum compare_func 
func,
 
nir_ssa_def *condition =
   nir_compare_func(, func,
-   alpha, nir_load_alpha_ref_float());
+   alpha, nir_load_alpha_ref_float(, 32));
 
nir_intrinsic_instr *discard =
   nir_intrinsic_instr_create(b.shader,
diff --git a/src/compiler/nir/nir_lower_clip.c 
b/src/compiler/nir/nir_lower_clip.c
index ea12f51a7bb..b9a91f7d40b 100644
--- a/src/compiler/nir/nir_lower_clip.c
+++ b/src/compiler/nir/nir_lower_clip.c
@@ -174,7 +174,8 @@ lower_clip_vs(nir_function_impl *impl, unsigned ucp_enables,
for (int plane = 0; plane < MAX_CLIP_PLANES; plane++) {
   if (ucp_enables & (1 << plane)) {
  nir_ssa_def *ucp =
-nir_load_system_value(, nir_intrinsic_load_user_clip_plane, 
plane);
+nir_load_system_value(, nir_intrinsic_load_user_clip_plane,
+  plane, 32);
 
  /* calculate clipdist[plane] - dot(ucp, cv): */
  clipdist[plane] = nir_fdot4(, ucp, cv);
diff --git a/src/compiler/nir/nir_lower_subgroups.c 
b/src/compiler/nir/nir_lower_subgroups.c
index ee5e8bd644b..c474b9fd27a 100644
--- a/src/compiler/nir/nir_lower_subgroups.c
+++ b/src/compiler/nir/nir_lower_subgroups.c
@@ -226,7 +226,7 @@ static nir_ssa_def *
 lower_shuffle(nir_builder *b, nir_intrinsic_instr *intrin,
   bool lower_to_scalar, bool lower_to_32bit)
 {
-   nir_ssa_def *index = nir_load_subgroup_invocation(b);
+   nir_ssa_def *index = nir_load_subgroup_invocation(b, 32);
switch (intrin->intrinsic) {
case nir_intrinsic_shuffle_xor:
   assert(intrin->src[1].is_ssa);
@@ -338,7 +338,7 @@ lower_subgroups_intrin(nir_builder *b, nir_intrinsic_instr 
*intrin,
   assert(options->subgroup_size <= 64);
   uint64_t group_mask = ~0ull >> (64 - options->subgroup_size);
 
-  nir_ssa_def *count = nir_load_subgroup_invocation(b);
+  nir_ssa_def *count = nir_load_subgroup_invocation(b, 32);
   nir_ssa_def *val;
   switch (intrin->intrinsic) {
   case 

[Mesa-dev] [PATCH 4/8] nir/spirv: initial handling of OpenCL.std extension opcodes

[Karol Herbst]

Not complete, mostly just adding things as I encounter them in CTS. But
not getting far enough yet to hit most of the OpenCL.std instructions.

Anyway, this is better than nothing and covers the most common builtins.

Signed-off-by: Karol Herbst 
---
 src/compiler/nir/meson.build   |   1 +
 src/compiler/nir/nir_builtin_builder.c | 249 +-
 src/compiler/nir/nir_builtin_builder.h | 150 -
 src/compiler/spirv/spirv_to_nir.c  |   2 +
 src/compiler/spirv/vtn_alu.c   |  15 ++
 src/compiler/spirv/vtn_glsl450.c   |   2 +-
 src/compiler/spirv/vtn_opencl.c| 284 +
 src/compiler/spirv/vtn_private.h   |   3 +
 8 files changed, 701 insertions(+), 5 deletions(-)
 create mode 100644 src/compiler/spirv/vtn_opencl.c

diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
index a1bb19356ce..d72654cb5c8 100644
--- a/src/compiler/nir/meson.build
+++ b/src/compiler/nir/meson.build
@@ -201,6 +201,7 @@ files_libnir = files(
   '../spirv/vtn_amd.c',
   '../spirv/vtn_cfg.c',
   '../spirv/vtn_glsl450.c',
+  '../spirv/vtn_opencl.c',
   '../spirv/vtn_private.h',
   '../spirv/vtn_subgroup.c',
   '../spirv/vtn_variables.c',
diff --git a/src/compiler/nir/nir_builtin_builder.c 
b/src/compiler/nir/nir_builtin_builder.c
index 252a7691f36..e37915e92ca 100644
--- a/src/compiler/nir/nir_builtin_builder.c
+++ b/src/compiler/nir/nir_builtin_builder.c
@@ -21,11 +21,43 @@
  * IN THE SOFTWARE.
  */
 
+#include 
+
 #include "nir.h"
 #include "nir_builtin_builder.h"
 
 nir_ssa_def*
-nir_cross(nir_builder *b, nir_ssa_def *x, nir_ssa_def *y)
+nir_iadd_sat(nir_builder *b, nir_ssa_def *x, nir_ssa_def *y)
+{
+   int64_t max;
+   switch (x->bit_size) {
+   case 64:
+  max = INT64_MAX;
+  break;
+   case 32:
+  max = INT32_MAX;
+  break;
+   case 16:
+  max = INT16_MAX;
+  break;
+   case  8:
+  max = INT8_MAX;
+  break;
+   }
+
+   nir_ssa_def *sum = nir_iadd(b, x, y);
+
+   nir_ssa_def *hi = nir_bcsel(b, nir_ilt(b, sum, x),
+   nir_imm_intN_t(b, max, x->bit_size), sum);
+
+   nir_ssa_def *lo = nir_bcsel(b, nir_ilt(b, x, sum),
+   nir_imm_intN_t(b, max + 1, x->bit_size), sum);
+
+   return nir_bcsel(b, nir_ige(b, y, nir_imm_intN_t(b, 1, y->bit_size)), hi, 
lo);
+}
+
+nir_ssa_def*
+nir_cross3(nir_builder *b, nir_ssa_def *x, nir_ssa_def *y)
 {
unsigned yzx[3] = { 1, 2, 0 };
unsigned zxy[3] = { 2, 0, 1 };
@@ -36,6 +68,63 @@ nir_cross(nir_builder *b, nir_ssa_def *x, nir_ssa_def *y)
   nir_swizzle(b, y, yzx, 3, true)));
 }
 
+nir_ssa_def*
+nir_cross4(nir_builder *b, nir_ssa_def *x, nir_ssa_def *y)
+{
+   nir_ssa_def *cross = nir_cross3(b, x, y);
+
+   return nir_vec4(b,
+  nir_channel(b, cross, 0),
+  nir_channel(b, cross, 1),
+  nir_channel(b, cross, 2),
+  nir_imm_intN_t(b, 0, cross->bit_size));
+}
+
+static nir_ssa_def*
+nir_hadd(nir_builder *b, nir_ssa_def *x, nir_ssa_def *y, bool sign)
+{
+   nir_ssa_def *imm1 = nir_imm_int(b, 1);
+
+   nir_ssa_def *t0 = nir_ixor(b, x, y);
+   nir_ssa_def *t1 = nir_iand(b, x, y);
+
+   nir_ssa_def *t2;
+   if (sign)
+  t2 = nir_ishr(b, t0, imm1);
+   else
+  t2 = nir_ushr(b, t0, imm1);
+   return nir_iadd(b, t1, t2);
+}
+
+nir_ssa_def*
+nir_ihadd(nir_builder *b, nir_ssa_def *x, nir_ssa_def *y)
+{
+   return nir_hadd(b, x, y, true);
+}
+
+nir_ssa_def*
+nir_uhadd(nir_builder *b, nir_ssa_def *x, nir_ssa_def *y)
+{
+   return nir_hadd(b, x, y, false);
+}
+
+nir_ssa_def*
+nir_length(nir_builder *b, nir_ssa_def *vec)
+{
+   nir_ssa_def *finf = nir_imm_floatN_t(b, INFINITY, vec->bit_size);
+
+   nir_ssa_def *abs = nir_fabs(b, vec);
+   if (vec->num_components == 1)
+  return abs;
+
+   nir_ssa_def *maxc = nir_fmax(b, nir_channel(b, abs, 0), nir_channel(b, abs, 
1));
+   for (int i = 2; i < vec->num_components; ++i)
+  maxc = nir_fmax(b, maxc, nir_channel(b, abs, i));
+   abs = nir_fdiv(b, abs, maxc);
+   nir_ssa_def *res = nir_fmul(b, nir_fsqrt(b, nir_fdot(b, abs, abs)), maxc);
+   return nir_bcsel(b, nir_feq(b, maxc, finf), maxc, res);
+}
+
 nir_ssa_def*
 nir_fast_length(nir_builder *b, nir_ssa_def *vec)
 {
@@ -49,6 +138,107 @@ nir_fast_length(nir_builder *b, nir_ssa_def *vec)
}
 }
 
+nir_ssa_def*
+nir_nextafter(nir_builder *b, nir_ssa_def *x, nir_ssa_def *y)
+{
+   nir_ssa_def *zero = nir_imm_intN_t(b, 0, x->bit_size);
+   nir_ssa_def *one = nir_imm_intN_t(b, 1, x->bit_size);
+   nir_ssa_def *nzero = nir_imm_intN_t(b, 1ull << (x->bit_size - 1), 
x->bit_size);
+
+   nir_ssa_def *condeq = nir_feq(b, x, y);
+   nir_ssa_def *conddir = nir_flt(b, x, y);
+   nir_ssa_def *condnzero = nir_feq(b, x, nzero);
+
+   // beware of -0.0 - 1 == NaN
+   nir_ssa_def *xn =
+  nir_bcsel(b,
+condnzero,
+nir_imm_intN_t(b, (1 << (x->bit_size - 1)) + 1, x->bit_size),
+nir_isub(b, x, one));
+
+   // beware of -0.0 + 1 == -0x1p-149
+  

[Mesa-dev] [PATCH 5/8] nir/spirv: print id for unsupported alu opcode

[Karol Herbst]

Signed-off-by: Karol Herbst 
---
 src/compiler/spirv/vtn_alu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 0ec0234f531..5a0347989e9 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -415,7 +415,7 @@ vtn_nir_alu_op_for_spirv_opcode(struct vtn_builder *b,
case SpvOpDPdyCoarse:   return nir_op_fddy_coarse;
 
default:
-  vtn_fail("No NIR equivalent");
+  vtn_fail("No NIR equivalent: %u", opcode);
}
 }
 
-- 
2.17.1

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[Mesa-dev] [PATCH v2 6/8] nir/spirv: add OpIsFinite and OpIsNormal

[Karol Herbst]

From: Rob Clark 

v2 (Karol Herbst ):
   make compatible with 64 bit floats
   fix isfinite

Signed-off-by: Karol Herbst 
---
 src/compiler/spirv/vtn_alu.c | 32 
 1 file changed, 32 insertions(+)

diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 5a0347989e9..5db6c7f0a87 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -583,6 +583,38 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
   break;
}
 
+   case SpvOpIsFinite: {
+  nir_ssa_def *inf = nir_imm_floatN_t(>nb, INFINITY, src[0]->bit_size);
+  nir_ssa_def *isNumber = nir_feq(>nb, src[0], src[0]);
+  nir_ssa_def *isNotInf = nir_ine(>nb, nir_fabs(>nb, src[0]), inf);
+  val->ssa->def = nir_iand(>nb, isNumber, isNotInf);
+  break;
+   }
+
+   case SpvOpIsNormal: {
+  unsigned bit_size = src[0]->bit_size;
+
+  uint32_t m;
+  if (bit_size == 64)
+ m = 11;
+  else if (bit_size == 32)
+ m = 8;
+  else if (bit_size == 16)
+ m = 5;
+  else
+ assert(!"unknown float type");
+
+  nir_ssa_def *shift = nir_imm_int(>nb, bit_size - m - 1);
+  nir_ssa_def *abs = nir_fabs(>nb, src[0]);
+  nir_ssa_def *exp = nir_iadd(>nb,
+  nir_ushr(>nb, abs, shift),
+  nir_imm_intN_t(>nb, -1, bit_size));
+  val->ssa->def = nir_ult(>nb,
+  exp,
+  nir_imm_intN_t(>nb, (1 << m) - 2, bit_size));
+  break;
+   }
+
case SpvOpFUnordEqual:
case SpvOpFUnordNotEqual:
case SpvOpFUnordLessThan:
-- 
2.17.1

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[Mesa-dev] [PATCH 7/8] nir/spirv: cast shift operand to u32

[Karol Herbst]

Signed-off-by: Karol Herbst 
---
 src/compiler/spirv/vtn_alu.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 5db6c7f0a87..d6f149d12e9 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -743,6 +743,16 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
  src[1] = tmp;
   }
 
+  switch (op) {
+  case nir_op_ishl:
+  case nir_op_ishr:
+  case nir_op_ushr:
+ src[1] = nir_u2u32(>nb, src[1]);
+ break;
+  default:
+ break;
+  }
+
   val->ssa->def = nir_build_alu(>nb, op, src[0], src[1], src[2], 
src[3]);
   break;
} /* default */
-- 
2.17.1

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[Mesa-dev] [PATCH 3/8] nir/spirv: import OpenCL.std.h

[Karol Herbst]

From: Rob Clark 

Lightly edited to be valid 'C' code.

Is there a bug open to fix this upstream?

Signed-off-by: Karol Herbst 
---
 src/compiler/spirv/OpenCL.std.h | 211 
 1 file changed, 211 insertions(+)
 create mode 100644 src/compiler/spirv/OpenCL.std.h

diff --git a/src/compiler/spirv/OpenCL.std.h b/src/compiler/spirv/OpenCL.std.h
new file mode 100644
index 000..1e9e7fc8d8a
--- /dev/null
+++ b/src/compiler/spirv/OpenCL.std.h
@@ -0,0 +1,211 @@
+/*
+** Copyright (c) 2015-2017 The Khronos Group Inc.
+**
+** Permission is hereby granted, free of charge, to any person obtaining a copy
+** of this software and/or associated documentation files (the "Materials"),
+** to deal in the Materials without restriction, including without limitation
+** the rights to use, copy, modify, merge, publish, distribute, sublicense,
+** and/or sell copies of the Materials, and to permit persons to whom the
+** Materials are furnished to do so, subject to the following conditions:
+**
+** The above copyright notice and this permission notice shall be included in
+** all copies or substantial portions of the Materials.
+**
+** MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS KHRONOS
+** STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS SPECIFICATIONS AND
+** HEADER INFORMATION ARE LOCATED AT https://www.khronos.org/registry/ 
+**
+** THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+** OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+** FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+** THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+** LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+** FROM,OUT OF OR IN CONNECTION WITH THE MATERIALS OR THE USE OR OTHER DEALINGS
+** IN THE MATERIALS.
+*/
+
+#ifndef OpenCLstd_H
+#define OpenCLstd_H
+
+enum OpenCLstd {
+
+// Section 2.1: Math extended instructions
+Acos = 0,
+Acosh = 1,
+Acospi = 2,
+Asin = 3,
+Asinh = 4,
+Asinpi = 5,
+Atan = 6,
+Atan2 = 7,
+Atanh = 8,
+Atanpi = 9,
+Atan2pi = 10,
+Cbrt = 11,
+Ceil = 12,
+Copysign = 13,
+Cos = 14,
+Cosh = 15,
+Cospi = 16,
+Erfc = 17,
+Erf = 18,
+Exp = 19,
+Exp2 = 20,
+Exp10 = 21,
+Expm1 = 22,
+Fabs = 23,
+Fdim = 24,
+Floor = 25,
+Fma = 26,
+Fmax = 27,
+Fmin = 28,
+Fmod = 29,
+Fract = 30, 
+Frexp = 31,
+Hypot = 32,
+Ilogb = 33,
+Ldexp = 34,
+Lgamma = 35,
+Lgamma_r = 36,
+Log = 37,
+Log2 = 38,
+Log10 = 39,
+Log1p = 40,
+Logb = 41,
+Mad = 42,
+Maxmag = 43,
+Minmag = 44,
+Modf = 45,
+Nan = 46,
+Nextafter = 47,
+Pow = 48,
+Pown = 49,
+Powr = 50,
+Remainder = 51,
+Remquo = 52,
+Rint = 53,
+Rootn = 54,
+Round = 55,
+Rsqrt = 56,
+Sin = 57,
+Sincos = 58,
+Sinh = 59,
+Sinpi = 60,
+Sqrt = 61,
+Tan = 62,
+Tanh = 63,
+Tanpi = 64,
+Tgamma = 65,
+Trunc = 66,
+Half_cos = 67,
+Half_divide = 68,
+Half_exp = 69,
+Half_exp2 = 70,
+Half_exp10 = 71,
+Half_log = 72,
+Half_log2 = 73,
+Half_log10 = 74,
+Half_powr = 75,
+Half_recip = 76,
+Half_rsqrt = 77,
+Half_sin = 78,
+Half_sqrt = 79,
+Half_tan = 80,
+Native_cos = 81,
+Native_divide = 82,
+Native_exp = 83,
+Native_exp2 = 84,
+Native_exp10 = 85,
+Native_log = 86,
+Native_log2 = 87,
+Native_log10 = 88,
+Native_powr = 89,
+Native_recip = 90,
+Native_rsqrt = 91,
+Native_sin = 92,
+Native_sqrt = 93,
+Native_tan = 94,
+
+// Section 2.2: Integer instructions
+SAbs = 141,
+SAbs_diff = 142,
+SAdd_sat = 143,
+UAdd_sat = 144,
+SHadd = 145,
+UHadd = 146,
+SRhadd = 147,
+URhadd = 148,
+SClamp = 149,
+UClamp = 150, 
+Clz = 151,
+Ctz = 152,
+SMad_hi = 153,
+UMad_sat = 154,
+SMad_sat = 155,
+SMax = 156,
+UMax = 157,
+SMin = 158,
+UMin = 159,
+SMul_hi = 160,
+Rotate = 161,
+SSub_sat = 162,
+USub_sat = 163,
+U_Upsample = 164,
+S_Upsample = 165,
+Popcount = 166,
+SMad24 = 167,
+UMad24 = 168,
+SMul24 = 169,
+UMul24 = 170,
+UAbs = 201,
+UAbs_diff = 202,
+UMul_hi = 203,
+UMad_hi = 204,
+
+// Section 2.3: Common instructions
+FClamp = 95,
+Degrees = 96,
+FMax_common = 97,
+FMin_common = 98, 
+Mix = 99,
+Radians = 100,
+Step = 101,
+Smoothstep = 102,
+Sign = 103,
+
+// Section 2.4: Geometric instructions
+Cross = 104,
+Distance = 105, 
+Length = 106,
+Normalize = 107,
+Fast_distance = 108,
+Fast_length = 109,
+Fast_normalize = 110,
+
+// Section 2.5: Relational instructions
+Bitselect = 186,
+Select = 187,
+
+// Section 2.6: Vector Data 

[Mesa-dev] [PATCH 0/8] More OpenCL patches

[Karol Herbst]

This time there are actually some OpenCL patches like adding support for
the OpenCL SPIR-V extensions or a few opcodes we don't hit with vulkan
or glsl.

Also some of the glsl builtins are moved into a new file so that we can
start sharing builtin implementations across multiple SPIR-V extensions.

Last thing is preparing for vec8/vec16 types and handling 64 bit system
values, which is required by OpenCL.

Karol Herbst (6):
  nir: add builtin builder
  nir: prepare for bumping up max components to 16
  nir/spirv: initial handling of OpenCL.std extension opcodes
  nir/spirv: print id for unsupported alu opcode
  nir/spirv: cast shift operand to u32
  nir: specify bit_size when loading system values

Rob Clark (2):
  nir/spirv: import OpenCL.std.h
  nir/spirv: add OpIsFinite and OpIsNormal

 src/compiler/Makefile.sources |   2 +
 src/compiler/nir/meson.build  |   3 +
 src/compiler/nir/nir.c|  14 +-
 src/compiler/nir/nir.h|  34 +-
 src/compiler/nir/nir_builder.h|  17 +-
 src/compiler/nir/nir_builder_opcodes_h.py |   9 +-
 src/compiler/nir/nir_builtin_builder.c| 312 ++
 src/compiler/nir/nir_builtin_builder.h| 223 +
 src/compiler/nir/nir_lower_alpha_test.c   |   2 +-
 src/compiler/nir/nir_lower_alu_to_scalar.c|   6 +-
 src/compiler/nir/nir_lower_clip.c |   3 +-
 src/compiler/nir/nir_lower_io_to_scalar.c |   4 +-
 .../nir/nir_lower_load_const_to_scalar.c  |   2 +-
 src/compiler/nir/nir_lower_subgroups.c|   8 +-
 src/compiler/nir/nir_lower_system_values.c|  49 +--
 src/compiler/nir/nir_lower_two_sided_color.c  |   2 +-
 src/compiler/nir/nir_lower_wpos_center.c  |   2 +-
 src/compiler/nir/nir_opt_constant_folding.c   |   2 +-
 src/compiler/nir/nir_opt_copy_prop_vars.c |   4 +-
 src/compiler/nir/nir_print.c  |   9 +-
 src/compiler/nir/nir_search.c |   8 +-
 src/compiler/nir/nir_validate.c   |   6 +-
 src/compiler/spirv/OpenCL.std.h   | 211 
 src/compiler/spirv/spirv_to_nir.c |   4 +-
 src/compiler/spirv/vtn_alu.c  |  61 +++-
 src/compiler/spirv/vtn_glsl450.c  |  58 +---
 src/compiler/spirv/vtn_opencl.c   | 284 
 src/compiler/spirv/vtn_private.h  |   3 +
 src/compiler/spirv/vtn_subgroup.c |   2 +-
 src/gallium/auxiliary/nir/tgsi_to_nir.c   |   3 +-
 src/intel/blorp/blorp_blit.c  |   2 +-
 src/intel/blorp/blorp_clear.c |   2 +-
 .../compiler/brw_nir_lower_cs_intrinsics.c|   6 +-
 src/mesa/drivers/dri/i965/brw_tcs.c   |   2 +-
 34 files changed, 1220 insertions(+), 139 deletions(-)
 create mode 100644 src/compiler/nir/nir_builtin_builder.c
 create mode 100644 src/compiler/nir/nir_builtin_builder.h
 create mode 100644 src/compiler/spirv/OpenCL.std.h
 create mode 100644 src/compiler/spirv/vtn_opencl.c

-- 
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[Mesa-dev] [PATCH v2 2/8] nir: prepare for bumping up max components to 16

[Karol Herbst]

OpenCL knows vector of size 8 and 16.

v2: rebased on master (nir_swizzle rework)
rework more declarations with nir_component_mask_t
adjust print_var_decl

Reviewed-by: Jason Ekstrand 
Signed-off-by: Karol Herbst 
---
 src/compiler/nir/nir.c| 14 
 src/compiler/nir/nir.h| 34 ++-
 src/compiler/nir/nir_builder.h| 17 ++
 src/compiler/nir/nir_lower_alu_to_scalar.c|  6 ++--
 src/compiler/nir/nir_lower_io_to_scalar.c |  4 +--
 .../nir/nir_lower_load_const_to_scalar.c  |  2 +-
 src/compiler/nir/nir_opt_constant_folding.c   |  2 +-
 src/compiler/nir/nir_opt_copy_prop_vars.c |  4 +--
 src/compiler/nir/nir_print.c  |  9 ++---
 src/compiler/nir/nir_search.c |  8 ++---
 src/compiler/nir/nir_validate.c   |  6 ++--
 src/compiler/spirv/spirv_to_nir.c |  2 +-
 src/compiler/spirv/vtn_alu.c  |  2 +-
 13 files changed, 57 insertions(+), 53 deletions(-)

diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index ca89a46f7d4..bc7f05b3e86 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -251,7 +251,7 @@ nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src *src,
nir_src_copy(>src, >src, >instr);
dest->abs = src->abs;
dest->negate = src->negate;
-   for (unsigned i = 0; i < 4; i++)
+   for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++)
   dest->swizzle[i] = src->swizzle[i];
 }
 
@@ -421,10 +421,8 @@ alu_src_init(nir_alu_src *src)
 {
src_init(>src);
src->abs = src->negate = false;
-   src->swizzle[0] = 0;
-   src->swizzle[1] = 1;
-   src->swizzle[2] = 2;
-   src->swizzle[3] = 3;
+   for (int i = 0; i < NIR_MAX_VEC_COMPONENTS; ++i)
+  src->swizzle[i] = i;
 }
 
 nir_alu_instr *
@@ -1426,10 +1424,10 @@ nir_ssa_def_rewrite_uses_after(nir_ssa_def *def, 
nir_src new_src,
   nir_if_rewrite_condition(use_src->parent_if, new_src);
 }
 
-uint8_t
+nir_component_mask_t
 nir_ssa_def_components_read(const nir_ssa_def *def)
 {
-   uint8_t read_mask = 0;
+   nir_component_mask_t read_mask = 0;
nir_foreach_use(use, def) {
   if (use->parent_instr->type == nir_instr_type_alu) {
  nir_alu_instr *alu = nir_instr_as_alu(use->parent_instr);
@@ -1437,7 +1435,7 @@ nir_ssa_def_components_read(const nir_ssa_def *def)
  int src_idx = alu_src - >src[0];
  assert(src_idx >= 0 && src_idx < nir_op_infos[alu->op].num_inputs);
 
- for (unsigned c = 0; c < 4; c++) {
+ for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; c++) {
 if (!nir_alu_instr_channel_used(alu, src_idx, c))
continue;
 
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 92ab3a699cc..d3e63be091f 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -57,6 +57,8 @@ extern "C" {
 
 #define NIR_FALSE 0u
 #define NIR_TRUE (~0u)
+#define NIR_MAX_VEC_COMPONENTS 4
+typedef uint8_t nir_component_mask_t;
 
 /** Defines a cast function
  *
@@ -115,16 +117,16 @@ typedef enum {
 } nir_rounding_mode;
 
 typedef union {
-   float f32[4];
-   double f64[4];
-   int8_t i8[4];
-   uint8_t u8[4];
-   int16_t i16[4];
-   uint16_t u16[4];
-   int32_t i32[4];
-   uint32_t u32[4];
-   int64_t i64[4];
-   uint64_t u64[4];
+   float f32[NIR_MAX_VEC_COMPONENTS];
+   double f64[NIR_MAX_VEC_COMPONENTS];
+   int8_t i8[NIR_MAX_VEC_COMPONENTS];
+   uint8_t u8[NIR_MAX_VEC_COMPONENTS];
+   int16_t i16[NIR_MAX_VEC_COMPONENTS];
+   uint16_t u16[NIR_MAX_VEC_COMPONENTS];
+   int32_t i32[NIR_MAX_VEC_COMPONENTS];
+   uint32_t u32[NIR_MAX_VEC_COMPONENTS];
+   int64_t i64[NIR_MAX_VEC_COMPONENTS];
+   uint64_t u64[NIR_MAX_VEC_COMPONENTS];
 } nir_const_value;
 
 typedef struct nir_constant {
@@ -135,7 +137,7 @@ typedef struct nir_constant {
 * by the type associated with the \c nir_variable.  Constants may be
 * scalars, vectors, or matrices.
 */
-   nir_const_value values[4];
+   nir_const_value values[NIR_MAX_VEC_COMPONENTS];
 
/* we could get this from the var->type but makes clone *much* easier to
 * not have to care about the type.
@@ -697,7 +699,7 @@ typedef struct {
 * a statement like "foo.xzw = bar.zyx" would have a writemask of 1101b and
 * a swizzle of {2, x, 1, 0} where x means "don't care."
 */
-   uint8_t swizzle[4];
+   uint8_t swizzle[NIR_MAX_VEC_COMPONENTS];
 } nir_alu_src;
 
 typedef struct {
@@ -712,7 +714,7 @@ typedef struct {
 
bool saturate;
 
-   unsigned write_mask : 4; /* ignored if dest.is_ssa is true */
+   unsigned write_mask : NIR_MAX_VEC_COMPONENTS; /* ignored if dest.is_ssa is 
true */
 } nir_alu_dest;
 
 typedef enum {
@@ -841,14 +843,14 @@ typedef struct {
/**
 * The number of components in each input
 */
-   unsigned input_sizes[4];
+   unsigned input_sizes[NIR_MAX_VEC_COMPONENTS];
 
/**
 * The type of vector that each input takes. Note that negate and
 * absolute value are only allowed on inputs 

[Mesa-dev] [PATCH v2 1/8] nir: add builtin builder

[Karol Herbst]

also move some of the GLSL builtins over we will need for implementing
some OpenCL builtins

v2: replace NIR_IMM_FP by nir_imm_floatN_t in ported code
fix up changes caused by swizzle rework

Signed-off-by: Karol Herbst 
---
 src/compiler/Makefile.sources  |  2 +
 src/compiler/nir/meson.build   |  2 +
 src/compiler/nir/nir_builtin_builder.c | 65 +
 src/compiler/nir/nir_builtin_builder.h | 79 ++
 src/compiler/spirv/vtn_glsl450.c   | 58 +--
 5 files changed, 161 insertions(+), 45 deletions(-)
 create mode 100644 src/compiler/nir/nir_builtin_builder.c
 create mode 100644 src/compiler/nir/nir_builtin_builder.h

diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index db4dd1e89f4..cc147218c4e 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -203,6 +203,8 @@ NIR_FILES = \
nir/nir.c \
nir/nir.h \
nir/nir_builder.h \
+   nir/nir_builtin_builder.c \
+   nir/nir_builtin_builder.h \
nir/nir_clone.c \
nir/nir_constant_expressions.h \
nir/nir_control_flow.c \
diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
index 28aa8de7014..a1bb19356ce 100644
--- a/src/compiler/nir/meson.build
+++ b/src/compiler/nir/meson.build
@@ -87,6 +87,8 @@ files_libnir = files(
   'nir.c',
   'nir.h',
   'nir_builder.h',
+  'nir_builtin_builder.c',
+  'nir_builtin_builder.h',
   'nir_clone.c',
   'nir_constant_expressions.h',
   'nir_control_flow.c',
diff --git a/src/compiler/nir/nir_builtin_builder.c 
b/src/compiler/nir/nir_builtin_builder.c
new file mode 100644
index 000..252a7691f36
--- /dev/null
+++ b/src/compiler/nir/nir_builtin_builder.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright © 2018 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "nir.h"
+#include "nir_builtin_builder.h"
+
+nir_ssa_def*
+nir_cross(nir_builder *b, nir_ssa_def *x, nir_ssa_def *y)
+{
+   unsigned yzx[3] = { 1, 2, 0 };
+   unsigned zxy[3] = { 2, 0, 1 };
+
+   return nir_fsub(b, nir_fmul(b, nir_swizzle(b, x, yzx, 3, true),
+  nir_swizzle(b, y, zxy, 3, true)),
+  nir_fmul(b, nir_swizzle(b, x, zxy, 3, true),
+  nir_swizzle(b, y, yzx, 3, true)));
+}
+
+nir_ssa_def*
+nir_fast_length(nir_builder *b, nir_ssa_def *vec)
+{
+   switch (vec->num_components) {
+   case 1: return nir_fsqrt(b, nir_fmul(b, vec, vec));
+   case 2: return nir_fsqrt(b, nir_fdot2(b, vec, vec));
+   case 3: return nir_fsqrt(b, nir_fdot3(b, vec, vec));
+   case 4: return nir_fsqrt(b, nir_fdot4(b, vec, vec));
+   default:
+  unreachable("Invalid number of components");
+   }
+}
+
+nir_ssa_def*
+nir_smoothstep(nir_builder *b, nir_ssa_def *edge0, nir_ssa_def *edge1, 
nir_ssa_def *x)
+{
+   nir_ssa_def *f2 = nir_imm_floatN_t(b, 2.0, x->bit_size);
+   nir_ssa_def *f3 = nir_imm_floatN_t(b, 3.0, x->bit_size);
+
+   /* t = clamp((x - edge0) / (edge1 - edge0), 0, 1) */
+   nir_ssa_def *t =
+  nir_fsat(b, nir_fdiv(b, nir_fsub(b, x, edge0),
+  nir_fsub(b, edge1, edge0)));
+
+   /* result = t * t * (3 - 2 * t) */
+   return nir_fmul(b, t, nir_fmul(b, t, nir_fsub(b, f3, nir_fmul(b, f2, t;
+}
diff --git a/src/compiler/nir/nir_builtin_builder.h 
b/src/compiler/nir/nir_builtin_builder.h
new file mode 100644
index 000..5b76d012c85
--- /dev/null
+++ b/src/compiler/nir/nir_builtin_builder.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright © 2018 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, 

Re: [Mesa-dev] [PATCH V2 4/4] nir: add a couple of ior opts to nir_opt_algebraic

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

On Sun, Jul 15, 2018 at 10:19 PM Timothy Arceri 
wrote:

> One of these was seen in a Deus Ex shader.
>
> V2: make opts more generic.
>
> Cc: Jason Ekstrand 
> ---
>  src/compiler/nir/nir_opt_algebraic.py | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/src/compiler/nir/nir_opt_algebraic.py
> b/src/compiler/nir/nir_opt_algebraic.py
> index 0986dde6851..a9c2d821d7d 100644
> --- a/src/compiler/nir/nir_opt_algebraic.py
> +++ b/src/compiler/nir/nir_opt_algebraic.py
> @@ -286,6 +286,9 @@ optimizations = [
> (('iand', ('uge(is_used_once)', a, b), ('uge', a, c)), ('uge', a,
> ('umax', b, c))),
> (('iand', ('uge(is_used_once)', a, c), ('uge', b, c)), ('uge',
> ('umin', a, b), c)),
>
> +   (('ior', 'a@bool', ('ieq', a, False)), True),
> +   (('ior', 'a@bool', ('inot', a)), True),
> +
> (('iand', ('ieq', 'a@32', 0), ('ieq', 'b@32', 0)), ('ieq', ('ior',
> 'a@32', 'b@32'), 0)),
>
> # These patterns can result when (a < b || a < c) => (a < min(b, c))
> --
> 2.17.1
>
>
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[Mesa-dev] [PATCH] gm107/ir/lib: use xmad for imul/imad

[Rhys Perry]

Seems to be about two times faster at the cost of being larger, using and
clobbering one more register and being a little more difficult to read.

Signed-off-by: Rhys Perry 
---
 src/gallium/drivers/nouveau/codegen/lib/gm107.asm  | 92 ++---
 .../drivers/nouveau/codegen/lib/gm107.asm.h| 94 +++---
 .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp  |  2 +-
 3 files changed, 128 insertions(+), 60 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/lib/gm107.asm 
b/src/gallium/drivers/nouveau/codegen/lib/gm107.asm
index 7ee5f8fc65..d7db3ee7fb 100644
--- a/src/gallium/drivers/nouveau/codegen/lib/gm107.asm
+++ b/src/gallium/drivers/nouveau/codegen/lib/gm107.asm
@@ -7,36 +7,56 @@
 //
 // INPUT:   $r0: dividend, $r1: divisor
 // OUTPUT:  $r0: result, $r1: modulus
-// CLOBBER: $r2 - $r3, $p0 - $p1
-// SIZE:22 / 14 * 8 bytes
+// CLOBBER: $r2 - $r4, $p0 - $p1
+//
+// xmad $r4 s1 s0 s2
+// xmad mrg d0 s1 h1 s0 $r255
+// xmad psl cbcc d0 h1 s1 h1 d0 $r4
+// is d0 = s0 * s1 + s2 (clobbering $r4)
 //
 gm107_div_u32:
sched (st 0xd wr 0x0 wt 0x3f) (st 0x1 wt 0x1) (st 0x6)
flo u32 $r2 $r1
lop xor 1 $r2 $r2 0x1f
mov $r3 0x1 0xf
-   sched (st 0x1) (st 0xf wr 0x0) (st 0x6 wr 0x0 wt 0x1)
+   sched (st 0x1) (st 0xf wr 0x0) (st 0x1 wt 0x1)
shl $r2 $r3 $r2
i2i u32 u32 $r1 neg $r1
-   imul u32 u32 $r3 $r1 $r2
-   sched (st 0x6 wr 0x0 wt 0x1) (st 0x6 wr 0x0 wt 0x1) (st 0x6 wr 0x0 wt 0x1)
+   xmad $r4 $r2 $r1 $r255
+   sched (st 0x6) (st 0x6) (st 0x6 wr 0x0)
+   xmad mrg $r3 $r2 h1 $r1 $r255
+   xmad psl cbcc $r3 h1 $r2 h1 $r3 $r4
imad u32 u32 hi $r2 $r2 $r3 $r2
-   imul u32 u32 $r3 $r1 $r2
+   sched (st 0x1 wt 0x1) (st 0x6) (st 0x6)
+   xmad $r4 $r2 $r1 $r255
+   xmad mrg $r3 $r2 h1 $r1 $r255
+   xmad psl cbcc $r3 h1 $r2 h1 $r3 $r4
+   sched (st 0x6 wr 0x0) (st 0x1 wt 0x1) (st 0x6)
imad u32 u32 hi $r2 $r2 $r3 $r2
-   sched (st 0x6 wr 0x0 wt 0x1) (st 0x6 wr 0x0 wt 0x1) (st 0x6 wr 0x0 wt 0x1)
-   imul u32 u32 $r3 $r1 $r2
+   xmad $r4 $r2 $r1 $r255
+   xmad mrg $r3 $r2 h1 $r1 $r255
+   sched (st 0x6) (st 0x6 wr 0x0 wt 0x1) (st 0x1 wt 0x1)
+   xmad psl cbcc $r3 h1 $r2 h1 $r3 $r4
imad u32 u32 hi $r2 $r2 $r3 $r2
-   imul u32 u32 $r3 $r1 $r2
-   sched (st 0x6 wr 0x0 wt 0x1) (st 0x6 wr 0x0 wt 0x1) (st 0x6 wr 0x0 rd 0x1 
wt 0x1)
+   xmad $r4 $r2 $r1 $r255
+   sched (st 0x6) (st 0x6) (st 0x6 wr 0x0)
+   xmad mrg $r3 $r2 h1 $r1 $r255
+   xmad psl cbcc $r3 h1 $r2 h1 $r3 $r4
imad u32 u32 hi $r2 $r2 $r3 $r2
-   imul u32 u32 $r3 $r1 $r2
+   sched (st 0x1 wt 0x1) (st 0x6) (st 0x6)
+   xmad $r4 $r2 $r1 $r255
+   xmad mrg $r3 $r2 h1 $r1 $r255
+   xmad psl cbcc $r3 h1 $r2 h1 $r3 $r4
+   sched (st 0x6 wr 0x0 rd 0x1) (st 0x6 wt 0x2) (st 0x6 wr 0x0 rd 0x1 wt 0x1)
imad u32 u32 hi $r2 $r2 $r3 $r2
-   sched (st 0x6 wt 0x2) (st 0x6 wr 0x0 rd 0x1 wt 0x1) (st 0xf wr 0x0 rd 0x1 
wt 0x2)
mov $r3 $r0 0xf
imul u32 u32 hi $r0 $r0 $r2
+   sched (st 0xf wr 0x0 rd 0x1 wt 0x2) (st 0x1 wt 0x3) (st 0x6)
i2i u32 u32 $r2 neg $r1
-   sched (st 0x6 wr 0x0 wt 0x3) (st 0xd wt 0x1) (st 0x1)
-   imad u32 u32 $r1 $r1 $r0 $r3
+   xmad $r4 $r0 $r1 $r3
+   xmad mrg $r1 $r0 h1 $r1 $r255
+   sched (st 0x6) (st 0xd) (st 0x1)
+   xmad psl cbcc $r1 h1 $r0 h1 $r1 $r4
isetp ge u32 and $p0 1 $r1 $r2 1
$p0 iadd $r1 $r1 neg $r2
sched (st 0x5) (st 0xd) (st 0x1)
@@ -52,7 +72,7 @@ gm107_div_u32:
 //
 // INPUT:   $r0: dividend, $r1: divisor
 // OUTPUT:  $r0: result, $r1: modulus
-// CLOBBER: $r2 - $r3, $p0 - $p3
+// CLOBBER: $r2 - $r4, $p0 - $p3
 //
 gm107_div_s32:
sched (st 0xd wt 0x3f) (st 0x1) (st 0x1 wr 0x0)
@@ -63,35 +83,51 @@ gm107_div_s32:
i2i s32 s32 $r1 abs $r1
flo u32 $r2 $r1
lop xor 1 $r2 $r2 0x1f
-   sched (st 0x6) (st 0x1) (st 0xf wr 0x1)
+   sched (st 0x6) (st 0x1) (st 0xf wr 0x0)
mov $r3 0x1 0xf
shl $r2 $r3 $r2
i2i u32 u32 $r1 neg $r1
-   sched (st 0x6 wr 0x1 wt 0x2) (st 0x6 wr 0x1 wt 0x2) (st 0x6 wr 0x1 wt 0x2)
-   imul u32 u32 $r3 $r1 $r2
+   sched (st 0x1 wt 0x1) (st 0x6) (st 0x6)
+   xmad $r4 $r2 $r1 $r255
+   xmad mrg $r3 $r2 h1 $r1 $r255
+   xmad psl cbcc $r3 h1 $r2 h1 $r3 $r4
+   sched (st 0x6 wr 0x0) (st 0x1 wt 0x1) (st 0x6)
imad u32 u32 hi $r2 $r2 $r3 $r2
-   imul u32 u32 $r3 $r1 $r2
-   sched (st 0x6 wr 0x1 wt 0x2) (st 0x6 wr 0x1 wt 0x2) (st 0x6 wr 0x1 wt 0x2)
+   xmad $r4 $r2 $r1 $r255
+   xmad mrg $r3 $r2 h1 $r1 $r255
+   sched (st 0x6) (st 0x6 wr 0x0) (st 0x1 wt 0x1)
+   xmad psl cbcc $r3 h1 $r2 h1 $r3 $r4
imad u32 u32 hi $r2 $r2 $r3 $r2
-   imul u32 u32 $r3 $r1 $r2
+   xmad $r4 $r2 $r1 $r255
+   sched (st 0x6) (st 0x6) (st 0x6 wr 0x0 wt 0x1)
+   xmad mrg $r3 $r2 h1 $r1 $r255
+   xmad psl cbcc $r3 h1 $r2 h1 $r3 $r4
imad u32 u32 hi $r2 $r2 $r3 $r2
-   sched (st 0x6 wr 0x1 wt 0x2) (st 0x6 wr 0x1 wt 0x2) (st 0x6 wr 0x1 wt 0x2)
-   imul u32 u32 $r3 $r1 $r2
+   sched (st 0x1 wt 0x1) (st 0x6) (st 0x6)
+   xmad $r4 $r2 $r1 $r255
+   xmad mrg $r3 $r2 h1 $r1 $r255
+   xmad psl cbcc $r3 h1 $r2 h1 $r3 $r4
+   sched (st 

Re: [Mesa-dev] [PATCH 1/3] virgl: move bind-flags to virgl_winsys.h

[Erik Faye-Lund]

On 16. juli 2018 13:34, Gert Wollny wrote:

Am Montag, den 16.07.2018, 12:23 +0200 schrieb Erik Faye-Lund:

virglrenderer's virgl_hw.h doesn't contain these, and it's the
virgl winsys that cares about these, so let's move them there.

This reduces the diff between the two different versions of
virgl_hw.h, and should make it easier to upgrade the file in
the future.

Signed-off-by: Erik Faye-Lund 
---
  src/gallium/drivers/virgl/virgl_hw.h   | 12 
  src/gallium/drivers/virgl/virgl_resource.h |  2 ++
  src/gallium/drivers/virgl/virgl_winsys.h   | 12 
  3 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_hw.h
b/src/gallium/drivers/virgl/virgl_hw.h
index 157267558a..d0df23e2f6 100644
--- a/src/gallium/drivers/virgl/virgl_hw.h
+++ b/src/gallium/drivers/virgl/virgl_hw.h
@@ -202,18 +202,6 @@ enum virgl_formats {
  #define VIRGL_CAP_TGSI_INVARIANT   (1 << 0)
  #define VIRGL_CAP_TEXTURE_VIEW (1 << 1)
  
-#define VIRGL_BIND_DEPTH_STENCIL (1 << 0)

-#define VIRGL_BIND_RENDER_TARGET (1 << 1)
-#define VIRGL_BIND_SAMPLER_VIEW  (1 << 3)
-#define VIRGL_BIND_VERTEX_BUFFER (1 << 4)
-#define VIRGL_BIND_INDEX_BUFFER  (1 << 5)
-#define VIRGL_BIND_CONSTANT_BUFFER (1 << 6)
-#define VIRGL_BIND_DISPLAY_TARGET (1 << 7)
-#define VIRGL_BIND_STREAM_OUTPUT (1 << 11)
-#define VIRGL_BIND_CURSOR(1 << 16)
-#define VIRGL_BIND_CUSTOM(1 << 17)
-#define VIRGL_BIND_SCANOUT   (1 << 18)
-

In virglrenderer there is a set of VREND_RES_* that are mostly the
same, so I assume that they should be in sync (I wouldn't bet on it
though). If it can be resolved that these two sets are independent of
each other then the patch is
   Reviewed-By: Gert Wollny 

Otherwise it might be better to move the VREND_RES_* defines into
virgl_hw.h in virglrenderer and rename so that at one point the two
virgl_hw.h files will have the same content.


Oh, thanks for noticing. Yeah, these need to be the same. They get 
passed through virgl_drm_winsys_resource_cache_create() to the 
VIRTGPU_RESOURCE_CREATEioctl, to VIRTIO_GPU_CMD_RESOURCE_CREATE_3D in 
qemu, and in turn gets interpreted by vrend_renderer_resource_create...


So yeah, these needs to be in sync. I guess the pragmatic choice would 
be to use these definitions in virglrenderer's copy here. I'll send a 
new proposal to virglrenderer for this bit, and drop this patch from 
this series.
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Re: [Mesa-dev] [PATCH 3/3] virgl: update virgl_hw.h from virglrenderer

[Gert Wollny]

As you said, patch 2/3 will need rebasing now. With that 
patches 2 and 3 are 
  Reviewed-By: Gert Wollny 

Am Montag, den 16.07.2018, 12:23 +0200 schrieb Erik Faye-Lund:
> This just makes sure we're currently up-to-date with what
> virglrenderer has.
> 
> Signed-off-by: Erik Faye-Lund 
> ---
>  src/gallium/drivers/virgl/virgl_hw.h | 19 ++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/src/gallium/drivers/virgl/virgl_hw.h
> b/src/gallium/drivers/virgl/virgl_hw.h
> index 086757def6..ff6a3430e5 100644
> --- a/src/gallium/drivers/virgl/virgl_hw.h
> +++ b/src/gallium/drivers/virgl/virgl_hw.h
> @@ -37,6 +37,7 @@ enum virgl_formats {
> VIRGL_FORMAT_B5G5R5A1_UNORM  = 5,
> VIRGL_FORMAT_B4G4R4A4_UNORM  = 6,
> VIRGL_FORMAT_B5G6R5_UNORM= 7,
> +   VIRGL_FORMAT_R10G10B10A2_UNORM   = 8,
> VIRGL_FORMAT_L8_UNORM= 9,/**< ubyte luminance
> */
> VIRGL_FORMAT_A8_UNORM= 10,   /**< ubyte alpha */
> VIRGL_FORMAT_L8A8_UNORM  = 12,   /**< ubyte alpha,
> luminance */
> @@ -112,6 +113,8 @@ enum virgl_formats {
> VIRGL_FORMAT_B10G10R10A2_UNORM   = 131,
> VIRGL_FORMAT_R8G8B8X8_UNORM  = 134,
> VIRGL_FORMAT_B4G4R4X4_UNORM  = 135,
> +   VIRGL_FORMAT_X24S8_UINT  = 136,
> +   VIRGL_FORMAT_S8X24_UINT  = 137,
> VIRGL_FORMAT_B2G3R3_UNORM= 139,
>  
> VIRGL_FORMAT_L16A16_UNORM= 140,
> @@ -186,7 +189,7 @@ enum virgl_formats {
> VIRGL_FORMAT_L32_SINT= 223,
> VIRGL_FORMAT_L32A32_SINT = 224,
>  
> -   VIRGL_FORMAT_B10G10R10A2_UINT= 225, 
> +   VIRGL_FORMAT_B10G10R10A2_UINT= 225,
> VIRGL_FORMAT_R8G8B8X8_SNORM  = 229,
>  
> VIRGL_FORMAT_R8G8B8X8_SRGB   = 230,
> @@ -194,6 +197,16 @@ enum virgl_formats {
> VIRGL_FORMAT_B10G10R10X2_UNORM   = 233,
> VIRGL_FORMAT_R16G16B16X16_UNORM  = 234,
> VIRGL_FORMAT_R16G16B16X16_SNORM  = 235,
> +
> +   VIRGL_FORMAT_R10G10B10A2_UINT= 253,
> +
> +   VIRGL_FORMAT_BPTC_RGBA_UNORM = 255,
> +   VIRGL_FORMAT_BPTC_SRGBA  = 256,
> +   VIRGL_FORMAT_BPTC_RGB_FLOAT  = 257,
> +   VIRGL_FORMAT_BPTC_RGB_UFLOAT = 258,
> +
> +   VIRGL_FORMAT_R10G10B10X2_UNORM   = 308,
> +   VIRGL_FORMAT_A4B4G4R4_UNORM  = 311,
> VIRGL_FORMAT_MAX,
>  };
>  
> @@ -263,6 +276,10 @@ struct virgl_caps_v1 {
>  uint32_t max_texture_gather_components;
>  };
>  
> +/*
> + * This struct should be growable when used in capset 2,
> + * so we shouldn't have to add a v3 ever.
> + */
>  struct virgl_caps_v2 {
>  struct virgl_caps_v1 v1;
>  float min_aliased_point_size;
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Re: [Mesa-dev] [PATCH 1/3] virgl: move bind-flags to virgl_winsys.h

[Gert Wollny]

Am Montag, den 16.07.2018, 12:23 +0200 schrieb Erik Faye-Lund:
> virglrenderer's virgl_hw.h doesn't contain these, and it's the
> virgl winsys that cares about these, so let's move them there.
> 
> This reduces the diff between the two different versions of
> virgl_hw.h, and should make it easier to upgrade the file in
> the future.
> 
> Signed-off-by: Erik Faye-Lund 
> ---
>  src/gallium/drivers/virgl/virgl_hw.h   | 12 
>  src/gallium/drivers/virgl/virgl_resource.h |  2 ++
>  src/gallium/drivers/virgl/virgl_winsys.h   | 12 
>  3 files changed, 14 insertions(+), 12 deletions(-)
> 
> diff --git a/src/gallium/drivers/virgl/virgl_hw.h
> b/src/gallium/drivers/virgl/virgl_hw.h
> index 157267558a..d0df23e2f6 100644
> --- a/src/gallium/drivers/virgl/virgl_hw.h
> +++ b/src/gallium/drivers/virgl/virgl_hw.h
> @@ -202,18 +202,6 @@ enum virgl_formats {
>  #define VIRGL_CAP_TGSI_INVARIANT   (1 << 0)
>  #define VIRGL_CAP_TEXTURE_VIEW (1 << 1)
>  
> -#define VIRGL_BIND_DEPTH_STENCIL (1 << 0)
> -#define VIRGL_BIND_RENDER_TARGET (1 << 1)
> -#define VIRGL_BIND_SAMPLER_VIEW  (1 << 3)
> -#define VIRGL_BIND_VERTEX_BUFFER (1 << 4)
> -#define VIRGL_BIND_INDEX_BUFFER  (1 << 5)
> -#define VIRGL_BIND_CONSTANT_BUFFER (1 << 6)
> -#define VIRGL_BIND_DISPLAY_TARGET (1 << 7)
> -#define VIRGL_BIND_STREAM_OUTPUT (1 << 11)
> -#define VIRGL_BIND_CURSOR(1 << 16)
> -#define VIRGL_BIND_CUSTOM(1 << 17)
> -#define VIRGL_BIND_SCANOUT   (1 << 18)
> -

In virglrenderer there is a set of VREND_RES_* that are mostly the
same, so I assume that they should be in sync (I wouldn't bet on it
though). If it can be resolved that these two sets are independent of
each other then the patch is 
  Reviewed-By: Gert Wollny 

Otherwise it might be better to move the VREND_RES_* defines into
virgl_hw.h in virglrenderer and rename so that at one point the two
virgl_hw.h files will have the same content.

>  struct virgl_caps_bool_set1 {
>  unsigned indep_blend_enable:1;
>  unsigned indep_blend_func:1;
> diff --git a/src/gallium/drivers/virgl/virgl_resource.h
> b/src/gallium/drivers/virgl/virgl_resource.h
> index bab9bcb9b4..d9ad4733b4 100644
> --- a/src/gallium/drivers/virgl/virgl_resource.h
> +++ b/src/gallium/drivers/virgl/virgl_resource.h
> @@ -30,6 +30,8 @@
>  #include "util/u_transfer.h"
>  
>  #include "virgl_hw.h"
> +#include "virgl_winsys.h"
> +
>  #define VR_MAX_TEXTURE_2D_LEVELS 15
>  
>  struct winsys_handle;
> diff --git a/src/gallium/drivers/virgl/virgl_winsys.h
> b/src/gallium/drivers/virgl/virgl_winsys.h
> index 99ab4d3840..acd68c060e 100644
> --- a/src/gallium/drivers/virgl/virgl_winsys.h
> +++ b/src/gallium/drivers/virgl/virgl_winsys.h
> @@ -42,6 +42,18 @@ struct virgl_cmd_buf {
> uint32_t *buf;
>  };
>  
> +#define VIRGL_BIND_DEPTH_STENCIL (1 << 0)
> +#define VIRGL_BIND_RENDER_TARGET (1 << 1)
> +#define VIRGL_BIND_SAMPLER_VIEW  (1 << 3)
> +#define VIRGL_BIND_VERTEX_BUFFER (1 << 4)
> +#define VIRGL_BIND_INDEX_BUFFER  (1 << 5)
> +#define VIRGL_BIND_CONSTANT_BUFFER (1 << 6)
> +#define VIRGL_BIND_DISPLAY_TARGET (1 << 7)
> +#define VIRGL_BIND_STREAM_OUTPUT (1 << 11)
> +#define VIRGL_BIND_CURSOR(1 << 16)
> +#define VIRGL_BIND_CUSTOM(1 << 17)
> +#define VIRGL_BIND_SCANOUT   (1 << 18)
> +
>  struct virgl_winsys {
> unsigned pci_id;
>  
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Re: [Mesa-dev] [PATCH] mesa/virgl: Fix off-by-one and copy-paste error in multisample position evaluation

[Gert Wollny]

Am Montag, den 16.07.2018, 12:11 +0200 schrieb Erik Faye-Lund:
> On 13. juli 2018 14:46, Gert Wollny wrote:
> > Fixes: 91f48cdfe5c817158c533a8f67c60e9aabbe4479
> > virgl: Add support for glGetMultisample
> > Signed-off-by: Gert Wollny 
> > ---
> >   src/gallium/drivers/virgl/virgl_context.c | 6 +++---
> >   1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/src/gallium/drivers/virgl/virgl_context.c
> > b/src/gallium/drivers/virgl/virgl_context.c
> > index d985bf906f..f5e3832d99 100644
> > --- a/src/gallium/drivers/virgl/virgl_context.c
> > +++ b/src/gallium/drivers/virgl/virgl_context.c
> > @@ -943,11 +943,11 @@ static void virgl_get_sample_position(struct
> > pipe_context *ctx,
> > return;
> >  } else if (sample_count == 2) {
> > bits = vs->caps.caps.v2.msaa_sample_positions[0] >> (8 *
> > index);
> > -   } else if (sample_count < 4) {
> > +   } else if (sample_count <= 4) {
> > bits = vs->caps.caps.v2.msaa_sample_positions[1] >> (8 *
> > index);
> > -   } else if (sample_count < 8) {
> > +   } else if (sample_count <= 8) {
> > bits = vs->caps.caps.v2.msaa_sample_positions[2 + (index >>
> > 2)] >> (8 * (index & 3));
> > -   } else if (sample_count < 8) {
> > +   } else if (sample_count <= 16) {
> 
> This isn't technically speaking an off-by-one... perhaps adjust the 
> commit message a bit?

That was the copy-paste error part, but I'll clarify the commit message

thanks for reviewing, 
Gert  
> 
> > bits = vs->caps.caps.v2.msaa_sample_positions[4 + (index >>
> > 2)] >> (8 * (index & 3));
> >  }
> >  out_value[0] = ((bits >> 4) & 0xf) / 16.0f;
> 
> Reviewed-by: Erik Faye-Lund 
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[Mesa-dev] [PATCH] virgl: implement set_min_samples

[Erik Faye-Lund]

This allows us to implement glMinSampleShading correctly, which up
until now just got ignored.

Signed-off-by: Erik Faye-Lund 
---

This implements the mesa-side of VIRGL_CCMD_SET_MIN_SAMPLES, which
is already in the master-branch of virglre...

 src/gallium/drivers/virgl/virgl_context.c  | 12 
 src/gallium/drivers/virgl/virgl_encode.c   |  7 +++
 src/gallium/drivers/virgl/virgl_encode.h   |  3 +++
 src/gallium/drivers/virgl/virgl_hw.h   |  1 +
 src/gallium/drivers/virgl/virgl_protocol.h |  5 +
 5 files changed, 28 insertions(+)

diff --git a/src/gallium/drivers/virgl/virgl_context.c 
b/src/gallium/drivers/virgl/virgl_context.c
index d985bf906f..6f0695ee2c 100644
--- a/src/gallium/drivers/virgl/virgl_context.c
+++ b/src/gallium/drivers/virgl/virgl_context.c
@@ -844,6 +844,17 @@ static void virgl_set_sample_mask(struct pipe_context *ctx,
virgl_encoder_set_sample_mask(vctx, sample_mask);
 }
 
+static void virgl_set_min_samples(struct pipe_context *ctx,
+ unsigned min_samples)
+{
+   struct virgl_context *vctx = virgl_context(ctx);
+   struct virgl_screen *rs = virgl_screen(ctx->screen);
+
+   if (!(rs->caps.caps.v2.capability_bits & VIRGL_CAP_SET_MIN_SAMPLES))
+  return;
+   virgl_encoder_set_min_samples(vctx, min_samples);
+}
+
 static void virgl_set_clip_state(struct pipe_context *ctx,
 const struct pipe_clip_state *clip)
 {
@@ -1025,6 +1036,7 @@ struct pipe_context *virgl_context_create(struct 
pipe_screen *pscreen,
vctx->base.set_polygon_stipple = virgl_set_polygon_stipple;
vctx->base.set_scissor_states = virgl_set_scissor_states;
vctx->base.set_sample_mask = virgl_set_sample_mask;
+   vctx->base.set_min_samples = virgl_set_min_samples;
vctx->base.set_stencil_ref = virgl_set_stencil_ref;
vctx->base.set_clip_state = virgl_set_clip_state;
 
diff --git a/src/gallium/drivers/virgl/virgl_encode.c 
b/src/gallium/drivers/virgl/virgl_encode.c
index 6b800d3d07..c7c6b1e7d3 100644
--- a/src/gallium/drivers/virgl/virgl_encode.c
+++ b/src/gallium/drivers/virgl/virgl_encode.c
@@ -726,6 +726,13 @@ void virgl_encoder_set_sample_mask(struct virgl_context 
*ctx,
virgl_encoder_write_dword(ctx->cbuf, sample_mask);
 }
 
+void virgl_encoder_set_min_samples(struct virgl_context *ctx,
+  unsigned min_samples)
+{
+   virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_MIN_SAMPLES, 
0, VIRGL_SET_MIN_SAMPLES_SIZE));
+   virgl_encoder_write_dword(ctx->cbuf, min_samples);
+}
+
 void virgl_encoder_set_clip_state(struct virgl_context *ctx,
  const struct pipe_clip_state *clip)
 {
diff --git a/src/gallium/drivers/virgl/virgl_encode.h 
b/src/gallium/drivers/virgl/virgl_encode.h
index 837075ea48..21c506eb56 100644
--- a/src/gallium/drivers/virgl/virgl_encode.h
+++ b/src/gallium/drivers/virgl/virgl_encode.h
@@ -211,6 +211,9 @@ void virgl_encoder_set_polygon_stipple(struct virgl_context 
*ctx,
 void virgl_encoder_set_sample_mask(struct virgl_context *ctx,
   unsigned sample_mask);
 
+void virgl_encoder_set_min_samples(struct virgl_context *ctx,
+  unsigned min_samples);
+
 void virgl_encoder_set_clip_state(struct virgl_context *ctx,
  const struct pipe_clip_state *clip);
 
diff --git a/src/gallium/drivers/virgl/virgl_hw.h 
b/src/gallium/drivers/virgl/virgl_hw.h
index 157267558a..118249e695 100644
--- a/src/gallium/drivers/virgl/virgl_hw.h
+++ b/src/gallium/drivers/virgl/virgl_hw.h
@@ -201,6 +201,7 @@ enum virgl_formats {
 #define VIRGL_CAP_NONE 0
 #define VIRGL_CAP_TGSI_INVARIANT   (1 << 0)
 #define VIRGL_CAP_TEXTURE_VIEW (1 << 1)
+#define VIRGL_CAP_SET_MIN_SAMPLES  (1 << 2)
 
 #define VIRGL_BIND_DEPTH_STENCIL (1 << 0)
 #define VIRGL_BIND_RENDER_TARGET (1 << 1)
diff --git a/src/gallium/drivers/virgl/virgl_protocol.h 
b/src/gallium/drivers/virgl/virgl_protocol.h
index bd5a8b4043..53493d5c15 100644
--- a/src/gallium/drivers/virgl/virgl_protocol.h
+++ b/src/gallium/drivers/virgl/virgl_protocol.h
@@ -85,6 +85,7 @@ enum virgl_context_cmd {
VIRGL_CCMD_BIND_SHADER,
 
VIRGL_CCMD_SET_TESS_STATE,
+   VIRGL_CCMD_SET_MIN_SAMPLES,
 };
 
 /*
@@ -486,4 +487,8 @@ enum virgl_context_cmd {
 /* tess state */
 #define VIRGL_TESS_STATE_SIZE 6
 
+/* set min samples */
+#define VIRGL_SET_MIN_SAMPLES_SIZE 1
+#define VIRGL_SET_MIN_SAMPLES_MASK 1
+
 #endif
-- 
2.18.0.rc2

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Re: [Mesa-dev] [PATCH] mesa/virgl: Fix off-by-one and copy-paste error in multisample position evaluation

[Erik Faye-Lund]

Just a heads-up, this patch conflicts with this one:

https://patchwork.freedesktop.org/patch/239169/

Your were sent out first, so I'll be happy to rebase mine when this has 
landed...


On 13. juli 2018 14:46, Gert Wollny wrote:

Fixes: 91f48cdfe5c817158c533a8f67c60e9aabbe4479
virgl: Add support for glGetMultisample
Signed-off-by: Gert Wollny 
---
  src/gallium/drivers/virgl/virgl_context.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_context.c 
b/src/gallium/drivers/virgl/virgl_context.c
index d985bf906f..f5e3832d99 100644
--- a/src/gallium/drivers/virgl/virgl_context.c
+++ b/src/gallium/drivers/virgl/virgl_context.c
@@ -943,11 +943,11 @@ static void virgl_get_sample_position(struct pipe_context 
*ctx,
return;
 } else if (sample_count == 2) {
bits = vs->caps.caps.v2.msaa_sample_positions[0] >> (8 * index);
-   } else if (sample_count < 4) {
+   } else if (sample_count <= 4) {
bits = vs->caps.caps.v2.msaa_sample_positions[1] >> (8 * index);
-   } else if (sample_count < 8) {
+   } else if (sample_count <= 8) {
bits = vs->caps.caps.v2.msaa_sample_positions[2 + (index >> 2)] >> (8 * 
(index & 3));
-   } else if (sample_count < 8) {
+   } else if (sample_count <= 16) {
bits = vs->caps.caps.v2.msaa_sample_positions[4 + (index >> 2)] >> (8 * 
(index & 3));
 }
 out_value[0] = ((bits >> 4) & 0xf) / 16.0f;


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[Mesa-dev] [PATCH 2/3] virgl: rename msaa_sample_positions -> sample_locations

[Erik Faye-Lund]

This matches what this field is called in virglrenderer's copy of
this.

While we're at it, fixup the indentation.

This reduces the diff between the two different versions of
virgl_hw.h, and should make it easier to upgrade the file in
the future.

Signed-off-by: Erik Faye-Lund 
---
 src/gallium/drivers/virgl/virgl_context.c | 8 
 src/gallium/drivers/virgl/virgl_hw.h  | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_context.c 
b/src/gallium/drivers/virgl/virgl_context.c
index d985bf906f..b1e2f3ee42 100644
--- a/src/gallium/drivers/virgl/virgl_context.c
+++ b/src/gallium/drivers/virgl/virgl_context.c
@@ -942,13 +942,13 @@ static void virgl_get_sample_position(struct pipe_context 
*ctx,
   out_value[0] = out_value[1] = 0.5f;
   return;
} else if (sample_count == 2) {
-  bits = vs->caps.caps.v2.msaa_sample_positions[0] >> (8 * index);
+  bits = vs->caps.caps.v2.sample_locations[0] >> (8 * index);
} else if (sample_count < 4) {
-  bits = vs->caps.caps.v2.msaa_sample_positions[1] >> (8 * index);
+  bits = vs->caps.caps.v2.sample_locations[1] >> (8 * index);
} else if (sample_count < 8) {
-  bits = vs->caps.caps.v2.msaa_sample_positions[2 + (index >> 2)] >> (8 * 
(index & 3));
+  bits = vs->caps.caps.v2.sample_locations[2 + (index >> 2)] >> (8 * 
(index & 3));
} else if (sample_count < 8) {
-  bits = vs->caps.caps.v2.msaa_sample_positions[4 + (index >> 2)] >> (8 * 
(index & 3));
+  bits = vs->caps.caps.v2.sample_locations[4 + (index >> 2)] >> (8 * 
(index & 3));
}
out_value[0] = ((bits >> 4) & 0xf) / 16.0f;
out_value[1] = (bits & 0xf) / 16.0f;
diff --git a/src/gallium/drivers/virgl/virgl_hw.h 
b/src/gallium/drivers/virgl/virgl_hw.h
index d0df23e2f6..086757def6 100644
--- a/src/gallium/drivers/virgl/virgl_hw.h
+++ b/src/gallium/drivers/virgl/virgl_hw.h
@@ -287,7 +287,7 @@ struct virgl_caps_v2 {
 uint32_t uniform_buffer_offset_alignment;
 uint32_t shader_buffer_offset_alignment;
 uint32_t capability_bits;
-   uint32_t msaa_sample_positions[8];
+uint32_t sample_locations[8];
 };
 
 union virgl_caps {
-- 
2.18.0.rc2

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[Mesa-dev] [PATCH 3/3] virgl: update virgl_hw.h from virglrenderer

[Erik Faye-Lund]

This just makes sure we're currently up-to-date with what
virglrenderer has.

Signed-off-by: Erik Faye-Lund 
---
 src/gallium/drivers/virgl/virgl_hw.h | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/virgl/virgl_hw.h 
b/src/gallium/drivers/virgl/virgl_hw.h
index 086757def6..ff6a3430e5 100644
--- a/src/gallium/drivers/virgl/virgl_hw.h
+++ b/src/gallium/drivers/virgl/virgl_hw.h
@@ -37,6 +37,7 @@ enum virgl_formats {
VIRGL_FORMAT_B5G5R5A1_UNORM  = 5,
VIRGL_FORMAT_B4G4R4A4_UNORM  = 6,
VIRGL_FORMAT_B5G6R5_UNORM= 7,
+   VIRGL_FORMAT_R10G10B10A2_UNORM   = 8,
VIRGL_FORMAT_L8_UNORM= 9,/**< ubyte luminance */
VIRGL_FORMAT_A8_UNORM= 10,   /**< ubyte alpha */
VIRGL_FORMAT_L8A8_UNORM  = 12,   /**< ubyte alpha, luminance */
@@ -112,6 +113,8 @@ enum virgl_formats {
VIRGL_FORMAT_B10G10R10A2_UNORM   = 131,
VIRGL_FORMAT_R8G8B8X8_UNORM  = 134,
VIRGL_FORMAT_B4G4R4X4_UNORM  = 135,
+   VIRGL_FORMAT_X24S8_UINT  = 136,
+   VIRGL_FORMAT_S8X24_UINT  = 137,
VIRGL_FORMAT_B2G3R3_UNORM= 139,
 
VIRGL_FORMAT_L16A16_UNORM= 140,
@@ -186,7 +189,7 @@ enum virgl_formats {
VIRGL_FORMAT_L32_SINT= 223,
VIRGL_FORMAT_L32A32_SINT = 224,
 
-   VIRGL_FORMAT_B10G10R10A2_UINT= 225, 
+   VIRGL_FORMAT_B10G10R10A2_UINT= 225,
VIRGL_FORMAT_R8G8B8X8_SNORM  = 229,
 
VIRGL_FORMAT_R8G8B8X8_SRGB   = 230,
@@ -194,6 +197,16 @@ enum virgl_formats {
VIRGL_FORMAT_B10G10R10X2_UNORM   = 233,
VIRGL_FORMAT_R16G16B16X16_UNORM  = 234,
VIRGL_FORMAT_R16G16B16X16_SNORM  = 235,
+
+   VIRGL_FORMAT_R10G10B10A2_UINT= 253,
+
+   VIRGL_FORMAT_BPTC_RGBA_UNORM = 255,
+   VIRGL_FORMAT_BPTC_SRGBA  = 256,
+   VIRGL_FORMAT_BPTC_RGB_FLOAT  = 257,
+   VIRGL_FORMAT_BPTC_RGB_UFLOAT = 258,
+
+   VIRGL_FORMAT_R10G10B10X2_UNORM   = 308,
+   VIRGL_FORMAT_A4B4G4R4_UNORM  = 311,
VIRGL_FORMAT_MAX,
 };
 
@@ -263,6 +276,10 @@ struct virgl_caps_v1 {
 uint32_t max_texture_gather_components;
 };
 
+/*
+ * This struct should be growable when used in capset 2,
+ * so we shouldn't have to add a v3 ever.
+ */
 struct virgl_caps_v2 {
 struct virgl_caps_v1 v1;
 float min_aliased_point_size;
-- 
2.18.0.rc2

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[Mesa-dev] [PATCH 1/3] virgl: move bind-flags to virgl_winsys.h

[Erik Faye-Lund]

virglrenderer's virgl_hw.h doesn't contain these, and it's the
virgl winsys that cares about these, so let's move them there.

This reduces the diff between the two different versions of
virgl_hw.h, and should make it easier to upgrade the file in
the future.

Signed-off-by: Erik Faye-Lund 
---
 src/gallium/drivers/virgl/virgl_hw.h   | 12 
 src/gallium/drivers/virgl/virgl_resource.h |  2 ++
 src/gallium/drivers/virgl/virgl_winsys.h   | 12 
 3 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_hw.h 
b/src/gallium/drivers/virgl/virgl_hw.h
index 157267558a..d0df23e2f6 100644
--- a/src/gallium/drivers/virgl/virgl_hw.h
+++ b/src/gallium/drivers/virgl/virgl_hw.h
@@ -202,18 +202,6 @@ enum virgl_formats {
 #define VIRGL_CAP_TGSI_INVARIANT   (1 << 0)
 #define VIRGL_CAP_TEXTURE_VIEW (1 << 1)
 
-#define VIRGL_BIND_DEPTH_STENCIL (1 << 0)
-#define VIRGL_BIND_RENDER_TARGET (1 << 1)
-#define VIRGL_BIND_SAMPLER_VIEW  (1 << 3)
-#define VIRGL_BIND_VERTEX_BUFFER (1 << 4)
-#define VIRGL_BIND_INDEX_BUFFER  (1 << 5)
-#define VIRGL_BIND_CONSTANT_BUFFER (1 << 6)
-#define VIRGL_BIND_DISPLAY_TARGET (1 << 7)
-#define VIRGL_BIND_STREAM_OUTPUT (1 << 11)
-#define VIRGL_BIND_CURSOR(1 << 16)
-#define VIRGL_BIND_CUSTOM(1 << 17)
-#define VIRGL_BIND_SCANOUT   (1 << 18)
-
 struct virgl_caps_bool_set1 {
 unsigned indep_blend_enable:1;
 unsigned indep_blend_func:1;
diff --git a/src/gallium/drivers/virgl/virgl_resource.h 
b/src/gallium/drivers/virgl/virgl_resource.h
index bab9bcb9b4..d9ad4733b4 100644
--- a/src/gallium/drivers/virgl/virgl_resource.h
+++ b/src/gallium/drivers/virgl/virgl_resource.h
@@ -30,6 +30,8 @@
 #include "util/u_transfer.h"
 
 #include "virgl_hw.h"
+#include "virgl_winsys.h"
+
 #define VR_MAX_TEXTURE_2D_LEVELS 15
 
 struct winsys_handle;
diff --git a/src/gallium/drivers/virgl/virgl_winsys.h 
b/src/gallium/drivers/virgl/virgl_winsys.h
index 99ab4d3840..acd68c060e 100644
--- a/src/gallium/drivers/virgl/virgl_winsys.h
+++ b/src/gallium/drivers/virgl/virgl_winsys.h
@@ -42,6 +42,18 @@ struct virgl_cmd_buf {
uint32_t *buf;
 };
 
+#define VIRGL_BIND_DEPTH_STENCIL (1 << 0)
+#define VIRGL_BIND_RENDER_TARGET (1 << 1)
+#define VIRGL_BIND_SAMPLER_VIEW  (1 << 3)
+#define VIRGL_BIND_VERTEX_BUFFER (1 << 4)
+#define VIRGL_BIND_INDEX_BUFFER  (1 << 5)
+#define VIRGL_BIND_CONSTANT_BUFFER (1 << 6)
+#define VIRGL_BIND_DISPLAY_TARGET (1 << 7)
+#define VIRGL_BIND_STREAM_OUTPUT (1 << 11)
+#define VIRGL_BIND_CURSOR(1 << 16)
+#define VIRGL_BIND_CUSTOM(1 << 17)
+#define VIRGL_BIND_SCANOUT   (1 << 18)
+
 struct virgl_winsys {
unsigned pci_id;
 
-- 
2.18.0.rc2

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[Mesa-dev] [PATCH 0/3] virgl: synchronize virgl_hw.h with virglrenderer

[Erik Faye-Lund]

Here's a few patches to get the delta between our copy of virgl_hw.h and the
copy in the virglrenderer repository as small as possible.

The goal is to make it easier to track this file in the future by simply
copying the new version of the file on top of the old.

I've left out one new cap that currently exists in master
(VIRGL_CAP_SET_MIN_SAMPLES), for two reasons:
reasons:

1. It wasn't yet in master when I generated this patch-set
2. I'm about to send out a patch-set that adds it (and respects it)
   separately.

Erik Faye-Lund (3):
  virgl: move bind-flags to virgl_winsys.h
  virgl: rename msaa_sample_positions -> sample_locations
  virgl: update virgl_hw.h from virglrenderer

 src/gallium/drivers/virgl/virgl_context.c  |  8 +++---
 src/gallium/drivers/virgl/virgl_hw.h   | 33 +-
 src/gallium/drivers/virgl/virgl_resource.h |  2 ++
 src/gallium/drivers/virgl/virgl_winsys.h   | 12 
 4 files changed, 37 insertions(+), 18 deletions(-)

-- 
2.18.0.rc2

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Re: [Mesa-dev] [PATCH] mesa/virgl: Fix off-by-one and copy-paste error in multisample position evaluation

[Erik Faye-Lund]

On 13. juli 2018 14:46, Gert Wollny wrote:

Fixes: 91f48cdfe5c817158c533a8f67c60e9aabbe4479
virgl: Add support for glGetMultisample
Signed-off-by: Gert Wollny 
---
  src/gallium/drivers/virgl/virgl_context.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_context.c 
b/src/gallium/drivers/virgl/virgl_context.c
index d985bf906f..f5e3832d99 100644
--- a/src/gallium/drivers/virgl/virgl_context.c
+++ b/src/gallium/drivers/virgl/virgl_context.c
@@ -943,11 +943,11 @@ static void virgl_get_sample_position(struct pipe_context 
*ctx,
return;
 } else if (sample_count == 2) {
bits = vs->caps.caps.v2.msaa_sample_positions[0] >> (8 * index);
-   } else if (sample_count < 4) {
+   } else if (sample_count <= 4) {
bits = vs->caps.caps.v2.msaa_sample_positions[1] >> (8 * index);
-   } else if (sample_count < 8) {
+   } else if (sample_count <= 8) {
bits = vs->caps.caps.v2.msaa_sample_positions[2 + (index >> 2)] >> (8 * 
(index & 3));
-   } else if (sample_count < 8) {
+   } else if (sample_count <= 16) {


This isn't technically speaking an off-by-one... perhaps adjust the 
commit message a bit?



bits = vs->caps.caps.v2.msaa_sample_positions[4 + (index >> 2)] >> (8 * 
(index & 3));
 }
 out_value[0] = ((bits >> 4) & 0xf) / 16.0f;


Reviewed-by: Erik Faye-Lund 
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[Mesa-dev] [PATCH v4 2/4] r600 shader: Add extra function to evaluate array index

[Gert Wollny]

From: Gert Wollny 

The added function evaluates the array index according to the function

idx = floor(ai + 0.5);

Signed-off-by: Gert Wollny 
---
 src/gallium/drivers/r600/r600_shader.c | 34 ++
 1 file changed, 34 insertions(+)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 6655b000aa..e2f44afc05 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -7448,6 +7448,40 @@ static int r600_do_buffer_txq(struct r600_shader_ctx 
*ctx, int reg_idx, int offs
}
 }
 
+/* Evaluate the texture array index according to floor(z+0.5) */
+static int r600_shader_evaluate_array_index(struct r600_bytecode_alu *alu,
+   
  int reg, int chan, int rel,
+   
  struct r600_bytecode *bc)
+{
+   int r;
+
+   /* evaluate array index according to floor(z+0.5) */
+   alu->op = ALU_OP2_ADD;
+   alu->src[1].sel = V_SQ_ALU_SRC_0_5;
+   alu->dst.sel = reg;
+   alu->dst.chan = chan;
+   alu->dst.rel = rel;
+   alu->dst.write = 1;
+   alu->last = 1;
+   r = r600_bytecode_add_alu(bc, alu);
+   if (r)
+   return r;
+
+   memset(alu, 0, sizeof(struct r600_bytecode_alu));
+   alu->op = ALU_OP1_FLOOR;
+   alu->src[0].sel = reg;
+   alu->src[0].chan = chan;
+   alu->src[0].rel = rel;
+   alu->dst.sel = reg;
+   alu->dst.chan = chan;
+   alu->dst.rel = rel;
+   alu->dst.write = 1;
+   alu->last = 1;
+   r = r600_bytecode_add_alu(bc, alu);
+   if (r)
+   return r;
+   return 0;
+}
 
 static int tgsi_tex(struct r600_shader_ctx *ctx)
 {
-- 
2.16.4

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[Mesa-dev] [PATCH v4 4/4] r600: Correct evaluation of cube array index and face

[Gert Wollny]

From: Gert Wollny 

The array index needs to be corrected and it must be insured that its
value is non-negative before it is combined with the face id.

Fixes 182 from android/cts/master/gles31-master.txt:
  dEQP-GLES31.functional.texture.filtering.cube_array.formats.*
  dEQP-GLES31.functional.texture.filtering.cube_array.sizes.*
  
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_mipmap_*
  
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.linear_mipmap_*
  dEQP-GLES31.functional.texture.filtering.cube_array.no_edges_visible.*

Signed-off-by: Gert Wollny 
---
 src/gallium/drivers/r600/r600_shader.c | 29 -
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 6f1e0b34f3..e05a93ca62 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -7754,11 +7754,38 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
if (r)
return r;
 
+   /* Evaluate the array index according to 
floor(idx + 0.5). This
+* needs to be done before merging the face 
select value, because
+* otherwise the fractional part of the array 
index will interfere
+* with the face select value */
+   memset(, 0, sizeof(struct 
r600_bytecode_alu));
+   r600_bytecode_src([0], >src[0], 3);
+   r = r600_shader_evaluate_array_index(, 
ctx->temp_reg, 3, 0, ctx->bc);
+   if (r)
+   return r;
+
+   /* Because the array slice index and the cube 
face index are merged
+* into one value we have to make sure the 
array slice index is >= 0,
+* otherwise the face selection might fail */
+   memset(, 0, sizeof(struct 
r600_bytecode_alu));
+   alu.op = ALU_OP2_MAX;
+   alu.src[0].sel = ctx->temp_reg;
+   alu.src[0].chan = 3;
+   alu.src[1].sel = V_SQ_ALU_SRC_0;
+   alu.dst.sel = ctx->temp_reg;
+   alu.dst.chan = 3;
+   alu.dst.write = 1;
+   alu.last = 1;
+   r = r600_bytecode_add_alu(ctx->bc, );
+   if (r)
+   return r;
+
/* have to multiply original layer by 8 and add 
to face id (temp.w) in Z */
memset(, 0, sizeof(struct 
r600_bytecode_alu));
alu.op = ALU_OP3_MULADD;
alu.is_op3 = 1;
-   r600_bytecode_src([0], >src[0], 3);
+   alu.src[0].sel = ctx->temp_reg;
+   alu.src[0].chan = 3;
alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
alu.src[1].chan = 0;
alu.src[1].value = u_bitcast_f2u(8.0f);
-- 
2.16.4

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[Mesa-dev] [PATCH v4 3/4] r600: correct texture offset for array index lookup

[Gert Wollny]

From: Gert Wollny 

Correct the array index for TEXTURE_*1D_ARRAY, and TEXTURE_*2D_ARRAY

v2: - Don't apply texture offset correction for GATHER*O (corrects piglit
  failures reported by Dave Airlie)
- unconditionally set the texture offset to 1 (=0.5) because the shader
  can't set an offset for the array index (Roland Scheidegger)

v3: - Set texture offset also for GATHER*0 via SET_TEXTURE_OFFSET to be
  consistent for all GATHER operations (thanks Roland Scheidegger for
  pointing out this inconsistency).
- Don't set the offset for GET_TEXTURE_RESINFO operations
- correct typos (Roland)

v4: - evaluate array index relying only on arithmetic used in the shaders
  (Roland pointed out that changing the texture state with respect to 
   rounding might have unwanted effects)
- make use of the newly introduced function for evaluating the index

Fixes 325 tests from android/cts/master/gles3-master.txt:
  dEQP-GLES3.functional.shaders.texture_functions.texture.*sampler2darray*
  dEQP-GLES3.functional.shaders.texture_functions.textureoffset.*sampler2darray*
  dEQP-GLES3.functional.shaders.texture_functions.texturelod.sampler2darray*
  
dEQP-GLES3.functional.shaders.texture_functions.texturelodoffset.*sampler2darray*
  dEQP-GLES3.functional.shaders.texture_functions.texturegrad.*sampler2darray*
  
dEQP-GLES3.functional.shaders.texture_functions.texturegradoffset.*sampler2darray*
  dEQP-GLES3.functional.texture.filtering.2d_array.formats.*
  dEQP-GLES3.functional.texture.filtering.2d_array.sizes.*
  dEQP-GLES3.functional.texture.filtering.2d_array.combinations.*
  dEQP-GLES3.functional.texture.shadow.2d_array.*
  dEQP-GLES3.functional.texture.vertex.2d_array.*

Acked-by: Roland Scheidegger  (v2)
Signed-off-by: Gert Wollny 
---
 src/gallium/drivers/r600/r600_shader.c | 38 +-
 1 file changed, 33 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index e2f44afc05..6f1e0b34f3 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -7512,6 +7512,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
int8_t offset_x = 0, offset_y = 0, offset_z = 0;
boolean has_txq_cube_array_z = false;
unsigned sampler_index_mode;
+   int array_index_offset_channel = -1;
 
if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
@@ -8307,7 +8308,14 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
t->src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + 
inst->TexOffsets[0].Index;
t->src_sel_x = inst->TexOffsets[0].SwizzleX;
t->src_sel_y = inst->TexOffsets[0].SwizzleY;
-   t->src_sel_z = inst->TexOffsets[0].SwizzleZ;
+   if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
+inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)
+   /* make sure array index selector is 0, this is just a 
safety
+* precaution because TGSI seems to emit offset Y also 
for Z */
+   t->src_sel_z = 4;
+   else
+   t->src_sel_z = inst->TexOffsets[0].SwizzleZ;
+
t->src_sel_w = 4;
 
t->dst_sel_x = 7;
@@ -8463,19 +8471,39 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
opcode == FETCH_OP_SAMPLE_C_LB) {
/* the array index is read from Y */
tex.coord_type_y = 0;
+   array_index_offset_channel = tex.src_sel_y;
} else {
/* the array index is read from Z */
tex.coord_type_z = 0;
tex.src_sel_z = tex.src_sel_y;
+   array_index_offset_channel = tex.src_sel_z;
}
} else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
-  inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
-  ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
+   inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY) {
+   tex.coord_type_z = 0;
+   array_index_offset_channel = tex.src_sel_z;
+   } else if  ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
-   (ctx->bc->chip_class >= EVERGREEN)))
-   /* the array index is read from Z */
+   (ctx->bc->chip_class >= EVERGREEN))
+   /* the array index is read from Z, coordinate will be corrected 
elsewhere  */
tex.coord_type_z = 0;
 
+   /* We have array access to 1D or 2D ARRAY, the coordinates are not int 
->
+* evaluate the array index  */
+   if (array_index_offset_channel >= 0 &&

[Mesa-dev] [PATCH v4 1/4] r600: Delay emission of texture gradients and lookup offsets

[Gert Wollny]

From: Gert Wollny 

Gradients used in texture lookups and the offsets must reside in the
same fetch clause (the first is imposed by the hardware and the second
is expected by sb). In order to ensure that no ALU clause is inserted
between emission and use of these, delay the emission of these
instructions until the texture instruction using them is also emitted.

This is needed in preparation for the correction of the texture array
indices.

Signed-off-by: Gert Wollny 
---
 src/gallium/drivers/r600/r600_shader.c | 92 ++
 1 file changed, 48 insertions(+), 44 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 4b91da..6655b000aa 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -7453,9 +7453,10 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 {
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
struct r600_bytecode_tex tex;
+   struct r600_bytecode_tex grad_offs[3];
struct r600_bytecode_alu alu;
unsigned src_gpr;
-   int r, i, j;
+   int r, i, j, n_grad_offs = 0;
int opcode;
bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
inst->Instruction.Opcode == TGSI_OPCODE_TXF 
&&
@@ -7828,31 +7829,29 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
}
for (i = 1; i < 3; i++) {
/* set gradients h/v */
-   memset(, 0, sizeof(struct r600_bytecode_tex));
-   tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
+   struct r600_bytecode_tex *t = _offs[n_grad_offs++];
+   memset(t, 0, sizeof(struct r600_bytecode_tex));
+   t->op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
FETCH_OP_SET_GRADIENTS_V;
-   tex.sampler_id = tgsi_tex_get_src_gpr(ctx, 
sampler_src_reg);
-   tex.sampler_index_mode = sampler_index_mode;
-   tex.resource_id = tex.sampler_id + 
R600_MAX_CONST_BUFFERS;
-   tex.resource_index_mode = sampler_index_mode;
-
-   tex.src_gpr = (i == 1) ? temp_h : temp_v;
-   tex.src_sel_x = 0;
-   tex.src_sel_y = 1;
-   tex.src_sel_z = 2;
-   tex.src_sel_w = 3;
-
-   tex.dst_gpr = r600_get_temp(ctx); /* just to avoid 
confusing the asm scheduler */
-   tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = 
tex.dst_sel_w = 7;
+   t->sampler_id = tgsi_tex_get_src_gpr(ctx, 
sampler_src_reg);
+   t->sampler_index_mode = sampler_index_mode;
+   t->resource_id = t->sampler_id + R600_MAX_CONST_BUFFERS;
+   t->resource_index_mode = sampler_index_mode;
+
+   t->src_gpr = (i == 1) ? temp_h : temp_v;
+   t->src_sel_x = 0;
+   t->src_sel_y = 1;
+   t->src_sel_z = 2;
+   t->src_sel_w = 3;
+
+   t->dst_gpr = r600_get_temp(ctx); /* just to avoid 
confusing the asm scheduler */
+   t->dst_sel_x = t->dst_sel_y = t->dst_sel_z = 
t->dst_sel_w = 7;
if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
-   tex.coord_type_x = 1;
-   tex.coord_type_y = 1;
-   tex.coord_type_z = 1;
-   tex.coord_type_w = 1;
+   t->coord_type_x = 1;
+   t->coord_type_y = 1;
+   t->coord_type_z = 1;
+   t->coord_type_w = 1;
}
-   r = r600_bytecode_add_tex(ctx->bc, );
-   if (r)
-   return r;
}
}
 
@@ -8257,32 +8256,30 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
if (opcode == FETCH_OP_GATHER4 &&
inst->TexOffsets[0].File != TGSI_FILE_NULL &&
inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
+   struct r600_bytecode_tex *t;
opcode = FETCH_OP_GATHER4_O;
 
/* GATHER4_O/GATHER4_C_O use offset values loaded by
   SET_TEXTURE_OFFSETS instruction. The immediate offset values
   encoded in the instruction are ignored. */
-   memset(, 0, sizeof(struct r600_bytecode_tex));
-   tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
-   tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
-   tex.sampler_index_mode = sampler_index_mode;
-   tex.resource_id = 

[Mesa-dev] [PATCH v4 0/4] r600: Fix array texture slice index evaluation

[Gert Wollny]

From: Gert Wollny 

Hello Roland, Dave, and everybody else, 

this is a 90% rewrite of the earlier series. 

- I removed the changes to the texture state and handle everything in the 
  shader. Since this was needed for cube arrays anyway, and also taking Rolands
  concern into account I thought it is best to do this for the other arrays as 
  well.
- I've identified to the root cause why sb was having problems with the
  GATHER_O instruction, and reworked the code to make sure that the related
  texture instructions are all emitted in one CF clause, This is also required
  for the SET_GRADIENT instructions. 
- I've also correct the array index for cube textures now.

I didn't see any changes with 

  piglit run gpu -t texture -t gather -t formats

Many thanks for reviewing, 
Gert 

Gert Wollny (4):
  r600: Delay emission of texture gradients and lookup offsets
  r600: Add extra function to evaluate array index
  r600: correct texture offset for array index lookup
  r600: Correct evaluation of cube array index and face

 src/gallium/drivers/r600/r600_shader.c | 187 -
 1 file changed, 140 insertions(+), 47 deletions(-)

-- 
2.16.4

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[Mesa-dev] [PATCH] gallium/winsys/kms: do not munmap NULL pointers

[Jan Palus]

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107098
Signed-off-by: Jan Palus 
---
 src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c 
b/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
index 3fe1b1a731..7aa86df0af 100644
--- a/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
+++ b/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
@@ -368,10 +368,14 @@ kms_sw_displaytarget_unmap(struct sw_winsys *ws,
DEBUG_PRINT("KMS-DEBUG: unmapped buffer %u (was %p)\n", kms_sw_dt->handle, 
kms_sw_dt->mapped);
DEBUG_PRINT("KMS-DEBUG: unmapped buffer %u (was %p)\n", kms_sw_dt->handle, 
kms_sw_dt->ro_mapped);
 
-   munmap(kms_sw_dt->mapped, kms_sw_dt->size);
-   kms_sw_dt->mapped = NULL;
-   munmap(kms_sw_dt->ro_mapped, kms_sw_dt->size);
-   kms_sw_dt->ro_mapped = NULL;
+   if (kms_sw_dt->mapped != NULL) {
+  munmap(kms_sw_dt->mapped, kms_sw_dt->size);
+  kms_sw_dt->mapped = NULL;
+   }
+   if (kms_sw_dt->ro_mapped != NULL) {
+  munmap(kms_sw_dt->ro_mapped, kms_sw_dt->size);
+  kms_sw_dt->ro_mapped = NULL;
+   }
 }
 
 static struct sw_displaytarget *
-- 
2.18.0

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[Mesa-dev] failed VCE resume (-110).

[xzj8b3]

[   29.524770] radeon :04:00.0: WB enabled
[   29.524773] radeon :04:00.0: fence driver on ring 0 use gpu addr
0x8c00 and cpu addr 0x5bfa1c58
[   29.524774] radeon :04:00.0: fence driver on ring 1 use gpu addr
0x8c04 and cpu addr 0xabfa2b51
[   29.524775] radeon :04:00.0: fence driver on ring 2 use gpu addr
0x8c08 and cpu addr 0x9f781d34
[   29.524777] radeon :04:00.0: fence driver on ring 3 use gpu addr
0x8c0c and cpu addr 0xae77ed65
[   29.524778] radeon :04:00.0: fence driver on ring 4 use gpu addr
0x8c10 and cpu addr 0xb585a9db
[   29.525581] radeon :04:00.0: fence driver on ring 5 use gpu addr
0x00075a18 and cpu addr 0x84142428
[   29.626840] radeon :04:00.0: failed VCE resume (-110).


But don't you can resolve this issue by deleting the alarm signalling every
time???


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Re: [Mesa-dev] [PATCH 1/4] nir: add inot algebraic opt

[Matt Turner]

On Sun, Jul 15, 2018 at 7:26 PM, Timothy Arceri  wrote:
> Noticed in a unigine shader.
> ---
>  src/compiler/nir/nir_opt_algebraic.py | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/src/compiler/nir/nir_opt_algebraic.py 
> b/src/compiler/nir/nir_opt_algebraic.py
> index 5e07d662b07..0986dde6851 100644
> --- a/src/compiler/nir/nir_opt_algebraic.py
> +++ b/src/compiler/nir/nir_opt_algebraic.py
> @@ -223,6 +223,7 @@ optimizations = [
> (('bcsel', ('inot', a), b, c), ('bcsel', a, c, b)),
> (('bcsel', a, ('bcsel', a, b, c), d), ('bcsel', a, b, d)),
> (('bcsel', a, True, 'b@bool'), ('ior', a, b)),
> +   (('inot', ('bcsel', a, ('inot', b), c)), ('bcsel', a, b, ('inot', c))),

Shouldn't we have an equivalent rule for the other argument, like

+   (('inot', ('bcsel', a, b, ('inot', c))), ('bcsel', a, ('inot', b), c)),

I assume we would not benefit from a general rule that simply
propagates inot inside to both b and c unconditionally.
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Re: [Mesa-dev] [PATCH v2] intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY.

[Sergii Romantsov]

Hello, Kenneth.
Any more remarks?

On Thu, Jul 12, 2018 at 3:47 PM, Sergii Romantsov <
sergii.romant...@gmail.com> wrote:

> SNB doesn't have a definition of 3DSTATE_CONSTANT_BODY, thats
> why we got segmentation fault when used INTEL_DEBUG=bat.
> Fixed by adding of 3DSTATE_CONSTANT_BODY into 3DSTATE_CONSTANT
> of VS, GS and PS structures.
>
> v2: added definition of 3DSTATE_CONSTANT_BODY to the gen6.xml
>
> Fixes: 169d8e011ae (intel: Fix 3DSTATE_CONSTANT buffer decoding.)
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107190
> Signed-off-by: Sergii Romantsov 
> ---
>  src/intel/genxml/gen6.xml | 38
> ++-
>  src/mesa/drivers/dri/i965/genX_state_upload.c | 12 -
>  2 files changed, 20 insertions(+), 30 deletions(-)
>
> diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
> index c2967cd..62d2574 100644
> --- a/src/intel/genxml/gen6.xml
> +++ b/src/intel/genxml/gen6.xml
> @@ -622,6 +622,17 @@
>  
>
>
> +  
> + type="offset"/>
> + type="uint"/>
> + type="address"/>
> + type="uint"/>
> + type="address"/>
> + type="uint"/>
> + type="address"/>
> + type="uint"/>
> +  
> +
>
>   default="3"/>
>   default="3"/>
> @@ -633,14 +644,7 @@
>  
>   type="MEMORY_OBJECT_CONTROL_STATE"/>
>  
> - type="offset"/>
> - type="uint"/>
> - type="address"/>
> - type="uint"/>
> - type="address"/>
> - type="uint"/>
> - type="address"/>
> - type="uint"/>
> + type="3DSTATE_CONSTANT_BODY"/>
>
>
>
> @@ -654,14 +658,7 @@
>  
>   type="MEMORY_OBJECT_CONTROL_STATE"/>
>  
> - type="offset"/>
> - type="uint"/>
> - type="address"/>
> - type="uint"/>
> - type="address"/>
> - type="uint"/>
> - type="address"/>
> - type="uint"/>
> + type="3DSTATE_CONSTANT_BODY"/>
>
>
>
> @@ -675,14 +672,7 @@
>  
>   type="MEMORY_OBJECT_CONTROL_STATE"/>
>  
> - type="offset"/>
> - type="uint"/>
> - type="address"/>
> - type="uint"/>
> - type="address"/>
> - type="uint"/>
> - type="address"/>
> - type="uint"/>
> + type="3DSTATE_CONSTANT_BODY"/>
>
>
>
> diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
> b/src/mesa/drivers/dri/i965/genX_state_upload.c
> index 7fe1288..a4e395c 100644
> --- a/src/mesa/drivers/dri/i965/genX_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
> @@ -1879,8 +1879,8 @@ genX(upload_wm)(struct brw_context *brw)
>   /* Pointer to the WM constant buffer.  Covered by the set of
>* state flags from gen6_upload_wm_push_constants.
>*/
> - wmcp.PointertoPSConstantBuffer0 = stage_state->push_const_
> offset;
> - wmcp.PSConstantBuffer0ReadLength = stage_state->push_const_size
> - 1;
> + wmcp.ConstantBody.PointertoConstantBuffer0 =
> stage_state->push_const_offset;
> + wmcp.ConstantBody.ConstantBuffer0ReadLength =
> stage_state->push_const_size - 1;
>}
> }
>  #endif
> @@ -2215,8 +2215,8 @@ genX(upload_vs_state)(struct brw_context *brw)
> brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_VS), cvs) {
>if (stage_state->push_const_size != 0) {
>   cvs.Buffer0Valid = true;
> - cvs.PointertoVSConstantBuffer0 = stage_state->push_const_offset;
> - cvs.VSConstantBuffer0ReadLength = stage_state->push_const_size
> - 1;
> + cvs.ConstantBody.PointertoConstantBuffer0 =
> stage_state->push_const_offset;
> + cvs.ConstantBody.ConstantBuffer0ReadLength =
> stage_state->push_const_size - 1;
>}
> }
>  #endif
> @@ -2707,8 +2707,8 @@ genX(upload_gs_state)(struct brw_context *brw)
> brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_GS), cgs) {
>if (active && stage_state->push_const_size != 0) {
>   cgs.Buffer0Valid = true;
> - cgs.PointertoGSConstantBuffer0 = stage_state->push_const_offset;
> - cgs.GSConstantBuffer0ReadLength = stage_state->push_const_size
> - 1;
> + cgs.ConstantBody.PointertoConstantBuffer0 =
> stage_state->push_const_offset;
> + cgs.ConstantBody.ConstantBuffer0ReadLength =
> stage_state->push_const_size - 1;
>}
> }
>  #endif
> --
> 2.7.4
>
>
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Re: [Mesa-dev] [PATCH v5 00/21] Introducing SPIR-V support to clover

[Karol Herbst]

the second patch also lacks review: "clover: update ICD table to
support everything up to 2.2"

On Sun, Jul 15, 2018 at 9:26 PM, Pierre Moreau  wrote:
> Hello,
>
> I would appreciate if the following patches could be reviewed:
> * Patch 07 (latest: v6): clover/api: Rework the validation of devices for 
> building;
>   @Francisco: I made the modifications you asked for, but I am not sure 
> whether
>   the “LGTM” should be translated as an Ack or a Rb.
> * Patch 14 (latest: v7): clover/llvm: Allow translating from SPIR-V to LLVM IR
> * Patch 16 (latest: v8): clover/spirv: Add functions for validating SPIR-V 
> binaries
> * Patch 17 (latest: v5): clover: Implement clCreateProgramWithILKHR;
>
> The latest version of the whole series can be found at
> https://github.com/pierremoreau/mesa/commits/clover_spirv_series_v8
>
> Thank you in advance,
> Pierre
>
>
> On 2018-05-23 — 23:58, Pierre Moreau wrote:
>> Hello everyone,
>>
>> I updated a few patches of the series to have it use the new official
>> SPIR-V <-> LLVM translator, that can be found at
>> https://github.com/KhronosGroup/SPIRV-LLVM-Translator.
>>
>> The whole series, rebased on the current Mesa HEAD, can be found at
>> https://github.com/pierremoreau/mesa/tree/clover_spirv_series_v7.
>>
>> A few patches are still missing reviews:
>> * Patch 07: clover/api: Rework the validation of devices for building;
>>   @Francisco: I made the modifications you asked for, but I am not sure 
>> whether
>>   the “LGTM” should be translated as an Ack or an Rb.
>> * Patch 17: clover: Implement clCreateProgramWithILKHR;
>> * and the three patches I just resent as v7.
>>
>> Thank you.
>>
>> Pierre
>>
>> On 2018-03-25 — 20:02, Pierre Moreau wrote:
>> > Hello,
>> >
>> > This has only minor changes compared to the previous version, but as it
>> > introduces a new patch, I preferred to resend the whole series, as patch
>> > numbering would be messed up otherwise.
>> >
>> > As is_valid_spirv will be also used by the SPIR-V backend, I moved that
>> > function away from api/program.cpp and into spirv/invocation.cpp, to avoid
>> > introducing it in one place in this series, and moving it around in the 
>> > next
>> > series.
>> >
>> > The current repository for llvm-spirv is temporary, and should be replaced 
>> > by
>> > an official one during next week. I’ll send an update to patch 13 when that
>> > happens.
>> >
>> > The series is accessible at
>> > https://github.com/pierremoreau/mesa/tree/clover_spirv_series_v5.
>> >
>> > Thanks in advance for the reviews and comments.
>> > Pierre
>> >
>> >
>> > v5:
>> > * Update patch 02 to return the proper type for
>> >   clCreateCommandQueueWithProperties;
>> > * Add a comment in patch 13 to indicate where to find llvm-spirv;
>> > * Move the is_spirv_valid function to spirv/invocation.cpp and improve it 
>> > to
>> >   take an OpenCL version as argument, which is used to configure the SPIR-V
>> >   validator, instead of hardcoding OpenCL 1.2: new patch 16;
>> > * Edit patch 17 to use SPIR-V functions from the backend.
>> >
>> > Missing reviews/acks for:
>> > * Patch 07: “clover/api: Rework the validation of devices for building”;
>> > * Patch 14: “clover/llvm: Allow translating from SPIR-V to LLVM IR”;
>> > * Patch 18: “clover: Handle CL_PROGRAM_IL in clGetProgramInfo”
>> >
>> >
>> > Karol Herbst (1):
>> >   clover: update ICD table to support everything up to 2.2
>> >
>> > Pierre Moreau (20):
>> >   include/CL: Update to the latest OpenCL 2.2 headers
>> >   clover/api: Fix tab indentation to spaces
>> >   clover: Remove the TGSI backend as unused
>> >   clover: Add an helper for checking if an IR is supported
>> >   clover/device: Replace usage of "1 << PIPE_SHADER_IR_*" with
>> > supports_ir
>> >   clover/api: Rework the validation of devices for building
>> >   clover/api: Fail if trying to build a non-executable binary
>> >   clover: Disallow creating libraries from other libraries
>> >   clover: Track flags per module section
>> >   clover: Move device extensions definitions to core/device.cpp
>> >   clover: Move platform extensions definitions to clover/platform.cpp
>> >   configure.ac,meson: Check for SPIRV-Tools and llvm-spirv
>> >   clover/llvm: Allow translating from SPIR-V to LLVM IR
>> >   include/CL: Add cl_khr_il_program
>> >   clover/spirv: Add functions for validating SPIR-V binaries
>> >   clover: Implement clCreateProgramWithILKHR
>> >   clover: Handle CL_PROGRAM_IL in clGetProgramInfo
>> >   clover/api: Implement CL_DEVICE_IL_VERSION
>> >   clover: Advertise cl_khr_il_program
>> >   clover: Implement clCreateProgramWithIL from OpenCL 2.1
>> >
>> >  configure.ac   |   18 +
>> >  include/CL/cl.h|  472 +++--
>> >  include/CL/cl_d3d10.h  |7 +-
>> >  include/CL/cl_d3d11.h  |7 +-
>> >  include/CL/cl_dx9_media_sharing.h  |9 +-
>> >