Re: [Mesa-dev] [PATCH v2] nir: fix nir_copy_propagation test
On Tue, Oct 23, 2018 at 7:56 AM Juan A. Suarez Romero
wrote:
>
> Use nir_src_comp_as_uint() to read the proper second component, as
> nir_src_as_uint() returns the first one.
>
> v2: Use nir_src_comp_as_uint() [Jason]
>
> Fixes: 16870de8a0a ("nir: Use nir_src_is_const and nir_src_as_* in core
> code")
> Signed-off-by: Juan A. Suarez Romero
> ---
> src/compiler/nir/tests/vars_tests.cpp | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/compiler/nir/tests/vars_tests.cpp
> b/src/compiler/nir/tests/vars_tests.cpp
> index 02c53804b84..a7bbeb02277 100644
> --- a/src/compiler/nir/tests/vars_tests.cpp
> +++ b/src/compiler/nir/tests/vars_tests.cpp
> @@ -375,7 +375,7 @@ TEST_F(nir_copy_prop_vars_test,
> store_store_load_different_components)
> ASSERT_TRUE(store_to_v1->src[1].is_ssa);
>
> ASSERT_TRUE(nir_src_is_const(store_to_v1->src[1]));
> - ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 20);
> + ASSERT_EQ(nir_src_comp_as_uint(store_to_v1->src[1], 1), 20);
> break;
>}
> }
> @@ -424,7 +424,7 @@ TEST_F(nir_copy_prop_vars_test,
> store_store_load_different_components_in_many_bl
> ASSERT_TRUE(store_to_v1->src[1].is_ssa);
>
> ASSERT_TRUE(nir_src_is_const(store_to_v1->src[1]));
> - ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 20);
> + ASSERT_EQ(nir_src_comp_as_uint(store_to_v1->src[1], 1), 20);
> break;
>}
> }
> --
> 2.17.2
>
> ___
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Tested-by: Vinson Lee
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[Mesa-dev] [Bug 108530] [Tracker] Mesa 18.3 Release Tracker
https://bugs.freedesktop.org/show_bug.cgi?id=108530 Vinson Lee changed: What|Removed |Added Depends on||108532 Referenced Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=108532 [Bug 108532] make check nir_copy_prop_vars_test.store_store_load_different_components regression -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 108532] make check nir_copy_prop_vars_test.store_store_load_different_components regression
https://bugs.freedesktop.org/show_bug.cgi?id=108532 Vinson Lee changed: What|Removed |Added Blocks||108530 Referenced Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=108530 [Bug 108530] [Tracker] Mesa 18.3 Release Tracker -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 108530] [Tracker] Mesa 18.3 Release Tracker
https://bugs.freedesktop.org/show_bug.cgi?id=108530 Vinson Lee changed: What|Removed |Added Depends on||108082 Referenced Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=108082 [Bug 108082] warning: unknown warning option '-Wno-format-truncation' [-Wunknown-warning-option] -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 108082] warning: unknown warning option '-Wno-format-truncation' [-Wunknown-warning-option]
https://bugs.freedesktop.org/show_bug.cgi?id=108082 Vinson Lee changed: What|Removed |Added Blocks||108530 Referenced Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=108530 [Bug 108530] [Tracker] Mesa 18.3 Release Tracker -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 106881] glUniform4fv does not work
https://bugs.freedesktop.org/show_bug.cgi?id=106881 --- Comment #8 from Yang Gu --- Yang is OOO from Oct 15 to 26 for vacation and TPAC 2018. Please expect slow response. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 106810] ProgramBinary does not switch program correctly when using transform feedback
https://bugs.freedesktop.org/show_bug.cgi?id=106810 --- Comment #6 from Tapani Pälli --- *** Bug 106881 has been marked as a duplicate of this bug. *** -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 106881] glUniform4fv does not work
https://bugs.freedesktop.org/show_bug.cgi?id=106881 Tapani Pälli changed: What|Removed |Added Resolution|FIXED |DUPLICATE --- Comment #7 from Tapani Pälli --- (was duplicate) *** This bug has been marked as a duplicate of bug 106810 *** -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/4] meson: fix formatting and add extra_files to i965
Reviewed-by: Tapani Pälli On 10/24/18 1:56 AM, Dylan Baker wrote: extra_files is just a nice way to to tell certain IDE's (and those reading the file) that this file is also a dependency. Meson will use the .d file generated by the compiler to figure out what the target actually depends on. --- src/mesa/drivers/dri/i965/meson.build | 22 -- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/src/mesa/drivers/dri/i965/meson.build b/src/mesa/drivers/dri/i965/meson.build index bf366a6c157..24172955e9b 100644 --- a/src/mesa/drivers/dri/i965/meson.build +++ b/src/mesa/drivers/dri/i965/meson.build @@ -191,20 +191,22 @@ intel_tiled_memcpy = static_library( inc_common, inc_intel, inc_dri_common, inc_drm_uapi, ], c_args : [c_vis_args, no_override_init_args, '-msse2'], + extra_files : ['intel_tiled_memcpy.c'] ) if with_sse41 -intel_tiled_memcpy_sse41 = static_library( - 'intel_tiled_memcpy_sse41', - [files_intel_tiled_memcpy_sse41], - include_directories : [ -inc_common, inc_intel, inc_dri_common, inc_drm_uapi, - ], - link_args : [ '-Wl,--exclude-libs=ALL' ], - c_args : [c_vis_args, no_override_init_args, '-Wl,--exclude-libs=ALL', '-msse2', sse41_args], -) + intel_tiled_memcpy_sse41 = static_library( +'intel_tiled_memcpy_sse41', +[files_intel_tiled_memcpy_sse41], +include_directories : [ + inc_common, inc_intel, inc_dri_common, inc_drm_uapi, +], +link_args : ['-Wl,--exclude-libs=ALL'], +c_args : [c_vis_args, no_override_init_args, '-Wl,--exclude-libs=ALL', '-msse2', sse41_args], +extra_files : ['intel_tiled_memcpy.c'] + ) else -intel_tiled_memcpy_sse41 = [] + intel_tiled_memcpy_sse41 = [] endif ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 4/4] autotools: include intel_tiled_memcopy.c
Thanks for fixing these issues;
Reviewed-by: Tapani Pälli
On 10/24/18 1:56 AM, Dylan Baker wrote:
There are two problems with the fixed patch. First, it fails to create a
dependency on the sourced .c file, so changes to intel_tiled_memcpy.c
won't trigger a rebuild. It also doesn't get included in the dist
tarball.
CC: Tapani Pälli
Fixes: 11b1afdc92db98e93f2ca50beeb7fc481a11e708
("i965/tiled_memcpy: inline movntdqa loads in tiled_to_linear")
---
src/mesa/drivers/dri/i965/Makefile.am | 4
src/mesa/drivers/dri/i965/Makefile.sources | 3 +++
2 files changed, 7 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/Makefile.am
b/src/mesa/drivers/dri/i965/Makefile.am
index dc19da2c4a6..fda17589cfb 100644
--- a/src/mesa/drivers/dri/i965/Makefile.am
+++ b/src/mesa/drivers/dri/i965/Makefile.am
@@ -126,6 +126,7 @@ CLEANFILES = $(BUILT_SOURCES)
EXTRA_DIST = \
brw_oa.py \
$(i965_oa_xml_FILES) \
+ $(intel_tiled_memcpy_dep_FILES) \
meson.build
brw_oa_metrics.c: brw_oa.py $(i965_oa_xml_FILES)
@@ -135,3 +136,6 @@ brw_oa_metrics.c: brw_oa.py $(i965_oa_xml_FILES)
$(i965_oa_xml_FILES:%=$(srcdir)/%)
brw_oa_metrics.h: brw_oa_metrics.c
+
+intel_tiled_memcpy_normal.c: $(intel_tiled_memcpy_dep_FILES)
+intel_tiled_memcpy_sse41.c: $(intel_tiled_memcpy_dep_FILES)
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
b/src/mesa/drivers/dri/i965/Makefile.sources
index 0ab0e42fb18..043a70029f2 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -121,6 +121,9 @@ intel_tiled_memcpy_sse41_FILES = \
intel_tiled_memcpy_sse41.c \
intel_tiled_memcpy_sse41.h
+intel_tiled_memcpy_dep_FILES = \
+ intel_tiled_memcpy.c
+
i965_gen4_FILES = \
genX_blorp_exec.c \
genX_state_upload.c
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Re: [Mesa-dev] [PATCH v2] nir: fix nir_copy_propagation test
Please CC and close https://bugs.freedesktop.org/show_bug.cgi?id=108532
when you push this.
--Jason
On Tue, Oct 23, 2018 at 12:12 PM Jason Ekstrand
wrote:
> Reviewed-by: Jason Ekstrand
>
> On Tue, Oct 23, 2018 at 9:55 AM Juan A. Suarez Romero
> wrote:
>
>> Use nir_src_comp_as_uint() to read the proper second component, as
>> nir_src_as_uint() returns the first one.
>>
>> v2: Use nir_src_comp_as_uint() [Jason]
>>
>> Fixes: 16870de8a0a ("nir: Use nir_src_is_const and nir_src_as_* in core
>> code")
>> Signed-off-by: Juan A. Suarez Romero
>> ---
>> src/compiler/nir/tests/vars_tests.cpp | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/src/compiler/nir/tests/vars_tests.cpp
>> b/src/compiler/nir/tests/vars_tests.cpp
>> index 02c53804b84..a7bbeb02277 100644
>> --- a/src/compiler/nir/tests/vars_tests.cpp
>> +++ b/src/compiler/nir/tests/vars_tests.cpp
>> @@ -375,7 +375,7 @@ TEST_F(nir_copy_prop_vars_test,
>> store_store_load_different_components)
>> ASSERT_TRUE(store_to_v1->src[1].is_ssa);
>>
>> ASSERT_TRUE(nir_src_is_const(store_to_v1->src[1]));
>> - ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 20);
>> + ASSERT_EQ(nir_src_comp_as_uint(store_to_v1->src[1], 1), 20);
>> break;
>>}
>> }
>> @@ -424,7 +424,7 @@ TEST_F(nir_copy_prop_vars_test,
>> store_store_load_different_components_in_many_bl
>> ASSERT_TRUE(store_to_v1->src[1].is_ssa);
>>
>> ASSERT_TRUE(nir_src_is_const(store_to_v1->src[1]));
>> - ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 20);
>> + ASSERT_EQ(nir_src_comp_as_uint(store_to_v1->src[1], 1), 20);
>> break;
>>}
>> }
>> --
>> 2.17.2
>>
>>
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Re: [Mesa-dev] EXT_gpu_shader4 / GL_EXT_gpu_shader4.mbox
Hello Marek, better late then... Tested-by: Dieter Nützel Merged it into current git (0ff1ccca25). Do you need any special tests? Dieter Am 08.09.2018 00:06, schrieb Marek Olšák: Hi Dieter, Here: https://cgit.freedesktop.org/~mareko/mesa/log/?h=ext_gpu_shader4 Marek On Tue, Sep 4, 2018 at 8:43 PM, Dieter Nützel wrote: Hello Marek, what about GL_EXT_gpu_shader4.mbox and mesa-only-allow-EXT_gpu_shader4-in-the-compatibility-profile.mbox 2cond gallium-split-depth_clip-into-depth_clip_near-depth_clip_far.mbox didn't apply any longer, but I've tested it before latest commits, so tb for that, from me. Thanks, Dieter ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] freedreno: use fd_bc_alloc_batch instead of fd_batch_create.
Following the commit 2385d7b066 and 8e798e28f7, for resource dependancy
tracking.
Fixes:
dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_depth_fbo
with FD_MESA_DEBUG=inorder
---
src/gallium/drivers/freedreno/a5xx/fd5_blitter.c | 2 +-
src/gallium/drivers/freedreno/freedreno_batch.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_blitter.c
b/src/gallium/drivers/freedreno/a5xx/fd5_blitter.c
index 6e8177d344..09ff2b71ec 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_blitter.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_blitter.c
@@ -459,7 +459,7 @@ fd5_blitter_blit(struct fd_context *ctx, const struct
pipe_blit_info *info)
return;
}
- batch = fd_batch_create(ctx, true);
+ batch = fd_bc_alloc_batch(>screen->batch_cache, ctx, true);
fd5_emit_restore(batch, batch->draw);
fd5_emit_lrz_flush(batch->draw);
diff --git a/src/gallium/drivers/freedreno/freedreno_batch.c
b/src/gallium/drivers/freedreno/freedreno_batch.c
index 487176cc63..c83466d176 100644
--- a/src/gallium/drivers/freedreno/freedreno_batch.c
+++ b/src/gallium/drivers/freedreno/freedreno_batch.c
@@ -360,7 +360,7 @@ fd_batch_flush(struct fd_batch *batch, bool sync, bool
force)
*/
new_batch = NULL;
} else {
- new_batch = fd_batch_create(ctx, false);
+ new_batch =
fd_bc_alloc_batch(>screen->batch_cache, ctx, false);
util_copy_framebuffer_state(_batch->framebuffer,
>framebuffer);
}
--
2.17.1
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[Mesa-dev] [PATCH 2/2] freedreno: ir3: fix wrong return if reg is an array
Since ir3_register struct has union, it could return true even
if it's an array register accidentally when checking whether it
is address/predicate register.
Fixes: dEQP-GLES31.functional.ssbo.layout.random.arrays_of_arrays.6
---
src/gallium/drivers/freedreno/ir3/ir3.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/freedreno/ir3/ir3.h
b/src/gallium/drivers/freedreno/ir3/ir3.h
index 3055c10f1d..db94603558 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3.h
@@ -739,7 +739,7 @@ static inline bool writes_addr(struct ir3_instruction
*instr)
{
if (instr->regs_count > 0) {
struct ir3_register *dst = instr->regs[0];
- return reg_num(dst) == REG_A0;
+ return (reg_num(dst) == REG_A0) && !(dst->flags &
IR3_REG_ARRAY);
}
return false;
}
@@ -748,7 +748,7 @@ static inline bool writes_pred(struct ir3_instruction
*instr)
{
if (instr->regs_count > 0) {
struct ir3_register *dst = instr->regs[0];
- return reg_num(dst) == REG_P0;
+ return (reg_num(dst) == REG_P0) && !(dst->flags &
IR3_REG_ARRAY);
}
return false;
}
--
2.17.1
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[Mesa-dev] [Bug 108532] make check nir_copy_prop_vars_test.store_store_load_different_components regression
https://bugs.freedesktop.org/show_bug.cgi?id=108532 Vinson Lee changed: What|Removed |Added Keywords||bisected CC||b...@basnieuwenhuizen.nl, ||ja...@jlekstrand.net --- Comment #1 from Vinson Lee --- 16870de8a0aab97bd3534b660e7ea73e90ac11cd is the first bad commit commit 16870de8a0aab97bd3534b660e7ea73e90ac11cd Author: Jason Ekstrand Date: Sat Oct 20 09:10:02 2018 -0500 nir: Use nir_src_is_const and nir_src_as_* in core code Reviewed-by: Bas Nieuwenhuizen :04 04 fbda312921231321d5edc1cce5285591f9091f1f ec69c85ecdeccbd82fabcd7b14da602a4bdb69a7 M src -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/1] util: Change remaining uint32 cache ids to sha1
After discussion with Timothy Arceri. disk_cache_get_function_identifier
was using only the first byte of the sha1 build-id. Replace
disk_cache_get_function_identifier with implementation from
radv_get_build_id. Instead of writing a uint32_t it now writes to a
mesa_sha1. All drivers using disk_cache_get_function_identifier are
updated accordingly.
Reviewed-by: Timothy Arceri
Fixes: 83ea8dd99bb1 ("util: add disk_cache_get_function_identifier()")
---
src/amd/vulkan/radv_device.c | 22 +--
src/gallium/drivers/nouveau/nouveau_screen.c | 29 -
src/gallium/drivers/r600/r600_pipe_common.c | 43 ++---
src/gallium/drivers/radeonsi/si_pipe.c | 64 ++--
src/util/disk_cache.h| 16 +++--
5 files changed, 81 insertions(+), 93 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index cf1132098d..81b558b91c 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -49,24 +49,6 @@
#include "util/debug.h"
#include "util/mesa-sha1.h"
-static bool
-radv_get_build_id(void *ptr, struct mesa_sha1 *ctx)
-{
- uint32_t timestamp;
-
-#ifdef HAVE_DL_ITERATE_PHDR
- const struct build_id_note *note = NULL;
- if ((note = build_id_find_nhdr_for_addr(ptr))) {
- _mesa_sha1_update(ctx, build_id_data(note),
build_id_length(note));
- } else
-#endif
- if (disk_cache_get_function_timestamp(ptr, )) {
- _mesa_sha1_update(ctx, , sizeof(timestamp));
- } else
- return false;
- return true;
-}
-
static int
radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
{
@@ -77,8 +59,8 @@ radv_device_get_cache_uuid(enum radeon_family family, void
*uuid)
memset(uuid, 0, VK_UUID_SIZE);
_mesa_sha1_init();
- if (!radv_get_build_id(radv_device_get_cache_uuid, ) ||
- !radv_get_build_id(LLVMInitializeAMDGPUTargetInfo, ))
+ if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid,
) ||
+ !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
))
return -1;
_mesa_sha1_update(, , sizeof(family));
diff --git a/src/gallium/drivers/nouveau/nouveau_screen.c
b/src/gallium/drivers/nouveau/nouveau_screen.c
index eb184d3559..d7898ed58f 100644
--- a/src/gallium/drivers/nouveau/nouveau_screen.c
+++ b/src/gallium/drivers/nouveau/nouveau_screen.c
@@ -148,20 +148,21 @@ nouveau_screen_bo_get_handle(struct pipe_screen *pscreen,
static void
nouveau_disk_cache_create(struct nouveau_screen *screen)
{
- uint32_t mesa_id;
- char *mesa_id_str;
- int res;
-
- if (disk_cache_get_function_identifier(nouveau_disk_cache_create,
- _id)) {
- res = asprintf(_id_str, "%u", mesa_id);
- if (res != -1) {
- screen->disk_shader_cache =
-disk_cache_create(nouveau_screen_get_name(>base),
- mesa_id_str, 0);
- free(mesa_id_str);
- }
- }
+ struct mesa_sha1 ctx;
+ unsigned char sha1[20];
+ char cache_id[20 * 2 + 1];
+
+ _mesa_sha1_init();
+ if (!disk_cache_get_function_identifier(nouveau_disk_cache_create,
+ ))
+ return;
+
+ _mesa_sha1_final(, sha1);
+ disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
+
+ screen->disk_shader_cache =
+ disk_cache_create(nouveau_screen_get_name(>base),
+cache_id, 0);
}
int
diff --git a/src/gallium/drivers/r600/r600_pipe_common.c
b/src/gallium/drivers/r600/r600_pipe_common.c
index 6b581242a1..e7c645611d 100644
--- a/src/gallium/drivers/r600/r600_pipe_common.c
+++ b/src/gallium/drivers/r600/r600_pipe_common.c
@@ -854,27 +854,28 @@ static void r600_disk_cache_create(struct
r600_common_screen *rscreen)
if (rscreen->debug_flags & DBG_ALL_SHADERS)
return;
- uint32_t mesa_id;
- if (disk_cache_get_function_identifier(r600_disk_cache_create,
- _id)) {
- char *mesa_id_str;
- int res = -1;
-
- res = asprintf(_id_str, "%u", mesa_id);
- if (res != -1) {
- /* These flags affect shader compilation. */
- uint64_t shader_debug_flags =
- rscreen->debug_flags &
- (DBG_FS_CORRECT_DERIVS_AFTER_KILL |
-DBG_UNSAFE_MATH);
-
- rscreen->disk_shader_cache =
- disk_cache_create(r600_get_family_name(rscreen),
- mesa_id_str,
- shader_debug_flags);
- free(mesa_id_str);
- }
- }
+ struct mesa_sha1 ctx;
+ unsigned char sha1[20];
+ char cache_id[20 * 2 + 1];
+
+
[Mesa-dev] [PATCH 0/1] util: Change remaining uint32 cache ids to sha1
This patch fixes a problem where only the first byte of the build hash was being used for the disk cache id. There was some discussion on gitlab: https://gitlab.freedesktop.org/mesa/mesa/commit/83ea8dd99bb16e5d9bb880e64cd2047abc536b70#note_52154 I've tested radeon_si and radv locally, but not nouveau or r600. David McFarland (1): util: Change remaining uint32 cache ids to sha1 src/amd/vulkan/radv_device.c | 22 +-- src/gallium/drivers/nouveau/nouveau_screen.c | 29 - src/gallium/drivers/r600/r600_pipe_common.c | 43 ++--- src/gallium/drivers/radeonsi/si_pipe.c | 64 ++-- src/util/disk_cache.h| 16 +++-- 5 files changed, 81 insertions(+), 93 deletions(-) -- 2.19.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/4] gen: Add AMD_gpu_shader_int64.xml to tarball
CC: Ian Romanick
CC: Marek Olšák
Fixes: b3c17330e631695b5e5dc209ba9ea1a528618c97
("mesa: expose AMD_gpu_shader_int64")
---
src/mapi/glapi/gen/Makefile.am | 1 +
src/mapi/glapi/gen/meson.build | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/mapi/glapi/gen/Makefile.am b/src/mapi/glapi/gen/Makefile.am
index e59e6cc90a3..187928e377a 100644
--- a/src/mapi/glapi/gen/Makefile.am
+++ b/src/mapi/glapi/gen/Makefile.am
@@ -190,6 +190,7 @@ API_XML = \
ARB_viewport_array.xml \
AMD_depth_clamp_separate.xml \
AMD_draw_buffers_blend.xml \
+ AMD_gpu_shader_int64.xml \
AMD_performance_monitor.xml \
ARB_vertex_type_2_10_10_10_rev.xml \
APPLE_object_purgeable.xml \
diff --git a/src/mapi/glapi/gen/meson.build b/src/mapi/glapi/gen/meson.build
index 1cf3339e30e..f494e9707b6 100644
--- a/src/mapi/glapi/gen/meson.build
+++ b/src/mapi/glapi/gen/meson.build
@@ -97,6 +97,7 @@ api_xml_files = files(
'ARB_viewport_array.xml',
'AMD_depth_clamp_separate.xml',
'AMD_draw_buffers_blend.xml',
+ 'AMD_gpu_shader_int64.xml',
'AMD_performance_monitor.xml',
'ARB_vertex_type_2_10_10_10_rev.xml',
'APPLE_object_purgeable.xml',
--
2.19.1
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[Mesa-dev] [PATCH 4/4] autotools: include intel_tiled_memcopy.c
There are two problems with the fixed patch. First, it fails to create a
dependency on the sourced .c file, so changes to intel_tiled_memcpy.c
won't trigger a rebuild. It also doesn't get included in the dist
tarball.
CC: Tapani Pälli
Fixes: 11b1afdc92db98e93f2ca50beeb7fc481a11e708
("i965/tiled_memcpy: inline movntdqa loads in tiled_to_linear")
---
src/mesa/drivers/dri/i965/Makefile.am | 4
src/mesa/drivers/dri/i965/Makefile.sources | 3 +++
2 files changed, 7 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/Makefile.am
b/src/mesa/drivers/dri/i965/Makefile.am
index dc19da2c4a6..fda17589cfb 100644
--- a/src/mesa/drivers/dri/i965/Makefile.am
+++ b/src/mesa/drivers/dri/i965/Makefile.am
@@ -126,6 +126,7 @@ CLEANFILES = $(BUILT_SOURCES)
EXTRA_DIST = \
brw_oa.py \
$(i965_oa_xml_FILES) \
+ $(intel_tiled_memcpy_dep_FILES) \
meson.build
brw_oa_metrics.c: brw_oa.py $(i965_oa_xml_FILES)
@@ -135,3 +136,6 @@ brw_oa_metrics.c: brw_oa.py $(i965_oa_xml_FILES)
$(i965_oa_xml_FILES:%=$(srcdir)/%)
brw_oa_metrics.h: brw_oa_metrics.c
+
+intel_tiled_memcpy_normal.c: $(intel_tiled_memcpy_dep_FILES)
+intel_tiled_memcpy_sse41.c: $(intel_tiled_memcpy_dep_FILES)
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
b/src/mesa/drivers/dri/i965/Makefile.sources
index 0ab0e42fb18..043a70029f2 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -121,6 +121,9 @@ intel_tiled_memcpy_sse41_FILES = \
intel_tiled_memcpy_sse41.c \
intel_tiled_memcpy_sse41.h
+intel_tiled_memcpy_dep_FILES = \
+ intel_tiled_memcpy.c
+
i965_gen4_FILES = \
genX_blorp_exec.c \
genX_state_upload.c
--
2.19.1
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[Mesa-dev] [PATCH 3/4] meson: fix formatting and add extra_files to i965
extra_files is just a nice way to to tell certain IDE's (and those reading the file) that this file is also a dependency. Meson will use the .d file generated by the compiler to figure out what the target actually depends on. --- src/mesa/drivers/dri/i965/meson.build | 22 -- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/src/mesa/drivers/dri/i965/meson.build b/src/mesa/drivers/dri/i965/meson.build index bf366a6c157..24172955e9b 100644 --- a/src/mesa/drivers/dri/i965/meson.build +++ b/src/mesa/drivers/dri/i965/meson.build @@ -191,20 +191,22 @@ intel_tiled_memcpy = static_library( inc_common, inc_intel, inc_dri_common, inc_drm_uapi, ], c_args : [c_vis_args, no_override_init_args, '-msse2'], + extra_files : ['intel_tiled_memcpy.c'] ) if with_sse41 -intel_tiled_memcpy_sse41 = static_library( - 'intel_tiled_memcpy_sse41', - [files_intel_tiled_memcpy_sse41], - include_directories : [ -inc_common, inc_intel, inc_dri_common, inc_drm_uapi, - ], - link_args : [ '-Wl,--exclude-libs=ALL' ], - c_args : [c_vis_args, no_override_init_args, '-Wl,--exclude-libs=ALL', '-msse2', sse41_args], -) + intel_tiled_memcpy_sse41 = static_library( +'intel_tiled_memcpy_sse41', +[files_intel_tiled_memcpy_sse41], +include_directories : [ + inc_common, inc_intel, inc_dri_common, inc_drm_uapi, +], +link_args : ['-Wl,--exclude-libs=ALL'], +c_args : [c_vis_args, no_override_init_args, '-Wl,--exclude-libs=ALL', '-msse2', sse41_args], +extra_files : ['intel_tiled_memcpy.c'] + ) else -intel_tiled_memcpy_sse41 = [] + intel_tiled_memcpy_sse41 = [] endif -- 2.19.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/4] gen: Add EXT_vertex_attrib_64bit.xml to dependency lists
Which is also required to put it in the tarball, a requirement for
building with meson from the tarball.
CC: Ian Romanick
CC: Marek Olšák
Fixes: 263c962cfdee6b43578ee5f28601309ea77d1434
("mesa: expose EXT_vertex_attrib_64bit")
---
src/mapi/glapi/gen/Makefile.am | 1 +
src/mapi/glapi/gen/meson.build | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/mapi/glapi/gen/Makefile.am b/src/mapi/glapi/gen/Makefile.am
index ab369a0d333..e59e6cc90a3 100644
--- a/src/mapi/glapi/gen/Makefile.am
+++ b/src/mapi/glapi/gen/Makefile.am
@@ -205,6 +205,7 @@ API_XML = \
EXT_texture_array.xml \
EXT_texture_integer.xml \
EXT_transform_feedback.xml \
+ EXT_vertex_attrib_64bit.xml \
EXT_window_rectangles.xml \
GREMEDY_string_marker.xml \
INTEL_performance_query.xml \
diff --git a/src/mapi/glapi/gen/meson.build b/src/mapi/glapi/gen/meson.build
index c638b1ece60..1cf3339e30e 100644
--- a/src/mapi/glapi/gen/meson.build
+++ b/src/mapi/glapi/gen/meson.build
@@ -112,6 +112,7 @@ api_xml_files = files(
'EXT_texture_array.xml',
'EXT_texture_integer.xml',
'EXT_transform_feedback.xml',
+ 'EXT_vertex_attrib_64bit.xml',
'EXT_window_rectangles.xml',
'GREMEDY_string_marker.xml',
'INTEL_performance_query.xml',
--
2.19.1
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[Mesa-dev] [AppVeyor] mesa master #9135 failed
Build mesa 9135 failed Commit 0ff1ccca25 by Timothy Arceri on 10/23/2018 10:56 AM: radv: call nir_link_xfb_varyings()\n\nReviewed-by: Samuel Pitoiset Configure your notification preferences ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Mesa-stable][PATCH] Scons: Put to rest zombie texture_float build option
I found a remnant of texture_float build option that wasn't removed in
https://gitlab.freedesktop.org/mesa/mesa/commit/66673bef941af344314fe9c91cad8cd330b245eb
This patch removes it.
---
common.py | 3 ---
1 file changed, 3 deletions(-)
diff --git a/common.py b/common.py
index f4f2bb4..be3ccfc 100644
--- a/common.py
+++ b/common.py
@@ -105,9 +105,6 @@ def AddOptions(opts):
opts.Add(BoolOption('debug', 'DEPRECATED: debug build', 'yes'))
opts.Add(BoolOption('profile', 'DEPRECATED: profile build', 'no'))
opts.Add(BoolOption('quiet', 'DEPRECATED: profile build', 'yes'))
- opts.Add(BoolOption('texture_float',
- 'enable floating-point textures and renderbuffers',
- 'no'))
opts.Add(BoolOption('swr', 'Build OpenSWR', 'no'))
if host_platform == 'windows':
opts.Add('MSVC_VERSION', 'Microsoft Visual C/C++ version')
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Re: [Mesa-dev] [PATCH 3/3] radv: call nir_link_xfb_varyings()
Patches 2-3 are:
Reviewed-by: Samuel Pitoiset
Thanks!
On 10/23/18 12:56 PM, Timothy Arceri wrote:
---
src/amd/vulkan/radv_pipeline.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 396b44d25a1..c21ca1743a4 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1792,6 +1792,10 @@ radv_link_shaders(struct radv_pipeline *pipeline,
nir_shader **shaders)
unsigned first = ordered_shaders[shader_count - 1]->info.stage;
unsigned last = ordered_shaders[0]->info.stage;
+ if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
+ ordered_shaders[1]->info.has_transform_feedback_varyings)
+ nir_link_xfb_varyings(ordered_shaders[1],
ordered_shaders[0]);
+
for (int i = 0; i < shader_count; ++i) {
nir_variable_mode mask = 0;
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[Mesa-dev] [Bug 108532] make check nir_copy_prop_vars_test.store_store_load_different_components regression
https://bugs.freedesktop.org/show_bug.cgi?id=108532 Bug ID: 108532 Summary: make check nir_copy_prop_vars_test.store_store_load_different_com ponents regression Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: All Status: NEW Keywords: regression Severity: normal Priority: medium Component: Mesa core Assignee: mesa-dev@lists.freedesktop.org Reporter: v...@freedesktop.org QA Contact: mesa-dev@lists.freedesktop.org Mesa 18.3.0-devel: src/compiler/test-suite.log # TOTAL: 10 # PASS: 9 # SKIP: 0 # XFAIL: 0 # FAIL: 1 # XPASS: 0 # ERROR: 0 .. contents:: :depth: 2 FAIL: nir/tests/vars_tests == Running main() from gtest_main.cc [==] Running 17 tests from 3 test cases. [--] Global test environment set-up. [--] 4 tests from nir_redundant_load_vars_test [ RUN ] nir_redundant_load_vars_test.duplicated_load [ OK ] nir_redundant_load_vars_test.duplicated_load (0 ms) [ RUN ] nir_redundant_load_vars_test.duplicated_load_in_two_blocks [ OK ] nir_redundant_load_vars_test.duplicated_load_in_two_blocks (0 ms) [ RUN ] nir_redundant_load_vars_test.invalidate_inside_if_block [ OK ] nir_redundant_load_vars_test.invalidate_inside_if_block (0 ms) [ RUN ] nir_redundant_load_vars_test.invalidate_live_load_in_the_end_of_loop [ OK ] nir_redundant_load_vars_test.invalidate_live_load_in_the_end_of_loop (0 ms) [--] 4 tests from nir_redundant_load_vars_test (0 ms total) [--] 7 tests from nir_copy_prop_vars_test [ RUN ] nir_copy_prop_vars_test.simple_copies [ OK ] nir_copy_prop_vars_test.simple_copies (0 ms) [ RUN ] nir_copy_prop_vars_test.simple_store_load [ OK ] nir_copy_prop_vars_test.simple_store_load (0 ms) [ RUN ] nir_copy_prop_vars_test.store_store_load [ OK ] nir_copy_prop_vars_test.store_store_load (0 ms) [ RUN ] nir_copy_prop_vars_test.store_store_load_different_components Assertion failed: (nir_src_num_components(src) == 1), function nir_src_as_uint, file nir/nir.c, line 1275. FAIL nir/tests/vars_tests (exit status: 134) -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v4 0/3] Add and enable extension EXT_sRGB_write_control
From: Gert Wollny another update to the series, thanks for reviewing, Gert v4: Use PIPE_FORMAT_R8G8B8A8_SRGB as key format to check support for this extension. v3: correct Gallium to only create sRGB renderbuffers based on Visual.srgbCapable when on desktop GL. v2: - core: Correct the extension table to list the extension as GLES only - core: drop EXTRA_API_ES3, the requirements for get operations listed here get OR-ed. (both Ilia Mirkin) - gallium: always enable the extension when sRGB is supported (Ilia Mirkin). - gallium: Correct handling by moving extension initialization to the place where gallium/st actually takes care of this. This also fixes properly disabling the extension via MESA_EXTENSION_OVERRIDE - gallium: reinstate check for desktop GL and add check for the extension when creating the framebuffer - intel: Also text whether the extension is properly disabled by MESA_EXTENSION_OVERRIDE best, Gert Gert Wollny (3): mesa/core: Add support for EXT_sRGB_write_control mesa/st: enable EXT_sRGB_write_control for Gallium drivers that support it intel/i965: Enable extension EXT_sRGB_write_control src/gallium/docs/source/screen.rst | 3 ++ src/mesa/drivers/dri/i965/intel_extensions.c | 1 + src/mesa/main/enable.c | 4 +-- src/mesa/main/extensions_table.h | 1 + src/mesa/main/get.c | 5 +++ src/mesa/main/get_hash_params.py | 1 + src/mesa/main/mtypes.h | 1 + src/mesa/state_tracker/st_extensions.c | 8 - src/mesa/state_tracker/st_manager.c | 37 9 files changed, 44 insertions(+), 17 deletions(-) -- 2.18.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v4 2/3] mesa/st: enable EXT_sRGB_write_control for Gallium drivers that support it
From: Gert Wollny
With this patch the extension EXT_sRGB_write_control is enabled for
gallium drivers that support sRGB formats as render targets.
Tested (and pass) on r600 (evergreen) and softpipe:
dEQP-GLES31.functional.fbo.srgb_write_control.framebuffer_srgb_enabled*
with "MESA_GLES_VERSION_OVERRIDE=3.2" (the tests needlessly check for this), and
dEQP-GLES31.functional.fbo.srgb_write_control.framebuffer_srgb_unsupported_enum
when extension is manually disabled via MESA_EXTENSION_OVERRIDE
v2: - always enable the extension when sRGB is supported (Ilia Mirkin).
- Correct handling by moving extension initialization to the
place where gallium/st actually takes care of this. This also
fixes properly disabling the extension via MESA_EXTENSION_OVERRIDE
- reinstate check for desktop GL and add check for the extension
when creating the framebuffer
v3: - Only create sRGB renderbuffers based on Visual.srgbCapable when
on desktop GL.
v4: - Use PIPE_FORMAT_B8G8R8A8_SRGB to check for the capability, since this
is also the format that is used top check for EGL_KHR_gl_colorspace
support. virgl on a GLES host usually doesn't provide this format but
one can make it available to signal that the host supports this
extension.
Signed-off-by: Gert Wollny
---
src/gallium/docs/source/screen.rst | 3 +++
src/mesa/state_tracker/st_extensions.c | 8 +-
src/mesa/state_tracker/st_manager.c| 37 --
3 files changed, 33 insertions(+), 15 deletions(-)
diff --git a/src/gallium/docs/source/screen.rst
b/src/gallium/docs/source/screen.rst
index 0abd164494..da677eb04b 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -477,6 +477,9 @@ subpixel precision bias in bits during conservative
rasterization.
0 means no limit.
* ``PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET``: The maximum supported value for
of pipe_vertex_element::src_offset.
+* ``PIPE_CAP_SRGB_WRITE_CONTROL``: Indicates whether the drivers on GLES
supports
+ enabling/disabling the conversion from linear space to sRGB at framebuffer or
+ blend time.
.. _pipe_capf:
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index 798ee60875..38d6a3ed1d 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -1167,7 +1167,7 @@ void st_init_extensions(struct pipe_screen *screen,
consts->MaxFramebufferSamples =
get_max_samples_for_formats(screen, ARRAY_SIZE(void_formats),
void_formats, 32,
- PIPE_BIND_RENDER_TARGET);
+ PIPE_BIND_RENDER_TARGET);
if (extensions->AMD_framebuffer_multisample_advanced) {
/* AMD_framebuffer_multisample_advanced */
@@ -1393,6 +1393,12 @@ void st_init_extensions(struct pipe_screen *screen,
}
#endif
+ extensions->EXT_sRGB_write_control =
+ screen->is_format_supported(screen, PIPE_FORMAT_B8G8R8A8_SRGB,
+ PIPE_TEXTURE_2D, 0, 0,
+ (PIPE_BIND_DISPLAY_TARGET |
+ PIPE_BIND_RENDER_TARGET));
+
if (screen->get_param(screen, PIPE_CAP_DOUBLES)) {
extensions->ARB_gpu_shader_fp64 = GL_TRUE;
extensions->ARB_vertex_attrib_64bit = GL_TRUE;
diff --git a/src/mesa/state_tracker/st_manager.c
b/src/mesa/state_tracker/st_manager.c
index ceb48dd490..df898beb23 100644
--- a/src/mesa/state_tracker/st_manager.c
+++ b/src/mesa/state_tracker/st_manager.c
@@ -295,7 +295,7 @@ st_framebuffer_update_attachments(struct st_framebuffer
*stfb)
*/
static boolean
st_framebuffer_add_renderbuffer(struct st_framebuffer *stfb,
-gl_buffer_index idx)
+gl_buffer_index idx, bool prefer_srgb)
{
struct gl_renderbuffer *rb;
enum pipe_format format;
@@ -318,7 +318,7 @@ st_framebuffer_add_renderbuffer(struct st_framebuffer *stfb,
break;
default:
format = stfb->iface->visual->color_format;
- if (stfb->Base.Visual.sRGBCapable)
+ if (prefer_srgb)
format = util_format_srgb(format);
sw = FALSE;
break;
@@ -436,6 +436,7 @@ st_framebuffer_create(struct st_context *st,
struct st_framebuffer *stfb;
struct gl_config mode;
gl_buffer_index idx;
+ bool prefer_srgb = false;
if (!stfbi)
return NULL;
@@ -457,14 +458,15 @@ st_framebuffer_create(struct st_context *st,
* format such that util_format_srgb(visual->color_format) can be supported
* by the pipe driver. We still need to advertise the capability here.
*
-* For GLES, however, sRGB framebuffer write is controlled only by the
-* capability of the framebuffer. There is GL_EXT_sRGB_write_control to
-* give applications the control back, but sRGB write is still
[Mesa-dev] [PATCH v4 3/3] intel/i965: Enable extension EXT_sRGB_write_control
From: Gert Wollny v2: Fix ordering of extensions (Ian Romanick) Enables and passes on i965: dEQP-GLES31.functional.fbo.srgb_write_control.framebuffer_srgb_enabled* Signed-off-by: Gert Wollny --- src/mesa/drivers/dri/i965/intel_extensions.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index d7e02efb54..3c147291ff 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -104,6 +104,7 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.EXT_point_parameters = true; ctx->Extensions.EXT_provoking_vertex = true; ctx->Extensions.EXT_render_snorm = true; + ctx->Extensions.EXT_sRGB_write_control = true; ctx->Extensions.EXT_stencil_two_side = true; ctx->Extensions.EXT_texture_array = true; ctx->Extensions.EXT_texture_env_dot3 = true; -- 2.18.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v4 1/3] mesa/core: Add support for EXT_sRGB_write_control
From: Gert Wollny
This GLES extension gives the applications the control over deciding whether
the conversion from linear space to sRGB is necessary by enabling or
disabling this conversion at framebuffer write or blending time just
like it is possible for desktop GL.
v2: - Correct the extension table to list the extension as GLES only
- drop EXTRA_API_ES3, the requirements for get operations listed
here get OR-ed. (both Ilia Mirkin)
Signed-off-by: Gert Wollny
---
src/mesa/main/enable.c | 4 ++--
src/mesa/main/extensions_table.h | 1 +
src/mesa/main/get.c | 5 +
src/mesa/main/get_hash_params.py | 1 +
src/mesa/main/mtypes.h | 1 +
5 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/enable.c b/src/mesa/main/enable.c
index bd3e493da5..06c5a0eb68 100644
--- a/src/mesa/main/enable.c
+++ b/src/mesa/main/enable.c
@@ -1125,7 +1125,7 @@ _mesa_set_enable(struct gl_context *ctx, GLenum cap,
GLboolean state)
/* GL3.0 - GL_framebuffer_sRGB */
case GL_FRAMEBUFFER_SRGB_EXT:
- if (!_mesa_is_desktop_gl(ctx))
+ if (!_mesa_is_desktop_gl(ctx) &&
!ctx->Extensions.EXT_sRGB_write_control)
goto invalid_enum_error;
CHECK_EXTENSION(EXT_framebuffer_sRGB, cap);
_mesa_set_framebuffer_srgb(ctx, state);
@@ -1765,7 +1765,7 @@ _mesa_IsEnabled( GLenum cap )
/* GL3.0 - GL_framebuffer_sRGB */
case GL_FRAMEBUFFER_SRGB_EXT:
- if (!_mesa_is_desktop_gl(ctx))
+ if (!_mesa_is_desktop_gl(ctx) &&
!ctx->Extensions.EXT_sRGB_write_control)
goto invalid_enum_error;
CHECK_EXTENSION(EXT_framebuffer_sRGB);
return ctx->Color.sRGBEnabled;
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index 09bf923bd0..8679ee2fc5 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -265,6 +265,7 @@ EXT(EXT_shader_integer_mix ,
EXT_shader_integer_mix
EXT(EXT_shader_io_blocks, dummy_true
, x , x , x , 31, 2014)
EXT(EXT_shader_samples_identical, EXT_shader_samples_identical
, GLL, GLC, x , 31, 2015)
EXT(EXT_shadow_funcs, ARB_shadow
, GLL, x , x , x , 2002)
+EXT(EXT_sRGB_write_control , EXT_sRGB_write_control
, x, x , x , 30, 2013)
EXT(EXT_stencil_two_side, EXT_stencil_two_side
, GLL, x , x , x , 2001)
EXT(EXT_stencil_wrap, dummy_true
, GLL, x , x , x , 2002)
EXT(EXT_subtexture , dummy_true
, GLL, x , x , x , 1995)
diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index 1b1679e8bf..3a77bc6f8d 100644
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
@@ -394,6 +394,11 @@ static const int extra_ARB_compute_shader_es31[] = {
EXTRA_END
};
+static const int extra_EXT_sRGB_write_control_es30[] = {
+ EXT(EXT_sRGB_write_control),
+ EXTRA_END
+};
+
static const int extra_ARB_shader_storage_buffer_object_es31[] = {
EXT(ARB_shader_storage_buffer_object),
EXTRA_API_ES31,
diff --git a/src/mesa/main/get_hash_params.py b/src/mesa/main/get_hash_params.py
index 1840db6ebb..822fab8151 100644
--- a/src/mesa/main/get_hash_params.py
+++ b/src/mesa/main/get_hash_params.py
@@ -262,6 +262,7 @@ descriptor=[
# Enums in GLES2, GLES3
{ "apis": ["GLES2", "GLES3"], "params": [
[ "GPU_DISJOINT_EXT", "LOC_CUSTOM, TYPE_INT, 0,
extra_EXT_disjoint_timer_query" ],
+ [ "FRAMEBUFFER_SRGB_EXT", "CONTEXT_BOOL(Color.sRGBEnabled),
extra_EXT_sRGB_write_control_es30" ],
]},
{ "apis": ["GL", "GL_CORE", "GLES2"], "params": [
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 9ed49b7ff2..31cf62fdb6 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -4253,6 +4253,7 @@ struct gl_extensions
GLboolean EXT_semaphore_fd;
GLboolean EXT_shader_integer_mix;
GLboolean EXT_shader_samples_identical;
+ GLboolean EXT_sRGB_write_control;
GLboolean EXT_stencil_two_side;
GLboolean EXT_texture_array;
GLboolean EXT_texture_compression_latc;
--
2.18.1
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Re: [Mesa-dev] [PATCH v2] anv: Allow presenting via a different GPU
Yeah, I saw this while I was working on the bus_info stuff and I'm not sure
why we never enabled PRIME for Intel. I think I may have had a reason but
I have no idea what it was and I don't see a problem with it.
Reviewed-by: Jason Ekstrand
On Tue, Oct 23, 2018 at 10:32 AM Alex Smith
wrote:
> anv_GetPhysicalDeviceSurfaceSupportKHR will already return success for
> this, but anv_GetPhysicalDevice{Xcb,Xlib}PresentationSupportKHR do not.
> Apps which check for presentation support via the latter (all Feral
> Vulkan games at least) will therefore fail.
>
> This allows me to render on an Intel GPU and present to a display
> connected to an AMD card (tested HD 530 + Vega 64).
>
> v2: Rebase on current master.
>
> Signed-off-by: Alex Smith
> ---
> src/intel/vulkan/anv_wsi_x11.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/vulkan/anv_wsi_x11.c
> b/src/intel/vulkan/anv_wsi_x11.c
> index bfa76e88e7..7a27ceab64 100644
> --- a/src/intel/vulkan/anv_wsi_x11.c
> +++ b/src/intel/vulkan/anv_wsi_x11.c
> @@ -41,7 +41,7 @@ VkBool32 anv_GetPhysicalDeviceXcbPresentationSupportKHR(
> return wsi_get_physical_device_xcb_presentation_support(
>>wsi_device,
>queueFamilyIndex,
> - false,
> + true,
>connection, visual_id);
> }
>
> @@ -56,7 +56,7 @@ VkBool32 anv_GetPhysicalDeviceXlibPresentationSupportKHR(
> return wsi_get_physical_device_xcb_presentation_support(
>>wsi_device,
>queueFamilyIndex,
> - false,
> + true,
>XGetXCBConnection(dpy), visualID);
> }
>
> --
> 2.14.4
>
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Re: [Mesa-dev] [PATCH 30/31] nir/algebraic: Add some optimizations for D3D-style booleans
On Tue, Oct 23, 2018 at 1:38 AM Connor Abbott wrote:
> On Tue, Oct 23, 2018 at 12:16 AM Jason Ekstrand
> wrote:
> >
> > D3D booleans use a 32-bit 0/-1 representation. Because this previously
> > matched NIR exactly, we didn't have to really optimize for it. Now that
> > we have 1-bit booleans, we need some specific optimizations to chew
> > through the D3D12-style booleans.
> > ---
> > src/compiler/nir/nir_opt_algebraic.py | 13 +
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/src/compiler/nir/nir_opt_algebraic.py
> b/src/compiler/nir/nir_opt_algebraic.py
> > index f0861c4411d..4d778e4b308 100644
> > --- a/src/compiler/nir/nir_opt_algebraic.py
> > +++ b/src/compiler/nir/nir_opt_algebraic.py
> > @@ -239,6 +239,7 @@ optimizations = [
> > (('fne', ('b2f', a), 0.0), a),
> > (('ieq', ('b2i', a), 0), ('inot', a)),
> > (('ine', ('b2i', a), 0), a),
> > + (('ine', ('ineg', ('b2i', a)), 0), a),
> >
> > (('fne', ('u2f32', a), 0.0), ('ine', a, 0)),
> > (('feq', ('u2f32', a), 0.0), ('ieq', a, 0)),
> > @@ -528,6 +529,18 @@ optimizations = [
> > (('bcsel', a, b, b), b),
> > (('fcsel', a, b, b), b),
> >
> > + # D3D Boolean eumulation
> > + (('bcsel', a, -1, 0), ('ineg', ('b2i', a))),
> > + (('bcsel', a, 0, -1), ('ineg', ('b2i', ('inot', a,
> > + (('iand', ('ineg', ('b2i', a)), ('ineg', ('b2i', b))),
> > +('ineg', ('b2i', ('iand', a, b,
> > + (('ior', ('ineg', ('b2i', a)), ('ineg', ('b2i', b))),
> > +('ineg', ('b2i', ('ior', a, b,
> > + (('ieq', ('ineg', ('b2i', a)), 0), ('inot', a)),
> > + (('ieq', ('ineg', ('b2i', a)), -1), a),
> > + (('ine', ('ineg', ('b2i', a)), 0), a),
>
> Isn't this the same as the line you added above?
>
Yes, it is. I've deleted the top one locally.
--Jason
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Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
On Tue, Oct 23, 2018 at 12:04 PM Christian Gmeiner <
christian.gmei...@gmail.com> wrote:
> Am Di., 23. Okt. 2018 um 18:31 Uhr schrieb Ian Romanick <
> i...@freedesktop.org>:
> >
> > On 10/23/2018 08:33 AM, Connor Abbott wrote:
> > > On Tue, Oct 23, 2018 at 12:16 AM Jason Ekstrand
> wrote:
> > >>
> > >> This should be useful for drivers that don't support real integers.
> > >>
> > >> Cc: Alyssa Rosenzweig
> > >> ---
> > >> src/compiler/Makefile.sources | 1 +
> > >> src/compiler/nir/meson.build | 1 +
> > >> src/compiler/nir/nir_lower_bool_to_float.c | 181
> +
> > >> 3 files changed, 183 insertions(+)
> > >> create mode 100644 src/compiler/nir/nir_lower_bool_to_float.c
> > >>
> > >> diff --git a/src/compiler/Makefile.sources
> b/src/compiler/Makefile.sources
> > >> index 8f65f974ab8..2ff12ff43cb 100644
> > >> --- a/src/compiler/Makefile.sources
> > >> +++ b/src/compiler/Makefile.sources
> > >> @@ -230,6 +230,7 @@ NIR_FILES = \
> > >> nir/nir_lower_atomics_to_ssbo.c \
> > >> nir/nir_lower_bitmap.c \
> > >> nir/nir_lower_bit_size.c \
> > >> + nir/nir_lower_bool_to_float.c \
> > >> nir/nir_lower_bool_to_int32.c \
> > >> nir/nir_lower_clamp_color_outputs.c \
> > >> nir/nir_lower_clip.c \
> > >> diff --git a/src/compiler/nir/meson.build
> b/src/compiler/nir/meson.build
> > >> index 5809551c9d4..f715668a03b 100644
> > >> --- a/src/compiler/nir/meson.build
> > >> +++ b/src/compiler/nir/meson.build
> > >> @@ -113,6 +113,7 @@ files_libnir = files(
> > >>'nir_lower_alpha_test.c',
> > >>'nir_lower_atomics_to_ssbo.c',
> > >>'nir_lower_bitmap.c',
> > >> + 'nir_lower_bool_to_float.c',
> > >>'nir_lower_bool_to_int32.c',
> > >>'nir_lower_clamp_color_outputs.c',
> > >>'nir_lower_clip.c',
> > >> diff --git a/src/compiler/nir/nir_lower_bool_to_float.c
> b/src/compiler/nir/nir_lower_bool_to_float.c
> > >> new file mode 100644
> > >> index 000..7aa5efb5a2f
> > >> --- /dev/null
> > >> +++ b/src/compiler/nir/nir_lower_bool_to_float.c
> > >> @@ -0,0 +1,181 @@
> > >> +/*
> > >> + * Copyright © 2018 Intel Corporation
> > >> + *
> > >> + * Permission is hereby granted, free of charge, to any person
> obtaining a
> > >> + * copy of this software and associated documentation files (the
> "Software"),
> > >> + * to deal in the Software without restriction, including without
> limitation
> > >> + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> > >> + * and/or sell copies of the Software, and to permit persons to whom
> the
> > >> + * Software is furnished to do so, subject to the following
> conditions:
> > >> + *
> > >> + * The above copyright notice and this permission notice (including
> the next
> > >> + * paragraph) shall be included in all copies or substantial
> portions of the
> > >> + * Software.
> > >> + *
> > >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> > >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> > >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT SHALL
> > >> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
> OR OTHER
> > >> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING
> > >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> OTHER DEALINGS
> > >> + * IN THE SOFTWARE.
> > >> + */
> > >> +
> > >> +#include "nir.h"
> > >> +#include "nir_builder.h"
> > >> +
> > >> +static bool
> > >> +assert_ssa_def_is_not_1bit(nir_ssa_def *def, UNUSED void *unused)
> > >> +{
> > >> + assert(def->bit_size > 1);
> > >> + return true;
> > >> +}
> > >> +
> > >> +static bool
> > >> +rewrite_1bit_ssa_def_to_32bit(nir_ssa_def *def, void *_progress)
> > >> +{
> > >> + bool *progress = _progress;
> > >> + if (def->bit_size == 1) {
> > >> + def->bit_size = 32;
> > >> + *progress = true;
> > >> + }
> > >> + return true;
> > >> +}
> > >> +
> > >> +static bool
> > >> +lower_alu_instr(nir_builder *b, nir_alu_instr *alu)
> > >> +{
> > >> + const nir_op_info *op_info = _op_infos[alu->op];
> > >> +
> > >> + b->cursor = nir_before_instr(>instr);
> > >> +
> > >> + /* Replacement SSA value */
> > >> + nir_ssa_def *rep = NULL;
> > >> + switch (alu->op) {
> > >> + case nir_op_b2f: alu->op = nir_op_fmov; break;
> > >> + case nir_op_b2i: alu->op = nir_op_fmov; break;
> > >> + case nir_op_f2b:
> > >> + case nir_op_i2b:
> > >> + rep = nir_sne(b, nir_ssa_for_alu_src(b, alu, 0),
> > >> + nir_imm_float(b, 0));
> > >> + break;
> > >> +
> > >> + case nir_op_flt: alu->op = nir_op_slt; break;
> > >> + case nir_op_fge: alu->op = nir_op_sge; break;
> > >> + case nir_op_feq: alu->op = nir_op_seq; break;
> > >> + case nir_op_fne: alu->op = nir_op_sne; break;
> > >> + case nir_op_ilt: alu->op = nir_op_slt; break;
> > >> + case nir_op_ige: alu->op =
Re: [Mesa-dev] [PATCH] docs/calendar: Add 18.3 plan and expand 18.2
Quoting Juan A. Suarez Romero (2018-10-23 09:53:03) > On Tue, 2018-10-23 at 09:30 -0700, Dylan Baker wrote: > > CC: Emil Velikov > > CC: Juan A. Romero Suarez > > --- > > docs/release-calendar.html | 38 +- > > 1 file changed, 37 insertions(+), 1 deletion(-) > > > > diff --git a/docs/release-calendar.html b/docs/release-calendar.html > > index a525c62..6bd4fc0c0e8 100644 > > --- a/docs/release-calendar.html > > +++ b/docs/release-calendar.html > > @@ -39,7 +39,7 @@ if you'd like to nominate a patch in the next stable > > release. > > Notes > > > > > > -18.2 > > +18.2 > > 2018-10-31 > > 18.2.4 > > Andres Gomez > > @@ -49,8 +49,44 @@ if you'd like to nominate a patch in the next stable > > release. > > 2018-11-14 > > 18.2.5 > > Andres Gomez > > + > > + > > + > > +2018-11-28 > > +18.2.6 > > +Juan A. Suarez > > + > > + > > + > > +2018-12-12 > > +18.2.7 > > +Juan A. Suarez > > Last planned 18.2.x release > > > > +18.3 > > +2018-10-31 > > +18.2.0-rc1 > >^^^ > Should be 18.3.0 (same in the rest of the RCs) Oops :) > > > +Dylan Baker > > + > > + > > + > > +2018-11-07 > > +18.2.0-rc2 > > +Dylan Baker > > + > > + > > + > > +2018-11-14 > > +18.2.0-rc3 > > +Dylan Baker > > + > > + > > + > > +2018-11-21 > > +18.2.0-rc4/ > > >extra slash > > > > With those fixes, this is: > > Reviewed-by: Juan A. Suarez both fixed locally. I'll give Emil a bit to look at it before I push, thanks! > > > +Dylan Baker > > +Last planned RC/final release > > + > > > > > > > signature.asc Description: signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2] nir: fix nir_copy_propagation test
Reviewed-by: Jason Ekstrand
On Tue, Oct 23, 2018 at 9:55 AM Juan A. Suarez Romero
wrote:
> Use nir_src_comp_as_uint() to read the proper second component, as
> nir_src_as_uint() returns the first one.
>
> v2: Use nir_src_comp_as_uint() [Jason]
>
> Fixes: 16870de8a0a ("nir: Use nir_src_is_const and nir_src_as_* in core
> code")
> Signed-off-by: Juan A. Suarez Romero
> ---
> src/compiler/nir/tests/vars_tests.cpp | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/compiler/nir/tests/vars_tests.cpp
> b/src/compiler/nir/tests/vars_tests.cpp
> index 02c53804b84..a7bbeb02277 100644
> --- a/src/compiler/nir/tests/vars_tests.cpp
> +++ b/src/compiler/nir/tests/vars_tests.cpp
> @@ -375,7 +375,7 @@ TEST_F(nir_copy_prop_vars_test,
> store_store_load_different_components)
> ASSERT_TRUE(store_to_v1->src[1].is_ssa);
>
> ASSERT_TRUE(nir_src_is_const(store_to_v1->src[1]));
> - ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 20);
> + ASSERT_EQ(nir_src_comp_as_uint(store_to_v1->src[1], 1), 20);
> break;
>}
> }
> @@ -424,7 +424,7 @@ TEST_F(nir_copy_prop_vars_test,
> store_store_load_different_components_in_many_bl
> ASSERT_TRUE(store_to_v1->src[1].is_ssa);
>
> ASSERT_TRUE(nir_src_is_const(store_to_v1->src[1]));
> - ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 20);
> + ASSERT_EQ(nir_src_comp_as_uint(store_to_v1->src[1], 1), 20);
> break;
>}
> }
> --
> 2.17.2
>
>
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Re: [Mesa-dev] [PATCH] amd/common: check DRM version 3.27 for JPEG decode
On Tue, Oct 23, 2018 at 1:06 PM Liu, Leo wrote:
>
> JPEG was added after DRM version 3.26
>
> Signed-off-by: Leo Liu
> Fixes: 4558758c51749(amd/common: add vcn jpeg ip info query)
> Cc: Boyuan Zhang
> Cc: Alex Smith
Reviewed-by: Alex Deucher
> ---
> src/amd/common/ac_gpu_info.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
> index ed08b500c63..2c70fb2c721 100644
> --- a/src/amd/common/ac_gpu_info.c
> +++ b/src/amd/common/ac_gpu_info.c
> @@ -186,7 +186,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
> }
> }
>
> - if (info->drm_major == 3 && info->drm_minor >= 17) {
> + if (info->drm_major == 3 && info->drm_minor >= 27) {
> r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0,
> _jpeg);
> if (r) {
> fprintf(stderr, "amdgpu:
> amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
> --
> 2.17.1
>
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[Mesa-dev] [PATCH] amd/common: check DRM version 3.27 for JPEG decode
JPEG was added after DRM version 3.26
Signed-off-by: Leo Liu
Fixes: 4558758c51749(amd/common: add vcn jpeg ip info query)
Cc: Boyuan Zhang
Cc: Alex Smith
---
src/amd/common/ac_gpu_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index ed08b500c63..2c70fb2c721 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -186,7 +186,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
}
}
- if (info->drm_major == 3 && info->drm_minor >= 17) {
+ if (info->drm_major == 3 && info->drm_minor >= 27) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0,
_jpeg);
if (r) {
fprintf(stderr, "amdgpu:
amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
--
2.17.1
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Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
Am Di., 23. Okt. 2018 um 18:31 Uhr schrieb Ian Romanick :
>
> On 10/23/2018 08:33 AM, Connor Abbott wrote:
> > On Tue, Oct 23, 2018 at 12:16 AM Jason Ekstrand
> > wrote:
> >>
> >> This should be useful for drivers that don't support real integers.
> >>
> >> Cc: Alyssa Rosenzweig
> >> ---
> >> src/compiler/Makefile.sources | 1 +
> >> src/compiler/nir/meson.build | 1 +
> >> src/compiler/nir/nir_lower_bool_to_float.c | 181 +
> >> 3 files changed, 183 insertions(+)
> >> create mode 100644 src/compiler/nir/nir_lower_bool_to_float.c
> >>
> >> diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
> >> index 8f65f974ab8..2ff12ff43cb 100644
> >> --- a/src/compiler/Makefile.sources
> >> +++ b/src/compiler/Makefile.sources
> >> @@ -230,6 +230,7 @@ NIR_FILES = \
> >> nir/nir_lower_atomics_to_ssbo.c \
> >> nir/nir_lower_bitmap.c \
> >> nir/nir_lower_bit_size.c \
> >> + nir/nir_lower_bool_to_float.c \
> >> nir/nir_lower_bool_to_int32.c \
> >> nir/nir_lower_clamp_color_outputs.c \
> >> nir/nir_lower_clip.c \
> >> diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
> >> index 5809551c9d4..f715668a03b 100644
> >> --- a/src/compiler/nir/meson.build
> >> +++ b/src/compiler/nir/meson.build
> >> @@ -113,6 +113,7 @@ files_libnir = files(
> >>'nir_lower_alpha_test.c',
> >>'nir_lower_atomics_to_ssbo.c',
> >>'nir_lower_bitmap.c',
> >> + 'nir_lower_bool_to_float.c',
> >>'nir_lower_bool_to_int32.c',
> >>'nir_lower_clamp_color_outputs.c',
> >>'nir_lower_clip.c',
> >> diff --git a/src/compiler/nir/nir_lower_bool_to_float.c
> >> b/src/compiler/nir/nir_lower_bool_to_float.c
> >> new file mode 100644
> >> index 000..7aa5efb5a2f
> >> --- /dev/null
> >> +++ b/src/compiler/nir/nir_lower_bool_to_float.c
> >> @@ -0,0 +1,181 @@
> >> +/*
> >> + * Copyright © 2018 Intel Corporation
> >> + *
> >> + * Permission is hereby granted, free of charge, to any person obtaining a
> >> + * copy of this software and associated documentation files (the
> >> "Software"),
> >> + * to deal in the Software without restriction, including without
> >> limitation
> >> + * the rights to use, copy, modify, merge, publish, distribute,
> >> sublicense,
> >> + * and/or sell copies of the Software, and to permit persons to whom the
> >> + * Software is furnished to do so, subject to the following conditions:
> >> + *
> >> + * The above copyright notice and this permission notice (including the
> >> next
> >> + * paragraph) shall be included in all copies or substantial portions of
> >> the
> >> + * Software.
> >> + *
> >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> >> EXPRESS OR
> >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> >> MERCHANTABILITY,
> >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
> >> SHALL
> >> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> >> OTHER
> >> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> >> DEALINGS
> >> + * IN THE SOFTWARE.
> >> + */
> >> +
> >> +#include "nir.h"
> >> +#include "nir_builder.h"
> >> +
> >> +static bool
> >> +assert_ssa_def_is_not_1bit(nir_ssa_def *def, UNUSED void *unused)
> >> +{
> >> + assert(def->bit_size > 1);
> >> + return true;
> >> +}
> >> +
> >> +static bool
> >> +rewrite_1bit_ssa_def_to_32bit(nir_ssa_def *def, void *_progress)
> >> +{
> >> + bool *progress = _progress;
> >> + if (def->bit_size == 1) {
> >> + def->bit_size = 32;
> >> + *progress = true;
> >> + }
> >> + return true;
> >> +}
> >> +
> >> +static bool
> >> +lower_alu_instr(nir_builder *b, nir_alu_instr *alu)
> >> +{
> >> + const nir_op_info *op_info = _op_infos[alu->op];
> >> +
> >> + b->cursor = nir_before_instr(>instr);
> >> +
> >> + /* Replacement SSA value */
> >> + nir_ssa_def *rep = NULL;
> >> + switch (alu->op) {
> >> + case nir_op_b2f: alu->op = nir_op_fmov; break;
> >> + case nir_op_b2i: alu->op = nir_op_fmov; break;
> >> + case nir_op_f2b:
> >> + case nir_op_i2b:
> >> + rep = nir_sne(b, nir_ssa_for_alu_src(b, alu, 0),
> >> + nir_imm_float(b, 0));
> >> + break;
> >> +
> >> + case nir_op_flt: alu->op = nir_op_slt; break;
> >> + case nir_op_fge: alu->op = nir_op_sge; break;
> >> + case nir_op_feq: alu->op = nir_op_seq; break;
> >> + case nir_op_fne: alu->op = nir_op_sne; break;
> >> + case nir_op_ilt: alu->op = nir_op_slt; break;
> >> + case nir_op_ige: alu->op = nir_op_sge; break;
> >> + case nir_op_ieq: alu->op = nir_op_seq; break;
> >> + case nir_op_ine: alu->op = nir_op_sne; break;
> >> + case nir_op_ult: alu->op = nir_op_slt; break;
> >> + case nir_op_uge: alu->op = nir_op_sge; break;
> >> +
> >> + case nir_op_ball_fequal2: alu->op =
Re: [Mesa-dev] [PATCH] docs/calendar: Add 18.3 plan and expand 18.2
On Tue, 2018-10-23 at 09:30 -0700, Dylan Baker wrote: > CC: Emil Velikov > CC: Juan A. Romero Suarez > --- > docs/release-calendar.html | 38 +- > 1 file changed, 37 insertions(+), 1 deletion(-) > > diff --git a/docs/release-calendar.html b/docs/release-calendar.html > index a525c62..6bd4fc0c0e8 100644 > --- a/docs/release-calendar.html > +++ b/docs/release-calendar.html > @@ -39,7 +39,7 @@ if you'd like to nominate a patch in the next stable > release. > Notes > > > -18.2 > +18.2 > 2018-10-31 > 18.2.4 > Andres Gomez > @@ -49,8 +49,44 @@ if you'd like to nominate a patch in the next stable > release. > 2018-11-14 > 18.2.5 > Andres Gomez > + > + > + > +2018-11-28 > +18.2.6 > +Juan A. Suarez > + > + > + > +2018-12-12 > +18.2.7 > +Juan A. Suarez > Last planned 18.2.x release > > +18.3 > +2018-10-31 > +18.2.0-rc1 ^^^ Should be 18.3.0 (same in the rest of the RCs) > +Dylan Baker > + > + > + > +2018-11-07 > +18.2.0-rc2 > +Dylan Baker > + > + > + > +2018-11-14 > +18.2.0-rc3 > +Dylan Baker > + > + > + > +2018-11-21 > +18.2.0-rc4/ extra slash With those fixes, this is: Reviewed-by: Juan A. Suarez > +Dylan Baker > +Last planned RC/final release > + > > > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 108530] [Tracker] Mesa 18.3 Release Tracker
https://bugs.freedesktop.org/show_bug.cgi?id=108530 Michel Dänzer changed: What|Removed |Added Depends on||108330 Referenced Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=108330 [Bug 108330] WarThunder game performance killed after Ryzen optimisations -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
On 10/23/2018 08:33 AM, Connor Abbott wrote:
> On Tue, Oct 23, 2018 at 12:16 AM Jason Ekstrand wrote:
>>
>> This should be useful for drivers that don't support real integers.
>>
>> Cc: Alyssa Rosenzweig
>> ---
>> src/compiler/Makefile.sources | 1 +
>> src/compiler/nir/meson.build | 1 +
>> src/compiler/nir/nir_lower_bool_to_float.c | 181 +
>> 3 files changed, 183 insertions(+)
>> create mode 100644 src/compiler/nir/nir_lower_bool_to_float.c
>>
>> diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
>> index 8f65f974ab8..2ff12ff43cb 100644
>> --- a/src/compiler/Makefile.sources
>> +++ b/src/compiler/Makefile.sources
>> @@ -230,6 +230,7 @@ NIR_FILES = \
>> nir/nir_lower_atomics_to_ssbo.c \
>> nir/nir_lower_bitmap.c \
>> nir/nir_lower_bit_size.c \
>> + nir/nir_lower_bool_to_float.c \
>> nir/nir_lower_bool_to_int32.c \
>> nir/nir_lower_clamp_color_outputs.c \
>> nir/nir_lower_clip.c \
>> diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
>> index 5809551c9d4..f715668a03b 100644
>> --- a/src/compiler/nir/meson.build
>> +++ b/src/compiler/nir/meson.build
>> @@ -113,6 +113,7 @@ files_libnir = files(
>>'nir_lower_alpha_test.c',
>>'nir_lower_atomics_to_ssbo.c',
>>'nir_lower_bitmap.c',
>> + 'nir_lower_bool_to_float.c',
>>'nir_lower_bool_to_int32.c',
>>'nir_lower_clamp_color_outputs.c',
>>'nir_lower_clip.c',
>> diff --git a/src/compiler/nir/nir_lower_bool_to_float.c
>> b/src/compiler/nir/nir_lower_bool_to_float.c
>> new file mode 100644
>> index 000..7aa5efb5a2f
>> --- /dev/null
>> +++ b/src/compiler/nir/nir_lower_bool_to_float.c
>> @@ -0,0 +1,181 @@
>> +/*
>> + * Copyright © 2018 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the
>> "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>> OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> DEALINGS
>> + * IN THE SOFTWARE.
>> + */
>> +
>> +#include "nir.h"
>> +#include "nir_builder.h"
>> +
>> +static bool
>> +assert_ssa_def_is_not_1bit(nir_ssa_def *def, UNUSED void *unused)
>> +{
>> + assert(def->bit_size > 1);
>> + return true;
>> +}
>> +
>> +static bool
>> +rewrite_1bit_ssa_def_to_32bit(nir_ssa_def *def, void *_progress)
>> +{
>> + bool *progress = _progress;
>> + if (def->bit_size == 1) {
>> + def->bit_size = 32;
>> + *progress = true;
>> + }
>> + return true;
>> +}
>> +
>> +static bool
>> +lower_alu_instr(nir_builder *b, nir_alu_instr *alu)
>> +{
>> + const nir_op_info *op_info = _op_infos[alu->op];
>> +
>> + b->cursor = nir_before_instr(>instr);
>> +
>> + /* Replacement SSA value */
>> + nir_ssa_def *rep = NULL;
>> + switch (alu->op) {
>> + case nir_op_b2f: alu->op = nir_op_fmov; break;
>> + case nir_op_b2i: alu->op = nir_op_fmov; break;
>> + case nir_op_f2b:
>> + case nir_op_i2b:
>> + rep = nir_sne(b, nir_ssa_for_alu_src(b, alu, 0),
>> + nir_imm_float(b, 0));
>> + break;
>> +
>> + case nir_op_flt: alu->op = nir_op_slt; break;
>> + case nir_op_fge: alu->op = nir_op_sge; break;
>> + case nir_op_feq: alu->op = nir_op_seq; break;
>> + case nir_op_fne: alu->op = nir_op_sne; break;
>> + case nir_op_ilt: alu->op = nir_op_slt; break;
>> + case nir_op_ige: alu->op = nir_op_sge; break;
>> + case nir_op_ieq: alu->op = nir_op_seq; break;
>> + case nir_op_ine: alu->op = nir_op_sne; break;
>> + case nir_op_ult: alu->op = nir_op_slt; break;
>> + case nir_op_uge: alu->op = nir_op_sge; break;
>> +
>> + case nir_op_ball_fequal2: alu->op = nir_op_fall_equal2; break;
>> + case nir_op_ball_fequal3: alu->op = nir_op_fall_equal3; break;
>> + case nir_op_ball_fequal4: alu->op = nir_op_fall_equal4; break;
>> + case nir_op_bany_fnequal2: alu->op = nir_op_fany_nequal2; break;
>> + case nir_op_bany_fnequal3: alu->op = nir_op_fany_nequal3; break;
>> + case nir_op_bany_fnequal4: alu->op =
[Mesa-dev] [PATCH] docs/calendar: Add 18.3 plan and expand 18.2
CC: Emil Velikov CC: Juan A. Romero Suarez --- docs/release-calendar.html | 38 +- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/docs/release-calendar.html b/docs/release-calendar.html index a525c62..6bd4fc0c0e8 100644 --- a/docs/release-calendar.html +++ b/docs/release-calendar.html @@ -39,7 +39,7 @@ if you'd like to nominate a patch in the next stable release. Notes -18.2 +18.2 2018-10-31 18.2.4 Andres Gomez @@ -49,8 +49,44 @@ if you'd like to nominate a patch in the next stable release. 2018-11-14 18.2.5 Andres Gomez + + + +2018-11-28 +18.2.6 +Juan A. Suarez + + + +2018-12-12 +18.2.7 +Juan A. Suarez Last planned 18.2.x release +18.3 +2018-10-31 +18.2.0-rc1 +Dylan Baker + + + +2018-11-07 +18.2.0-rc2 +Dylan Baker + + + +2018-11-14 +18.2.0-rc3 +Dylan Baker + + + +2018-11-21 +18.2.0-rc4/ +Dylan Baker +Last planned RC/final release + -- 2.19.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] 18.3 release plan
Hi List, It's that time again, release time! We're a little late getting started, but here's the plan: Branch point/RC1: 10/31 RC2: 11/7 RC3: 11/14 RC4/final release: 11/21 With point releases following the normal two week period, this would also require adding two additional 18.2 releases: 18.2.6: 11/21 18.2.7: 12/05 I have gone ahead and created the 18.3 tracker bug, so please start adding any block bugs to that issue. I'll be sending out a patch to update the calendar accordingly shortly. You may note that this means you now have 8 days until the branch point to get last minute fixes into 18.3. I'd really like to do the branch point/RC1 on the 31st, as this will allow the stable releases to nicely leapfrog the US thanksgiving holiday and the Christmas holiday weeks. Dylan signature.asc Description: signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 108530] [Tracker] Mesa 18.3 Release Tracker
https://bugs.freedesktop.org/show_bug.cgi?id=108530 Dylan Baker changed: What|Removed |Added Depends on||107870 Referenced Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=107870 [Bug 107870] Undefined symbols for architecture x86_64: "_util_cpu_caps" -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 107870] Undefined symbols for architecture x86_64: "_util_cpu_caps"
https://bugs.freedesktop.org/show_bug.cgi?id=107870 Dylan Baker changed: What|Removed |Added Blocks|106157 |18530 Referenced Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=18530 [Bug 18530] Should implement IPv4 socket for file transfer https://bugs.freedesktop.org/show_bug.cgi?id=106157 [Bug 106157] [Tracker] Mesa 18.1 release tracker -- You are receiving this mail because: You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 107870] Undefined symbols for architecture x86_64: "_util_cpu_caps"
https://bugs.freedesktop.org/show_bug.cgi?id=107870 Dylan Baker changed: What|Removed |Added Blocks|18530 |108530 Referenced Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=18530 [Bug 18530] Should implement IPv4 socket for file transfer https://bugs.freedesktop.org/show_bug.cgi?id=108530 [Bug 108530] [Tracker] Mesa 18.3 Release Tracker -- You are receiving this mail because: You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 106157] [Tracker] Mesa 18.1 release tracker
https://bugs.freedesktop.org/show_bug.cgi?id=106157 Dylan Baker changed: What|Removed |Added Depends on|107870 | Referenced Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=107870 [Bug 107870] Undefined symbols for architecture x86_64: "_util_cpu_caps" -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 107870] Undefined symbols for architecture x86_64: "_util_cpu_caps"
https://bugs.freedesktop.org/show_bug.cgi?id=107870 Dylan Baker changed: What|Removed |Added Blocks||106157 Referenced Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=106157 [Bug 106157] [Tracker] Mesa 18.1 release tracker -- You are receiving this mail because: You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 106157] [Tracker] Mesa 18.1 release tracker
https://bugs.freedesktop.org/show_bug.cgi?id=106157 Dylan Baker changed: What|Removed |Added Depends on||107870 Referenced Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=107870 [Bug 107870] Undefined symbols for architecture x86_64: "_util_cpu_caps" -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 108530] [Tracker] Mesa 18.3 Release Tracker
https://bugs.freedesktop.org/show_bug.cgi?id=108530 Bug ID: 108530 Summary: [Tracker] Mesa 18.3 Release Tracker Product: Mesa Version: unspecified Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Other Assignee: mesa-dev@lists.freedesktop.org Reporter: baker.dyla...@gmail.com QA Contact: mesa-dev@lists.freedesktop.org This is a tracker for all regressions from 18.2 until 18.3 release. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 107457] [Tracker] Mesa 18.2 release tracker
https://bugs.freedesktop.org/show_bug.cgi?id=107457 Dylan Baker changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #2 from Dylan Baker --- Closing this as 18.2 has already been released. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 106157] [Tracker] Mesa 18.1 release tracker
https://bugs.freedesktop.org/show_bug.cgi?id=106157 Dylan Baker changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #5 from Dylan Baker --- 18.1 is EOL, no new bugs will be addressed. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 107502] Newest libdrm is required by amdgpu, but drm_intel error is emitted
https://bugs.freedesktop.org/show_bug.cgi?id=107502 Dylan Baker changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #3 from Dylan Baker --- I think this has been addressed, we now emit a message telling you which driver bumped the drm version. -- You are receiving this mail because: You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] docs: update calendar
Reviewed-by: Dylan Baker Quoting Juan A. Suarez Romero (2018-10-05 02:17:45) > I'll take care of 18.2 releases series on Andres behalf. > > CC: Andres Gomez > CC: Dylan Baker > CC: Emil Velikov > --- > docs/release-calendar.html | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/docs/release-calendar.html b/docs/release-calendar.html > index f92f7ba00fb..379d1a089e5 100644 > --- a/docs/release-calendar.html > +++ b/docs/release-calendar.html > @@ -42,25 +42,25 @@ if you'd like to nominate a patch in the next stable > release. > 18.2 > 2018-10-03 > 18.2.2 > -Andres Gomez > +Juan A. Suarez > > > > 2018-10-17 > 18.2.3 > -Andres Gomez > +Juan A. Suarez > > > > 2018-10-31 > 18.2.4 > -Andres Gomez > +Juan A. Suarez > > > > 2018-11-14 > 18.2.5 > -Andres Gomez > +Juan A. Suarez > Last planned 18.2.x release > > > -- > 2.17.1 > signature.asc Description: signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/3] radeon/vcn: use util function to get h264 profile idc
From: Boyuan Zhang
Use utility function for converting h264 pipe video profile to profile idc,
instead of using array.
Signed-off-by: Boyuan Zhang
---
src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 143721211db..a29c0a0150d 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -48,7 +48,6 @@ RADEON_ENC_CS(cmd)
#define RADEON_ENC_END() *begin = (>cs->current.buf[enc->cs->current.cdw]
- begin) * 4; \
enc->total_task_size += *begin;}
-static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
static void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer
*buf,
@@ -303,7 +302,7 @@ static void radeon_enc_spec_misc(struct radeon_encoder *enc)
enc->enc_pic.spec_misc.cabac_init_idc = 0;
enc->enc_pic.spec_misc.half_pel_enabled = 1;
enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
- enc->enc_pic.spec_misc.profile_idc = profiles[enc->base.profile -
PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE];
+ enc->enc_pic.spec_misc.profile_idc =
u_get_h264_profile_idc(enc->base.profile);
enc->enc_pic.spec_misc.level_idc = enc->base.level;
RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_SPEC_MISC);
--
2.17.1
___
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mesa-dev@lists.freedesktop.org
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[Mesa-dev] [PATCH 2/3] radeon/vce: use util function to get h264 profile idc
From: Boyuan Zhang
Use utility function for converting h264 pipe video profile to profile idc,
instead of using array.
Signed-off-by: Boyuan Zhang
---
src/gallium/drivers/radeon/radeon_vce_40_2_2.c | 5 +
src/gallium/drivers/radeon/radeon_vce_52.c | 5 +
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
index 66b54dab25a..e17468c9097 100644
--- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
@@ -38,8 +38,6 @@
#include "radeon_video.h"
#include "radeon_vce.h"
-static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
-
static void session(struct rvce_encoder *enc)
{
RVCE_BEGIN(0x0001); // session cmd
@@ -82,8 +80,7 @@ static void create(struct rvce_encoder *enc)
RVCE_BEGIN(0x0101); // create cmd
RVCE_CS(0x); // encUseCircularBuffer
- RVCE_CS(profiles[enc->base.profile -
- PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE]); // encProfile
+ RVCE_CS(u_get_h264_profile_idc(enc->base.profile)); // encProfile
RVCE_CS(enc->base.level); // encLevel
RVCE_CS(0x); // encPicStructRestriction
RVCE_CS(enc->base.width); // encImageWidth
diff --git a/src/gallium/drivers/radeon/radeon_vce_52.c
b/src/gallium/drivers/radeon/radeon_vce_52.c
index 421539c4bdc..fc7ddc62a90 100644
--- a/src/gallium/drivers/radeon/radeon_vce_52.c
+++ b/src/gallium/drivers/radeon/radeon_vce_52.c
@@ -38,8 +38,6 @@
#include "radeon_video.h"
#include "radeon_vce.h"
-static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
-
static void get_rate_control_param(struct rvce_encoder *enc, struct
pipe_h264_enc_picture_desc *pic)
{
enc->enc_pic.rc.rc_method = pic->rate_ctrl.rate_ctrl_method;
@@ -172,8 +170,7 @@ static void create(struct rvce_encoder *enc)
RVCE_BEGIN(0x0101); // create cmd
RVCE_CS(enc->enc_pic.ec.enc_use_circular_buffer);
- RVCE_CS(profiles[enc->base.profile -
- PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE]); // encProfile
+ RVCE_CS(u_get_h264_profile_idc(enc->base.profile)); // encProfile
RVCE_CS(enc->base.level); // encLevel
RVCE_CS(enc->enc_pic.ec.enc_pic_struct_restriction);
RVCE_CS(enc->base.width); // encImageWidth
--
2.17.1
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[Mesa-dev] [PATCH 1/3] vl: get h264 profile idc
From: Boyuan Zhang
Adding a function for converting h264 pipe video profile to profile idc
Signed-off-by: Boyuan Zhang
---
src/gallium/auxiliary/util/u_video.h | 24
1 file changed, 24 insertions(+)
diff --git a/src/gallium/auxiliary/util/u_video.h
b/src/gallium/auxiliary/util/u_video.h
index 967ebc57489..f6e93dd0387 100644
--- a/src/gallium/auxiliary/util/u_video.h
+++ b/src/gallium/auxiliary/util/u_video.h
@@ -239,6 +239,30 @@ u_get_h264_level(uint32_t width, uint32_t height, uint32_t
*max_reference)
return 52;
}
+static inline uint32_t
+u_get_h264_profile_idc(enum pipe_video_profile profile)
+{
+ switch (profile) {
+ case PIPE_VIDEO_PROFILE_MPEG4_AVC_CONSTRAINED_BASELINE:
+ case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
+ return 66;
+ case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
+ return 77;
+ case PIPE_VIDEO_PROFILE_MPEG4_AVC_EXTENDED:
+ return 88;
+ case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
+ return 100;
+ case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH10:
+ return 110;
+ case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH422:
+ return 122;
+ case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH444:
+ return 244;
+ default:
+ return 66; //use baseline profile instead
+ }
+}
+
#ifdef __cplusplus
}
#endif
--
2.17.1
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Re: [Mesa-dev] [PATCH 13/15] amd/common: add vcn jpeg ip info query
Hi,
With this commit, both radeonsi and radv fail to load for me with:
amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.
If I comment out that query in ac_gpu_info.c, then they work again. I'm
running kernel 4.18.7 with a Vega 64 - is the DRM version check on that
correct?
Thanks,
Alex
On Wed, 17 Oct 2018 at 20:06, wrote:
> From: Boyuan Zhang
>
> Signed-off-by: Boyuan Zhang
> Reviewed-by: Leo Liu
> ---
> src/amd/common/ac_gpu_info.c | 14 --
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
> index 766ad83547..8c50738c3f 100644
> --- a/src/amd/common/ac_gpu_info.c
> +++ b/src/amd/common/ac_gpu_info.c
> @@ -99,7 +99,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
> struct drm_amdgpu_info_device device_info = {};
> struct amdgpu_buffer_size_alignments alignment_info = {};
> struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
> - struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
> + struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {},
> vcn_jpeg = {};
> struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
> struct amdgpu_gds_resource_info gds = {};
> uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0,
> uvd_feature = 0;
> @@ -186,6 +186,14 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle
> dev,
> }
> }
>
> + if (info->drm_major == 3 && info->drm_minor >= 17) {
> + r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0,
> _jpeg);
> + if (r) {
> + fprintf(stderr, "amdgpu:
> amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
> + return false;
> + }
> + }
> +
> r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
> >me_fw_version,
> >me_fw_feature);
> @@ -340,7 +348,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle
> dev,
> info->max_se = amdinfo->num_shader_engines;
> info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
> info->has_hw_decode =
> - (uvd.available_rings != 0) || (vcn_dec.available_rings !=
> 0);
> + (uvd.available_rings != 0) || (vcn_dec.available_rings !=
> 0) ||
> + (vcn_jpeg.available_rings != 0);
> info->uvd_fw_version =
> uvd.available_rings ? uvd_version : 0;
> info->vce_fw_version =
> @@ -439,6 +448,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle
> dev,
> ib_align = MAX2(ib_align, vce.ib_start_alignment);
> ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
> ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
> + ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
> assert(ib_align);
> info->ib_start_alignment = ib_align;
>
> --
> 2.17.1
>
> ___
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>
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[Mesa-dev] [PATCH v7 5/5] radeonsi: Enable adaptive_sync by default for radeon
It's better to let most applications make use of adaptive sync
by default. Problematic applications can be placed on the blacklist
or the user can manually disable the feature.
Signed-off-by: Nicholas Kazlauskas
---
src/gallium/drivers/radeonsi/driinfo_radeonsi.h | 4
1 file changed, 4 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
index 8c5078c13f..cbf3bb01fb 100644
--- a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
+++ b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
@@ -1,4 +1,8 @@
// DriConf options specific to radeonsi
+DRI_CONF_SECTION_QUALITY
+DRI_CONF_ADAPTIVE_SYNC("true")
+DRI_CONF_SECTION_END
+
DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_RADEONSI_ENABLE_SISCHED("false")
DRI_CONF_RADEONSI_ASSUME_NO_Z_FIGHTS("false")
--
2.19.1
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[Mesa-dev] [PATCH v7 4/5] loader/dri3: Enable adaptive_sync via _VARIABLE_REFRESH property
The DDX driver can be notified of adaptive sync suitability by
flagging the application's window with the _VARIABLE_REFRESH property.
This property is set on the first swap the application performs
when adaptive_sync is set to true in the drirc.
It's performed here instead of when the loader is initialized for
two reasons:
(1) The window's drawable can be missing during loader init.
This can be observed during the Unigine Superposition benchmark.
(2) Adaptive sync will only be enabled closer to when the application
actually begins rendering.
If adaptive_sync is false then the _VARIABLE_REFRESH property
is deleted on loader init.
The property is only managed on the glx DRI3 backend for now. This
should cover most common applications and games on modern hardware.
Vulkan support can be implemented in a similar manner but would likely
require splitting the function out into a common helper function.
Signed-off-by: Nicholas Kazlauskas
---
src/loader/loader_dri3_helper.c | 48 -
src/loader/loader_dri3_helper.h | 2 ++
2 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/src/loader/loader_dri3_helper.c b/src/loader/loader_dri3_helper.c
index 1981b5f051..e5a6e2a9a1 100644
--- a/src/loader/loader_dri3_helper.c
+++ b/src/loader/loader_dri3_helper.c
@@ -101,6 +101,32 @@ get_xcb_visualtype_for_depth(struct loader_dri3_drawable
*draw, int depth)
return NULL;
}
+/* Sets the adaptive sync window property state. */
+static void
+set_adaptive_sync_property(xcb_connection_t *conn, xcb_drawable_t drawable,
+ uint32_t state)
+{
+ static char const name[] = "_VARIABLE_REFRESH";
+ xcb_intern_atom_cookie_t cookie;
+ xcb_intern_atom_reply_t* reply;
+ xcb_void_cookie_t check;
+
+ cookie = xcb_intern_atom(conn, 0, sizeof(name), name);
+ reply = xcb_intern_atom_reply(conn, cookie, NULL);
+ if (reply == NULL)
+ return;
+
+ if (state)
+ check = xcb_change_property_checked(conn, XCB_PROP_MODE_REPLACE,
+ drawable, reply->atom,
+ XCB_ATOM_CARDINAL, 32, 1, );
+ else
+ check = xcb_delete_property_checked(conn, drawable, reply->atom);
+
+ xcb_discard_reply(conn, check.sequence);
+ free(reply);
+}
+
/* Get red channel mask for given drawable at given depth. */
static unsigned int
dri3_get_red_mask_for_depth(struct loader_dri3_drawable *draw, int depth)
@@ -331,16 +357,30 @@ loader_dri3_drawable_init(xcb_connection_t *conn,
draw->have_back = 0;
draw->have_fake_front = 0;
draw->first_init = true;
+ draw->adaptive_sync = false;
+ draw->adaptive_sync_active = false;
draw->cur_blit_source = -1;
draw->back_format = __DRI_IMAGE_FORMAT_NONE;
mtx_init(>mtx, mtx_plain);
cnd_init(>event_cnd);
- if (draw->ext->config)
+ if (draw->ext->config) {
+ unsigned char adaptive_sync;
+
draw->ext->config->configQueryi(draw->dri_screen,
"vblank_mode", _mode);
+ draw->ext->config->configQueryb(draw->dri_screen,
+ "adaptive_sync",
+ _sync);
+
+ draw->adaptive_sync = adaptive_sync;
+ }
+
+ if (!draw->adaptive_sync)
+ set_adaptive_sync_property(conn, draw->drawable, false);
+
switch (vblank_mode) {
case DRI_CONF_VBLANK_NEVER:
case DRI_CONF_VBLANK_DEF_INTERVAL_0:
@@ -879,6 +919,12 @@ loader_dri3_swap_buffers_msc(struct loader_dri3_drawable
*draw,
back = dri3_find_back_alloc(draw);
mtx_lock(>mtx);
+
+ if (draw->adaptive_sync && !draw->adaptive_sync_active) {
+ set_adaptive_sync_property(draw->conn, draw->drawable, true);
+ draw->adaptive_sync_active = true;
+ }
+
if (draw->is_different_gpu && back) {
/* Update the linear buffer before presenting the pixmap */
(void) loader_dri3_blit_image(draw,
diff --git a/src/loader/loader_dri3_helper.h b/src/loader/loader_dri3_helper.h
index 0d18181312..663ce3c0e2 100644
--- a/src/loader/loader_dri3_helper.h
+++ b/src/loader/loader_dri3_helper.h
@@ -156,6 +156,8 @@ struct loader_dri3_drawable {
xcb_special_event_t *special_event;
bool first_init;
+ bool adaptive_sync;
+ bool adaptive_sync_active;
int swap_interval;
struct loader_dri3_extensions *ext;
--
2.19.1
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[Mesa-dev] [PATCH v7 2/5] util: Add adaptive_sync driconf option
This option lets the user decide whether mesa should notify the
window manager / DDX driver that the current application is adaptive
sync capable.
It's off by default.
Signed-off-by: Nicholas Kazlauskas
---
src/util/xmlpool/t_options.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index e0a30f5fd1..80ddf0e203 100644
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -210,6 +210,11 @@ DRI_CONF_OPT_BEGIN_V(vblank_mode,enum,def,"0:3") \
DRI_CONF_DESC_END \
DRI_CONF_OPT_END
+#define DRI_CONF_ADAPTIVE_SYNC(def) \
+DRI_CONF_OPT_BEGIN_B(adaptive_sync,def) \
+DRI_CONF_DESC(en,gettext("Adapt the monitor sync to the application
performance (when possible)")) \
+DRI_CONF_OPT_END
+
#define DRI_CONF_MESA_GLTHREAD(def) \
DRI_CONF_OPT_BEGIN_B(mesa_glthread, def) \
DRI_CONF_DESC(en,gettext("Enable offloading GL driver work to a
separate thread")) \
--
2.19.1
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[Mesa-dev] [PATCH v7 3/5] drirc: Initial blacklist for adaptive sync
Applications that don't present at a predictable rate (ie. not games) shouldn't have adapative sync enabled. This list covers some of the common desktop compositors, web browsers and video players. Signed-off-by: Nicholas Kazlauskas --- src/util/00-mesa-defaults.conf | 82 ++ 1 file changed, 82 insertions(+) diff --git a/src/util/00-mesa-defaults.conf b/src/util/00-mesa-defaults.conf index a937c46d05..8e9a87d603 100644 --- a/src/util/00-mesa-defaults.conf +++ b/src/util/00-mesa-defaults.conf @@ -21,6 +21,8 @@ Application bugs worked around in this file: built-ins (specifically gl_VertexID), which causes the vertex shaders to fail to compile. +* Applications that are not suitable for adapative sync are blacklisted here. + TODO: document the other workarounds. --> @@ -314,6 +316,86 @@ TODO: document the other workarounds. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- 2.19.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v7 1/5] util: Get program name based on path when possible
Some programs start with the path and command line arguments in
argv[0] (program_invocation_name). Chromium is an example of
an application using mesa that does this.
This tries to query the real path for the symbolic link /proc/self/exe
to find the program name instead. It only uses the realpath if it
was a prefix of the invocation to avoid breaking wine programs.
Cc: Timothy Arceri
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Eric Engestrom
---
src/util/u_process.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/src/util/u_process.c b/src/util/u_process.c
index 5e5927678d..a1667e7807 100644
--- a/src/util/u_process.c
+++ b/src/util/u_process.c
@@ -41,8 +41,29 @@ static const char *
__getProgramName()
{
char * arg = strrchr(program_invocation_name, '/');
- if (arg)
+ if (arg) {
+ /* If the / character was found this is likely a linux path or
+ * an invocation path for a 64-bit wine program.
+ *
+ * However, some programs pass command line arguments into argv[0].
+ * Strip these arguments out by using the realpath only if it was
+ * a prefix of the invocation name.
+ */
+ static char *path;
+
+ if (!path)
+ path = realpath("/proc/self/exe", NULL);
+
+ if (path && strncmp(path, program_invocation_name, strlen(path)) == 0) {
+ /* This shouldn't be null because path is a a prefix,
+ * but check it anyway since path is static. */
+ char * name = strrchr(path, '/');
+ if (name)
+return name + 1;
+ }
+
return arg+1;
+ }
/* If there was no '/' at all we likely have a windows like path from
* a wine application.
--
2.19.1
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[Mesa-dev] [PATCH v7 0/5] Mesa integration for DRM variable refresh rate API
These patches are part of a proposed new interface for supporting variable refresh rate via DRM properties. It adds a new option for supporting adaptive sync to drirc along with the implementation of notifying the window manager/DDX of the support via a window property. The option is enabled by default for radeonsi so included is an initial blacklist of applications that shouldn't have this option enabled. Program name detection needed an additional patch to work for a few of the applications on the initial blacklist. === Changes from v6 === * Fixed unitialized variable use in loader patch === Changes from v5 === * Variable refresh property is now deleted when draw->ext->config is NULL === Changes from v4 === * "adaptive_sync_enable" shortened to now "adaptive_sync" * Reordered patches for more logical bisection * Replaced suspicious pointer arithmetic in get program name path to better clarify intent * Errors are now discarded when setting/destroying variable refresh property * Updated formatting in dri3 loader patch === Changes from v3 === * Blacklist updated to include more desktop environments * Variable refresh property is now deleted when adaptive_sync_enable is false during loader init - this should resolve a potential issue with reusing windows with blacklisted applications. === Changes from v2 === * A patch to add the option to the drirc was missing from the v2 patchset. That patch is now included in v3. * The method to fix program name detection for Chromium based applications for the drirc was modified to not break detection for 32-bit/64-bit WINE applications. === Adaptive sync and variable refresh rate === Adaptive sync is part of the DisplayPort specification and allows for graphics adapters to drive displays with varying frame timings. Variable refresh rate (VRR) is essentially the same, but defined for HDMI. === Use cases for variable refresh rate === Variable frame (flip) timings don't align well with fixed refresh rate displays. This results in stuttering, tearing and/or input lag. By adjusting the display refresh rate dynamically these issues can be reduced or eliminated. However, not all content is suitable for dynamic refresh adaptation. The user may experience "flickering" from differences in panel luminance at different refresh rates. Content that flips at an infrequent rate or demand is more likely to cause large changes in refresh rate that result in flickering. Userland needs a way to let the driver know when the screen content is suitable for variable refresh rates. === DRM API to support variable refresh rates === This patch introduces a new API via atomic properties on the DRM connector and CRTC. The drm_connector has one new optional boolean property: * bool vrr_capable - set by the driver if the hardware is capable of supporting variable refresh rates The drm_crtc has one new default boolean property: * bool vrr_enabled - set by userspace indicating that variable refresh rate should be enabled == Overview for DRM driver developers === Driver developers can attach the "vrr_capable" property by calling drm_connector_attach_vrr_capable_property(). This should be done on connectors that could be capable of supporting variable refresh rates (such as DP or HDMI). The "vrr_capable" can then be updated accordingly by calling drm_connector_set_vrr_capable_property(). The "vrr_enabled" property can be checked from the drm_crtc_state object. === Overview for Userland developers == The "vrr_enabled" property on the CRTC should be set to true when the CRTC is suitable for variable refresh rates. To demonstrate the suitability of the API for variable refresh and dynamic adaptation there are additional patches using this API that implement adaptive variable refresh across kernel and userland projects: * DRM (dri-devel) * amdgpu DRM kernel driver (amd-gfx) * xf86-video-amdgpu (https://gitlab.freedesktop.org/xorg/driver/xf86-video-amdgpu) * mesa (mesa-dev) These patches enable adaptive variable refresh on X for AMD hardware. Support for variable refresh is disabled by default in xf86-video-amdgpu and will require additional user configuration. The patches have been tested as working on upstream userland with the GNOME desktop environment under a single monitor setup. They also work on KDE in a single monitor setup with the compositor disabled. The patches require that suitable applications flip via the Present extension to xf86-video-amdgpu for the entire Screen. Some compositors may interfere with this if they are unable to unredirect the window. Full implementation details for these changes can be reviewed in their respective mailing lists and the xf86-video-amdgpu GitLab. === Previous discussions === These patches are based upon feedback from previous threads on the subject. These are linked below for reference: https://lists.freedesktop.org/archives/amd-gfx/2018-April/021047.html
Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
On Tue, Oct 23, 2018 at 12:16 AM Jason Ekstrand wrote:
>
> This should be useful for drivers that don't support real integers.
>
> Cc: Alyssa Rosenzweig
> ---
> src/compiler/Makefile.sources | 1 +
> src/compiler/nir/meson.build | 1 +
> src/compiler/nir/nir_lower_bool_to_float.c | 181 +
> 3 files changed, 183 insertions(+)
> create mode 100644 src/compiler/nir/nir_lower_bool_to_float.c
>
> diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
> index 8f65f974ab8..2ff12ff43cb 100644
> --- a/src/compiler/Makefile.sources
> +++ b/src/compiler/Makefile.sources
> @@ -230,6 +230,7 @@ NIR_FILES = \
> nir/nir_lower_atomics_to_ssbo.c \
> nir/nir_lower_bitmap.c \
> nir/nir_lower_bit_size.c \
> + nir/nir_lower_bool_to_float.c \
> nir/nir_lower_bool_to_int32.c \
> nir/nir_lower_clamp_color_outputs.c \
> nir/nir_lower_clip.c \
> diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
> index 5809551c9d4..f715668a03b 100644
> --- a/src/compiler/nir/meson.build
> +++ b/src/compiler/nir/meson.build
> @@ -113,6 +113,7 @@ files_libnir = files(
>'nir_lower_alpha_test.c',
>'nir_lower_atomics_to_ssbo.c',
>'nir_lower_bitmap.c',
> + 'nir_lower_bool_to_float.c',
>'nir_lower_bool_to_int32.c',
>'nir_lower_clamp_color_outputs.c',
>'nir_lower_clip.c',
> diff --git a/src/compiler/nir/nir_lower_bool_to_float.c
> b/src/compiler/nir/nir_lower_bool_to_float.c
> new file mode 100644
> index 000..7aa5efb5a2f
> --- /dev/null
> +++ b/src/compiler/nir/nir_lower_bool_to_float.c
> @@ -0,0 +1,181 @@
> +/*
> + * Copyright © 2018 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "nir.h"
> +#include "nir_builder.h"
> +
> +static bool
> +assert_ssa_def_is_not_1bit(nir_ssa_def *def, UNUSED void *unused)
> +{
> + assert(def->bit_size > 1);
> + return true;
> +}
> +
> +static bool
> +rewrite_1bit_ssa_def_to_32bit(nir_ssa_def *def, void *_progress)
> +{
> + bool *progress = _progress;
> + if (def->bit_size == 1) {
> + def->bit_size = 32;
> + *progress = true;
> + }
> + return true;
> +}
> +
> +static bool
> +lower_alu_instr(nir_builder *b, nir_alu_instr *alu)
> +{
> + const nir_op_info *op_info = _op_infos[alu->op];
> +
> + b->cursor = nir_before_instr(>instr);
> +
> + /* Replacement SSA value */
> + nir_ssa_def *rep = NULL;
> + switch (alu->op) {
> + case nir_op_b2f: alu->op = nir_op_fmov; break;
> + case nir_op_b2i: alu->op = nir_op_fmov; break;
> + case nir_op_f2b:
> + case nir_op_i2b:
> + rep = nir_sne(b, nir_ssa_for_alu_src(b, alu, 0),
> + nir_imm_float(b, 0));
> + break;
> +
> + case nir_op_flt: alu->op = nir_op_slt; break;
> + case nir_op_fge: alu->op = nir_op_sge; break;
> + case nir_op_feq: alu->op = nir_op_seq; break;
> + case nir_op_fne: alu->op = nir_op_sne; break;
> + case nir_op_ilt: alu->op = nir_op_slt; break;
> + case nir_op_ige: alu->op = nir_op_sge; break;
> + case nir_op_ieq: alu->op = nir_op_seq; break;
> + case nir_op_ine: alu->op = nir_op_sne; break;
> + case nir_op_ult: alu->op = nir_op_slt; break;
> + case nir_op_uge: alu->op = nir_op_sge; break;
> +
> + case nir_op_ball_fequal2: alu->op = nir_op_fall_equal2; break;
> + case nir_op_ball_fequal3: alu->op = nir_op_fall_equal3; break;
> + case nir_op_ball_fequal4: alu->op = nir_op_fall_equal4; break;
> + case nir_op_bany_fnequal2: alu->op = nir_op_fany_nequal2; break;
> + case nir_op_bany_fnequal3: alu->op = nir_op_fany_nequal3; break;
> + case nir_op_bany_fnequal4: alu->op = nir_op_fany_nequal4; break;
> + case nir_op_ball_iequal2: alu->op = nir_op_fall_equal2; break;
> + case nir_op_ball_iequal3: alu->op = nir_op_fall_equal3; break;
> + case
[Mesa-dev] [PATCH v2] anv: Allow presenting via a different GPU
anv_GetPhysicalDeviceSurfaceSupportKHR will already return success for
this, but anv_GetPhysicalDevice{Xcb,Xlib}PresentationSupportKHR do not.
Apps which check for presentation support via the latter (all Feral
Vulkan games at least) will therefore fail.
This allows me to render on an Intel GPU and present to a display
connected to an AMD card (tested HD 530 + Vega 64).
v2: Rebase on current master.
Signed-off-by: Alex Smith
---
src/intel/vulkan/anv_wsi_x11.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/vulkan/anv_wsi_x11.c b/src/intel/vulkan/anv_wsi_x11.c
index bfa76e88e7..7a27ceab64 100644
--- a/src/intel/vulkan/anv_wsi_x11.c
+++ b/src/intel/vulkan/anv_wsi_x11.c
@@ -41,7 +41,7 @@ VkBool32 anv_GetPhysicalDeviceXcbPresentationSupportKHR(
return wsi_get_physical_device_xcb_presentation_support(
>wsi_device,
queueFamilyIndex,
- false,
+ true,
connection, visual_id);
}
@@ -56,7 +56,7 @@ VkBool32 anv_GetPhysicalDeviceXlibPresentationSupportKHR(
return wsi_get_physical_device_xcb_presentation_support(
>wsi_device,
queueFamilyIndex,
- false,
+ true,
XGetXCBConnection(dpy), visualID);
}
--
2.14.4
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Re: [Mesa-dev] [PATCH mesa] anv: move variable to proper scope and mark as MAYBE_UNUSED
Reviewed-by: Lionel Landwerlin
On 23/10/2018 15:37, Eric Engestrom wrote:
Signed-off-by: Eric Engestrom
---
src/intel/vulkan/anv_queue.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/intel/vulkan/anv_queue.c b/src/intel/vulkan/anv_queue.c
index db89385b86644417d47a..05739cb26df571c5f4db 100644
--- a/src/intel/vulkan/anv_queue.c
+++ b/src/intel/vulkan/anv_queue.c
@@ -542,8 +542,6 @@ anv_wait_for_bo_fences(struct anv_device *device,
bool waitAll,
uint64_t _timeout)
{
- int ret;
-
/* DRM_IOCTL_I915_GEM_WAIT uses a signed 64 bit timeout and is supposed
* to block indefinitely timeouts <= 0. Unfortunately, this was broken
* for a couple of kernel releases. Since there's no way to know
@@ -647,6 +645,7 @@ anv_wait_for_bo_fences(struct anv_device *device,
abstime.tv_nsec = abs_nsec;
abstime.tv_sec = MIN2(abs_sec, INT_TYPE_MAX(abstime.tv_sec));
+MAYBE_UNUSED int ret;
ret = pthread_cond_timedwait(>queue_submit,
>mutex, );
assert(ret != EINVAL);
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Re: [Mesa-dev] [PATCH mesa] anv: use snprintf() instead of memset()+strcpy()
Reviewed-by: Lionel Landwerlin
On 23/10/2018 15:31, Eric Engestrom wrote:
snprintf() guarantees that it will not write more chars than allowed,
and that the string will be null-terminated, without the need to fill
the whole thing with zeroes to begin with.
Signed-off-by: Eric Engestrom
---
src/intel/vulkan/anv_device.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index c009176dcc6c605e2e41..3ac1bad93ed8713b0da5 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -37,6 +37,7 @@
#include "util/build_id.h"
#include "util/disk_cache.h"
#include "util/mesa-sha1.h"
+#include "util/u_string.h"
#include "git_sha1.h"
#include "vk_util.h"
#include "common/gen_defines.h"
@@ -1135,12 +1136,10 @@ void anv_GetPhysicalDeviceProperties2(
(VkPhysicalDeviceDriverPropertiesKHR *) ext;
driver_props->driverID = VK_DRIVER_ID_INTEL_OPEN_SOURCE_MESA_KHR;
- memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
- strcpy(driver_props->driverName,
+ util_snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR,
"Intel open-source Mesa driver");
- memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
- strcpy(driver_props->driverInfo,
+ util_snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
"Mesa " PACKAGE_VERSION MESA_GIT_SHA1);
driver_props->conformanceVersion = (VkConformanceVersionKHR) {
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Re: [Mesa-dev] [PATCH mesa] anv: wrap API errors in vk_error()
I think there are a few cases below where your change "over reports"
meaning reporting the same error that has been signaled previously
(device lost in particular).
And cases where the application is just giving a wrong value, I might be
wrong but I don't think we should report those ones either.
Cheers,
-
Lionel
On 23/10/2018 15:34, Eric Engestrom wrote:
Signed-off-by: Eric Engestrom
---
src/intel/vulkan/anv_android.c | 2 +-
src/intel/vulkan/anv_device.c | 10 +-
src/intel/vulkan/anv_formats.c | 2 +-
src/intel/vulkan/anv_image.c | 2 +-
src/intel/vulkan/anv_queue.c | 6 +++---
src/intel/vulkan/anv_wsi_display.c | 2 +-
6 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/src/intel/vulkan/anv_android.c b/src/intel/vulkan/anv_android.c
index 46c41d57861f18f48275..1334cbbc13814893b3b6 100644
--- a/src/intel/vulkan/anv_android.c
+++ b/src/intel/vulkan/anv_android.c
@@ -314,7 +314,7 @@ VkResult anv_GetSwapchainGrallocUsageANDROID(
}
if (*grallocUsage == 0)
- return VK_ERROR_FORMAT_NOT_SUPPORTED;
+ return vk_error(VK_ERROR_FORMAT_NOT_SUPPORTED);
Looks like an application error. I don't think we should report it.
return VK_SUCCESS;
}
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 3ac1bad93ed8713b0da5..211991d6874d52c10ff3 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -2133,7 +2133,7 @@ VkResult anv_DeviceWaitIdle(
{
ANV_FROM_HANDLE(anv_device, device, _device);
if (unlikely(device->lost))
- return VK_ERROR_DEVICE_LOST;
+ return vk_error(VK_ERROR_DEVICE_LOST);
Drop this one, the error should have been reported earlier.
struct anv_batch batch;
@@ -2236,7 +2236,7 @@ VkResult anv_AllocateMemory(
assert(pAllocateInfo->allocationSize > 0);
if (pAllocateInfo->allocationSize > MAX_MEMORY_ALLOCATION_SIZE)
- return VK_ERROR_OUT_OF_DEVICE_MEMORY;
+ return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
Somewhat not sure here. It's the application asking for a value we
report is above the maximum.
Not really a driver error.
/* FINISHME: Fail if allocation request exceeds heap size. */
@@ -2807,7 +2807,7 @@ VkResult anv_QueueBindSparse(
{
ANV_FROM_HANDLE(anv_queue, queue, _queue);
if (unlikely(queue->device->lost))
- return VK_ERROR_DEVICE_LOST;
+ return vk_error(VK_ERROR_DEVICE_LOST);
Drop this one, the error should have been reported earlier.
return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
}
@@ -2865,7 +2865,7 @@ VkResult anv_GetEventStatus(
ANV_FROM_HANDLE(anv_event, event, _event);
if (unlikely(device->lost))
- return VK_ERROR_DEVICE_LOST;
+ return vk_error(VK_ERROR_DEVICE_LOST);
Drop this one, the error should have been reported earlier.
if (!device->info.has_llc) {
/* Invalidate read cache before reading event written by GPU. */
@@ -3095,7 +3095,7 @@ VkResult anv_GetCalibratedTimestampsEXT(
if (ret != 0) {
device->lost = TRUE;
-return VK_ERROR_DEVICE_LOST;
+return vk_error(VK_ERROR_DEVICE_LOST);
}
uint64_t device_period = DIV_ROUND_UP(10,
timestamp_frequency);
max_clock_period = MAX2(max_clock_period, device_period);
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 9199567f4454ae6df653..cd1ca9f7b8378a3b24ed 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -907,7 +907,7 @@ anv_get_image_format_properties(
.maxResourceSize = 0,
};
- return VK_ERROR_FORMAT_NOT_SUPPORTED;
+ return vk_error(VK_ERROR_FORMAT_NOT_SUPPORTED);
}
I don't think this is an error, just reporting that the particular
format/tiling/etc... is not supported
VkResult anv_GetPhysicalDeviceImageFormatProperties(
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index e89ce012be7c31f2410a..3e462a3e5739e32b4535 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -355,7 +355,7 @@ make_surface(const struct anv_device *dev,
.tiling_flags = tiling_flags);
if (!ok)
- return VK_ERROR_OUT_OF_DEVICE_MEMORY;
+ return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
image->planes[plane].aux_usage = ISL_AUX_USAGE_NONE;
diff --git a/src/intel/vulkan/anv_queue.c b/src/intel/vulkan/anv_queue.c
index e0c0a42069f1e52dafeb..db89385b86644417d47a 100644
--- a/src/intel/vulkan/anv_queue.c
+++ b/src/intel/vulkan/anv_queue.c
@@ -399,7 +399,7 @@ VkResult anv_GetFenceStatus(
ANV_FROM_HANDLE(anv_fence, fence, _fence);
if (unlikely(device->lost))
- return VK_ERROR_DEVICE_LOST;
+ return vk_error(VK_ERROR_DEVICE_LOST);
struct anv_fence_impl *impl =
fence->temporary.type != ANV_FENCE_TYPE_NONE ?
@@ -672,7 +672,7 @@
Re: [Mesa-dev] [PATCH v2] nir: fix nir_copy_propagation test
On 2018-10-23 4:55 p.m., Juan A. Suarez Romero wrote:
> Use nir_src_comp_as_uint() to read the proper second component, as
> nir_src_as_uint() returns the first one.
>
> v2: Use nir_src_comp_as_uint() [Jason]
>
> Fixes: 16870de8a0a ("nir: Use nir_src_is_const and nir_src_as_* in core
> code")
> Signed-off-by: Juan A. Suarez Romero
> ---
> src/compiler/nir/tests/vars_tests.cpp | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/compiler/nir/tests/vars_tests.cpp
> b/src/compiler/nir/tests/vars_tests.cpp
> index 02c53804b84..a7bbeb02277 100644
> --- a/src/compiler/nir/tests/vars_tests.cpp
> +++ b/src/compiler/nir/tests/vars_tests.cpp
> @@ -375,7 +375,7 @@ TEST_F(nir_copy_prop_vars_test,
> store_store_load_different_components)
> ASSERT_TRUE(store_to_v1->src[1].is_ssa);
>
> ASSERT_TRUE(nir_src_is_const(store_to_v1->src[1]));
> - ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 20);
> + ASSERT_EQ(nir_src_comp_as_uint(store_to_v1->src[1], 1), 20);
> break;
>}
> }
> @@ -424,7 +424,7 @@ TEST_F(nir_copy_prop_vars_test,
> store_store_load_different_components_in_many_bl
> ASSERT_TRUE(store_to_v1->src[1].is_ssa);
>
> ASSERT_TRUE(nir_src_is_const(store_to_v1->src[1]));
> - ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 20);
> + ASSERT_EQ(nir_src_comp_as_uint(store_to_v1->src[1], 1), 20);
> break;
>}
> }
>
Thanks Juan!
Tested-by: Michel Dänzer
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa and X developer
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[Mesa-dev] [PATCH v2] nir: fix nir_copy_propagation test
Use nir_src_comp_as_uint() to read the proper second component, as
nir_src_as_uint() returns the first one.
v2: Use nir_src_comp_as_uint() [Jason]
Fixes: 16870de8a0a ("nir: Use nir_src_is_const and nir_src_as_* in core
code")
Signed-off-by: Juan A. Suarez Romero
---
src/compiler/nir/tests/vars_tests.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/compiler/nir/tests/vars_tests.cpp
b/src/compiler/nir/tests/vars_tests.cpp
index 02c53804b84..a7bbeb02277 100644
--- a/src/compiler/nir/tests/vars_tests.cpp
+++ b/src/compiler/nir/tests/vars_tests.cpp
@@ -375,7 +375,7 @@ TEST_F(nir_copy_prop_vars_test,
store_store_load_different_components)
ASSERT_TRUE(store_to_v1->src[1].is_ssa);
ASSERT_TRUE(nir_src_is_const(store_to_v1->src[1]));
- ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 20);
+ ASSERT_EQ(nir_src_comp_as_uint(store_to_v1->src[1], 1), 20);
break;
}
}
@@ -424,7 +424,7 @@ TEST_F(nir_copy_prop_vars_test,
store_store_load_different_components_in_many_bl
ASSERT_TRUE(store_to_v1->src[1].is_ssa);
ASSERT_TRUE(nir_src_is_const(store_to_v1->src[1]));
- ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 20);
+ ASSERT_EQ(nir_src_comp_as_uint(store_to_v1->src[1], 1), 20);
break;
}
}
--
2.17.2
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Re: [Mesa-dev] [PATCH mesa] anv: drop unused includes
Reviewed-by: Lionel Landwerlin On 23/10/2018 15:25, Eric Engestrom wrote: Signed-off-by: Eric Engestrom --- src/intel/vulkan/anv_wsi_wayland.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/intel/vulkan/anv_wsi_wayland.c b/src/intel/vulkan/anv_wsi_wayland.c index 3aeb1994110c563456cd..26383f42387ea28af0b5 100644 --- a/src/intel/vulkan/anv_wsi_wayland.c +++ b/src/intel/vulkan/anv_wsi_wayland.c @@ -21,9 +21,6 @@ * IN THE SOFTWARE. */ -#include "vk_format_info.h" -#include - #include "wsi_common_wayland.h" #include "anv_private.h" ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] nir: fix nir_copy_propagation test
On Tue, 2018-10-23 at 09:26 -0500, Jason Ekstrand wrote:
> The commit message is correct but doesn't match the patch.
>
> On October 23, 2018 08:59:25 "Juan A. Suarez Romero"
> wrote:
>
> > Commit 16870de8a0a introduced the use of nir_src_as_* functions, so
> > copy_propagation tests need to check expected value for the first
> > component.
> >
> >
> > Fixes: 16870de8a0a ("nir: Use nir_src_is_const and nir_src_as_* in core
> > code")
> > Signed-off-by: Juan A. Suarez Romero
> > ---
> > src/compiler/nir/tests/vars_tests.cpp | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> >
> > diff --git a/src/compiler/nir/tests/vars_tests.cpp
> > b/src/compiler/nir/tests/vars_tests.cpp
> > index 02c53804b84..fdb3317ca02 100644
> > --- a/src/compiler/nir/tests/vars_tests.cpp
> > +++ b/src/compiler/nir/tests/vars_tests.cpp
> > @@ -375,7 +375,7 @@ TEST_F(nir_copy_prop_vars_test,
> > store_store_load_different_components)
> > ASSERT_TRUE(store_to_v1->src[1].is_ssa);
> >
> > ASSERT_TRUE(nir_src_is_const(store_to_v1->src[1]));
> > - ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 20);
> > + ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 30);
>
> I don't think we want to change from 20 to 30 here. Instead, we want to use
> nir_src_comp_as_uint to get component 1.
>
Right. Didn't realize about this function. Thanks!
J.A.
> --Jason
>
> > break;
> > }
> >}
> > @@ -424,7 +424,7 @@ TEST_F(nir_copy_prop_vars_test,
> > store_store_load_different_components_in_many_bl
> > ASSERT_TRUE(store_to_v1->src[1].is_ssa);
> >
> > ASSERT_TRUE(nir_src_is_const(store_to_v1->src[1]));
> > - ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 20);
> > + ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 30);
> > break;
> > }
> >}
> > --
> > 2.17.2
>
>
>
>
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[Mesa-dev] [PATCH mesa] anv: move variable to proper scope and mark as MAYBE_UNUSED
Signed-off-by: Eric Engestrom
---
src/intel/vulkan/anv_queue.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/intel/vulkan/anv_queue.c b/src/intel/vulkan/anv_queue.c
index db89385b86644417d47a..05739cb26df571c5f4db 100644
--- a/src/intel/vulkan/anv_queue.c
+++ b/src/intel/vulkan/anv_queue.c
@@ -542,8 +542,6 @@ anv_wait_for_bo_fences(struct anv_device *device,
bool waitAll,
uint64_t _timeout)
{
- int ret;
-
/* DRM_IOCTL_I915_GEM_WAIT uses a signed 64 bit timeout and is supposed
* to block indefinitely timeouts <= 0. Unfortunately, this was broken
* for a couple of kernel releases. Since there's no way to know
@@ -647,6 +645,7 @@ anv_wait_for_bo_fences(struct anv_device *device,
abstime.tv_nsec = abs_nsec;
abstime.tv_sec = MIN2(abs_sec, INT_TYPE_MAX(abstime.tv_sec));
+MAYBE_UNUSED int ret;
ret = pthread_cond_timedwait(>queue_submit,
>mutex, );
assert(ret != EINVAL);
--
Cheers,
Eric
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[Mesa-dev] [PATCH mesa] anv: wrap API errors in vk_error()
Signed-off-by: Eric Engestrom
---
src/intel/vulkan/anv_android.c | 2 +-
src/intel/vulkan/anv_device.c | 10 +-
src/intel/vulkan/anv_formats.c | 2 +-
src/intel/vulkan/anv_image.c | 2 +-
src/intel/vulkan/anv_queue.c | 6 +++---
src/intel/vulkan/anv_wsi_display.c | 2 +-
6 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/src/intel/vulkan/anv_android.c b/src/intel/vulkan/anv_android.c
index 46c41d57861f18f48275..1334cbbc13814893b3b6 100644
--- a/src/intel/vulkan/anv_android.c
+++ b/src/intel/vulkan/anv_android.c
@@ -314,7 +314,7 @@ VkResult anv_GetSwapchainGrallocUsageANDROID(
}
if (*grallocUsage == 0)
- return VK_ERROR_FORMAT_NOT_SUPPORTED;
+ return vk_error(VK_ERROR_FORMAT_NOT_SUPPORTED);
return VK_SUCCESS;
}
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 3ac1bad93ed8713b0da5..211991d6874d52c10ff3 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -2133,7 +2133,7 @@ VkResult anv_DeviceWaitIdle(
{
ANV_FROM_HANDLE(anv_device, device, _device);
if (unlikely(device->lost))
- return VK_ERROR_DEVICE_LOST;
+ return vk_error(VK_ERROR_DEVICE_LOST);
struct anv_batch batch;
@@ -2236,7 +2236,7 @@ VkResult anv_AllocateMemory(
assert(pAllocateInfo->allocationSize > 0);
if (pAllocateInfo->allocationSize > MAX_MEMORY_ALLOCATION_SIZE)
- return VK_ERROR_OUT_OF_DEVICE_MEMORY;
+ return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
/* FINISHME: Fail if allocation request exceeds heap size. */
@@ -2807,7 +2807,7 @@ VkResult anv_QueueBindSparse(
{
ANV_FROM_HANDLE(anv_queue, queue, _queue);
if (unlikely(queue->device->lost))
- return VK_ERROR_DEVICE_LOST;
+ return vk_error(VK_ERROR_DEVICE_LOST);
return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
}
@@ -2865,7 +2865,7 @@ VkResult anv_GetEventStatus(
ANV_FROM_HANDLE(anv_event, event, _event);
if (unlikely(device->lost))
- return VK_ERROR_DEVICE_LOST;
+ return vk_error(VK_ERROR_DEVICE_LOST);
if (!device->info.has_llc) {
/* Invalidate read cache before reading event written by GPU. */
@@ -3095,7 +3095,7 @@ VkResult anv_GetCalibratedTimestampsEXT(
if (ret != 0) {
device->lost = TRUE;
-return VK_ERROR_DEVICE_LOST;
+return vk_error(VK_ERROR_DEVICE_LOST);
}
uint64_t device_period = DIV_ROUND_UP(10,
timestamp_frequency);
max_clock_period = MAX2(max_clock_period, device_period);
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 9199567f4454ae6df653..cd1ca9f7b8378a3b24ed 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -907,7 +907,7 @@ anv_get_image_format_properties(
.maxResourceSize = 0,
};
- return VK_ERROR_FORMAT_NOT_SUPPORTED;
+ return vk_error(VK_ERROR_FORMAT_NOT_SUPPORTED);
}
VkResult anv_GetPhysicalDeviceImageFormatProperties(
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index e89ce012be7c31f2410a..3e462a3e5739e32b4535 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -355,7 +355,7 @@ make_surface(const struct anv_device *dev,
.tiling_flags = tiling_flags);
if (!ok)
- return VK_ERROR_OUT_OF_DEVICE_MEMORY;
+ return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
image->planes[plane].aux_usage = ISL_AUX_USAGE_NONE;
diff --git a/src/intel/vulkan/anv_queue.c b/src/intel/vulkan/anv_queue.c
index e0c0a42069f1e52dafeb..db89385b86644417d47a 100644
--- a/src/intel/vulkan/anv_queue.c
+++ b/src/intel/vulkan/anv_queue.c
@@ -399,7 +399,7 @@ VkResult anv_GetFenceStatus(
ANV_FROM_HANDLE(anv_fence, fence, _fence);
if (unlikely(device->lost))
- return VK_ERROR_DEVICE_LOST;
+ return vk_error(VK_ERROR_DEVICE_LOST);
struct anv_fence_impl *impl =
fence->temporary.type != ANV_FENCE_TYPE_NONE ?
@@ -672,7 +672,7 @@ anv_wait_for_bo_fences(struct anv_device *device,
done:
if (unlikely(device->lost))
- return VK_ERROR_DEVICE_LOST;
+ return vk_error(VK_ERROR_DEVICE_LOST);
return result;
}
@@ -762,7 +762,7 @@ VkResult anv_WaitForFences(
ANV_FROM_HANDLE(anv_device, device, _device);
if (unlikely(device->lost))
- return VK_ERROR_DEVICE_LOST;
+ return vk_error(VK_ERROR_DEVICE_LOST);
if (anv_all_fences_syncobj(fenceCount, pFences)) {
return anv_wait_for_syncobj_fences(device, fenceCount, pFences,
diff --git a/src/intel/vulkan/anv_wsi_display.c
b/src/intel/vulkan/anv_wsi_display.c
index 3212c235bab0552970ed..d5fdf81930859711c9d4 100644
--- a/src/intel/vulkan/anv_wsi_display.c
+++ b/src/intel/vulkan/anv_wsi_display.c
@@ -288,7 +288,7 @@ anv_RegisterDisplayEventEXT(VkDevice _device,
fence = vk_zalloc2(>alloc, allocator, sizeof (*fence), 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (!fence)
-
[Mesa-dev] [PATCH mesa] anv: use snprintf() instead of memset()+strcpy()
snprintf() guarantees that it will not write more chars than allowed,
and that the string will be null-terminated, without the need to fill
the whole thing with zeroes to begin with.
Signed-off-by: Eric Engestrom
---
src/intel/vulkan/anv_device.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index c009176dcc6c605e2e41..3ac1bad93ed8713b0da5 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -37,6 +37,7 @@
#include "util/build_id.h"
#include "util/disk_cache.h"
#include "util/mesa-sha1.h"
+#include "util/u_string.h"
#include "git_sha1.h"
#include "vk_util.h"
#include "common/gen_defines.h"
@@ -1135,12 +1136,10 @@ void anv_GetPhysicalDeviceProperties2(
(VkPhysicalDeviceDriverPropertiesKHR *) ext;
driver_props->driverID = VK_DRIVER_ID_INTEL_OPEN_SOURCE_MESA_KHR;
- memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
- strcpy(driver_props->driverName,
+ util_snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR,
"Intel open-source Mesa driver");
- memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
- strcpy(driver_props->driverInfo,
+ util_snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
"Mesa " PACKAGE_VERSION MESA_GIT_SHA1);
driver_props->conformanceVersion = (VkConformanceVersionKHR) {
--
Cheers,
Eric
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Re: [Mesa-dev] [PATCH mesa] anv: drop unused includes
Rb On October 23, 2018 09:26:16 Eric Engestrom wrote: Signed-off-by: Eric Engestrom --- src/intel/vulkan/anv_wsi_wayland.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/intel/vulkan/anv_wsi_wayland.c b/src/intel/vulkan/anv_wsi_wayland.c index 3aeb1994110c563456cd..26383f42387ea28af0b5 100644 --- a/src/intel/vulkan/anv_wsi_wayland.c +++ b/src/intel/vulkan/anv_wsi_wayland.c @@ -21,9 +21,6 @@ * IN THE SOFTWARE. */ -#include "vk_format_info.h" -#include - #include "wsi_common_wayland.h" #include "anv_private.h" -- Cheers, Eric ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] nir: fix nir_copy_propagation test
The commit message is correct but doesn't match the patch.
On October 23, 2018 08:59:25 "Juan A. Suarez Romero"
wrote:
Commit 16870de8a0a introduced the use of nir_src_as_* functions, so
copy_propagation tests need to check expected value for the first
component.
Fixes: 16870de8a0a ("nir: Use nir_src_is_const and nir_src_as_* in core
code")
Signed-off-by: Juan A. Suarez Romero
---
src/compiler/nir/tests/vars_tests.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/compiler/nir/tests/vars_tests.cpp
b/src/compiler/nir/tests/vars_tests.cpp
index 02c53804b84..fdb3317ca02 100644
--- a/src/compiler/nir/tests/vars_tests.cpp
+++ b/src/compiler/nir/tests/vars_tests.cpp
@@ -375,7 +375,7 @@ TEST_F(nir_copy_prop_vars_test,
store_store_load_different_components)
ASSERT_TRUE(store_to_v1->src[1].is_ssa);
ASSERT_TRUE(nir_src_is_const(store_to_v1->src[1]));
- ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 20);
+ ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 30);
I don't think we want to change from 20 to 30 here. Instead, we want to use
nir_src_comp_as_uint to get component 1.
--Jason
break;
}
}
@@ -424,7 +424,7 @@ TEST_F(nir_copy_prop_vars_test,
store_store_load_different_components_in_many_bl
ASSERT_TRUE(store_to_v1->src[1].is_ssa);
ASSERT_TRUE(nir_src_is_const(store_to_v1->src[1]));
- ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 20);
+ ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 30);
break;
}
}
--
2.17.2
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[Mesa-dev] [PATCH mesa] anv: drop unused includes
Signed-off-by: Eric Engestrom --- src/intel/vulkan/anv_wsi_wayland.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/intel/vulkan/anv_wsi_wayland.c b/src/intel/vulkan/anv_wsi_wayland.c index 3aeb1994110c563456cd..26383f42387ea28af0b5 100644 --- a/src/intel/vulkan/anv_wsi_wayland.c +++ b/src/intel/vulkan/anv_wsi_wayland.c @@ -21,9 +21,6 @@ * IN THE SOFTWARE. */ -#include "vk_format_info.h" -#include - #include "wsi_common_wayland.h" #include "anv_private.h" -- Cheers, Eric ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 4/9] nir: Use nir_src_is_const and nir_src_as_* in core code
Hi Jason, this change caused an assertion failure for me during make check, in the nir/tests/vars_tests test under src/compiler. See the attached backtrace. -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer Core was generated by `./nir/tests/vars_tests'. Program terminated with signal SIGABRT, Aborted. #0 __GI_raise (sig=sig@entry=6) at ../sysdeps/unix/sysv/linux/raise.c:51 51 ../sysdeps/unix/sysv/linux/raise.c: No such file or directory. (gdb) bt #0 __GI_raise (sig=sig@entry=6) at ../sysdeps/unix/sysv/linux/raise.c:51 #1 0x7fa17a3a62f1 in __GI_abort () at abort.c:79 #2 0x7fa17a39da8a in __assert_fail_base (fmt=0x7fa17a4f1ec8 "%s%s%s:%u: %s%sAssertion `%s' failed.\n%n", assertion=assertion@entry=0x559a19a47c08 "nir_src_num_components(src) == 1", file=file@entry=0x559a19a477e0 "../../../src/compiler/nir/nir.c", line=line@entry=1275, function=function@entry=0x559a19a48490 <__PRETTY_FUNCTION__.25988> "nir_src_as_uint") at assert.c:92 #3 0x7fa17a39db02 in __GI___assert_fail (assertion=assertion@entry=0x559a19a47c08 "nir_src_num_components(src) == 1", file=file@entry=0x559a19a477e0 "../../../src/compiler/nir/nir.c", line=line@entry=1275, function=function@entry=0x559a19a48490 <__PRETTY_FUNCTION__.25988> "nir_src_as_uint") at assert.c:101 #4 0x559a19a0ee64 in nir_src_as_uint (src=...) at ../../../src/compiler/nir/nir.c:1276 #5 0x559a199e3244 in nir_copy_prop_vars_test_store_store_load_different_components_Test::TestBody() () at ../../../src/compiler/nir/tests/vars_tests.cpp:378 #6 0x559a19a0be1e in testing::internal::HandleSehExceptionsInMethodIfSupported (location=0x559a19a4468f "the test body", method=, object=0x559a19f20b60) at ../../../src/gtest/src/gtest.cc:2383 #7 testing::internal::HandleExceptionsInMethodIfSupported (object=object@entry=0x559a19f20b60, method=, location=location@entry=0x559a19a4468f "the test body") at ../../../src/gtest/src/gtest.cc:2438 #8 0x559a19a023ba in testing::Test::Run (this=0x559a19f20b60) at ../../../src/gtest/src/gtest.cc:2474 #9 0x559a19a02508 in testing::TestInfo::Run (this=0x559a19f1f350) at ../../../src/gtest/src/gtest.cc:2656 #10 0x559a19a025e4 in testing::TestCase::Run (this=0x559a19f1ee90) at ../../../src/gtest/src/gtest.cc:2774 #11 0x559a19a02ad4 in testing::internal::UnitTestImpl::RunAllTests() () at /usr/include/c++/8/bits/stl_vector.h:930 #12 0x559a19a0c2fe in testing::internal::HandleSehExceptionsInMethodIfSupported (location=0x559a19a45830 "auxiliary test code (environments or event listeners)", method=, object=0x559a19f1e100) at ../../../src/gtest/src/gtest.cc:2383 #13 testing::internal::HandleExceptionsInMethodIfSupported (object=0x559a19f1e100, method=, location=location@entry=0x559a19a45830 "auxiliary test code (environments or event listeners)") at ../../../src/gtest/src/gtest.cc:2438 #14 0x559a19a02bc2 in testing::UnitTest::Run() () at ../../../src/gtest/include/gtest/gtest.h:1287 #15 0x559a199db934 in RUN_ALL_TESTS () at ../../../src/gtest/include/gtest/gtest.h:2233 #16 main (argc=, argv=0x7fffc3ee3048) at ../../../src/gtest/src/gtest_main.cc:37 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] nir: fix nir_copy_propagation test
Commit 16870de8a0a introduced the use of nir_src_as_* functions, so
copy_propagation tests need to check expected value for the first
component.
Fixes: 16870de8a0a ("nir: Use nir_src_is_const and nir_src_as_* in core
code")
Signed-off-by: Juan A. Suarez Romero
---
src/compiler/nir/tests/vars_tests.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/compiler/nir/tests/vars_tests.cpp
b/src/compiler/nir/tests/vars_tests.cpp
index 02c53804b84..fdb3317ca02 100644
--- a/src/compiler/nir/tests/vars_tests.cpp
+++ b/src/compiler/nir/tests/vars_tests.cpp
@@ -375,7 +375,7 @@ TEST_F(nir_copy_prop_vars_test,
store_store_load_different_components)
ASSERT_TRUE(store_to_v1->src[1].is_ssa);
ASSERT_TRUE(nir_src_is_const(store_to_v1->src[1]));
- ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 20);
+ ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 30);
break;
}
}
@@ -424,7 +424,7 @@ TEST_F(nir_copy_prop_vars_test,
store_store_load_different_components_in_many_bl
ASSERT_TRUE(store_to_v1->src[1].is_ssa);
ASSERT_TRUE(nir_src_is_const(store_to_v1->src[1]));
- ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 20);
+ ASSERT_EQ(nir_src_as_uint(store_to_v1->src[1]), 30);
break;
}
}
--
2.17.2
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Re: [Mesa-dev] [PATCH] radv: fix btoi for R32G32B32 when the dest offset is not 0
Reviewed-by: Bas Nieuwenhuizen
On Mon, Oct 22, 2018 at 3:41 PM Samuel Pitoiset
wrote:
>
> Fixes: 593996bc02 ("radv: implement buffer to image operations for R32G32B32")
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_meta_bufimage.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_meta_bufimage.c
> b/src/amd/vulkan/radv_meta_bufimage.c
> index 73a5034222..ec449c5bca 100644
> --- a/src/amd/vulkan/radv_meta_bufimage.c
> +++ b/src/amd/vulkan/radv_meta_bufimage.c
> @@ -556,8 +556,8 @@ build_nir_btoi_r32g32b32_compute_shader(struct
> radv_device *dev)
>
> nir_ssa_def *global_pos =
> nir_iadd(,
> -nir_imul(, pos_y, >dest.ssa),
> -nir_imul(, pos_x, nir_imm_int(, 3)));
> +nir_imul(, nir_channel(, img_coord, 1),
> >dest.ssa),
> +nir_imul(, nir_channel(, img_coord, 0),
> nir_imm_int(, 3)));
>
> nir_ssa_def *input_img_deref = _build_deref_var(,
> input_img)->dest.ssa;
>
> --
> 2.19.1
>
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[Mesa-dev] [PATCH mesa] util: remove unnecessary random whitespaces
Suggested-by: Timothy Arceri Signed-off-by: Eric Engestrom --- Timothy, I opted to remove them all instead of adding even more, as it would break again next time something changes (the set_foreach() one was already broken before my patch for instance) and result in lots of unnecessary churn for seemingly no gain, and I don't like hiding the backslash away (it hinders readability). --- src/util/hash_table.h | 6 +++--- src/util/set.h| 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/util/hash_table.h b/src/util/hash_table.h index b96cd6146960a6a6f8a1..b9c9dfa01aeaa5e9cac1 100644 --- a/src/util/hash_table.h +++ b/src/util/hash_table.h @@ -139,9 +139,9 @@ _mesa_fnv32_1a_accumulate_block(uint32_t hash, const void *data, size_t size) * an entry's data with the deleted marker), but not against insertion * (which may rehash the table, making entry a dangling pointer). */ -#define hash_table_foreach(ht, entry) \ - for (struct hash_entry *entry = _mesa_hash_table_next_entry(ht, NULL); \ -entry != NULL; \ +#define hash_table_foreach(ht, entry) \ + for (struct hash_entry *entry = _mesa_hash_table_next_entry(ht, NULL); \ +entry != NULL; \ entry = _mesa_hash_table_next_entry(ht, entry)) static inline void diff --git a/src/util/set.h b/src/util/set.h index 3c9abfe77128292557ec..4307f4732fd4fde132a0 100644 --- a/src/util/set.h +++ b/src/util/set.h @@ -96,9 +96,9 @@ _mesa_set_random_entry(struct set *set, * insertion (which may rehash the set, making entry a dangling * pointer). */ -#define set_foreach(set, entry) \ - for (struct set_entry *entry = _mesa_set_next_entry(set, NULL); \ -entry != NULL; \ +#define set_foreach(set, entry) \ + for (struct set_entry *entry = _mesa_set_next_entry(set, NULL); \ +entry != NULL; \ entry = _mesa_set_next_entry(set, entry)) #ifdef __cplusplus -- Cheers, Eric ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/3] nir: add linking helper nir_link_xfb_varyings()
From: Samuel Pitoiset
The linking opts shouldn't try removing or compacting XFB varyings
in the consumer. To avoid this we copy the always_active_io flag
from the producer.
---
src/compiler/nir/nir.h | 1 +
src/compiler/nir/nir_linking_helpers.c | 33 ++
2 files changed, 34 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 0ba19cbb25d..60ea4fbc7ff 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2799,6 +2799,7 @@ bool nir_remove_unused_io_vars(nir_shader *shader, struct
exec_list *var_list,
uint64_t *used_by_other_stage_patches);
void nir_compact_varyings(nir_shader *producer, nir_shader *consumer,
bool default_to_smooth_interp);
+void nir_link_xfb_varyings(nir_shader *producer, nir_shader *consumer);
typedef enum {
/* If set, this forces all non-flat fragment shader inputs to be
diff --git a/src/compiler/nir/nir_linking_helpers.c
b/src/compiler/nir/nir_linking_helpers.c
index 85677b7c176..ca46a6b71b0 100644
--- a/src/compiler/nir/nir_linking_helpers.c
+++ b/src/compiler/nir/nir_linking_helpers.c
@@ -523,3 +523,36 @@ nir_compact_varyings(nir_shader *producer, nir_shader
*consumer,
compact_components(producer, consumer, comps, interp_type, interp_loc,
default_to_smooth_interp);
}
+
+/*
+ * Mark XFB varyings as always_active_io in the consumer so the linking opts
+ * don't touch them.
+ */
+void
+nir_link_xfb_varyings(nir_shader *producer, nir_shader *consumer)
+{
+ nir_variable *input_vars[MAX_VARYING] = {};
+
+ nir_foreach_variable(var, >inputs) {
+ if (var->data.location >= VARYING_SLOT_VAR0 &&
+ var->data.location - VARYING_SLOT_VAR0 < MAX_VARYING) {
+
+ unsigned location = var->data.location - VARYING_SLOT_VAR0;
+ input_vars[location] = var;
+ }
+ }
+
+ nir_foreach_variable(var, >outputs) {
+ if (var->data.location >= VARYING_SLOT_VAR0 &&
+ var->data.location - VARYING_SLOT_VAR0 < MAX_VARYING) {
+
+ if (!var->data.always_active_io)
+continue;
+
+ unsigned location = var->data.location - VARYING_SLOT_VAR0;
+ if (input_vars[location]) {
+input_vars[location]->data.always_active_io = true;
+ }
+ }
+ }
+}
--
2.17.2
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[Mesa-dev] [PATCH 2/3] radv: move nir_lower_io_to_scalar_early() to radv_link_shaders()
nir_lower_io_to_scalar_early() is really part of the link time
optimisations. Moving it here allows the code to be simplified
and also keeps the code easy to follow in the next patch.
---
src/amd/vulkan/radv_pipeline.c | 44 ++
1 file changed, 18 insertions(+), 26 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 8d15a048bbf..396b44d25a1 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1788,6 +1788,24 @@ radv_link_shaders(struct radv_pipeline *pipeline,
nir_shader **shaders)
ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
}
+ if (shader_count > 1) {
+ unsigned first = ordered_shaders[shader_count - 1]->info.stage;
+ unsigned last = ordered_shaders[0]->info.stage;
+
+ for (int i = 0; i < shader_count; ++i) {
+ nir_variable_mode mask = 0;
+
+ if (ordered_shaders[i]->info.stage != first)
+ mask = mask | nir_var_shader_in;
+
+ if (ordered_shaders[i]->info.stage != last)
+ mask = mask | nir_var_shader_out;
+
+ nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
+ radv_optimize_nir(ordered_shaders[i], false, false);
+ }
+ }
+
for (int i = 1; i < shader_count; ++i) {
nir_lower_io_arrays_to_elements(ordered_shaders[i],
ordered_shaders[i - 1]);
@@ -2033,17 +2051,6 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
modules[MESA_SHADER_FRAGMENT] = _m;
}
- /* Determine first and last stage. */
- unsigned first = MESA_SHADER_STAGES;
- unsigned last = 0;
- for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
- if (!pStages[i])
- continue;
- if (first == MESA_SHADER_STAGES)
- first = i;
- last = i;
- }
-
for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
const VkPipelineShaderStageCreateInfo *stage = pStages[i];
@@ -2061,21 +2068,6 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
if (nir[i]->info.name) {
nir[i] = nir_shader_clone(NULL, nir[i]);
}
-
- if (first != last) {
- nir_variable_mode mask = 0;
-
- if (i != first)
- mask = mask | nir_var_shader_in;
-
- if (i != last)
- mask = mask | nir_var_shader_out;
-
- if (!(flags &
VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)) {
- nir_lower_io_to_scalar_early(nir[i], mask);
- radv_optimize_nir(nir[i], false, false);
- }
- }
}
if (nir[MESA_SHADER_TESS_CTRL]) {
--
2.17.2
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[Mesa-dev] [PATCH 3/3] radv: call nir_link_xfb_varyings()
---
src/amd/vulkan/radv_pipeline.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 396b44d25a1..c21ca1743a4 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1792,6 +1792,10 @@ radv_link_shaders(struct radv_pipeline *pipeline,
nir_shader **shaders)
unsigned first = ordered_shaders[shader_count - 1]->info.stage;
unsigned last = ordered_shaders[0]->info.stage;
+ if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
+ ordered_shaders[1]->info.has_transform_feedback_varyings)
+ nir_link_xfb_varyings(ordered_shaders[1],
ordered_shaders[0]);
+
for (int i = 0; i < shader_count; ++i) {
nir_variable_mode mask = 0;
--
2.17.2
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Re: [Mesa-dev] [PATCH 00/31] nir: Use a 1-bit data type for booleans
On Mon, 2018-10-22 at 17:13 -0500, Jason Ekstrand wrote: > This is something that Connor and I have talked about quite a bit > over the > last couple of months. The core idea is to replace NIR's current 32- > bit > 0/-1 D3D10-style booleans with a 1-bit data type. All in all, I > think it > worked out pretty well though I really don't like the proliferation > of > 32-bit comparison opcodes we now have kicking around for i965. > > Why? No hardware really has a 1-bit type, right? Well, sort > of... AMD > actually uses 64-bit scalars for booleans with one bit per > invocation. > However, most hardware such as Intel uses some other larger value for > booleans. The real benefit of 1-bit booleans and requiring a > lowering pass > is that you can do somewhat custom lowering (like AMD wants) and your > lowering pass can always tell in an instant if a value is a boolean > based > on the bit size. As can be seen in the last patch, this makes it > really > easy to implement a bool -> float lowering pass for hardware that > doesn't > have real integers where NIR's current booleans are actually rather > painful. > > On Intel, the situation is a bit more complicated. It's tempting to > say > that we have 32-bit D3D10 booleans. However, they're not really > D3D10 > booleans on gen4-5 because the top 31 bits are undefined garbage and, > while > iand, ior, ixor, and inot operations work, you have to iand with 1 at > the > last minute to clear off all that garbage. Also, on all generations, > a > comparison of two N-bit values results in an N-bit boolean, not a 32- > bit > bool. This has caused the Igalia folks no end of trouble as they've > been > working on native 8 and 16-bit support. If, instead, we have a 1-bit > bool > with a lowering pass and we can lower to whatever we want, then we > could > lower to a set of comparison opcodes that return the same bit-size as > they > compare and it would match GEN hardware much better. This is great! I have been working on and off on a backend optimization pass to revert the 32-bit conversions we had to inject to honor NIR's 32-bit booleans during the NIR->FS translation and honestly, the more I worked on it the less I liked it. > But what about performance? Aren't there all sorts of neat tricks we > can > do with D3D10 booleans like b & 1.0f for b2f? As it turns out, not > really; > that's about the only one. There is some small advantage when > optimizing > shaders that come from D3D if your native representation of booleans > matches that of D3D. However, penultimate patch in this series adds > a few > small optimizations that get us to actually better than we were > before. > With the entire series, shader-db on Kaby Lak looks like this: > > total instructions in shared programs: 15084098 -> 14988578 (- > 0.63%) > instructions in affected programs: 1321114 -> 1225594 (-7.23%) > helped: 2340 > HURT: 23 > > total cycles in shared programs: 369790134 -> 359798399 (-2.70%) > cycles in affected programs: 134085452 -> 124093717 (-7.45%) > helped: 2149 > HURT: 720 > > total loops in shared programs: 4393 -> 4393 (0.00%) > loops in affected programs: 0 -> 0 > helped: 0 > HURT: 0 > > total spills in shared programs: 10158 -> 10051 (-1.05%) > spills in affected programs: 1429 -> 1322 (-7.49%) > helped: 8 > HURT: 15 > > total fills in shared programs: 22105 -> 21720 (-1.74%) > fills in affected programs: 2853 -> 2468 (-13.49%) > helped: 12 > HURT: 15 > > How about ease of use? Are they a pain to deal with? Yes, adding > support > for 1-bit types was a bit awkward in a few places but most of it was > dealing with all the places where we have 32-bit booleans baked into > assumptions. Getting rid of that baking in solves the problem and > also > makes the whole IR more future-proof. > > All in all, I'd say I'm pretty happy with it. However, I'd like > other > people (particularly the AMD folks) to play with it a bit and verify > that > it solves their problems as well. Also, I added a lowering pass and > tried > to turn it on in everyone's driver but may not have put it in the > right > spot. Please double-check my work. For those wishing to take a > look, you > can also find the entire series on my gitlab here: > > https://gitlab.freedesktop.org/jekstrand/mesa/commits/review/nir-1-bit-bool I'll try to rebase my work on top of this and see how things look like as well, thanks again for doing this Jason. Iago > Please review! > > --Jason > > Cc: Connor Abbott > Cc: Timothy Arceri > Cc: Eric Anholt > Cc: Rob Clark > Cc: Karol Herbst > Cc: Bas Nieuwenhuizen > Cc: Alyssa Rosenzweig > > > Jason Ekstrand (31): > nir/validate: Print when the validation failed > nir/constant_folding: Add an unreachable to a switch > nir/constant_folding: Use nir_src_as_bool for discard_if > nir/builder: Add a nir_imm_true/false helpers > nir/builder: Handle 16-bit floats in
Re: [Mesa-dev] [PATCH] st/mesa: Record shader access qualifiers for images
On Friday, October 19, 2018 3:04:45 PM PDT Marek Olšák wrote: > On Mon, Oct 15, 2018 at 6:35 PM Kenneth Graunke > wrote: > > > From: Jason Ekstrand > > > > They're not required to be the same as the access flag on the image > > unit. For hardware that does shader image lowering based on the > > qualifier (Intel), it may be required for state setup. > > --- > > src/gallium/include/pipe/p_state.h | 1 + > > src/mesa/state_tracker/st_atom_image.c | 27 ++ > > src/mesa/state_tracker/st_cb_texture.c | 2 +- > > src/mesa/state_tracker/st_texture.c| 2 +- > > src/mesa/state_tracker/st_texture.h| 5 +++-- > > 5 files changed, 29 insertions(+), 8 deletions(-) > > > > diff --git a/src/gallium/include/pipe/p_state.h > > b/src/gallium/include/pipe/p_state.h > > index a58d91fb3dd..331417b1d7f 100644 > > --- a/src/gallium/include/pipe/p_state.h > > +++ b/src/gallium/include/pipe/p_state.h > > @@ -485,6 +485,7 @@ struct pipe_image_view > > struct pipe_resource *resource; /**< resource into which this is a > > view */ > > enum pipe_format format; /**< typed PIPE_FORMAT_x */ > > unsigned access; /**< PIPE_IMAGE_ACCESS_x */ > > + unsigned shader_access; /**< PIPE_IMAGE_ACCESS_x */ > > > > Can you use uint16_t for both access masks? Other than that: > > Reviewed-by: Marek Olšák > > Marek Good call, that way we don't make the struct any larger. I made that changed and pushed the patch. Thanks for the review! signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv: Emit enqueued pipeline barriers on event write.
Cc stable? On 10/23/18 10:59 AM, Bas Nieuwenhuizen wrote: Since the CPU can read them we need to execute any GPU->CPU flushes before the event is written. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108524 Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver" --- src/amd/vulkan/radv_cmd_buffer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 339704990e2..e21aaa9535d 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -4337,6 +4337,8 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer, struct radeon_cmdbuf *cs = cmd_buffer->cs; uint64_t va = radv_buffer_get_va(event->bo); + si_emit_cache_flush(cmd_buffer); + radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo); MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18); ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv: Emit enqueued pipeline barriers on event write.
Reviewed-by: Samuel Pitoiset On 10/23/18 10:59 AM, Bas Nieuwenhuizen wrote: Since the CPU can read them we need to execute any GPU->CPU flushes before the event is written. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108524 Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver" --- src/amd/vulkan/radv_cmd_buffer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 339704990e2..e21aaa9535d 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -4337,6 +4337,8 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer, struct radeon_cmdbuf *cs = cmd_buffer->cs; uint64_t va = radv_buffer_get_va(event->bo); + si_emit_cache_flush(cmd_buffer); + radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo); MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18); ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 108524] [RADV] GPU lockup on event synchronization
https://bugs.freedesktop.org/show_bug.cgi?id=108524 --- Comment #1 from Bas Nieuwenhuizen --- I did not see a lockup* but this fixes the data issue: https://patchwork.freedesktop.org/patch/257901/ *: I got some what looks like the program just trying to dump too much stuff too the terminal, while the terminal cannot redraw because you are keeping a commandbuffer in flight. You can avoid this by using the compute queue or by dumping less stuff to the terminal (as fixing the data issue effectively does) -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radv: Emit enqueued pipeline barriers on event write.
Since the CPU can read them we need to execute any GPU->CPU flushes before the event is written. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108524 Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver" --- src/amd/vulkan/radv_cmd_buffer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 339704990e2..e21aaa9535d 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -4337,6 +4337,8 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer, struct radeon_cmdbuf *cs = cmd_buffer->cs; uint64_t va = radv_buffer_get_va(event->bo); + si_emit_cache_flush(cmd_buffer); + radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo); MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18); -- 2.19.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 108524] [RADV] GPU lockup on event synchronization
https://bugs.freedesktop.org/show_bug.cgi?id=108524 Bug ID: 108524 Summary: [RADV] GPU lockup on event synchronization Product: Mesa Version: 18.2 Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: Drivers/Vulkan/radeon Assignee: mesa-dev@lists.freedesktop.org Reporter: nex...@gmail.com QA Contact: mesa-dev@lists.freedesktop.org I'm working on Device - Host - Device synchronization with VkEvent, but doing that results to a lockup using radv. It works with amdvlk though as you can read in the original issue on the Khronos github page here: https://github.com/KhronosGroup/Vulkan-Docs/issues/755 Here is sample source code that reproduces the problem: https://gist.github.com/neXyon/859b2e52bac9a5a56b804d8a9d5fa4a5 -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 107765] [regression] Batman Arkham City crashes with DXVK under wine
https://bugs.freedesktop.org/show_bug.cgi?id=107765 --- Comment #14 from Samuel Pitoiset --- Can you try this branch please? https://cgit.freedesktop.org/~hakzsam/mesa/log/?h=radv_itoi_r32g32b32 -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa/glformats: Remove redundant helper _mesa_base_format_component_count
On 10/23/2018 08:17 AM, Tapani Pälli wrote:
>
> On 10/23/18 8:56 AM, Eduardo Lima Mitev wrote:
>> There exists _mesa_components_in_format() which already includes
>> all cases handled in _mesa_base_format_component_count().
>
> I guess the idea here was that one function only covers 'base formats'
> and other one all formats. But I guess none of the users verify if 'base
> format' is sane this way? If this is the case and there are no regressions;
>
Yes, this is the best explanation for adding the helper.
However, looking at the the two uses of this function, it is not
expected that it validates the format as a base format. Also,
_mesa_base_format_component_count() handle mostly base formats anyway.
I ran the patch through Intel CI with no regressions.
> Reviewed-by: Tapani Pälli
>
Thanks!
Eduardo
>
>> ---
>> src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
>> src/mesa/main/glformats.c | 27 ---
>> src/mesa/main/glformats.h | 3 ---
>> src/mesa/main/teximage.c | 4 ++--
>> 4 files changed, 3 insertions(+), 33 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
>> b/src/mesa/drivers/dri/i965/brw_blorp.c
>> index ad3a47ef035..b286b231537 100644
>> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
>> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
>> @@ -1195,7 +1195,7 @@ set_write_disables(const struct
>> intel_renderbuffer *irb,
>> * RGB we can treat alpha as not used and write whatever we like
>> into it.
>> */
>> const GLenum base_format = irb->Base.Base._BaseFormat;
>> - const int components =
>> _mesa_base_format_component_count(base_format);
>> + const int components = _mesa_components_in_format(base_format);
>> bool disables = false;
>> assert(components > 0);
>> diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
>> index bbeb6034dd7..6cb3435dea2 100644
>> --- a/src/mesa/main/glformats.c
>> +++ b/src/mesa/main/glformats.c
>> @@ -1630,33 +1630,6 @@ _mesa_base_format_has_channel(GLenum
>> base_format, GLenum pname)
>> }
>> -/**
>> - * Returns the number of channels/components for a base format.
>> - */
>> -GLint
>> -_mesa_base_format_component_count(GLenum base_format)
>> -{
>> - switch (base_format) {
>> - case GL_LUMINANCE:
>> - case GL_RED:
>> - case GL_ALPHA:
>> - case GL_INTENSITY:
>> - case GL_DEPTH_COMPONENT:
>> - return 1;
>> - case GL_RG:
>> - case GL_LUMINANCE_ALPHA:
>> - case GL_DEPTH_STENCIL:
>> - return 2;
>> - case GL_RGB:
>> - return 3;
>> - case GL_RGBA:
>> - return 4;
>> - default:
>> - return -1;
>> - }
>> -}
>> -
>> -
>> /**
>> * If format is a generic compressed format, return the corresponding
>> * non-compressed format. For other formats, return the format as-is.
>> diff --git a/src/mesa/main/glformats.h b/src/mesa/main/glformats.h
>> index 5a21317159d..0aefdf50fef 100644
>> --- a/src/mesa/main/glformats.h
>> +++ b/src/mesa/main/glformats.h
>> @@ -119,9 +119,6 @@ _mesa_unpack_format_to_base_format(GLenum format);
>> extern GLboolean
>> _mesa_base_format_has_channel(GLenum base_format, GLenum pname);
>> -extern GLint
>> -_mesa_base_format_component_count(GLenum base_format);
>> -
>> extern GLenum
>> _mesa_generic_compressed_format_to_uncompressed_format(GLenum format);
>> diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
>> index d45854bd17f..6805b47c728 100644
>> --- a/src/mesa/main/teximage.c
>> +++ b/src/mesa/main/teximage.c
>> @@ -2407,8 +2407,8 @@ copytexture_error_check( struct gl_context *ctx,
>> GLuint dimensions,
>> if (_mesa_is_gles(ctx)) {
>> bool valid = true;
>> - if (_mesa_base_format_component_count(baseFormat) >
>> - _mesa_base_format_component_count(rb_base_format)) {
>> + if (_mesa_components_in_format(baseFormat) >
>> + _mesa_components_in_format(rb_base_format)) {
>> valid = false;
>> }
>> if (baseFormat == GL_DEPTH_COMPONENT ||
>>
>
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Re: [Mesa-dev] [PATCH 30/31] nir/algebraic: Add some optimizations for D3D-style booleans
On Tue, Oct 23, 2018 at 12:16 AM Jason Ekstrand wrote:
>
> D3D booleans use a 32-bit 0/-1 representation. Because this previously
> matched NIR exactly, we didn't have to really optimize for it. Now that
> we have 1-bit booleans, we need some specific optimizations to chew
> through the D3D12-style booleans.
> ---
> src/compiler/nir/nir_opt_algebraic.py | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/src/compiler/nir/nir_opt_algebraic.py
> b/src/compiler/nir/nir_opt_algebraic.py
> index f0861c4411d..4d778e4b308 100644
> --- a/src/compiler/nir/nir_opt_algebraic.py
> +++ b/src/compiler/nir/nir_opt_algebraic.py
> @@ -239,6 +239,7 @@ optimizations = [
> (('fne', ('b2f', a), 0.0), a),
> (('ieq', ('b2i', a), 0), ('inot', a)),
> (('ine', ('b2i', a), 0), a),
> + (('ine', ('ineg', ('b2i', a)), 0), a),
>
> (('fne', ('u2f32', a), 0.0), ('ine', a, 0)),
> (('feq', ('u2f32', a), 0.0), ('ieq', a, 0)),
> @@ -528,6 +529,18 @@ optimizations = [
> (('bcsel', a, b, b), b),
> (('fcsel', a, b, b), b),
>
> + # D3D Boolean eumulation
> + (('bcsel', a, -1, 0), ('ineg', ('b2i', a))),
> + (('bcsel', a, 0, -1), ('ineg', ('b2i', ('inot', a,
> + (('iand', ('ineg', ('b2i', a)), ('ineg', ('b2i', b))),
> +('ineg', ('b2i', ('iand', a, b,
> + (('ior', ('ineg', ('b2i', a)), ('ineg', ('b2i', b))),
> +('ineg', ('b2i', ('ior', a, b,
> + (('ieq', ('ineg', ('b2i', a)), 0), ('inot', a)),
> + (('ieq', ('ineg', ('b2i', a)), -1), a),
> + (('ine', ('ineg', ('b2i', a)), 0), a),
Isn't this the same as the line you added above?
> + (('ine', ('ineg', ('b2i', a)), -1), ('inot', a)),
> +
> # Conversions
> (('i2b', ('b2i', a)), a),
> (('f2i32', ('ftrunc', a)), ('f2i32', a)),
> --
> 2.19.1
>
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Re: [Mesa-dev] [PATCH] mesa/glformats: Remove redundant helper _mesa_base_format_component_count
On 10/23/18 8:56 AM, Eduardo Lima Mitev wrote:
There exists _mesa_components_in_format() which already includes
all cases handled in _mesa_base_format_component_count().
I guess the idea here was that one function only covers 'base formats'
and other one all formats. But I guess none of the users verify if 'base
format' is sane this way? If this is the case and there are no regressions;
Reviewed-by: Tapani Pälli
---
src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
src/mesa/main/glformats.c | 27 ---
src/mesa/main/glformats.h | 3 ---
src/mesa/main/teximage.c | 4 ++--
4 files changed, 3 insertions(+), 33 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index ad3a47ef035..b286b231537 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1195,7 +1195,7 @@ set_write_disables(const struct intel_renderbuffer *irb,
* RGB we can treat alpha as not used and write whatever we like into it.
*/
const GLenum base_format = irb->Base.Base._BaseFormat;
- const int components = _mesa_base_format_component_count(base_format);
+ const int components = _mesa_components_in_format(base_format);
bool disables = false;
assert(components > 0);
diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index bbeb6034dd7..6cb3435dea2 100644
--- a/src/mesa/main/glformats.c
+++ b/src/mesa/main/glformats.c
@@ -1630,33 +1630,6 @@ _mesa_base_format_has_channel(GLenum base_format, GLenum
pname)
}
-/**
- * Returns the number of channels/components for a base format.
- */
-GLint
-_mesa_base_format_component_count(GLenum base_format)
-{
- switch (base_format) {
- case GL_LUMINANCE:
- case GL_RED:
- case GL_ALPHA:
- case GL_INTENSITY:
- case GL_DEPTH_COMPONENT:
- return 1;
- case GL_RG:
- case GL_LUMINANCE_ALPHA:
- case GL_DEPTH_STENCIL:
- return 2;
- case GL_RGB:
- return 3;
- case GL_RGBA:
- return 4;
- default:
- return -1;
- }
-}
-
-
/**
* If format is a generic compressed format, return the corresponding
* non-compressed format. For other formats, return the format as-is.
diff --git a/src/mesa/main/glformats.h b/src/mesa/main/glformats.h
index 5a21317159d..0aefdf50fef 100644
--- a/src/mesa/main/glformats.h
+++ b/src/mesa/main/glformats.h
@@ -119,9 +119,6 @@ _mesa_unpack_format_to_base_format(GLenum format);
extern GLboolean
_mesa_base_format_has_channel(GLenum base_format, GLenum pname);
-extern GLint
-_mesa_base_format_component_count(GLenum base_format);
-
extern GLenum
_mesa_generic_compressed_format_to_uncompressed_format(GLenum format);
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index d45854bd17f..6805b47c728 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -2407,8 +2407,8 @@ copytexture_error_check( struct gl_context *ctx, GLuint
dimensions,
if (_mesa_is_gles(ctx)) {
bool valid = true;
- if (_mesa_base_format_component_count(baseFormat) >
- _mesa_base_format_component_count(rb_base_format)) {
+ if (_mesa_components_in_format(baseFormat) >
+ _mesa_components_in_format(rb_base_format)) {
valid = false;
}
if (baseFormat == GL_DEPTH_COMPONENT ||
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