Re: [Mesa-dev] [RFC 0/2] Alternate default config mechanism
On 5/21/19 4:53 PM, Sumit Semwal wrote: Hello everyone, First up, my apologies on not being able to respond earlier; secondly, thanks very much for your review. On Wed, 15 May 2019 at 19:27, Emil Velikov wrote: Hi all, On Tue, 14 May 2019 at 08:18, Tapani Pälli wrote: On 5/13/19 6:52 PM, Haehnle, Nicolai wrote: This approach seems entirely incompatible with si_debug_options.h, and will be an absolute maintenance nightmare going forward for adding / removing options, because you're introducing a second location where options are defined. Quite frankly, this seems like a terrible idea as-is. If you really can't use XML for whatever reason, then please find some way of deriving both the tables here and the XML from the same single source of truth. I was looking at this yesterday and came up with same conclusion. We should have the options in one place. Currently libexpat is statically linked with Android >=O, maybe for such restricted environments we could just inline the xml as is at compile time and parse that later or alternatively (maybe cleaner) parse and generate default option cache already during compilation? I realise that jumping the "me too" train does not help much, so here are some alternative ideas. How about we first distil the reasons why this is a problem and what kind. Then explore independent solution for each one - as-is this seems like a one-size-fits-all approach. I totally agree that this seems like a rudimentary / ugly approach, and we can definitely improve upon it once the reasons are discussed. Some examples: - XML file may be inaccessible - the in-driver defaults should work(tm) Yes there are some app specific ones, yet neither(?) of these apps is present on Android - libexpat is not available, but libFOO is - investigate into a compat wrapper - cannot use external libraries (libexpat or equivalent) - static link AFAIU, in the Android space, it is a combination of some of the above: a. current Android doesn't allow GL drivers to access config files from the vendor partition: this is enforced via selinux policy. For point a, vendors can (and should) define their own policy rules regarding what file access and ioctl's are required. This is done by setting BOARD_SEPOLICY_DIRS in BoardConfig.mk file. That directory then contains all the necessary rules required for the particular driver to work. As example: BOARD_SEPOLICY_DIRS += device/samsung/tuna/sepolicy If a vendor wanted to use xml based configuration for Mesa it should be possible by setting a sepolicy rule so that particular library is able to access such file. Looking at Android Celadon selinux files, 'file_contexts' is probably the place to do it. b. Also, they had some concerns around how safe libexpat is vis-a-vis dual-loading, and that's where the concern around static linking came from. Alistair, could you please correct me if I am wrong, and if there are additional details on the need of this? // Tapani ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] nir_opt_copy_prop_vars doing the wrong thing
https://gitlab.freedesktop.org/airlied/mesa/tree/nir-copy-props-cast-test
Contains a unit test that triggers it for me.
Dave.
On Sat, 11 May 2019 at 09:54, Jason Ekstrand wrote:
>
> We have unit tests for that pass. Maybe you could write one which exercises
> the issue? It'd help in debugging.
>
> On Thu, May 9, 2019 at 8:12 PM Dave Airlie wrote:
>>
>> I've got a bunch of cases where copy prop vars is getting things wrong
>> around casts, it finds a store to an vec2 but ends up with the
>> writemask staying at 0x3 but the item being store being a single
>> 64-bit.
>>
>> Debug is attached below.
>>
>> Dave.
>>
>> nir_lower_memcpy_deref
>> shader: MESA_SHADER_KERNEL
>> local-size: 0, 0, 0 (variable)
>> shared-size: 1
>> inputs: 16
>> outputs: 0
>> uniforms: 0
>> shared: 0
>> decl_var shader_in INTERP_MODE_NONE uint64_t @0 (0.x, 0, 0)
>> decl_var shader_in INTERP_MODE_NONE uint64_t @1 (1.x, 8, 0)
>> decl_function __wrapped_vload2_private (0 params)
>>
>> impl __wrapped_vload2_private {
>> decl_var INTERP_MODE_NONE uint[3] @2
>> block block_0:
>> /* preds: */
>> vec1 64 ssa_0 = deref_var &@0 (shader_in uint64_t)
>> vec1 64 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */
>> vec1 64 ssa_2 = deref_var &@1 (shader_in uint64_t)
>> vec1 64 ssa_3 = intrinsic load_deref (ssa_2) (0) /* access=0 */
>> vec1 64 ssa_4 = load_const (0x 0 /* 0.00 */)
>> vec1 64 ssa_5 = load_const (0x 0 /* 0.00 */)
>> vec1 64 ssa_6 = deref_cast (uint *)ssa_1 (global uint)
>> vec1 64 ssa_7 = deref_cast (uvec2 *)ssa_3 (global uvec2)
>> vec1 32 ssa_8 = intrinsic load_deref (ssa_6) (0) /* access=0 */
>> vec1 64 ssa_9 = deref_var &@2 (function_temp uint[3])
>> vec1 64 ssa_10 = deref_cast (uint[3] *)ssa_9 (function_temp uint[3])
>> vec1 64 ssa_11 = load_const (0x 0 /* 0.00 */)
>> vec1 64 ssa_13 = load_const (0x 0 /* 0.00 */)
>> vec1 64 ssa_14 = deref_array &(*ssa_9)[0] (function_temp uint) /* &@2[0]
>> */
>> intrinsic store_deref (ssa_14, ssa_8) (1, 0) /* wrmask=x */ /* access=0
>> */
>> vec1 64 ssa_15 = deref_cast (uint *)ssa_1 (global uint)
>> vec1 64 ssa_16 = load_const (0x 1 /* 0.00 */)
>> vec1 64 ssa_17 = deref_ptr_as_array &(*ssa_15)[1] (global uint) /*
>> &(*(uint *)ssa_1)[1] */
>> vec1 32 ssa_18 = intrinsic load_deref (ssa_17) (0) /* access=0 */
>> vec1 64 ssa_19 = deref_var &@2 (function_temp uint[3])
>> vec1 64 ssa_20 = deref_cast (uint[3] *)ssa_19 (function_temp uint[3])
>> vec1 64 ssa_21 = load_const (0x 0 /* 0.00 */)
>> vec1 64 ssa_23 = load_const (0x 1 /* 0.00 */)
>> vec1 64 ssa_24 = deref_array &(*ssa_19)[1] (function_temp uint) /*
>> &@2[1] */
>> intrinsic store_deref (ssa_24, ssa_18) (1, 0) /* wrmask=x */ /* access=0
>> */
>> vec1 64 ssa_25 = deref_cast (uint *)ssa_1 (global uint)
>> vec1 64 ssa_26 = load_const (0x 2 /* 0.00 */)
>> vec1 64 ssa_27 = deref_ptr_as_array &(*ssa_25)[2] (global uint) /*
>> &(*(uint *)ssa_1)[2] */
>> vec1 32 ssa_28 = intrinsic load_deref (ssa_27) (0) /* access=0 */
>> vec1 64 ssa_29 = deref_var &@2 (function_temp uint[3])
>> vec1 64 ssa_30 = deref_cast (uint[3] *)ssa_29 (function_temp uint[3])
>> vec1 64 ssa_31 = load_const (0x 0 /* 0.00 */)
>> vec1 64 ssa_33 = load_const (0x 2 /* 0.00 */)
>> vec1 64 ssa_34 = deref_array &(*ssa_29)[2] (function_temp uint) /*
>> &@2[2] */
>> intrinsic store_deref (ssa_34, ssa_28) (1, 0) /* wrmask=x */ /* access=0
>> */
>> vec1 64 ssa_35 = deref_cast (uvec2 *)ssa_14 (function_temp uvec2)
>> vec2 32 ssa_37 = intrinsic load_deref (ssa_35) (0) /* access=0 */
>> intrinsic store_deref (ssa_7, ssa_37) (3, 0) /* wrmask=xy */ /* access=0
>> */
>> vec1 64 ssa_38 = deref_cast (uvec2 *)ssa_24 (function_temp uvec2)
>> vec2 32 ssa_40 = intrinsic load_deref (ssa_38) (0) /* access=0 */
>> vec1 64 ssa_41 = deref_cast (uvec2 *)ssa_3 (global uvec2)
>> vec1 64 ssa_42 = load_const (0x 1 /* 0.00 */)
>> vec1 64 ssa_43 = deref_ptr_as_array &(*ssa_41)[1] (global uvec2)
>> /* &(*(uvec2 *)ssa_3)[1] */
>> intrinsic store_deref (ssa_43, ssa_40) (3, 0) /* wrmask=xy */ /*
>> access=0 */
>> /* succs: block_1 */
>> block block_1:
>> }
>>
>> nir_opt_copy_prop_vars
>> ## nir_copy_prop_vars_impl for __wrapped_vload2_private
>> # block0
>>
>> vec1 64 ssa_0 = deref_var (shader_in uint64_t)
>> vec1 64 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */
>> uint64_t unnamed: ssa_1
>>
>> vec1 64 ssa_2 = deref_var (shader_in uint64_t)
>> vec1 64 ssa_3 = intrinsic load_deref (ssa_2) (0) /* access=0 */
>> uint64_t unnamed: ssa_1
>> uint64_t unnamed: ssa_3
>>
>> vec1 64 ssa_6 = deref_cast (uint *)ssa_1 (global uint)
>> vec1 64 ssa_7 = deref_cast (uvec2 *)ssa_3
Re: [Mesa-dev] [PATCH] i965/tex: ignore the diff between GL_TEXTURE_2D and GL_TEXTURE_RECTANGLE
On 5/21/19 4:36 AM, Olivier Fourdan wrote: > Hi all, > > On Thu, Jul 19, 2018 at 12:08 PM andrey simiklit > wrote: >>> Ugh... not so good. According to Oliver on the bug, this just make the >>> assert go away and doesn't actually fix anything. Likely this is needed >>> but not sufficient. >> >> So as far as I understand Oliver found the bad commit in xorg glamor: >> https://bugs.freedesktop.org/show_bug.cgi?id=107287 >> >> So at the moment we should fix just this "assertion" issue for Intel because >> "rendering" issue came from xorg/glamor and there is no "rendering" issue in >> Intel part. >> Please correct me if I incorrect. > > Reviving an old thread/patch here. > > Andrey, I reckon your patch here is still much needed as it fixes the > assert() issue: > > intel_mipmap_tree.c:1301: intel_miptree_match_image: Assertion > `image->TexObject->Target == mt->target' failed. > > Which is still occurring even with current master. > > My patch was to fix the rendering issue (landed a while ago before > 18.1 iirc), but yours was never merged and is still needed, I can > reproduce the assert() at will with the reproducer from > https://bugs.freedesktop.org/show_bug.cgi?id=107117 > > Jason, can we reconsider Andrii's patch? It still applies cleanly > (https://patchwork.freedesktop.org/patch/237490/) Looking at the patch and the "Simple reproducer" in the bug, I think this just papers over the issue. It seems like the problem is somewhere down inside the driver's handling of glXBindTexImageEXT. My best guess is that the texture is GL_TEXTURE_2D but the miptree backing it is GL_TEXTURE_RECTANGLE. It seems that the glXBindTexImageEXT handling should mark the miptree as GL_TEXTURE_2D when binding the image to a texture that is GL_TEXTURE_2D. Or is that not possible for some non-obvious reason? > Cheers, > Olivier > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2] radv: implement VK_EXT_sample_locations
So this does not seem to use the sample locations during layout transitions?
AFAIK those are needed for e.g. HTILE decompression as it is based on
equations somehow.
On Thu, May 16, 2019 at 11:51 AM Samuel Pitoiset
wrote:
>
> Basically, this extension allows applications to use custom
> sample locations. It doesn't support variable sample locations
> during subpass. Note that we don't have to upload the user
> sample locations because the spec doesn't allow this.
>
> Only enabled on VI+ because it's untested on older chips.
>
> v2: - change sampleLocationCoordinateRange[1] to 0.9375
> - compute and emit PA_SC_CENTROID_PRIORITY_{0,1}
> - rebased on top of master
> - some cleanups
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 223 ++
> src/amd/vulkan/radv_device.c | 27
> src/amd/vulkan/radv_extensions.py | 1 +
> src/amd/vulkan/radv_pipeline.c| 30
> src/amd/vulkan/radv_private.h | 26 +++-
> 5 files changed, 300 insertions(+), 7 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
> b/src/amd/vulkan/radv_cmd_buffer.c
> index 4f592bc7f68..fb79c1c6713 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -105,6 +105,7 @@ radv_bind_dynamic_state(struct radv_cmd_buffer
> *cmd_buffer,
> dest->viewport.count = src->viewport.count;
> dest->scissor.count = src->scissor.count;
> dest->discard_rectangle.count = src->discard_rectangle.count;
> + dest->sample_location.count = src->sample_location.count;
>
> if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
> if (memcmp(>viewport.viewports,
> >viewport.viewports,
> @@ -192,6 +193,22 @@ radv_bind_dynamic_state(struct radv_cmd_buffer
> *cmd_buffer,
> }
> }
>
> + if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
> + if (dest->sample_location.per_pixel !=
> src->sample_location.per_pixel ||
> + dest->sample_location.grid_size.width !=
> src->sample_location.grid_size.width ||
> + dest->sample_location.grid_size.height !=
> src->sample_location.grid_size.height ||
> + memcmp(>sample_location.locations,
> + >sample_location.locations,
> + src->sample_location.count *
> sizeof(VkSampleLocationEXT))) {
> + dest->sample_location.per_pixel =
> src->sample_location.per_pixel;
> + dest->sample_location.grid_size =
> src->sample_location.grid_size;
> + typed_memcpy(dest->sample_location.locations,
> +src->sample_location.locations,
> +src->sample_location.count);
> + dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
> + }
> + }
> +
> cmd_buffer->state.dirty |= dest_mask;
> }
>
> @@ -632,6 +649,190 @@ radv_emit_descriptor_pointers(struct radv_cmd_buffer
> *cmd_buffer,
> }
> }
>
> +/**
> + * Convert the user sample locations to hardware sample locations (the values
> + * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
> + */
> +static void
> +radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
> + uint32_t x, uint32_t y, VkOffset2D *sample_locs)
> +{
> + uint32_t x_offset = x % state->grid_size.width;
> + uint32_t y_offset = y % state->grid_size.height;
> + uint32_t num_samples = (uint32_t)state->per_pixel;
> + VkSampleLocationEXT *user_locs;
> + uint32_t pixel_offset;
> +
> + pixel_offset = (x_offset + y_offset * state->grid_size.width) *
> num_samples;
> +
> + assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
> + user_locs = >locations[pixel_offset];
> +
> + for (uint32_t i = 0; i < num_samples; i++) {
> + float shifted_pos_x = user_locs[i].x - 0.5;
> + float shifted_pos_y = user_locs[i].y - 0.5;
> +
> + int32_t scaled_pos_x = floor(shifted_pos_x * 16);
> + int32_t scaled_pos_y = floor(shifted_pos_y * 16);
> +
> + sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
> + sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
> + }
> +}
> +
> +/**
> + * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
> + * locations.
> + */
> +static void
> +radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
> + uint32_t *sample_locs_pixel)
> +{
> + for (uint32_t i = 0; i < num_samples; i++) {
> + uint32_t sample_reg_idx = i / 4;
> + uint32_t sample_loc_idx = i % 4;
> + int32_t pos_x = sample_locs[i].x;
> + int32_t pos_y = sample_locs[i].y;
> +
> + uint32_t shift_x = 8 * sample_loc_idx;
> + uint32_t shift_y =
Re: [Mesa-dev] [PATCH 2/4] radv: clean up the sample locations codebase
r-b
On Thu, May 16, 2019 at 11:50 AM Samuel Pitoiset
wrote:
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 2 +-
> src/amd/vulkan/radv_pipeline.c | 2 +-
> src/amd/vulkan/radv_private.h| 4 +-
> src/amd/vulkan/si_cmd_buffer.c | 166 ++-
> 4 files changed, 76 insertions(+), 98 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
> b/src/amd/vulkan/radv_cmd_buffer.c
> index e4e5966da54..4f592bc7f68 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -669,7 +669,7 @@ radv_update_multisample_state(struct radv_cmd_buffer
> *cmd_buffer,
>
> radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
> ms->pa_sc_mode_cntl_0);
>
> - radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
> + radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
>
> /* GFX9: Flush DFSM when the AA mode changes. */
> if (cmd_buffer->device->dfsm_allowed) {
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index c89a6f139ba..56fd65bec29 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -1128,7 +1128,7 @@ radv_pipeline_init_multisample_state(struct
> radv_pipeline *pipeline,
> S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
> S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
> ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples)
> |
> -
> S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
> +
> S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
> S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /*
> CM_R_028BE0_PA_SC_AA_CONFIG */
> ms->pa_sc_mode_cntl_1 |=
> S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
> if (ps_iter_samples > 1)
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index 9563e86a680..7834a505562 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -1212,8 +1212,8 @@ void radv_cmd_buffer_clear_subpass(struct
> radv_cmd_buffer *cmd_buffer);
> void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
> void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
> void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
> -void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int
> nr_samples);
> -unsigned radv_cayman_get_maxdist(int log_samples);
> +void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int
> nr_samples);
> +unsigned radv_get_default_max_sample_dist(int log_samples);
> void radv_device_init_msaa(struct radv_device *device);
>
> void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
> diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
> index b93cd88a1d1..56d7a9a3682 100644
> --- a/src/amd/vulkan/si_cmd_buffer.c
> +++ b/src/amd/vulkan/si_cmd_buffer.c
> @@ -1300,144 +1300,122 @@ void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
> *cmd_buffer)
>
> /* For MSAA sample positions. */
> #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
> - (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
> - (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) |
> \
> - (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) |
> \
> + unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
> +(((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
> +(((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
> (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
>
> -
> -/* 2xMSAA
> - * There are two locations (4, 4), (-4, -4). */
> -const uint32_t eg_sample_locs_2x[4] = {
> - FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
> - FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
> - FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
> - FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
> -};
> -const unsigned eg_max_dist_2x = 4;
> -/* 4xMSAA
> - * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
> -const uint32_t eg_sample_locs_4x[4] = {
> - FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
> - FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
> - FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
> - FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
> -};
> -const unsigned eg_max_dist_4x = 6;
> -
> -/* Cayman 8xMSAA */
> -static const uint32_t cm_sample_locs_8x[] = {
> - FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
> - FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
> - FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
> - FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
> - FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
> -
Re: [Mesa-dev] [PATCH] radv: do not reset query pool during creation
r-b On Tue, May 21, 2019 at 1:36 PM Samuel Pitoiset wrote: > > From the Vulkan spec 1.1.108: >"After query pool creation, each query must be reset before > it is used." > > So, the driver doesn't need to do this at creation time. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_query.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c > index 520711e4864..be1cf589d63 100644 > --- a/src/amd/vulkan/radv_query.c > +++ b/src/amd/vulkan/radv_query.c > @@ -1035,8 +1035,6 @@ VkResult radv_CreateQueryPool( > struct radv_query_pool *pool = vk_alloc2(>alloc, pAllocator, >sizeof(*pool), 8, > > VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); > - uint32_t initial_value = pCreateInfo->queryType == > VK_QUERY_TYPE_TIMESTAMP > -? TIMESTAMP_NOT_READY : 0; > > if (!pool) > return vk_error(device->instance, > VK_ERROR_OUT_OF_HOST_MEMORY); > @@ -1082,7 +1080,6 @@ VkResult radv_CreateQueryPool( > vk_free2(>alloc, pAllocator, pool); > return vk_error(device->instance, > VK_ERROR_OUT_OF_DEVICE_MEMORY); > } > - memset(pool->ptr, initial_value, pool->size); > > *pQueryPool = radv_query_pool_to_handle(pool); > return VK_SUCCESS; > -- > 2.21.0 > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [ANNOUNCE] mesa 19.0.5
Hi List, I'd like to announce the availability of mesa 19.0.5. Just as a reminder the plan is to have one more release of the 19.0 series in two weeks, but that is subject to change base on the 19.1 release progress. Things have slowed back down from the last release, which is good for this late in the series. No one area has received too much work, with a little bit sprinkled in here and there in both core code and drivers. Dylan Shortlog Caio Marcelo de Oliveira Filho (2): nir: Fix nir_opt_idiv_const when negatives are involved nir: Fix clone of nir_variable state slots Charmaine Lee (2): st/mesa: purge framebuffers with current context after unbinding winsys buffers mesa: unreference current winsys buffers when unbinding winsys buffers Dylan Baker (5): docs: Add SHA256 sums for mesa 19.0.4 cherry-ignore: add patches for panfrost cherry-ignore: Add more 19.1 patches bump version to 19.0.5 docs: Add release notes for 19.0.5 Eric Engestrom (1): meson: expose glapi through osmesa Gert Wollny (2): softpipe/buffer: load only as many components as the the buffer resource type provides Revert "softpipe/buffer: load only as many components as the the buffer resource type provides" Ian Romanick (1): Revert "nir: add late opt to turn inot/b2f combos back to bcsel" Jason Ekstrand (3): intel/fs/ra: Only add dest interference to sources that exist intel/fs/ra: Stop adding RA interference to too many SENDS nodes anv: Only consider minSampleShading when sampleShadingEnable is set Józef Kucia (1): radv: clear vertex bindings while resetting command buffer Kenneth Graunke (1): i965: Fix memory leaks in brw_upload_cs_work_groups_surface(). Leo Liu (1): winsys/amdgpu: add VCN JPEG to no user fence group Lionel Landwerlin (1): anv: Use corresponding type from the vector allocation Marek Olšák (1): st/mesa: fix 2 crashes in st_tgsi_lower_yuv Nanley Chery (1): anv: Fix some depth buffer sampling cases on ICL+ Samuel Pitoiset (1): radv: add a workaround for Monster Hunter World and LLVM 7&8 git tag: mesa-19.0.5 https://mesa.freedesktop.org/archive/mesa-19.0.5.tar.gz MD5: 5b7507af83b43431a4185b1848f8f2a1 mesa-19.0.5.tar.gz SHA1: 5e0ef8d6426c91f8662e8a7f42abd03716b31fdc mesa-19.0.5.tar.gz SHA256: b6e6b78c23bec15d1e7887c78b7ad00ce395ea1b20ad8aab6ce441f55f724e70 mesa-19.0.5.tar.gz SHA512: fbc29ed77501ec44b029e18739f97aae0de319d8bdd5ffcfd4d01549ee2bd9b9f2e2a6ef35379ea2698e084e1589eb43d1ae7b75200c254167f0f26ba9c22f25 mesa-19.0.5.tar.gz PGP: https://mesa.freedesktop.org/archive/mesa-19.0.5.tar.gz.sig https://mesa.freedesktop.org/archive/mesa-19.0.5.tar.xz MD5: 1509a3251d459fd8b6fadf9329669dc1 mesa-19.0.5.tar.xz SHA1: 647352d5989d3ca9b5c83fe06ed1d84f341f6ad5 mesa-19.0.5.tar.xz SHA256: 6aecb7f67c136768692fb3c33a54196186c6c4fcafab7973516a355e1a54f831 mesa-19.0.5.tar.xz SHA512: aecd5ee54ac0316d5e318dbea0abdc06f23e67d75d36eb82d6cf6a396c9e850e1ccf4fa8815f8c4097b6039ebb1524673189350cbfd4b766ce75ce17c26d9d8d mesa-19.0.5.tar.xz PGP: https://mesa.freedesktop.org/archive/mesa-19.0.5.tar.xz.sig signature.asc Description: signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radeonsi: fix a regression in si_rebind_buffer
This fixes the issues I had when running Outast via vigl, thanks
Tested-By: Gert Wollny
On Di, 2019-05-21 at 14:34 -0400, Marek Olšák wrote:
> From: Marek Olšák
>
> Don't update non-buffer images.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110701
> Fixes: 78e35df52aa2f7d770f929a0866a0faa89c261a9 "radeonsi: update
> buffer descriptors in all contexts after buffer invalidation"
> Cc: 19.1
> ---
> src/gallium/drivers/radeonsi/si_descriptors.c | 12
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
> b/src/gallium/drivers/radeonsi/si_descriptors.c
> index 84c9d674981..1cb0ac93caa 100644
> --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> @@ -1698,21 +1698,22 @@ void si_rebind_buffer(struct si_context
> *sctx, struct pipe_resource *buf)
> for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
> struct si_samplers *samplers =
> >samplers[shader];
> struct si_descriptors *descs =
> si_sampler_and_image_descriptors(sctx,
> shader);
> unsigned mask = samplers->enabled_mask;
>
> while (mask) {
> unsigned i = u_bit_scan();
> struct pipe_resource *buffer =
> samplers->views[i]->texture;
>
> - if (buffer && (!buf || buffer == buf))
> {
> + if (buffer && buffer->target ==
> PIPE_BUFFER &&
> + (!buf || buffer == buf)) {
> unsigned desc_slot =
> si_get_sampler_slot(i);
>
> si_set_buf_desc_address(si_reso
> urce(buffer),
> sampler
> s->views[i]->u.buf.offset,
> descs-
> >list + desc_slot * 16 + 4);
> sctx->descriptors_dirty |=
> 1u <<
> si_sampler_and_image_descriptors_idx(shader);
>
> radeon_add_to_gfx_buffer_list_c
> heck_mem(
> sctx,
> si_resource(buffer),
> @@ -1728,21 +1729,22 @@ void si_rebind_buffer(struct si_context
> *sctx, struct pipe_resource *buf)
> for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
> struct si_images *images =
> >images[shader];
> struct si_descriptors *descs =
> si_sampler_and_image_descriptors(sctx,
> shader);
> unsigned mask = images->enabled_mask;
>
> while (mask) {
> unsigned i = u_bit_scan();
> struct pipe_resource *buffer = images-
> >views[i].resource;
>
> - if (buffer && (!buf || buffer == buf))
> {
> + if (buffer && buffer->target ==
> PIPE_BUFFER &&
> + (!buf || buffer == buf)) {
> unsigned desc_slot =
> si_get_image_slot(i);
>
> if (images->views[i].access &
> PIPE_IMAGE_ACCESS_WRITE)
> si_mark_image_range_val
> id(>views[i]);
>
> si_set_buf_desc_address(si_reso
> urce(buffer),
> images-
> >views[i].u.buf.offset,
> descs-
> >list + desc_slot * 8 + 4);
> sctx->descriptors_dirty |=
> 1u <<
> si_sampler_and_image_descriptors_idx(shader);
> @@ -1759,21 +1761,22 @@ void si_rebind_buffer(struct si_context
> *sctx, struct pipe_resource *buf)
> /* Bindless texture handles */
> if (!buffer || buffer->texture_handle_allocated) {
> struct si_descriptors *descs =
> >bindless_descriptors;
>
> util_dynarray_foreach(>resident_tex_handles,
> struct si_texture_handle *,
> tex_handle) {
> struct pipe_sampler_view *view = (*tex_handle)-
> >view;
> unsigned desc_slot = (*tex_handle)->desc_slot;
> struct pipe_resource *buffer = view->texture;
>
> - if (buffer && (!buf || buffer == buf)) {
> + if (buffer && buffer->target == PIPE_BUFFER &&
> + (!buf || buffer == buf)) {
> si_set_buf_desc_address(si_resource(buf
> fer),
> view-
> >u.buf.offset,
>
[Mesa-dev] [Bug 110707] llvm-config: unknown component name: x86asmprinter
https://bugs.freedesktop.org/show_bug.cgi?id=110707 --- Comment #1 from Roland Scheidegger --- Yes this component apparently disappeared. By the looks of it a lot of the code got moved into MCTargetDesc, but I'm not sure yet if it actually needs another lib added instead or if it can just be removed. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] radeonsi: update buffer descriptors in all contexts after buffer invalidation
It should be fixed with: "[PATCH] radeonsi: fix a regression in
si_rebind_buffer"
Marek
On Tue, May 21, 2019, 6:24 AM Mike Lothian wrote:
> Can someone with access revert from master until this is fixed? It's
> been broken for 3 days now
>
> On Tue, 21 May 2019 at 09:01, Juan A. Suarez Romero
> wrote:
> >
> > On Tue, 2019-05-21 at 09:36 +0200, Gert Wollny wrote:
> > > Hi Marek,
> > >
> > > it seems that this patch is causing a few issues [1], any idea what is
> > > going on? Maybe it is best to revert the patch for now?
> > >
> > > Best,
> > > Gert
> > >
> >
> >
> > As this is commit is causing issues, I'm withdrawing it out of 19.1
> branch.
> >
> > If later a fix is provided, let me know so I can re-add it to the branch,
> > together with the fix.
> >
> > Thanks.
> >
> > J.A.
> >
> > > [1] https://bugzilla.freedesktop.org/show_bug.cgi?id=110701
> > >
> > > On Fr, 2019-05-10 at 01:19 -0400, Marek Olšák wrote:
> > > > From: Marek Olšák
> > > >
> > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108824
> > > >
> > > > Cc: 19.1
> > > > ---
> > > > src/gallium/drivers/radeonsi/si_descriptors.c | 94 -
> > > > --
> > > > src/gallium/drivers/radeonsi/si_pipe.h| 2 +
> > > > src/gallium/drivers/radeonsi/si_state_draw.c | 9 +-
> > > > 3 files changed, 72 insertions(+), 33 deletions(-)
> > > >
> > > > diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
> > > > b/src/gallium/drivers/radeonsi/si_descriptors.c
> > > > index 744fc9a15d7..6a4dcacc0f3 100644
> > > > --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> > > > +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> > > > @@ -1580,242 +1580,272 @@ void
> > > > si_update_needs_color_decompress_masks(struct si_context *sctx)
> > > > si_samplers_update_needs_color_decompress_mask(
> > > > > samplers[i]);
> > > > si_images_update_needs_color_decompress_mask(
> > > > > images[i]);
> > > > si_update_shader_needs_decompress_mask(sctx, i);
> > > > }
> > > >
> > > > si_resident_handles_update_needs_color_decompress(sctx);
> > > > }
> > > >
> > > > /* BUFFER DISCARD/INVALIDATION */
> > > >
> > > > -/** Reset descriptors of buffer resources after \p buf has been
> > > > invalidated. */
> > > > +/* Reset descriptors of buffer resources after \p buf has been
> > > > invalidated.
> > > > + * If buf == NULL, reset all descriptors.
> > > > + */
> > > > static void si_reset_buffer_resources(struct si_context *sctx,
> > > > struct si_buffer_resources
> > > > *buffers,
> > > > unsigned descriptors_idx,
> > > > unsigned slot_mask,
> > > > struct pipe_resource *buf,
> > > > enum radeon_bo_priority priority)
> > > > {
> > > > struct si_descriptors *descs =
> > > > > descriptors[descriptors_idx];
> > > > unsigned mask = buffers->enabled_mask & slot_mask;
> > > >
> > > > while (mask) {
> > > > unsigned i = u_bit_scan();
> > > > - if (buffers->buffers[i] == buf) {
> > > > - si_set_buf_desc_address(si_resource(buf),
> > > > buffers->offsets[i],
> > > > + struct pipe_resource *buffer = buffers->buffers[i];
> > > > +
> > > > + if (buffer && (!buf || buffer == buf)) {
> > > > + si_set_buf_desc_address(si_resource(buffer),
> > > > buffers->offsets[i],
> > > > descs->list + i*4);
> > > > sctx->descriptors_dirty |= 1u <<
> > > > descriptors_idx;
> > > >
> > > > radeon_add_to_gfx_buffer_list_check_mem(sctx,
> > > > - si_reso
> > > > urce(buf),
> > > > + si_reso
> > > > urce(buffer),
> > > > buffers
> > > > ->writable_mask & (1u << i) ?
> > > >
> > > > RADEON_USAGE_READWRITE :
> > > >
> > > > RADEON_USAGE_READ,
> > > > priorit
> > > > y, true);
> > > > }
> > > > }
> > > > }
> > > >
> > > > -/* Update all resource bindings where the buffer is bound, including
> > > > +/* Update all buffer bindings where the buffer is bound, including
> > > > * all resource descriptors. This is invalidate_buffer without
> > > > - * the invalidation. */
> > > > + * the invalidation.
> > > > + *
> > > > + * If buf == NULL, update all buffer bindings.
> > > > + */
> > > > void si_rebind_buffer(struct si_context *sctx, struct pipe_resource
> > > > *buf)
> > > > {
> > > > struct si_resource *buffer = si_resource(buf);
> > > > unsigned i, shader;
> > > > unsigned num_elems = sctx->vertex_elements ?
> > > >sctx->vertex_elements->count :
> > > > 0;
> > > >
> > > > /*
[Mesa-dev] [PATCH] radeonsi: fix a regression in si_rebind_buffer
From: Marek Olšák
Don't update non-buffer images.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110701
Fixes: 78e35df52aa2f7d770f929a0866a0faa89c261a9 "radeonsi: update buffer
descriptors in all contexts after buffer invalidation"
Cc: 19.1
---
src/gallium/drivers/radeonsi/si_descriptors.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 84c9d674981..1cb0ac93caa 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1698,21 +1698,22 @@ void si_rebind_buffer(struct si_context *sctx, struct
pipe_resource *buf)
for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
struct si_samplers *samplers = >samplers[shader];
struct si_descriptors *descs =
si_sampler_and_image_descriptors(sctx, shader);
unsigned mask = samplers->enabled_mask;
while (mask) {
unsigned i = u_bit_scan();
struct pipe_resource *buffer =
samplers->views[i]->texture;
- if (buffer && (!buf || buffer == buf)) {
+ if (buffer && buffer->target == PIPE_BUFFER &&
+ (!buf || buffer == buf)) {
unsigned desc_slot =
si_get_sampler_slot(i);
si_set_buf_desc_address(si_resource(buffer),
samplers->views[i]->u.buf.offset,
descs->list +
desc_slot * 16 + 4);
sctx->descriptors_dirty |=
1u <<
si_sampler_and_image_descriptors_idx(shader);
radeon_add_to_gfx_buffer_list_check_mem(
sctx, si_resource(buffer),
@@ -1728,21 +1729,22 @@ void si_rebind_buffer(struct si_context *sctx, struct
pipe_resource *buf)
for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
struct si_images *images = >images[shader];
struct si_descriptors *descs =
si_sampler_and_image_descriptors(sctx, shader);
unsigned mask = images->enabled_mask;
while (mask) {
unsigned i = u_bit_scan();
struct pipe_resource *buffer =
images->views[i].resource;
- if (buffer && (!buf || buffer == buf)) {
+ if (buffer && buffer->target == PIPE_BUFFER &&
+ (!buf || buffer == buf)) {
unsigned desc_slot =
si_get_image_slot(i);
if (images->views[i].access &
PIPE_IMAGE_ACCESS_WRITE)
si_mark_image_range_valid(>views[i]);
si_set_buf_desc_address(si_resource(buffer),
images->views[i].u.buf.offset,
descs->list +
desc_slot * 8 + 4);
sctx->descriptors_dirty |=
1u <<
si_sampler_and_image_descriptors_idx(shader);
@@ -1759,21 +1761,22 @@ void si_rebind_buffer(struct si_context *sctx, struct
pipe_resource *buf)
/* Bindless texture handles */
if (!buffer || buffer->texture_handle_allocated) {
struct si_descriptors *descs = >bindless_descriptors;
util_dynarray_foreach(>resident_tex_handles,
struct si_texture_handle *, tex_handle) {
struct pipe_sampler_view *view = (*tex_handle)->view;
unsigned desc_slot = (*tex_handle)->desc_slot;
struct pipe_resource *buffer = view->texture;
- if (buffer && (!buf || buffer == buf)) {
+ if (buffer && buffer->target == PIPE_BUFFER &&
+ (!buf || buffer == buf)) {
si_set_buf_desc_address(si_resource(buffer),
view->u.buf.offset,
descs->list +
desc_slot * 16 + 4);
(*tex_handle)->desc_dirty = true;
sctx->bindless_descriptors_dirty = true;
[Mesa-dev] [Bug 110716] SWR doesn't work with OSMesa
https://bugs.freedesktop.org/show_bug.cgi?id=110716 --- Comment #4 from Chuck Atkins --- > Comment # 1 on bug 110716 from Krzysztof Raszkowski > I've tried to reproduce it with master top mesa but without success (works > fine). What is exact version of mesa you've build? master as of this afternoon, 810b95e, > And one comment to autotools->meson change. With autotools default build mode > was without asserts. With meson default buildtype is debugoptimized. > To have the same buildtype as it was in autotools please add > --buildtype=release parameter to meson. The full configuration I'm using, basically trying to build bare-bones GLX and OSMesa libraries that only contain software OpenGL renderers: meson --buildtype=release -Dprefix=/path/to/install/master -Dglvnd=false -Dgallium-nine=false -Dgallium-omx=disabled -Dgallium-opencl=disabled -Dgallium-va=false -Dgallium-vdpau=false -Dgallium-xa=false -Dgallium-xvmc=false -Dvulkan-drivers= -Dosmesa=gallium -Dglx=gallium-xlib -Degl=false -Dgbm=false -Dopengl=true -Dgles1=false -Dgles2=false -Dshared-glapi=true -Dllvm=true -Dswr-arches=avx2 -Dplatforms=x11,surfaceless -Dgallium-drivers=swrast,swr -Ddri-drivers= /path/to/source/master If I do a release build to silence the assert then I get a segfault. Note that release or debug, swr works with glx via libGL.so and segfaults when using libOSMesa.so -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 110697] glXWaitForMscOML and glXWaitVideoSyncSGI may block indefinitely
https://bugs.freedesktop.org/show_bug.cgi?id=110697 QwertyChouskie changed: What|Removed |Added CC||asdfghrbljz...@outlook.com --- Comment #4 from QwertyChouskie --- Just to clarify, is this a problem with all versions of Mesa or just 19.0+? -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 110716] SWR doesn't work with OSMesa
https://bugs.freedesktop.org/show_bug.cgi?id=110716 --- Comment #3 from Krzysztof Raszkowski --- (In reply to Eric Engestrom from comment #2) > (In reply to Krzysztof Raszkowski from comment #1) > > And one comment to autotools->meson change. With autotools default build > > mode was without asserts. With meson default buildtype is debugoptimized. > > To have the same buildtype as it was in autotools please add > > --buildtype=release parameter to meson. > > I believe the point of this bug report is to fix the bug, not to silence the > assert() reporting it ;) > > Either the assert is correct and there's a bug that needs to be fixed, or > the assert is wrong and it needs to be fixed. You're absolutely right. That's why I'm asking about exact version of mesa. Second part of my response is only explanation about the difference between autotools and meson. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 110716] SWR doesn't work with OSMesa
https://bugs.freedesktop.org/show_bug.cgi?id=110716 --- Comment #2 from Eric Engestrom --- (In reply to Krzysztof Raszkowski from comment #1) > And one comment to autotools->meson change. With autotools default build > mode was without asserts. With meson default buildtype is debugoptimized. > To have the same buildtype as it was in autotools please add > --buildtype=release parameter to meson. I believe the point of this bug report is to fix the bug, not to silence the assert() reporting it ;) Either the assert is correct and there's a bug that needs to be fixed, or the assert is wrong and it needs to be fixed. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 110716] SWR doesn't work with OSMesa
https://bugs.freedesktop.org/show_bug.cgi?id=110716 --- Comment #1 from Krzysztof Raszkowski --- Hi Chuck, thanks for reporting this bug. I've tried to reproduce it with master top mesa but without success (works fine). What is exact version of mesa you've build? And one comment to autotools->meson change. With autotools default build mode was without asserts. With meson default buildtype is debugoptimized. To have the same buildtype as it was in autotools please add --buildtype=release parameter to meson. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [ANNOUNCE] mesa 19.1.0-rc3
Hello, list. The third release candidate for Mesa 19.1.0 is now available. Remind that right now there are two bugs blocking the final release: #110302 - [bisected][regression] piglit egl-create-pbuffer-surface and egl-gl-colorspace regressions #110357 - [REGRESSION] [BISECTED] [OpenGL CTS] cts-runner --type=gl46 fails in new attempted "41" configuration Caio Marcelo de Oliveira Filho (2): nir: Fix nir_opt_idiv_const when negatives are involved nir: Fix clone of nir_variable state slots Charmaine Lee (2): st/mesa: purge framebuffers with current context after unbinding winsys buffers mesa: unreference current winsys buffers when unbinding winsys buffers Dave Airlie (1): glsl: init packed in more constructors. Eric Engestrom (2): util/os_file: always use the 'grow' mechanism meson: expose glapi through osmesa Gert Wollny (1): Revert "softpipe/buffer: load only as many components as the the buffer resource type provides" Ian Romanick (1): Revert "nir: add late opt to turn inot/b2f combos back to bcsel" Jason Ekstrand (5): intel/fs/ra: Only add dest interference to sources that exist intel/fs/ra: Stop adding RA interference to too many SENDS nodes anv: Emulate texture swizzle in the shader when needed anv: Stop forcing bindless for images anv: Only consider minSampleShading when sampleShadingEnable is set Juan A. Suarez Romero (2): cherry-ignore: radeonsi: update buffer descriptors in all contexts after buffer invalidation Update version to 19.1.0-rc3 Lionel Landwerlin (4): nir: fix lower_non_uniform_access pass vulkan/overlay-layer: fix cast errors vulkan/overlay: fix truncating error on 32bit platforms nir: lower_non_uniform_access: iterate over instructions safely Marek Olšák (1): radeonsi: remove old_va parameter from si_rebind_buffer by remembering offsets Nanley Chery (1): anv: Fix some depth buffer sampling cases on ICL+ Neha Bhende (1): draw: fix memory leak introduced 7720ce32a Samuel Pitoiset (1): radv: add a workaround for Monster Hunter World and LLVM 7&8 git tag: mesa-19.1.0-rc3 https://mesa.freedesktop.org/archive/mesa-19.1.0-rc3.tar.xz MD5: 414c5e038f3d16ff741236dda6065418 mesa-19.1.0-rc3.tar.xz SHA1: c1e984fbeb7e86c8cd8b21f40b81372e0147d720 mesa-19.1.0-rc3.tar.xz SHA256: 3c67d2114c48f0b8006208ec04e0b216e16e57cdff2e95ac8f05dd1e443a354f mesa-19.1.0-rc3.tar.xz SHA512: 740d5d13458b54e1942bfe7165938ec414aa7949aa60109ba872236f3b483c7305ac76b1b48c38dc6fd7691748106447757ac081f364952cc9e00f45fa9e2ea5 mesa-19.1.0-rc3.tar.xz PGP: https://mesa.freedesktop.org/archive/mesa-19.1.0-rc3.tar.xz.sig signature.asc Description: This is a digitally signed message part ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/tex: ignore the diff between GL_TEXTURE_2D and GL_TEXTURE_RECTANGLE
> > Hi all, > > On Thu, Jul 19, 2018 at 12:08 PM andrey simiklit > wrote: > > > Ugh... not so good. According to Oliver on the bug, this just make > the assert go away and doesn't actually fix anything. Likely this is > needed but not sufficient. > > > > So as far as I understand Oliver found the bad commit in xorg glamor: > > https://bugs.freedesktop.org/show_bug.cgi?id=107287 > > > > So at the moment we should fix just this "assertion" issue for Intel > because "rendering" issue came from xorg/glamor and there is no "rendering" > issue in Intel part. > > Please correct me if I incorrect. > > Reviving an old thread/patch here. > > Andrey, I reckon your patch here is still much needed as it fixes the > assert() issue: > > intel_mipmap_tree.c:1301: intel_miptree_match_image: Assertion > `image->TexObject->Target == mt->target' failed. > > Which is still occurring even with current master. > > My patch was to fix the rendering issue (landed a while ago before > 18.1 iirc), but yours was never merged and is still needed, I can > reproduce the assert() at will with the reproducer from > https://bugs.freedesktop.org/show_bug.cgi?id=107117 > > I could re-create this changes as MR instead of patch unless nobody against it. I fixed a bit the style of this patch to avoid new local variables: https://gitlab.freedesktop.org/asimiklit/mesa/commit/c11aae1cd403dde240c3877974f6a4b467cc83f5 > Jason, can we reconsider Andrii's patch? It still applies cleanly > (https://patchwork.freedesktop.org/patch/237490/) > > Cheers, > Olivier > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [RFC 0/2] Alternate default config mechanism
Hello everyone, First up, my apologies on not being able to respond earlier; secondly, thanks very much for your review. On Wed, 15 May 2019 at 19:27, Emil Velikov wrote: > > Hi all, > > On Tue, 14 May 2019 at 08:18, Tapani Pälli wrote: > > > > > > On 5/13/19 6:52 PM, Haehnle, Nicolai wrote: > > > This approach seems entirely incompatible with si_debug_options.h, and > > > will be an absolute maintenance nightmare going forward for adding / > > > removing options, because you're introducing a second location where > > > options are defined. > > > > > > Quite frankly, this seems like a terrible idea as-is. > > > > > > If you really can't use XML for whatever reason, then please find some > > > way of deriving both the tables here and the XML from the same single > > > source of truth. > > > > I was looking at this yesterday and came up with same conclusion. We > > should have the options in one place. Currently libexpat is statically > > linked with Android >=O, maybe for such restricted environments we could > > just inline the xml as is at compile time and parse that later or > > alternatively (maybe cleaner) parse and generate default option cache > > already during compilation? > > > I realise that jumping the "me too" train does not help much, so here > are some alternative ideas. > > How about we first distil the reasons why this is a problem and what > kind. Then explore independent solution for each one - as-is this > seems like a one-size-fits-all approach. I totally agree that this seems like a rudimentary / ugly approach, and we can definitely improve upon it once the reasons are discussed. > Some examples: > - XML file may be inaccessible - the in-driver defaults should work(tm) > Yes there are some app specific ones, yet neither(?) of these apps is > present on Android > - libexpat is not available, but libFOO is - investigate into a compat > wrapper > - cannot use external libraries (libexpat or equivalent) - static link > AFAIU, in the Android space, it is a combination of some of the above: a. current Android doesn't allow GL drivers to access config files from the vendor partition: this is enforced via selinux policy. b. Also, they had some concerns around how safe libexpat is vis-a-vis dual-loading, and that's where the concern around static linking came from. Alistair, could you please correct me if I am wrong, and if there are additional details on the need of this? > -Emil Best, Sumit. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] Mesa (master): glsl: do not use deprecated bison-keyword
Right. I guess with an old enough bison version, this can happen. I'll see if I can come up with something better.On May 21, 2019 15:47, Brian Paul wrote:I think this change broke the MSVC build for us.
I may not have time to investigate until later today.
-Brian
On 05/21/2019 05:41 AM, GitLab Mirror wrote:
> Module: Mesa
> Branch: master
> Commit: eb85124a9f6e9cb94d0d4a99f91bbae374777e3a
> URL: https://nam04.safelinks.protection.outlook.com/?url=""
>
> Author: Erik Faye-Lund
> Date: Mon May 20 13:29:05 2019 +0200
>
> glsl: do not use deprecated bison-keyword
>
> %error-verbose has been deprecated since Bison 3.0, which was released
> in 2013. In Bison 3.3.1 which was recently released, this has started
> causing warnings. Let's update the code to do this in the modern way
> intead, to avoid cluttering the output needlessly.
>
> Signed-off-by: Erik Faye-Lund
> Reviewed-by: Timothy Arceri
>
> ---
>
> src/compiler/glsl/glcpp/glcpp-parse.y | 2 +-
> src/compiler/glsl/glsl_parser.yy | 2 +-
> src/mesa/program/program_parse.y | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/compiler/glsl/glcpp/glcpp-parse.y b/src/compiler/glsl/glcpp/glcpp-parse.y
> index 1c095cb66f9..736af7e680d 100644
> --- a/src/compiler/glsl/glcpp/glcpp-parse.y
> +++ b/src/compiler/glsl/glcpp/glcpp-parse.y
> @@ -155,7 +155,7 @@ add_builtin_define(glcpp_parser_t *parser, const char *name, int value);
> %}
>
> %pure-parser
> -%error-verbose
> +%define parse.error verbose
>
> %locations
> %initial-action {
> diff --git a/src/compiler/glsl/glsl_parser.yy b/src/compiler/glsl/glsl_parser.yy
> index 6426f890b9e..dc6aade2643 100644
> --- a/src/compiler/glsl/glsl_parser.yy
> +++ b/src/compiler/glsl/glsl_parser.yy
> @@ -81,7 +81,7 @@ static bool match_layout_qualifier(const char *s1, const char *s2,
> %expect 0
>
> %pure-parser
> -%error-verbose
> +%define parse.error verbose
>
> %locations
> %initial-action {
> diff --git a/src/mesa/program/program_parse.y b/src/mesa/program/program_parse.y
> index 7398f5f507a..3d0c1e2ea9e 100644
> --- a/src/mesa/program/program_parse.y
> +++ b/src/mesa/program/program_parse.y
> @@ -124,7 +124,7 @@ static struct asm_instruction *asm_instruction_copy_ctor(
> %locations
> %lex-param { struct asm_parser_state *state }
> %parse-param { struct asm_parser_state *state }
> -%error-verbose
> +%define parse.error verbose
>
> %union {
> struct asm_instruction *inst;
>
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Re: [Mesa-dev] Mesa (master): glsl: do not use deprecated bison-keyword
I think this change broke the MSVC build for us.
I may not have time to investigate until later today.
-Brian
On 05/21/2019 05:41 AM, GitLab Mirror wrote:
Module: Mesa
Branch: master
Commit: eb85124a9f6e9cb94d0d4a99f91bbae374777e3a
URL:
https://nam04.safelinks.protection.outlook.com/?url=http%3A%2F%2Fcgit.freedesktop.org%2Fmesa%2Fmesa%2Fcommit%2F%3Fid%3Deb85124a9f6e9cb94d0d4a99f91bbae374777e3adata=02%7C01%7Cbrianp%40vmware.com%7C8fb4b04aba0f46cf005d08d6dde15558%7Cb39138ca3cee4b4aa4d6cd83d9dd62f0%7C0%7C0%7C636940357210597924sdata=N0sBC6rz%2F4KcpZyCKuNbNqNNhSE%2Fu6d8DcMCQY7STkY%3Dreserved=0
Author: Erik Faye-Lund
Date: Mon May 20 13:29:05 2019 +0200
glsl: do not use deprecated bison-keyword
%error-verbose has been deprecated since Bison 3.0, which was released
in 2013. In Bison 3.3.1 which was recently released, this has started
causing warnings. Let's update the code to do this in the modern way
intead, to avoid cluttering the output needlessly.
Signed-off-by: Erik Faye-Lund
Reviewed-by: Timothy Arceri
---
src/compiler/glsl/glcpp/glcpp-parse.y | 2 +-
src/compiler/glsl/glsl_parser.yy | 2 +-
src/mesa/program/program_parse.y | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/compiler/glsl/glcpp/glcpp-parse.y
b/src/compiler/glsl/glcpp/glcpp-parse.y
index 1c095cb66f9..736af7e680d 100644
--- a/src/compiler/glsl/glcpp/glcpp-parse.y
+++ b/src/compiler/glsl/glcpp/glcpp-parse.y
@@ -155,7 +155,7 @@ add_builtin_define(glcpp_parser_t *parser, const char
*name, int value);
%}
%pure-parser
-%error-verbose
+%define parse.error verbose
%locations
%initial-action {
diff --git a/src/compiler/glsl/glsl_parser.yy b/src/compiler/glsl/glsl_parser.yy
index 6426f890b9e..dc6aade2643 100644
--- a/src/compiler/glsl/glsl_parser.yy
+++ b/src/compiler/glsl/glsl_parser.yy
@@ -81,7 +81,7 @@ static bool match_layout_qualifier(const char *s1, const char
*s2,
%expect 0
%pure-parser
-%error-verbose
+%define parse.error verbose
%locations
%initial-action {
diff --git a/src/mesa/program/program_parse.y b/src/mesa/program/program_parse.y
index 7398f5f507a..3d0c1e2ea9e 100644
--- a/src/mesa/program/program_parse.y
+++ b/src/mesa/program/program_parse.y
@@ -124,7 +124,7 @@ static struct asm_instruction *asm_instruction_copy_ctor(
%locations
%lex-param { struct asm_parser_state *state }
%parse-param { struct asm_parser_state *state }
-%error-verbose
+%define parse.error verbose
%union {
struct asm_instruction *inst;
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[Mesa-dev] [PATCH] radv: fix the availability bit for timestamp queries
The previous code was just wrong because it copied the timestamp
value directly to the destination buffer. If the query pool was
resetted just before, the value was 0x which is considered
as available.
The new logic uses a WRITE_DATA packet to always initialize the
availability bit to zero, and it uses a COND_WRITE to packet to
set the bit if the timestamp is ready.
This fixes
dEQP-VK.pipeline.timestamp.misc_tests.reset_query_before_copy.
Signed-off-by: Samuel Pitoiset
---
src/amd/common/sid.h| 3 +++
src/amd/vulkan/radv_query.c | 31 +--
2 files changed, 28 insertions(+), 6 deletions(-)
diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
index 3c0b7001d2b..16faf0e3e66 100644
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -182,6 +182,9 @@
#define PKT3_SURFACE_SYNC 0x43 /* deprecated on CIK, use
ACQUIRE_MEM */
#define PKT3_ME_INITIALIZE 0x44 /* not on CIK */
#define PKT3_COND_WRITE0x45
+#defineCOND_WRITE_FUNC(x) ((x) & 0x7)
+#defineCOND_WRITE_POLL_SPACE(x)(((unsigned)(x) & 0x1)
<< 4)
+#defineCOND_WRITE_WRITE_SPACE(x) (((unsigned)(x) & 0x1)
<< 8)
#define PKT3_EVENT_WRITE 0x46
#define PKT3_EVENT_WRITE_EOP 0x47 /* not on GFX9 */
#define EOP_DST_SEL(x) ((x) << 16)
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 63a2ab773a8..f2b88e9c300 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -1345,7 +1345,7 @@ void radv_CmdCopyQueryPoolResults(
unsigned query = firstQuery + i;
uint64_t local_src_va = va + query * pool->stride;
- MAYBE_UNUSED unsigned cdw_max =
radeon_check_space(cmd_buffer->device->ws, cs, 19);
+ MAYBE_UNUSED unsigned cdw_max =
radeon_check_space(cmd_buffer->device->ws, cs, 27);
if (flags & VK_QUERY_RESULT_WAIT_BIT) {
@@ -1360,13 +1360,32 @@ void radv_CmdCopyQueryPoolResults(
if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
uint64_t avail_dest_va = dest_va + elem_size;
- radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
- radeon_emit(cs,
COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
-
COPY_DATA_DST_SEL(COPY_DATA_DST_MEM_GRBM));
- radeon_emit(cs, local_src_va);
- radeon_emit(cs, local_src_va >> 32);
+ /* Make sure to initialize the availability bit
+* to zero because the conditional packet will
+* only write 1 if the result is available.
+*/
+ radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
+ radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
+ S_370_WR_CONFIRM(1) |
+ S_370_ENGINE_SEL(V_370_PFP));
+ radeon_emit(cs, avail_dest_va);
+ radeon_emit(cs, avail_dest_va >> 32);
+ radeon_emit(cs, 0);
+
+ /* Set the availability bit to 1 only if the
+* high 32 bits of the timestamp is ready.
+*/
+ radeon_emit(cs, PKT3(PKT3_COND_WRITE, 7, 0));
+ radeon_emit(cs, COND_WRITE_FUNC(4) | /* not
equal */
+ COND_WRITE_POLL_SPACE(1) | /*
memory */
+ COND_WRITE_WRITE_SPACE(1));
+ radeon_emit(cs, local_src_va + 4);
+ radeon_emit(cs, (local_src_va + 4) >> 32);
+ radeon_emit(cs, TIMESTAMP_NOT_READY >> 32);
+ radeon_emit(cs, 0x);
radeon_emit(cs, avail_dest_va);
radeon_emit(cs, avail_dest_va >> 32);
+ radeon_emit(cs, 1);
}
radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
--
2.21.0
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Re: [Mesa-dev] [PATCH] i965/tex: ignore the diff between GL_TEXTURE_2D and GL_TEXTURE_RECTANGLE
Hi all, On Thu, Jul 19, 2018 at 12:08 PM andrey simiklit wrote: > > Ugh... not so good. According to Oliver on the bug, this just make the > > assert go away and doesn't actually fix anything. Likely this is needed > > but not sufficient. > > So as far as I understand Oliver found the bad commit in xorg glamor: > https://bugs.freedesktop.org/show_bug.cgi?id=107287 > > So at the moment we should fix just this "assertion" issue for Intel because > "rendering" issue came from xorg/glamor and there is no "rendering" issue in > Intel part. > Please correct me if I incorrect. Reviving an old thread/patch here. Andrey, I reckon your patch here is still much needed as it fixes the assert() issue: intel_mipmap_tree.c:1301: intel_miptree_match_image: Assertion `image->TexObject->Target == mt->target' failed. Which is still occurring even with current master. My patch was to fix the rendering issue (landed a while ago before 18.1 iirc), but yours was never merged and is still needed, I can reproduce the assert() at will with the reproducer from https://bugs.freedesktop.org/show_bug.cgi?id=107117 Jason, can we reconsider Andrii's patch? It still applies cleanly (https://patchwork.freedesktop.org/patch/237490/) Cheers, Olivier ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radv: do not reset query pool during creation
From the Vulkan spec 1.1.108: "After query pool creation, each query must be reset before it is used." So, the driver doesn't need to do this at creation time. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_query.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index 520711e4864..be1cf589d63 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -1035,8 +1035,6 @@ VkResult radv_CreateQueryPool( struct radv_query_pool *pool = vk_alloc2(>alloc, pAllocator, sizeof(*pool), 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); - uint32_t initial_value = pCreateInfo->queryType == VK_QUERY_TYPE_TIMESTAMP -? TIMESTAMP_NOT_READY : 0; if (!pool) return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY); @@ -1082,7 +1080,6 @@ VkResult radv_CreateQueryPool( vk_free2(>alloc, pAllocator, pool); return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY); } - memset(pool->ptr, initial_value, pool->size); *pQueryPool = radv_query_pool_to_handle(pool); return VK_SUCCESS; -- 2.21.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] radeonsi: update buffer descriptors in all contexts after buffer invalidation
Can someone with access revert from master until this is fixed? It's
been broken for 3 days now
On Tue, 21 May 2019 at 09:01, Juan A. Suarez Romero wrote:
>
> On Tue, 2019-05-21 at 09:36 +0200, Gert Wollny wrote:
> > Hi Marek,
> >
> > it seems that this patch is causing a few issues [1], any idea what is
> > going on? Maybe it is best to revert the patch for now?
> >
> > Best,
> > Gert
> >
>
>
> As this is commit is causing issues, I'm withdrawing it out of 19.1 branch.
>
> If later a fix is provided, let me know so I can re-add it to the branch,
> together with the fix.
>
> Thanks.
>
> J.A.
>
> > [1] https://bugzilla.freedesktop.org/show_bug.cgi?id=110701
> >
> > On Fr, 2019-05-10 at 01:19 -0400, Marek Olšák wrote:
> > > From: Marek Olšák
> > >
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108824
> > >
> > > Cc: 19.1
> > > ---
> > > src/gallium/drivers/radeonsi/si_descriptors.c | 94 -
> > > --
> > > src/gallium/drivers/radeonsi/si_pipe.h| 2 +
> > > src/gallium/drivers/radeonsi/si_state_draw.c | 9 +-
> > > 3 files changed, 72 insertions(+), 33 deletions(-)
> > >
> > > diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
> > > b/src/gallium/drivers/radeonsi/si_descriptors.c
> > > index 744fc9a15d7..6a4dcacc0f3 100644
> > > --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> > > +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> > > @@ -1580,242 +1580,272 @@ void
> > > si_update_needs_color_decompress_masks(struct si_context *sctx)
> > > si_samplers_update_needs_color_decompress_mask(
> > > > samplers[i]);
> > > si_images_update_needs_color_decompress_mask(
> > > > images[i]);
> > > si_update_shader_needs_decompress_mask(sctx, i);
> > > }
> > >
> > > si_resident_handles_update_needs_color_decompress(sctx);
> > > }
> > >
> > > /* BUFFER DISCARD/INVALIDATION */
> > >
> > > -/** Reset descriptors of buffer resources after \p buf has been
> > > invalidated. */
> > > +/* Reset descriptors of buffer resources after \p buf has been
> > > invalidated.
> > > + * If buf == NULL, reset all descriptors.
> > > + */
> > > static void si_reset_buffer_resources(struct si_context *sctx,
> > > struct si_buffer_resources
> > > *buffers,
> > > unsigned descriptors_idx,
> > > unsigned slot_mask,
> > > struct pipe_resource *buf,
> > > enum radeon_bo_priority priority)
> > > {
> > > struct si_descriptors *descs =
> > > > descriptors[descriptors_idx];
> > > unsigned mask = buffers->enabled_mask & slot_mask;
> > >
> > > while (mask) {
> > > unsigned i = u_bit_scan();
> > > - if (buffers->buffers[i] == buf) {
> > > - si_set_buf_desc_address(si_resource(buf),
> > > buffers->offsets[i],
> > > + struct pipe_resource *buffer = buffers->buffers[i];
> > > +
> > > + if (buffer && (!buf || buffer == buf)) {
> > > + si_set_buf_desc_address(si_resource(buffer),
> > > buffers->offsets[i],
> > > descs->list + i*4);
> > > sctx->descriptors_dirty |= 1u <<
> > > descriptors_idx;
> > >
> > > radeon_add_to_gfx_buffer_list_check_mem(sctx,
> > > - si_reso
> > > urce(buf),
> > > + si_reso
> > > urce(buffer),
> > > buffers
> > > ->writable_mask & (1u << i) ?
> > >
> > > RADEON_USAGE_READWRITE :
> > >
> > > RADEON_USAGE_READ,
> > > priorit
> > > y, true);
> > > }
> > > }
> > > }
> > >
> > > -/* Update all resource bindings where the buffer is bound, including
> > > +/* Update all buffer bindings where the buffer is bound, including
> > > * all resource descriptors. This is invalidate_buffer without
> > > - * the invalidation. */
> > > + * the invalidation.
> > > + *
> > > + * If buf == NULL, update all buffer bindings.
> > > + */
> > > void si_rebind_buffer(struct si_context *sctx, struct pipe_resource
> > > *buf)
> > > {
> > > struct si_resource *buffer = si_resource(buf);
> > > unsigned i, shader;
> > > unsigned num_elems = sctx->vertex_elements ?
> > >sctx->vertex_elements->count :
> > > 0;
> > >
> > > /* We changed the buffer, now we need to bind it where the old
> > > one
> > > * was bound. This consists of 2 things:
> > > * 1) Updating the resource descriptor and dirtying it.
> > > * 2) Adding a relocation to the CS, so that it's usable.
> > > */
> > >
> > > /* Vertex buffers. */
> > > - if (buffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
> > > + if (!buffer)
Re: [Mesa-dev] [PATCH 2/2] radeonsi: update buffer descriptors in all contexts after buffer invalidation
On Tue, 2019-05-21 at 09:36 +0200, Gert Wollny wrote:
> Hi Marek,
>
> it seems that this patch is causing a few issues [1], any idea what is
> going on? Maybe it is best to revert the patch for now?
>
> Best,
> Gert
>
As this is commit is causing issues, I'm withdrawing it out of 19.1 branch.
If later a fix is provided, let me know so I can re-add it to the branch,
together with the fix.
Thanks.
J.A.
> [1] https://bugzilla.freedesktop.org/show_bug.cgi?id=110701
>
> On Fr, 2019-05-10 at 01:19 -0400, Marek Olšák wrote:
> > From: Marek Olšák
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108824
> >
> > Cc: 19.1
> > ---
> > src/gallium/drivers/radeonsi/si_descriptors.c | 94 -
> > --
> > src/gallium/drivers/radeonsi/si_pipe.h| 2 +
> > src/gallium/drivers/radeonsi/si_state_draw.c | 9 +-
> > 3 files changed, 72 insertions(+), 33 deletions(-)
> >
> > diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
> > b/src/gallium/drivers/radeonsi/si_descriptors.c
> > index 744fc9a15d7..6a4dcacc0f3 100644
> > --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> > +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> > @@ -1580,242 +1580,272 @@ void
> > si_update_needs_color_decompress_masks(struct si_context *sctx)
> > si_samplers_update_needs_color_decompress_mask(
> > > samplers[i]);
> > si_images_update_needs_color_decompress_mask(
> > > images[i]);
> > si_update_shader_needs_decompress_mask(sctx, i);
> > }
> >
> > si_resident_handles_update_needs_color_decompress(sctx);
> > }
> >
> > /* BUFFER DISCARD/INVALIDATION */
> >
> > -/** Reset descriptors of buffer resources after \p buf has been
> > invalidated. */
> > +/* Reset descriptors of buffer resources after \p buf has been
> > invalidated.
> > + * If buf == NULL, reset all descriptors.
> > + */
> > static void si_reset_buffer_resources(struct si_context *sctx,
> > struct si_buffer_resources
> > *buffers,
> > unsigned descriptors_idx,
> > unsigned slot_mask,
> > struct pipe_resource *buf,
> > enum radeon_bo_priority priority)
> > {
> > struct si_descriptors *descs =
> > > descriptors[descriptors_idx];
> > unsigned mask = buffers->enabled_mask & slot_mask;
> >
> > while (mask) {
> > unsigned i = u_bit_scan();
> > - if (buffers->buffers[i] == buf) {
> > - si_set_buf_desc_address(si_resource(buf),
> > buffers->offsets[i],
> > + struct pipe_resource *buffer = buffers->buffers[i];
> > +
> > + if (buffer && (!buf || buffer == buf)) {
> > + si_set_buf_desc_address(si_resource(buffer),
> > buffers->offsets[i],
> > descs->list + i*4);
> > sctx->descriptors_dirty |= 1u <<
> > descriptors_idx;
> >
> > radeon_add_to_gfx_buffer_list_check_mem(sctx,
> > - si_reso
> > urce(buf),
> > + si_reso
> > urce(buffer),
> > buffers
> > ->writable_mask & (1u << i) ?
> >
> > RADEON_USAGE_READWRITE :
> >
> > RADEON_USAGE_READ,
> > priorit
> > y, true);
> > }
> > }
> > }
> >
> > -/* Update all resource bindings where the buffer is bound, including
> > +/* Update all buffer bindings where the buffer is bound, including
> > * all resource descriptors. This is invalidate_buffer without
> > - * the invalidation. */
> > + * the invalidation.
> > + *
> > + * If buf == NULL, update all buffer bindings.
> > + */
> > void si_rebind_buffer(struct si_context *sctx, struct pipe_resource
> > *buf)
> > {
> > struct si_resource *buffer = si_resource(buf);
> > unsigned i, shader;
> > unsigned num_elems = sctx->vertex_elements ?
> >sctx->vertex_elements->count :
> > 0;
> >
> > /* We changed the buffer, now we need to bind it where the old
> > one
> > * was bound. This consists of 2 things:
> > * 1) Updating the resource descriptor and dirtying it.
> > * 2) Adding a relocation to the CS, so that it's usable.
> > */
> >
> > /* Vertex buffers. */
> > - if (buffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
> > + if (!buffer) {
> > + if (num_elems)
> > + sctx->vertex_buffers_dirty = true;
> > + } else if (buffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
> > for (i = 0; i < num_elems; i++) {
> > int vb =
Re: [Mesa-dev] [PATCH 2/2] radeonsi: update buffer descriptors in all contexts after buffer invalidation
Hi Marek,
it seems that this patch is causing a few issues [1], any idea what is
going on? Maybe it is best to revert the patch for now?
Best,
Gert
[1] https://bugzilla.freedesktop.org/show_bug.cgi?id=110701
On Fr, 2019-05-10 at 01:19 -0400, Marek Olšák wrote:
> From: Marek Olšák
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108824
>
> Cc: 19.1
> ---
> src/gallium/drivers/radeonsi/si_descriptors.c | 94 -
> --
> src/gallium/drivers/radeonsi/si_pipe.h| 2 +
> src/gallium/drivers/radeonsi/si_state_draw.c | 9 +-
> 3 files changed, 72 insertions(+), 33 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
> b/src/gallium/drivers/radeonsi/si_descriptors.c
> index 744fc9a15d7..6a4dcacc0f3 100644
> --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> @@ -1580,242 +1580,272 @@ void
> si_update_needs_color_decompress_masks(struct si_context *sctx)
> si_samplers_update_needs_color_decompress_mask(
> >samplers[i]);
> si_images_update_needs_color_decompress_mask(
> >images[i]);
> si_update_shader_needs_decompress_mask(sctx, i);
> }
>
> si_resident_handles_update_needs_color_decompress(sctx);
> }
>
> /* BUFFER DISCARD/INVALIDATION */
>
> -/** Reset descriptors of buffer resources after \p buf has been
> invalidated. */
> +/* Reset descriptors of buffer resources after \p buf has been
> invalidated.
> + * If buf == NULL, reset all descriptors.
> + */
> static void si_reset_buffer_resources(struct si_context *sctx,
> struct si_buffer_resources
> *buffers,
> unsigned descriptors_idx,
> unsigned slot_mask,
> struct pipe_resource *buf,
> enum radeon_bo_priority priority)
> {
> struct si_descriptors *descs =
> >descriptors[descriptors_idx];
> unsigned mask = buffers->enabled_mask & slot_mask;
>
> while (mask) {
> unsigned i = u_bit_scan();
> - if (buffers->buffers[i] == buf) {
> - si_set_buf_desc_address(si_resource(buf),
> buffers->offsets[i],
> + struct pipe_resource *buffer = buffers->buffers[i];
> +
> + if (buffer && (!buf || buffer == buf)) {
> + si_set_buf_desc_address(si_resource(buffer),
> buffers->offsets[i],
> descs->list + i*4);
> sctx->descriptors_dirty |= 1u <<
> descriptors_idx;
>
> radeon_add_to_gfx_buffer_list_check_mem(sctx,
> - si_reso
> urce(buf),
> + si_reso
> urce(buffer),
> buffers
> ->writable_mask & (1u << i) ?
>
> RADEON_USAGE_READWRITE :
>
> RADEON_USAGE_READ,
> priorit
> y, true);
> }
> }
> }
>
> -/* Update all resource bindings where the buffer is bound, including
> +/* Update all buffer bindings where the buffer is bound, including
> * all resource descriptors. This is invalidate_buffer without
> - * the invalidation. */
> + * the invalidation.
> + *
> + * If buf == NULL, update all buffer bindings.
> + */
> void si_rebind_buffer(struct si_context *sctx, struct pipe_resource
> *buf)
> {
> struct si_resource *buffer = si_resource(buf);
> unsigned i, shader;
> unsigned num_elems = sctx->vertex_elements ?
> sctx->vertex_elements->count :
> 0;
>
> /* We changed the buffer, now we need to bind it where the old
> one
>* was bound. This consists of 2 things:
>* 1) Updating the resource descriptor and dirtying it.
>* 2) Adding a relocation to the CS, so that it's usable.
>*/
>
> /* Vertex buffers. */
> - if (buffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
> + if (!buffer) {
> + if (num_elems)
> + sctx->vertex_buffers_dirty = true;
> + } else if (buffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
> for (i = 0; i < num_elems; i++) {
> int vb = sctx->vertex_elements-
> >vertex_buffer_index[i];
>
> if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
> continue;
> if (!sctx->vertex_buffer[vb].buffer.resource)
> continue;
>
> if (sctx->vertex_buffer[vb].buffer.resource ==
> buf) {
>
