from:"alexdeucher"

[Mesa-dev] [PATCH] R600/SI: Add processor types for each CIK variant

2013-06-28 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 lib/Target/R600/Processors.td |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/lib/Target/R600/Processors.td b/lib/Target/R600/Processors.td
index 81f407e..a0735d4 100644
--- a/lib/Target/R600/Processors.td
+++ b/lib/Target/R600/Processors.td
@@ -48,3 +48,6 @@ def : Procpitcairn,   SI_Itin, [FeatureSouthernIslands];
 def : Procverde,  SI_Itin, [FeatureSouthernIslands];
 def : Procoland,  SI_Itin, [FeatureSouthernIslands];
 def : Prochainan, SI_Itin, [FeatureSouthernIslands];
+def : Procbonaire,SI_Itin, [FeatureSouthernIslands];
+def : Prockabini, SI_Itin, [FeatureSouthernIslands];
+def : Prockaveri, SI_Itin, [FeatureSouthernIslands];
\ No newline at end of file
-- 
1.7.7.5

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[Mesa-dev] [PATCH] winsys/radeon: add env var to disable VM on Cayman/Trinity

2013-06-10 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Set env var RADEON_VA=0 to disable VM on Cayman/Trinity.
Useful for debugging.

Note: this is a candidate for the 9.1 branch.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 15d5d31..ee4dfa1 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -399,6 +399,8 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
   ws-info.r600_ib_vm_max_size))
 ws-info.r600_virtual_address = FALSE;
 }
+   if (ws-gen == DRV_R600  !debug_get_bool_option(RADEON_VA, TRUE))
+   ws-info.r600_virtual_address = FALSE;
 }
 
 /* Get max pipes, this is only needed for compute shaders.  All evergreen+
-- 
1.7.7.5

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[Mesa-dev] [PATCH 1/3] radeonsi: add support for hainan chips

2013-05-13 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Note: this is a candidate for the 9.1 branch

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/radeonsi/radeonsi_pipe.c  |1 +
 src/gallium/drivers/radeonsi/si_state.c   |3 +++
 src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |1 +
 src/gallium/winsys/radeon/drm/radeon_winsys.h |1 +
 4 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c 
b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
index 0e6b941..fa40097 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
@@ -300,6 +300,7 @@ static const char *r600_get_family_name(enum radeon_family 
family)
case CHIP_PITCAIRN: return AMD PITCAIRN;
case CHIP_VERDE: return AMD CAPE VERDE;
case CHIP_OLAND: return AMD OLAND;
+   case CHIP_HAINAN: return AMD HAINAN;
default: return AMD unknown;
}
 }
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index be40fdf..ed95b1d 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2791,6 +2791,9 @@ void si_init_config(struct r600_context *rctx)
case CHIP_OLAND:
si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0082);
break;
+   case CHIP_HAINAN:
+   si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x);
+   break;
default:
si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x);
break;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 3689020..15d5d31 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -321,6 +321,7 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
 case CHIP_PITCAIRN:
 case CHIP_VERDE:
 case CHIP_OLAND:
+case CHIP_HAINAN:
 ws-info.chip_class = TAHITI;
 break;
 }
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h 
b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index 1c2fb69..d0f16e1 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -124,6 +124,7 @@ enum radeon_family {
 CHIP_PITCAIRN,
 CHIP_VERDE,
 CHIP_OLAND,
+CHIP_HAINAN,
 CHIP_LAST,
 };
 
-- 
1.7.7.5

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[Mesa-dev] [PATCH 2/3] radeonsi: update r600_get_llvm_processor_name for hainan

2013-05-13 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/radeonsi/radeonsi_pipe.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c 
b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
index fa40097..b988e72 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
@@ -289,6 +289,7 @@ const char *r600_get_llvm_processor_name(enum radeon_family 
family)
case CHIP_PITCAIRN: return pitcairn;
case CHIP_VERDE: return verde;
case CHIP_OLAND: return oland;
+   case CHIP_HAINAN: return hainan;
default: return ;
}
 }
-- 
1.7.7.5

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[Mesa-dev] [PATCH 3/3] radeonsi: add Hainan pci ids

2013-05-13 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Note: this is a candidate for the 9.1 branch

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 include/pci_ids/radeonsi_pci_ids.h |7 +++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/include/pci_ids/radeonsi_pci_ids.h 
b/include/pci_ids/radeonsi_pci_ids.h
index 68d7948..f823a2e 100644
--- a/include/pci_ids/radeonsi_pci_ids.h
+++ b/include/pci_ids/radeonsi_pci_ids.h
@@ -63,3 +63,10 @@ CHIPSET(0x6620, OLAND_6620, OLAND)
 CHIPSET(0x6621, OLAND_6621, OLAND)
 CHIPSET(0x6623, OLAND_6623, OLAND)
 CHIPSET(0x6631, OLAND_6631, OLAND)
+
+CHIPSET(0x6660, HAINAN_6660, HAINAN)
+CHIPSET(0x6663, HAINAN_6663, HAINAN)
+CHIPSET(0x6664, HAINAN_6664, HAINAN)
+CHIPSET(0x6665, HAINAN_6665, HAINAN)
+CHIPSET(0x6667, HAINAN_6667, HAINAN)
+CHIPSET(0x666F, HAINAN_666F, HAINAN)
-- 
1.7.7.5

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[Mesa-dev] [PATCH] r600g: don't emit surface_sync after FLUSH_AND_INV_EVENT

2013-05-03 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

It shouldn't be needed since the FLUSH_AND_INV_EVENT has already
made sure the destination caches are flushed.  Additionally,
we didn't previously emit the surface_sync until this commit:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5e4c07e7964a3258ed02b530bcdc24c0650204b
Emitting them together causes hangs in compute on cayman/TN
and hangs in Heaven on evergreen.

Note: this patch is a candidate for the 9.1 branch, but requires:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=156bcca62c9f4e79e78929f72bc085757f36a65a
as well.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/r600_hw_context.c |   26 --
 1 files changed, 0 insertions(+), 26 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_hw_context.c 
b/src/gallium/drivers/r600/r600_hw_context.c
index 6d8b2cf..944b666 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -226,32 +226,6 @@ void r600_flush_emit(struct r600_context *rctx)
if (rctx-flags  R600_CONTEXT_FLUSH_AND_INV) {
cs-buf[cs-cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
cs-buf[cs-cdw++] = 
EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
-   if (rctx-chip_class = EVERGREEN) {
-   /* We were previously setting the CB and DB bits on
-* cp_coher_cntl, but this is unnecessary since
-* we are emitting the
-* EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT packet.
-* Setting the CB bits was causing lockups when using
-* compute on cayman.
-*
-* XXX: Do even need to emit a surface sync packet here?
-* Prior to e5e4c07e7964a3258ed02b530bcdc24c0650204b
-* surface sync was not being emitted with the
-* R600_CONTEXT_FLUSH_AND_INV flag.
-*/
-   cp_coher_cntl = S_0085F0_TC_ACTION_ENA(1) |
-   S_0085F0_DB_ACTION_ENA(1) |
-   S_0085F0_SH_ACTION_ENA(1) |
-   S_0085F0_SMX_ACTION_ENA(1) |
-   S_0085F0_FULL_CACHE_ENA(1);
-   } else {
-   cp_coher_cntl = S_0085F0_SMX_ACTION_ENA(1) |
-   S_0085F0_SH_ACTION_ENA(1) |
-   S_0085F0_VC_ACTION_ENA(1) |
-   S_0085F0_TC_ACTION_ENA(1) |
-   S_0085F0_FULL_CACHE_ENA(1);
-   }
-   emit_flush = 1;
}
 
if (rctx-flags  R600_CONTEXT_INVAL_READ_CACHES) {
-- 
1.7.7.5

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[Mesa-dev] [PATCH] r600g: use CP DMA for buffer clears on evergreen+

2013-04-24 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Lighter weight then using streamout.  Only evergreen
and newer asics support embedded data as src with
CP DMA.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/evergreen_hw_context.c |   66 +++
 src/gallium/drivers/r600/evergreend.h   |   42 ++
 src/gallium/drivers/r600/r600_blit.c|   10 +++-
 src/gallium/drivers/r600/r600_pipe.h|3 +
 4 files changed, 119 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c 
b/src/gallium/drivers/r600/evergreen_hw_context.c
index d980c18..7cab879 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -106,3 +106,69 @@ void evergreen_dma_copy(struct r600_context *rctx,
util_range_add(rdst-valid_buffer_range, dst_offset,
   dst_offset + size);
 }
+
+/* The max number of bytes to copy per packet. */
+#define CP_DMA_MAX_BYTE_COUNT ((1  21) - 8)
+
+void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
+  struct pipe_resource *dst, uint64_t offset,
+  unsigned size, uint32_t clear_value)
+{
+   struct radeon_winsys_cs *cs = rctx-rings.gfx.cs;
+
+   assert(size);
+   assert(rctx-screen-has_cp_dma);
+
+   offset += r600_resource_va(rctx-screen-screen, dst);
+
+   /* We flush the caches, because we might read from or write
+* to resources which are bound right now. */
+   rctx-flags |= R600_CONTEXT_INVAL_READ_CACHES |
+  R600_CONTEXT_FLUSH_AND_INV |
+  R600_CONTEXT_FLUSH_AND_INV_CB_META |
+  R600_CONTEXT_FLUSH_AND_INV_DB_META |
+  R600_CONTEXT_STREAMOUT_FLUSH |
+  R600_CONTEXT_WAIT_3D_IDLE;
+
+   while (size) {
+   unsigned sync = 0;
+   unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
+   unsigned reloc;
+
+   r600_need_cs_space(rctx, 10 + (rctx-flags ? 
R600_MAX_FLUSH_CS_DWORDS : 0), FALSE);
+
+   /* Flush the caches for the first copy only. */
+   if (rctx-flags) {
+   r600_flush_emit(rctx);
+   }
+
+   /* Do the synchronization after the last copy, so that all data 
is written to memory. */
+   if (size == byte_count) {
+   sync = PKT3_CP_DMA_CP_SYNC;
+   }
+
+   /* This must be done after r600_need_cs_space. */
+   reloc = r600_context_bo_reloc(rctx, rctx-rings.gfx,
+ (struct r600_resource*)dst, 
RADEON_USAGE_WRITE);
+
+   r600_write_value(cs, PKT3(PKT3_CP_DMA, 4, 0));
+   r600_write_value(cs, clear_value);  /* DATA [31:0] */
+   r600_write_value(cs, sync | PKT3_CP_DMA_SRC_SEL(2));/* 
CP_SYNC [31] | SRC_SEL[30:29] */
+   r600_write_value(cs, offset);   /* DST_ADDR_LO [31:0] */
+   r600_write_value(cs, (offset  32)  0xff);/* 
DST_ADDR_HI [7:0] */
+   r600_write_value(cs, byte_count);   /* COMMAND [29:22] | 
BYTE_COUNT [20:0] */
+
+   r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
+   r600_write_value(cs, reloc);
+
+   size -= byte_count;
+   offset += byte_count;
+   }
+
+   /* Invalidate the read caches. */
+   rctx-flags |= R600_CONTEXT_INVAL_READ_CACHES;
+
+   util_range_add(r600_resource(dst)-valid_buffer_range, offset,
+  offset + size);
+}
+
diff --git a/src/gallium/drivers/r600/evergreend.h 
b/src/gallium/drivers/r600/evergreend.h
index 53b68a4..5d72432 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -118,6 +118,48 @@
 #define PKT3_PREDICATE(x)   (((x)  0)  0x1)
 #define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | 
PKT_COUNT_S(count))
 
+#define PKT3_CP_DMA0x41
+/* 1. header
+ * 2. SRC_ADDR_LO [31:0] or DATA [31:0]
+ * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 
SRC_ADDR_HI [7:0]
+ * 4. DST_ADDR_LO [31:0]
+ * 5. DST_ADDR_HI [7:0]
+ * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
+ */
+#define PKT3_CP_DMA_CP_SYNC   (1  31)
+#define PKT3_CP_DMA_SRC_SEL(x)   ((x)  29)
+/* 0 - SRC_ADDR
+ * 1 - GDS (program SAS to 1 as well)
+ * 2 - DATA
+ */
+#define PKT3_CP_DMA_DST_SEL(x)   ((x)  20)
+/* 0 - DST_ADDR
+ * 1 - GDS (program DAS to 1 as well)
+ */
+/* COMMAND */
+#define PKT3_CP_DMA_CMD_SRC_SWAP(x) ((x)  23)
+/* 0 - none
+ * 1 - 8 in 16
+ * 2 - 8 in 32
+ * 3 - 8 in 64
+ */
+#define PKT3_CP_DMA_CMD_DST_SWAP(x) ((x)  24)
+/* 0 - none
+ * 1 - 8 in 16
+ * 2 - 8 in 32
+ * 3 - 8 in 64
+ */
+#define PKT3_CP_DMA_CMD_SAS   (1  26)
+/* 0 - memory
+ * 1 -

[Mesa-dev] [PATCH] r600g: disable hyperz by default on 9.1

2013-04-22 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

There are too many cases were we end up with lockups.
Once we sort out the remaining issues on master, they
can be backported and hyperz can be re-enabled on 9.1

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/r600_pipe.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_pipe.c 
b/src/gallium/drivers/r600/r600_pipe.c
index a7973a5..80b859f 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -1157,7 +1157,7 @@ struct pipe_screen *r600_screen_create(struct 
radeon_winsys *ws)
 * case were triggering lockup quickly such as :
 * piglit/bin/depthstencil-render-miplevels 1024 d=s=z24_s8
 */
-   rscreen-use_hyperz = debug_get_bool_option(R600_HYPERZ, TRUE);
+   rscreen-use_hyperz = debug_get_bool_option(R600_HYPERZ, FALSE);
rscreen-use_hyperz = rscreen-info.drm_minor = 26 ? 
rscreen-use_hyperz : FALSE;
 
rscreen-global_pool = compute_memory_pool_new(rscreen);
-- 
1.7.7.5

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[Mesa-dev] [PATCH 1/2] r600g: fall back to blitter for compressed textures

2013-03-15 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

The hw can only access compressed textures as tiled not
linear so we need to do format tricks to handle them
properly.  The blitter code already handles this so
just fallback to the blitter for compressed textures.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=60802

Note: this is a candidate for the 9.1 branch.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/evergreen_state.c |9 +
 src/gallium/drivers/r600/r600_state.c  |9 +
 2 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 2bdefb0..4387c86 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3674,6 +3674,15 @@ boolean evergreen_dma_blit(struct pipe_context *ctx,
return FALSE;
}
 
+   /* HW can only handle tiled compressed textures.
+* Need to do format tricks in blitter code to handle them
+* properly so bail here and let the blitter code handle it.
+*/
+   if (src_mode != dst_mode) {
+   if (util_format_is_compressed(src-format))
+   return FALSE;
+   }
+
if (src_mode == dst_mode) {
uint64_t dst_offset, src_offset;
/* simple dma blit would do NOTE code here assume :
diff --git a/src/gallium/drivers/r600/r600_state.c 
b/src/gallium/drivers/r600/r600_state.c
index 846c159..8929d6e 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -3113,6 +3113,15 @@ boolean r600_dma_blit(struct pipe_context *ctx,
return FALSE;
}
 
+   /* HW can only handle tiled compressed textures.
+* Need to do format tricks in blitter code to handle them
+* properly so bail here and let the blitter code handle it.
+*/
+   if (src_mode != dst_mode) {
+   if (util_format_is_compressed(src-format))
+   return FALSE;
+   }
+
if (src_mode == dst_mode) {
uint64_t dst_offset, src_offset, size;
 
-- 
1.7.7.5

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[Mesa-dev] [PATCH 2/2] r600g: properly set non_disp tiling mode for DMA

2013-03-15 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Needs to be set just like other blocks.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/evergreen_state.c |   11 +--
 1 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 4387c86..bef3577 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3528,7 +3528,7 @@ static void evergreen_dma_copy_tile(struct r600_context 
*rctx,
struct r600_texture *rdst = (struct r600_texture*)dst;
unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
-   unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split;
+   unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, 
non_disp_tiling = 0;
uint64_t base, addr;
 
/* make sure that the dma ring is only one active */
@@ -3541,6 +3541,13 @@ static void evergreen_dma_copy_tile(struct r600_context 
*rctx,
dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? 
RADEON_SURF_MODE_LINEAR : dst_mode;
assert(dst_mode != src_mode);
 
+   if (util_format_has_depth(util_format_description(src-format)))
+   non_disp_tiling = 1;
+   if (rctx-chip_class == CAYMAN) {
+   if (util_format_get_blocksize(src-format) = 16)
+   non_disp_tiling = 1;
+   }
+
y = 0;
sub_cmd = 0x8;
lbpp = util_logbase2(bpp);
@@ -3620,7 +3627,7 @@ static void evergreen_dma_copy_tile(struct r600_context 
*rctx,
cs-buf[cs-cdw++] = (pitch_tile_max  0) | ((height - 1)  
16);
cs-buf[cs-cdw++] = (slice_tile_max  0);
cs-buf[cs-cdw++] = (x  0) | (z  18);
-   cs-buf[cs-cdw++] = (y  0) | (tile_split  21) | (nbanks  
25);
+   cs-buf[cs-cdw++] = (y  0) | (tile_split  21) | (nbanks  
25) | (non_disp_tiling  28);
cs-buf[cs-cdw++] = addr  0xfffc;
cs-buf[cs-cdw++] = (addr  32UL)  0xff;
copy_height -= cheight;
-- 
1.7.7.5

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[Mesa-dev] [PATCH 1/2] r600g: fall back to blitter for compressed textures on cayman (v2)

2013-03-15 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

The DMA block seems to have alignment issues with large
block sizes.  Use the blitter for these surfaces.

v2: cayman/TN only

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=60802

Note: this is a candidate for the 9.1 branch.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/evergreen_state.c |9 +
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 2bdefb0..b40ed01 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3674,6 +3674,15 @@ boolean evergreen_dma_blit(struct pipe_context *ctx,
return FALSE;
}
 
+   /* The DMA block on cayman seems to have alignment issues
+* with large block sizes.  Needs more investigation.
+*/
+   if ((rctx-chip_class == CAYMAN) 
+   (src_mode != dst_mode) 
+   (util_format_get_blocksize(src-format) = 16)) {
+   return FALSE;
+   }
+
if (src_mode == dst_mode) {
uint64_t dst_offset, src_offset;
/* simple dma blit would do NOTE code here assume :
-- 
1.7.7.5

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[Mesa-dev] [PATCH 2/2] r600g: properly set non_disp tiling mode for DMA (v2)

2013-03-15 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Needs to be set for depth, stencil, and fmask just
like other blocks.

v2: drop additional cayman bits for now

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/evergreen_state.c |8 ++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index b40ed01..387a0d7 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3528,7 +3528,7 @@ static void evergreen_dma_copy_tile(struct r600_context 
*rctx,
struct r600_texture *rdst = (struct r600_texture*)dst;
unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
-   unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split;
+   unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, 
non_disp_tiling = 0;
uint64_t base, addr;
 
/* make sure that the dma ring is only one active */
@@ -3541,6 +3541,10 @@ static void evergreen_dma_copy_tile(struct r600_context 
*rctx,
dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? 
RADEON_SURF_MODE_LINEAR : dst_mode;
assert(dst_mode != src_mode);
 
+   /* non_disp_tiling bit needs to be set for depth, stencil, and fmask 
surfaces */
+   if (util_format_has_depth(util_format_description(src-format)))
+   non_disp_tiling = 1;
+
y = 0;
sub_cmd = 0x8;
lbpp = util_logbase2(bpp);
@@ -3620,7 +3624,7 @@ static void evergreen_dma_copy_tile(struct r600_context 
*rctx,
cs-buf[cs-cdw++] = (pitch_tile_max  0) | ((height - 1)  
16);
cs-buf[cs-cdw++] = (slice_tile_max  0);
cs-buf[cs-cdw++] = (x  0) | (z  18);
-   cs-buf[cs-cdw++] = (y  0) | (tile_split  21) | (nbanks  
25);
+   cs-buf[cs-cdw++] = (y  0) | (tile_split  21) | (nbanks  
25) | (non_disp_tiling  28);
cs-buf[cs-cdw++] = addr  0xfffc;
cs-buf[cs-cdw++] = (addr  32UL)  0xff;
copy_height -= cheight;
-- 
1.7.7.5

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[Mesa-dev] [PATCH] r600g: r6xx deadlock workaround (v2)

2013-02-22 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Write to a CB register between draws.

May fix:
https://bugs.freedesktop.org/show_bug.cgi?id=50655
https://bugs.freedesktop.org/show_bug.cgi?id=47116

v2: flush along with workaround.

Note: this is a candidate for the 9.1 branch.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/r600_state_common.c |6 ++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_state_common.c 
b/src/gallium/drivers/r600/r600_state_common.c
index c4bd758..0834169 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1360,6 +1360,12 @@ static void r600_draw_vbo(struct pipe_context *ctx, 
const struct pipe_draw_info
rctx-vgt_state.atom.dirty = true;
}
 
+   /* Workaround for hardware deadlock on certain R600 ASICs: write into a 
CB register. */
+   if (rctx-chip_class == R600) {
+   rctx-flags |= R600_CONTEXT_FLUSH_AND_INV;
+   rctx-cb_misc_state.atom.dirty = true;
+   }
+
/* Emit states. */
r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
r600_flush_emit(rctx);
-- 
1.7.7.5

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[Mesa-dev] [PATCH 0/4] r6xx flushing rework and enable CP DMA

2013-02-22 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

This patch set cleans up the flushing on r6xx in what seems to be
a logical manner.  The last patch enables CP DMA on r6xx.  No piglit
regressions on RS780 which I was testing on.

Alex Deucher (4):
  r600g: add missing emit_flush for R600_CONTEXT_FLUSH_AND_INV case
  r600g: synchronize streamout buffers on r6xx too (v2)
  r600g: set additional cp_coher_cntl bits for 6xx/7xx flush (v2)
  r600g: enable CP DMA on r6xx (v2)

 src/gallium/drivers/r600/r600_blit.c   |3 +--
 src/gallium/drivers/r600/r600_hw_context.c |   26 +-
 2 files changed, 18 insertions(+), 11 deletions(-)

-- 
1.7.7.5

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[Mesa-dev] [PATCH 1/4] r600g: add missing emit_flush for R600_CONTEXT_FLUSH_AND_INV case

2013-02-22 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

We set the cp_coher_cntl bits but never emit them.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/r600_hw_context.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_hw_context.c 
b/src/gallium/drivers/r600/r600_hw_context.c
index f6dc418..0531c60 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -676,6 +676,7 @@ void r600_flush_emit(struct r600_context *rctx)
S_0085F0_TC_ACTION_ENA(1) |
S_0085F0_FULL_CACHE_ENA(1);
}
+   emit_flush = 1;
}
 
if (rctx-flags  R600_CONTEXT_INVAL_READ_CACHES) {
-- 
1.7.7.5

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[Mesa-dev] [PATCH 3/4] r600g: set additional cp_coher_cntl bits for 6xx/7xx flush (v2)

2013-02-22 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

I don't see why we shouldn't be setting these bits on 6xx/7xx
as well.  They shouldn't hurt anything and we may be missing
synchronizations with certain blocks by not setting them.
The ddx already sets cp_coher_cntl in a similar manner.

v2: adjust selected bits.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/r600_hw_context.c |   12 +++-
 1 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_hw_context.c 
b/src/gallium/drivers/r600/r600_hw_context.c
index cf72549..735fdf2 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -669,12 +669,22 @@ void r600_flush_emit(struct r600_context *rctx)
S_0085F0_SH_ACTION_ENA(1) |
S_0085F0_SMX_ACTION_ENA(1) |
S_0085F0_FULL_CACHE_ENA(1);
-   } else {
+   } else if (rctx-chip_class == R700) {
cp_coher_cntl = S_0085F0_SMX_ACTION_ENA(1) |
S_0085F0_SH_ACTION_ENA(1) |
S_0085F0_VC_ACTION_ENA(1) |
S_0085F0_TC_ACTION_ENA(1) |
S_0085F0_FULL_CACHE_ENA(1);
+   } else if (rctx-chip_class == R600) {
+   cp_coher_cntl = S_0085F0_SMX_ACTION_ENA(1) |
+   S_0085F0_SH_ACTION_ENA(1) |
+   S_0085F0_VC_ACTION_ENA(1) |
+   S_0085F0_TC_ACTION_ENA(1) |
+   S_0085F0_FULL_CACHE_ENA(1) |
+   S_0085F0_CB0_DEST_BASE_ENA(1) |
+   S_0085F0_CB1_DEST_BASE_ENA(1) |
+   S_0085F0_CB_ACTION_ENA(1) |
+   S_0085F0_DEST_BASE_0_ENA(1);
}
emit_flush = 1;
}
-- 
1.7.7.5

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[Mesa-dev] [PATCH 1/6] r600g: add PS_PARTIAL_FLUSH flag

2013-02-22 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

PS_PARTIAL flushes seems to be required in certain
cases to prevent hangs, especially on r6xx.

Note: this is a candidate for the 9.1 branch.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/r600.h|1 +
 src/gallium/drivers/r600/r600_hw_context.c |5 +
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index 08b77e4..11dbb3b 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -151,6 +151,7 @@ struct r600_so_target {
 #define R600_CONTEXT_WAIT_CP_DMA_IDLE  (1  3)
 #define R600_CONTEXT_FLUSH_AND_INV (1  4)
 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (1  5)
+#define R600_CONTEXT_PS_PARTIAL_FLUSH  (1  6)
 
 struct r600_context;
 struct r600_screen;
diff --git a/src/gallium/drivers/r600/r600_hw_context.c 
b/src/gallium/drivers/r600/r600_hw_context.c
index f6dc418..09dc98b 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -624,6 +624,11 @@ void r600_flush_emit(struct r600_context *rctx)
return;
}
 
+   if (rctx-flags  R600_CONTEXT_PS_PARTIAL_FLUSH) {
+   cs-buf[cs-cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
+   cs-buf[cs-cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | 
EVENT_INDEX(4);
+   }
+
if (rctx-flags  R600_CONTEXT_WAIT_3D_IDLE) {
wait_until |= S_008040_WAIT_3D_IDLE(1);
}
-- 
1.7.7.5

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[Mesa-dev] [PATCH 2/6] r600g: r6xx deadlock workaround (v6)

2013-02-22 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=50655
https://bugs.freedesktop.org/show_bug.cgi?id=47116

v2: flush along with workaround.
v3: just need a flush
v4: try WAIT_UNTIL
v5: switch to PS partial flush
v6: rework patch

Note: this is a candidate for the 9.1 branch.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/r600_state_common.c |6 ++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_state_common.c 
b/src/gallium/drivers/r600/r600_state_common.c
index c4bd758..1654233 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1360,6 +1360,12 @@ static void r600_draw_vbo(struct pipe_context *ctx, 
const struct pipe_draw_info
rctx-vgt_state.atom.dirty = true;
}
 
+   /* Workaround for hardware deadlock on certain R600 ASICs: write into a 
CB register. */
+   if (rctx-chip_class == R600) {
+   rctx-flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
+   rctx-cb_misc_state.atom.dirty = true;
+   }
+
/* Emit states. */
r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
r600_flush_emit(rctx);
-- 
1.7.7.5

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[Mesa-dev] [PATCH 3/6] r600g: emit a ps partial flush after CP DMA

2013-02-22 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

May fix:
https://bugs.freedesktop.org/show_bug.cgi?id=58042

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/r600_hw_context.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_hw_context.c 
b/src/gallium/drivers/r600/r600_hw_context.c
index 09dc98b..7020c78 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -1166,7 +1166,7 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx,
}
 
/* Invalidate the read caches. */
-   rctx-flags |= R600_CONTEXT_INVAL_READ_CACHES;
+   rctx-flags |= R600_CONTEXT_INVAL_READ_CACHES | 
R600_CONTEXT_PS_PARTIAL_FLUSH;
 }
 
 void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw)
-- 
1.7.7.5

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[Mesa-dev] [PATCH 4/6] r600g: synchronize streamout buffers on r6xx too (v3)

2013-02-22 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Streamout buffers need to be synchronized on r6xx as
well.

v2: Add DEST flush as well.
v3: drop DEST flush

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/r600_hw_context.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_hw_context.c 
b/src/gallium/drivers/r600/r600_hw_context.c
index 7020c78..81463f6 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -690,7 +690,7 @@ void r600_flush_emit(struct r600_context *rctx)
emit_flush = 1;
}
 
-   if (rctx-family = CHIP_RV770  rctx-flags  
R600_CONTEXT_STREAMOUT_FLUSH) {
+   if (rctx-flags  R600_CONTEXT_STREAMOUT_FLUSH) {
cp_coher_cntl |= S_0085F0_SO0_DEST_BASE_ENA(1) |
S_0085F0_SO1_DEST_BASE_ENA(1) |
S_0085F0_SO2_DEST_BASE_ENA(1) |
-- 
1.7.7.5

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[Mesa-dev] [PATCH 5/6] r600g: add missing emit_flush for R600_CONTEXT_FLUSH_AND_INV case

2013-02-22 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

We set the cp_coher_cntl bits but never emit them.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/r600_hw_context.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_hw_context.c 
b/src/gallium/drivers/r600/r600_hw_context.c
index 81463f6..8c92030 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -681,6 +681,7 @@ void r600_flush_emit(struct r600_context *rctx)
S_0085F0_TC_ACTION_ENA(1) |
S_0085F0_FULL_CACHE_ENA(1);
}
+   emit_flush = 1;
}
 
if (rctx-flags  R600_CONTEXT_INVAL_READ_CACHES) {
-- 
1.7.7.5

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[Mesa-dev] [PATCH 6/6] r600g: enable CP DMA on r6xx (v3)

2013-02-22 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

With the previous flushing changes this seems to work
reliably now.

v2: add R600_CONTEXT_FLUSH_AND_INV
v3: just enable CP DMA

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/r600_blit.c   |3 +--
 src/gallium/drivers/r600/r600_hw_context.c |6 --
 2 files changed, 1 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_blit.c 
b/src/gallium/drivers/r600/r600_blit.c
index 046eab5..019b456 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -508,8 +508,7 @@ void r600_copy_buffer(struct pipe_context *ctx, struct 
pipe_resource *dst, unsig
 {
struct r600_context *rctx = (struct r600_context*)ctx;
 
-   /* CP DMA doesn't work on R600 (flushing seems to be unreliable). */
-   if (rctx-screen-info.drm_minor = 27  rctx-chip_class = R700) {
+   if (rctx-screen-info.drm_minor = 27) {
r600_cp_dma_copy_buffer(rctx, dst, dstx, src, src_box-x, 
src_box-width);
}
else if (rctx-screen-has_streamout 
diff --git a/src/gallium/drivers/r600/r600_hw_context.c 
b/src/gallium/drivers/r600/r600_hw_context.c
index 8c92030..0537916 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -1108,12 +1108,6 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx,
struct radeon_winsys_cs *cs = rctx-rings.gfx.cs;
 
assert(size);
-   assert(rctx-chip_class != R600);
-
-   /* CP DMA doesn't work on R600 (flushing seems to be unreliable). */
-   if (rctx-chip_class == R600) {
-   return;
-   }
 
dst_offset += r600_resource_va(rctx-screen-screen, dst);
src_offset += r600_resource_va(rctx-screen-screen, src);
-- 
1.7.7.5

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[Mesa-dev] [PATCH] r600g: don't enable ReZ mode on evergreen

2013-02-20 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Can cause lockups in certain cases when
zfunc/zenable/zwrite change without a flush
in between.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=60969

This is a candidate for the 9.1 branch.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/evergreen_state.c |5 -
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index fd73613..4a91942 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3536,9 +3536,12 @@ void evergreen_update_db_shader_control(struct 
r600_context * rctx)
 * write to the zbuffer. Write to zbuffer is delayed after fragment 
shader
 * execution and thus after alpha test so if discarded by the alpha test
 * the z value is not written.
+* If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
+* get a hang unless you flush the DB in between.  For now just use
+* LATE_Z.
 */
if (rctx-alphatest_state.sx_alpha_test_control) {
-   db_shader_control |= S_02880C_Z_ORDER(V_02880C_RE_Z);
+   db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
} else {
db_shader_control |= 
S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
}
-- 
1.7.7.5

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[Mesa-dev] [PATCH] r600g: don't emit WAIT_UNTIL on cayman/TN (v2)

2013-01-28 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

It shouldn't be needed and older kernels don't support
it.

v2: Replace with PS partial flush as before.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=59945

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/r600_hw_context.c |   37 +---
 1 files changed, 28 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_hw_context.c 
b/src/gallium/drivers/r600/r600_hw_context.c
index e13b502..d716038 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -613,6 +613,22 @@ void r600_flush_emit(struct r600_context *rctx)
return;
}
 
+   if (rctx-flags  R600_CONTEXT_WAIT_3D_IDLE) {
+   wait_until |= S_008040_WAIT_3D_IDLE(1);
+   }
+   if (rctx-flags  R600_CONTEXT_WAIT_CP_DMA_IDLE) {
+   wait_until |= S_008040_WAIT_CP_DMA_IDLE(1);
+   }
+
+   if (wait_until) {
+   /* Use of WAIT_UNTIL is deprecated on Cayman+ */
+   if (rctx-family = CHIP_CAYMAN) {
+   /* emit a PS partial flush on Cayman/TN */
+   cs-buf[cs-cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
+   cs-buf[cs-cdw++] = 
EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
+   }
+   }
+
if (rctx-chip_class = R700 
(rctx-flags  R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
cs-buf[cs-cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
@@ -675,15 +691,12 @@ void r600_flush_emit(struct r600_context *rctx)
cs-buf[cs-cdw++] = 0x000A;  /* POLL_INTERVAL */
}
 
-   if (rctx-flags  R600_CONTEXT_WAIT_3D_IDLE) {
-   wait_until |= S_008040_WAIT_3D_IDLE(1);
-   }
-   if (rctx-flags  R600_CONTEXT_WAIT_CP_DMA_IDLE) {
-   wait_until |= S_008040_WAIT_CP_DMA_IDLE(1);
-   }
if (wait_until) {
-   /* wait for things to settle */
-   r600_write_config_reg(cs, R_008040_WAIT_UNTIL, wait_until);
+   /* Use of WAIT_UNTIL is deprecated on Cayman+ */
+   if (rctx-family  CHIP_CAYMAN) {
+   /* wait for things to settle */
+   r600_write_config_reg(cs, R_008040_WAIT_UNTIL, 
wait_until);
+   }
}
 
/* everything is properly flushed */
@@ -862,7 +875,13 @@ void r600_context_emit_fence(struct r600_context *ctx, 
struct r600_resource *fen
va = r600_resource_va(ctx-screen-screen, (void*)fence_bo);
va = va + (offset  2);
 
-   r600_write_config_reg(cs, R_008040_WAIT_UNTIL, 
S_008040_WAIT_3D_IDLE(1));
+   /* Use of WAIT_UNTIL is deprecated on Cayman+ */
+   if (ctx-family = CHIP_CAYMAN) {
+   cs-buf[cs-cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
+   cs-buf[cs-cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | 
EVENT_INDEX(4);
+   } else {
+   r600_write_config_reg(cs, R_008040_WAIT_UNTIL, 
S_008040_WAIT_3D_IDLE(1));
+   }
 
cs-buf[cs-cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
cs-buf[cs-cdw++] = 
EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
-- 
1.7.7.5

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[Mesa-dev] [PATCH] r600g: don't emit WAIT_UNTIL on cayman/TN

2013-01-27 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

It shouldn't be needed and older kernels don't support
it.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=59945

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/r600_hw_context.c |6 --
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_hw_context.c 
b/src/gallium/drivers/r600/r600_hw_context.c
index e13b502..310c19e 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -683,7 +683,8 @@ void r600_flush_emit(struct r600_context *rctx)
}
if (wait_until) {
/* wait for things to settle */
-   r600_write_config_reg(cs, R_008040_WAIT_UNTIL, wait_until);
+   if (rctx-family  CHIP_CAYMAN)
+   r600_write_config_reg(cs, R_008040_WAIT_UNTIL, 
wait_until);
}
 
/* everything is properly flushed */
@@ -862,7 +863,8 @@ void r600_context_emit_fence(struct r600_context *ctx, 
struct r600_resource *fen
va = r600_resource_va(ctx-screen-screen, (void*)fence_bo);
va = va + (offset  2);
 
-   r600_write_config_reg(cs, R_008040_WAIT_UNTIL, 
S_008040_WAIT_3D_IDLE(1));
+   if (ctx-family  CHIP_CAYMAN)
+   r600_write_config_reg(cs, R_008040_WAIT_UNTIL, 
S_008040_WAIT_3D_IDLE(1));
 
cs-buf[cs-cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
cs-buf[cs-cdw++] = 
EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
-- 
1.7.7.5

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[Mesa-dev] [PATCH] r600g: fix up CP DMA for VM on cayman and TN

2013-01-25 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Need to add the virtual address.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/r600.h|4 ++--
 src/gallium/drivers/r600/r600_hw_context.c |   11 +++
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index 93604fb..06e914f 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -172,8 +172,8 @@ void r600_context_streamout_end(struct r600_context *ctx);
 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean 
count_draw_in);
 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block 
*block, unsigned pkt_flags);
 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
-struct pipe_resource *dst, unsigned dst_offset,
-struct pipe_resource *src, unsigned src_offset,
+struct pipe_resource *dst, unsigned long 
dst_offset,
+struct pipe_resource *src, unsigned long 
src_offset,
 unsigned size);
 
 int evergreen_context_init(struct r600_context *ctx);
diff --git a/src/gallium/drivers/r600/r600_hw_context.c 
b/src/gallium/drivers/r600/r600_hw_context.c
index caebf5c..e13b502 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -1065,8 +1065,8 @@ void r600_context_streamout_end(struct r600_context *ctx)
 #define CP_DMA_MAX_BYTE_COUNT ((1  21) - 8)
 
 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
-struct pipe_resource *dst, unsigned dst_offset,
-struct pipe_resource *src, unsigned src_offset,
+struct pipe_resource *dst, unsigned long 
dst_offset,
+struct pipe_resource *src, unsigned long 
src_offset,
 unsigned size)
 {
struct radeon_winsys_cs *cs = rctx-cs;
@@ -1079,6 +1079,9 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx,
return;
}
 
+   dst_offset += r600_resource_va(rctx-screen-screen, dst);
+   src_offset += r600_resource_va(rctx-screen-screen, src);
+
/* We flush the caches, because we might read from or write
 * to resources which are bound right now. */
rctx-flags |= R600_CONTEXT_INVAL_READ_CACHES |
@@ -1112,9 +1115,9 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx,
 
r600_write_value(cs, PKT3(PKT3_CP_DMA, 4, 0));
r600_write_value(cs, src_offset);   /* SRC_ADDR_LO [31:0] */
-   r600_write_value(cs, sync); /* CP_SYNC [31] | 
SRC_ADDR_HI [7:0] */
+   r600_write_value(cs, sync | ((src_offset  32)  0xff));   
/* CP_SYNC [31] | SRC_ADDR_HI [7:0] */
r600_write_value(cs, dst_offset);   /* DST_ADDR_LO [31:0] */
-   r600_write_value(cs, 0);/* DST_ADDR_HI [7:0] */
+   r600_write_value(cs, (dst_offset  32)  0xff);
/* DST_ADDR_HI [7:0] */
r600_write_value(cs, byte_count);   /* COMMAND [29:22] | 
BYTE_COUNT [20:0] */
 
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
-- 
1.7.7.5

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[Mesa-dev] [PATCH 1/2] radeonsi: emit PA_SC_RASTER_CONFIG

2012-11-16 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Use per asic golden values.

Programming this register doesn't seem to be strictly
necessary on SI, but programming it wrong leads to
rendering issues or reduced performance so just
go ahead and program the golden values explicitly
to avoid any potential problems down the road.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/radeonsi/si_state.c |   11 +++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index db305d4..2bd55bb 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2665,5 +2665,16 @@ void si_init_config(struct r600_context *rctx)
 
si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
 
+   switch (rctx-screen-family) {
+   case CHIP_TAHITI:
+   case CHIP_PITCAIRN:
+   si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
+   break;
+   case CHIP_VERDE:
+   default:
+   si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x124a);
+   break;
+   }
+
si_pm4_set_state(rctx, init, pm4);
 }
-- 
1.7.7.5

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[Mesa-dev] [PATCH 2/2] radeonsi: clean up some magic numbers

2012-11-16 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/radeonsi/si_state.c |3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 2bd55bb..0683b67 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2655,7 +2655,8 @@ void si_init_config(struct r600_context *rctx)
   S_028AA8_PRIMGROUP_SIZE(63));
si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x);
si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
-   si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, (3  1) | 1);
+   si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
+  S_008A14_CLIP_VTX_REORDER_ENA(1));
 
si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
-- 
1.7.7.5

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[Mesa-dev] [PATCH 1/3] radeonsi: assert that the DB format is valid

2012-11-15 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Rather than disabling the depth buffer.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/radeonsi/si_state.c |9 +++--
 1 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index e7a4005..c5ae49a 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1687,6 +1687,8 @@ static void si_db(struct r600_context *rctx, struct 
si_pm4_state *pm4,
 
format = si_translate_dbformat(rtex-real_format);
 
+   assert(format != ~0U);
+
z_offs = r600_resource_va(rctx-context.screen, surf-base.texture);
z_offs += rtex-surface.level[level].offset;
 
@@ -1739,12 +1741,7 @@ static void si_db(struct r600_context *rctx, struct 
si_pm4_state *pm4,
   S_028008_SLICE_MAX(state-zsbuf-u.tex.last_layer));
 
si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1);
-   if (format != ~0U) {
-   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
-
-   } else {
-   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
-   }
+   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
 
if (rtex-surface.flags  RADEON_SURF_SBUFFER) {
si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
-- 
1.7.7.5

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[Mesa-dev] [PATCH 2/3] radeonsi: assert the CB format is valid

2012-11-15 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/radeonsi/si_state.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index c5ae49a..b4e09ed 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1606,6 +1606,7 @@ static void si_cb(struct r600_context *rctx, struct 
si_pm4_state *pm4,
}
 
format = si_translate_colorformat(surf-base.format);
+   assert(format != ~0U);
swap = si_translate_colorswap(surf-base.format);
if (rtex-resource.b.b.usage == PIPE_USAGE_STAGING) {
endian = V_028C70_ENDIAN_NONE;
-- 
1.7.7.5

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[Mesa-dev] [PATCH 3/3] radeonsi: cleanup si_db()

2012-11-15 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Clean up a few magic numbers and rework the code a bit.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
Reviewed-by: Christian König christian.koe...@amd.com
Reviewed-by: Michel Dänzer michel.daen...@amd.com
---
 src/gallium/drivers/radeonsi/si_state.c |   22 ++
 src/gallium/drivers/radeonsi/sid.h  |2 ++
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index b4e09ed..f2d9db8 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1677,8 +1677,8 @@ static void si_db(struct r600_context *rctx, struct 
si_pm4_state *pm4,
uint64_t z_offs, s_offs;
 
if (state-zsbuf == NULL) {
-   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
-   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
+   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 
S_028040_FORMAT(V_028040_Z_INVALID));
+   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 
S_028044_FORMAT(V_028044_STENCIL_INVALID));
return;
}
 
@@ -1707,7 +1707,10 @@ static void si_db(struct r600_context *rctx, struct 
si_pm4_state *pm4,
}
 
z_info = S_028040_FORMAT(format);
-   s_info = S_028044_FORMAT(1);
+   if (rtex-surface.flags  RADEON_SURF_SBUFFER)
+   s_info = S_028044_FORMAT(V_028044_STENCIL_8);
+   else
+   s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
 
if (rtex-surface.level[level].mode == RADEON_SURF_MODE_1D) {
z_info |= S_028040_TILE_MODE_INDEX(4);
@@ -1732,8 +1735,8 @@ static void si_db(struct r600_context *rctx, struct 
si_pm4_state *pm4,
} else {
R600_ERR(Invalid DB tiling mode %d!\n,
 rtex-surface.level[level].mode);
-   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
-   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
+   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 
S_028040_FORMAT(V_028040_Z_INVALID));
+   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 
S_028044_FORMAT(V_028044_STENCIL_INVALID));
return;
}
 
@@ -1741,14 +1744,9 @@ static void si_db(struct r600_context *rctx, struct 
si_pm4_state *pm4,
   S_028008_SLICE_START(state-zsbuf-u.tex.first_layer) |
   S_028008_SLICE_MAX(state-zsbuf-u.tex.last_layer));
 
-   si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1);
+   si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 
S_02803C_ADDR5_SWIZZLE_MASK(1));
si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
-
-   if (rtex-surface.flags  RADEON_SURF_SBUFFER) {
-   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
-   } else {
-   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
-   }
+   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
 
si_pm4_add_bo(pm4, rtex-resource, RADEON_USAGE_READWRITE);
si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
diff --git a/src/gallium/drivers/radeonsi/sid.h 
b/src/gallium/drivers/radeonsi/sid.h
index bc5fcda..57553a6 100644
--- a/src/gallium/drivers/radeonsi/sid.h
+++ b/src/gallium/drivers/radeonsi/sid.h
@@ -4645,6 +4645,8 @@
 #define   S_028044_FORMAT(x)  (((x)  
0x1)  0)
 #define   G_028044_FORMAT(x)  (((x)  
0)  0x1)
 #define   C_028044_FORMAT 
0xFFFE
+#define V_028044_STENCIL_INVALID0x00
+#define V_028044_STENCIL_8  0x01
 #define   S_028044_TILE_MODE_INDEX(x) (((x)  
0x07)  20)
 #define   G_028044_TILE_MODE_INDEX(x) (((x)  
20)  0x07)
 #define   C_028044_TILE_MODE_INDEX
0xFF8F
-- 
1.7.7.5

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[Mesa-dev] [PATCH 1/3] radeonsi: assert that the DB format is valid (v2)

2012-11-15 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Rather than disabling the depth buffer.

v2: use INVALID hw format rather than ~0U

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/radeonsi/si_state.c |   13 +
 1 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index e7a4005..fbc636d 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1109,7 +1109,7 @@ static uint32_t si_translate_dbformat(enum pipe_format 
format)
case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
return V_028040_Z_32_FLOAT;
default:
-   return ~0U;
+   return V_028040_Z_INVALID;
}
 }
 
@@ -1438,7 +1438,7 @@ static bool si_is_colorbuffer_format_supported(enum 
pipe_format format)
 
 static bool si_is_zs_format_supported(enum pipe_format format)
 {
-   return si_translate_dbformat(format) != ~0U;
+   return si_translate_dbformat(format) != V_028040_Z_INVALID;
 }
 
 boolean si_is_format_supported(struct pipe_screen *screen,
@@ -1687,6 +1687,8 @@ static void si_db(struct r600_context *rctx, struct 
si_pm4_state *pm4,
 
format = si_translate_dbformat(rtex-real_format);
 
+   assert(format != V_028040_Z_INVALID);
+
z_offs = r600_resource_va(rctx-context.screen, surf-base.texture);
z_offs += rtex-surface.level[level].offset;
 
@@ -1739,12 +1741,7 @@ static void si_db(struct r600_context *rctx, struct 
si_pm4_state *pm4,
   S_028008_SLICE_MAX(state-zsbuf-u.tex.last_layer));
 
si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1);
-   if (format != ~0U) {
-   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
-
-   } else {
-   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
-   }
+   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
 
if (rtex-surface.flags  RADEON_SURF_SBUFFER) {
si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
-- 
1.7.7.5

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[Mesa-dev] [PATCH 2/3] radeonsi: assert the CB format is valid (v2)

2012-11-15 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

v2: use INVALID hw format rather than ~0U

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/radeonsi/si_state.c |5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index fbc636d..31a55a2 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -831,7 +831,7 @@ static uint32_t si_translate_colorformat(enum pipe_format 
format)
case PIPE_FORMAT_R4A4_UNORM:
case PIPE_FORMAT_A4R4_UNORM:
default:
-   return ~0U; /* Unsupported. */
+   return V_028C70_COLOR_INVALID; /* Unsupported. */
}
 }
 
@@ -1432,7 +1432,7 @@ static bool si_is_vertex_format_supported(struct 
pipe_screen *screen, enum pipe_
 
 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
 {
-   return si_translate_colorformat(format) != ~0U 
+   return si_translate_colorformat(format) != V_028C70_COLOR_INVALID 
si_translate_colorswap(format) != ~0U;
 }
 
@@ -1606,6 +1606,7 @@ static void si_cb(struct r600_context *rctx, struct 
si_pm4_state *pm4,
}
 
format = si_translate_colorformat(surf-base.format);
+   assert(format != V_028C70_COLOR_INVALID);
swap = si_translate_colorswap(surf-base.format);
if (rtex-resource.b.b.usage == PIPE_USAGE_STAGING) {
endian = V_028C70_ENDIAN_NONE;
-- 
1.7.7.5

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[Mesa-dev] [PATCH 3/3] radeonsi: cleanup si_db()

2012-11-15 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Clean up a few magic numbers and rework the code a bit.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
Reviewed-by: Christian König christian.koe...@amd.com
Reviewed-by: Michel Dänzer michel.daen...@amd.com
---
 src/gallium/drivers/radeonsi/si_state.c |   22 ++
 src/gallium/drivers/radeonsi/sid.h  |2 ++
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 31a55a2..e0e0524 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1677,8 +1677,8 @@ static void si_db(struct r600_context *rctx, struct 
si_pm4_state *pm4,
uint64_t z_offs, s_offs;
 
if (state-zsbuf == NULL) {
-   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
-   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
+   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 
S_028040_FORMAT(V_028040_Z_INVALID));
+   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 
S_028044_FORMAT(V_028044_STENCIL_INVALID));
return;
}
 
@@ -1707,7 +1707,10 @@ static void si_db(struct r600_context *rctx, struct 
si_pm4_state *pm4,
}
 
z_info = S_028040_FORMAT(format);
-   s_info = S_028044_FORMAT(1);
+   if (rtex-surface.flags  RADEON_SURF_SBUFFER)
+   s_info = S_028044_FORMAT(V_028044_STENCIL_8);
+   else
+   s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
 
if (rtex-surface.level[level].mode == RADEON_SURF_MODE_1D) {
z_info |= S_028040_TILE_MODE_INDEX(4);
@@ -1732,8 +1735,8 @@ static void si_db(struct r600_context *rctx, struct 
si_pm4_state *pm4,
} else {
R600_ERR(Invalid DB tiling mode %d!\n,
 rtex-surface.level[level].mode);
-   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
-   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
+   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 
S_028040_FORMAT(V_028040_Z_INVALID));
+   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 
S_028044_FORMAT(V_028044_STENCIL_INVALID));
return;
}
 
@@ -1741,14 +1744,9 @@ static void si_db(struct r600_context *rctx, struct 
si_pm4_state *pm4,
   S_028008_SLICE_START(state-zsbuf-u.tex.first_layer) |
   S_028008_SLICE_MAX(state-zsbuf-u.tex.last_layer));
 
-   si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1);
+   si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 
S_02803C_ADDR5_SWIZZLE_MASK(1));
si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
-
-   if (rtex-surface.flags  RADEON_SURF_SBUFFER) {
-   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
-   } else {
-   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
-   }
+   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
 
si_pm4_add_bo(pm4, rtex-resource, RADEON_USAGE_READWRITE);
si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
diff --git a/src/gallium/drivers/radeonsi/sid.h 
b/src/gallium/drivers/radeonsi/sid.h
index bc5fcda..57553a6 100644
--- a/src/gallium/drivers/radeonsi/sid.h
+++ b/src/gallium/drivers/radeonsi/sid.h
@@ -4645,6 +4645,8 @@
 #define   S_028044_FORMAT(x)  (((x)  
0x1)  0)
 #define   G_028044_FORMAT(x)  (((x)  
0)  0x1)
 #define   C_028044_FORMAT 
0xFFFE
+#define V_028044_STENCIL_INVALID0x00
+#define V_028044_STENCIL_8  0x01
 #define   S_028044_TILE_MODE_INDEX(x) (((x)  
0x07)  20)
 #define   G_028044_TILE_MODE_INDEX(x) (((x)  
20)  0x07)
 #define   C_028044_TILE_MODE_INDEX
0xFF8F
-- 
1.7.7.5

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[Mesa-dev] [PATCH 1/3] radeonsi: return Z_INVALID if the Z buffer is invalid

2012-11-14 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

setting the DB format to Z_INVALID disables the depth buffer.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/radeonsi/si_state.c |   10 +++---
 1 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index e7a4005..1f76788 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1109,7 +1109,7 @@ static uint32_t si_translate_dbformat(enum pipe_format 
format)
case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
return V_028040_Z_32_FLOAT;
default:
-   return ~0U;
+   return V_028040_Z_INVALID;
}
 }
 
@@ -1438,7 +1438,7 @@ static bool si_is_colorbuffer_format_supported(enum 
pipe_format format)
 
 static bool si_is_zs_format_supported(enum pipe_format format)
 {
-   return si_translate_dbformat(format) != ~0U;
+   return si_translate_dbformat(format) != V_028040_Z_INVALID;
 }
 
 boolean si_is_format_supported(struct pipe_screen *screen,
@@ -1739,12 +1739,8 @@ static void si_db(struct r600_context *rctx, struct 
si_pm4_state *pm4,
   S_028008_SLICE_MAX(state-zsbuf-u.tex.last_layer));
 
si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1);
-   if (format != ~0U) {
-   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
 
-   } else {
-   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
-   }
+   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
 
if (rtex-surface.flags  RADEON_SURF_SBUFFER) {
si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
-- 
1.7.7.5

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[Mesa-dev] [PATCH 2/3] radeonsi: return_INVALID if the color buffer is invalid

2012-11-14 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

setting the CB format to Z_INVALID disables the color buffer.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/radeonsi/si_state.c |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 1f76788..a41bcf0 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -831,7 +831,7 @@ static uint32_t si_translate_colorformat(enum pipe_format 
format)
case PIPE_FORMAT_R4A4_UNORM:
case PIPE_FORMAT_A4R4_UNORM:
default:
-   return ~0U; /* Unsupported. */
+   return V_028C70_COLOR_INVALID; /* Unsupported. */
}
 }
 
@@ -1432,7 +1432,7 @@ static bool si_is_vertex_format_supported(struct 
pipe_screen *screen, enum pipe_
 
 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
 {
-   return si_translate_colorformat(format) != ~0U 
+   return si_translate_colorformat(format) != V_028C70_COLOR_INVALID 
si_translate_colorswap(format) != ~0U;
 }
 
-- 
1.7.7.5

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[Mesa-dev] [PATCH 3/3] radeonsi: cleanup si_db()

2012-11-14 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Clean up a few magic numbers and rework the code a bit.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/radeonsi/si_state.c |   22 ++
 src/gallium/drivers/radeonsi/sid.h  |2 ++
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index a41bcf0..dd5af52 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1676,8 +1676,8 @@ static void si_db(struct r600_context *rctx, struct 
si_pm4_state *pm4,
uint64_t z_offs, s_offs;
 
if (state-zsbuf == NULL) {
-   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
-   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
+   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 
S_028040_FORMAT(V_028040_Z_INVALID));
+   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 
S_028044_FORMAT(V_028044_STENCIL_INVALID));
return;
}
 
@@ -1704,7 +1704,10 @@ static void si_db(struct r600_context *rctx, struct 
si_pm4_state *pm4,
}
 
z_info = S_028040_FORMAT(format);
-   s_info = S_028044_FORMAT(1);
+   if (rtex-surface.flags  RADEON_SURF_SBUFFER)
+   s_info = S_028044_FORMAT(V_028044_STENCIL_8);
+   else
+   s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
 
if (rtex-surface.level[level].mode == RADEON_SURF_MODE_1D) {
z_info |= S_028040_TILE_MODE_INDEX(4);
@@ -1729,8 +1732,8 @@ static void si_db(struct r600_context *rctx, struct 
si_pm4_state *pm4,
} else {
R600_ERR(Invalid DB tiling mode %d!\n,
 rtex-surface.level[level].mode);
-   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
-   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
+   si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 
S_028040_FORMAT(V_028040_Z_INVALID));
+   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 
S_028044_FORMAT(V_028044_STENCIL_INVALID));
return;
}
 
@@ -1738,15 +1741,10 @@ static void si_db(struct r600_context *rctx, struct 
si_pm4_state *pm4,
   S_028008_SLICE_START(state-zsbuf-u.tex.first_layer) |
   S_028008_SLICE_MAX(state-zsbuf-u.tex.last_layer));
 
-   si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1);
+   si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 
S_02803C_ADDR5_SWIZZLE_MASK(1));
 
si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
-
-   if (rtex-surface.flags  RADEON_SURF_SBUFFER) {
-   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
-   } else {
-   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
-   }
+   si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
 
si_pm4_add_bo(pm4, rtex-resource, RADEON_USAGE_READWRITE);
si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
diff --git a/src/gallium/drivers/radeonsi/sid.h 
b/src/gallium/drivers/radeonsi/sid.h
index bc5fcda..57553a6 100644
--- a/src/gallium/drivers/radeonsi/sid.h
+++ b/src/gallium/drivers/radeonsi/sid.h
@@ -4645,6 +4645,8 @@
 #define   S_028044_FORMAT(x)  (((x)  
0x1)  0)
 #define   G_028044_FORMAT(x)  (((x)  
0)  0x1)
 #define   C_028044_FORMAT 
0xFFFE
+#define V_028044_STENCIL_INVALID0x00
+#define V_028044_STENCIL_8  0x01
 #define   S_028044_TILE_MODE_INDEX(x) (((x)  
0x07)  20)
 #define   G_028044_TILE_MODE_INDEX(x) (((x)  
20)  0x07)
 #define   C_028044_TILE_MODE_INDEX
0xFF8F
-- 
1.7.7.5

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[Mesa-dev] [PATCH 0/5] r600g: Fix common state for cayman compute

2012-10-25 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

This patch set cleans up and unifies the common state and CS init
set up between evergreen and cayman and gfx and compute.  No piglit
regressions on the gfx side here.  This also allows compute to run
on cayman without causing a CS error in the kernel when VM is enabled
due to emitting some evergreen-only registers.  However, the GPU
hangs on the cayman compute command buffer.

Alex Deucher (5):
  r600g/compute: always CONTEXT_CONTROL packet at start of CS
  r600g: rework evergreen_init_common_regs()
  r600g: there are 16 const buffer size regs for each shader stage
  r600g: emit some additional regs on cayman
  r600g: split cayman common state out into a shared function

 src/gallium/drivers/r600/evergreen_compute.c |   17 ++-
 src/gallium/drivers/r600/evergreen_state.c   |  177 ++
 src/gallium/drivers/r600/evergreend.h|1 +
 src/gallium/drivers/r600/r600_pipe.h |4 +
 4 files changed, 146 insertions(+), 53 deletions(-)

-- 
1.7.7.5

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[Mesa-dev] [PATCH 1/5] r600g/compute: always CONTEXT_CONTROL packet at start of CS

2012-10-25 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

It's required.  The CP uses this to properly allocate new
contexts.  Also do a CS partial flush since we are updating
CONFIG regs which are single state.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/evergreen_compute.c |9 +
 src/gallium/drivers/r600/evergreend.h|1 +
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_compute.c 
b/src/gallium/drivers/r600/evergreen_compute.c
index 655cf75..55906c9 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -626,6 +626,15 @@ void evergreen_init_atom_start_compute_cs(struct 
r600_context *ctx)
r600_init_command_buffer(cb, 256);
cb-pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
 
+   /* This must be first. */
+   r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
+   r600_store_value(cb, 0x8000);
+   r600_store_value(cb, 0x8000);
+
+   /* We're setting config registers here. */
+   r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
+   r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | 
EVENT_INDEX(4));
+
switch (ctx-family) {
case CHIP_CEDAR:
default:
diff --git a/src/gallium/drivers/r600/evergreend.h 
b/src/gallium/drivers/r600/evergreend.h
index d10ec7f..98df83d 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -43,6 +43,7 @@
 #define EVERGREEN_CTL_CONST_OFFSET  0x0003CFF0
 #define EVERGREEN_CTL_CONST_END 0x0003FF0C
 
+#define EVENT_TYPE_CS_PARTIAL_FLUSH0x07
 #define EVENT_TYPE_PS_PARTIAL_FLUSH0x10
 #define EVENT_TYPE_ZPASS_DONE  0x15
 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT   0x16
-- 
1.7.7.5

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[Mesa-dev] [PATCH 2/5] r600g: rework evergreen_init_common_regs()

2012-10-25 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

Move gfx specific bits out as the code is shared with
compute.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/evergreen_state.c |   73 +---
 1 files changed, 33 insertions(+), 40 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 88e1682..0d02d52 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2679,47 +2679,9 @@ void evergreen_init_common_regs(struct 
r600_command_buffer *cb,
 
r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
 
-   r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
-   r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
-   r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
-
-   r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0x);
-
-   r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
-   r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
-   r600_store_value(cb, 0x3F80); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
-
-   r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
-   r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
-   r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
-   r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
-
/* The cs checker requires this register to be set. */
r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
 
-   r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, 
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
-   r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, 
S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
-
-   /* to avoid GPU doing any preloading of constant from random address */
-   r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
-   r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
-   r600_store_value(cb, 0);
-   r600_store_value(cb, 0);
-   r600_store_value(cb, 0);
-   r600_store_value(cb, 0);
-   r600_store_value(cb, 0);
-   r600_store_value(cb, 0);
-   r600_store_value(cb, 0);
-   r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
-   r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
-   r600_store_value(cb, 0);
-   r600_store_value(cb, 0);
-   r600_store_value(cb, 0);
-   r600_store_value(cb, 0);
-   r600_store_value(cb, 0);
-   r600_store_value(cb, 0);
-   r600_store_value(cb, 0);
-
r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, 
S_028354_SURFACE_SYNC_MASK(0xf));
 
return;
@@ -2760,8 +2722,8 @@ void evergreen_init_atom_start_cs(struct r600_context 
*rctx)
r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | 
EVENT_INDEX(4));
 
-   evergreen_init_common_regs(cb, rctx-chip_class
-   , rctx-family, rctx-screen-info.drm_minor);
+   evergreen_init_common_regs(cb, rctx-chip_class,
+  rctx-family, rctx-screen-info.drm_minor);
 
family = rctx-family;
switch (family) {
@@ -3015,6 +2977,11 @@ void evergreen_init_atom_start_cs(struct r600_context 
*rctx)
 
r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0x);
+   r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0x);
+
+   r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
+   r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
+   r600_store_value(cb, 0x3F80); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
 
r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x043F);
@@ -3039,8 +3006,34 @@ void evergreen_init_atom_start_cs(struct r600_context 
*rctx)
r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* 
R_028034_PA_SC_SCREEN_SCISSOR_BR */
 
+   r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, 
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
+   r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, 
S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
 
+   /* to avoid GPU doing any preloading of constant from random address */
+   r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
+   r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+

[Mesa-dev] [PATCH 3/5] r600g: there are 16 const buffer size regs for each shader stage

2012-10-25 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

we were previously only setting 8 of them.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/evergreen_state.c |   21 +++--
 1 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 0d02d52..29e6822 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3011,7 +3011,7 @@ void evergreen_init_atom_start_cs(struct r600_context 
*rctx)
r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
 
/* to avoid GPU doing any preloading of constant from random address */
-   r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
+   r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
r600_store_value(cb, 0);
r600_store_value(cb, 0);
@@ -3020,7 +3020,16 @@ void evergreen_init_atom_start_cs(struct r600_context 
*rctx)
r600_store_value(cb, 0);
r600_store_value(cb, 0);
r600_store_value(cb, 0);
-   r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+
+   r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
r600_store_value(cb, 0);
r600_store_value(cb, 0);
@@ -3029,6 +3038,14 @@ void evergreen_init_atom_start_cs(struct r600_context 
*rctx)
r600_store_value(cb, 0);
r600_store_value(cb, 0);
r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
 
r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
-- 
1.7.7.5

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[Mesa-dev] [PATCH 4/5] r600g: emit some additional regs on cayman

2012-10-25 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

These are common to both evergreen and cayman, but were
not emitted on cayman.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/evergreen_state.c |   54 
 1 files changed, 54 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 29e6822..1bf6996 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2455,6 +2455,23 @@ static void cayman_init_atom_start_cs(struct 
r600_context *rctx)
 
r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
 
+   r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
+   r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, 
S_00913C_VTX_DONE_DELAY(4));
+
+   r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
+   r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
+   r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
+   r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
+   r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
+   r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
+   r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
+
+   r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
+   r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
+   r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
+   r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
+   r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
+
r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
@@ -2568,6 +2585,43 @@ static void cayman_init_atom_start_cs(struct 
r600_context *rctx)
r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, 
S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
 
+   /* to avoid GPU doing any preloading of constant from random address */
+   r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
+   r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+
+   r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
+   r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+   r600_store_value(cb, 0);
+
r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, 
S_028354_SURFACE_SYNC_MASK(0xf));
r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
if (rctx-screen-has_streamout) {
-- 
1.7.7.5

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[Mesa-dev] [PATCH 5/5] r600g: split cayman common state out into a shared function

2012-10-25 Thread alexdeucher

From: Alex Deucher alexander.deuc...@amd.com

And use it for compute.  This should improve compute support
on cayman.

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 src/gallium/drivers/r600/evergreen_compute.c |8 -
 src/gallium/drivers/r600/evergreen_state.c   |   39 -
 src/gallium/drivers/r600/r600_pipe.h |4 ++
 3 files changed, 35 insertions(+), 16 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_compute.c 
b/src/gallium/drivers/r600/evergreen_compute.c
index 55906c9..1e1ed4a 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -681,8 +681,12 @@ void evergreen_init_atom_start_compute_cs(struct 
r600_context *ctx)
}
 
/* Config Registers */
-   evergreen_init_common_regs(cb, ctx-chip_class
-   , ctx-family, ctx-screen-info.drm_minor);
+   if (ctx-chip_class  CAYMAN)
+   evergreen_init_common_regs(cb, ctx-chip_class, ctx-family,
+  ctx-screen-info.drm_minor);
+   else
+   cayman_init_common_regs(cb, ctx-chip_class, ctx-family,
+   ctx-screen-info.drm_minor);
 
/* The primitive type always needs to be POINTLIST for compute. */
r600_store_config_reg(cb, R_008958_VGT_PRIMITIVE_TYPE,
diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 1bf6996..96e246a 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2427,6 +2427,29 @@ void evergreen_init_state_functions(struct r600_context 
*rctx)
evergreen_init_compute_state_functions(rctx);
 }
 
+void cayman_init_common_regs(struct r600_command_buffer *cb,
+enum chip_class ctx_chip_class,
+enum radeon_family ctx_family,
+int ctx_drm_minor)
+{
+   r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
+   r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
+   /* always set the temp clauses */
+   r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* 
R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
+
+   r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 
2);
+   r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
+   r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
+
+   r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1  
8));
+
+   r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
+
+   r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, 
S_028354_SURFACE_SYNC_MASK(0xf));
+
+   r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
+}
+
 static void cayman_init_atom_start_cs(struct r600_context *rctx)
 {
struct r600_command_buffer *cb = rctx-start_cs_cmd;
@@ -2442,18 +2465,8 @@ static void cayman_init_atom_start_cs(struct 
r600_context *rctx)
r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | 
EVENT_INDEX(4));
 
-   r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
-   r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
-   /* always set the temp clauses */
-   r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* 
R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
-
-   r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 
2);
-   r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
-   r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
-
-   r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1  
8));
-
-   r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
+   cayman_init_common_regs(cb, rctx-chip_class,
+   rctx-family, rctx-screen-info.drm_minor);
 
r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, 
S_00913C_VTX_DONE_DELAY(4));
@@ -2622,8 +2635,6 @@ static void cayman_init_atom_start_cs(struct r600_context 
*rctx)
r600_store_value(cb, 0);
r600_store_value(cb, 0);
 
-   r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, 
S_028354_SURFACE_SYNC_MASK(0xf));
-   r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
if (rctx-screen-has_streamout) {
r600_store_context_reg(cb, 
R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
}
diff --git a/src/gallium/drivers/r600/r600_pipe.h 
b/src/gallium/drivers/r600/r600_pipe.h
index 2690c1b..3474a59 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -512,6 +512,10 @@ void evergreen_init_common_regs(struct r600_command_buffer 
*cb,
enum chip_class

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