Re: [Mesa-dev] [PATCH] gallivm/radeonsi: allow to pass two swizzles into fetches.
On 2018-08-31 2:14 a.m., Dave Airlie wrote: > On Fri., 31 Aug. 2018, 01:22 Michel Dänzer, wrote: >> >> On 2018-08-27 11:16 p.m., Dave Airlie wrote: >>> From: Dave Airlie >>> >>> This hijacks the top 16-bits of swizzle, to pass in the swizzle >>> for the second channel. >>> >>> This fixes handling .yx swizzles of 64-bit values. >>> >>> This should fixup radeonsi and llvmpipe. >>> >>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107524 >> >> This change broke a bunch of piglit tests for me with radeonsi on >> Bonair >> > > Wierd I did piglit runs locally, but I must have screwed them up somehow. Shit happens. :) > I've sent two patches to fix up the regressions, thanks for finding > and reporting them! Thank you for fixing them up so promptly! -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gallivm/radeonsi: allow to pass two swizzles into fetches.
On Fri., 31 Aug. 2018, 01:22 Michel Dänzer, wrote: > > On 2018-08-27 11:16 p.m., Dave Airlie wrote: > > From: Dave Airlie > > > > This hijacks the top 16-bits of swizzle, to pass in the swizzle > > for the second channel. > > > > This fixes handling .yx swizzles of 64-bit values. > > > > This should fixup radeonsi and llvmpipe. > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107524 > > This change broke a bunch of piglit tests for me with radeonsi on > Bonair > Wierd I did piglit runs locally, but I must have screwed them up somehow. I've sent two patches to fix up the regressions, thanks for finding and reporting them! Dave. > spec@arb_enhanced_layouts@execution@component-layout@vs-fs-array-dvec3 > spec@arb_tessellation_shader@execution@dvec2-vs-tcs-tes > spec@arb_tessellation_shader@execution@double-array-vs-tcs-tes > spec@arb_tessellation_shader@execution@double-vs-tcs-tes > spec@arb_tessellation_shader@execution@dvec3-vs-tcs-tes > spec@arb_tessellation_shader@execution@variable-indexing@tes-input-array-dvec4-index-rd > spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-dvec4-index-wr-before-tcs > spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-dvec4-index-wr > spec@arb_tessellation_shader@execution@variable-indexing@tcs-input-array-dvec4-index-rd > > > -- > Earthling Michel Dänzer | http://www.amd.com > Libre software enthusiast | Mesa and X developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gallivm/radeonsi: allow to pass two swizzles into fetches.
On 2018-08-27 11:16 p.m., Dave Airlie wrote: > From: Dave Airlie > > This hijacks the top 16-bits of swizzle, to pass in the swizzle > for the second channel. > > This fixes handling .yx swizzles of 64-bit values. > > This should fixup radeonsi and llvmpipe. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107524 This change broke a bunch of piglit tests for me with radeonsi on Bonaire: spec@arb_enhanced_layouts@execution@component-layout@vs-fs-array-dvec3 spec@arb_tessellation_shader@execution@dvec2-vs-tcs-tes spec@arb_tessellation_shader@execution@double-array-vs-tcs-tes spec@arb_tessellation_shader@execution@double-vs-tcs-tes spec@arb_tessellation_shader@execution@dvec3-vs-tcs-tes spec@arb_tessellation_shader@execution@variable-indexing@tes-input-array-dvec4-index-rd spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-dvec4-index-wr-before-tcs spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-dvec4-index-wr spec@arb_tessellation_shader@execution@variable-indexing@tcs-input-array-dvec4-index-rd -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gallivm/radeonsi: allow to pass two swizzles into fetches.
Reviewed-by: Marek Olšák
Marek
On Mon, Aug 27, 2018 at 5:16 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> This hijacks the top 16-bits of swizzle, to pass in the swizzle
> for the second channel.
>
> This fixes handling .yx swizzles of 64-bit values.
>
> This should fixup radeonsi and llvmpipe.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107524
> ---
> src/gallium/auxiliary/gallivm/lp_bld_tgsi.c | 9 ++
> .../auxiliary/gallivm/lp_bld_tgsi_soa.c | 86 ---
> src/gallium/drivers/radeonsi/si_shader.c | 7 +-
> .../drivers/radeonsi/si_shader_tgsi_setup.c | 18 ++--
> 4 files changed, 79 insertions(+), 41 deletions(-)
>
> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
> b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
> index 64d2cd703be..2c3be8fb127 100644
> --- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
> +++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
> @@ -353,6 +353,15 @@ lp_build_emit_fetch_src(
> assert(0 && "invalid swizzle in emit_fetch()");
> return bld_base->base.undef;
>}
> + if (tgsi_type_is_64bit(stype)) {
> +unsigned swizzle2;
> +swizzle2 = tgsi_util_get_full_src_register_swizzle(reg, chan_index +
> 1);
> +if (swizzle2 > 3) {
> + assert(0 && "invalid swizzle in emit_fetch()");
> + return bld_base->base.undef;
> +}
> +swizzle |= (swizzle2 << 16);
> + }
> }
>
> assert(reg->Register.Index <=
> bld_base->info->file_max[reg->Register.File]);
> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
> b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
> index 83d7dbea9a2..79ece639e35 100644
> --- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
> +++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
> @@ -1190,7 +1190,7 @@ emit_fetch_constant(
> struct lp_build_tgsi_context * bld_base,
> const struct tgsi_full_src_register * reg,
> enum tgsi_opcode_type stype,
> - unsigned swizzle)
> + unsigned swizzle_in)
> {
> struct lp_build_tgsi_soa_context * bld = lp_soa_context(bld_base);
> struct gallivm_state *gallivm = bld_base->base.gallivm;
> @@ -1200,6 +1200,7 @@ emit_fetch_constant(
> LLVMValueRef consts_ptr;
> LLVMValueRef num_consts;
> LLVMValueRef res;
> + unsigned swizzle = swizzle_in & 0x;
>
> /* XXX: Handle fetching xyzw components as a vector */
> assert(swizzle != ~0u);
> @@ -1241,7 +1242,7 @@ emit_fetch_constant(
>
>if (tgsi_type_is_64bit(stype)) {
> LLVMValueRef swizzle_vec2;
> - swizzle_vec2 = lp_build_const_int_vec(gallivm, uint_bld->type,
> swizzle + 1);
> + swizzle_vec2 = lp_build_const_int_vec(gallivm, uint_bld->type,
> swizzle_in >> 16);
> index_vec2 = lp_build_shl_imm(uint_bld, indirect_index, 2);
> index_vec2 = lp_build_add(uint_bld, index_vec2, swizzle_vec2);
>}
> @@ -1256,21 +1257,42 @@ emit_fetch_constant(
>
>scalar_ptr = LLVMBuildGEP(builder, consts_ptr,
> , 1, "");
> - if (stype == TGSI_TYPE_DOUBLE) {
> - LLVMTypeRef dptr_type =
> LLVMPointerType(LLVMDoubleTypeInContext(gallivm->context), 0);
> - scalar_ptr = LLVMBuildBitCast(builder, scalar_ptr, dptr_type, "");
> - bld_broad = _base->dbl_bld;
> - } else if (stype == TGSI_TYPE_UNSIGNED64) {
> - LLVMTypeRef u64ptr_type =
> LLVMPointerType(LLVMInt64TypeInContext(gallivm->context), 0);
> - scalar_ptr = LLVMBuildBitCast(builder, scalar_ptr, u64ptr_type, "");
> - bld_broad = _base->uint64_bld;
> - } else if (stype == TGSI_TYPE_SIGNED64) {
> - LLVMTypeRef i64ptr_type =
> LLVMPointerType(LLVMInt64TypeInContext(gallivm->context), 0);
> - scalar_ptr = LLVMBuildBitCast(builder, scalar_ptr, i64ptr_type, "");
> - bld_broad = _base->int64_bld;
> +
> + if (tgsi_type_is_64bit(stype) && ((swizzle_in >> 16) != swizzle + 1)) {
> +
> + LLVMValueRef scalar2, scalar2_ptr;
> + LLVMValueRef shuffles[2];
> + index = lp_build_const_int32(gallivm, reg->Register.Index * 4 +
> (swizzle_in >> 16));
> +
> + scalar2_ptr = LLVMBuildGEP(builder, consts_ptr,
> +, 1, "");
> +
> + scalar = LLVMBuildLoad(builder, scalar_ptr, "");
> + scalar2 = LLVMBuildLoad(builder, scalar2_ptr, "");
> + shuffles[0] = lp_build_const_int32(gallivm, 0);
> + shuffles[1] = lp_build_const_int32(gallivm, 1);
> +
> + res =
> LLVMGetUndef(LLVMVectorType(LLVMFloatTypeInContext(gallivm->context),
> bld_base->base.type.length * 2));
> + res = LLVMBuildInsertElement(builder, res, scalar, shuffles[0], "");
> + res = LLVMBuildInsertElement(builder, res, scalar2, shuffles[1],
> "");
> + } else {
> +if (stype == TGSI_TYPE_DOUBLE) {
> + LLVMTypeRef dptr_type =
> LLVMPointerType(LLVMDoubleTypeInContext(gallivm->context), 0);
> +
[Mesa-dev] [PATCH] gallivm/radeonsi: allow to pass two swizzles into fetches.
From: Dave Airlie
This hijacks the top 16-bits of swizzle, to pass in the swizzle
for the second channel.
This fixes handling .yx swizzles of 64-bit values.
This should fixup radeonsi and llvmpipe.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107524
---
src/gallium/auxiliary/gallivm/lp_bld_tgsi.c | 9 ++
.../auxiliary/gallivm/lp_bld_tgsi_soa.c | 86 ---
src/gallium/drivers/radeonsi/si_shader.c | 7 +-
.../drivers/radeonsi/si_shader_tgsi_setup.c | 18 ++--
4 files changed, 79 insertions(+), 41 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
index 64d2cd703be..2c3be8fb127 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
@@ -353,6 +353,15 @@ lp_build_emit_fetch_src(
assert(0 && "invalid swizzle in emit_fetch()");
return bld_base->base.undef;
}
+ if (tgsi_type_is_64bit(stype)) {
+unsigned swizzle2;
+swizzle2 = tgsi_util_get_full_src_register_swizzle(reg, chan_index +
1);
+if (swizzle2 > 3) {
+ assert(0 && "invalid swizzle in emit_fetch()");
+ return bld_base->base.undef;
+}
+swizzle |= (swizzle2 << 16);
+ }
}
assert(reg->Register.Index <= bld_base->info->file_max[reg->Register.File]);
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
index 83d7dbea9a2..79ece639e35 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
@@ -1190,7 +1190,7 @@ emit_fetch_constant(
struct lp_build_tgsi_context * bld_base,
const struct tgsi_full_src_register * reg,
enum tgsi_opcode_type stype,
- unsigned swizzle)
+ unsigned swizzle_in)
{
struct lp_build_tgsi_soa_context * bld = lp_soa_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
@@ -1200,6 +1200,7 @@ emit_fetch_constant(
LLVMValueRef consts_ptr;
LLVMValueRef num_consts;
LLVMValueRef res;
+ unsigned swizzle = swizzle_in & 0x;
/* XXX: Handle fetching xyzw components as a vector */
assert(swizzle != ~0u);
@@ -1241,7 +1242,7 @@ emit_fetch_constant(
if (tgsi_type_is_64bit(stype)) {
LLVMValueRef swizzle_vec2;
- swizzle_vec2 = lp_build_const_int_vec(gallivm, uint_bld->type,
swizzle + 1);
+ swizzle_vec2 = lp_build_const_int_vec(gallivm, uint_bld->type,
swizzle_in >> 16);
index_vec2 = lp_build_shl_imm(uint_bld, indirect_index, 2);
index_vec2 = lp_build_add(uint_bld, index_vec2, swizzle_vec2);
}
@@ -1256,21 +1257,42 @@ emit_fetch_constant(
scalar_ptr = LLVMBuildGEP(builder, consts_ptr,
, 1, "");
- if (stype == TGSI_TYPE_DOUBLE) {
- LLVMTypeRef dptr_type =
LLVMPointerType(LLVMDoubleTypeInContext(gallivm->context), 0);
- scalar_ptr = LLVMBuildBitCast(builder, scalar_ptr, dptr_type, "");
- bld_broad = _base->dbl_bld;
- } else if (stype == TGSI_TYPE_UNSIGNED64) {
- LLVMTypeRef u64ptr_type =
LLVMPointerType(LLVMInt64TypeInContext(gallivm->context), 0);
- scalar_ptr = LLVMBuildBitCast(builder, scalar_ptr, u64ptr_type, "");
- bld_broad = _base->uint64_bld;
- } else if (stype == TGSI_TYPE_SIGNED64) {
- LLVMTypeRef i64ptr_type =
LLVMPointerType(LLVMInt64TypeInContext(gallivm->context), 0);
- scalar_ptr = LLVMBuildBitCast(builder, scalar_ptr, i64ptr_type, "");
- bld_broad = _base->int64_bld;
+
+ if (tgsi_type_is_64bit(stype) && ((swizzle_in >> 16) != swizzle + 1)) {
+
+ LLVMValueRef scalar2, scalar2_ptr;
+ LLVMValueRef shuffles[2];
+ index = lp_build_const_int32(gallivm, reg->Register.Index * 4 +
(swizzle_in >> 16));
+
+ scalar2_ptr = LLVMBuildGEP(builder, consts_ptr,
+, 1, "");
+
+ scalar = LLVMBuildLoad(builder, scalar_ptr, "");
+ scalar2 = LLVMBuildLoad(builder, scalar2_ptr, "");
+ shuffles[0] = lp_build_const_int32(gallivm, 0);
+ shuffles[1] = lp_build_const_int32(gallivm, 1);
+
+ res =
LLVMGetUndef(LLVMVectorType(LLVMFloatTypeInContext(gallivm->context),
bld_base->base.type.length * 2));
+ res = LLVMBuildInsertElement(builder, res, scalar, shuffles[0], "");
+ res = LLVMBuildInsertElement(builder, res, scalar2, shuffles[1], "");
+ } else {
+if (stype == TGSI_TYPE_DOUBLE) {
+ LLVMTypeRef dptr_type =
LLVMPointerType(LLVMDoubleTypeInContext(gallivm->context), 0);
+ scalar_ptr = LLVMBuildBitCast(builder, scalar_ptr, dptr_type, "");
+ bld_broad = _base->dbl_bld;
+} else if (stype == TGSI_TYPE_UNSIGNED64) {
+ LLVMTypeRef u64ptr_type =
LLVMPointerType(LLVMInt64TypeInContext(gallivm->context), 0);
+ scalar_ptr =
