Re: [Mesa-dev] [PATCH 2/3] ac/nir_to_llvm: add ac_are_tessfactors_def_in_all_invocs()

[Timothy Arceri]

On 8/1/19 6:43 am, Marek Olšák wrote:


On Mon, Dec 17, 2018 at 8:18 PM Timothy Arceri > wrote:


The following patch will use this with the radeonsi NIR backend
but I've added it to ac so we can use it with RADV in future.

This is a NIR implementation of the tgsi function
tgsi_scan_tess_ctrl().
---
  src/amd/common/ac_nir_to_llvm.c | 161 
  src/amd/common/ac_nir_to_llvm.h |   2 +
  2 files changed, 163 insertions(+)

diff --git a/src/amd/common/ac_nir_to_llvm.c
b/src/amd/common/ac_nir_to_llvm.c
index 4294956de1..055940b75f 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4063,3 +4063,164 @@ ac_lower_indirect_derefs(struct nir_shader
*nir, enum chip_class chip_class)

         nir_lower_indirect_derefs(nir, indirect_mask);
  }
+
+static unsigned
+get_inst_tessfactor_writemask(nir_intrinsic_instr *intrin)
+{
+       if (intrin->intrinsic != nir_intrinsic_store_deref)
+               return 0;
+
+       nir_variable *var =
+ 
  nir_deref_instr_get_variable(nir_src_as_deref(intrin->src[0]));

+
+       if (var->data.mode != nir_var_shader_out)
+               return 0;
+
+       unsigned writemask = 0;
+       const int location = var->data.location;
+       unsigned first_component = var->data.location_frac;
+       unsigned num_comps = intrin->dest.ssa.num_components;
+
+       if (location == VARYING_SLOT_TESS_LEVEL_INNER)
+               writemask = ((1 << num_comps + 1) - 1) <<
first_component;


Parentheses are missing in "1 << num_comps + 1".

+       else if (location == VARYING_SLOT_TESS_LEVEL_OUTER)
+               writemask = (((1 << num_comps + 1) - 1) <<
first_component) << 4;


Same here.


Good catch. I did test this code when writing it ... maybe these are 
scalars when we see them here. Anyway I'll fix this anyway and send a 
patch shortly.




Marek

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Re: [Mesa-dev] [PATCH 2/3] ac/nir_to_llvm: add ac_are_tessfactors_def_in_all_invocs()

[Marek Olšák]

On Mon, Dec 17, 2018 at 8:18 PM Timothy Arceri 
wrote:

> The following patch will use this with the radeonsi NIR backend
> but I've added it to ac so we can use it with RADV in future.
>
> This is a NIR implementation of the tgsi function
> tgsi_scan_tess_ctrl().
> ---
>  src/amd/common/ac_nir_to_llvm.c | 161 
>  src/amd/common/ac_nir_to_llvm.h |   2 +
>  2 files changed, 163 insertions(+)
>
> diff --git a/src/amd/common/ac_nir_to_llvm.c
> b/src/amd/common/ac_nir_to_llvm.c
> index 4294956de1..055940b75f 100644
> --- a/src/amd/common/ac_nir_to_llvm.c
> +++ b/src/amd/common/ac_nir_to_llvm.c
> @@ -4063,3 +4063,164 @@ ac_lower_indirect_derefs(struct nir_shader *nir,
> enum chip_class chip_class)
>
> nir_lower_indirect_derefs(nir, indirect_mask);
>  }
> +
> +static unsigned
> +get_inst_tessfactor_writemask(nir_intrinsic_instr *intrin)
> +{
> +   if (intrin->intrinsic != nir_intrinsic_store_deref)
> +   return 0;
> +
> +   nir_variable *var =
> +
>  nir_deref_instr_get_variable(nir_src_as_deref(intrin->src[0]));
> +
> +   if (var->data.mode != nir_var_shader_out)
> +   return 0;
> +
> +   unsigned writemask = 0;
> +   const int location = var->data.location;
> +   unsigned first_component = var->data.location_frac;
> +   unsigned num_comps = intrin->dest.ssa.num_components;
> +
> +   if (location == VARYING_SLOT_TESS_LEVEL_INNER)
> +   writemask = ((1 << num_comps + 1) - 1) << first_component;
>

Parentheses are missing in "1 << num_comps + 1".


> +   else if (location == VARYING_SLOT_TESS_LEVEL_OUTER)
> +   writemask = (((1 << num_comps + 1) - 1) <<
> first_component) << 4;
>

Same here.

Marek
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[Mesa-dev] [PATCH 2/3] ac/nir_to_llvm: add ac_are_tessfactors_def_in_all_invocs()

[Timothy Arceri]

The following patch will use this with the radeonsi NIR backend
but I've added it to ac so we can use it with RADV in future.

This is a NIR implementation of the tgsi function
tgsi_scan_tess_ctrl().
---
 src/amd/common/ac_nir_to_llvm.c | 161 
 src/amd/common/ac_nir_to_llvm.h |   2 +
 2 files changed, 163 insertions(+)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 4294956de1..055940b75f 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4063,3 +4063,164 @@ ac_lower_indirect_derefs(struct nir_shader *nir, enum 
chip_class chip_class)
 
nir_lower_indirect_derefs(nir, indirect_mask);
 }
+
+static unsigned
+get_inst_tessfactor_writemask(nir_intrinsic_instr *intrin)
+{
+   if (intrin->intrinsic != nir_intrinsic_store_deref)
+   return 0;
+
+   nir_variable *var =
+   nir_deref_instr_get_variable(nir_src_as_deref(intrin->src[0]));
+
+   if (var->data.mode != nir_var_shader_out)
+   return 0;
+
+   unsigned writemask = 0;
+   const int location = var->data.location;
+   unsigned first_component = var->data.location_frac;
+   unsigned num_comps = intrin->dest.ssa.num_components;
+
+   if (location == VARYING_SLOT_TESS_LEVEL_INNER)
+   writemask = ((1 << num_comps + 1) - 1) << first_component;
+   else if (location == VARYING_SLOT_TESS_LEVEL_OUTER)
+   writemask = (((1 << num_comps + 1) - 1) << first_component) << 
4;
+
+   return writemask;
+}
+
+static void
+scan_tess_ctrl(nir_cf_node *cf_node, unsigned *upper_block_tf_writemask,
+  unsigned *cond_block_tf_writemask,
+  bool *tessfactors_are_def_in_all_invocs, bool is_nested_cf)
+{
+   switch (cf_node->type) {
+   case nir_cf_node_block: {
+   nir_block *block = nir_cf_node_as_block(cf_node);
+   nir_foreach_instr(instr, block) {
+   if (instr->type != nir_instr_type_intrinsic)
+   continue;
+
+   nir_intrinsic_instr *intrin = 
nir_instr_as_intrinsic(instr);
+   if (intrin->intrinsic == nir_intrinsic_barrier) {
+
+   /* If we find a barrier in nested control flow 
put this in the
+* too hard basket. In GLSL this is not 
possible but it is in
+* SPIR-V.
+*/
+   if (is_nested_cf) {
+   *tessfactors_are_def_in_all_invocs = 
false;
+   return;
+   }
+
+   /* The following case must be prevented:
+*gl_TessLevelInner = ...;
+*barrier();
+*if (gl_InvocationID == 1)
+*   gl_TessLevelInner = ...;
+*
+* If you consider disjoint code segments 
separated by barriers, each
+* such segment that writes tess factor 
channels should write the same
+* channels in all codepaths within that 
segment.
+*/
+   if (upper_block_tf_writemask || 
cond_block_tf_writemask) {
+   /* Accumulate the result: */
+   *tessfactors_are_def_in_all_invocs &=
+   !(*cond_block_tf_writemask & 
~(*upper_block_tf_writemask));
+
+   /* Analyze the next code segment from 
scratch. */
+   *upper_block_tf_writemask = 0;
+   *cond_block_tf_writemask = 0;
+   }
+   } else
+   *upper_block_tf_writemask |= 
get_inst_tessfactor_writemask(intrin);
+   }
+
+   break;
+   }
+   case nir_cf_node_if: {
+   unsigned then_tessfactor_writemask = 0;
+   unsigned else_tessfactor_writemask = 0;
+
+   nir_if *if_stmt = nir_cf_node_as_if(cf_node);
+   foreach_list_typed(nir_cf_node, nested_node, node, 
_stmt->then_list) {
+   scan_tess_ctrl(nested_node, _tessfactor_writemask,
+  cond_block_tf_writemask,
+  tessfactors_are_def_in_all_invocs, true);
+   }
+
+   foreach_list_typed(nir_cf_node, nested_node, node, 
_stmt->else_list) {
+   scan_tess_ctrl(nested_node, _tessfactor_writemask,
+  cond_block_tf_writemask,
+