Re: [Mesa-dev] [PATCH 2/2] radv: Disallow indirect outputs for GS on GFX9 as well.

[Bas Nieuwenhuizen]

On Fri, Oct 27, 2017 at 5:03 PM, Andres Gomez  wrote:
> Bas, this patch looks like it should have been marked as fixing
> 6ce550453f1 instead of e38685cc62e (?).

Well my reasoning was that the bug got "visible" when we enabled Vega.
The patch you refer to fixed part of it, but not all of it, and then
this patch fixes the rest.

>
> In any case, I was wondering whether it would be interesting to bring
> them both to the 17.2 stable queue and whether we would also want
> Timothy's preceding patch:
>
> 087e010b2b3dd83a539f97203909d6c43b5da87c radv: copy indirect lowering 
> settings from radeonsi

Yes, that would be reasonable. Timothy's patch is an optimization
though, so I'd be happy to send a backport that only generates the
variable needed for the other two if you'd prefer that.

>
> Let me know what you think.
>
> On Sun, 2017-10-22 at 18:43 +0200, Bas Nieuwenhuizen wrote:
>> Since it also uses the output vector before writing to memory.
>>
>> Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
>> ---
>>  src/amd/vulkan/radv_shader.c | 4 +---
>>  1 file changed, 1 insertion(+), 3 deletions(-)
>>
>> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
>> index 07e68d6032b..6176a2e590d 100644
>> --- a/src/amd/vulkan/radv_shader.c
>> +++ b/src/amd/vulkan/radv_shader.c
>> @@ -265,9 +265,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
>>   indirect_mask |= nir_var_shader_in;
>>   }
>>   if (!llvm_has_working_vgpr_indexing &&
>> - (nir->info.stage == MESA_SHADER_VERTEX ||
>> -  nir->info.stage == MESA_SHADER_TESS_EVAL ||
>> -  nir->info.stage == MESA_SHADER_FRAGMENT))
>> + nir->info.stage != MESA_SHADER_TESS_CTRL)
>>   indirect_mask |= nir_var_shader_out;
>>
>>   /* TODO: We shouldn't need to do this, however LLVM isn't currently
> --
> Br,
>
> Andres
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Re: [Mesa-dev] [PATCH 2/2] radv: Disallow indirect outputs for GS on GFX9 as well.

[Andres Gomez]

Bas, this patch looks like it should have been marked as fixing
6ce550453f1 instead of e38685cc62e (?).

In any case, I was wondering whether it would be interesting to bring
them both to the 17.2 stable queue and whether we would also want
Timothy's preceding patch:

087e010b2b3dd83a539f97203909d6c43b5da87c radv: copy indirect lowering settings 
from radeonsi

Let me know what you think.

On Sun, 2017-10-22 at 18:43 +0200, Bas Nieuwenhuizen wrote:
> Since it also uses the output vector before writing to memory.
> 
> Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
> ---
>  src/amd/vulkan/radv_shader.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
> index 07e68d6032b..6176a2e590d 100644
> --- a/src/amd/vulkan/radv_shader.c
> +++ b/src/amd/vulkan/radv_shader.c
> @@ -265,9 +265,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
>   indirect_mask |= nir_var_shader_in;
>   }
>   if (!llvm_has_working_vgpr_indexing &&
> - (nir->info.stage == MESA_SHADER_VERTEX ||
> -  nir->info.stage == MESA_SHADER_TESS_EVAL ||
> -  nir->info.stage == MESA_SHADER_FRAGMENT))
> + nir->info.stage != MESA_SHADER_TESS_CTRL)
>   indirect_mask |= nir_var_shader_out;
>  
>   /* TODO: We shouldn't need to do this, however LLVM isn't currently
-- 
Br,

Andres
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Re: [Mesa-dev] [PATCH 2/2] radv: Disallow indirect outputs for GS on GFX9 as well.

[Timothy Arceri]

Reviewed-by: Timothy Arceri 

On 23/10/17 03:43, Bas Nieuwenhuizen wrote:

Since it also uses the output vector before writing to memory.

Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
---
  src/amd/vulkan/radv_shader.c | 4 +---
  1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 07e68d6032b..6176a2e590d 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -265,9 +265,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
indirect_mask |= nir_var_shader_in;
}
if (!llvm_has_working_vgpr_indexing &&
-   (nir->info.stage == MESA_SHADER_VERTEX ||
-nir->info.stage == MESA_SHADER_TESS_EVAL ||
-nir->info.stage == MESA_SHADER_FRAGMENT))
+   nir->info.stage != MESA_SHADER_TESS_CTRL)
indirect_mask |= nir_var_shader_out;
  
  	/* TODO: We shouldn't need to do this, however LLVM isn't currently



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