[neonixie-l] Re: Multiple HV5530 question
Thanks again. So with two level shifters available and two open pins on the 1284P, which two of three lines, CLK, DATA, and LE, would be best to separate? From your description, are you saying that CLK and DATA are the two best separated? On Sunday, October 18, 2015 at 12:30:45 PM UTC-4, gregebert wrote: > > Separating CLK or DATA for individual HV5530's will, as you said, > accomplish the same result. Separating LE is another option but you have to > be careful to keep-track of what has been shifted. It's not obvious from > the diagrams I posted, but I actually have 4 serial data signals on the > ribbon-cable, and I jumper a separate serial-data signal on each board > (which limits my design to 4 boards or 24 digits with a single ribbon > cable). > > It's entirely possible to construct a single serial shift-chain, but you > have to be careful about timing between cascaded HV5530's. According to the > datasheet, the data hold-time is 10nsec. The min prop-delay of the 5530 is > not specified, so you have to assume it's zero. In order to guarantee > hold-time margin, the following equation applies: Hold-margin = > MinPropDelay - ClkSkew - MinHoldTime. In this case, even if you have zero > CLK skew, you still have a 10nsec violation on the hold-time. Now, with > real silicon the MinPropDelay is finite, and I *suspect* it's more than > 10nsec, but I'm not going to risk it. In my case, I created a second clock > signal and I can guarantee hold-time margin through the sequencing of the > signals from my FPGA. > > Clock skew has a lot of subtleties. Yes, it's largely due to the > board-trace flight-times, but it's also due to finite risetime of the clk > signal itself and when each HV5530 determines the CLK is high or low. This > will vary from device to device, and the effect is worsened with slow > rise/fall times. Logic-level translators are quite slow, with delays in > 100's of nsec; I took no chances and used separate clks. I could have used > an inverter to create the second CLK phase, but that was adding another IC > and I already had a spare pin on the FPGA. > -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to neonixie-l+unsubscr...@googlegroups.com. To post to this group, send an email to neonixie-l@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/cf1fea45-a99b-461a-9f0d-c1a602b8b7b2%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[neonixie-l] Re: Multiple HV5530 question
There's no need to separate *both* CLK and DATA. If you have separate data lines and CLK everything at the same time, you've basically shortened the length of the serial data chain, and you're loading them in parallel. This will give you the fastest load-time. On the other hand, if you split the CLK line and use a shared DATA line, you could implement the 2-phase clocking scheme similar to what I do. -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to neonixie-l+unsubscr...@googlegroups.com. To post to this group, send an email to neonixie-l@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/21a17312-1963-432b-b779-e8916c97fc9f%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[neonixie-l] Re: Multiple HV5530 question
So to be clear, if you split the CLK lines into CLKA and CLKB, the serial data will go into the first HV5530. The first, third, fifth, etc HV5530's would use CLKA. The second, fourth, etc HV5530's would use CLKB. The DATA_OUT of the first HV5530 goes to the DATA_IN of the second HV5530, etc. Since the HV5530 is falling-edge triggered, you would bring CLKB low first, then CLKA low afterwards. It doesn't matter when you bring either of these clock lines high as long as you meet the minimum high and low times (62nsec). The minimum 'spacing' between falling edges is the setup time (25ns) plus the max prop delay (100ns), or 125ns. I would recommend more than this to account for clock-skew, noise, etc. -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to neonixie-l+unsubscr...@googlegroups.com. To post to this group, send an email to neonixie-l@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/329832e7-0c82-42b9-ae3b-dbaecedbd6f8%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[neonixie-l] Re: Multiple HV5530 question
Thank you. I'll do it that way. On Saturday, October 17, 2015 at 9:26:23 AM UTC-4, Mitch wrote: > > Hi All, > > The seven digit, IN-18 board is on order so I'm on to the next project, a > fifteen digit Union Square Metronome type clock similar to Jarek's clock > here: > http://hackaday.com/tag/metronome/ > > Four HV5530s will be connected in series and updated every second, driving > twelve Nixies. That should not be a problem. One HV5530 will update two, > 1/10 second, and one, 1/100 second Nixie, updated at 10ms. > > All five will have the blanking lines connected together, to a PWM pin. > That leaves Data, Clock, and Latch, and only two extra level shifters are > available on the CD4054B. > > My thought is that only the latch line on the four HV5530s needs to be > separated from the latch line on the single, fifth HV5530 because even > though the data will be presented and clocked to all five HV5530s, if it is > never latched and subsequently replaced with it's correct data, incorrect > data will never latch to the wrong display. > > With two available level shifters and pins available on the 1284P, clock > and latch could be separated, but I'm not sure if separating the clock line > too, will make a difference. > > Please give me advice on this. > > By the way, the cost estimate for the seven digit, IN-18 board from OSH > Park was just over $210 for three boards, with shipping. I decided to try > PCBWay this time because their estimate was $70 with DHL shipping for five > boards. > > Thanks. > > > > > -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to neonixie-l+unsubscr...@googlegroups.com. To post to this group, send an email to neonixie-l@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/7b16c4ff-8f2f-40dd-8925-cf56cbff27e0%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [neonixie-l] Re: Multiple HV5530 question
If you are going to use FPGA, then why not let it design itself? http://www.damninteresting.com/on-the-origin-of-circuits/ John K. [there are more learned refs] - Original Message - From: gregebert To: neonixie-l Sent: Monday, October 19, 2015 3:00 AM Subject: [neonixie-l] Re: Multiple HV5530 question Separating CLK or DATA for individual HV5530's will, as you said, accomplish the same result. Separating LE is another option but you have to be careful to keep-track of what has been shifted. It's not obvious from the diagrams I posted, but I actually have 4 serial data signals on the ribbon-cable, and I jumper a separate serial-data signal on each board (which limits my design to 4 boards or 24 digits with a single ribbon cable). It's entirely possible to construct a single serial shift-chain, but you have to be careful about timing between cascaded HV5530's. According to the datasheet, the data hold-time is 10nsec. The min prop-delay of the 5530 is not specified, so you have to assume it's zero. In order to guarantee hold-time margin, the following equation applies: Hold-margin = MinPropDelay - ClkSkew - MinHoldTime. In this case, even if you have zero CLK skew, you still have a 10nsec violation on the hold-time. Now, with real silicon the MinPropDelay is finite, and I suspect it's more than 10nsec, but I'm not going to risk it. In my case, I created a second clock signal and I can guarantee hold-time margin through the sequencing of the signals from my FPGA. Clock skew has a lot of subtleties. Yes, it's largely due to the board-trace flight-times, but it's also due to finite risetime of the clk signal itself and when each HV5530 determines the CLK is high or low. This will vary from device to device, and the effect is worsened with slow rise/fall times. Logic-level translators are quite slow, with delays in 100's of nsec; I took no chances and used separate clks. I could have used an inverter to create the second CLK phase, but that was adding another IC and I already had a spare pin on the FPGA. -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to neonixie-l+unsubscr...@googlegroups.com. To post to this group, send email to neonixie-l@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/71ab7481-17a7-41ba-ad49-3176db378f42%40googlegroups.com. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to neonixie-l+unsubscr...@googlegroups.com. To post to this group, send an email to neonixie-l@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/98700625C72047B2BA84ABBB9423FCDF%40compunet4f9da9. For more options, visit https://groups.google.com/d/optout.
[neonixie-l] Re: Multiple HV5530 question
David - Four are connected serially, updating 120 bits of 128 available. That group is updated every second. The fifth chip stands alone and only 30 of 32 bits needs to be updated every 10ms. Greg - This is a much simpler application. From what I understand, which is not too much, it appears that separating CLK or LE or DATA will accomplish the same thing, and only one needs to be separated. Is this correct? The level shifter has two available lines so no additional hardware will be necessary. On Saturday, October 17, 2015 at 7:33:47 PM UTC-4, gregebert wrote: > > Here's the approach I took. The PCB is a standalone 6-digit clock, but I > designed it so they can be abutted for as many digits as you wish. In my > case I'm using 3 boards for 14 digits. On each board, there are 2 clock > signals (CLK, CLKB) and I cascade the 2 HV5530's in series. The HV5530's > are clocked separately to ensure hold-time margin for the serial data. I > use a level-shifter from the 3.3V levels from the FPGA to the 12V levels > for the HV5530. > > There's no advantage for me to thread the serial data between boards, > because there's already a level-translator. > > To connect multiple boards, I provide a separate serial-data-in for each > board. All other signals are connected in parallel via a 10-conductor > ribbon cable. There is a termination resistor for the CLK and CLKB lines to > ground, and it will be populated on the last board at the end of the ribbon > cable. > > I should have provided a screenshot of the timing diagrams I have from the > simulations. > -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to neonixie-l+unsubscr...@googlegroups.com. To post to this group, send an email to neonixie-l@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/c3463f5c-2be7-4f2f-94ee-c188cd59785f%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[neonixie-l] Re: Multiple HV5530 question
Separating CLK or DATA for individual HV5530's will, as you said, accomplish the same result. Separating LE is another option but you have to be careful to keep-track of what has been shifted. It's not obvious from the diagrams I posted, but I actually have 4 serial data signals on the ribbon-cable, and I jumper a separate serial-data signal on each board (which limits my design to 4 boards or 24 digits with a single ribbon cable). It's entirely possible to construct a single serial shift-chain, but you have to be careful about timing between cascaded HV5530's. According to the datasheet, the data hold-time is 10nsec. The min prop-delay of the 5530 is not specified, so you have to assume it's zero. In order to guarantee hold-time margin, the following equation applies: Hold-margin = MinPropDelay - ClkSkew - MinHoldTime. In this case, even if you have zero CLK skew, you still have a 10nsec violation on the hold-time. Now, with real silicon the MinPropDelay is finite, and I *suspect* it's more than 10nsec, but I'm not going to risk it. In my case, I created a second clock signal and I can guarantee hold-time margin through the sequencing of the signals from my FPGA. Clock skew has a lot of subtleties. Yes, it's largely due to the board-trace flight-times, but it's also due to finite risetime of the clk signal itself and when each HV5530 determines the CLK is high or low. This will vary from device to device, and the effect is worsened with slow rise/fall times. Logic-level translators are quite slow, with delays in 100's of nsec; I took no chances and used separate clks. I could have used an inverter to create the second CLK phase, but that was adding another IC and I already had a spare pin on the FPGA. -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to neonixie-l+unsubscr...@googlegroups.com. To post to this group, send an email to neonixie-l@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/71ab7481-17a7-41ba-ad49-3176db378f42%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
