Re: [PATCH bpf-next 1/7] mips: bpf: implement jitting of BPF_ALU | BPF_ARSH | BPF_X

[Paul Burton]

Hi Jiong,

On Tue, Dec 04, 2018 at 03:55:16PM -0500, Jiong Wang wrote:
> Jitting of BPF_K is supported already, but not BPF_X. This patch complete
> the support for the latter on both MIPS and microMIPS.
> 
> Cc: Paul Burton 
> Cc: linux-m...@vger.kernel.org
> Signed-off-by: Jiong Wang 
> ---
>  arch/mips/include/asm/uasm.h  | 1 +
>  arch/mips/include/uapi/asm/inst.h | 1 +
>  arch/mips/mm/uasm-micromips.c | 1 +
>  arch/mips/mm/uasm-mips.c  | 1 +
>  arch/mips/mm/uasm.c   | 9 +
>  arch/mips/net/ebpf_jit.c  | 4 
>  6 files changed, 13 insertions(+), 4 deletions(-)

I don't seem to have been copied on the rest of the series, but this
patch standalone looks good from a MIPS standpoint. If the series is
going through the net tree (and again, I can't see whether that seems
likely because I don't have the rest of the series) then:

Acked-by: Paul Burton 

If you want me to take this patch through the MIPS tree instead then let
me know.

Thanks,
Paul

Re: [PATCH v2 bpf] mips: bpf: fix encoding bug for mm_srlv32_op

[Paul Burton]

Hi Jakub,

On Mon, Dec 03, 2018 at 03:55:45PM -0800, Jakub Kicinski wrote:
> On Mon, 3 Dec 2018 22:42:04 +0000, Paul Burton wrote:
> > Jiong Wang wrote:
> > > For micro-mips, srlv inside POOL32A encoding space should use 0x50
> > > sub-opcode, NOT 0x90.
> > > 
> > > Some early version ISA doc describes the encoding as 0x90 for both srlv 
> > > and
> > > srav, this looks to me was a typo. I checked Binutils libopcode
> > > implementation which is using 0x50 for srlv and 0x90 for srav.
> > > 
> > > v1->v2:
> > > - Keep mm_srlv32_op sorted by value.
> > > 
> > > Fixes: f31318fdf324 ("MIPS: uasm: Add srlv uasm instruction")
> > > Cc: Markos Chandras 
> > > Cc: Paul Burton 
> > > Cc: linux-m...@vger.kernel.org
> > > Acked-by: Jakub Kicinski 
> > > Acked-by: Song Liu 
> > > Signed-off-by: Jiong Wang   
> > 
> > Applied to mips-fixes.
> 
> Newbie process related question - are the arch JIT patches routed via
> arch trees or bpf-next?  Jiong has more (slightly conflicting) JIT
> patches to send - I wonder how they'll get applied and whether to wait
> for the mips -> Linus -> net -> bpf merge chain.

I'd expect that to be a case-by-case "what makes most sense this time?"
sort of question.

In this particular patch the code you're changing isn't specifically
BPF-related code, it's part of the MIPS uasm assembler which MIPS BPF
happens to use behind the scenes, so since it seemed like a pretty
standalone patch taking it through the MIPS tree made sense to me.

If you have related patches the best thing to do would be to submit them
together as a series. Then after the maintainers involved can see the
patches we can figure out the best way to apply them.

Thanks,
Paul

Re: [PATCH v2 bpf] mips: bpf: fix encoding bug for mm_srlv32_op

[Paul Burton]

Hello,

Jiong Wang wrote:
> For micro-mips, srlv inside POOL32A encoding space should use 0x50
> sub-opcode, NOT 0x90.
> 
> Some early version ISA doc describes the encoding as 0x90 for both srlv and
> srav, this looks to me was a typo. I checked Binutils libopcode
> implementation which is using 0x50 for srlv and 0x90 for srav.
> 
> v1->v2:
> - Keep mm_srlv32_op sorted by value.
> 
> Fixes: f31318fdf324 ("MIPS: uasm: Add srlv uasm instruction")
> Cc: Markos Chandras 
> Cc: Paul Burton 
> Cc: linux-m...@vger.kernel.org
> Acked-by: Jakub Kicinski 
> Acked-by: Song Liu 
> Signed-off-by: Jiong Wang 

Applied to mips-fixes.

Thanks,
Paul

[ This message was auto-generated; if you believe anything is incorrect
  then please email paul.bur...@mips.com to report it. ]

Re: [PATCH bpf] mips: bpf: fix encoding bug for mm_srlv32_op

[Paul Burton]

Hi Jiong,

On Sat, Dec 01, 2018 at 04:10:01AM -0500, Jiong Wang wrote:
> For micro-mips, srlv inside POOL32A encoding space should use 0x50
> sub-opcode, NOT 0x90.
> 
> Some early version ISA doc describes the encoding as 0x90 for both srlv and
> srav, this looks to me was a typo. I checked Binutils libopcode
> implementation which is using 0x50 for srlv and 0x90 for srav.

Are you aware of documentation that gets this right? Looking at the
latest microMIPS spec I have available (6.05) it looks like this is
still documented incorrectly. I'll pass this along to the architecture
team.

> Fixes: f31318fdf324 ("MIPS: uasm: Add srlv uasm instruction")
> CC: Markos Chandras 
> CC: Paul Burton 
> Acked-by: Jakub Kicinski 
> Signed-off-by: Jiong Wang 
> ---
>  arch/mips/include/uapi/asm/inst.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/mips/include/uapi/asm/inst.h 
> b/arch/mips/include/uapi/asm/inst.h
> index c05dcf5..80f35e7 100644
> --- a/arch/mips/include/uapi/asm/inst.h
> +++ b/arch/mips/include/uapi/asm/inst.h
> @@ -370,7 +370,7 @@ enum mm_32a_minor_op {
>   mm_pool32axf_op = 0x03c,
>   mm_srl32_op = 0x040,
>   mm_sra_op = 0x080,
> - mm_srlv32_op = 0x090,
> + mm_srlv32_op = 0x050,
>   mm_rotr_op = 0x0c0,
>   mm_lwxs_op = 0x118,
>   mm_addu32_op = 0x150,

Could you also move it above mm_sra_op to keep them sorted by value?

When submitting v2 please also copy the linux-mips mailing list -
linux-m...@vger.kernel.org.

Thanks,
Paul

Re: [PATCH 3/4] net: lantiq: Add Lantiq / Intel vrx200 Ethernet driver

[Paul Burton]

Hi Hauke,

On Sat, Jul 21, 2018 at 09:13:57PM +0200, Hauke Mehrtens wrote:
> diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
> index e0af39b33e28..c704312ef7d5 100644
> --- a/arch/mips/lantiq/xway/sysctrl.c
> +++ b/arch/mips/lantiq/xway/sysctrl.c
> @@ -536,7 +536,7 @@ void __init ltq_soc_init(void)
>   clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS);
>  
>   clkdev_add_pmu("1da0.usif", "NULL", 1, 0, PMU_USIF);
> - clkdev_add_pmu("1e108000.eth", NULL, 0, 0,
> + clkdev_add_pmu("1e10b308.eth", NULL, 0, 0,
>   PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
>   PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
>   PMU_PPE_QSB | PMU_PPE_TOP);

Is this intentional?

Why is it needed? Was the old address wrong? Does it change anything
functionally?

If it is needed it seems like a separate change - unless there's some
reason it's tied to adding this driver?

Should this really apply only to the lantiq,vr9 case or also to the
similar lantiq,grx390 & lantiq,ar10 paths?

Whatever the answers to these questions it would be good to include them
in the commit message.

Thanks,
Paul

Re: [PATCH 1/4] MIPS: lantiq: Do not enable IRQs in dma open

[Paul Burton]

Hi Hauke,

On Sat, Jul 21, 2018 at 09:13:55PM +0200, Hauke Mehrtens wrote:
> When a DMA channel is opened the IRQ should not get activated
> automatically, this allows it to pull data out manually without the help
> of interrupts. This is needed for a workaround in the vrx200 Ethernet
> driver.
> 
> Signed-off-by: Hauke Mehrtens 
> ---
>  arch/mips/lantiq/xway/dma.c| 1 -
>  drivers/net/ethernet/lantiq_etop.c | 1 +
>  2 files changed, 1 insertion(+), 1 deletion(-)

If you'd like this to go via the netdev tree to keep it with the rest of
the series:

Acked-by: Paul Burton 

Though I'd be happier if we didn't have DMA code seemingly used only by
an ethernet driver in arch/mips/ :)

Thanks,
Paul

Re: [PATCH v7 06/11] net: pch_gbe: Only enable MAC when PHY link is active

[Paul Burton]

Hi Florian,

On Wed, Jun 27, 2018 at 10:54:24AM -0700, Florian Fainelli wrote:
> On 06/26/2018 05:06 PM, Paul Burton wrote:
> > When using a PHY connected via RGMII, as the pch_gbe driver presumes is
> > the case, the RX clock is provided by the PHY to the MAC. Various PHYs,
> > including both the AR8031 used by the Minnowboard & the RTL8211E used by
> > the MIPS Boston development board, will stop generating the RX clock
> > when the ethernet link is down (eg. the ethernet cable is unplugged).
> > 
> > Various pieces of functionality in the EG20T MAC, ranging from basics
> > like completing a MAC reset to programming MAC addresses, rely upon the
> > RX clock being provided. When the clock is not provided these pieces of
> > functionality simply never complete, and the busy bits that indicate
> > they're in progress remain set indefinitely.
> > 
> > The pch_gbe driver currently requires that the RX clock is always
> > provided, and attempts to enforce this by disabling the hibernation
> > feature of the AR8031 PHY to keep it generating the RX clock. This patch
> > moves us away from this model by only configuring the MAC when the PHY
> > indicates that the ethernet link is up. When the link is up we should be
> > able to safely expect that the RX clock is being provided, and therefore
> > safely reset & configure the MAC.
> 
> What we ended up doing in the bcmgenet driver is loop back the RX and TX
> clocks such that we always have a clock that we can use to perform any
> MAC operation, including reset.
> 
> Is this an option here?

That sounds like a nice solution, but I don't see a way to do it in the
EG20T datasheet[1].

> You might also want to split the allocation from the actual
> initialization if this is not done already.

Some of the buffer allocation is still happening in pch_gbe_up() rather
than when the link actually comes up, but there is more that could
probably be moved.

Thanks,
Paul

[1] 
https://www.intel.com/content/www/us/en/intelligent-systems/queens-bay/platform-controller-hub-eg20t-datasheet.html

Re: [PATCH v7 09/11] net: pch_gbe: Convert to mdiobus and phylib

[Paul Burton]

Hi Andrew,

On Wed, Jun 27, 2018 at 07:51:44PM +0200, Andrew Lunn wrote:
> > @@ -5,7 +5,8 @@
> >  config PCH_GBE
> > tristate "OKI SEMICONDUCTOR IOH(ML7223/ML7831) GbE"
> > depends on PCI && (X86_32 || COMPILE_TEST)
> > -   select MII
> > +   select PHYLIB
> > +   imply AT803X_PHY if X86_32
> > select PTP_1588_CLOCK_PCH
> > select NET_PTP_CLASSIFY
> 
> That is unusual. I don't think any other MAC driver does this.
> 
> If the AT803X driver is not available, it will fall back to the
> generic PHY driver. That means RGMII delays will not get set
> correctly, no interrupts, no wol, and no workaround for the 8030.
> 
> Are any of these relevant to your board?

Well, my board uses an RTL8211E PHY, doesn't support suspending so WoL
isn't applicable & with this series isn't yet using PHY interrupts
(though that would be ideal as a later addition). So for my board I
enable CONFIG_REALTEK_PHY & I don't have CONFIG_AT8031X_PHY enabled.

It seems the Minnowboard uses the AT8031 PHY, but it's not the only X86
board that includes the EG20T & not all of those use the AT8031. For
example I have access to an Aaeon NanoCOM-TC module[1] which uses the
EG20T & pch_gbe, but its datasheet lists an RTL8211CL PHY (which is
presumably misconfigured by current kernels, though at least for basic
network access is functional).

The idea behind using imply was that it allows kernel configurations
that have up to now only supported the AT8031 PHY via pch_gbe's custom
code to automatically continue to support that PHY, but also allows
support for it to be disabled for systems that do not use that PHY (for
example mine or the Aaeon system).

Would you prefer that the MAC driver instead selects the PHY drivers for
all PHYs known to have been used with the MAC? Or would you be happy if
I added the equivalent in patch 11:

  imply REALTEK_PHY if MIPS

Though perhaps REALTEK_PHY would be good to enable for X86_32 too to
cover that Aaeon system...

Thanks,
Paul

[1] http://www.aaeon.com/en/p/com-express-modules-nanocom-tc

Re: [PATCH v7 06/11] net: pch_gbe: Only enable MAC when PHY link is active

[Paul Burton]

Hi Andrew,

On Wed, Jun 27, 2018 at 07:30:14PM +0200, Andrew Lunn wrote:
> On Tue, Jun 26, 2018 at 05:06:07PM -0700, Paul Burton wrote:
> > When using a PHY connected via RGMII, as the pch_gbe driver presumes is
> > the case, the RX clock is provided by the PHY to the MAC. Various PHYs,
> > including both the AR8031 used by the Minnowboard & the RTL8211E used by
> > the MIPS Boston development board, will stop generating the RX clock
> > when the ethernet link is down (eg. the ethernet cable is unplugged).
> > 
> > Various pieces of functionality in the EG20T MAC, ranging from basics
> > like completing a MAC reset to programming MAC addresses, rely upon the
> > RX clock being provided. When the clock is not provided these pieces of
> > functionality simply never complete, and the busy bits that indicate
> > they're in progress remain set indefinitely.
> > 
> > The pch_gbe driver currently requires that the RX clock is always
> > provided, and attempts to enforce this by disabling the hibernation
> > feature of the AR8031 PHY to keep it generating the RX clock. This patch
> > moves us away from this model by only configuring the MAC when the PHY
> > indicates that the ethernet link is up. When the link is up we should be
> > able to safely expect that the RX clock is being provided, and therefore
> > safely reset & configure the MAC.
> 
> Hi Paul
> 
> I like the concept, but the implementation is not clear. Maybe it just
> needs more details in the commit message. What has the watchdog got to
> do with link up?

pch_gbe_watchdog() polls for the link coming up or going down, so that's
where we find out that the link is up.

> And what happens on link down? Does the MAC need shutting down? I
> don't see such code here.

Well, depending upon the PHY the RX clock might stop which will prevent
parts of the MAC from functioning properly. Exactly which parts I don't
really know - the EG20T documentation is vague & unclear. I do know
that:

  - We won't receive packets any more, of course. This should be fine
without any extra handling because we just won't see any futher DMA
complete interrupts (or the associated bit set when polling).

  - A MAC reset won't complete - ie. the pch_gbe_wait_clr_bit() in
pch_gbe_reset()/pch_gbe_reset_hw() will time out. This I think
should be OK because after this patch we won't generally reset the
MAC when the link is down anyway, except perhaps the PCI error_state
case in pch_gbe_down(). I'm not sure what the reset there is for...

  - Masking or unmasking MAC address registers won't complete - ie. the
pch_gbe_wait_clr_bit() in pch_gbe_mac_mar_set() or
pch_gbe_set_multi() will time out. This is again when the link is
already known to be up, although there is a case in
__pch_gbe_suspend() which is setting up WoL that I'm not so sure
about...

Thanks,
Paul

Re: [PATCH v7 03/11] net: pch_gbe: Probe PHY ID & initialize only once

[Paul Burton]

Hi Andrew,

On Wed, Jun 27, 2018 at 07:21:31PM +0200, Andrew Lunn wrote:
> > [1] Please, someone patent PHY hotplugging & rigorously enforce said
> > patent such that nobody can do it. At least not with an EG20T MAC.
> 
> Hi Paul
> 
> It is already possible, and probably patented. SFP cages are usually
> used for fibre optical modules. But it is also possible to have copper
> modules, which contain a standard PHY. And SFP modules are
> hot-plugable...

D'oh, but at least not relevant to the EG20T/pch_gbe :)

> > @@ -2577,6 +2579,8 @@ static int pch_gbe_probe(struct pci_dev *pdev,
> > if (ret)
> > goto err_free_netdev;
> >  
> > +   pch_gbe_check_options(adapter);
> > +
> > /* Initialize PHY */
> > ret = pch_gbe_init_phy(adapter);
> > if (ret) {
> > @@ -2606,8 +2610,6 @@ static int pch_gbe_probe(struct pci_dev *pdev,
> >  
> > INIT_WORK(>reset_task, pch_gbe_reset_task);
> >  
> > -   pch_gbe_check_options(adapter);
> > -
> > /* initialize the wol settings based on the eeprom settings */
> > adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
> > dev_info(>dev, "MAC address : %pM\n", netdev->dev_addr);
> 
> But these two changes seem unrelated. Should they be in a different
> patch?

This is actually needed because pch_gbe_check_options() sets up, amongst
other things, the autoneg_advertised field in struct pch_gbe_phy_info
and that needs to happen before pch_gbe_phy_init_setting() is called.

Thanks,
Paul

[PATCH v7 01/11] net: pch_gbe: Remove unused struct pch_gbe_adapter fields

[Paul Burton]

Remove a bunch of unused fields from struct pch_gbe_adapter. Among these
polling_netdev, config_space & led_status are entirely unused.
ethtool_lock is initialized but we never attempt to acquire the lock, so
that is effectively unused too. A msg_enable field was documented but
missing, so drop that from the kerneldoc comment.

Signed-off-by: Paul Burton 
Cc: Andrew Lunn 
Cc: David S. Miller 
Cc: netdev@vger.kernel.org
---

Changes in v7: New patch

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h  | 9 -
 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 1 -
 2 files changed, 10 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index 44c2f291e766..be218ac81f21 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -555,11 +555,9 @@ struct pch_gbe_privdata {
 /**
  * struct pch_gbe_adapter - board specific private data structure
  * @stats_lock:Spinlock structure for status
- * @ethtool_lock:  Spinlock structure for ethtool
  * @irq_sem:   Semaphore for interrupt
  * @netdev:Pointer of network device structure
  * @pdev:  Pointer of pci device structure
- * @polling_netdev:Pointer of polling network device structure
  * @napi:  NAPI structure
  * @hw:Pointer of hardware structure
  * @stats: Hardware status
@@ -567,9 +565,6 @@ struct pch_gbe_privdata {
  * @mii:   MII information structure
  * @watchdog_timer:Watchdog timer list
  * @wake_up_evt:   Wake up event
- * @config_space:  Configuration space
- * @msg_enable:Driver message level
- * @led_status:LED status
  * @tx_ring:   Pointer of Tx descriptor ring structure
  * @rx_ring:   Pointer of Rx descriptor ring structure
  * @rx_buffer_len: Receive buffer length
@@ -579,12 +574,10 @@ struct pch_gbe_privdata {
 
 struct pch_gbe_adapter {
spinlock_t stats_lock;
-   spinlock_t ethtool_lock;
atomic_t irq_sem;
struct net_device *netdev;
struct pci_dev *pdev;
int irq;
-   struct net_device *polling_netdev;
struct napi_struct napi;
struct pch_gbe_hw hw;
struct pch_gbe_hw_stats stats;
@@ -592,8 +585,6 @@ struct pch_gbe_adapter {
struct mii_if_info mii;
struct timer_list watchdog_timer;
u32 wake_up_evt;
-   u32 *config_space;
-   unsigned long led_status;
struct pch_gbe_tx_ring *tx_ring;
struct pch_gbe_rx_ring *rx_ring;
unsigned long rx_buffer_len;
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 43c0c10dfeb7..8908ef654d94 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -1998,7 +1998,6 @@ static int pch_gbe_sw_init(struct pch_gbe_adapter 
*adapter)
}
spin_lock_init(>hw.miim_lock);
spin_lock_init(>stats_lock);
-   spin_lock_init(>ethtool_lock);
atomic_set(>irq_sem, 0);
pch_gbe_irq_disable(adapter);
 
-- 
2.18.0

[PATCH v7 11/11] net: pch_gbe: Allow build on MIPS platforms

[Paul Burton]

Allow the pch_gbe driver to be built on MIPS platforms, allowing its use
on the MIPS Boston development board.

Signed-off-by: Paul Burton 
Cc: Andrew Lunn 
Cc: David S. Miller 
Cc: netdev@vger.kernel.org

---

Changes in v7: None

 drivers/net/ethernet/oki-semi/pch_gbe/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig 
b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
index 5276f4ff3b63..8e3630b9a9d1 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
@@ -4,7 +4,7 @@
 
 config PCH_GBE
tristate "OKI SEMICONDUCTOR IOH(ML7223/ML7831) GbE"
-   depends on PCI && (X86_32 || COMPILE_TEST)
+   depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
select PHYLIB
imply AT803X_PHY if X86_32
select PTP_1588_CLOCK_PCH
-- 
2.18.0

[PATCH v7 04/11] net: pch_gbe: Remove irq_sem

[Paul Burton]

The pch_gbe driver uses an irq_sem variable to implement a sempahore
that seems to inconsistently count the number of times we enable or
disable interrupts, and only write to the interrupt enable register when
this count hits 0. This makes absolutely no sense to me, both from the
perspective of how the implementation is modifying the variable & more
fundamentally the fact that we know when we want or do not want
interrupts enabled without any need for the semaphore.

This patch removes irq_sem, so pch_gbe_irq_enable() &
pch_gbe_irq_disable() will both always write to the INT_EN register.

Signed-off-by: Paul Burton 
Cc: Andrew Lunn 
Cc: David S. Miller 
Cc: netdev@vger.kernel.org
---

Changes in v7: New patch

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h  | 2 --
 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 7 +--
 2 files changed, 1 insertion(+), 8 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index be218ac81f21..1bb0ea4f5503 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -555,7 +555,6 @@ struct pch_gbe_privdata {
 /**
  * struct pch_gbe_adapter - board specific private data structure
  * @stats_lock:Spinlock structure for status
- * @irq_sem:   Semaphore for interrupt
  * @netdev:Pointer of network device structure
  * @pdev:  Pointer of pci device structure
  * @napi:  NAPI structure
@@ -574,7 +573,6 @@ struct pch_gbe_privdata {
 
 struct pch_gbe_adapter {
spinlock_t stats_lock;
-   atomic_t irq_sem;
struct net_device *netdev;
struct pci_dev *pdev;
int irq;
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 5157cea16773..ee38bba8b9ce 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -761,7 +761,6 @@ static void pch_gbe_irq_disable(struct pch_gbe_adapter 
*adapter)
 {
struct pch_gbe_hw *hw = >hw;
 
-   atomic_inc(>irq_sem);
iowrite32(0, >reg->INT_EN);
ioread32(>reg->INT_ST);
synchronize_irq(adapter->irq);
@@ -778,8 +777,7 @@ static void pch_gbe_irq_enable(struct pch_gbe_adapter 
*adapter)
 {
struct pch_gbe_hw *hw = >hw;
 
-   if (likely(atomic_dec_and_test(>irq_sem)))
-   iowrite32(PCH_GBE_INT_ENABLE_MASK, >reg->INT_EN);
+   iowrite32(PCH_GBE_INT_ENABLE_MASK, >reg->INT_EN);
ioread32(>reg->INT_ST);
netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
   ioread32(>reg->INT_EN));
@@ -1345,7 +1343,6 @@ static irqreturn_t pch_gbe_intr(int irq, void *data)
(adapter->rx_stop_flag)) {
if (likely(napi_schedule_prep(>napi))) {
/* Enable only Rx Descriptor empty */
-   atomic_inc(>irq_sem);
int_en = ioread32(>reg->INT_EN);
int_en &=
~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
@@ -1954,7 +1951,6 @@ void pch_gbe_down(struct pch_gbe_adapter *adapter)
/* signal that we're down so the interrupt handler does not
 * reschedule our watchdog timer */
napi_disable(>napi);
-   atomic_set(>irq_sem, 0);
 
pch_gbe_irq_disable(adapter);
pch_gbe_free_irq(adapter);
@@ -2000,7 +1996,6 @@ static int pch_gbe_sw_init(struct pch_gbe_adapter 
*adapter)
}
spin_lock_init(>hw.miim_lock);
spin_lock_init(>stats_lock);
-   atomic_set(>irq_sem, 0);
pch_gbe_irq_disable(adapter);
 
pch_gbe_init_stats(adapter);
-- 
2.18.0

[PATCH v7 09/11] net: pch_gbe: Convert to mdiobus and phylib

[Paul Burton]

From: Andrew Lunn 

Convert this driver to use the mdio bus and phylib infrastructure. It
will then use the common AT803X PHY driver, rather than use its own
code. Have the shared code also handle the GPIO used to reset the PHY.

Over all, these changes should make it easier to use other PHYs with the
MAC chip, and reduces the lines of code.

[paul.bur...@mips.com:
  - Select CONFIG_PHYLIB.
  - Drop selection of CONFIG_MII.
  - Imply AT803X_PHY for X86_32, rather than selecting it for all.
  - Add GPIOF_ACTIVE_LOW to the minnow PHY reset GPIO flags.
  - Rebase atop changes in the rest of the series.
  - Drop the AR8031 PHY hibernation disable fixup.]

Signed-off-by: Andrew Lunn 
Signed-off-by: Paul Burton 
Cc: Andrew Lunn 
Cc: David S. Miller 
Cc: netdev@vger.kernel.org

---

Changes in v7:
- Heavy rebasing atop earlier patches.

Changes in v6:
- New patch

 drivers/net/ethernet/oki-semi/pch_gbe/Kconfig |   3 +-
 .../net/ethernet/oki-semi/pch_gbe/Makefile|   2 +-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe.h   |   7 +-
 .../oki-semi/pch_gbe/pch_gbe_ethtool.c|  88 +
 .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c  | 239 ++---
 .../ethernet/oki-semi/pch_gbe/pch_gbe_param.c | 265 --
 .../ethernet/oki-semi/pch_gbe/pch_gbe_phy.c   | 335 --
 .../ethernet/oki-semi/pch_gbe/pch_gbe_phy.h   |  34 --
 8 files changed, 126 insertions(+), 847 deletions(-)
 delete mode 100644 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c
 delete mode 100644 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig 
b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
index 5f7a35212796..5276f4ff3b63 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
@@ -5,7 +5,8 @@
 config PCH_GBE
tristate "OKI SEMICONDUCTOR IOH(ML7223/ML7831) GbE"
depends on PCI && (X86_32 || COMPILE_TEST)
-   select MII
+   select PHYLIB
+   imply AT803X_PHY if X86_32
select PTP_1588_CLOCK_PCH
select NET_PTP_CLASSIFY
---help---
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/Makefile 
b/drivers/net/ethernet/oki-semi/pch_gbe/Makefile
index 862de0f3bc41..133c89bc2933 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/Makefile
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/Makefile
@@ -1,4 +1,4 @@
 obj-$(CONFIG_PCH_GBE) += pch_gbe.o
 
-pch_gbe-y := pch_gbe_phy.o pch_gbe_ethtool.o pch_gbe_param.o
+pch_gbe-y := pch_gbe_ethtool.o pch_gbe_param.o
 pch_gbe-y += pch_gbe_main.o
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index f8acd8031951..e6a0bd053ae5 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -22,7 +22,8 @@
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
-#include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -578,8 +579,8 @@ struct pch_gbe_adapter {
struct pch_gbe_hw hw;
struct pch_gbe_hw_stats stats;
struct work_struct reset_task;
-   struct mii_if_info mii;
-   struct timer_list watchdog_timer;
+   struct mii_bus *mdiobus;
+   struct phy_device *phydev;
u32 wake_up_evt;
struct pch_gbe_tx_ring *tx_ring;
struct pch_gbe_rx_ring *rx_ring;
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c
index adaa0024adfe..5dc08eccb7e6 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c
@@ -17,7 +17,6 @@
  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  */
 #include "pch_gbe.h"
-#include "pch_gbe_phy.h"
 
 /**
  * pch_gbe_stats - Stats item information
@@ -71,41 +70,8 @@ static const struct pch_gbe_stats pch_gbe_gstrings_stats[] = 
{
 #define PCH_GBE_STATS_LEN (PCH_GBE_GLOBAL_STATS_LEN + PCH_GBE_QUEUE_STATS_LEN)
 
 #define PCH_GBE_MAC_REGS_LEN(sizeof(struct pch_gbe_regs) / 4)
+#define PCH_GBE_PHY_REGS_LEN   32
 #define PCH_GBE_REGS_LEN(PCH_GBE_MAC_REGS_LEN + PCH_GBE_PHY_REGS_LEN)
-/**
- * pch_gbe_get_link_ksettings - Get device-specific settings
- * @netdev: Network interface device structure
- * @ecmd:   Ethtool command
- * Returns:
- * 0:  Successful.
- * Negative value: Failed.
- */
-static int pch_gbe_get_link_ksettings(struct net_device *netdev,
- struct ethtool_link_ksettings *ecmd)
-{
-   struct pch_gbe_adapter *adapter = netdev_priv(netdev);
-   u32 supported, advertising;
-
-   mii_ethtool_get_link_ksettings(>mii, ecmd);
-
-   ethtool_convert_link_mode_to_legacy_u32(,
-   ecmd->link_modes.supported);
-   ethtool_convert_link_mode_to_legacy_u32(,
-   

[PATCH v7 07/11] net: pch_gbe: Remove AR8031 PHY hibernation disable

[Paul Burton]

We should now be able to cope with the PHY entering hibernation, ie.
ceasing to provide the RX clock, whilst the ethernet link is down.

Remove the code responsible for disabling the AR8031 PHY's hibernation
feature, allowing the PHY to enter its low power hibernation state.

Signed-off-by: Paul Burton 
Cc: Andrew Lunn 
Cc: David S. Miller 
Cc: netdev@vger.kernel.org
---

Changes in v7: New patch

 .../net/ethernet/oki-semi/pch_gbe/pch_gbe.h   |  2 -
 .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c  |  5 ---
 .../ethernet/oki-semi/pch_gbe/pch_gbe_phy.c   | 42 ---
 .../ethernet/oki-semi/pch_gbe/pch_gbe_phy.h   |  1 -
 4 files changed, 50 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index 1bb0ea4f5503..f8acd8031951 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -542,13 +542,11 @@ struct pch_gbe_hw_stats {
 /**
  * struct pch_gbe_privdata - PCI Device ID driver data
  * @phy_tx_clk_delay:  Bool, configure the PHY TX delay in software
- * @phy_disable_hibernate: Bool, disable PHY hibernation
  * @platform_init: Platform initialization callback, called from
  * probe, prior to PHY initialization.
  */
 struct pch_gbe_privdata {
bool phy_tx_clk_delay;
-   bool phy_disable_hibernate;
int (*platform_init)(struct pci_dev *pdev);
 };
 
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 721ce29b6467..c9b064ac06a1 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -2622,10 +2622,6 @@ static int pch_gbe_probe(struct pci_dev *pdev,
 
dev_dbg(>dev, "PCH Network Connection\n");
 
-   /* Disable hibernation on certain platforms */
-   if (adapter->pdata && adapter->pdata->phy_disable_hibernate)
-   pch_gbe_phy_disable_hibernate(>hw);
-
device_set_wakeup_enable(>dev, 1);
return 0;
 
@@ -2663,7 +2659,6 @@ static int pch_gbe_minnow_platform_init(struct pci_dev 
*pdev)
 
 static struct pch_gbe_privdata pch_gbe_minnow_privdata = {
.phy_tx_clk_delay = true,
-   .phy_disable_hibernate = true,
.platform_init = pch_gbe_minnow_platform_init,
 };
 
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c
index 6b35b573beef..561e71880c29 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c
@@ -78,9 +78,7 @@
 #define PHY_AR8031_DBG_OFF  0x1D
 #define PHY_AR8031_DBG_DAT  0x1E
 #define PHY_AR8031_SERDES   0x05
-#define PHY_AR8031_HIBERNATE0x0B
 #define PHY_AR8031_SERDES_TX_CLK_DLY   0x0100 /* TX clock delay of 2.0ns */
-#define PHY_AR8031_PS_HIB_EN   0x8000 /* Hibernate enable */
 
 /* Phy Id Register (word 2) */
 #define PHY_REVISION_MASK0x000F
@@ -335,43 +333,3 @@ void pch_gbe_phy_init_setting(struct pch_gbe_hw *hw)
if (adapter->pdata && adapter->pdata->phy_tx_clk_delay)
pch_gbe_phy_tx_clk_delay(hw);
 }
-
-/**
- * pch_gbe_phy_disable_hibernate - Disable the PHY low power state
- * @hw:Pointer to the HW structure
- * Returns
- * 0:  Successful.
- * -EINVAL:Invalid argument.
- */
-int pch_gbe_phy_disable_hibernate(struct pch_gbe_hw *hw)
-{
-   struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
-   u16 mii_reg;
-   int ret = 0;
-
-   switch (hw->phy.id) {
-   case PHY_AR803X_ID:
-   netdev_dbg(adapter->netdev,
-  "Disabling hibernation for AR803X PHY\n");
-   ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_OFF,
-PHY_AR8031_HIBERNATE);
-   if (ret)
-   break;
-
-   pch_gbe_phy_read_reg_miic(hw, PHY_AR8031_DBG_DAT, _reg);
-   mii_reg &= ~PHY_AR8031_PS_HIB_EN;
-   ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_DAT,
-mii_reg);
-   break;
-   default:
-   netdev_err(adapter->netdev,
-  "Unknown PHY (%x), could not disable hibernation\n",
-  hw->phy.id);
-   return -EINVAL;
-   }
-
-   if (ret)
-   netdev_err(adapter->netdev,
-  "Could not disable PHY hibernation\n");
-   return ret;
-}
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h
index 23ac38711619..a80644b4fce8 100644
--- a/drivers/net/ethernet/oki-semi/

[PATCH v7 10/11] ptp: pch: Allow build on MIPS platforms

[Paul Burton]

Allow the ptp_pch driver to be built on MIPS platforms in preparation
for use on the MIPS Boston board.

Signed-off-by: Paul Burton 
Acked-by: Richard Cochran 
Cc: Andrew Lunn 
Cc: David S. Miller 
Cc: netdev@vger.kernel.org
---

Changes in v7: None

 drivers/ptp/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index d137c480db46..fd5f2c6c18ba 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -90,7 +90,7 @@ config DP83640_PHY
 
 config PTP_1588_CLOCK_PCH
tristate "Intel PCH EG20T as PTP clock"
-   depends on X86_32 || COMPILE_TEST
+   depends on X86_32 || MIPS || COMPILE_TEST
depends on HAS_IOMEM && NET
imply PTP_1588_CLOCK
help
-- 
2.18.0

[PATCH v7 03/11] net: pch_gbe: Probe PHY ID & initialize only once

[Paul Burton]

The pch_gbe driver currently probes for the PHY ID & configures the PHY
every time the MAC is reset, even though we know that the PHY won't have
changed since the last MAC reset [1].

This patch moves the PHY probe to instead happen only once when the
driver is probed, saving time & moving us closer to the behavior we'll
have with phylib.

[1] Please, someone patent PHY hotplugging & rigorously enforce said
patent such that nobody can do it. At least not with an EG20T MAC.

Signed-off-by: Paul Burton 
Cc: Andrew Lunn 
Cc: David S. Miller 
Cc: netdev@vger.kernel.org
---

Changes in v7: New patch

 .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c  | 26 ++-
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 9651fa02d4bb..5157cea16773 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -617,8 +617,10 @@ static void pch_gbe_init_stats(struct pch_gbe_adapter 
*adapter)
 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
 {
struct net_device *netdev = adapter->netdev;
+   struct pch_gbe_hw *hw = >hw;
u32 addr;
u16 bmcr, stat;
+   s32 ret_val;
 
/* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
@@ -652,6 +654,16 @@ static int pch_gbe_init_phy(struct pch_gbe_adapter 
*adapter)
adapter->mii.mdio_read = pch_gbe_mdio_read;
adapter->mii.mdio_write = pch_gbe_mdio_write;
adapter->mii.supports_gmii = mii_check_gmii_support(>mii);
+
+   ret_val = pch_gbe_phy_get_id(hw);
+   if (ret_val) {
+   netdev_err(adapter->netdev, "pch_gbe_phy_get_id error\n");
+   return -EIO;
+   }
+   pch_gbe_phy_init_setting(hw);
+   /* Setup Mac interface option RGMII */
+   pch_gbe_phy_set_rgmii(hw);
+
return 0;
 }
 
@@ -721,22 +733,12 @@ void pch_gbe_reset(struct pch_gbe_adapter *adapter)
 {
struct net_device *netdev = adapter->netdev;
struct pch_gbe_hw *hw = >hw;
-   s32 ret_val;
 
pch_gbe_mac_reset_hw(hw);
/* reprogram multicast address register after reset */
pch_gbe_set_multi(netdev);
/* Setup the receive address. */
pch_gbe_mac_init_rx_addrs(hw, PCH_GBE_MAR_ENTRIES);
-
-   ret_val = pch_gbe_phy_get_id(hw);
-   if (ret_val) {
-   netdev_err(adapter->netdev, "pch_gbe_phy_get_id error\n");
-   return;
-   }
-   pch_gbe_phy_init_setting(hw);
-   /* Setup Mac interface option RGMII */
-   pch_gbe_phy_set_rgmii(hw);
 }
 
 /**
@@ -2577,6 +2579,8 @@ static int pch_gbe_probe(struct pci_dev *pdev,
if (ret)
goto err_free_netdev;
 
+   pch_gbe_check_options(adapter);
+
/* Initialize PHY */
ret = pch_gbe_init_phy(adapter);
if (ret) {
@@ -2606,8 +2610,6 @@ static int pch_gbe_probe(struct pci_dev *pdev,
 
INIT_WORK(>reset_task, pch_gbe_reset_task);
 
-   pch_gbe_check_options(adapter);
-
/* initialize the wol settings based on the eeprom settings */
adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
dev_info(>dev, "MAC address : %pM\n", netdev->dev_addr);
-- 
2.18.0

[PATCH v7 08/11] net: pch_gbe: Clean up resets

[Paul Burton]

Currently pch_gbe_reset() performs a number of tasks:

  1) Calls pch_gbe_reset_hw(), which:

 1a) Reads the MAC address from the hardware, even though we already
 did that in pch_gbe_open() & it should not have changed.

 1b) Writes to the RESET register to reset the MAC.

 1c) Writes the MODE register to configure GMII/RGMII mode,
 potentially before the MAC reset has finished.

 1d) Polls for the completion of the MAC reset.

 1e) Configures the device MAC address.

  2) Calls pch_gbe_set_multi() to configure multicast addresses &
 hardware MAC filtering.

  3) Calls pch_gbe_mac_init_rx_addrs(), which:

 3a) Configures the device MAC address again, duplicating step 1e.

 3b) Masks & clears all other MAC registers, wiping out the
 configuration performed by step 2.

This is needlessly repetitive & split across 3 functions for no good
reason. This patch cleans this up significantly by:

  a) Inlining pch_gbe_mac_reset_hw() into pch_gbe_reset(), moving the
 MODE register write to after the MAC reset has completed & removing
 the initial read of the MAC address.

  b) Removing pch_gbe_mac_init_rx_addrs() entirely, leaving the
 address configuration performed by pch_gbe_set_multi() intact.

With this done we know that pch_gbe_reset() will leave us with the
multicast MAC addresses & filtering configured correctly, so we can
remove the call to pch_gbe_set_multi() in pch_gbe_watchdog().

Signed-off-by: Paul Burton 
Cc: Andrew Lunn 
Cc: David S. Miller 
Cc: netdev@vger.kernel.org
---

Changes in v7: New patch

 .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c  | 54 ---
 1 file changed, 11 insertions(+), 43 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index c9b064ac06a1..123c7818698d 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -357,22 +357,6 @@ static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 
* addr, u32 index)
pch_gbe_wait_clr_bit(>reg->ADDR_MASK, PCH_GBE_BUSY);
 }
 
-/**
- * pch_gbe_mac_reset_hw - Reset hardware
- * @hw:Pointer to the HW structure
- */
-static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
-{
-   /* Read the MAC address. and store to the private data */
-   pch_gbe_mac_read_mac_addr(hw);
-   iowrite32(PCH_GBE_ALL_RST, >reg->RESET);
-   iowrite32(PCH_GBE_MODE_GMII_ETHER, >reg->MODE);
-   pch_gbe_wait_clr_bit(>reg->RESET, PCH_GBE_ALL_RST);
-   /* Setup the receive addresses */
-   pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
-   return;
-}
-
 static void pch_gbe_disable_mac_rx(struct pch_gbe_hw *hw)
 {
u32 rctl;
@@ -389,28 +373,6 @@ static void pch_gbe_enable_mac_rx(struct pch_gbe_hw *hw)
iowrite32((rctl | PCH_GBE_MRE_MAC_RX_EN), >reg->MAC_RX_EN);
 }
 
-/**
- * pch_gbe_mac_init_rx_addrs - Initialize receive address's
- * @hw:Pointer to the HW structure
- * @mar_count: Receive address registers
- */
-static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
-{
-   u32 i;
-
-   /* Setup the receive address */
-   pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
-
-   /* Zero out the other receive addresses */
-   for (i = 1; i < mar_count; i++) {
-   iowrite32(0, >reg->mac_adr[i].high);
-   iowrite32(0, >reg->mac_adr[i].low);
-   }
-   iowrite32(0xFFFE, >reg->ADDR_MASK);
-   /* wait busy */
-   pch_gbe_wait_clr_bit(>reg->ADDR_MASK, PCH_GBE_BUSY);
-}
-
 /**
  * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
  * @hw:Pointer to the HW structure
@@ -734,11 +696,18 @@ void pch_gbe_reset(struct pch_gbe_adapter *adapter)
struct net_device *netdev = adapter->netdev;
struct pch_gbe_hw *hw = >hw;
 
-   pch_gbe_mac_reset_hw(hw);
-   /* reprogram multicast address register after reset */
+   /* Perform the reset & wait for it to complete */
+   iowrite32(PCH_GBE_ALL_RST, >reg->RESET);
+   pch_gbe_wait_clr_bit(>reg->RESET, PCH_GBE_ALL_RST);
+
+   /* Configure GMII/RGMII mode */
+   iowrite32(PCH_GBE_MODE_GMII_ETHER, >reg->MODE);
+
+   /* Program the MAC address */
+   pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
+
+   /* Configure multicast addresses & filtering */
pch_gbe_set_multi(netdev);
-   /* Setup the receive address. */
-   pch_gbe_mac_init_rx_addrs(hw, PCH_GBE_MAR_ENTRIES);
 }
 
 /**
@@ -1944,7 +1913,6 @@ static void pch_gbe_watchdog(struct timer_list *t)
pch_gbe_set_mode(adapter, hw->mac.link_speed,
 hw->mac.link_duplex);
 
-   pch_gbe_set_multi(netdev);
pch_gbe_setup_tctl(adapter);
pch_gbe_configure_tx(adapter);
pch_gbe_setup_rctl(adapter);
-- 
2.18.0

[PATCH v7 06/11] net: pch_gbe: Only enable MAC when PHY link is active

[Paul Burton]

When using a PHY connected via RGMII, as the pch_gbe driver presumes is
the case, the RX clock is provided by the PHY to the MAC. Various PHYs,
including both the AR8031 used by the Minnowboard & the RTL8211E used by
the MIPS Boston development board, will stop generating the RX clock
when the ethernet link is down (eg. the ethernet cable is unplugged).

Various pieces of functionality in the EG20T MAC, ranging from basics
like completing a MAC reset to programming MAC addresses, rely upon the
RX clock being provided. When the clock is not provided these pieces of
functionality simply never complete, and the busy bits that indicate
they're in progress remain set indefinitely.

The pch_gbe driver currently requires that the RX clock is always
provided, and attempts to enforce this by disabling the hibernation
feature of the AR8031 PHY to keep it generating the RX clock. This patch
moves us away from this model by only configuring the MAC when the PHY
indicates that the ethernet link is up. When the link is up we should be
able to safely expect that the RX clock is being provided, and therefore
safely reset & configure the MAC.

Signed-off-by: Paul Burton 
Cc: Andrew Lunn 
Cc: David S. Miller 
Cc: netdev@vger.kernel.org
---

Changes in v7: New patch

 .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c  | 44 +--
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index eb290c1edce0..721ce29b6467 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -1837,7 +1837,6 @@ static int pch_gbe_request_irq(struct pch_gbe_adapter 
*adapter)
 int pch_gbe_up(struct pch_gbe_adapter *adapter)
 {
struct net_device *netdev = adapter->netdev;
-   struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
int err = -EINVAL;
 
@@ -1847,14 +1846,6 @@ int pch_gbe_up(struct pch_gbe_adapter *adapter)
goto out;
}
 
-   /* hardware has been reset, we need to reload some things */
-   pch_gbe_set_multi(netdev);
-
-   pch_gbe_setup_tctl(adapter);
-   pch_gbe_configure_tx(adapter);
-   pch_gbe_setup_rctl(adapter);
-   pch_gbe_configure_rx(adapter);
-
err = pch_gbe_request_irq(adapter);
if (err) {
netdev_err(netdev,
@@ -1867,18 +1858,9 @@ int pch_gbe_up(struct pch_gbe_adapter *adapter)
   "Error: can't bring device up - alloc rx buffers 
pool failed\n");
goto freeirq;
}
-   pch_gbe_alloc_tx_buffers(adapter, tx_ring);
-   pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
adapter->tx_queue_len = netdev->tx_queue_len;
-   pch_gbe_enable_dma_rx(>hw);
-   pch_gbe_enable_mac_rx(>hw);
 
mod_timer(>watchdog_timer, jiffies);
-
-   napi_enable(>napi);
-   pch_gbe_irq_enable(adapter);
-   netif_start_queue(adapter->netdev);
-
return 0;
 
 freeirq:
@@ -1930,6 +1912,8 @@ static void pch_gbe_watchdog(struct timer_list *t)
 {
struct pch_gbe_adapter *adapter = from_timer(adapter, t,
 watchdog_timer);
+   struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
+   struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
struct net_device *netdev = adapter->netdev;
struct pch_gbe_hw *hw = >hw;
 
@@ -1950,12 +1934,32 @@ static void pch_gbe_watchdog(struct timer_list *t)
}
hw->mac.link_speed = ethtool_cmd_speed();
hw->mac.link_duplex = cmd.duplex;
+
+   pch_gbe_reset(adapter);
+
/* Set the RGMII control. */
pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
   hw->mac.link_duplex);
/* Set the communication mode */
pch_gbe_set_mode(adapter, hw->mac.link_speed,
 hw->mac.link_duplex);
+
+   pch_gbe_set_multi(netdev);
+   pch_gbe_setup_tctl(adapter);
+   pch_gbe_configure_tx(adapter);
+   pch_gbe_setup_rctl(adapter);
+   pch_gbe_configure_rx(adapter);
+
+   pch_gbe_alloc_tx_buffers(adapter, tx_ring);
+   pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
+
+   pch_gbe_enable_dma_rx(>hw);
+   pch_gbe_enable_mac_rx(>hw);
+
+   napi_enable(>napi);
+   pch_gbe_irq_enable(adapter);
+   netif_start_queue(adapter->netdev);
+
netdev_dbg(netdev,
   "Link is Up %d Mbps %s-Duplex\n",
   hw->mac.link_speed,
@@ -2568,

[PATCH v7 02/11] net: pch_gbe: Mask spare MAC addresses all at once

[Paul Burton]

pch_gbe_set_multi() loops through each unused MAC address register,
masking them one by one & waiting for a bit to clear indicating that the
change has taken effect before zeroing out the MAC register.

This is needlessly inefficient. We can instead set all the desired mask
bits with a single write to the ADDR_MASK register & wait only once for
the busy bit to clear indicating that the addresses are masked (ie.
ignored) as required.

It's pointless zeroing the MAC registers since they're masked anyway so
their contents are irrelevant, so we can avoid looping over them here
entirely.

Signed-off-by: Paul Burton 
Cc: Andrew Lunn 
Cc: David S. Miller 
Cc: netdev@vger.kernel.org
---

Changes in v7: New patch

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 8908ef654d94..9651fa02d4bb 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -2140,15 +2140,13 @@ static void pch_gbe_set_multi(struct net_device *netdev)
pch_gbe_mac_mar_set(hw, ha->addr, i++);
 
/* If there are spare MAC registers, mask & clear them */
-   for (; i < PCH_GBE_MAR_ENTRIES; i++) {
-   /* Clear MAC address mask */
+   if (i < PCH_GBE_MAR_ENTRIES) {
adrmask = ioread32(>reg->ADDR_MASK);
-   iowrite32(adrmask | BIT(i), >reg->ADDR_MASK);
+   adrmask |= GENMASK(PCH_GBE_MAR_ENTRIES - 1, i);
+   iowrite32(adrmask, >reg->ADDR_MASK);
+
/* wait busy */
pch_gbe_wait_clr_bit(>reg->ADDR_MASK, PCH_GBE_BUSY);
-   /* Clear MAC address */
-   iowrite32(0, >reg->mac_adr[i].high);
-   iowrite32(0, >reg->mac_adr[i].low);
}
 
netdev_dbg(netdev,
-- 
2.18.0

[PATCH v7 00/11] net: pch_gbe: Fixes, conversion to phylib, enable for MIPS

[Paul Burton]

This series cleans up & reworks the pch_gbe driver such that it no
longer contains PHY-specific code, converts it to phylib & enables it to
be built on MIPS systems for use with the MIPS Boston development board.

Unfortunately I don't have access to a Minnowboard, which the driver
contains some platform-specific code for, so I haven't been able to test
the end result there.

Applies cleanly atop net-next as of commit 27a2628b3c24 ("selftests:
forwarding: mirror_gre_vlan_bridge_1q: Unset rp_filter").

Thanks,
Paul

Andrew Lunn (1):
  net: pch_gbe: Convert to mdiobus and phylib

Paul Burton (10):
  net: pch_gbe: Remove unused struct pch_gbe_adapter fields
  net: pch_gbe: Mask spare MAC addresses all at once
  net: pch_gbe: Probe PHY ID & initialize only once
  net: pch_gbe: Remove irq_sem
  net: pch_gbe: Move pch_gbe_watchdog lower in pch_gbe_main.c
  net: pch_gbe: Only enable MAC when PHY link is active
  net: pch_gbe: Remove AR8031 PHY hibernation disable
  net: pch_gbe: Clean up resets
  ptp: pch: Allow build on MIPS platforms
  net: pch_gbe: Allow build on MIPS platforms

 drivers/net/ethernet/oki-semi/pch_gbe/Kconfig |   5 +-
 .../net/ethernet/oki-semi/pch_gbe/Makefile|   2 +-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe.h   |  20 +-
 .../oki-semi/pch_gbe/pch_gbe_ethtool.c|  88 +---
 .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c  | 407 --
 .../ethernet/oki-semi/pch_gbe/pch_gbe_param.c | 265 
 .../ethernet/oki-semi/pch_gbe/pch_gbe_phy.c   | 377 
 .../ethernet/oki-semi/pch_gbe/pch_gbe_phy.h   |  35 --
 drivers/ptp/Kconfig   |   2 +-
 9 files changed, 191 insertions(+), 1010 deletions(-)
 delete mode 100644 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c
 delete mode 100644 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h

-- 
2.18.0

[PATCH v7 05/11] net: pch_gbe: Move pch_gbe_watchdog lower in pch_gbe_main.c

[Paul Burton]

This patch moves the pch_gbe_watchdog() function lower in pch_gbe_main.c
in order to allow use of other functions in the next patch, without
requiring lots of forward declarations. Doing this as a separate patch
makes it clearer what actually changed in the next patch.

The function is unmodified except for whitespace changes to satisfy
checkpatch.

Signed-off-by: Paul Burton 
Cc: Andrew Lunn 
Cc: David S. Miller 
Cc: netdev@vger.kernel.org
---

Changes in v7: New patch

 .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c  | 103 +-
 1 file changed, 52 insertions(+), 51 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index ee38bba8b9ce..eb290c1edce0 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -1046,57 +1046,6 @@ static void pch_gbe_set_mode(struct pch_gbe_adapter 
*adapter, u16 speed,
iowrite32(mode, >reg->MODE);
 }
 
-/**
- * pch_gbe_watchdog - Watchdog process
- * @data:  Board private structure
- */
-static void pch_gbe_watchdog(struct timer_list *t)
-{
-   struct pch_gbe_adapter *adapter = from_timer(adapter, t,
-watchdog_timer);
-   struct net_device *netdev = adapter->netdev;
-   struct pch_gbe_hw *hw = >hw;
-
-   netdev_dbg(netdev, "right now = %ld\n", jiffies);
-
-   pch_gbe_update_stats(adapter);
-   if ((mii_link_ok(>mii)) && (!netif_carrier_ok(netdev))) {
-   struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
-   netdev->tx_queue_len = adapter->tx_queue_len;
-   /* mii library handles link maintenance tasks */
-   if (mii_ethtool_gset(>mii, )) {
-   netdev_err(netdev, "ethtool get setting Error\n");
-   mod_timer(>watchdog_timer,
- round_jiffies(jiffies +
-   PCH_GBE_WATCHDOG_PERIOD));
-   return;
-   }
-   hw->mac.link_speed = ethtool_cmd_speed();
-   hw->mac.link_duplex = cmd.duplex;
-   /* Set the RGMII control. */
-   pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
-   hw->mac.link_duplex);
-   /* Set the communication mode */
-   pch_gbe_set_mode(adapter, hw->mac.link_speed,
-hw->mac.link_duplex);
-   netdev_dbg(netdev,
-  "Link is Up %d Mbps %s-Duplex\n",
-  hw->mac.link_speed,
-  cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
-   netif_carrier_on(netdev);
-   netif_wake_queue(netdev);
-   } else if ((!mii_link_ok(>mii)) &&
-  (netif_carrier_ok(netdev))) {
-   netdev_dbg(netdev, "NIC Link is Down\n");
-   hw->mac.link_speed = SPEED_10;
-   hw->mac.link_duplex = DUPLEX_HALF;
-   netif_carrier_off(netdev);
-   netif_stop_queue(netdev);
-   }
-   mod_timer(>watchdog_timer,
- round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
-}
-
 /**
  * pch_gbe_tx_queue - Carry out queuing of the transmission data
  * @adapter:  Board private structure
@@ -1973,6 +1922,58 @@ void pch_gbe_down(struct pch_gbe_adapter *adapter)
rx_ring->rx_buff_pool = NULL;
 }
 
+/**
+ * pch_gbe_watchdog - Watchdog process
+ * @data:  Board private structure
+ */
+static void pch_gbe_watchdog(struct timer_list *t)
+{
+   struct pch_gbe_adapter *adapter = from_timer(adapter, t,
+watchdog_timer);
+   struct net_device *netdev = adapter->netdev;
+   struct pch_gbe_hw *hw = >hw;
+
+   netdev_dbg(netdev, "right now = %ld\n", jiffies);
+
+   pch_gbe_update_stats(adapter);
+   if ((mii_link_ok(>mii)) && (!netif_carrier_ok(netdev))) {
+   struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
+
+   netdev->tx_queue_len = adapter->tx_queue_len;
+   /* mii library handles link maintenance tasks */
+   if (mii_ethtool_gset(>mii, )) {
+   netdev_err(netdev, "ethtool get setting Error\n");
+   mod_timer(>watchdog_timer,
+ round_jiffies(jiffies +
+   PCH_GBE_WATCHDOG_PERIOD));
+   return;
+   }
+   hw->mac.link_speed = ethtool_cmd_speed();
+   hw->mac.link_duplex = cmd.duplex;
+   /* Set the RGMII control. */
+   pch_gbe_set_

[PATCH 10/14] net: pch_gbe: Remove PCH_GBE_MAC_IFOP_RGMII define

[Paul Burton]

The pch_gbe driver currently presumes that the PHY is connected using
RGMII, and would need further work to support other buses. It includes a
define which is always set that conditionalises some of the
RGMII-specific code regardless. Remove it. If we do ever support
different MII buses then preprocessor defines won't be the best way to
select between them anyway.

Signed-off-by: Paul Burton 
---

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 9 -
 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h  | 1 -
 2 files changed, 10 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 5846e8cf1750..11c42aa42b8a 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -366,9 +366,7 @@ static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
/* Read the MAC address. and store to the private data */
pch_gbe_mac_read_mac_addr(hw);
iowrite32(PCH_GBE_ALL_RST, >reg->RESET);
-#ifdef PCH_GBE_MAC_IFOP_RGMII
iowrite32(PCH_GBE_MODE_GMII_ETHER, >reg->MODE);
-#endif
pch_gbe_wait_clr_bit(>reg->RESET, PCH_GBE_ALL_RST);
/* Setup the receive addresses */
pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
@@ -776,9 +774,7 @@ void pch_gbe_reset(struct pch_gbe_adapter *adapter)
}
pch_gbe_phy_init_setting(hw);
/* Setup Mac interface option RGMII */
-#ifdef PCH_GBE_MAC_IFOP_RGMII
pch_gbe_phy_set_rgmii(hw);
-#endif
 }
 
 /**
@@ -1044,7 +1040,6 @@ static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter 
*adapter, u16 speed,
unsigned long rgmii = 0;
 
/* Set the RGMII control. */
-#ifdef PCH_GBE_MAC_IFOP_RGMII
switch (speed) {
case SPEED_10:
rgmii = (PCH_GBE_RGMII_RATE_2_5M |
@@ -1060,10 +1055,6 @@ static void pch_gbe_set_rgmii_ctrl(struct 
pch_gbe_adapter *adapter, u16 speed,
break;
}
iowrite32(rgmii, >reg->RGMII_CTRL);
-#else  /* GMII */
-   rgmii = 0;
-   iowrite32(rgmii, >reg->RGMII_CTRL);
-#endif
 }
 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
  u16 duplex)
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h
index efb955be8cac..23ac38711619 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h
@@ -21,7 +21,6 @@
 
 #define PCH_GBE_PHY_REGS_LEN   32
 #definePCH_GBE_PHY_RESET_DELAY_US  10
-#define PCH_GBE_MAC_IFOP_RGMII
 
 s32 pch_gbe_phy_get_id(struct pch_gbe_hw *hw);
 s32 pch_gbe_phy_read_reg_miic(struct pch_gbe_hw *hw, u32 offset, u16 *data);
-- 
2.17.1

[PATCH 08/14] net: pch_gbe: Remove get_bus_info HAL abstraction

[Paul Burton]

For some reason the pch_gbe driver contains a struct pch_gbe_functions
with pointers used by a HAL abstraction layer, even though there is only
one implementation of each function.

This patch removes the get_bus_info abstraction. Its single
implementation (pch_gbe_plat_get_bus_info) only sets values within a
struct pch_gbe_bus_info which is never used, so we simply remove the
call to it in pch_gbe_probe & remove struct pch_gbe_bus_info entirely.

Now that struct pch_gbe_functions is empty we remove it entirely too.

Signed-off-by: Paul Burton 
---

 .../net/ethernet/oki-semi/pch_gbe/pch_gbe.h   | 23 
 .../ethernet/oki-semi/pch_gbe/pch_gbe_api.c   | 58 ---
 .../ethernet/oki-semi/pch_gbe/pch_gbe_api.h   |  1 -
 .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c  |  1 -
 4 files changed, 83 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index 2e824baff9d7..44c2f291e766 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -326,16 +326,6 @@ struct pch_gbe_regs {
 #define PCH_GBE_FC_FULL3
 #define PCH_GBE_FC_DEFAULT PCH_GBE_FC_FULL
 
-
-struct pch_gbe_hw;
-/**
- * struct  pch_gbe_functions - HAL APi function pointer
- * @get_bus_info:  for pch_gbe_hal_get_bus_info
- */
-struct pch_gbe_functions {
-   void (*get_bus_info) (struct pch_gbe_hw *);
-};
-
 /**
  * struct pch_gbe_mac_info - MAC information
  * @addr[6]:   Store the MAC address
@@ -376,17 +366,6 @@ struct pch_gbe_phy_info {
u16 autoneg_advertised;
 };
 
-/*!
- * @ingroup Gigabit Ether driver Layer
- * @struct  pch_gbe_bus_info
- * @brief   Bus information
- */
-struct pch_gbe_bus_info {
-   u8 type;
-   u8 speed;
-   u8 width;
-};
-
 /*!
  * @ingroup Gigabit Ether driver Layer
  * @struct  pch_gbe_hw
@@ -398,10 +377,8 @@ struct pch_gbe_hw {
struct pch_gbe_regs  __iomem *reg;
spinlock_t miim_lock;
 
-   const struct pch_gbe_functions *func;
struct pch_gbe_mac_info mac;
struct pch_gbe_phy_info phy;
-   struct pch_gbe_bus_info bus;
 };
 
 /**
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
index 03fbd4752d4f..89c0db27b797 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
@@ -20,47 +20,6 @@
 #include "pch_gbe_phy.h"
 #include "pch_gbe_api.h"
 
-/* bus type values */
-#define pch_gbe_bus_type_unknown   0
-#define pch_gbe_bus_type_pci   1
-#define pch_gbe_bus_type_pcix  2
-#define pch_gbe_bus_type_pci_express   3
-#define pch_gbe_bus_type_reserved  4
-
-/* bus speed values */
-#define pch_gbe_bus_speed_unknown  0
-#define pch_gbe_bus_speed_33   1
-#define pch_gbe_bus_speed_66   2
-#define pch_gbe_bus_speed_100  3
-#define pch_gbe_bus_speed_120  4
-#define pch_gbe_bus_speed_133  5
-#define pch_gbe_bus_speed_2500 6
-#define pch_gbe_bus_speed_reserved 7
-
-/* bus width values */
-#define pch_gbe_bus_width_unknown  0
-#define pch_gbe_bus_width_pcie_x1  1
-#define pch_gbe_bus_width_pcie_x2  2
-#define pch_gbe_bus_width_pcie_x4  4
-#define pch_gbe_bus_width_32   5
-#define pch_gbe_bus_width_64   6
-#define pch_gbe_bus_width_reserved 7
-
-/**
- * pch_gbe_plat_get_bus_info - Obtain bus information for adapter
- * @hw:Pointer to the HW structure
- */
-static void pch_gbe_plat_get_bus_info(struct pch_gbe_hw *hw)
-{
-   hw->bus.type  = pch_gbe_bus_type_pci_express;
-   hw->bus.speed = pch_gbe_bus_speed_2500;
-   hw->bus.width = pch_gbe_bus_width_pcie_x1;
-}
-
-static const struct pch_gbe_functions pch_gbe_ops = {
-   .get_bus_info  = pch_gbe_plat_get_bus_info,
-};
-
 /**
  * pch_gbe_plat_init_function_pointers - Init func ptrs
  * @hw:Pointer to the HW structure
@@ -69,8 +28,6 @@ static void pch_gbe_plat_init_function_pointers(struct 
pch_gbe_hw *hw)
 {
/* Set PHY parameter */
hw->phy.reset_delay_us = PCH_GBE_PHY_RESET_DELAY_US;
-   /* Set function pointers */
-   hw->func = _gbe_ops;
 }
 
 /**
@@ -91,18 +48,3 @@ s32 pch_gbe_hal_setup_init_funcs(struct pch_gbe_hw *hw)
pch_gbe_plat_init_function_pointers(hw);
return 0;
 }
-
-/**
- * pch_gbe_hal_get_bus_info - Obtain bus information for adapter
- * @hw:Pointer to the HW structure
- */
-void pch_gbe_hal_get_bus_info(struct pch_gbe_hw *hw)
-{
-   if (!hw->func->get_bus_info) {
-   struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
-
-   netdev_err(adapter->netdev, "ERROR: configuration\n");
-   return;
-   }
-   hw->func->get_bus_info(hw);
-}
diff --git a/drivers/net/ethernet/oki-sem

[PATCH 11/14] net: pch_gbe: Remove dead RINGFREE code

[Paul Burton]

The pch_gbe driver includes some code which appears to be an attempt to
work around a problem with the pch_gbe_free_rx_resources &
pch_gbe_free_tx_resources functions that no longer exists. Remove the
code guarded by the never-defined RINGFREE preprocessor macro.

Signed-off-by: Paul Burton 
---

 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c | 13 -
 1 file changed, 13 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c
index a7bdb53790ff..adaa0024adfe 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c
@@ -349,25 +349,12 @@ static int pch_gbe_set_ringparam(struct net_device 
*netdev,
err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
if (err)
goto err_setup_tx;
-   /* save the new, restore the old in order to free it,
-* then restore the new back again */
-#ifdef RINGFREE
-   adapter->rx_ring = rx_old;
-   adapter->tx_ring = tx_old;
-   pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
-   pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
-   kfree(tx_old);
-   kfree(rx_old);
-   adapter->rx_ring = rxdr;
-   adapter->tx_ring = txdr;
-#else
pch_gbe_free_rx_resources(adapter, rx_old);
pch_gbe_free_tx_resources(adapter, tx_old);
kfree(tx_old);
kfree(rx_old);
adapter->rx_ring = rxdr;
adapter->tx_ring = txdr;
-#endif
err = pch_gbe_up(adapter);
}
return err;
-- 
2.17.1

[PATCH 02/14] net: pch_gbe: Remove power_{up,down}_phy HAL abstraction

[Paul Burton]

For some reason the pch_gbe driver contains a struct pch_gbe_functions
with pointers used by a HAL abstraction layer, even though there is only
one implementation of each function.

This patch removes the power_up_phy & power_down_phy abstractions in
favor of calling pch_phy_power_up & pch_phy_power_down directly.

Signed-off-by: Paul Burton 
---

 .../net/ethernet/oki-semi/pch_gbe/pch_gbe.h   |  4 
 .../ethernet/oki-semi/pch_gbe/pch_gbe_api.c   | 22 ---
 .../ethernet/oki-semi/pch_gbe/pch_gbe_api.h   |  2 --
 .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c  | 12 +-
 4 files changed, 6 insertions(+), 34 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index 697e29dd4bd3..8dc40faef720 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -336,8 +336,6 @@ struct pch_gbe_hw;
  * @write_phy_reg: for pch_gbe_hal_write_phy_reg
  * @reset_phy: for pch_gbe_hal_phy_hw_reset
  * @sw_reset_phy:  for pch_gbe_hal_phy_sw_reset
- * @power_up_phy:  for pch_gbe_hal_power_up_phy
- * @power_down_phy:for pch_gbe_hal_power_down_phy
  * @read_mac_addr: for pch_gbe_hal_read_mac_addr
  */
 struct pch_gbe_functions {
@@ -347,8 +345,6 @@ struct pch_gbe_functions {
s32 (*write_phy_reg) (struct pch_gbe_hw *, u32, u16);
void (*reset_phy) (struct pch_gbe_hw *);
void (*sw_reset_phy) (struct pch_gbe_hw *);
-   void (*power_up_phy) (struct pch_gbe_hw *hw);
-   void (*power_down_phy) (struct pch_gbe_hw *hw);
s32 (*read_mac_addr) (struct pch_gbe_hw *);
 };
 
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
index 51250363566b..d66933b68934 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
@@ -90,8 +90,6 @@ static const struct pch_gbe_functions pch_gbe_ops = {
.write_phy_reg = pch_gbe_phy_write_reg_miic,
.reset_phy = pch_gbe_phy_hw_reset,
.sw_reset_phy  = pch_gbe_phy_sw_reset,
-   .power_up_phy  = pch_gbe_phy_power_up,
-   .power_down_phy= pch_gbe_phy_power_down,
.read_mac_addr = pch_gbe_mac_read_mac_addr
 };
 
@@ -240,23 +238,3 @@ s32 pch_gbe_hal_read_mac_addr(struct pch_gbe_hw *hw)
}
return hw->func->read_mac_addr(hw);
 }
-
-/**
- * pch_gbe_hal_power_up_phy - Power up PHY
- * @hw:Pointer to the HW structure
- */
-void pch_gbe_hal_power_up_phy(struct pch_gbe_hw *hw)
-{
-   if (hw->func->power_up_phy)
-   hw->func->power_up_phy(hw);
-}
-
-/**
- * pch_gbe_hal_power_down_phy - Power down PHY
- * @hw:Pointer to the HW structure
- */
-void pch_gbe_hal_power_down_phy(struct pch_gbe_hw *hw)
-{
-   if (hw->func->power_down_phy)
-   hw->func->power_down_phy(hw);
-}
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
index 91ce07c8306c..be2f202c26c4 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
@@ -29,7 +29,5 @@ s32 pch_gbe_hal_write_phy_reg(struct pch_gbe_hw *hw, u32 
offset, u16 data);
 void pch_gbe_hal_phy_hw_reset(struct pch_gbe_hw *hw);
 void pch_gbe_hal_phy_sw_reset(struct pch_gbe_hw *hw);
 s32 pch_gbe_hal_read_mac_addr(struct pch_gbe_hw *hw);
-void pch_gbe_hal_power_up_phy(struct pch_gbe_hw *hw);
-void pch_gbe_hal_power_down_phy(struct pch_gbe_hw *hw);
 
 #endif
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 044a7561752c..13fc828c7fd3 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -2072,7 +2072,7 @@ static int pch_gbe_open(struct net_device *netdev)
err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
if (err)
goto err_setup_rx;
-   pch_gbe_hal_power_up_phy(hw);
+   pch_gbe_phy_power_up(hw);
err = pch_gbe_up(adapter);
if (err)
goto err_up;
@@ -2081,7 +2081,7 @@ static int pch_gbe_open(struct net_device *netdev)
 
 err_up:
if (!adapter->wake_up_evt)
-   pch_gbe_hal_power_down_phy(hw);
+   pch_gbe_phy_power_down(hw);
pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
 err_setup_rx:
pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
@@ -2104,7 +2104,7 @@ static int pch_gbe_stop(struct net_device *netdev)
 
pch_gbe_down(adapter);
if (!adapter->wake_up_evt)
-   pch_gbe_hal_power_down_phy(hw);
+   pch_gbe_phy_power_down(hw);
pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
pch_gbe_free_rx_resources(

[PATCH 09/14] net: pch_gbe: Remove pch_gbe_hal_setup_init_funcs

[Paul Burton]

The pch_gbe driver calls a pch_gbe_hal_setup_init_funcs function which
ultimately sets the value of one field in struct pch_gbe_phy_info in a
convoluted way.

This patch removes pch_gbe_hal_setup_init_funcs in favor of inlining it,
and in turn its callee pch_gbe_plat_init_function_pointers, into the
single caller pch_gbe_sw_init.

With this pch_gbe_api.c & pch_gbe_api.h are essentially empty, so they
are removed & inclusions of the latter replaced with pch_gbe_phy.h which
was previously being included via pch_gbe_api.h.

Signed-off-by: Paul Burton 
---

 .../net/ethernet/oki-semi/pch_gbe/Makefile|  2 +-
 .../ethernet/oki-semi/pch_gbe/pch_gbe_api.c   | 50 ---
 .../ethernet/oki-semi/pch_gbe/pch_gbe_api.h   | 26 --
 .../oki-semi/pch_gbe/pch_gbe_ethtool.c|  2 +-
 .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c  |  8 +--
 5 files changed, 4 insertions(+), 84 deletions(-)
 delete mode 100644 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
 delete mode 100644 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/Makefile 
b/drivers/net/ethernet/oki-semi/pch_gbe/Makefile
index 31288d4ad248..862de0f3bc41 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/Makefile
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/Makefile
@@ -1,4 +1,4 @@
 obj-$(CONFIG_PCH_GBE) += pch_gbe.o
 
 pch_gbe-y := pch_gbe_phy.o pch_gbe_ethtool.o pch_gbe_param.o
-pch_gbe-y += pch_gbe_api.o pch_gbe_main.o
+pch_gbe-y += pch_gbe_main.o
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
deleted file mode 100644
index 89c0db27b797..
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright (C) 1999 - 2010 Intel Corporation.
- * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
- *
- * This code was derived from the Intel e1000e Linux driver.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-#include "pch_gbe.h"
-#include "pch_gbe_phy.h"
-#include "pch_gbe_api.h"
-
-/**
- * pch_gbe_plat_init_function_pointers - Init func ptrs
- * @hw:Pointer to the HW structure
- */
-static void pch_gbe_plat_init_function_pointers(struct pch_gbe_hw *hw)
-{
-   /* Set PHY parameter */
-   hw->phy.reset_delay_us = PCH_GBE_PHY_RESET_DELAY_US;
-}
-
-/**
- * pch_gbe_hal_setup_init_funcs - Initializes function pointers
- * @hw:Pointer to the HW structure
- * Returns:
- * 0:  Successfully
- * ENOSYS: Function is not registered
- */
-s32 pch_gbe_hal_setup_init_funcs(struct pch_gbe_hw *hw)
-{
-   if (!hw->reg) {
-   struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
-
-   netdev_err(adapter->netdev, "ERROR: Registers not mapped\n");
-   return -ENOSYS;
-   }
-   pch_gbe_plat_init_function_pointers(hw);
-   return 0;
-}
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
deleted file mode 100644
index b3b713a32f38..
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 1999 - 2010 Intel Corporation.
- * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
- *
- * This code was derived from the Intel e1000e Linux driver.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-#ifndef _PCH_GBE_API_H_
-#define _PCH_GBE_API_H_
-
-#include "pch_gbe_phy.h"
-
-s32 pch_gbe_hal_setup_init_funcs(struct pch_gbe_hw *hw);
-
-#endif
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c
index da39d771ad87..a7bdb53790ff 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c
+++ b/driv

[PATCH 07/14] net: pch_gbe: Remove init_hw HAL abstraction

[Paul Burton]

For some reason the pch_gbe driver contains a struct pch_gbe_functions
with pointers used by a HAL abstraction layer, even though there is only
one implementation of each function.

This patch removes the init_hw abstraction in favor of inlining its
single implementation (pch_gbe_plat_init_hw) into its single caller
(pch_gbe_reset).

Signed-off-by: Paul Burton 
---

 .../net/ethernet/oki-semi/pch_gbe/pch_gbe.h   |  2 -
 .../ethernet/oki-semi/pch_gbe/pch_gbe_api.c   | 45 ---
 .../ethernet/oki-semi/pch_gbe/pch_gbe_api.h   |  1 -
 .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c  | 19 ++--
 4 files changed, 15 insertions(+), 52 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index 728e876bffc6..2e824baff9d7 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -331,11 +331,9 @@ struct pch_gbe_hw;
 /**
  * struct  pch_gbe_functions - HAL APi function pointer
  * @get_bus_info:  for pch_gbe_hal_get_bus_info
- * @init_hw:   for pch_gbe_hal_init_hw
  */
 struct pch_gbe_functions {
void (*get_bus_info) (struct pch_gbe_hw *);
-   s32 (*init_hw) (struct pch_gbe_hw *);
 };
 
 /**
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
index 484be4225352..03fbd4752d4f 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
@@ -57,35 +57,8 @@ static void pch_gbe_plat_get_bus_info(struct pch_gbe_hw *hw)
hw->bus.width = pch_gbe_bus_width_pcie_x1;
 }
 
-/**
- * pch_gbe_plat_init_hw - Initialize hardware
- * @hw:Pointer to the HW structure
- * Returns:
- * 0:  Successfully
- * Negative value: Failed-EBUSY
- */
-static s32 pch_gbe_plat_init_hw(struct pch_gbe_hw *hw)
-{
-   s32 ret_val;
-
-   ret_val = pch_gbe_phy_get_id(hw);
-   if (ret_val) {
-   struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
-
-   netdev_err(adapter->netdev, "pch_gbe_phy_get_id error\n");
-   return ret_val;
-   }
-   pch_gbe_phy_init_setting(hw);
-   /* Setup Mac interface option RGMII */
-#ifdef PCH_GBE_MAC_IFOP_RGMII
-   pch_gbe_phy_set_rgmii(hw);
-#endif
-   return ret_val;
-}
-
 static const struct pch_gbe_functions pch_gbe_ops = {
.get_bus_info  = pch_gbe_plat_get_bus_info,
-   .init_hw   = pch_gbe_plat_init_hw,
 };
 
 /**
@@ -133,21 +106,3 @@ void pch_gbe_hal_get_bus_info(struct pch_gbe_hw *hw)
}
hw->func->get_bus_info(hw);
 }
-
-/**
- * pch_gbe_hal_init_hw - Initialize hardware
- * @hw:Pointer to the HW structure
- * Returns:
- * 0:  Successfully
- * ENOSYS: Function is not registered
- */
-s32 pch_gbe_hal_init_hw(struct pch_gbe_hw *hw)
-{
-   if (!hw->func->init_hw) {
-   struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
-
-   netdev_err(adapter->netdev, "ERROR: configuration\n");
-   return -ENOSYS;
-   }
-   return hw->func->init_hw(hw);
-}
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
index 9cd19605f4ff..56cae9cfb5c5 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
@@ -23,6 +23,5 @@
 
 s32 pch_gbe_hal_setup_init_funcs(struct pch_gbe_hw *hw);
 void pch_gbe_hal_get_bus_info(struct pch_gbe_hw *hw);
-s32 pch_gbe_hal_init_hw(struct pch_gbe_hw *hw);
 
 #endif
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 175d6608bdb9..9297a94df999 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -760,14 +760,25 @@ void pch_gbe_reinit_locked(struct pch_gbe_adapter 
*adapter)
 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
 {
struct net_device *netdev = adapter->netdev;
+   struct pch_gbe_hw *hw = >hw;
+   s32 ret_val;
 
-   pch_gbe_mac_reset_hw(>hw);
+   pch_gbe_mac_reset_hw(hw);
/* reprogram multicast address register after reset */
pch_gbe_set_multi(netdev);
/* Setup the receive address. */
-   pch_gbe_mac_init_rx_addrs(>hw, PCH_GBE_MAR_ENTRIES);
-   if (pch_gbe_hal_init_hw(>hw))
-   netdev_err(netdev, "Hardware Error\n");
+   pch_gbe_mac_init_rx_addrs(hw, PCH_GBE_MAR_ENTRIES);
+
+   ret_val = pch_gbe_phy_get_id(hw);
+   if (ret_val) {
+   netdev_err(adapter->netdev, "pch_gbe_phy_get_id error\n");
+   return;
+   }
+   pch_gbe_phy_init_setting(hw);
+   /* Setup Mac interface option RGMII */
+#ifdef PCH_GBE_MAC_IFOP_RGMII
+   pch_gbe_phy_set_rgmii(hw);
+#endif
 }
 
 /**
-- 
2.17.1

[PATCH 03/14] net: pch_gbe: Remove read_mac_addr HAL abstraction

[Paul Burton]

For some reason the pch_gbe driver contains a struct pch_gbe_functions
with pointers used by a HAL abstraction layer, even though there is only
one implementation of each function.

This patch removes the read_mac_addr abstraction in favor of calling
pch_gbe_mac_read_mac_addr directly. Since this is defined in the same
translation unit as all of its callers, we can make it static & remove
it from the pch_gbe.h header.

Signed-off-by: Paul Burton 
---

 .../net/ethernet/oki-semi/pch_gbe/pch_gbe.h   |  3 ---
 .../ethernet/oki-semi/pch_gbe/pch_gbe_api.c   | 19 ---
 .../ethernet/oki-semi/pch_gbe/pch_gbe_api.h   |  1 -
 .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c  |  4 ++--
 4 files changed, 2 insertions(+), 25 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index 8dc40faef720..5dbfcd55efa8 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -336,7 +336,6 @@ struct pch_gbe_hw;
  * @write_phy_reg: for pch_gbe_hal_write_phy_reg
  * @reset_phy: for pch_gbe_hal_phy_hw_reset
  * @sw_reset_phy:  for pch_gbe_hal_phy_sw_reset
- * @read_mac_addr: for pch_gbe_hal_read_mac_addr
  */
 struct pch_gbe_functions {
void (*get_bus_info) (struct pch_gbe_hw *);
@@ -345,7 +344,6 @@ struct pch_gbe_functions {
s32 (*write_phy_reg) (struct pch_gbe_hw *, u32, u16);
void (*reset_phy) (struct pch_gbe_hw *);
void (*sw_reset_phy) (struct pch_gbe_hw *);
-   s32 (*read_mac_addr) (struct pch_gbe_hw *);
 };
 
 /**
@@ -676,7 +674,6 @@ void pch_gbe_set_ethtool_ops(struct net_device *netdev);
 
 /* pch_gbe_mac.c */
 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw);
-s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw);
 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
  u16 data);
 #endif /* _PCH_GBE_H_ */
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
index d66933b68934..3c6e009955ab 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
@@ -90,7 +90,6 @@ static const struct pch_gbe_functions pch_gbe_ops = {
.write_phy_reg = pch_gbe_phy_write_reg_miic,
.reset_phy = pch_gbe_phy_hw_reset,
.sw_reset_phy  = pch_gbe_phy_sw_reset,
-   .read_mac_addr = pch_gbe_mac_read_mac_addr
 };
 
 /**
@@ -220,21 +219,3 @@ void pch_gbe_hal_phy_sw_reset(struct pch_gbe_hw *hw)
}
hw->func->sw_reset_phy(hw);
 }
-
-/**
- * pch_gbe_hal_read_mac_addr - Reads MAC address
- * @hw:Pointer to the HW structure
- * Returns:
- * 0:  Successfully
- * ENOSYS: Function is not registered
- */
-s32 pch_gbe_hal_read_mac_addr(struct pch_gbe_hw *hw)
-{
-   if (!hw->func->read_mac_addr) {
-   struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
-
-   netdev_err(adapter->netdev, "ERROR: configuration\n");
-   return -ENOSYS;
-   }
-   return hw->func->read_mac_addr(hw);
-}
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
index be2f202c26c4..13fcdfb4a94d 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
@@ -28,6 +28,5 @@ s32 pch_gbe_hal_read_phy_reg(struct pch_gbe_hw *hw, u32 
offset, u16 *data);
 s32 pch_gbe_hal_write_phy_reg(struct pch_gbe_hw *hw, u32 offset, u16 data);
 void pch_gbe_hal_phy_hw_reset(struct pch_gbe_hw *hw);
 void pch_gbe_hal_phy_sw_reset(struct pch_gbe_hw *hw);
-s32 pch_gbe_hal_read_mac_addr(struct pch_gbe_hw *hw);
 
 #endif
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 13fc828c7fd3..fc5079fa01e8 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -287,7 +287,7 @@ static inline void pch_gbe_mac_load_mac_addr(struct 
pch_gbe_hw *hw)
  * Returns:
  * 0:  Successful.
  */
-s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
+static s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
 {
struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
u32  adr1a, adr1b;
@@ -2627,7 +2627,7 @@ static int pch_gbe_probe(struct pci_dev *pdev,
pch_gbe_hal_get_bus_info(>hw);
 
/* Read the MAC address. and store to the private data */
-   ret = pch_gbe_hal_read_mac_addr(>hw);
+   ret = pch_gbe_mac_read_mac_addr(>hw);
if (ret) {
dev_err(>dev, "MAC address Read Error\n");
goto err_free_adapter;
-- 
2.17.1

[PATCH 14/14] net: pch_gbe: Clean up pch_gbe_set_multi

[Paul Burton]

Refactor pch_gbe_set_multi in order to avoid unnecessary indentation &
make it clearer what the code is doing.

The one behavioral change from this patch is that we'll no longer
configure the MAC address registers for multicast addresses when the
IFF_PROMISC or IFF_ALLMULTI flags are set. In these cases, just as when
we want to monitor more multicast addresses than we have MAC address
registers, we disable multicast filtering so the MAC address registers
are unused.

Signed-off-by: Paul Burton 

---

 .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c  | 33 +--
 1 file changed, 16 insertions(+), 17 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index dc8c4050fad3..43c0c10dfeb7 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -2110,28 +2110,27 @@ static void pch_gbe_set_multi(struct net_device *netdev)
 
netdev_dbg(netdev, "netdev->flags : 0x%08x\n", netdev->flags);
 
-   /* Check for Promiscuous and All Multicast modes */
+   /* By default enable address & multicast filtering */
rctl = ioread32(>reg->RX_MODE);
+   rctl |= PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN;
+
+   /* Promiscuous mode disables all hardware address filtering */
+   if (netdev->flags & IFF_PROMISC)
+   rctl &= ~(PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
+
+   /* If we want to monitor more multicast addresses than the hardware can
+* support then disable hardware multicast filtering.
+*/
mc_count = netdev_mc_count(netdev);
-   if ((netdev->flags & IFF_PROMISC)) {
-   rctl &= ~PCH_GBE_ADD_FIL_EN;
+   if ((netdev->flags & IFF_ALLMULTI) || mc_count >= PCH_GBE_MAR_ENTRIES)
rctl &= ~PCH_GBE_MLT_FIL_EN;
-   } else if ((netdev->flags & IFF_ALLMULTI)) {
-   /* all the multicasting receive permissions */
-   rctl |= PCH_GBE_ADD_FIL_EN;
-   rctl &= ~PCH_GBE_MLT_FIL_EN;
-   } else {
-   if (mc_count >= PCH_GBE_MAR_ENTRIES) {
-   /* all the multicasting receive permissions */
-   rctl |= PCH_GBE_ADD_FIL_EN;
-   rctl &= ~PCH_GBE_MLT_FIL_EN;
-   } else {
-   rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
-   }
-   }
+
iowrite32(rctl, >reg->RX_MODE);
 
-   if (mc_count >= PCH_GBE_MAR_ENTRIES)
+   /* If we're not using multicast filtering then there's no point
+* configuring the unused MAC address registers.
+*/
+   if (!(rctl & PCH_GBE_MLT_FIL_EN))
return;
 
/* Load the first set of multicast addresses into MAC address registers
-- 
2.17.1

[PATCH 13/14] net: pch_gbe: Inline pch_gbe_mac_mc_addr_list_update

[Paul Burton]

The pch_gbe driver sets up multicast address filters using a convoluted
mechanism by which pch_gbe_set_multi allocates an array to hold
multicast addresses, copies desired addresses into that array, calls a
pch_gbe_mac_mc_addr_list_update function which copies addresses out of
that array into MAC registers, then frees the array.

This patch simplifies this somewhat by inlining
pch_gbe_mac_mc_addr_list_update into pch_gbe_set_multi, and removing the
requirement for the MAC addresses to stored consecutively in a single
array.

Signed-off-by: Paul Burton 
---

 .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c  | 73 +--
 1 file changed, 19 insertions(+), 54 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 3f2dd36d45ad..dc8c4050fad3 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -411,44 +411,6 @@ static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw 
*hw, u16 mar_count)
pch_gbe_wait_clr_bit(>reg->ADDR_MASK, PCH_GBE_BUSY);
 }
 
-
-/**
- * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
- * @hw:Pointer to the HW structure
- * @mc_addr_list:   Array of multicast addresses to program
- * @mc_addr_count:  Number of multicast addresses to program
- * @mar_used_count: The first MAC Address register free to program
- * @mar_total_num:  Total number of supported MAC Address Registers
- */
-static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
-   u8 *mc_addr_list, u32 mc_addr_count,
-   u32 mar_used_count, u32 
mar_total_num)
-{
-   u32 i, adrmask;
-
-   /* Load the first set of multicast addresses into the exact
-* filters (RAR).  If there are not enough to fill the RAR
-* array, clear the filters.
-*/
-   for (i = mar_used_count; i < mar_total_num; i++) {
-   if (mc_addr_count) {
-   pch_gbe_mac_mar_set(hw, mc_addr_list, i);
-   mc_addr_count--;
-   mc_addr_list += ETH_ALEN;
-   } else {
-   /* Clear MAC address mask */
-   adrmask = ioread32(>reg->ADDR_MASK);
-   iowrite32((adrmask | (0x0001 << i)),
-   >reg->ADDR_MASK);
-   /* wait busy */
-   pch_gbe_wait_clr_bit(>reg->ADDR_MASK, PCH_GBE_BUSY);
-   /* Clear MAC address */
-   iowrite32(0, >reg->mac_adr[i].high);
-   iowrite32(0, >reg->mac_adr[i].low);
-   }
-   }
-}
-
 /**
  * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
  * @hw:Pointer to the HW structure
@@ -2143,10 +2105,8 @@ static void pch_gbe_set_multi(struct net_device *netdev)
struct pch_gbe_adapter *adapter = netdev_priv(netdev);
struct pch_gbe_hw *hw = >hw;
struct netdev_hw_addr *ha;
-   u8 *mta_list;
-   u32 rctl;
-   int i;
-   int mc_count;
+   u32 rctl, adrmask;
+   int mc_count, i;
 
netdev_dbg(netdev, "netdev->flags : 0x%08x\n", netdev->flags);
 
@@ -2173,20 +2133,25 @@ static void pch_gbe_set_multi(struct net_device *netdev)
 
if (mc_count >= PCH_GBE_MAR_ENTRIES)
return;
-   mta_list = kmalloc_array(ETH_ALEN, mc_count, GFP_ATOMIC);
-   if (!mta_list)
-   return;
 
-   /* The shared function expects a packed array of only addresses. */
-   i = 0;
-   netdev_for_each_mc_addr(ha, netdev) {
-   if (i == mc_count)
-   break;
-   memcpy(mta_list + (i++ * ETH_ALEN), >addr, ETH_ALEN);
+   /* Load the first set of multicast addresses into MAC address registers
+* for use by hardware filtering.
+*/
+   i = 1;
+   netdev_for_each_mc_addr(ha, netdev)
+   pch_gbe_mac_mar_set(hw, ha->addr, i++);
+
+   /* If there are spare MAC registers, mask & clear them */
+   for (; i < PCH_GBE_MAR_ENTRIES; i++) {
+   /* Clear MAC address mask */
+   adrmask = ioread32(>reg->ADDR_MASK);
+   iowrite32(adrmask | BIT(i), >reg->ADDR_MASK);
+   /* wait busy */
+   pch_gbe_wait_clr_bit(>reg->ADDR_MASK, PCH_GBE_BUSY);
+   /* Clear MAC address */
+   iowrite32(0, >reg->mac_adr[i].high);
+   iowrite32(0, >reg->mac_adr[i].low);
}
-   pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
-   PCH_GBE_MAR_ENTRIES);
-   kfree(mta_list);
 
netdev_dbg(netdev,
 "RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x  
netdev->mc_count : 0x%08x\n",
-- 
2.17.1

[PATCH 04/14] net: pch_gbe: Remove sw_reset_phy HAL abstraction

[Paul Burton]

For some reason the pch_gbe driver contains a struct pch_gbe_functions
with pointers used by a HAL abstraction layer, even though there is only
one implementation of each function.

This patch removes the sw_reset_phy abstraction, which it turns out is
never even used. Its one implementation, which is already called
directly within the same translation unit, can therefore be made static
and removed from the pch_gbe_phy.h header.

Signed-off-by: Paul Burton 
---

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h  |  2 --
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c  | 16 
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h  |  1 -
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c  |  2 +-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h  |  1 -
 5 files changed, 1 insertion(+), 21 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index 5dbfcd55efa8..47ee7428c3d3 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -335,7 +335,6 @@ struct pch_gbe_hw;
  * @read_phy_reg:  for pch_gbe_hal_read_phy_reg
  * @write_phy_reg: for pch_gbe_hal_write_phy_reg
  * @reset_phy: for pch_gbe_hal_phy_hw_reset
- * @sw_reset_phy:  for pch_gbe_hal_phy_sw_reset
  */
 struct pch_gbe_functions {
void (*get_bus_info) (struct pch_gbe_hw *);
@@ -343,7 +342,6 @@ struct pch_gbe_functions {
s32 (*read_phy_reg) (struct pch_gbe_hw *, u32, u16 *);
s32 (*write_phy_reg) (struct pch_gbe_hw *, u32, u16);
void (*reset_phy) (struct pch_gbe_hw *);
-   void (*sw_reset_phy) (struct pch_gbe_hw *);
 };
 
 /**
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
index 3c6e009955ab..e1ecfb076029 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
@@ -89,7 +89,6 @@ static const struct pch_gbe_functions pch_gbe_ops = {
.read_phy_reg  = pch_gbe_phy_read_reg_miic,
.write_phy_reg = pch_gbe_phy_write_reg_miic,
.reset_phy = pch_gbe_phy_hw_reset,
-   .sw_reset_phy  = pch_gbe_phy_sw_reset,
 };
 
 /**
@@ -204,18 +203,3 @@ void pch_gbe_hal_phy_hw_reset(struct pch_gbe_hw *hw)
}
hw->func->reset_phy(hw);
 }
-
-/**
- * pch_gbe_hal_phy_sw_reset - Soft PHY reset
- * @hw:Pointer to the HW structure
- */
-void pch_gbe_hal_phy_sw_reset(struct pch_gbe_hw *hw)
-{
-   if (!hw->func->sw_reset_phy) {
-   struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
-
-   netdev_err(adapter->netdev, "ERROR: configuration\n");
-   return;
-   }
-   hw->func->sw_reset_phy(hw);
-}
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
index 13fcdfb4a94d..aa802f670055 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
@@ -27,6 +27,5 @@ s32 pch_gbe_hal_init_hw(struct pch_gbe_hw *hw);
 s32 pch_gbe_hal_read_phy_reg(struct pch_gbe_hw *hw, u32 offset, u16 *data);
 s32 pch_gbe_hal_write_phy_reg(struct pch_gbe_hw *hw, u32 offset, u16 data);
 void pch_gbe_hal_phy_hw_reset(struct pch_gbe_hw *hw);
-void pch_gbe_hal_phy_sw_reset(struct pch_gbe_hw *hw);
 
 #endif
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c
index a5cad5ea9436..6b35b573beef 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c
@@ -184,7 +184,7 @@ s32 pch_gbe_phy_write_reg_miic(struct pch_gbe_hw *hw, u32 
offset, u16 data)
  * pch_gbe_phy_sw_reset - PHY software reset
  * @hw:Pointer to the HW structure
  */
-void pch_gbe_phy_sw_reset(struct pch_gbe_hw *hw)
+static void pch_gbe_phy_sw_reset(struct pch_gbe_hw *hw)
 {
u16 phy_ctrl;
 
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h
index 95ad0151ad02..efb955be8cac 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h
@@ -26,7 +26,6 @@
 s32 pch_gbe_phy_get_id(struct pch_gbe_hw *hw);
 s32 pch_gbe_phy_read_reg_miic(struct pch_gbe_hw *hw, u32 offset, u16 *data);
 s32 pch_gbe_phy_write_reg_miic(struct pch_gbe_hw *hw, u32 offset, u16 data);
-void pch_gbe_phy_sw_reset(struct pch_gbe_hw *hw);
 void pch_gbe_phy_hw_reset(struct pch_gbe_hw *hw);
 void pch_gbe_phy_power_up(struct pch_gbe_hw *hw);
 void pch_gbe_phy_power_down(struct pch_gbe_hw *hw);
-- 
2.17.1

[PATCH 12/14] net: pch_gbe: Use module_pci_driver()

[Paul Burton]

Make use of the module_pci_driver() macro to remove some needless
boilerplate code from the pch_gbe driver. This does have the side effect
of removing the print of the driver's version during probe, but this is
pretty useless information anyway - the version has changed only once
whilst the driver has been in mainline, despite many changes being made
to it before and since.

Signed-off-by: Paul Burton 
---

 .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c  | 19 +--
 1 file changed, 1 insertion(+), 18 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 11c42aa42b8a..3f2dd36d45ad 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -2770,24 +2770,7 @@ static struct pci_driver pch_gbe_driver = {
.shutdown = pch_gbe_shutdown,
.err_handler = _gbe_err_handler
 };
-
-
-static int __init pch_gbe_init_module(void)
-{
-   int ret;
-
-   pr_info("EG20T PCH Gigabit Ethernet Driver - version %s\n",DRV_VERSION);
-   ret = pci_register_driver(_gbe_driver);
-   return ret;
-}
-
-static void __exit pch_gbe_exit_module(void)
-{
-   pci_unregister_driver(_gbe_driver);
-}
-
-module_init(pch_gbe_init_module);
-module_exit(pch_gbe_exit_module);
+module_pci_driver(pch_gbe_driver);
 
 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, ");
-- 
2.17.1

[PATCH 05/14] net: pch_gbe: Remove reset_phy HAL abstraction

[Paul Burton]

For some reason the pch_gbe driver contains a struct pch_gbe_functions
with pointers used by a HAL abstraction layer, even though there is only
one implementation of each function.

This patch removes the reset_phy abstraction in favor of calling
pch_gbe_phy_hw_reset directly.

Signed-off-by: Paul Burton 
---

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h  |  2 --
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c  | 16 
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h  |  1 -
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c |  4 ++--
 4 files changed, 2 insertions(+), 21 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index 47ee7428c3d3..02e8da2b6ad2 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -334,14 +334,12 @@ struct pch_gbe_hw;
  * @init_hw:   for pch_gbe_hal_init_hw
  * @read_phy_reg:  for pch_gbe_hal_read_phy_reg
  * @write_phy_reg: for pch_gbe_hal_write_phy_reg
- * @reset_phy: for pch_gbe_hal_phy_hw_reset
  */
 struct pch_gbe_functions {
void (*get_bus_info) (struct pch_gbe_hw *);
s32 (*init_hw) (struct pch_gbe_hw *);
s32 (*read_phy_reg) (struct pch_gbe_hw *, u32, u16 *);
s32 (*write_phy_reg) (struct pch_gbe_hw *, u32, u16);
-   void (*reset_phy) (struct pch_gbe_hw *);
 };
 
 /**
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
index e1ecfb076029..6fe09af545e8 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
@@ -88,7 +88,6 @@ static const struct pch_gbe_functions pch_gbe_ops = {
.init_hw   = pch_gbe_plat_init_hw,
.read_phy_reg  = pch_gbe_phy_read_reg_miic,
.write_phy_reg = pch_gbe_phy_write_reg_miic,
-   .reset_phy = pch_gbe_phy_hw_reset,
 };
 
 /**
@@ -188,18 +187,3 @@ s32 pch_gbe_hal_write_phy_reg(struct pch_gbe_hw *hw, u32 
offset,
return 0;
return hw->func->write_phy_reg(hw, offset, data);
 }
-
-/**
- * pch_gbe_hal_phy_hw_reset - Hard PHY reset
- * @hw:Pointer to the HW structure
- */
-void pch_gbe_hal_phy_hw_reset(struct pch_gbe_hw *hw)
-{
-   if (!hw->func->reset_phy) {
-   struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
-
-   netdev_err(adapter->netdev, "ERROR: configuration\n");
-   return;
-   }
-   hw->func->reset_phy(hw);
-}
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
index aa802f670055..96540f6648b5 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
@@ -26,6 +26,5 @@ void pch_gbe_hal_get_bus_info(struct pch_gbe_hw *hw);
 s32 pch_gbe_hal_init_hw(struct pch_gbe_hw *hw);
 s32 pch_gbe_hal_read_phy_reg(struct pch_gbe_hw *hw, u32 offset, u16 *data);
 s32 pch_gbe_hal_write_phy_reg(struct pch_gbe_hw *hw, u32 offset, u16 data);
-void pch_gbe_hal_phy_hw_reset(struct pch_gbe_hw *hw);
 
 #endif
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index fc5079fa01e8..175d6608bdb9 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -2538,7 +2538,7 @@ static void pch_gbe_remove(struct pci_dev *pdev)
cancel_work_sync(>reset_task);
unregister_netdev(netdev);
 
-   pch_gbe_hal_phy_hw_reset(>hw);
+   pch_gbe_phy_hw_reset(>hw);
 
free_netdev(netdev);
 }
@@ -2674,7 +2674,7 @@ static int pch_gbe_probe(struct pci_dev *pdev,
return 0;
 
 err_free_adapter:
-   pch_gbe_hal_phy_hw_reset(>hw);
+   pch_gbe_phy_hw_reset(>hw);
 err_free_netdev:
free_netdev(netdev);
return ret;
-- 
2.17.1

[PATCH 01/14] net: pch_gbe: Remove unused copybreak parameter

[Paul Burton]

The pch_gbe driver includes a 'copybreak' parameter which appears to
have been copied from the e1000e driver but is entirely unused. Remove
the dead code.

Signed-off-by: Paul Burton 
---

 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c  | 15 ---
 1 file changed, 15 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 34a1581eda95..044a7561752c 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -34,7 +34,6 @@ const char pch_driver_version[] = DRV_VERSION;
 #define PCH_GBE_DMA_ALIGN  0
 #define PCH_GBE_DMA_PADDING2
 #define PCH_GBE_WATCHDOG_PERIOD(5 * HZ)/* watchdog 
time */
-#define PCH_GBE_COPYBREAK_DEFAULT  256
 #define PCH_GBE_PCI_BAR1
 #define PCH_GBE_RESERVE_MEMORY 0x20/* 2MB */
 
@@ -113,8 +112,6 @@ const char pch_driver_version[] = DRV_VERSION;
 
 #define MINNOW_PHY_RESET_GPIO  13
 
-static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
-
 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
   int data);
@@ -2784,14 +2781,6 @@ static int __init pch_gbe_init_module(void)
 
pr_info("EG20T PCH Gigabit Ethernet Driver - version %s\n",DRV_VERSION);
ret = pci_register_driver(_gbe_driver);
-   if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
-   if (copybreak == 0) {
-   pr_info("copybreak disabled\n");
-   } else {
-   pr_info("copybreak enabled for packets <= %u bytes\n",
-   copybreak);
-   }
-   }
return ret;
 }
 
@@ -2809,8 +2798,4 @@ MODULE_LICENSE("GPL");
 MODULE_VERSION(DRV_VERSION);
 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
 
-module_param(copybreak, uint, 0644);
-MODULE_PARM_DESC(copybreak,
-   "Maximum size of packet that is copied to a new buffer on receive");
-
 /* pch_gbe_main.c */
-- 
2.17.1

[PATCH 00/14] net: pch_gbe: Cleanups

[Paul Burton]

This series begins the process of cleaning up the pch_gbe network
driver. Whilst my ultimate goal is to add support for using this driver
on the MIPS Boston development board, this series sets that aside in
favor of making some more general cleanups. My hope is that this will
both make the driver a little more maleable & reduce the probability of
me gouging out my eyes.

Applies cleanly atop net-next as of 5424ea27390f ("netns: get more
entropy from net_hash_mix()").

Thanks,
    Paul

Paul Burton (14):
  net: pch_gbe: Remove unused copybreak parameter
  net: pch_gbe: Remove power_{up,down}_phy HAL abstraction
  net: pch_gbe: Remove read_mac_addr HAL abstraction
  net: pch_gbe: Remove sw_reset_phy HAL abstraction
  net: pch_gbe: Remove reset_phy HAL abstraction
  net: pch_gbe: Remove {read,write}_phy_reg HAL abstraction
  net: pch_gbe: Remove init_hw HAL abstraction
  net: pch_gbe: Remove get_bus_info HAL abstraction
  net: pch_gbe: Remove pch_gbe_hal_setup_init_funcs
  net: pch_gbe: Remove PCH_GBE_MAC_IFOP_RGMII define
  net: pch_gbe: Remove dead RINGFREE code
  net: pch_gbe: Use module_pci_driver()
  net: pch_gbe: Inline pch_gbe_mac_mc_addr_list_update
  net: pch_gbe: Clean up pch_gbe_set_multi

 .../net/ethernet/oki-semi/pch_gbe/Makefile|   2 +-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe.h   |  40 ---
 .../ethernet/oki-semi/pch_gbe/pch_gbe_api.c   | 262 --
 .../ethernet/oki-semi/pch_gbe/pch_gbe_api.h   |  35 ---
 .../oki-semi/pch_gbe/pch_gbe_ethtool.c|  19 +-
 .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c  | 193 -
 .../ethernet/oki-semi/pch_gbe/pch_gbe_phy.c   |   2 +-
 .../ethernet/oki-semi/pch_gbe/pch_gbe_phy.h   |   2 -
 8 files changed, 66 insertions(+), 489 deletions(-)
 delete mode 100644 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
 delete mode 100644 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h

-- 
2.17.1

[PATCH 06/14] net: pch_gbe: Remove {read,write}_phy_reg HAL abstraction

[Paul Burton]

For some reason the pch_gbe driver contains a struct pch_gbe_functions
with pointers used by a HAL abstraction layer, even though there is only
one implementation of each function.

This patch removes the read_phy_reg & write_phy_reg abstractions in
favor of calling pch_gbe_phy_read_reg_miic & pch_gbe_phy_write_reg_miic
directly.

Signed-off-by: Paul Burton 
---

 .../net/ethernet/oki-semi/pch_gbe/pch_gbe.h   |  4 ---
 .../ethernet/oki-semi/pch_gbe/pch_gbe_api.c   | 36 ---
 .../ethernet/oki-semi/pch_gbe/pch_gbe_api.h   |  2 --
 .../oki-semi/pch_gbe/pch_gbe_ethtool.c|  4 +--
 4 files changed, 2 insertions(+), 44 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index 02e8da2b6ad2..728e876bffc6 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -332,14 +332,10 @@ struct pch_gbe_hw;
  * struct  pch_gbe_functions - HAL APi function pointer
  * @get_bus_info:  for pch_gbe_hal_get_bus_info
  * @init_hw:   for pch_gbe_hal_init_hw
- * @read_phy_reg:  for pch_gbe_hal_read_phy_reg
- * @write_phy_reg: for pch_gbe_hal_write_phy_reg
  */
 struct pch_gbe_functions {
void (*get_bus_info) (struct pch_gbe_hw *);
s32 (*init_hw) (struct pch_gbe_hw *);
-   s32 (*read_phy_reg) (struct pch_gbe_hw *, u32, u16 *);
-   s32 (*write_phy_reg) (struct pch_gbe_hw *, u32, u16);
 };
 
 /**
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
index 6fe09af545e8..484be4225352 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c
@@ -86,8 +86,6 @@ static s32 pch_gbe_plat_init_hw(struct pch_gbe_hw *hw)
 static const struct pch_gbe_functions pch_gbe_ops = {
.get_bus_info  = pch_gbe_plat_get_bus_info,
.init_hw   = pch_gbe_plat_init_hw,
-   .read_phy_reg  = pch_gbe_phy_read_reg_miic,
-   .write_phy_reg = pch_gbe_phy_write_reg_miic,
 };
 
 /**
@@ -153,37 +151,3 @@ s32 pch_gbe_hal_init_hw(struct pch_gbe_hw *hw)
}
return hw->func->init_hw(hw);
 }
-
-/**
- * pch_gbe_hal_read_phy_reg - Reads PHY register
- * @hw:Pointer to the HW structure
- * @offset: The register to read
- * @data:   The buffer to store the 16-bit read.
- * Returns:
- * 0:  Successfully
- * Negative value: Failed
- */
-s32 pch_gbe_hal_read_phy_reg(struct pch_gbe_hw *hw, u32 offset,
-   u16 *data)
-{
-   if (!hw->func->read_phy_reg)
-   return 0;
-   return hw->func->read_phy_reg(hw, offset, data);
-}
-
-/**
- * pch_gbe_hal_write_phy_reg - Writes PHY register
- * @hw:Pointer to the HW structure
- * @offset: The register to read
- * @data:   The value to write.
- * Returns:
- * 0:  Successfully
- * Negative value: Failed
- */
-s32 pch_gbe_hal_write_phy_reg(struct pch_gbe_hw *hw, u32 offset,
-   u16 data)
-{
-   if (!hw->func->write_phy_reg)
-   return 0;
-   return hw->func->write_phy_reg(hw, offset, data);
-}
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
index 96540f6648b5..9cd19605f4ff 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h
@@ -24,7 +24,5 @@
 s32 pch_gbe_hal_setup_init_funcs(struct pch_gbe_hw *hw);
 void pch_gbe_hal_get_bus_info(struct pch_gbe_hw *hw);
 s32 pch_gbe_hal_init_hw(struct pch_gbe_hw *hw);
-s32 pch_gbe_hal_read_phy_reg(struct pch_gbe_hw *hw, u32 offset, u16 *data);
-s32 pch_gbe_hal_write_phy_reg(struct pch_gbe_hw *hw, u32 offset, u16 data);
 
 #endif
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c
index 731ce1e419e4..da39d771ad87 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c
@@ -125,7 +125,7 @@ static int pch_gbe_set_link_ksettings(struct net_device 
*netdev,
u32 advertising;
int ret;
 
-   pch_gbe_hal_write_phy_reg(hw, MII_BMCR, BMCR_RESET);
+   pch_gbe_phy_write_reg_miic(hw, MII_BMCR, BMCR_RESET);
 
memcpy(_ecmd, ecmd, sizeof(*ecmd));
 
@@ -204,7 +204,7 @@ static void pch_gbe_get_regs(struct net_device *netdev,
*regs_buff++ = ioread32(>reg->INT_ST + i);
/* PHY register */
for (i = 0; i < PCH_GBE_PHY_REGS_LEN; i++) {
-   pch_gbe_hal_read_phy_reg(>hw, i, );
+   pch_gbe_phy_read_reg_miic(>hw, i, );
*regs_buff++ = tmp;
}
 }
-- 
2.17.1

Re: [PATCH v6 1/6] net: phy: at803x: Export at803x_debug_reg_mask()

[Paul Burton]

Hi Andrew,

On Fri, May 11, 2018 at 09:24:46PM +0200, Andrew Lunn wrote:
> > I could reorder the probe function a little to initialize the PHY before
> > performing the MAC reset, drop this patch and the AR803X hibernation
> > stuff from patch 2 if you like. But again, I can't actually test the
> > result on the affected hardware.
> 
> Hi Paul
> 
> I don't like a MAC driver poking around in PHY registers.
> 
> So if you can rearrange the code, that would be great.
> 
>Thanks
>   Andrew

Sure, I'll give it a shot.

After digging into it I see 2 ways to go here:

  1) We could just always reset the PHY before we reset the MAC. That
 would give us a window of however long the PHY takes to enter its
 low power state & stop providing the RX clock during which we'd
 need the MAC reset to complete. In the case of the AR8031 that's
 "about 10 seconds" according to its data sheet. In this particular
 case that feels like plenty, but it does also feel a bit icky to
 rely on the timing chosen by the PHY manufacturer to line up with
 that of the MAC reset.

  2) We could introduce a couple of new phy_* functions to disable &
 enable low power states like the AR8031's hibernation feature, by
 calling new function pointers in struct phy_driver. Then pch_gbe &
 other MACs could call those to have the PHY driver disable
 hibernation at times where we know we'll need the RX clock and
 re-enable it afterwards.

I'm currently leaning towards option 2. How does that sound to you? Or
can you see another way to handle this?

Thanks,
Paul

Re: [PATCH v6 1/6] net: phy: at803x: Export at803x_debug_reg_mask()

[Paul Burton]

On Fri, May 11, 2018 at 11:25:02AM -0700, Paul Burton wrote:
> Hi Andrew,
> 
> On Fri, May 11, 2018 at 02:26:19AM +0200, Andrew Lunn wrote:
> > On Thu, May 10, 2018 at 04:16:52PM -0700, Paul Burton wrote:
> > > From: Andrew Lunn <and...@lunn.ch>
> > > 
> > > On some boards, this PHY has a problem when it hibernates. Export this
> > > function to a board can register a PHY fixup to disable hibernation.
> > 
> > What do you know about the problem?
> > 
> > https://patchwork.ozlabs.org/patch/686371/
> > 
> > I don't remember how it was solved, but you should probably do the
> > same.
> > 
> > Andrew
> 
> I'm afraid I don't know much about the problem - this one is your patch
> entirely unchanged, and I don't have access to the hardware in question
> (my board uses a Realtek RTL8211E PHY).
> 
> I presume you did this because the pch_gbe driver as-is in mainline
> disables hibernation for the AR803X PHY found on the MinnowBoard, so
> this would be preserving the existing behaviour of the driver?
> 
> That behaviour was introduced by commit f1a26fdf5944f ("pch_gbe: Add
> MinnowBoard support"), so perhaps Darren as its author might know more?
> 
> My presumption would be that this is done to ensure that the PHY is
> always providing the RX clock, which the EG20T manual says is required
> for the MAC reset register RX_RST & ALL_RST bits to clear. We wait for
> those using the call to pch_gbe_wait_clr_bit() in
> pch_gbe_mac_reset_hw(), which happens before we initialize the PHY.
> 
> I could reorder the probe function a little to initialize the PHY before
> performing the MAC reset, drop this patch and the AR803X hibernation
> stuff from patch 2 if you like. But again, I can't actually test the
> result on the affected hardware.
> 
> Thanks,
> Paul

I got an undeliverable response using Darren's email address from the
commit referenced above, so updating to the latest address I see for him
in git history.

Thanks,
Paul

Re: [PATCH v6 1/6] net: phy: at803x: Export at803x_debug_reg_mask()

[Paul Burton]

Hi Andrew,

On Fri, May 11, 2018 at 02:26:19AM +0200, Andrew Lunn wrote:
> On Thu, May 10, 2018 at 04:16:52PM -0700, Paul Burton wrote:
> > From: Andrew Lunn <and...@lunn.ch>
> > 
> > On some boards, this PHY has a problem when it hibernates. Export this
> > function to a board can register a PHY fixup to disable hibernation.
> 
> What do you know about the problem?
> 
> https://patchwork.ozlabs.org/patch/686371/
> 
> I don't remember how it was solved, but you should probably do the
> same.
> 
>   Andrew

I'm afraid I don't know much about the problem - this one is your patch
entirely unchanged, and I don't have access to the hardware in question
(my board uses a Realtek RTL8211E PHY).

I presume you did this because the pch_gbe driver as-is in mainline
disables hibernation for the AR803X PHY found on the MinnowBoard, so
this would be preserving the existing behaviour of the driver?

That behaviour was introduced by commit f1a26fdf5944f ("pch_gbe: Add
MinnowBoard support"), so perhaps Darren as its author might know more?

My presumption would be that this is done to ensure that the PHY is
always providing the RX clock, which the EG20T manual says is required
for the MAC reset register RX_RST & ALL_RST bits to clear. We wait for
those using the call to pch_gbe_wait_clr_bit() in
pch_gbe_mac_reset_hw(), which happens before we initialize the PHY.

I could reorder the probe function a little to initialize the PHY before
performing the MAC reset, drop this patch and the AR803X hibernation
stuff from patch 2 if you like. But again, I can't actually test the
result on the affected hardware.

Thanks,
Paul

[PATCH v6 6/6] MIPS: Boston: Adjust DT for pch_gbe PHY support

[Paul Burton]

The pch_gbe driver support for PHY reset GPIOs is now provided by the
standard phylib infrastructure, using a standard PHY binding. Adjust the
Boston devicetree to make use of the standard PHY binding.

This is possible because we bundle the DT along with the kernel binary
into a Flattened Image Tree, so the DT and kernel are always shipped
together for the Boston platform.

Signed-off-by: Paul Burton <paul.bur...@mips.com>
Cc: Andrew Lunn <and...@lunn.ch>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v6:
- New patch.

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/mips/boot/dts/img/boston.dts | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/mips/boot/dts/img/boston.dts 
b/arch/mips/boot/dts/img/boston.dts
index 65af3f6ba81c..cb55f7ba20c3 100644
--- a/arch/mips/boot/dts/img/boston.dts
+++ b/arch/mips/boot/dts/img/boston.dts
@@ -144,8 +144,17 @@
eg20t_mac@2,0,1 {
compatible = "pci8086,8802";
reg = <0x00020100 0 0 0 0>;
-   phy-reset-gpios = <_gpio 6
-  GPIO_ACTIVE_LOW>;
+
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ethernet-phy@0 {
+   compatible = 
"ethernet-phy-id001c.c915";
+   reg = <0>;
+   reset-gpios = <_gpio 6 
GPIO_ACTIVE_LOW>;
+   reset-assert-us = <25000>;
+   reset-deassert-us = <25000>;
+   };
};
 
eg20t_gpio: eg20t_gpio@2,0,2 {
-- 
2.17.0

[PATCH v6 5/6] net: pch_gbe: Allow build on MIPS platforms

[Paul Burton]

Allow the pch_gbe driver to be built on MIPS platforms, allowing its use
on the MIPS Boston development board.

Signed-off-by: Paul Burton <paul.bur...@mips.com>
Cc: Andrew Lunn <and...@lunn.ch>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v6:
- None.

Changes in v5:
- None.

Changes in v4:
- None.

Changes in v3:
- None.

Changes in v2:
- None.

 drivers/net/ethernet/oki-semi/pch_gbe/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig 
b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
index 045256e99586..bf85c44fb7e5 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
@@ -4,7 +4,7 @@
 
 config PCH_GBE
tristate "OKI SEMICONDUCTOR IOH(ML7223/ML7831) GbE"
-   depends on PCI && (X86_32 || COMPILE_TEST)
+   depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
select PTP_1588_CLOCK_PCH
select NET_PTP_CLASSIFY
select AT803X_PHY
-- 
2.17.0

[PATCH v6 4/6] ptp: pch: Allow build on MIPS platforms

[Paul Burton]

Allow the ptp_pch driver to be built on MIPS platforms in preparation
for use on the MIPS Boston board.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
Acked-by: Richard Cochran <richardcoch...@gmail.com>
Cc: Andrew Lunn <and...@lunn.ch>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

Signed-off-by: Paul Burton <paul.bur...@mips.com>
---

Changes in v6: None
Changes in v5:
- Newly included in this series to satisfy Kconfig.

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/ptp/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index a21ad10d613c..8618982ab96a 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -90,7 +90,7 @@ config DP83640_PHY
 
 config PTP_1588_CLOCK_PCH
tristate "Intel PCH EG20T as PTP clock"
-   depends on X86_32 || COMPILE_TEST
+   depends on X86_32 || MIPS || COMPILE_TEST
depends on HAS_IOMEM && NET
imply PTP_1588_CLOCK
help
-- 
2.17.0

[PATCH v6 3/6] net: pch_gbe: Support DeviceTree for MDIO/PHY description

[Paul Burton]

When running on a system which uses device tree, use
of_mdiobus_register() rather than plain mdiobus_register() in order to
support parsing PHY information from the DT.

On systems without CONFIG_OF_MDIO set of_mdiobus_register() falls back
to mdiobus_register() anyway, but here we check for a non-NULL device
node in order to continue functioning as-is if a system has
CONFIG_OF_MDIO=y but doesn't use the devicetree.

Signed-off-by: Paul Burton <paul.bur...@mips.com>
Cc: Andrew Lunn <and...@lunn.ch>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v6:
- New patch, significantly simplified by Andrew's preceding patches.

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index b20ed110cdef..f491044c2739 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -25,6 +25,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define DRV_VERSION "1.01"
 const char pch_driver_version[] = DRV_VERSION;
@@ -829,6 +830,9 @@ static int pch_gbe_init_mdio(struct pch_gbe_adapter 
*adapter)
 
adapter->mdiobus = bus;
 
+   if (dev->of_node)
+   return of_mdiobus_register(bus, dev->of_node);
+
return mdiobus_register(bus);
 }
 
-- 
2.17.0

[PATCH v6 1/6] net: phy: at803x: Export at803x_debug_reg_mask()

[Paul Burton]

From: Andrew Lunn <and...@lunn.ch>

On some boards, this PHY has a problem when it hibernates. Export this
function to a board can register a PHY fixup to disable hibernation.

Signed-off-by: Andrew Lunn <and...@lunn.ch>
Signed-off-by: Paul Burton <paul.bur...@mips.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v6:
- New patch.

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/net/phy/at803x.c   |  5 +++--
 include/linux/at803x_phy.h | 16 
 2 files changed, 19 insertions(+), 2 deletions(-)
 create mode 100644 include/linux/at803x_phy.h

diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index 411cf1072bae..5aede5708abf 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define AT803X_INTR_ENABLE 0x12
 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15)
@@ -93,8 +94,8 @@ static int at803x_debug_reg_read(struct phy_device *phydev, 
u16 reg)
return phy_read(phydev, AT803X_DEBUG_DATA);
 }
 
-static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
-u16 clear, u16 set)
+int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
+ u16 clear, u16 set)
 {
u16 val;
int ret;
diff --git a/include/linux/at803x_phy.h b/include/linux/at803x_phy.h
new file mode 100644
index ..2460c17d56ec
--- /dev/null
+++ b/include/linux/at803x_phy.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _AT803X_PHY_H
+#define _PHY_AT803X_PHY
+
+#define ATH8030_PHY_ID 0x004dd076
+#define ATH8031_PHY_ID 0x004dd074
+#define ATH8035_PHY_ID 0x004dd072
+#define AT803X_PHY_ID_MASK 0xffef
+
+#define AT8031_HIBERNATE   0x0B
+#define AT8031_PS_HIB_EN   0x8000 /* Hibernate enable */
+
+int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
+ u16 clear, u16 set);
+
+#endif /* _AT803X_PHY_H */
-- 
2.17.0

[PATCH v6 2/6] net: ethernet: pch_gbe: Convert to mdiobus and phylib

[Paul Burton]

From: Andrew Lunn <and...@lunn.ch>

Convert this driver to use the mdio bus and phylib infrastructure.  It
will then use the common AT803X PHY driver, rather than use its own
code. Have the shared code also handle the GPIO used to reset the PHY.
To implement disabling PHY hibernation, which appears to cause issues
on the minnow board, add a PHY fixup.

Over all, these changes should make it easier to use other PHYs with
the MAC chip, and reduces the lines of code.

[paul.bur...@mips.com:
  - Select CONFIG_PHYLIB.
  - Drop selection of CONFIG_MII.
  - Restore the define of PCH_GBE_MAC_IFOP_RGMII.
  - Add GPIOF_ACTIVE_LOW to the minnow PHY reset GPIO flags.]

Signed-off-by: Andrew Lunn <and...@lunn.ch>
Signed-off-by: Paul Burton <paul.bur...@mips.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v6:
- New patch.

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/Kconfig |   3 +-
 .../net/ethernet/oki-semi/pch_gbe/Makefile|   2 +-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe.h   |  35 +-
 .../ethernet/oki-semi/pch_gbe/pch_gbe_api.c   | 118 --
 .../ethernet/oki-semi/pch_gbe/pch_gbe_api.h   |   8 +-
 .../oki-semi/pch_gbe/pch_gbe_ethtool.c|  89 +
 .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c  | 378 +-
 .../ethernet/oki-semi/pch_gbe/pch_gbe_param.c | 265 
 .../ethernet/oki-semi/pch_gbe/pch_gbe_phy.c   | 377 -
 .../ethernet/oki-semi/pch_gbe/pch_gbe_phy.h   |  37 --
 10 files changed, 213 insertions(+), 1099 deletions(-)
 delete mode 100644 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c
 delete mode 100644 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig 
b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
index 5f7a35212796..045256e99586 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
@@ -5,9 +5,10 @@
 config PCH_GBE
tristate "OKI SEMICONDUCTOR IOH(ML7223/ML7831) GbE"
depends on PCI && (X86_32 || COMPILE_TEST)
-   select MII
select PTP_1588_CLOCK_PCH
select NET_PTP_CLASSIFY
+   select AT803X_PHY
+   select PHYLIB
---help---
  This is a gigabit ethernet driver for EG20T PCH.
  EG20T PCH is the platform controller hub that is used in Intel's
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/Makefile 
b/drivers/net/ethernet/oki-semi/pch_gbe/Makefile
index 31288d4ad248..163ddda97bd1 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/Makefile
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/Makefile
@@ -1,4 +1,4 @@
 obj-$(CONFIG_PCH_GBE) += pch_gbe.o
 
-pch_gbe-y := pch_gbe_phy.o pch_gbe_ethtool.o pch_gbe_param.o
+pch_gbe-y := pch_gbe_ethtool.o pch_gbe_param.o
 pch_gbe-y += pch_gbe_api.o pch_gbe_main.o
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index 697e29dd4bd3..055cf9a2b418 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -22,7 +22,8 @@
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
-#include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -332,23 +333,11 @@ struct pch_gbe_hw;
  * struct  pch_gbe_functions - HAL APi function pointer
  * @get_bus_info:  for pch_gbe_hal_get_bus_info
  * @init_hw:   for pch_gbe_hal_init_hw
- * @read_phy_reg:  for pch_gbe_hal_read_phy_reg
- * @write_phy_reg: for pch_gbe_hal_write_phy_reg
- * @reset_phy: for pch_gbe_hal_phy_hw_reset
- * @sw_reset_phy:  for pch_gbe_hal_phy_sw_reset
- * @power_up_phy:  for pch_gbe_hal_power_up_phy
- * @power_down_phy:for pch_gbe_hal_power_down_phy
  * @read_mac_addr: for pch_gbe_hal_read_mac_addr
  */
 struct pch_gbe_functions {
void (*get_bus_info) (struct pch_gbe_hw *);
s32 (*init_hw) (struct pch_gbe_hw *);
-   s32 (*read_phy_reg) (struct pch_gbe_hw *, u32, u16 *);
-   s32 (*write_phy_reg) (struct pch_gbe_hw *, u32, u16);
-   void (*reset_phy) (struct pch_gbe_hw *);
-   void (*sw_reset_phy) (struct pch_gbe_hw *);
-   void (*power_up_phy) (struct pch_gbe_hw *hw);
-   void (*power_down_phy) (struct pch_gbe_hw *hw);
s32 (*read_mac_addr) (struct pch_gbe_hw *);
 };
 
@@ -378,18 +367,10 @@ struct pch_gbe_mac_info {
 
 /**
  * struct pch_gbe_phy_info - PHY information
- * @addr:  PHY address
- * @id:PHY's identifier
- * @revision:  PHY's revision
  * @reset_delay_us:HW reset delay time[us]
- * @autoneg_advertised:Autoneg advertised
  */
 struct pch_gbe_phy_info {
-   u32 addr;
-   u32 id;
-   u32 revision;
u32 reset_delay_us;
-   u16 autoneg_advertised;
 };
 
 /*!
@@ -578,6 +559,8 @@ struct pch_gbe_hw_sta

[PATCH v6 0/6] net: pch_gbe: MIPS support

[Paul Burton]

The Intel EG20T Platform Controller Hub is used on the MIPS Boston
development board to provide various peripherals including ethernet.

This series migrates the pch_gbe driver's PHY support to use phylib,
implements support for device tree which we use to provide the PHY reset
GPIO, and allows the driver to be built for MIPS.

Applies atop v4.17-rc4.

Please note that I don't have access to the Intel systems (eg.
MinnowBoard v1) that make use of this driver, so am unable to test on
those. If anyone with such a system could test the series that would be
much appreciated.

v6 of the series is later than I'd hoped, but we had a product
release[1] that kept me busy. My apologies!

The series is significantly different to earlier versions - Andrew did
the legwork of converting to phylib and that simplified things
significantly. v5 contained further fixes to the driver which I've
removed from v6 such that this series is just enough to get the driver
running on the MIPS Boston platform, despite a few bugs in the interest
of a simpler & more focused patch series. I'll submit those fixes
separately.

Thanks,
Paul

[1] 
https://www.mips.com/press/new-mips-i7200-processor-core-delivers-unmatched-performance-and-efficiency-for-advanced-lte5g-communications-and-networking-ic-designs/

Andrew Lunn (2):
  net: phy: at803x: Export at803x_debug_reg_mask()
  net: ethernet: pch_gbe: Convert to mdiobus and phylib

Paul Burton (4):
  net: pch_gbe: Support DeviceTree for MDIO/PHY description
  ptp: pch: Allow build on MIPS platforms
  net: pch_gbe: Allow build on MIPS platforms
  MIPS: Boston: Adjust DT for pch_gbe PHY support

 arch/mips/boot/dts/img/boston.dts |  13 +-
 drivers/net/ethernet/oki-semi/pch_gbe/Kconfig |   5 +-
 .../net/ethernet/oki-semi/pch_gbe/Makefile|   2 +-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe.h   |  35 +-
 .../ethernet/oki-semi/pch_gbe/pch_gbe_api.c   | 118 --
 .../ethernet/oki-semi/pch_gbe/pch_gbe_api.h   |   8 +-
 .../oki-semi/pch_gbe/pch_gbe_ethtool.c|  89 +---
 .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c  | 382 +-
 .../ethernet/oki-semi/pch_gbe/pch_gbe_param.c | 265 
 .../ethernet/oki-semi/pch_gbe/pch_gbe_phy.c   | 377 -
 .../ethernet/oki-semi/pch_gbe/pch_gbe_phy.h   |  37 --
 drivers/net/phy/at803x.c  |   5 +-
 drivers/ptp/Kconfig   |   2 +-
 include/linux/at803x_phy.h|  16 +
 14 files changed, 249 insertions(+), 1105 deletions(-)
 delete mode 100644 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c
 delete mode 100644 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h
 create mode 100644 include/linux/at803x_phy.h

-- 
2.17.0

Re: [PATCH net-next RFC 0/2] Convert OKI PCH GBE to mdiobus and phylib

[Paul Burton]

Hi Andrew,

On Tue, Feb 20, 2018 at 03:28:17AM +0100, Andrew Lunn wrote:
> Hi Paul
> 
> Here is my stab at converting the OKI PCH GBE to use the common MDIO
> bus and phylib drivers. This is compile tested only, and pretty much
> guaranteed to be broken. But hopefully it will help you. Feel free to
> pick it up and make it work. Without hardware, there is not much more
> i can do, other than answer questions.

Thanks - this will be useful :) I'll try to find some time to get it
running this week.

> The handling of the GPIO for reset is possibly wrong.
> 
> 1) It is probably active high, when active low is wanted. Your patch
>would sort this out.
> 
> 2) It is possible the reset happens too late. Since there is no device
>tree binding for the minnow board, it is not possible to register
>the gpio with the core code until after it has been probed and
>attached to the MAC. If the PHY is being held in reset, it might
>not respond to the bus scan, and hence we fail to find it.  If that
>is true, we need a different solution.

Note that unfortunately I don't have access to the Minnow platform which
the driver as-is currently supports, so I won't be able to observe any
Minnow-specific issues either.

Thanks,
Paul

> Andrew Lunn (2):
>   net: phy: at803x: Export at803x_debug_reg_mask()
>   net: ethernet: pch_gbe: Convert to mdiobus and phylib
> 
>  drivers/net/ethernet/oki-semi/pch_gbe/Kconfig  |   1 +
>  drivers/net/ethernet/oki-semi/pch_gbe/Makefile |   2 +-
>  drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h|  35 +-
>  .../net/ethernet/oki-semi/pch_gbe/pch_gbe_api.c| 118 ---
>  .../net/ethernet/oki-semi/pch_gbe/pch_gbe_api.h|   8 +-
>  .../ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c|  89 +
>  .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 373 ++--
>  .../net/ethernet/oki-semi/pch_gbe/pch_gbe_param.c  | 265 ---
>  .../net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c| 377 
> -
>  .../net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h|  37 --
>  drivers/net/phy/at803x.c   |   5 +-
>  include/linux/at803x_phy.h |  16 +
>  12 files changed, 227 insertions(+), 1099 deletions(-)
>  delete mode 100644 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c
>  delete mode 100644 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h
>  create mode 100644 include/linux/at803x_phy.h
> 
> -- 
> 2.16.1
> 

Re: [PATCH v5 07/14] net: pch_gbe: Fix handling of TX padding

[Paul Burton]

Hi David,

On Mon, Feb 19, 2018 at 02:01:25PM +, David Laight wrote:
> From: Paul Burton
> > Sent: 17 February 2018 20:11
> > 
> > The ethernet controller found in the Intel EG20T Platform Controller
> > Hub requires that we place 2 bytes of padding between the ethernet
> > header & the packet payload. Our pch_gbe driver handles this by copying
> > packets to be transmitted to a temporary struct skb with the padding
> > bytes inserted
> ...
> 
> Uggg WFT is the driver doing that for?
> 
> I'd guess that the two byte pad is there so that a 4 byte aligned
> frame is still 4 byte aligned when the 14 byte ethernet header is added.
> So instead of copying the entire frame the MAC header should be built
> (or rebuilt?) two bytes further from the actual data.

I agree - the pch_gbe driver is pretty bad and does a lot of things
wrong. Frankly I'm amazed it's in tree, but it is & one patch series
isn't going to fix all of its shortcomings.

So whilst I totally agree that copying around the whole frame is awful,
it's a separate problem to the length used for DMA mapping being
incorrect which is what this patch addresses & I'd rather not start
adding more & more fixes or cleanups into this initial series before the
driver is even functional on my hardware.

Thanks,
Paul

Re: [PATCH v5 00/14] net: pch_gbe: Fixes & MIPS support

[Paul Burton]

Hi Andrew,

On Sun, Feb 18, 2018 at 06:56:07PM +0100, Andrew Lunn wrote:
> On Sun, Feb 18, 2018 at 09:03:10AM -0800, Paul Burton wrote:
> > Hi David,
> > 
> > On Sun, Feb 18, 2018 at 10:31:12AM -0500, David Miller wrote:
> > > Nobody is going to see and apply these patches if you don't CC: the
> > > Linux networking development list, netdev@vger.kernel.org
> > 
> > You're replying to mail that was "To: netdev@vger.kernel.org" and I see
> > the whole series in the archives[1] so it definitely reached the list.
> > 
> > I'm not sure I see the problem?
> 
> Hi Paul
> 
> I'm guess that David is wondering about version 1-4 of this patchset?
> As far as i can see, they were sent to the mips list, not the netdev
> list.

It has been quite a while since v4, but it and earlier revisions were
submitted to the netdev list too:

v4: https://www.spinics.net/lists/netdev/msg438550.html
v3: https://www.spinics.net/lists/netdev/msg438313.html
v2: https://marc.info/?l=linux-netdev=145450117711515=2

v1 was part of a larger series, but netdev was also copied on the
relevant patches starting here & the patches following it:

v1: https://marc.info/?l=linux-netdev=144890083511222=2

Thanks,
Paul

Re: [PATCH v5 00/14] net: pch_gbe: Fixes & MIPS support

[Paul Burton]

Hi David,

On Sun, Feb 18, 2018 at 10:31:12AM -0500, David Miller wrote:
> Nobody is going to see and apply these patches if you don't CC: the
> Linux networking development list, netdev@vger.kernel.org

You're replying to mail that was "To: netdev@vger.kernel.org" and I see
the whole series in the archives[1] so it definitely reached the list.

I'm not sure I see the problem?

Thanks,
Paul

[1] https://www.spinics.net/lists/netdev/msg484102.html

Re: [PATCH v5 02/14] net: pch_gbe: Pull PHY GPIO handling out of Minnow code

[Paul Burton]

Hi Andrew,

On Sun, Feb 18, 2018 at 12:34:42AM +0100, Andrew Lunn wrote:
> > Even if that is true, rewriting the driver's PHY handling would be a
> > very separate change to the changes this series make which allow this
> > driver to work on a platform besides the Minnowboard. The *only* thing
> > this series does relating to the PHY is allow the reset GPIO to be
> > handled properly - rewriting the existing PHY handling is beyond it's
> > scope.
> 
> Well, you are adding a device tree binding, which needs to be
> supported forever. This is going to make things messy in the future
> when you do such a cleanup that you follow the PHY binding, in that
> you have to handle both what you add here, and the official PHY
> binding.

Thank you - it's useful to know what your concern actually is.

> I would prefer that for the moment, you drop the PHY binding patches
> in this series. That is what i object to the most. Adding an MDIO
> driver and using the standard PHY driver for this PHY is all
> internal. You can change that anytime. But adding a binding means an
> ABI.

The problem is that the device in question doesn't actually work unless
we reset the PHY, so just removing the PHY reset GPIO handling would
break things.

How would you feel if I were to adjust the binding to match the standard
PHY binding, but internally leave the driver's PHY handling as-is for
now? That would:

  1) Allow for the pch_gbe driver to move towards more standard PHY
 handling in the future without DT changes.

  2) Be fairly straightforward to implement in this patchset - the code
 reading the DT would just follow the phandle to the PHY node to
 find the reset GPIO - thereby not holding up the rest of the series.

  3) Still function on our hardware.

Thanks,
Paul

Re: [PATCH v5 02/14] net: pch_gbe: Pull PHY GPIO handling out of Minnow code

[Paul Burton]

Hi Andrew,

On Sat, Feb 17, 2018 at 11:29:33PM +0100, Andrew Lunn wrote:
> On Sat, Feb 17, 2018 at 12:10:25PM -0800, Paul Burton wrote:
> > The MIPS Boston development board uses the Intel EG20T Platform
> > Controller Hub, including its gigabit ethernet controller, and requires
> > that its RTL8211E PHY be reset much like the Minnow platform. Pull the
> > PHY reset GPIO handling out of Minnow-specific code such that it can be
> > shared by later patches.
> 
> Hi Paul
> 
> I'm i right in saying the driver currently supports the Atheros AT8031
> PHY? The same phy which is supported in drivers/net/phy/at803x.c?

It looks like the driver does contain some code relating to that PHY,
but it's not the one I'm using with the MIPS Boston board - there we
have a Realtek RTL8211E (as mentioned in the commit message) which is
working fine alongside this pch_gbe driver too.

> If so, i think you are doing this all wrong.

Note that this is a driver which is already in mainline, and I didn't
write it. Claiming that *I* am doing this all wrong is a bit of a
stretch - all this patch does is make small changes to some existing
code, which only tangentially relates to a PHY driver, such that it
ceases to be specific to a single platform.

> You would be much better off throwing away pch_gbe_phy.c and write a
> proper MDIO driver. You then get the PHY driver for free, and the MDIO
> code could will handle your GPIO for you, in the standardised way.

Even if that is true, rewriting the driver's PHY handling would be a
very separate change to the changes this series make which allow this
driver to work on a platform besides the Minnowboard. The *only* thing
this series does relating to the PHY is allow the reset GPIO to be
handled properly - rewriting the existing PHY handling is beyond it's
scope.

Note that I do have various cleanups to the driver beyond this series
which I intend to submit after it is functional for my system[1], so I
am not saying that I don't care about improving the driver. But please,
let's do one thing at a time.

Thanks,
Paul

[1] 
https://git.linux-mips.org/cgit/paul/linux.git/log/?h=up417-boston-eth-cleanup

[PATCH v5 13/14] ptp: pch: Allow build on MIPS platforms

[Paul Burton]

Allow the ptp_pch driver to be built on MIPS platforms in preparation
for use on the MIPS Boston board.

Signed-off-by: Paul Burton <paul.bur...@mips.com>
Acked-by: Richard Cochran <richardcoch...@gmail.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v5:
- Newly included in this series to satisfy Kconfig.

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/ptp/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index a21ad10d613c..8618982ab96a 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -90,7 +90,7 @@ config DP83640_PHY
 
 config PTP_1588_CLOCK_PCH
tristate "Intel PCH EG20T as PTP clock"
-   depends on X86_32 || COMPILE_TEST
+   depends on X86_32 || MIPS || COMPILE_TEST
depends on HAS_IOMEM && NET
imply PTP_1588_CLOCK
help
-- 
2.16.1

[PATCH v5 11/14] net: pch_gbe: Ensure DMA is ordered with descriptor writes

[Paul Burton]

On weakly ordered systems writes to the RX or TX descriptors may be
reordered with the write to the DMA control register that enables DMA.
If this happens then the device may see descriptors in an intermediate
& invalid state, leading to incorrect behaviour. Add barriers to ensure
that DMA is enabled only after all writes to the descriptors.

Signed-off-by: Paul Burton <paul.bur...@mips.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v5:
- New patch.

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 4354842b9b7e..8e3ad7dcef0b 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -1260,6 +1260,9 @@ static void pch_gbe_tx_queue(struct pch_gbe_adapter 
*adapter,
tx_desc->tx_frame_ctrl = (frame_ctrl);
tx_desc->gbec_status = (DSC_INIT16);
 
+   /* Ensure writes to descriptors complete before DMA begins */
+   mmiowb();
+
if (unlikely(++ring_num == tx_ring->count))
ring_num = 0;
 
@@ -1961,6 +1964,9 @@ int pch_gbe_up(struct pch_gbe_adapter *adapter)
pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
adapter->tx_queue_len = netdev->tx_queue_len;
 
+   /* Ensure writes to descriptors complete before DMA begins */
+   mmiowb();
+
pch_gbe_enable_dma_tx(>hw);
pch_gbe_enable_dma_rx(>hw);
pch_gbe_enable_mac_rx(>hw);
-- 
2.16.1

[PATCH v5 07/14] net: pch_gbe: Fix handling of TX padding

[Paul Burton]

The ethernet controller found in the Intel EG20T Platform Controller
Hub requires that we place 2 bytes of padding between the ethernet
header & the packet payload. Our pch_gbe driver handles this by copying
packets to be transmitted to a temporary struct skb with the padding
bytes inserted, however it sets the length of this temporary skb to
equal that of the original, without the 2 padding bytes, and then uses
this length as that of the memory to map for DMA.

This is problematic on systems that don't have cache-coherent DMA, since
if the length of the original buffer is either a multiple of the
system's cache line size or one less than such a multiple then the size
we provide to dma_map_single() will not cover the last byte or two of
the data when rounded up to a cache line boundary. This may result in us
transmitting corrupt data in the last one or two bytes of the packet,
depending upon its length.

Fix this by setting the length of tmp_skb to include the 2 padding
bytes, which is actually the length of the data it holds. This is then
assigned to buffer_info->length & provided to dma_map_single() which
will operate on all of the data as desired. The EG20T datasheet
specifies that the padding bytes should not be included in the length
stored in the TX descriptor, so we switch that to use the length of the
original skb.

Whilst modifying this code we switch to using PCH_GBE_DMA_PADDING rather
than the magic number 2 to specify the size of the padding, making it
clearer what the code is doing, and fix a typo in the comment indicating
that padding is inserted.

Signed-off-by: Paul Burton <paul.bur...@mips.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 15 +++
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 77f7fbd98e8f..60e91c0fc98b 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -1223,13 +1223,12 @@ static void pch_gbe_tx_queue(struct pch_gbe_adapter 
*adapter,
buffer_info = _ring->buffer_info[ring_num];
tmp_skb = buffer_info->skb;
 
-   /* [Header:14][payload] ---> [Header:14][paddong:2][payload]*/
+   /* [Header:14][payload] ---> [Header:14][padding:2][payload] */
memcpy(tmp_skb->data, skb->data, ETH_HLEN);
-   tmp_skb->data[ETH_HLEN] = 0x00;
-   tmp_skb->data[ETH_HLEN + 1] = 0x00;
-   tmp_skb->len = skb->len;
-   memcpy(_skb->data[ETH_HLEN + 2], >data[ETH_HLEN],
-  (skb->len - ETH_HLEN));
+   memset(_skb->data[ETH_HLEN], 0, PCH_GBE_DMA_PADDING);
+   memcpy(_skb->data[ETH_HLEN + PCH_GBE_DMA_PADDING],
+  >data[ETH_HLEN], skb->len - ETH_HLEN);
+   tmp_skb->len = skb->len + PCH_GBE_DMA_PADDING;
/*-- Set Buffer information --*/
buffer_info->length = tmp_skb->len;
buffer_info->dma = dma_map_single(>pdev->dev, tmp_skb->data,
@@ -1248,8 +1247,8 @@ static void pch_gbe_tx_queue(struct pch_gbe_adapter 
*adapter,
/*-- Set Tx descriptor --*/
tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
tx_desc->buffer_addr = (buffer_info->dma);
-   tx_desc->length = (tmp_skb->len);
-   tx_desc->tx_words_eob = ((tmp_skb->len + 3));
+   tx_desc->length = (skb->len);
+   tx_desc->tx_words_eob = ((skb->len + 3));
tx_desc->tx_frame_ctrl = (frame_ctrl);
tx_desc->gbec_status = (DSC_INIT16);
 
-- 
2.16.1

[PATCH v5 05/14] net: pch_gbe: Always reset PHY along with MAC

[Paul Burton]

On the MIPS Boston development board, the EG20T MAC does not report
receiving the RX clock from the (RGMII) RTL8211E PHY unless the PHY is
reset at the same time as the MAC. Since the pch_gbe driver resets the
MAC a number of times - twice during probe, and when taking down the
network interface - we need to reset the PHY at all the same times. Do
that from pch_gbe_mac_reset_hw which is used to reset the MAC in all
cases.

Signed-off-by: Paul Burton <paul.bur...@mips.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 11e8ced4a0f4..90e795d5cc1c 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -380,10 +380,13 @@ static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
 {
/* Read the MAC address. and store to the private data */
pch_gbe_mac_read_mac_addr(hw);
+   pch_gbe_phy_set_reset(hw, 1);
iowrite32(PCH_GBE_ALL_RST, >reg->RESET);
 #ifdef PCH_GBE_MAC_IFOP_RGMII
iowrite32(PCH_GBE_MODE_GMII_ETHER, >reg->MODE);
 #endif
+   pch_gbe_phy_set_reset(hw, 0);
+   usleep_range(1250, 1500);
pch_gbe_wait_clr_bit(>reg->RESET, PCH_GBE_ALL_RST);
/* Setup the receive addresses */
pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
-- 
2.16.1

[PATCH v5 03/14] dt-bindings: net: Document Intel pch_gbe binding

[Paul Burton]

Introduce documentation for a device tree binding for the Intel Platform
Controller Hub (PCH) GigaBit Ethernet (GBE) device. Although this is a
PCIe device & thus largely auto-detectable, this binding will be used to
provide the driver with the PHY reset GPIO.

Signed-off-by: Paul Burton <paul.bur...@mips.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Rob Herring <robh...@kernel.org>
Cc: devicet...@vger.kernel.org
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v5:
- Use standard gpio & ethernet node names in example.
- Remove bus number from example unit addresses.

Changes in v4: None
Changes in v3:
- New patch.

Changes in v2: None

 Documentation/devicetree/bindings/net/pch_gbe.txt | 25 +++
 1 file changed, 25 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/pch_gbe.txt

diff --git a/Documentation/devicetree/bindings/net/pch_gbe.txt 
b/Documentation/devicetree/bindings/net/pch_gbe.txt
new file mode 100644
index ..cff2687e6e75
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pch_gbe.txt
@@ -0,0 +1,25 @@
+Intel Platform Controller Hub (PCH) GigaBit Ethernet (GBE)
+
+Required properties:
+- compatible:  Should be the PCI vendor & device ID, eg. 
"pci8086,8802".
+- reg: Should be a PCI device number as specified by the PCI 
bus
+   binding to IEEE Std 1275-1994.
+- phy-reset-gpios: Should be a GPIO list containing a single GPIO that
+   resets the attached PHY when active.
+
+Example:
+
+   ethernet@0,1 {
+   compatible = "pci8086,8802";
+   reg = <0x00020100 0 0 0 0>;
+   phy-reset-gpios = <_gpio 6
+  GPIO_ACTIVE_LOW>;
+   };
+
+   eg20t_gpio: gpio@0,2 {
+   compatible = "pci8086,8803";
+   reg = <0x00020200 0 0 0 0>;
+
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
-- 
2.16.1

[PATCH v5 08/14] net: pch_gbe: Fold pch_gbe_setup_[rt]ctl into pch_gbe_configure_[rt]x

[Paul Burton]

The pch_gbe driver splits configuration of the receive path between
pch_gbe_setup_rctl() & pch_gbe_configure_rx(), which are always called
together and in that order. The split between the two functions seems
somewhat arbitrary, as both are configuring registers for the receive
path. Fold pch_gbe_setup_rctl() into pch_gbe_configure_rx() such that
callers only need to call one function to configure the receive path
registers.

Similarly configuration of transmit path registers is split between
pch_gbe_setup_tctl() & pch_gbe_configure_tx(), and we fold the former
into the latter in the same way.

Signed-off-by: Paul Burton <paul.bur...@mips.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v5:
- New patch.

Changes in v4: None
Changes in v3: None
Changes in v2: None

 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 52 ++
 1 file changed, 13 insertions(+), 39 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 60e91c0fc98b..2d6980603ee4 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -831,39 +831,26 @@ static void pch_gbe_irq_enable(struct pch_gbe_adapter 
*adapter)
   ioread32(>reg->INT_EN));
 }
 
-
-
 /**
- * pch_gbe_setup_tctl - configure the Transmit control registers
+ * pch_gbe_configure_tx - Configure Transmit Unit after Reset
  * @adapter:  Board private structure
  */
-static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
+static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
 {
struct pch_gbe_hw *hw = >hw;
-   u32 tx_mode, tcpip;
+   u32 tdba, tdlen, dctrl, tx_mode, tcpip;
 
tx_mode = PCH_GBE_TM_LONG_PKT |
PCH_GBE_TM_ST_AND_FD |
PCH_GBE_TM_SHORT_PKT |
PCH_GBE_TM_TH_TX_STRT_8 |
-   PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
-
+   PCH_GBE_TM_TH_ALM_EMP_4 |
+   PCH_GBE_TM_TH_ALM_FULL_8;
iowrite32(tx_mode, >reg->TX_MODE);
 
tcpip = ioread32(>reg->TCPIP_ACC);
tcpip |= PCH_GBE_TX_TCPIPACC_EN;
iowrite32(tcpip, >reg->TCPIP_ACC);
-   return;
-}
-
-/**
- * pch_gbe_configure_tx - Configure Transmit Unit after Reset
- * @adapter:  Board private structure
- */
-static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
-{
-   struct pch_gbe_hw *hw = >hw;
-   u32 tdba, tdlen, dctrl;
 
netdev_dbg(adapter->netdev, "dma addr = 0x%08llx  size = 0x%08x\n",
   (unsigned long long)adapter->tx_ring->dma,
@@ -883,35 +870,25 @@ static void pch_gbe_configure_tx(struct pch_gbe_adapter 
*adapter)
 }
 
 /**
- * pch_gbe_setup_rctl - Configure the receive control registers
+ * pch_gbe_configure_rx - Configure Receive Unit after Reset
  * @adapter:  Board private structure
  */
-static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
+static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
 {
struct pch_gbe_hw *hw = >hw;
-   u32 rx_mode, tcpip;
-
-   rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
-   PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
+   u32 rdba, rdlen, rxdma, rx_mode, tcpip;
 
+   rx_mode = PCH_GBE_ADD_FIL_EN |
+ PCH_GBE_MLT_FIL_EN |
+ PCH_GBE_RH_ALM_EMP_4 |
+ PCH_GBE_RH_ALM_FULL_4 |
+ PCH_GBE_RH_RD_TRG_8;
iowrite32(rx_mode, >reg->RX_MODE);
 
tcpip = ioread32(>reg->TCPIP_ACC);
-
tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
iowrite32(tcpip, >reg->TCPIP_ACC);
-   return;
-}
-
-/**
- * pch_gbe_configure_rx - Configure Receive Unit after Reset
- * @adapter:  Board private structure
- */
-static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
-{
-   struct pch_gbe_hw *hw = >hw;
-   u32 rdba, rdlen, rxdma;
 
netdev_dbg(adapter->netdev, "dma adr = 0x%08llx  size = 0x%08x\n",
   (unsigned long long)adapter->rx_ring->dma,
@@ -1954,9 +1931,7 @@ int pch_gbe_up(struct pch_gbe_adapter *adapter)
/* hardware has been reset, we need to reload some things */
pch_gbe_set_multi(netdev);
 
-   pch_gbe_setup_tctl(adapter);
pch_gbe_configure_tx(adapter);
-   pch_gbe_setup_rctl(adapter);
pch_gbe_configure_rx(adapter);
 
err = pch_gbe_request_irq(adapter);
@@ -2486,7 +2461,6 @@ static int __pch_gbe_suspend(struct pci_dev *pdev)
pch_gbe_down(adapter);
if (wufc) {
pch_gbe_set_multi(netdev);
-   pch_gbe_setup_rctl(adapter);
pch_gbe_configure_rx(adapter);
pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
hw->mac.link_duplex);
-- 
2.16.1

[PATCH v5 10/14] net: pch_gbe: Disable TX DMA whilst configuring descriptors

[Paul Burton]

The pch_gbe driver enables TX DMA the first time we call
pch_gbe_configure_tx() and never disables it again, even if we
reconfigure the device & modify the transmit descriptor ring. This seems
unsafe, since the device may continue accessing descriptors whilst they
are in an unpredictable & possibly invalid state - especially on systems
where the CPUs writes to the descriptors is not coherent with DMA.

In the RX path pch_gbe_configure_rx() disables DMA before configuring
the descriptor pointers & before we set up the descriptors, then
pch_gbe_up() calls pch_gbe_enable_dma_rx() to enable DMA again after the
descriptors have been configured. Here we copy that same scheme for the
TX path - pch_gbe_configure_tx() calls pch_gbe_disable_dma_tx() to
disable DMA, and then after the descriptors have been configured
pch_gbe_up() calls pch_gbe_enable_dma_tx() to enable DMA. This should
ensure that the device doesn't begin reading descriptors before we have
configured them.

Signed-off-by: Paul Burton <paul.bur...@mips.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v5:
- New patch.

Changes in v4: None
Changes in v3: None
Changes in v2: None

 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 29 +-
 1 file changed, 23 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index b6cc4a34ed89..4354842b9b7e 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -851,6 +851,24 @@ static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw)
iowrite32(rxdma, >reg->DMA_CTRL);
 }
 
+static void pch_gbe_disable_dma_tx(struct pch_gbe_hw *hw)
+{
+   u32 rxdma;
+
+   rxdma = ioread32(>reg->DMA_CTRL);
+   rxdma &= ~PCH_GBE_TX_DMA_EN;
+   iowrite32(rxdma, >reg->DMA_CTRL);
+}
+
+static void pch_gbe_enable_dma_tx(struct pch_gbe_hw *hw)
+{
+   u32 rxdma;
+
+   rxdma = ioread32(>reg->DMA_CTRL);
+   rxdma |= PCH_GBE_TX_DMA_EN;
+   iowrite32(rxdma, >reg->DMA_CTRL);
+}
+
 /**
  * pch_gbe_configure_tx - Configure Transmit Unit after Reset
  * @adapter:  Board private structure
@@ -858,7 +876,7 @@ static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw)
 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
 {
struct pch_gbe_hw *hw = >hw;
-   u32 tdba, tdlen, dctrl, tx_mode, tcpip;
+   u32 tdba, tdlen, tx_mode, tcpip;
 
tx_mode = PCH_GBE_TM_LONG_PKT |
PCH_GBE_TM_ST_AND_FD |
@@ -876,17 +894,14 @@ static void pch_gbe_configure_tx(struct pch_gbe_adapter 
*adapter)
   (unsigned long long)adapter->tx_ring->dma,
   adapter->tx_ring->size);
 
+   pch_gbe_disable_dma_tx(hw);
+
/* Setup the HW Tx Head and Tail descriptor pointers */
tdba = adapter->tx_ring->dma;
tdlen = adapter->tx_ring->size - 0x10;
iowrite32(tdba, >reg->TX_DSC_BASE);
iowrite32(tdlen, >reg->TX_DSC_SIZE);
iowrite32(tdba, >reg->TX_DSC_SW_P);
-
-   /* Enables Transmission DMA */
-   dctrl = ioread32(>reg->DMA_CTRL);
-   dctrl |= PCH_GBE_TX_DMA_EN;
-   iowrite32(dctrl, >reg->DMA_CTRL);
 }
 
 /**
@@ -1945,6 +1960,8 @@ int pch_gbe_up(struct pch_gbe_adapter *adapter)
pch_gbe_alloc_tx_buffers(adapter, tx_ring);
pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
adapter->tx_queue_len = netdev->tx_queue_len;
+
+   pch_gbe_enable_dma_tx(>hw);
pch_gbe_enable_dma_rx(>hw);
pch_gbe_enable_mac_rx(>hw);
 
-- 
2.16.1

[PATCH v5 04/14] net: pch_gbe: Add device tree support

[Paul Burton]

Introduce support for retrieving the PHY reset GPIO from device tree,
which will be used on the MIPS Boston development board. This requires
support for probe deferral in order to work correctly, since the order
of device probe is not guaranteed & typically the EG20T GPIO controller
device will be probed after the ethernet MAC.

Signed-off-by: Paul Burton <paul.bur...@mips.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org
---

Changes in v5: None
Changes in v4:
- Use ERR_CAST(), thanks kbuild test robot/Fengguang!

Changes in v3: None
Changes in v2:
- Tidy up handling of parsing private data, drop err_out.

 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 31 +-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 712ac2f7bb2c..11e8ced4a0f4 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -23,6 +23,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #define DRV_VERSION "1.01"
 const char pch_driver_version[] = DRV_VERSION;
@@ -2556,13 +2558,40 @@ static void pch_gbe_remove(struct pci_dev *pdev)
free_netdev(netdev);
 }
 
+static struct pch_gbe_privdata *
+pch_gbe_get_priv(struct pci_dev *pdev, const struct pci_device_id *pci_id)
+{
+   struct pch_gbe_privdata *pdata;
+   struct gpio_desc *gpio;
+
+   if (!IS_ENABLED(CONFIG_OF))
+   return (struct pch_gbe_privdata *)pci_id->driver_data;
+
+   pdata = devm_kzalloc(>dev, sizeof(*pdata), GFP_KERNEL);
+   if (!pdata)
+   return ERR_PTR(-ENOMEM);
+
+   gpio = devm_gpiod_get(>dev, "phy-reset", GPIOD_ASIS);
+   if (!IS_ERR(gpio))
+   pdata->phy_reset_gpio = gpio;
+   else if (PTR_ERR(gpio) != -ENOENT)
+   return ERR_CAST(gpio);
+
+   return pdata;
+}
+
 static int pch_gbe_probe(struct pci_dev *pdev,
  const struct pci_device_id *pci_id)
 {
struct net_device *netdev;
struct pch_gbe_adapter *adapter;
+   struct pch_gbe_privdata *pdata;
int ret;
 
+   pdata = pch_gbe_get_priv(pdev, pci_id);
+   if (IS_ERR(pdata))
+   return PTR_ERR(pdata);
+
ret = pcim_enable_device(pdev);
if (ret)
return ret;
@@ -2600,7 +2629,7 @@ static int pch_gbe_probe(struct pci_dev *pdev,
adapter->pdev = pdev;
adapter->hw.back = adapter;
adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
-   adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
+   adapter->pdata = pdata;
if (adapter->pdata && adapter->pdata->platform_init)
adapter->pdata->platform_init(pdev, adapter->pdata);
 
-- 
2.16.1

[PATCH v5 09/14] net: pch_gbe: Use pch_gbe_disable_dma_rx() in pch_gbe_configure_rx()

[Paul Burton]

The pch_gbe_configure_rx() function open-codes the equivalent of
pch_gbe_disable_dma_rx(). Remove the duplication by moving
pch_gbe_disable_dma_rx(), and pch_gbe_enable_dma_rx() for consistency,
to be defined earlier than pch_gbe_configure_rx() and have
pch_gbe_configure_rx() call pch_gbe_disable_dma_rx() rather than
duplicate its functionality.

Signed-off-by: Paul Burton <paul.bur...@mips.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v5:
- New patch.

Changes in v4: None
Changes in v3: None
Changes in v2: None

 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 48 ++
 1 file changed, 22 insertions(+), 26 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 2d6980603ee4..b6cc4a34ed89 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -831,6 +831,26 @@ static void pch_gbe_irq_enable(struct pch_gbe_adapter 
*adapter)
   ioread32(>reg->INT_EN));
 }
 
+static void pch_gbe_disable_dma_rx(struct pch_gbe_hw *hw)
+{
+   u32 rxdma;
+
+   /* Disable Receive DMA */
+   rxdma = ioread32(>reg->DMA_CTRL);
+   rxdma &= ~PCH_GBE_RX_DMA_EN;
+   iowrite32(rxdma, >reg->DMA_CTRL);
+}
+
+static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw)
+{
+   u32 rxdma;
+
+   /* Enables Receive DMA */
+   rxdma = ioread32(>reg->DMA_CTRL);
+   rxdma |= PCH_GBE_RX_DMA_EN;
+   iowrite32(rxdma, >reg->DMA_CTRL);
+}
+
 /**
  * pch_gbe_configure_tx - Configure Transmit Unit after Reset
  * @adapter:  Board private structure
@@ -876,7 +896,7 @@ static void pch_gbe_configure_tx(struct pch_gbe_adapter 
*adapter)
 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
 {
struct pch_gbe_hw *hw = >hw;
-   u32 rdba, rdlen, rxdma, rx_mode, tcpip;
+   u32 rdba, rdlen, rx_mode, tcpip;
 
rx_mode = PCH_GBE_ADD_FIL_EN |
  PCH_GBE_MLT_FIL_EN |
@@ -897,11 +917,7 @@ static void pch_gbe_configure_rx(struct pch_gbe_adapter 
*adapter)
pch_gbe_mac_force_mac_fc(hw);
 
pch_gbe_disable_mac_rx(hw);
-
-   /* Disables Receive DMA */
-   rxdma = ioread32(>reg->DMA_CTRL);
-   rxdma &= ~PCH_GBE_RX_DMA_EN;
-   iowrite32(rxdma, >reg->DMA_CTRL);
+   pch_gbe_disable_dma_rx(hw);
 
netdev_dbg(adapter->netdev,
   "MAC_RX_EN reg = 0x%08x  DMA_CTRL reg = 0x%08x\n",
@@ -1290,26 +1306,6 @@ void pch_gbe_update_stats(struct pch_gbe_adapter 
*adapter)
spin_unlock_irqrestore(>stats_lock, flags);
 }
 
-static void pch_gbe_disable_dma_rx(struct pch_gbe_hw *hw)
-{
-   u32 rxdma;
-
-   /* Disable Receive DMA */
-   rxdma = ioread32(>reg->DMA_CTRL);
-   rxdma &= ~PCH_GBE_RX_DMA_EN;
-   iowrite32(rxdma, >reg->DMA_CTRL);
-}
-
-static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw)
-{
-   u32 rxdma;
-
-   /* Enables Receive DMA */
-   rxdma = ioread32(>reg->DMA_CTRL);
-   rxdma |= PCH_GBE_RX_DMA_EN;
-   iowrite32(rxdma, >reg->DMA_CTRL);
-}
-
 /**
  * pch_gbe_intr - Interrupt Handler
  * @irq:   Interrupt number
-- 
2.16.1

[PATCH v5 14/14] net: pch_gbe: Allow build on MIPS platforms

[Paul Burton]

Allow the pch_gbe driver to be built on MIPS platforms, allowing its use
on the MIPS Boston development board.

Signed-off-by: Paul Burton <paul.bur...@mips.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig 
b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
index 5f7a35212796..4d3809ae75e1 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
@@ -4,7 +4,7 @@
 
 config PCH_GBE
tristate "OKI SEMICONDUCTOR IOH(ML7223/ML7831) GbE"
-   depends on PCI && (X86_32 || COMPILE_TEST)
+   depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
select MII
select PTP_1588_CLOCK_PCH
select NET_PTP_CLASSIFY
-- 
2.16.1

[PATCH v5 12/14] net: pch_gbe: Fix TX RX descriptor accesses for big endian systems

[Paul Burton]

From: Hassan Naveed <hassan.nav...@mips.com>

Fix pch_gbe driver for ethernet operations for a big endian CPU.
Values written to and read from transmit and receive descriptors
in the pch_gbe driver are byte swapped from the perspective of a
big endian CPU, since the ethernet controller always operates in
little endian mode. Rectify this by appropriately byte swapping
these descriptor field values in the driver software.

Signed-off-by: Hassan Naveed <hassan.nav...@mips.com>
Signed-off-by: Paul Burton <paul.bur...@mips.com>
Reviewed-by: Paul Burton <paul.bur...@mips.com>
Reviewed-by: Matt Redfearn <matt.redfe...@mips.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v5:
- Newly included in this series.

Changes in v4: None
Changes in v3: None
Changes in v2:
- Use __le{16,32} for field types, checked with sparse.

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h| 22 
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 66 --
 2 files changed, 46 insertions(+), 42 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index 8ba9ced2d1fd..7159e39b4685 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -431,13 +431,13 @@ struct pch_gbe_hw {
  * @reserved2: Reserved
  */
 struct pch_gbe_rx_desc {
-   u32 buffer_addr;
-   u32 tcp_ip_status;
-   u16 rx_words_eob;
-   u16 gbec_status;
+   __le32 buffer_addr;
+   __le32 tcp_ip_status;
+   __le16 rx_words_eob;
+   __le16 gbec_status;
u8 dma_status;
u8 reserved1;
-   u16 reserved2;
+   __le16 reserved2;
 };
 
 /**
@@ -452,14 +452,14 @@ struct pch_gbe_rx_desc {
  * @gbec_status:   GMAC Status
  */
 struct pch_gbe_tx_desc {
-   u32 buffer_addr;
-   u16 length;
-   u16 reserved1;
-   u16 tx_words_eob;
-   u16 tx_frame_ctrl;
+   __le32 buffer_addr;
+   __le16 length;
+   __le16 reserved1;
+   __le16 tx_words_eob;
+   __le16 tx_frame_ctrl;
u8 dma_status;
u8 reserved2;
-   u16 gbec_status;
+   __le16 gbec_status;
 };
 
 
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 8e3ad7dcef0b..a0b8c8f4b4c9 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -1254,11 +1254,11 @@ static void pch_gbe_tx_queue(struct pch_gbe_adapter 
*adapter,
 
/*-- Set Tx descriptor --*/
tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
-   tx_desc->buffer_addr = (buffer_info->dma);
-   tx_desc->length = (skb->len);
-   tx_desc->tx_words_eob = ((skb->len + 3));
-   tx_desc->tx_frame_ctrl = (frame_ctrl);
-   tx_desc->gbec_status = (DSC_INIT16);
+   tx_desc->buffer_addr = cpu_to_le32(buffer_info->dma);
+   tx_desc->length = cpu_to_le16(skb->len);
+   tx_desc->tx_words_eob = cpu_to_le16(skb->len + 3);
+   tx_desc->tx_frame_ctrl = cpu_to_le16(frame_ctrl);
+   tx_desc->gbec_status = cpu_to_le16(DSC_INIT16);
 
/* Ensure writes to descriptors complete before DMA begins */
mmiowb();
@@ -1447,8 +1447,8 @@ pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
}
buffer_info->mapped = true;
rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
-   rx_desc->buffer_addr = (buffer_info->dma);
-   rx_desc->gbec_status = DSC_INIT16;
+   rx_desc->buffer_addr = cpu_to_le32(buffer_info->dma);
+   rx_desc->gbec_status = cpu_to_le16(DSC_INIT16);
 
netdev_dbg(netdev,
   "i = %d  buffer_info->dma = 0x08%llx  
buffer_info->length = 0x%x\n",
@@ -1520,7 +1520,7 @@ static void pch_gbe_alloc_tx_buffers(struct 
pch_gbe_adapter *adapter,
skb_reserve(skb, PCH_GBE_DMA_ALIGN);
buffer_info->skb = skb;
tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
-   tx_desc->gbec_status = (DSC_INIT16);
+   tx_desc->gbec_status = cpu_to_le16(DSC_INIT16);
}
return;
 }
@@ -1551,11 +1551,12 @@ pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
i = tx_ring->next_to_clean;
tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
netdev_dbg(adapter->netdev, "gbec_status:0x%04x  dma_status:0x%04x\n",
-  tx_desc->gbec_status, tx_desc->dma_status);
+  le16_to_cpu(tx_desc->gbec_status), tx_desc->dma_status);
 
unused = PCH_GBE_DESC_UNUSED(tx_ring);
thresh = tx_ring->count - PCH_GBE_TX_WEIGHT;
-   if ((tx_desc->gbec_status == DSC_INIT16) && (u

[PATCH v5 00/14] net: pch_gbe: Fixes & MIPS support

[Paul Burton]

The Intel EG20T Platform Controller Hub is used on the MIPS Boston
development board to provide various peripherals including ethernet.
This series fixes some issues with the pch_gbe driver discovered whilst
in use on the Boston board, and implements support for device tree which
we use to provide the PHY reset GPIO.

Applies atop v4.16-rc1.

Hassan Naveed (1):
  net: pch_gbe: Fix TX RX descriptor accesses for big endian systems

Paul Burton (13):
  net: pch_gbe: Mark Minnow PHY reset GPIO active low
  net: pch_gbe: Pull PHY GPIO handling out of Minnow code
  dt-bindings: net: Document Intel pch_gbe binding
  net: pch_gbe: Add device tree support
  net: pch_gbe: Always reset PHY along with MAC
  net: pch_gbe: Allow longer for resets
  net: pch_gbe: Fix handling of TX padding
  net: pch_gbe: Fold pch_gbe_setup_[rt]ctl into pch_gbe_configure_[rt]x
  net: pch_gbe: Use pch_gbe_disable_dma_rx() in pch_gbe_configure_rx()
  net: pch_gbe: Disable TX DMA whilst configuring descriptors
  net: pch_gbe: Ensure DMA is ordered with descriptor writes
  ptp: pch: Allow build on MIPS platforms
  net: pch_gbe: Allow build on MIPS platforms

 Documentation/devicetree/bindings/net/pch_gbe.txt  |  25 ++
 drivers/net/ethernet/oki-semi/pch_gbe/Kconfig  |   2 +-
 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h|  27 +-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 283 -
 drivers/ptp/Kconfig|   2 +-
 5 files changed, 204 insertions(+), 135 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/pch_gbe.txt

-- 
2.16.1

[PATCH v5 06/14] net: pch_gbe: Allow longer for resets

[Paul Burton]

Resets of the EG20T MAC on the MIPS Boston development board take longer
than the 1000 loops that pch_gbe_wait_clr_bit was performing. Rather
than simply increasing the number of loops, switch to using
readl_poll_timeout_atomic() from linux/iopoll.h in order to provide some
independence from the speed of the CPU.

Signed-off-by: Paul Burton <paul.bur...@mips.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v5:
- Bump up the timeout based on feedback from Marcin.

Changes in v4: None
Changes in v3:
- Switch to using readl_poll_timeout_atomic().

Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 90e795d5cc1c..77f7fbd98e8f 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #define DRV_VERSION "1.01"
@@ -318,13 +319,11 @@ s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
  */
 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
 {
+   int err;
u32 tmp;
 
-   /* wait busy */
-   tmp = 1000;
-   while ((ioread32(reg) & bit) && --tmp)
-   cpu_relax();
-   if (!tmp)
+   err = readl_poll_timeout_atomic(reg, tmp, !(tmp & bit), 10, 25000);
+   if (err)
pr_err("Error: busy bit is not cleared\n");
 }
 
-- 
2.16.1

[PATCH v5 01/14] net: pch_gbe: Mark Minnow PHY reset GPIO active low

[Paul Burton]

The Minnow PHY reset GPIO is set to 0 to enter reset & 1 to leave reset
- that is, it is an active low GPIO. In order to allow for the code to
be made more generic by further patches, indicate to the GPIO subsystem
that the GPIO is active low & invert the values it is set to such that
they reflect logically whether the device is being reset or not.

Signed-off-by: Paul Burton <paul.bur...@mips.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 7cd494611a74..d5c6f2e2d3a2 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -2688,7 +2688,8 @@ static int pch_gbe_probe(struct pci_dev *pdev,
  */
 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
 {
-   unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH | GPIOF_EXPORT;
+   unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW |
+   GPIOF_EXPORT | GPIOF_ACTIVE_LOW;
unsigned gpio = MINNOW_PHY_RESET_GPIO;
int ret;
 
@@ -2700,10 +2701,10 @@ static int pch_gbe_minnow_platform_init(struct pci_dev 
*pdev)
return ret;
}
 
-   gpio_set_value(gpio, 0);
-   usleep_range(1250, 1500);
gpio_set_value(gpio, 1);
usleep_range(1250, 1500);
+   gpio_set_value(gpio, 0);
+   usleep_range(1250, 1500);
 
return ret;
 }
-- 
2.16.1

[PATCH v5 02/14] net: pch_gbe: Pull PHY GPIO handling out of Minnow code

[Paul Burton]

The MIPS Boston development board uses the Intel EG20T Platform
Controller Hub, including its gigabit ethernet controller, and requires
that its RTL8211E PHY be reset much like the Minnow platform. Pull the
PHY reset GPIO handling out of Minnow-specific code such that it can be
shared by later patches.

Signed-off-by: Paul Burton <paul.bur...@mips.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org
---

Changes in v5:
- Name struct pch_gbe_privdata's platform_init pdata arg, per checkpatch.

Changes in v4: None
Changes in v3:
- Use adapter->pdata as arg to platform_init, to fix bisectability.

Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h|  5 +++-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 33 +++---
 2 files changed, 27 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index 697e29dd4bd3..8ba9ced2d1fd 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -580,15 +580,18 @@ struct pch_gbe_hw_stats {
 
 /**
  * struct pch_gbe_privdata - PCI Device ID driver data
+ * @phy_reset_gpio:PHY reset GPIO descriptor.
  * @phy_tx_clk_delay:  Bool, configure the PHY TX delay in software
  * @phy_disable_hibernate: Bool, disable PHY hibernation
  * @platform_init: Platform initialization callback, called from
  * probe, prior to PHY initialization.
  */
 struct pch_gbe_privdata {
+   struct gpio_desc *phy_reset_gpio;
bool phy_tx_clk_delay;
bool phy_disable_hibernate;
-   int (*platform_init)(struct pci_dev *pdev);
+   int (*platform_init)(struct pci_dev *pdev,
+struct pch_gbe_privdata *pdata);
 };
 
 /**
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index d5c6f2e2d3a2..712ac2f7bb2c 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -360,6 +360,16 @@ static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 
* addr, u32 index)
pch_gbe_wait_clr_bit(>reg->ADDR_MASK, PCH_GBE_BUSY);
 }
 
+static void pch_gbe_phy_set_reset(struct pch_gbe_hw *hw, int value)
+{
+   struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
+
+   if (!adapter->pdata || !adapter->pdata->phy_reset_gpio)
+   return;
+
+   gpiod_set_value(adapter->pdata->phy_reset_gpio, value);
+}
+
 /**
  * pch_gbe_mac_reset_hw - Reset hardware
  * @hw:Pointer to the HW structure
@@ -2592,7 +2602,14 @@ static int pch_gbe_probe(struct pci_dev *pdev,
adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
if (adapter->pdata && adapter->pdata->platform_init)
-   adapter->pdata->platform_init(pdev);
+   adapter->pdata->platform_init(pdev, adapter->pdata);
+
+   if (adapter->pdata && adapter->pdata->phy_reset_gpio) {
+   pch_gbe_phy_set_reset(>hw, 1);
+   usleep_range(1250, 1500);
+   pch_gbe_phy_set_reset(>hw, 0);
+   usleep_range(1250, 1500);
+   }
 
adapter->ptp_pdev =
pci_get_domain_bus_and_slot(pci_domain_nr(adapter->pdev->bus),
@@ -2686,7 +2703,8 @@ static int pch_gbe_probe(struct pci_dev *pdev,
 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
  * ensure it is awake for probe and init. Request the line and reset the PHY.
  */
-static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
+static int pch_gbe_minnow_platform_init(struct pci_dev *pdev,
+   struct pch_gbe_privdata *pdata)
 {
unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW |
GPIOF_EXPORT | GPIOF_ACTIVE_LOW;
@@ -2695,16 +2713,11 @@ static int pch_gbe_minnow_platform_init(struct pci_dev 
*pdev)
 
ret = devm_gpio_request_one(>dev, gpio, flags,
"minnow_phy_reset");
-   if (ret) {
+   if (!ret)
+   pdata->phy_reset_gpio = gpio_to_desc(gpio);
+   else
dev_err(>dev,
"ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
-   return ret;
-   }
-
-   gpio_set_value(gpio, 1);
-   usleep_range(1250, 1500);
-   gpio_set_value(gpio, 0);
-   usleep_range(1250, 1500);
 
return ret;
 }
-- 
2.16.1

Re: [PATCH] net: stmmac: Meet alignment requirements for DMA

[Paul Burton]

Hi David,

On Tuesday, 26 September 2017 21:53:21 PDT David Miller wrote:
> From: Paul Burton <paul.bur...@imgtec.com>
> Date: Tue, 26 Sep 2017 21:30:56 -0700
> 
> > Nobody said that you are required to do anything, I suggested that
> > it would be beneficial if you were to suggest a change to the
> > documented DMA API such that it allows your usage where it currently
> > does not.
> 
> Documentation is often wrong and it is here.  What 200+ drivers
> actually do and depend upon trumps a simple text document.

Agreed - but if the documented API is wrong then it should change.

> The requirement is that the memory remains quiescent on the cpu side
> while the device messes with it.  And that this quiescence requirement
> may or may not be on a cache line basis.
> 
> There is absolutely no requirement that the buffers themselves are
> cache line aligned.
> 
> In fact, receive buffers for networking are intentionally 2-byte
> aligned in order for the ipv4 headers to be naturally 32-bit aligned.
> 
> Cache line aligning receive buffers will actually make some
> architectures trap because of the bad alignment.
> 
> So see, this cache line alignment requirement is pure madness from
> just about any perspective whatsoever.

Thank you - that's more constructive.

I understand that the network code doesn't suffer from a problem with using 
non-cacheline-aligned buffers, because you guarantee that the CPU will not be 
writing to anything on either side of the memory mapped for DMA up to at least 
a cache line boundary. That is all well & good (though still, I think that 
ought to be documented somewhere even if just by a comment somewhere in linux/
sk_buff.h).

There is still a problem though in other cases which do not provide such a 
guarantee - for example the MMC issue I pointed out previously - which it 
would be useful to be able to catch rather than allowing silent memory 
corruption which can be difficult to track down. Whilst the particular case of 
mapping a struct sk_buff's data for DMA might not trigger this issue the issue 
does still exist in other cases for which aligning data to a cache line 
boundary is not always "pure madness".

So whilst it sounds like you'd happily just change or remove the paragraph 
about cache-line alignment in Documentation/DMA-API.txt, and I agree that 
would be a good start, I wonder whether we could do something better. One 
option might be for the warning in the MIPS DMA code to be predicated on one 
of the cache lines only partially covered by a DMA mapping actually being 
dirty - though this would probably be a more expensive check than we'd want in 
the general case so might have to be conditional upon some new debug entry in 
Kconfig. I'll give this some thought.

Thanks,
Paul

signature.asc
Description: This is a digitally signed message part.

Re: [PATCH] net: stmmac: Meet alignment requirements for DMA

[Paul Burton]

Hi David,

On Tuesday, 26 September 2017 19:52:44 PDT David Miller wrote:
> From: Paul Burton <paul.bur...@imgtec.com>
> Date: Tue, 26 Sep 2017 14:30:33 -0700
> 
> > I'd suggest that at a minimum if you're unwilling to obey the API as
> > described in Documentation/DMA-API.txt then it would be beneficial
> > if you could propose a change to it such that it works for you, and
> > perhaps we can extend the API & its documentation to allow your
> > usage whilst also allowing us to catch broken uses.
> 
> The networking driver code works fine as is.
> 
> I also didn't write that ill-advised documentation in the DMA docs,
> nor the non-merged new MIPS assertion.
> 
> So I'm trying to figure out on what basis I am required to do
> anything.
> 
> Thank you.

Nobody said you wrote the documentation, but you do maintain code which 
disobeys the documented DMA API & now you're being an ass about it 
unnecessarily.

Nobody said that you are required to do anything, I suggested that it would be 
beneficial if you were to suggest a change to the documented DMA API such that 
it allows your usage where it currently does not. If you don't want to have 
any input into that, and you actually think that your current approach of 
ignoring the documented API is the best path forwards, then we're probably 
done here & I'll be making a note to avoid yourself & anything under net/ to 
whatever extent is possible...

Thanks,
Paul

signature.asc
Description: This is a digitally signed message part.

Re: [PATCH] net: stmmac: Meet alignment requirements for DMA

[Paul Burton]

Hi David,

On Tuesday, 26 September 2017 13:33:09 PDT David Miller wrote:
> From: Paul Burton <paul.bur...@imgtec.com>
> Date: Tue, 26 Sep 2017 11:48:19 -0700
> 
> >> The device writes into only the bytes it was given access to, which
> >> starts at the DMA address.
> > 
> > OK - still fine but *only* if we don't write to anything that happens to
> > be
> > part of the cache lines that are only partially covered by the DMA mapping
> > & make them dirty. If we do then any writeback of those lines will
> > clobber data the device wrote, and any invalidation of them will discard
> > data the CPU wrote.
> > 
> > How would you have us ensure that such writes don't occur?
> > 
> > This really does not feel to me like something to leave up to drivers
> > without any means of checking or enforcing correctness. The requirement
> > to align DMA mappings at cache-line boundaries, as outlined in
> > Documentation/DMA-API.txt, allows this to be enforced. If you want to
> > ignore this requirement then there is no clear way to verify that we
> > aren't writing to cache lines involved in a DMA transfer whilst the
> > transfer is occurring, and no sane way to handle those cache lines if we
> > do.
> 
> The memory immediately before skb->data and immediately after
> skb->data+skb->len will not be accessed.  This is guaranteed.

This guarantee is not made known to the DMA API or the per-arch code backing 
it, nor can I see it documented anywhere. It's good to hear that it exists in 
some form though.

> I will request something exactly one more time to give you the benfit
> of the doubt that you want to show me why this is _really_ a problem
> and not a problem only in theory.

My previous message simply walked through your existing example & explained 
why your assumptions can be incorrect as far as the DMA API & interactions 
with caches go - I don't think that warrants the seemingly confrontational 
tone.

> Please show me an exact sequence, with current code, in a current driver
> that uses the DMA API properly, where corruption really can occur.

How about this:

  https://patchwork.kernel.org/patch/9423097/

Now this isn't networking code at fault, it was a problem with MMC. Given that 
you say there's a guarantee that networking code won't write to cache lines 
that partially include memory mapped for DMA, perhaps networking code is 
immune to this issue (though at a minimum I think that guarantee ought to be 
documented so that others know to keep it true).

The question remains though: what would you have us do to catch the broken 
uses of the DMA API with non-cacheline-aligned memory? By not obeying 
Documentation/DMA-API.txt you're preventing us from adding checks that catch 
others who also disobey the alignment requirement in ways that are not fine, 
and which result in otherwise difficult to track down memory corruption.

> The new restriction is absolutely not reasonable for this use case.
> It it furthermore impractical to require the 200+ drivers the use this
> technique to allocate and map networking buffers to abide by this new
> rule.  Many platforms with even worse cache problems that MIPS handle
> this just fine.
> 
> Thank you.

One disconnect here is that you describe a "new restriction" whilst the 
restriction we're talking about has been documented in Documentation/DMA-
API.txt since at least the beginning of the git era - it is not new at all.

The only thing that changed for us that I have intended to warn when the 
restriction is not met, because that often indicates genuine & otherwise 
difficult to detect bugs such as the MMC one I linked to above. FYI that 
warning has not gone into mainline yet anyway.

I'd suggest that at a minimum if you're unwilling to obey the API as described 
in Documentation/DMA-API.txt then it would be beneficial if you could propose 
a change to it such that it works for you, and perhaps we can extend the API & 
its documentation to allow your usage whilst also allowing us to catch broken 
uses.

Surely we can agree that the current situation wherein networking code clearly 
disobeys the documented API is not a good one, and that allowing other broken 
uses to slip by unnoticed except in rare difficult to track down corner cases 
is not good either.

Thanks,
Paul

signature.asc
Description: This is a digitally signed message part.

Re: [PATCH] net: stmmac: Meet alignment requirements for DMA

[Paul Burton]

Hi David,

On Tuesday, 26 September 2017 10:34:00 PDT David Miller wrote:
> From: Matt Redfearn 
> Date: Tue, 26 Sep 2017 14:57:39 +0100
> 
> > Since the MIPS architecture requires software cache management,
> > performing a dma_map_single(TO_DEVICE) will writeback and invalidate
> > the cachelines for the required region. To comply with (our
> > interpretation of) the DMA API documentation, the MIPS implementation
> > expects a cacheline aligned & sized buffer, so that it can writeback a
> > set of complete cachelines. Indeed a recent patch
> > (https://patchwork.linux-mips.org/patch/14624/) causes the MIPS dma
> > mapping code to emit warnings if the buffer it is requested to sync is
> > not cachline aligned. This driver, as is, fails this test and causes
> > thousands of warnings to be emitted.
> 
> For a device write, if the device does what it is told and does not
> access bytes outside of the periphery of the DMA mapping, nothing bad
> can happen.
> 
> When the DMA buffer is mapped, the cpu side cachelines are flushed (even
> ones which are partially part of the requsted mapping, this is _fine_).

This is not fine. Let's presume we writeback+invalidate the cache lines that 
are only partially covered by the DMA mapping at its beginning or end, and 
just invalidate all the lines that are wholly covered by the mapping. So far 
so good.

> The device writes into only the bytes it was given access to, which
> starts at the DMA address.

OK - still fine but *only* if we don't write to anything that happens to be 
part of the cache lines that are only partially covered by the DMA mapping & 
make them dirty. If we do then any writeback of those lines will clobber data 
the device wrote, and any invalidation of them will discard data the CPU 
wrote.

How would you have us ensure that such writes don't occur?

This really does not feel to me like something to leave up to drivers without 
any means of checking or enforcing correctness. The requirement to align DMA 
mappings at cache-line boundaries, as outlined in Documentation/DMA-API.txt, 
allows this to be enforced. If you want to ignore this requirement then there 
is no clear way to verify that we aren't writing to cache lines involved in a 
DMA transfer whilst the transfer is occurring, and no sane way to handle those 
cache lines if we do.

> The unmap and/or sync operation after the DMA transfer needs to do
> nothing on the cpu side since the map operation flushed the cpu side
> caches already.
> 
> When the cpu reads, it will pull the cacheline from main memory and
> see what the device wrote.

This is not true, because:

1) CPUs may speculatively read data. In between the invalidations that we did
   earlier & the point at which the transfer completes, the CPU may have
   speculatively read any arbitrary part of the memory mapped for DMA.

2) If we wrote to any lines that are only partially covered by the DMA mapping
   then of course they're valid & dirty, and an access won't fetch from main
   memory.

We therefore need to perform cache invalidation again at the end of the 
transfer - on MIPS you can grep for cpu_needs_post_dma_flush to find this. 
>From a glance ARM has similar post-DMA invalidation in 
__dma_page_dev_to_cpu(), ARM64 in __dma_unmap_area() etc etc.

At this point what would you have us do with cache lines that are only 
partially covered by the DMA mapping? As above - if we writeback+invalidate we 
risk clobbering data written by the device. If we just invalidate we risk 
discarding data written by the CPU. And this is even ignoring the risk that a 
writeback of one of these lines happens due to eviction during the DMA 
transfer, which we have no control over at all.

> It's not like the device can put "garbage" into the bytes earlier in
> the cacheline it was given partial access to.

Right - but the CPU can "put garbage" into the bytes the device was given 
access to, simply by fetching stale bytes from main memory before the device 
overwrites them.

> I really don't see what the problem is and why MIPS needs special
> handling.  You will have to give specific examples, step by step,
> where things can go wrong before I will be able to consider your
> changes.

MIPS doesn't need special handling - it just needs the driver to obey a 
documented restriction when using the DMA API. One could argue that it ought 
to be you who justifies why you feel networking drivers can ignore the 
documentation, and that if you disagree with the documented API you should aim 
to change it rather than ignore it.

Thanks,
Paul

signature.asc
Description: This is a digitally signed message part.

[PATCH v4 6/7] net: pch_gbe: Allow longer for resets

[Paul Burton]

Resets of the EG20T MAC on the MIPS Boston development board take longer
than the 1000 loops that pch_gbe_wait_clr_bit was performing. Rather
than simply increasing the number of loops, switch to using
readl_poll_timeout_atomic() from linux/iopoll.h in order to provide some
independence from the speed of the CPU.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: Eric Dumazet <eduma...@google.com>
Cc: Jarod Wilson <ja...@redhat.com>
Cc: Tobias Klauser <tklau...@distanz.ch>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v4: None

Changes in v3:
- Switch to using readl_poll_timeout_atomic().

Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index c8554d3adf1c..c109646803a4 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #define DRV_VERSION "1.01"
@@ -318,13 +319,11 @@ s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
  */
 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
 {
+   int err;
u32 tmp;
 
-   /* wait busy */
-   tmp = 1000;
-   while ((ioread32(reg) & bit) && --tmp)
-   cpu_relax();
-   if (!tmp)
+   err = readl_poll_timeout_atomic(reg, tmp, !(tmp & bit), 10, 500);
+   if (err)
pr_err("Error: busy bit is not cleared\n");
 }
 
-- 
2.13.0

[PATCH v4 2/7] net: pch_gbe: Pull PHY GPIO handling out of Minnow code

[Paul Burton]

The MIPS Boston development board uses the Intel EG20T Platform
Controller Hub, including its gigabit ethernet controller, and requires
that its RTL8211E PHY be reset much like the Minnow platform. Pull the
PHY reset GPIO handling out of Minnow-specific code such that it can be
shared by later patches.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: Eric Dumazet <eduma...@google.com>
Cc: Jarod Wilson <ja...@redhat.com>
Cc: Tobias Klauser <tklau...@distanz.ch>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org
---

Changes in v4: None

Changes in v3:
- Use adapter->pdata as arg to platform_init, to fix bisectability.

Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h|  4 ++-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 33 +++---
 2 files changed, 26 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index 8d710a3b4db0..de1dd08050f4 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -580,15 +580,17 @@ struct pch_gbe_hw_stats {
 
 /**
  * struct pch_gbe_privdata - PCI Device ID driver data
+ * @phy_reset_gpio:PHY reset GPIO descriptor.
  * @phy_tx_clk_delay:  Bool, configure the PHY TX delay in software
  * @phy_disable_hibernate: Bool, disable PHY hibernation
  * @platform_init: Platform initialization callback, called from
  * probe, prior to PHY initialization.
  */
 struct pch_gbe_privdata {
+   struct gpio_desc *phy_reset_gpio;
bool phy_tx_clk_delay;
bool phy_disable_hibernate;
-   int (*platform_init)(struct pci_dev *pdev);
+   int (*platform_init)(struct pci_dev *, struct pch_gbe_privdata *);
 };
 
 /**
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index d38198718005..cb9b904786e4 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -360,6 +360,16 @@ static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 
* addr, u32 index)
pch_gbe_wait_clr_bit(>reg->ADDR_MASK, PCH_GBE_BUSY);
 }
 
+static void pch_gbe_phy_set_reset(struct pch_gbe_hw *hw, int value)
+{
+   struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
+
+   if (!adapter->pdata || !adapter->pdata->phy_reset_gpio)
+   return;
+
+   gpiod_set_value(adapter->pdata->phy_reset_gpio, value);
+}
+
 /**
  * pch_gbe_mac_reset_hw - Reset hardware
  * @hw:Pointer to the HW structure
@@ -2601,7 +2611,14 @@ static int pch_gbe_probe(struct pci_dev *pdev,
adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
if (adapter->pdata && adapter->pdata->platform_init)
-   adapter->pdata->platform_init(pdev);
+   adapter->pdata->platform_init(pdev, adapter->pdata);
+
+   if (adapter->pdata && adapter->pdata->phy_reset_gpio) {
+   pch_gbe_phy_set_reset(>hw, 1);
+   usleep_range(1250, 1500);
+   pch_gbe_phy_set_reset(>hw, 0);
+   usleep_range(1250, 1500);
+   }
 
adapter->ptp_pdev = pci_get_bus_and_slot(adapter->pdev->bus->number,
   PCI_DEVFN(12, 4));
@@ -2694,7 +2711,8 @@ static int pch_gbe_probe(struct pci_dev *pdev,
 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
  * ensure it is awake for probe and init. Request the line and reset the PHY.
  */
-static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
+static int pch_gbe_minnow_platform_init(struct pci_dev *pdev,
+   struct pch_gbe_privdata *pdata)
 {
unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW |
GPIOF_EXPORT | GPIOF_ACTIVE_LOW;
@@ -2703,16 +2721,11 @@ static int pch_gbe_minnow_platform_init(struct pci_dev 
*pdev)
 
ret = devm_gpio_request_one(>dev, gpio, flags,
"minnow_phy_reset");
-   if (ret) {
+   if (!ret)
+   pdata->phy_reset_gpio = gpio_to_desc(gpio);
+   else
dev_err(>dev,
"ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
-   return ret;
-   }
-
-   gpio_set_value(gpio, 1);
-   usleep_range(1250, 1500);
-   gpio_set_value(gpio, 0);
-   usleep_range(1250, 1500);
 
return ret;
 }
-- 
2.13.0

[PATCH v4 1/7] net: pch_gbe: Mark Minnow PHY reset GPIO active low

[Paul Burton]

The Minnow PHY reset GPIO is set to 0 to enter reset & 1 to leave reset
- that is, it is an active low GPIO. In order to allow for the code to
be made more generic by further patches, indicate to the GPIO subsystem
that the GPIO is active low & invert the values it is set to such that
they reflect logically whether the device is being reset or not.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: Eric Dumazet <eduma...@google.com>
Cc: Jarod Wilson <ja...@redhat.com>
Cc: Tobias Klauser <tklau...@distanz.ch>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 5ae9681a2da7..d38198718005 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -2696,7 +2696,8 @@ static int pch_gbe_probe(struct pci_dev *pdev,
  */
 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
 {
-   unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH | GPIOF_EXPORT;
+   unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW |
+   GPIOF_EXPORT | GPIOF_ACTIVE_LOW;
unsigned gpio = MINNOW_PHY_RESET_GPIO;
int ret;
 
@@ -2708,10 +2709,10 @@ static int pch_gbe_minnow_platform_init(struct pci_dev 
*pdev)
return ret;
}
 
-   gpio_set_value(gpio, 0);
-   usleep_range(1250, 1500);
gpio_set_value(gpio, 1);
usleep_range(1250, 1500);
+   gpio_set_value(gpio, 0);
+   usleep_range(1250, 1500);
 
return ret;
 }
-- 
2.13.0

[PATCH v4 0/7] net: pch_gbe: Fixes & MIPS support

[Paul Burton]

The Intel EG20T Platform Controller Hub is used on the MIPS Boston
development board to provide various peripherals including ethernet.
This series fixes some issues with the pch_gbe driver discovered whilst
in use on the Boston board, and implements support for device tree which
we use to provide the PHY reset GPIO.

Applies atop v4.12-rc4.

Paul Burton (7):
  net: pch_gbe: Mark Minnow PHY reset GPIO active low
  net: pch_gbe: Pull PHY GPIO handling out of Minnow code
  dt-bindings: net: Document Intel pch_gbe binding
  net: pch_gbe: Add device tree support
  net: pch_gbe: Always reset PHY along with MAC
  net: pch_gbe: Allow longer for resets
  net: pch_gbe: Allow build on MIPS platforms

 Documentation/devicetree/bindings/net/pch_gbe.txt  | 25 +++
 drivers/net/ethernet/oki-semi/pch_gbe/Kconfig  |  2 +-
 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h|  4 +-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 79 +-
 4 files changed, 91 insertions(+), 19 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/pch_gbe.txt

-- 
2.13.0

Re: [PATCH v3 2/7] net: pch_gbe: Pull PHY GPIO handling out of Minnow code

[Paul Burton]

Hi Andrew,

On Saturday, 3 June 2017 10:52:00 PDT Andrew Lunn wrote:
> > diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
> > b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c index
> > d38198718005..cb9b904786e4 100644
> > --- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
> > +++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
> > @@ -360,6 +360,16 @@ static void pch_gbe_mac_mar_set(struct pch_gbe_hw
> > *hw, u8 * addr, u32 index)> 
> > pch_gbe_wait_clr_bit(>reg->ADDR_MASK, PCH_GBE_BUSY);
> >  
> >  }
> > 
> > +static void pch_gbe_phy_set_reset(struct pch_gbe_hw *hw, int value)
> > +{
> > +   struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
> > +
> > +   if (!adapter->pdata || !adapter->pdata->phy_reset_gpio)
> > +   return;
> > +
> > +   gpiod_set_value(adapter->pdata->phy_reset_gpio, value);
> 
> Hi Paul
> 
> Since you are using the gpiod_ API, the core will take notice of the
> active low/active high flag when performing this set.

Correct, and as desired.

> > ret = devm_gpio_request_one(>dev, gpio, flags,
> > 
> > "minnow_phy_reset");
> > 
> > -   if (ret) {
> > +   if (!ret)
> > +   pdata->phy_reset_gpio = gpio_to_desc(gpio);
> 
> Here however, you are using the gpio_ API, which ignores the active
> high/low flag in device tree. And in your binding patch, you give the
> example:
> 
> +   phy-reset-gpios = <_gpio 6
> +  GPIO_ACTIVE_LOW>;
> 
> This active low is totally ignored.

First of all, this path is for the existing Minnow platform, which doesn't use 
the device tree. That is, this code is the non-DT path so looking at what 
happens to flags in the device tree here makes no sense.

If you want to examine what happens in the DT case then please look at 
pch_gbe_get_priv() which uses devm_gpiod_get() which should honor the flags 
provided by the DT.

> I personally would say this is all messed up, and going to result in
> problems for somebody with a board which actually needs an
> GPIO_ACTIVE_HIGH.

It's a path which only applies to the Minnow board, which is always active 
low. Before patch 1 of this series that was done without the GPIOF_ACTIVE_LOW 
flag by setting GPIO values to reflect the physical GPIO line low/high rather 
than the logical active/not-active. After patch 1 this path began using 
GPIOF_ACTIVE_LOW such that the rest of the code can use logical active/not-
active values which work with either active low or active high GPIOs. In this 
Minnow-specific path GPIOF_ACTIVE_LOW is hardcoded, but again only applies to 
the Minnow board which doesn't take the GPIO value from device tree.

> Please use the gpiod_ API through out and respect the flags in the
> device tree binding.

The gpiod_ API, quite rightly, retrieves GPIOs associated with a device - for 
example via the device tree. The Minnow board, which is what the driver 
already supports in-tree, does not do this but instead hardcodes a GPIO number 
(MINNOW_PHY_RESET_GPIO). I don't own, use or care about the Minnow platform so 
that is not something that I can change. In the path that my patch does add, 
the path which is used with DT, I already do use the gpiod_ API & respect 
flags from the DT.

Thanks,
Paul

signature.asc
Description: This is a digitally signed message part.

[PATCH v3 7/7] net: pch_gbe: Allow build on MIPS platforms

[Paul Burton]

Allow the pch_gbe driver to be built on MIPS platforms, in preparation
for its use on the MIPS Boston board.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: Eric Dumazet <eduma...@google.com>
Cc: Jarod Wilson <ja...@redhat.com>
Cc: Tobias Klauser <tklau...@distanz.ch>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v3: None
Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig 
b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
index 5f7a35212796..4d3809ae75e1 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
@@ -4,7 +4,7 @@
 
 config PCH_GBE
tristate "OKI SEMICONDUCTOR IOH(ML7223/ML7831) GbE"
-   depends on PCI && (X86_32 || COMPILE_TEST)
+   depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
select MII
select PTP_1588_CLOCK_PCH
select NET_PTP_CLASSIFY
-- 
2.13.0

[PATCH v3 6/7] net: pch_gbe: Allow longer for resets

[Paul Burton]

Resets of the EG20T MAC on the MIPS Boston development board take longer
than the 1000 loops that pch_gbe_wait_clr_bit was performing. Rather
than simply increasing the number of loops, switch to using
readl_poll_timeout_atomic() from linux/iopoll.h in order to provide some
independence from the speed of the CPU.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: Eric Dumazet <eduma...@google.com>
Cc: Jarod Wilson <ja...@redhat.com>
Cc: Tobias Klauser <tklau...@distanz.ch>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v3:
- Switch to using readl_poll_timeout_atomic().

Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index f8791be7b3b5..3d0f4c8b1742 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #define DRV_VERSION "1.01"
@@ -318,13 +319,11 @@ s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
  */
 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
 {
+   int err;
u32 tmp;
 
-   /* wait busy */
-   tmp = 1000;
-   while ((ioread32(reg) & bit) && --tmp)
-   cpu_relax();
-   if (!tmp)
+   err = readl_poll_timeout_atomic(reg, tmp, !(tmp & bit), 10, 500);
+   if (err)
pr_err("Error: busy bit is not cleared\n");
 }
 
-- 
2.13.0

[PATCH v3 5/7] net: pch_gbe: Always reset PHY along with MAC

[Paul Burton]

On the MIPS Boston development board, the EG20T MAC does not report
receiving the RX clock from the (RGMII) RTL8211E PHY unless the PHY is
reset at the same time as the MAC. Since the pch_gbe driver resets the
MAC a number of times - twice during probe, and when taking down the
network interface - we need to reset the PHY at all the same times. Do
that from pch_gbe_mac_reset_hw which is used to reset the MAC in all
cases.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: Eric Dumazet <eduma...@google.com>
Cc: Jarod Wilson <ja...@redhat.com>
Cc: Tobias Klauser <tklau...@distanz.ch>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org
---

Changes in v3: None
Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 59a42c20d433..f8791be7b3b5 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -380,10 +380,13 @@ static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
 {
/* Read the MAC address. and store to the private data */
pch_gbe_mac_read_mac_addr(hw);
+   pch_gbe_phy_set_reset(hw, 1);
iowrite32(PCH_GBE_ALL_RST, >reg->RESET);
 #ifdef PCH_GBE_MAC_IFOP_RGMII
iowrite32(PCH_GBE_MODE_GMII_ETHER, >reg->MODE);
 #endif
+   pch_gbe_phy_set_reset(hw, 0);
+   usleep_range(1250, 1500);
pch_gbe_wait_clr_bit(>reg->RESET, PCH_GBE_ALL_RST);
/* Setup the receive addresses */
pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
-- 
2.13.0

[PATCH v3 3/7] dt-bindings: net: Document Intel pch_gbe binding

[Paul Burton]

Introduce documentation for a device tree binding for the Intel Platform
Controller Hub (PCH) GigaBit Ethernet (GBE) device. Although this is a
PCIe device & thus largely auto-detectable, this binding will be used to
provide the driver with the PHY reset GPIO.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: Eric Dumazet <eduma...@google.com>
Cc: Jarod Wilson <ja...@redhat.com>
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Rob Herring <robh...@kernel.org>
Cc: Tobias Klauser <tklau...@distanz.ch>
Cc: devicet...@vger.kernel.org
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org

---

Changes in v3:
- New patch.

Changes in v2: None

 Documentation/devicetree/bindings/net/pch_gbe.txt | 25 +++
 1 file changed, 25 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/pch_gbe.txt

diff --git a/Documentation/devicetree/bindings/net/pch_gbe.txt 
b/Documentation/devicetree/bindings/net/pch_gbe.txt
new file mode 100644
index ..5de479c26b04
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pch_gbe.txt
@@ -0,0 +1,25 @@
+Intel Platform Controller Hub (PCH) GigaBit Ethernet (GBE)
+
+Required properties:
+- compatible:  Should be the PCI vendor & device ID, eg. 
"pci8086,8802".
+- reg: Should be a PCI device number as specified by the PCI 
bus
+   binding to IEEE Std 1275-1994.
+- phy-reset-gpios: Should be a GPIO list containing a single GPIO that
+   resets the attached PHY when active.
+
+Example:
+
+   eg20t_mac@2,0,1 {
+   compatible = "pci8086,8802";
+   reg = <0x00020100 0 0 0 0>;
+   phy-reset-gpios = <_gpio 6
+  GPIO_ACTIVE_LOW>;
+   };
+
+   eg20t_gpio: eg20t_gpio@2,0,2 {
+   compatible = "pci8086,8803";
+   reg = <0x00020200 0 0 0 0>;
+
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
-- 
2.13.0

[PATCH v3 4/7] net: pch_gbe: Add device tree support

[Paul Burton]

Introduce support for retrieving the PHY reset GPIO from device tree,
which will be used on the MIPS Boston development board. This requires
support for probe deferral in order to work correctly, since the order
of device probe is not guaranteed & typically the EG20T GPIO controller
device will be probed after the ethernet MAC.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: Eric Dumazet <eduma...@google.com>
Cc: Jarod Wilson <ja...@redhat.com>
Cc: Tobias Klauser <tklau...@distanz.ch>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org
---

Changes in v3: None

Changes in v2:
- Tidy up handling of parsing private data, drop err_out.

 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 31 +-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index cb9b904786e4..59a42c20d433 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -23,6 +23,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #define DRV_VERSION "1.01"
 const char pch_driver_version[] = DRV_VERSION;
@@ -2565,13 +2567,40 @@ static void pch_gbe_remove(struct pci_dev *pdev)
free_netdev(netdev);
 }
 
+static struct pch_gbe_privdata *
+pch_gbe_get_priv(struct pci_dev *pdev, const struct pci_device_id *pci_id)
+{
+   struct pch_gbe_privdata *pdata;
+   struct gpio_desc *gpio;
+
+   if (!IS_ENABLED(CONFIG_OF))
+   return (struct pch_gbe_privdata *)pci_id->driver_data;
+
+   pdata = devm_kzalloc(>dev, sizeof(*pdata), GFP_KERNEL);
+   if (!pdata)
+   return ERR_PTR(-ENOMEM);
+
+   gpio = devm_gpiod_get(>dev, "phy-reset", GPIOD_ASIS);
+   if (!IS_ERR(gpio))
+   pdata->phy_reset_gpio = gpio;
+   else if (PTR_ERR(gpio) != -ENOENT)
+   return ERR_PTR(PTR_ERR(gpio));
+
+   return pdata;
+}
+
 static int pch_gbe_probe(struct pci_dev *pdev,
  const struct pci_device_id *pci_id)
 {
struct net_device *netdev;
struct pch_gbe_adapter *adapter;
+   struct pch_gbe_privdata *pdata;
int ret;
 
+   pdata = pch_gbe_get_priv(pdev, pci_id);
+   if (IS_ERR(pdata))
+   return PTR_ERR(pdata);
+
ret = pcim_enable_device(pdev);
if (ret)
return ret;
@@ -2609,7 +2638,7 @@ static int pch_gbe_probe(struct pci_dev *pdev,
adapter->pdev = pdev;
adapter->hw.back = adapter;
adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
-   adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
+   adapter->pdata = pdata;
if (adapter->pdata && adapter->pdata->platform_init)
adapter->pdata->platform_init(pdev, adapter->pdata);
 
-- 
2.13.0

[PATCH v3 2/7] net: pch_gbe: Pull PHY GPIO handling out of Minnow code

[Paul Burton]

The MIPS Boston development board uses the Intel EG20T Platform
Controller Hub, including its gigabit ethernet controller, and requires
that its RTL8211E PHY be reset much like the Minnow platform. Pull the
PHY reset GPIO handling out of Minnow-specific code such that it can be
shared by later patches.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: Eric Dumazet <eduma...@google.com>
Cc: Jarod Wilson <ja...@redhat.com>
Cc: Tobias Klauser <tklau...@distanz.ch>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org
---

Changes in v3:
- Use adapter->pdata as arg to platform_init, to fix bisectability.

Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h|  4 ++-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 33 +++---
 2 files changed, 26 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index 8d710a3b4db0..de1dd08050f4 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -580,15 +580,17 @@ struct pch_gbe_hw_stats {
 
 /**
  * struct pch_gbe_privdata - PCI Device ID driver data
+ * @phy_reset_gpio:PHY reset GPIO descriptor.
  * @phy_tx_clk_delay:  Bool, configure the PHY TX delay in software
  * @phy_disable_hibernate: Bool, disable PHY hibernation
  * @platform_init: Platform initialization callback, called from
  * probe, prior to PHY initialization.
  */
 struct pch_gbe_privdata {
+   struct gpio_desc *phy_reset_gpio;
bool phy_tx_clk_delay;
bool phy_disable_hibernate;
-   int (*platform_init)(struct pci_dev *pdev);
+   int (*platform_init)(struct pci_dev *, struct pch_gbe_privdata *);
 };
 
 /**
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index d38198718005..cb9b904786e4 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -360,6 +360,16 @@ static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 
* addr, u32 index)
pch_gbe_wait_clr_bit(>reg->ADDR_MASK, PCH_GBE_BUSY);
 }
 
+static void pch_gbe_phy_set_reset(struct pch_gbe_hw *hw, int value)
+{
+   struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
+
+   if (!adapter->pdata || !adapter->pdata->phy_reset_gpio)
+   return;
+
+   gpiod_set_value(adapter->pdata->phy_reset_gpio, value);
+}
+
 /**
  * pch_gbe_mac_reset_hw - Reset hardware
  * @hw:Pointer to the HW structure
@@ -2601,7 +2611,14 @@ static int pch_gbe_probe(struct pci_dev *pdev,
adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
if (adapter->pdata && adapter->pdata->platform_init)
-   adapter->pdata->platform_init(pdev);
+   adapter->pdata->platform_init(pdev, adapter->pdata);
+
+   if (adapter->pdata && adapter->pdata->phy_reset_gpio) {
+   pch_gbe_phy_set_reset(>hw, 1);
+   usleep_range(1250, 1500);
+   pch_gbe_phy_set_reset(>hw, 0);
+   usleep_range(1250, 1500);
+   }
 
adapter->ptp_pdev = pci_get_bus_and_slot(adapter->pdev->bus->number,
   PCI_DEVFN(12, 4));
@@ -2694,7 +2711,8 @@ static int pch_gbe_probe(struct pci_dev *pdev,
 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
  * ensure it is awake for probe and init. Request the line and reset the PHY.
  */
-static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
+static int pch_gbe_minnow_platform_init(struct pci_dev *pdev,
+   struct pch_gbe_privdata *pdata)
 {
unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW |
GPIOF_EXPORT | GPIOF_ACTIVE_LOW;
@@ -2703,16 +2721,11 @@ static int pch_gbe_minnow_platform_init(struct pci_dev 
*pdev)
 
ret = devm_gpio_request_one(>dev, gpio, flags,
"minnow_phy_reset");
-   if (ret) {
+   if (!ret)
+   pdata->phy_reset_gpio = gpio_to_desc(gpio);
+   else
dev_err(>dev,
"ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
-   return ret;
-   }
-
-   gpio_set_value(gpio, 1);
-   usleep_range(1250, 1500);
-   gpio_set_value(gpio, 0);
-   usleep_range(1250, 1500);
 
return ret;
 }
-- 
2.13.0

[PATCH v3 1/7] net: pch_gbe: Mark Minnow PHY reset GPIO active low

[Paul Burton]

The Minnow PHY reset GPIO is set to 0 to enter reset & 1 to leave reset
- that is, it is an active low GPIO. In order to allow for the code to
be made more generic by further patches, indicate to the GPIO subsystem
that the GPIO is active low & invert the values it is set to such that
they reflect logically whether the device is being reset or not.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
Cc: David S. Miller <da...@davemloft.net>
Cc: Eric Dumazet <eduma...@google.com>
Cc: Jarod Wilson <ja...@redhat.com>
Cc: Tobias Klauser <tklau...@distanz.ch>
Cc: linux-m...@linux-mips.org
Cc: netdev@vger.kernel.org
---

Changes in v3: None
Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 5ae9681a2da7..d38198718005 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -2696,7 +2696,8 @@ static int pch_gbe_probe(struct pci_dev *pdev,
  */
 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
 {
-   unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH | GPIOF_EXPORT;
+   unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW |
+   GPIOF_EXPORT | GPIOF_ACTIVE_LOW;
unsigned gpio = MINNOW_PHY_RESET_GPIO;
int ret;
 
@@ -2708,10 +2709,10 @@ static int pch_gbe_minnow_platform_init(struct pci_dev 
*pdev)
return ret;
}
 
-   gpio_set_value(gpio, 0);
-   usleep_range(1250, 1500);
gpio_set_value(gpio, 1);
usleep_range(1250, 1500);
+   gpio_set_value(gpio, 0);
+   usleep_range(1250, 1500);
 
return ret;
 }
-- 
2.13.0

[PATCH v3 0/7] net: pch_gbe: Fixes & MIPS support

[Paul Burton]

The Intel EG20T Platform Controller Hub is used on the MIPS Boston
development board to provide various peripherals including ethernet.
This series fixes some issues with the pch_gbe driver discovered whilst
in use on the Boston board, and implements support for device tree which
we use to provide the PHY reset GPIO.

Applies atop v4.12-rc3.

Paul Burton (7):
  net: pch_gbe: Mark Minnow PHY reset GPIO active low
  net: pch_gbe: Pull PHY GPIO handling out of Minnow code
  dt-bindings: net: Document Intel pch_gbe binding
  net: pch_gbe: Add device tree support
  net: pch_gbe: Always reset PHY along with MAC
  net: pch_gbe: Allow longer for resets
  net: pch_gbe: Allow build on MIPS platforms

 Documentation/devicetree/bindings/net/pch_gbe.txt  | 25 +++
 drivers/net/ethernet/oki-semi/pch_gbe/Kconfig  |  2 +-
 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h|  4 +-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 79 +-
 4 files changed, 91 insertions(+), 19 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/pch_gbe.txt

-- 
2.13.0

[PATCH] net: lantiq_etop: Remove unused 'i' variable

[Paul Burton]

Commit e7f4dc3536a4 ("mdio: Move allocation of interrupts into core")
removed the only use of the 'i' variable from ltq_etop_mdio_init() but
left the variable declaration behind, leading to the following compiler
warning:

  drivers/net/ethernet/lantiq_etop.c: In function 'ltq_etop_mdio_init':
  drivers/net/ethernet/lantiq_etop.c:414:6: warning: unused variable 'i' 
[-Wunused-variable]
int i;
^

Fix this by removing the declaration of the 'i' variable.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>

---

 drivers/net/ethernet/lantiq_etop.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/net/ethernet/lantiq_etop.c 
b/drivers/net/ethernet/lantiq_etop.c
index dc82b1b..0d2f8e9 100644
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
@@ -411,7 +411,6 @@ static int
 ltq_etop_mdio_init(struct net_device *dev)
 {
struct ltq_etop_priv *priv = netdev_priv(dev);
-   int i;
int err;
 
priv->mii_bus = mdiobus_alloc();
-- 
2.9.3

[PATCH] net: ti: cpmac: Fix compiler warning due to type confusion

[Paul Burton]

cpmac_start_xmit() used the max() macro on skb->len (an unsigned int)
and ETH_ZLEN (a signed int literal). This led to the following compiler
warning:

  In file included from include/linux/list.h:8:0,
   from include/linux/module.h:9,
   from drivers/net/ethernet/ti/cpmac.c:19:
  drivers/net/ethernet/ti/cpmac.c: In function 'cpmac_start_xmit':
  include/linux/kernel.h:748:17: warning: comparison of distinct pointer
  types lacks a cast
(void) (&_max1 == &_max2);  \
   ^
  drivers/net/ethernet/ti/cpmac.c:560:8: note: in expansion of macro 'max'
len = max(skb->len, ETH_ZLEN);
  ^

On top of this, it assigned the result of the max() macro to a signed
integer whilst all further uses of it result in it being cast to varying
widths of unsigned integer.

Fix this up by using max_t to ensure the comparison is performed as
unsigned integers, and for consistency change the type of the len
variable to unsigned int.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>

---

 drivers/net/ethernet/ti/cpmac.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/ti/cpmac.c b/drivers/net/ethernet/ti/cpmac.c
index 7eef45e..b1454bd 100644
--- a/drivers/net/ethernet/ti/cpmac.c
+++ b/drivers/net/ethernet/ti/cpmac.c
@@ -547,7 +547,8 @@ fatal_error:
 
 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
 {
-   int queue, len;
+   int queue;
+   unsigned int len;
struct cpmac_desc *desc;
struct cpmac_priv *priv = netdev_priv(dev);
 
@@ -557,7 +558,7 @@ static int cpmac_start_xmit(struct sk_buff *skb, struct 
net_device *dev)
if (unlikely(skb_padto(skb, ETH_ZLEN)))
return NETDEV_TX_OK;
 
-   len = max(skb->len, ETH_ZLEN);
+   len = max_t(unsigned int, skb->len, ETH_ZLEN);
queue = skb_get_queue_mapping(skb);
netif_stop_subqueue(dev, queue);
 
-- 
2.9.3

[PATCH v2 12/15] ptp: pch: Allow build on MIPS platforms

[Paul Burton]

Allow the ptp_pch driver to be built on MIPS platforms in preparation
for use on the MIPS Boston board.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
Acked-by: Richard Cochran <richardcoch...@gmail.com>
---

Changes in v2: None

 drivers/ptp/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index ee3de34..ee43549 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -74,7 +74,7 @@ config DP83640_PHY
 
 config PTP_1588_CLOCK_PCH
tristate "Intel PCH EG20T as PTP clock"
-   depends on X86_32 || COMPILE_TEST
+   depends on X86_32 || MIPS || COMPILE_TEST
depends on HAS_IOMEM && NET
select PTP_1588_CLOCK
help
-- 
2.7.0

[PATCH v2 1/6] net: pch_gbe: Allow build on MIPS platforms

[Paul Burton]

Allow the pch_gbe driver to be built on MIPS platforms, in preparation
for its use on the MIPS Boston board.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
---

Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig 
b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
index 5f7a352..4d3809a 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
@@ -4,7 +4,7 @@
 
 config PCH_GBE
tristate "OKI SEMICONDUCTOR IOH(ML7223/ML7831) GbE"
-   depends on PCI && (X86_32 || COMPILE_TEST)
+   depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
select MII
select PTP_1588_CLOCK_PCH
select NET_PTP_CLASSIFY
-- 
2.7.0

[PATCH v2 0/6] pch_gbe fixes for Imagination Technologies MIPS Boston

[Paul Burton]

This series has been extracted from an earlier larger series adding
support for the Imagination Technologies MIPS Boston development board.
The current version of that series without these patches included can be
found here:

http://marc.info/?l=linux-mips=145449909110835=2

This series is somewhat standalone & should fix theoretical issues for
other users of the driver, but has only been tested by myself in
conjunction with the above series on a Boston board.

Paul Burton (6):
  net: pch_gbe: Allow build on MIPS platforms
  net: pch_gbe: Mark Minnow PHY reset GPIO active low
  net: pch_gbe: Pull PHY GPIO handling out of Minnow code
  net: pch_gbe: Always reset PHY along with MAC
  net: pch_gbe: Add device tree support
  net: pch_gbe: Allow longer for resets

 drivers/net/ethernet/oki-semi/pch_gbe/Kconfig  |  2 +-
 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h|  4 +-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 71 ++
 3 files changed, 62 insertions(+), 15 deletions(-)

-- 
2.7.0

[PATCH v2 2/6] net: pch_gbe: Mark Minnow PHY reset GPIO active low

[Paul Burton]

The Minnow PHY reset GPIO is set to 0 to enter reset & 1 to leave reset
- that is, it is an active low GPIO. In order to allow for the code to
be made more generic by further patches, indicate to the GPIO subsystem
that the GPIO is active low & invert the values it is set to such that
they reflect logically whether the device is being reset or not.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
---

Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 3b98b263b..fde4c11 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -2717,7 +2717,8 @@ err_free_netdev:
  */
 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
 {
-   unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH | GPIOF_EXPORT;
+   unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW |
+   GPIOF_EXPORT | GPIOF_ACTIVE_LOW;
unsigned gpio = MINNOW_PHY_RESET_GPIO;
int ret;
 
@@ -2729,10 +2730,10 @@ static int pch_gbe_minnow_platform_init(struct pci_dev 
*pdev)
return ret;
}
 
-   gpio_set_value(gpio, 0);
-   usleep_range(1250, 1500);
gpio_set_value(gpio, 1);
usleep_range(1250, 1500);
+   gpio_set_value(gpio, 0);
+   usleep_range(1250, 1500);
 
return ret;
 }
-- 
2.7.0

[PATCH v2 6/6] net: pch_gbe: Allow longer for resets

[Paul Burton]

Resets of the EG20T MAC on the MIPS Boston development board take longer
than the 1000 loops that pch_gbe_wait_clr_bit was performing. Bump up
the number of loops.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>

---

Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 00ef83c..87994d2 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -321,7 +321,7 @@ static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
u32 tmp;
 
/* wait busy */
-   tmp = 1000;
+   tmp = 1;
while ((ioread32(reg) & bit) && --tmp)
cpu_relax();
if (!tmp)
-- 
2.7.0

[PATCH v2 4/6] net: pch_gbe: Always reset PHY along with MAC

[Paul Burton]

On the MIPS Boston development board, the EG20T MAC does not report
receiving the RX clock from the (RGMII) RTL8211E PHY unless the PHY is
reset at the same time as the MAC. Since the pch_gbe driver resets the
MAC a number of times - twice during probe, and when taking down the
network interface - we need to reset the PHY at all the same times. Do
that from pch_gbe_mac_reset_hw which is used to reset the MAC in all
cases.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
---

Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 23d28f0..824ff9e 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -378,10 +378,13 @@ static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
 {
/* Read the MAC address. and store to the private data */
pch_gbe_mac_read_mac_addr(hw);
+   pch_gbe_phy_set_reset(hw, 1);
iowrite32(PCH_GBE_ALL_RST, >reg->RESET);
 #ifdef PCH_GBE_MAC_IFOP_RGMII
iowrite32(PCH_GBE_MODE_GMII_ETHER, >reg->MODE);
 #endif
+   pch_gbe_phy_set_reset(hw, 0);
+   usleep_range(1250, 1500);
pch_gbe_wait_clr_bit(>reg->RESET, PCH_GBE_ALL_RST);
/* Setup the receive addresses */
pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
-- 
2.7.0

[PATCH v2 3/6] net: pch_gbe: Pull PHY GPIO handling out of Minnow code

[Paul Burton]

The MIPS Boston development board uses the Intel EG20T Platform
Controller Hub, including its gigabit ethernet controller, and requires
that its RTL8211E PHY be reset much like the Minnow platform. Pull the
PHY reset GPIO handling out of Minnow-specific code such that it can be
shared by later patches.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
---

Changes in v2: None

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h|  4 ++-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 33 +++---
 2 files changed, 26 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index 2a55d6d..884f90b 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -582,15 +582,17 @@ struct pch_gbe_hw_stats {
 
 /**
  * struct pch_gbe_privdata - PCI Device ID driver data
+ * @phy_reset_gpio:PHY reset GPIO descriptor.
  * @phy_tx_clk_delay:  Bool, configure the PHY TX delay in software
  * @phy_disable_hibernate: Bool, disable PHY hibernation
  * @platform_init: Platform initialization callback, called from
  * probe, prior to PHY initialization.
  */
 struct pch_gbe_privdata {
+   struct gpio_desc *phy_reset_gpio;
bool phy_tx_clk_delay;
bool phy_disable_hibernate;
-   int (*platform_init)(struct pci_dev *pdev);
+   int (*platform_init)(struct pci_dev *, struct pch_gbe_privdata *);
 };
 
 /**
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index fde4c11..23d28f0 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -360,6 +360,16 @@ static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 
* addr, u32 index)
pch_gbe_wait_clr_bit(>reg->ADDR_MASK, PCH_GBE_BUSY);
 }
 
+static void pch_gbe_phy_set_reset(struct pch_gbe_hw *hw, int value)
+{
+   struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
+
+   if (!adapter->pdata || !adapter->pdata->phy_reset_gpio)
+   return;
+
+   gpiod_set_value(adapter->pdata->phy_reset_gpio, value);
+}
+
 /**
  * pch_gbe_mac_reset_hw - Reset hardware
  * @hw:Pointer to the HW structure
@@ -2627,7 +2637,14 @@ static int pch_gbe_probe(struct pci_dev *pdev,
adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
if (adapter->pdata && adapter->pdata->platform_init)
-   adapter->pdata->platform_init(pdev);
+   adapter->pdata->platform_init(pdev, pdata);
+
+   if (adapter->pdata && adapter->pdata->phy_reset_gpio) {
+   pch_gbe_phy_set_reset(>hw, 1);
+   usleep_range(1250, 1500);
+   pch_gbe_phy_set_reset(>hw, 0);
+   usleep_range(1250, 1500);
+   }
 
adapter->ptp_pdev = pci_get_bus_and_slot(adapter->pdev->bus->number,
   PCI_DEVFN(12, 4));
@@ -2715,7 +2732,8 @@ err_free_netdev:
 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
  * ensure it is awake for probe and init. Request the line and reset the PHY.
  */
-static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
+static int pch_gbe_minnow_platform_init(struct pci_dev *pdev,
+   struct pch_gbe_privdata *pdata)
 {
unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW |
GPIOF_EXPORT | GPIOF_ACTIVE_LOW;
@@ -2724,16 +2742,11 @@ static int pch_gbe_minnow_platform_init(struct pci_dev 
*pdev)
 
ret = devm_gpio_request_one(>dev, gpio, flags,
"minnow_phy_reset");
-   if (ret) {
+   if (!ret)
+   pdata->phy_reset_gpio = gpio_to_desc(gpio);
+   else
dev_err(>dev,
"ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
-   return ret;
-   }
-
-   gpio_set_value(gpio, 1);
-   usleep_range(1250, 1500);
-   gpio_set_value(gpio, 0);
-   usleep_range(1250, 1500);
 
return ret;
 }
-- 
2.7.0

[PATCH v2 5/6] net: pch_gbe: Add device tree support

[Paul Burton]

Introduce support for retrieving the PHY reset GPIO from device tree,
which will be used on the MIPS Boston development board. This requires
support for probe deferral in order to work correctly, since the order
of device probe is not guaranteed & typically the EG20T GPIO controller
device will be probed after the ethernet MAC.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
---

Changes in v2:
- Tidy up handling of parsing private data, drop err_out.

 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 30 +-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 824ff9e..00ef83c 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -23,6 +23,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #define DRV_VERSION "1.01"
 const char pch_driver_version[] = DRV_VERSION;
@@ -2594,13 +2596,39 @@ static void pch_gbe_remove(struct pci_dev *pdev)
free_netdev(netdev);
 }
 
+static struct pch_gbe_privdata *
+pch_gbe_get_priv(struct pci_dev *pdev, const struct pci_device_id *pci_id)
+{
+   struct pch_gbe_privdata *pdata;
+   struct gpio_desc *gpio;
+
+   if (!config_enabled(CONFIG_OF))
+   return (struct pch_gbe_privdata *)pci_id->driver_data;
+
+   pdata = devm_kzalloc(>dev, sizeof(*pdata), GFP_KERNEL);
+   if (!pdata)
+   return ERR_PTR(-ENOMEM);
+
+   gpio = devm_gpiod_get(>dev, "phy-reset", GPIOD_ASIS);
+   if (IS_ERR(gpio))
+   return ERR_PTR(PTR_ERR(gpio));
+   pdata->phy_reset_gpio = gpio;
+
+   return pdata;
+}
+
 static int pch_gbe_probe(struct pci_dev *pdev,
  const struct pci_device_id *pci_id)
 {
struct net_device *netdev;
struct pch_gbe_adapter *adapter;
+   struct pch_gbe_privdata *pdata;
int ret;
 
+   pdata = pch_gbe_get_priv(pdev, pci_id);
+   if (IS_ERR(pdata))
+   return PTR_ERR(pdata);
+
ret = pcim_enable_device(pdev);
if (ret)
return ret;
@@ -2638,7 +2666,7 @@ static int pch_gbe_probe(struct pci_dev *pdev,
adapter->pdev = pdev;
adapter->hw.back = adapter;
adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
-   adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
+   adapter->pdata = pdata;
if (adapter->pdata && adapter->pdata->platform_init)
adapter->pdata->platform_init(pdev, pdata);
 
-- 
2.7.0

[PATCH 21/28] net: pch_gbe: mark Minnow PHY reset GPIO active low

[Paul Burton]

The Minnow PHY reset GPIO is set to 0 to enter reset & 1 to leave reset
- that is, it is an active low GPIO. In order to allow for the code to
be made more generic by further patches, indicate to the GPIO subsystem
that the GPIO is active low & invert the values it is set to such that
they reflect logically whether the device is being reset or not.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
---

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 3b98b263b..fde4c11 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -2717,7 +2717,8 @@ err_free_netdev:
  */
 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
 {
-   unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH | GPIOF_EXPORT;
+   unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW |
+   GPIOF_EXPORT | GPIOF_ACTIVE_LOW;
unsigned gpio = MINNOW_PHY_RESET_GPIO;
int ret;
 
@@ -2729,10 +2730,10 @@ static int pch_gbe_minnow_platform_init(struct pci_dev 
*pdev)
return ret;
}
 
-   gpio_set_value(gpio, 0);
-   usleep_range(1250, 1500);
gpio_set_value(gpio, 1);
usleep_range(1250, 1500);
+   gpio_set_value(gpio, 0);
+   usleep_range(1250, 1500);
 
return ret;
 }
-- 
2.6.2

--
To unsubscribe from this list: send the line "unsubscribe netdev" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 22/28] net: pch_gbe: pull PHY GPIO handling out of Minnow code

[Paul Burton]

The MIPS Boston development board uses the Intel EG20T Platform
Controller Hub, including its gigabit ethernet controller, and requires
that its RTL8211E PHY be reset much like the Minnow platform. Pull the
PHY reset GPIO handling out of Minnow-specific code such that it can be
shared by later patches.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
---

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h|  4 ++-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 33 +++---
 2 files changed, 26 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
index 2a55d6d..884f90b 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
@@ -582,15 +582,17 @@ struct pch_gbe_hw_stats {
 
 /**
  * struct pch_gbe_privdata - PCI Device ID driver data
+ * @phy_reset_gpio:PHY reset GPIO descriptor.
  * @phy_tx_clk_delay:  Bool, configure the PHY TX delay in software
  * @phy_disable_hibernate: Bool, disable PHY hibernation
  * @platform_init: Platform initialization callback, called from
  * probe, prior to PHY initialization.
  */
 struct pch_gbe_privdata {
+   struct gpio_desc *phy_reset_gpio;
bool phy_tx_clk_delay;
bool phy_disable_hibernate;
-   int (*platform_init)(struct pci_dev *pdev);
+   int (*platform_init)(struct pci_dev *, struct pch_gbe_privdata *);
 };
 
 /**
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index fde4c11..23d28f0 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -360,6 +360,16 @@ static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 
* addr, u32 index)
pch_gbe_wait_clr_bit(>reg->ADDR_MASK, PCH_GBE_BUSY);
 }
 
+static void pch_gbe_phy_set_reset(struct pch_gbe_hw *hw, int value)
+{
+   struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
+
+   if (!adapter->pdata || !adapter->pdata->phy_reset_gpio)
+   return;
+
+   gpiod_set_value(adapter->pdata->phy_reset_gpio, value);
+}
+
 /**
  * pch_gbe_mac_reset_hw - Reset hardware
  * @hw:Pointer to the HW structure
@@ -2627,7 +2637,14 @@ static int pch_gbe_probe(struct pci_dev *pdev,
adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
if (adapter->pdata && adapter->pdata->platform_init)
-   adapter->pdata->platform_init(pdev);
+   adapter->pdata->platform_init(pdev, pdata);
+
+   if (adapter->pdata && adapter->pdata->phy_reset_gpio) {
+   pch_gbe_phy_set_reset(>hw, 1);
+   usleep_range(1250, 1500);
+   pch_gbe_phy_set_reset(>hw, 0);
+   usleep_range(1250, 1500);
+   }
 
adapter->ptp_pdev = pci_get_bus_and_slot(adapter->pdev->bus->number,
   PCI_DEVFN(12, 4));
@@ -2715,7 +2732,8 @@ err_free_netdev:
 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
  * ensure it is awake for probe and init. Request the line and reset the PHY.
  */
-static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
+static int pch_gbe_minnow_platform_init(struct pci_dev *pdev,
+   struct pch_gbe_privdata *pdata)
 {
unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW |
GPIOF_EXPORT | GPIOF_ACTIVE_LOW;
@@ -2724,16 +2742,11 @@ static int pch_gbe_minnow_platform_init(struct pci_dev 
*pdev)
 
ret = devm_gpio_request_one(>dev, gpio, flags,
"minnow_phy_reset");
-   if (ret) {
+   if (!ret)
+   pdata->phy_reset_gpio = gpio_to_desc(gpio);
+   else
dev_err(>dev,
"ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
-   return ret;
-   }
-
-   gpio_set_value(gpio, 1);
-   usleep_range(1250, 1500);
-   gpio_set_value(gpio, 0);
-   usleep_range(1250, 1500);
 
return ret;
 }
-- 
2.6.2

--
To unsubscribe from this list: send the line "unsubscribe netdev" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 19/28] net: pch_gbe: allow build on MIPS platforms

[Paul Burton]

Allow the pch_gbe driver to be built on MIPS platforms, in preparation
for its use on the MIPS Boston board.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
---

 drivers/net/ethernet/oki-semi/pch_gbe/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig 
b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
index 5f7a352..4d3809a 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig
@@ -4,7 +4,7 @@
 
 config PCH_GBE
tristate "OKI SEMICONDUCTOR IOH(ML7223/ML7831) GbE"
-   depends on PCI && (X86_32 || COMPILE_TEST)
+   depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
select MII
select PTP_1588_CLOCK_PCH
select NET_PTP_CLASSIFY
-- 
2.6.2

--
To unsubscribe from this list: send the line "unsubscribe netdev" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 23/28] net: pch_gbe: always reset PHY along with MAC

[Paul Burton]

On the MIPS Boston development board, the EG20T MAC does not report
receiving the RX clock from the (RGMII) RTL8211E PHY unless the PHY is
reset at the same time as the MAC. Since the pch_gbe driver resets the
MAC a number of times - twice during probe, and when taking down the
network interface - we need to reset the PHY at all the same times. Do
that from pch_gbe_mac_reset_hw which is used to reset the MAC in all
cases.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
---

 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 23d28f0..824ff9e 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -378,10 +378,13 @@ static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
 {
/* Read the MAC address. and store to the private data */
pch_gbe_mac_read_mac_addr(hw);
+   pch_gbe_phy_set_reset(hw, 1);
iowrite32(PCH_GBE_ALL_RST, >reg->RESET);
 #ifdef PCH_GBE_MAC_IFOP_RGMII
iowrite32(PCH_GBE_MODE_GMII_ETHER, >reg->MODE);
 #endif
+   pch_gbe_phy_set_reset(hw, 0);
+   usleep_range(1250, 1500);
pch_gbe_wait_clr_bit(>reg->RESET, PCH_GBE_ALL_RST);
/* Setup the receive addresses */
pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
-- 
2.6.2

--
To unsubscribe from this list: send the line "unsubscribe netdev" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 24/28] net: pch_gbe: add device tree support

[Paul Burton]

Introduce support for retrieving the PHY reset GPIO from device tree,
which will be used on the MIPS Boston development board. This requires
support for probe deferral in order to work correctly, since the order
of device probe is not guaranteed & typically the EG20T GPIO controller
device will be probed after the ethernet MAC.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
---

 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   | 33 +-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c 
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 824ff9e..f2a9a38 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -23,6 +23,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #define DRV_VERSION "1.01"
 const char pch_driver_version[] = DRV_VERSION;
@@ -2594,13 +2596,41 @@ static void pch_gbe_remove(struct pci_dev *pdev)
free_netdev(netdev);
 }
 
+static int pch_gbe_parse_dt(struct pci_dev *pdev,
+   struct pch_gbe_privdata **pdata)
+{
+   struct device_node *np = pdev->dev.of_node;
+   struct gpio_desc *gpio;
+
+   if (!config_enabled(CONFIG_OF) || !np)
+   return 0;
+
+   if (!*pdata)
+   *pdata = devm_kzalloc(>dev, sizeof(**pdata), GFP_KERNEL);
+   if (!*pdata)
+   return -ENOMEM;
+
+   gpio = devm_gpiod_get(>dev, "phy-reset", GPIOD_ASIS);
+   if (IS_ERR(gpio))
+   return PTR_ERR(gpio);
+
+   (*pdata)->phy_reset_gpio = gpio;
+   return 0;
+}
+
 static int pch_gbe_probe(struct pci_dev *pdev,
  const struct pci_device_id *pci_id)
 {
struct net_device *netdev;
struct pch_gbe_adapter *adapter;
+   struct pch_gbe_privdata *pdata;
int ret;
 
+   pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
+   ret = pch_gbe_parse_dt(pdev, );
+   if (ret)
+   goto err_out;
+
ret = pcim_enable_device(pdev);
if (ret)
return ret;
@@ -2638,7 +2668,7 @@ static int pch_gbe_probe(struct pci_dev *pdev,
adapter->pdev = pdev;
adapter->hw.back = adapter;
adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
-   adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
+   adapter->pdata = pdata;
if (adapter->pdata && adapter->pdata->platform_init)
adapter->pdata->platform_init(pdev, pdata);
 
@@ -2729,6 +2759,7 @@ err_free_adapter:
pch_gbe_hal_phy_hw_reset(>hw);
 err_free_netdev:
free_netdev(netdev);
+err_out:
return ret;
 }
 
-- 
2.6.2

--
To unsubscribe from this list: send the line "unsubscribe netdev" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html