[PATCH v2 net] net: phy: Fix LED mode in DT single property.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

Fix the LED mode DT parameters combine to a single property
and change the vendor prefix i.e. mscc.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
Change set:
v0: Fix the LED mode DT parameters combine to a single property
v1: Fix the build test ERROR
v2: Add default LED mode "vsc85xx_dt_led_mode_get" function.

 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   | 20 +++
 drivers/net/phy/mscc.c | 65 --
 2 files changed, 45 insertions(+), 40 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt 
b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
index 0eedabe..2253de5 100644
--- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
+++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
@@ -6,12 +6,12 @@ Required properties:
  Documentation/devicetree/bindings/net/phy.txt
 
 Optional properties:
-- vsc8531,vddmac   : The vddmac in mV. Allowed values is listed
+- mscc,vddmac  : The vddmac in mV. Allowed values is listed
  in the first row of Table 1 (below).
  This property is only used in combination
  with the 'edge-slowdown' property.
  Default value is 3300.
-- vsc8531,edge-slowdown: % the edge should be slowed down relative to
+- mscc,edge-slowdown   : % the edge should be slowed down relative to
  the fastest possible edge time.
  Edge rate sets the drive strength of the MAC
  interface output signals.  Changing the
@@ -27,14 +27,11 @@ Optional properties:
  'vddmac'.
  Default value is 0%.
  Ref: Table:1 - Edge rate change (below).
-- vsc8531,led-0-mode   : LED mode. Specify how the LED[0] should behave.
+- mscc,led-mode: LED mode. Specify how the LED[0] and LED[1] 
should behave.
  Allowed values are define in
  "include/dt-bindings/net/mscc-phy-vsc8531.h".
- Default value is VSC8531_LINK_1000_ACTIVITY (1).
-- vsc8531,led-1-mode   : LED mode. Specify how the LED[1] should behave.
- Allowed values are define in
- "include/dt-bindings/net/mscc-phy-vsc8531.h".
- Default value is VSC8531_LINK_100_ACTIVITY (2).
+ Default LED[0] value is VSC8531_LINK_1000_ACTIVITY 
(1).
+ Default LED[1] value is VSC8531_LINK_100_ACTIVITY (2).
 
 Table: 1 - Edge rate change
 |
@@ -66,8 +63,7 @@ Example:
 
 vsc8531_0: ethernet-phy@0 {
 compatible = "ethernet-phy-id0007.0570";
-vsc8531,vddmac = <3300>;
-vsc8531,edge-slowdown  = <7>;
-vsc8531,led-0-mode = ;
-vsc8531,led-1-mode = ;
+mscc,vddmac= /bits/ 16 <3300>;
+mscc,edge-slowdown = /bits/ 8  <7>;
+mscc,led-mode  = ;
 };
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index 650c266..5cd705b 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -385,11 +385,11 @@ static int vsc85xx_edge_rate_magic_get(struct phy_device 
*phydev)
if (!of_node)
return -ENODEV;
 
-   rc = of_property_read_u16(of_node, "vsc8531,vddmac", );
+   rc = of_property_read_u16(of_node, "mscc,vddmac", );
if (rc != 0)
vdd = MSCC_VDDMAC_3300;
 
-   rc = of_property_read_u8(of_node, "vsc8531,edge-slowdown", );
+   rc = of_property_read_u8(of_node, "mscc,edge-slowdown", );
if (rc != 0)
sd = 0;
 
@@ -402,26 +402,43 @@ static int vsc85xx_edge_rate_magic_get(struct phy_device 
*phydev)
return -EINVAL;
 }
 
-static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
-  char *led,
-  u8 default_mode)
+static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, char *led)
 {
struct device *dev = >mdio.dev;
struct device_node *of_node = dev->of_node;
-   u8 led_mode;
-   int err;
+   struct vsc8531_private *vsc8531 = phydev->priv;
+   u8 led_0_mode = VSC8531_LINK_1000_ACTIVITY;
+   u8 led_1_mode = VSC8531_LINK_100_ACTIVITY;
+   const __be32 *paddr_end;
+   const __be32 *paddr;
+   int len;
 
if (!of_node)
return -ENODEV;
 
-   led_mode = default_mode;
-   err = of_property_read_u8(of_node, led, _mode);
-   if (!err &

[PATCH v2 net] net: phy: Fix LED mode in DT single property.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

Fix the LED mode DT parameters combine to a single property
and change the vendor prefix i.e. mscc.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
Change set:
v0: Fix the LED mode DT parameters combine to a single property
v1: Fix the build test ERROR
v2: Add default LED mode "vsc85xx_dt_led_mode_get" function.

 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   | 20 +++
 drivers/net/phy/mscc.c | 65 --
 2 files changed, 45 insertions(+), 40 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt 
b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
index 0eedabe..2253de5 100644
--- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
+++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
@@ -6,12 +6,12 @@ Required properties:
  Documentation/devicetree/bindings/net/phy.txt
 
 Optional properties:
-- vsc8531,vddmac   : The vddmac in mV. Allowed values is listed
+- mscc,vddmac  : The vddmac in mV. Allowed values is listed
  in the first row of Table 1 (below).
  This property is only used in combination
  with the 'edge-slowdown' property.
  Default value is 3300.
-- vsc8531,edge-slowdown: % the edge should be slowed down relative to
+- mscc,edge-slowdown   : % the edge should be slowed down relative to
  the fastest possible edge time.
  Edge rate sets the drive strength of the MAC
  interface output signals.  Changing the
@@ -27,14 +27,11 @@ Optional properties:
  'vddmac'.
  Default value is 0%.
  Ref: Table:1 - Edge rate change (below).
-- vsc8531,led-0-mode   : LED mode. Specify how the LED[0] should behave.
+- mscc,led-mode: LED mode. Specify how the LED[0] and LED[1] 
should behave.
  Allowed values are define in
  "include/dt-bindings/net/mscc-phy-vsc8531.h".
- Default value is VSC8531_LINK_1000_ACTIVITY (1).
-- vsc8531,led-1-mode   : LED mode. Specify how the LED[1] should behave.
- Allowed values are define in
- "include/dt-bindings/net/mscc-phy-vsc8531.h".
- Default value is VSC8531_LINK_100_ACTIVITY (2).
+ Default LED[0] value is VSC8531_LINK_1000_ACTIVITY 
(1).
+ Default LED[1] value is VSC8531_LINK_100_ACTIVITY (2).
 
 Table: 1 - Edge rate change
 |
@@ -66,8 +63,7 @@ Example:
 
 vsc8531_0: ethernet-phy@0 {
 compatible = "ethernet-phy-id0007.0570";
-vsc8531,vddmac = <3300>;
-vsc8531,edge-slowdown  = <7>;
-vsc8531,led-0-mode = ;
-vsc8531,led-1-mode = ;
+mscc,vddmac= /bits/ 16 <3300>;
+mscc,edge-slowdown = /bits/ 8  <7>;
+mscc,led-mode  = ;
 };
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index 650c266..30bc9ec 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -385,11 +385,11 @@ static int vsc85xx_edge_rate_magic_get(struct phy_device 
*phydev)
if (!of_node)
return -ENODEV;
 
-   rc = of_property_read_u16(of_node, "vsc8531,vddmac", );
+   rc = of_property_read_u16(of_node, "mscc,vddmac", );
if (rc != 0)
vdd = MSCC_VDDMAC_3300;
 
-   rc = of_property_read_u8(of_node, "vsc8531,edge-slowdown", );
+   rc = of_property_read_u8(of_node, "mscc,edge-slowdown", );
if (rc != 0)
sd = 0;
 
@@ -402,26 +402,43 @@ static int vsc85xx_edge_rate_magic_get(struct phy_device 
*phydev)
return -EINVAL;
 }
 
-static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
-  char *led,
-  u8 default_mode)
+static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, char *led)
 {
struct device *dev = >mdio.dev;
struct device_node *of_node = dev->of_node;
-   u8 led_mode;
-   int err;
+   struct vsc8531_private *vsc8531 = phydev->priv;
+   u8 led_0_mode = VSC8531_LINK_1000_ACTIVITY;
+   u8 led_1_mode = VSC8531_LINK_100_ACTIVITY;
+   const __be32 *paddr_end;
+   const __be32 *paddr;
+   int len;
 
if (!of_node)
return -ENODEV;
 
-   led_mode = default_mode;
-   err = of_property_read_u8(of_node, led, _mode);
-   if (!err &

[PATCH v1 net] net: phy: Fix LED mode in DT single property.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

Fix the LED mode DT parameters combine to a single property
and change the vendor prefix i.e. mscc.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
Change set:
v0: Fix the LED mode DT parameters combine to a single property
v1: Fix the build test ERROR

 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   | 20 +++-
 drivers/net/phy/mscc.c | 57 --
 2 files changed, 40 insertions(+), 37 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt 
b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
index 0eedabe..2253de5 100644
--- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
+++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
@@ -6,12 +6,12 @@ Required properties:
  Documentation/devicetree/bindings/net/phy.txt
 
 Optional properties:
-- vsc8531,vddmac   : The vddmac in mV. Allowed values is listed
+- mscc,vddmac  : The vddmac in mV. Allowed values is listed
  in the first row of Table 1 (below).
  This property is only used in combination
  with the 'edge-slowdown' property.
  Default value is 3300.
-- vsc8531,edge-slowdown: % the edge should be slowed down relative to
+- mscc,edge-slowdown   : % the edge should be slowed down relative to
  the fastest possible edge time.
  Edge rate sets the drive strength of the MAC
  interface output signals.  Changing the
@@ -27,14 +27,11 @@ Optional properties:
  'vddmac'.
  Default value is 0%.
  Ref: Table:1 - Edge rate change (below).
-- vsc8531,led-0-mode   : LED mode. Specify how the LED[0] should behave.
+- mscc,led-mode: LED mode. Specify how the LED[0] and LED[1] 
should behave.
  Allowed values are define in
  "include/dt-bindings/net/mscc-phy-vsc8531.h".
- Default value is VSC8531_LINK_1000_ACTIVITY (1).
-- vsc8531,led-1-mode   : LED mode. Specify how the LED[1] should behave.
- Allowed values are define in
- "include/dt-bindings/net/mscc-phy-vsc8531.h".
- Default value is VSC8531_LINK_100_ACTIVITY (2).
+ Default LED[0] value is VSC8531_LINK_1000_ACTIVITY 
(1).
+ Default LED[1] value is VSC8531_LINK_100_ACTIVITY (2).
 
 Table: 1 - Edge rate change
 |
@@ -66,8 +63,7 @@ Example:
 
 vsc8531_0: ethernet-phy@0 {
 compatible = "ethernet-phy-id0007.0570";
-vsc8531,vddmac = <3300>;
-vsc8531,edge-slowdown  = <7>;
-vsc8531,led-0-mode = ;
-vsc8531,led-1-mode = ;
+mscc,vddmac= /bits/ 16 <3300>;
+mscc,edge-slowdown = /bits/ 8  <7>;
+mscc,led-mode  = ;
 };
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index 650c266..dc35a90 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -385,11 +385,11 @@ static int vsc85xx_edge_rate_magic_get(struct phy_device 
*phydev)
if (!of_node)
return -ENODEV;
 
-   rc = of_property_read_u16(of_node, "vsc8531,vddmac", );
+   rc = of_property_read_u16(of_node, "mscc,vddmac", );
if (rc != 0)
vdd = MSCC_VDDMAC_3300;
 
-   rc = of_property_read_u8(of_node, "vsc8531,edge-slowdown", );
+   rc = of_property_read_u8(of_node, "mscc,edge-slowdown", );
if (rc != 0)
sd = 0;
 
@@ -402,26 +402,43 @@ static int vsc85xx_edge_rate_magic_get(struct phy_device 
*phydev)
return -EINVAL;
 }
 
-static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
-  char *led,
-  u8 default_mode)
+static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, char *led)
 {
struct device *dev = >mdio.dev;
struct device_node *of_node = dev->of_node;
-   u8 led_mode;
-   int err;
+   struct vsc8531_private *vsc8531 = phydev->priv;
+   u8 led_0_mode = VSC8531_LINK_1000_ACTIVITY;
+   u8 led_1_mode = VSC8531_LINK_100_ACTIVITY;
+   const __be32 *paddr_end;
+   const __be32 *paddr;
+   int len;
 
if (!of_node)
return -ENODEV;
 
-   led_mode = default_mode;
-   err = of_property_read_u8(of_node, led, _mode);
-   if (!err && (led_mode > 15 || led_mode == 7 || led_mode == 11)) {
-

Re: [PATCH v3 net-next] net: phy: Add LED mode driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Rob,

Thank you for code review comments.

On Tue, Feb 21, 2017 at 10:42:38AM -0600, Rob Herring wrote:
> EXTERNAL EMAIL
> 
> 
> > Do i need to change from  "vsc8531, led-0-mode" to "mscc, led-0-mode"
> > Is this your suggestion?
> 
> Well, there shouldn't be a space there, but yess, mscc is the prefix.
> 
> Read my original comments. I also suggested combining this to a single 
> property.
> 

Accepted your comment.
Fix the combining into single property and change prefix to mscc.
I sent the latest code for review. Please review and send your comments.

> Rob

---
Thanks,
Raju

[PATCH net] net: phy: Fix LED mode in DT single property.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

Fix the LED mode DT parameters combine to a single property
and change the vendor prefix i.e. mscc.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   | 20 -
 drivers/net/phy/mscc.c | 50 +-
 2 files changed, 38 insertions(+), 32 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt 
b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
index 0eedabe..2253de5 100644
--- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
+++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
@@ -6,12 +6,12 @@ Required properties:
  Documentation/devicetree/bindings/net/phy.txt
 
 Optional properties:
-- vsc8531,vddmac   : The vddmac in mV. Allowed values is listed
+- mscc,vddmac  : The vddmac in mV. Allowed values is listed
  in the first row of Table 1 (below).
  This property is only used in combination
  with the 'edge-slowdown' property.
  Default value is 3300.
-- vsc8531,edge-slowdown: % the edge should be slowed down relative to
+- mscc,edge-slowdown   : % the edge should be slowed down relative to
  the fastest possible edge time.
  Edge rate sets the drive strength of the MAC
  interface output signals.  Changing the
@@ -27,14 +27,11 @@ Optional properties:
  'vddmac'.
  Default value is 0%.
  Ref: Table:1 - Edge rate change (below).
-- vsc8531,led-0-mode   : LED mode. Specify how the LED[0] should behave.
+- mscc,led-mode: LED mode. Specify how the LED[0] and LED[1] 
should behave.
  Allowed values are define in
  "include/dt-bindings/net/mscc-phy-vsc8531.h".
- Default value is VSC8531_LINK_1000_ACTIVITY (1).
-- vsc8531,led-1-mode   : LED mode. Specify how the LED[1] should behave.
- Allowed values are define in
- "include/dt-bindings/net/mscc-phy-vsc8531.h".
- Default value is VSC8531_LINK_100_ACTIVITY (2).
+ Default LED[0] value is VSC8531_LINK_1000_ACTIVITY 
(1).
+ Default LED[1] value is VSC8531_LINK_100_ACTIVITY (2).
 
 Table: 1 - Edge rate change
 |
@@ -66,8 +63,7 @@ Example:
 
 vsc8531_0: ethernet-phy@0 {
 compatible = "ethernet-phy-id0007.0570";
-vsc8531,vddmac = <3300>;
-vsc8531,edge-slowdown  = <7>;
-vsc8531,led-0-mode = ;
-vsc8531,led-1-mode = ;
+mscc,vddmac= /bits/ 16 <3300>;
+mscc,edge-slowdown = /bits/ 8  <7>;
+mscc,led-mode  = ;
 };
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index 650c266..3e7e9d9 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -385,11 +385,11 @@ static int vsc85xx_edge_rate_magic_get(struct phy_device 
*phydev)
if (!of_node)
return -ENODEV;
 
-   rc = of_property_read_u16(of_node, "vsc8531,vddmac", );
+   rc = of_property_read_u16(of_node, "mscc,vddmac", );
if (rc != 0)
vdd = MSCC_VDDMAC_3300;
 
-   rc = of_property_read_u8(of_node, "vsc8531,edge-slowdown", );
+   rc = of_property_read_u8(of_node, "mscc,edge-slowdown", );
if (rc != 0)
sd = 0;
 
@@ -403,25 +403,43 @@ static int vsc85xx_edge_rate_magic_get(struct phy_device 
*phydev)
 }
 
 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
-  char *led,
-  u8 default_mode)
+  char *led)
 {
struct device *dev = >mdio.dev;
struct device_node *of_node = dev->of_node;
-   u8 led_mode;
-   int err;
+   struct vsc8531_private *vsc8531 = phydev->priv;
+   u8 led_0_mode = VSC8531_LINK_1000_ACTIVITY;
+   u8 led_1_mode = VSC8531_LINK_100_ACTIVITY;
+   const __be32 *paddr_end;
+   const __be32 *paddr;
+   int len;
 
if (!of_node)
return -ENODEV;
 
-   led_mode = default_mode;
-   err = of_property_read_u8(of_node, led, _mode);
-   if (!err && (led_mode > 15 || led_mode == 7 || led_mode == 11)) {
-   phydev_err(phydev, "DT %s invalid\n", led);
+   paddr = of_get_property(of_node, "mscc,led-mode", );
+   if (!paddr)
+  

Re: [PATCH v3 net-next] net: phy: Add LED mode driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Rob,

On Wed, Feb 15, 2017 at 10:45:40AM -0600, Rob Herring wrote:
> EXTERNAL EMAIL
> 
> 
> On Tue, Feb 07, 2017 at 07:10:26PM +0530, Raju Lakkaraju wrote:
> > From: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> >
> > +   Default value is VSC8531_LINK_1000_ACTIVITY (1).
> > +- vsc8531,led-1-mode : LED mode. Specify how the LED[1] should behave.
> 
> You failed to address my comment on v2. vsc8531 is not a vendor prefix.
> Please fix in a new patch since David already applied it.
> 

Accpeted my fault. i missed your comment.
Do i need to change from  "vsc8531, led-0-mode" to "mscc, led-0-mode"
Is this your suggestion?

> Rob

---
Thanks,
Raju.

[PATCH v3 net-next] net: phy: Add LED mode driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

LED Mode:
Microsemi PHY support 2 LEDs (LED[0] and LED[1]) to display different
status information that can be selected by setting LED mode.

LED Mode parameter (vsc8531, led-0-mode) and (vsc8531, led-1-mode) get
from Device Tree.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
Change set:
v0:
- Initial version of LED driver for Microsemi PHYs.
v1:
- Update all review comments given by Andrew.
- Add new header file "mscc-phy-vsc8531.h" to define DT macros.
- Add error/range check for DT LED mode input
v2:
- Fixed x86_64 build error.
v3:
- Update all review comments.
- Fix the error check condition.

 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   | 10 +++
 drivers/net/phy/mscc.c | 85 +-
 include/dt-bindings/net/mscc-phy-vsc8531.h | 29 
 3 files changed, 123 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/net/mscc-phy-vsc8531.h

diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt 
b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
index bdefefc6..0eedabe 100644
--- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
+++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
@@ -27,6 +27,14 @@ Optional properties:
  'vddmac'.
  Default value is 0%.
  Ref: Table:1 - Edge rate change (below).
+- vsc8531,led-0-mode   : LED mode. Specify how the LED[0] should behave.
+ Allowed values are define in
+ "include/dt-bindings/net/mscc-phy-vsc8531.h".
+ Default value is VSC8531_LINK_1000_ACTIVITY (1).
+- vsc8531,led-1-mode   : LED mode. Specify how the LED[1] should behave.
+ Allowed values are define in
+ "include/dt-bindings/net/mscc-phy-vsc8531.h".
+ Default value is VSC8531_LINK_100_ACTIVITY (2).
 
 Table: 1 - Edge rate change
 |
@@ -60,4 +68,6 @@ Example:
 compatible = "ethernet-phy-id0007.0570";
 vsc8531,vddmac = <3300>;
 vsc8531,edge-slowdown  = <7>;
+vsc8531,led-0-mode = ;
+vsc8531,led-1-mode = ;
 };
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index e03ead8..650c266 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 
 enum rgmii_rx_clock_delay {
RGMII_RX_CLK_DELAY_0_2_NS = 0,
@@ -52,6 +53,11 @@ enum rgmii_rx_clock_delay {
 #define MSCC_PHY_DEV_AUX_CNTL28
 #define HP_AUTO_MDIX_X_OVER_IND_MASK 0x2000
 
+#define MSCC_PHY_LED_MODE_SEL29
+#define LED_1_MODE_SEL_MASK  0x00F0
+#define LED_0_MODE_SEL_MASK  0x000F
+#define LED_1_MODE_SEL_POS   4
+
 #define MSCC_EXT_PAGE_ACCESS 31
 #define MSCC_PHY_PAGE_STANDARD   0x /* Standard registers */
 #define MSCC_PHY_PAGE_EXTENDED   0x0001 /* Extended registers */
@@ -99,6 +105,8 @@ enum rgmii_rx_clock_delay {
 
 struct vsc8531_private {
int rate_magic;
+   u8 led_0_mode;
+   u8 led_1_mode;
 };
 
 #ifdef CONFIG_OF_MDIO
@@ -123,6 +131,29 @@ static int vsc85xx_phy_page_set(struct phy_device *phydev, 
u8 page)
return rc;
 }
 
+static int vsc85xx_led_cntl_set(struct phy_device *phydev,
+   u8 led_num,
+   u8 mode)
+{
+   int rc;
+   u16 reg_val;
+
+   mutex_lock(>lock);
+   reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);
+   if (led_num) {
+   reg_val &= ~LED_1_MODE_SEL_MASK;
+   reg_val |= (((u16)mode << LED_1_MODE_SEL_POS) &
+   LED_1_MODE_SEL_MASK);
+   } else {
+   reg_val &= ~LED_0_MODE_SEL_MASK;
+   reg_val |= ((u16)mode & LED_0_MODE_SEL_MASK);
+   }
+   rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);
+   mutex_unlock(>lock);
+
+   return rc;
+}
+
 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
 {
u16 reg_val;
@@ -370,11 +401,41 @@ static int vsc85xx_edge_rate_magic_get(struct phy_device 
*phydev)
 
return -EINVAL;
 }
+
+static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
+  char *led,
+  u8 default_mode)
+{
+   struct device *dev = >mdio.dev;
+   struct device_node *of_node = dev->of_node;
+   u8 led_mode;
+   int err;
+
+   if (!of_node)
+   return -ENODEV;
+
+   led_mode = default_mode;
+   err = of_property_read_u8(of_node, led, _mode);
+   if (!err 

Re: [PATCH v2 net-next] net: phy: Add LED mode driver for Microsemi

[Raju Lakkaraju]

Hi Florian,

Thank you for review comments.

On Wed, Feb 01, 2017 at 10:04:08AM -0800, Florian Fainelli wrote:
> EXTERNAL EMAIL
> 
> 
> On 02/01/2017 04:53 AM, Raju Lakkaraju wrote:
> > From: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> >
> > LED Mode:
> > Microsemi PHY support 2 LEDs (LED[0] and LED[1]) to display different
> > status information that can be selected by setting LED mode.
> 
> Why is this LED selection done through Device Tree/initial configuration
> instead of coming up with a proper LED device registered by the PHY
> which allows you to select exactly how you want the modes to wind-up
> looking like?
> 

I wrote the LED driver similar to "Micrel". Added only LED mode.

> NB: you don't need a cover letter for single patches.
> 
Accepted. I will do.

> >
> > LED Mode parameter (vsc8531, led-0-mode) and (vsc8531, led-1-mode) get from
> > Device Tree.
> >
> > Tested on Beaglebone Black with VSC 8531 PHY.
> >
> > Change set:
> > v0:
> > - Initial version of LED driver for Microsemi PHYs.
> > v1:
> > - Update all review comments given by Andrew.
> > - Add new header file "mscc-phy-vsc8531.h" to define DT macros.
> > - Add error/range check for DT LED mode input
> > v2:
> > - Fixed x86_64 build error.
> >
> > Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> >
> >
> > Raju Lakkaraju (1):
> >   net: phy: Add LED mode driver for Microsemi PHYs.
> >
> >  .../devicetree/bindings/net/mscc-phy-vsc8531.txt   | 10 +++
> >  drivers/net/phy/mscc.c | 85 
> > +-
> >  include/dt-bindings/net/mscc-phy-vsc8531.h | 29 
> >  3 files changed, 123 insertions(+), 1 deletion(-)
> >  create mode 100644 include/dt-bindings/net/mscc-phy-vsc8531.h
> >
> 
> 
> --
> Florian


---
Thanks,
Raju.

Re: [PATCH v2 net-next] net: phy: Add LED mode driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for given review comments.

On Wed, Feb 01, 2017 at 02:55:55PM +0100, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> On Wed, Feb 01, 2017 at 06:23:46PM +0530, Raju Lakkaraju wrote:
> > From: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> >
> > LED Mode:
> > +   "include/dt-bindings/net/mscc-phy-vsc8531.h".
> > +   Default value is 1.
> 
> 1 is not very useful. What does it mean? How about:
> 
> Default value is LINK_1000_ACTIVITY (1)
> 

Accepted.

> > +- vsc8531,led-1-mode : LED mode. Specify how the LED[1] should behave.
> > +   Allowed values are define in
> > + int rc;
> > +
> > + if (!of_node)
> > + return -ENODEV;
> > +
> > + rc = of_property_read_u8(of_node, led, _mode);
> > + if ((rc == 0) &&
> > + ((led_mode > 15) || (led_mode == 7) || (led_mode == 11))) {
> > + phydev_err(phydev, "DT %s invalid\n", led);
> > + return -EINVAL;
> > + } else if (rc == -EINVAL) {
> > + return default_mode;
> > + }
> 
> I don't think you understood my comment about of_property_read_u8()
> not modifying _mode on error. Please read the comment again, and
> simplify this.
> 

If i understand your comment correctly, in case of return value -EINVAL, it
should return error. Am i correct?

i would perfer in case of of_property_read_u8( ) returns -EINVAL, 
i would like to configure LEDs with default state. Shall i configure?

Still if you think i did not understand your comments, please write little
bit more.

> > +
> > + return led_mode;
> > +}
> > +
> >  #else
> >  static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
> >  {
> >   return 0;
> >  }
> > +
> > +static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
> > +char *led,
> > +u8 default_mode)
> > +{
> > + return default_mode;
> > +}
> >  #endif /* CONFIG_OF_MDIO */
> >
> >  static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 
> > edge_rate)
> > @@ -499,6 +562,13 @@ static int vsc85xx_config_init(struct phy_device 
> > *phydev)
> >   if (rc)
> >   return rc;
> >
> > + rc = vsc85xx_led_cntl_set(phydev, 1, vsc8531->led_1_mode);
> > + if (rc)
> > + return rc;
> 
> Blank line please.
> 

Accepted.

> > + rc = vsc85xx_led_cntl_set(phydev, 0, vsc8531->led_0_mode);
> > + if (rc)
> > + return rc;
> > +
> >   rc = genphy_config_init(phydev);
> >
> >   return rc;
> > @@ -555,8 +625,9 @@ static int vsc85xx_read_status(struct phy_device 
> > *phydev)
> > + led_mode = vsc85xx_dt_led_mode_get(phydev, "vsc8531,led-0-mode",
> > +LINK_1000_ACTIVITY);
> > + if (led_mode < 0)
> > + return led_mode;
> > + vsc8531->led_0_mode = led_mode;
> 
> Blank line.
> 

Accepted.

> > + led_mode = vsc85xx_dt_led_mode_get(phydev, "vsc8531,led-1-mode",
> > +LINK_100_ACTIVITY);
> > +#define AUTONEG_FAULT   12
> > +#define SERIAL_MODE 13
> > +#define FORCE_LED_OFF   14
> > +#define FORCE_LED_ON15
> 
> You should prefix these with VSC8531_. Otherwise there is potential to
> have issues with two different PHYs defining some of these frequently
> used macros.
> 

Accepted.

>  Andrew

---
Thanks,
Raju.

[PATCH v2 net-next] net: phy: Add LED mode driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

LED Mode:
Microsemi PHY support 2 LEDs (LED[0] and LED[1]) to display different
status information that can be selected by setting LED mode.

LED Mode parameter (vsc8531, led-0-mode) and (vsc8531, led-1-mode) get
from Device Tree.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   | 10 +++
 drivers/net/phy/mscc.c | 85 +-
 include/dt-bindings/net/mscc-phy-vsc8531.h | 29 
 3 files changed, 123 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/net/mscc-phy-vsc8531.h

diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt 
b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
index bdefefc6..bb7450c 100644
--- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
+++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
@@ -27,6 +27,14 @@ Optional properties:
  'vddmac'.
  Default value is 0%.
  Ref: Table:1 - Edge rate change (below).
+- vsc8531,led-0-mode   : LED mode. Specify how the LED[0] should behave.
+ Allowed values are define in
+ "include/dt-bindings/net/mscc-phy-vsc8531.h".
+ Default value is 1.
+- vsc8531,led-1-mode   : LED mode. Specify how the LED[1] should behave.
+ Allowed values are define in
+ "include/dt-bindings/net/mscc-phy-vsc8531.h".
+ Default value is 2.
 
 Table: 1 - Edge rate change
 |
@@ -60,4 +68,6 @@ Example:
 compatible = "ethernet-phy-id0007.0570";
 vsc8531,vddmac = <3300>;
 vsc8531,edge-slowdown  = <7>;
+vsc8531,led-0-mode = ;
+vsc8531,led-1-mode = ;
 };
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index e03ead8..f0cb7cc 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 
 enum rgmii_rx_clock_delay {
RGMII_RX_CLK_DELAY_0_2_NS = 0,
@@ -52,6 +53,11 @@ enum rgmii_rx_clock_delay {
 #define MSCC_PHY_DEV_AUX_CNTL28
 #define HP_AUTO_MDIX_X_OVER_IND_MASK 0x2000
 
+#define MSCC_PHY_LED_MODE_SEL29
+#define LED_1_MODE_SEL_MASK  0x00F0
+#define LED_0_MODE_SEL_MASK  0x000F
+#define LED_1_MODE_SEL_POS   4
+
 #define MSCC_EXT_PAGE_ACCESS 31
 #define MSCC_PHY_PAGE_STANDARD   0x /* Standard registers */
 #define MSCC_PHY_PAGE_EXTENDED   0x0001 /* Extended registers */
@@ -99,6 +105,8 @@ enum rgmii_rx_clock_delay {
 
 struct vsc8531_private {
int rate_magic;
+   u8 led_0_mode;
+   u8 led_1_mode;
 };
 
 #ifdef CONFIG_OF_MDIO
@@ -123,6 +131,29 @@ static int vsc85xx_phy_page_set(struct phy_device *phydev, 
u8 page)
return rc;
 }
 
+static int vsc85xx_led_cntl_set(struct phy_device *phydev,
+   u8 led_num,
+   u8 mode)
+{
+   int rc;
+   u16 reg_val;
+
+   mutex_lock(>lock);
+   reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);
+   if (led_num) {
+   reg_val &= ~LED_1_MODE_SEL_MASK;
+   reg_val |= (((u16)mode << LED_1_MODE_SEL_POS) &
+   LED_1_MODE_SEL_MASK);
+   } else {
+   reg_val &= ~LED_0_MODE_SEL_MASK;
+   reg_val |= ((u16)mode & LED_0_MODE_SEL_MASK);
+   }
+   rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);
+   mutex_unlock(>lock);
+
+   return rc;
+}
+
 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
 {
u16 reg_val;
@@ -370,11 +401,43 @@ static int vsc85xx_edge_rate_magic_get(struct phy_device 
*phydev)
 
return -EINVAL;
 }
+
+static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
+  char *led,
+  u8 default_mode)
+{
+   struct device *dev = >mdio.dev;
+   struct device_node *of_node = dev->of_node;
+   u8 led_mode;
+   int rc;
+
+   if (!of_node)
+   return -ENODEV;
+
+   rc = of_property_read_u8(of_node, led, _mode);
+   if ((rc == 0) &&
+   ((led_mode > 15) || (led_mode == 7) || (led_mode == 11))) {
+   phydev_err(phydev, "DT %s invalid\n", led);
+   return -EINVAL;
+   } else if (rc == -EINVAL) {
+   return default_mode;
+   }
+
+   return led_mode;
+}
+
 #else
 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
 {
return 0;
 }

[PATCH v2 net-next] net: phy: Add LED mode driver for Microsemi

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

LED Mode:
Microsemi PHY support 2 LEDs (LED[0] and LED[1]) to display different
status information that can be selected by setting LED mode.

LED Mode parameter (vsc8531, led-0-mode) and (vsc8531, led-1-mode) get from
Device Tree.

Tested on Beaglebone Black with VSC 8531 PHY.

Change set:
v0:
- Initial version of LED driver for Microsemi PHYs.
v1:
- Update all review comments given by Andrew.
- Add new header file "mscc-phy-vsc8531.h" to define DT macros.
- Add error/range check for DT LED mode input
v2:
- Fixed x86_64 build error.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>


Raju Lakkaraju (1):
  net: phy: Add LED mode driver for Microsemi PHYs.

 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   | 10 +++
 drivers/net/phy/mscc.c | 85 +-
 include/dt-bindings/net/mscc-phy-vsc8531.h | 29 
 3 files changed, 123 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/net/mscc-phy-vsc8531.h

-- 
2.7.4

[PATCH v1 net-next] net: phy: Add LED mode driver for Microsemi

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

LED Mode:
Microsemi PHY support 2 LEDs (LED[0] and LED[1]) to display different
status information that can be selected by setting LED mode.

LED Mode parameter (vsc8531, led-0-mode) and (vsc8531, led-1-mode) get from
Device Tree.

Tested on Beaglebone Black with VSC 8531 PHY.

Change set:
v0:
- Initial version of LED driver for Microsemi PHYs.
v1:
- Update all review comments given by Andrew.
- Add new header file "mscc-phy-vsc8531.h" to define DT macros.
- Add error/range check for DT LED mode input

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>

Raju Lakkaraju (1):
  net: phy: Add LED mode driver for Microsemi PHYs.

 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   | 10 +++
 drivers/net/phy/mscc.c | 85 +-
 include/dt-bindings/net/mscc-phy-vsc8531.h | 29 
 3 files changed, 123 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/net/mscc-phy-vsc8531.h

-- 
2.7.4

[PATCH v1 net-next] net: phy: Add LED mode driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

LED Mode:
Microsemi PHY support 2 LEDs (LED[0] and LED[1]) to display different
status information that can be selected by setting LED mode.

LED Mode parameter (vsc8531, led-0-mode) and (vsc8531, led-1-mode) get
from Device Tree.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   | 10 +++
 drivers/net/phy/mscc.c | 85 +-
 include/dt-bindings/net/mscc-phy-vsc8531.h | 29 
 3 files changed, 123 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/net/mscc-phy-vsc8531.h

diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt 
b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
index bdefefc6..bb7450c 100644
--- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
+++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
@@ -27,6 +27,14 @@ Optional properties:
  'vddmac'.
  Default value is 0%.
  Ref: Table:1 - Edge rate change (below).
+- vsc8531,led-0-mode   : LED mode. Specify how the LED[0] should behave.
+ Allowed values are define in
+ "include/dt-bindings/net/mscc-phy-vsc8531.h".
+ Default value is 1.
+- vsc8531,led-1-mode   : LED mode. Specify how the LED[1] should behave.
+ Allowed values are define in
+ "include/dt-bindings/net/mscc-phy-vsc8531.h".
+ Default value is 2.
 
 Table: 1 - Edge rate change
 |
@@ -60,4 +68,6 @@ Example:
 compatible = "ethernet-phy-id0007.0570";
 vsc8531,vddmac = <3300>;
 vsc8531,edge-slowdown  = <7>;
+vsc8531,led-0-mode = ;
+vsc8531,led-1-mode = ;
 };
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index e03ead8..3d2f3be 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 
 enum rgmii_rx_clock_delay {
RGMII_RX_CLK_DELAY_0_2_NS = 0,
@@ -52,6 +53,11 @@ enum rgmii_rx_clock_delay {
 #define MSCC_PHY_DEV_AUX_CNTL28
 #define HP_AUTO_MDIX_X_OVER_IND_MASK 0x2000
 
+#define MSCC_PHY_LED_MODE_SEL29
+#define LED_1_MODE_SEL_MASK  0x00F0
+#define LED_0_MODE_SEL_MASK  0x000F
+#define LED_1_MODE_SEL_POS   4
+
 #define MSCC_EXT_PAGE_ACCESS 31
 #define MSCC_PHY_PAGE_STANDARD   0x /* Standard registers */
 #define MSCC_PHY_PAGE_EXTENDED   0x0001 /* Extended registers */
@@ -99,6 +105,8 @@ enum rgmii_rx_clock_delay {
 
 struct vsc8531_private {
int rate_magic;
+   u8 led_0_mode;
+   u8 led_1_mode;
 };
 
 #ifdef CONFIG_OF_MDIO
@@ -123,6 +131,29 @@ static int vsc85xx_phy_page_set(struct phy_device *phydev, 
u8 page)
return rc;
 }
 
+static int vsc85xx_led_cntl_set(struct phy_device *phydev,
+   u8 led_num,
+   u8 mode)
+{
+   int rc;
+   u16 reg_val;
+
+   mutex_lock(>lock);
+   reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);
+   if (led_num) {
+   reg_val &= ~LED_1_MODE_SEL_MASK;
+   reg_val |= (((u16)mode << LED_1_MODE_SEL_POS) &
+   LED_1_MODE_SEL_MASK);
+   } else {
+   reg_val &= ~LED_0_MODE_SEL_MASK;
+   reg_val |= ((u16)mode & LED_0_MODE_SEL_MASK);
+   }
+   rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);
+   mutex_unlock(>lock);
+
+   return rc;
+}
+
 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
 {
u16 reg_val;
@@ -370,11 +401,43 @@ static int vsc85xx_edge_rate_magic_get(struct phy_device 
*phydev)
 
return -EINVAL;
 }
+
+static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
+  char *led,
+  u8 default_mode)
+{
+   struct device *dev = >mdio.dev;
+   struct device_node *of_node = dev->of_node;
+   u8 led_mode;
+   int rc;
+
+   if (!of_node)
+   return -ENODEV;
+
+   rc = of_property_read_u8(of_node, led, _mode);
+   if ((rc == 0) &&
+   ((led_mode > 15) || (led_mode == 7) || (led_mode == 11))) {
+   phydev_err(phydev, "DT %s invalid\n", led);
+   return -EINVAL;
+   } else if (rc == -EINVAL) {
+   return default_mode;
+   }
+
+   return led_mode;
+}
+
 #else
 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
 {
return 0;

Re: [PATCH net-next] net: phy: Add LED mode driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for review and valuable comments.

On Tue, Jan 31, 2017 at 02:30:09PM +0100, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> On Tue, Jan 31, 2017 at 11:16:01AM +0530, Raju Lakkaraju wrote:
> > From: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> >
> > LED Mode:
> > Microsemi PHY support 2 LEDs (LED[0] and LED[1]) to display different
> > status information that can be selected by setting LED mode.
> >
> > LED Mode parameter (vddmac, led-0-mode) and (vddmac, led-1-mode) get
> > from Device Tree.
> 
> Hi Raju
> 
> How is vddmac an LED mode parameter?
> 

Typo. I will correct.
It should be "vsc8531, led-0-mode".

> > Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> > ---
> >  .../devicetree/bindings/net/mscc-phy-vsc8531.txt   | 39 
> >  drivers/net/phy/mscc.c | 72 
> > ++
> >  2 files changed, 111 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt 
> > b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
> > index bdefefc6..1abf4b6 100644
> > --- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
> > +++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
> > @@ -27,6 +27,12 @@ Optional properties:
> > 'vddmac'.
> > Default value is 0%.
> > Ref: Table:1 - Edge rate change (below).
> > +- vsc8531,led-0-mode : LED mode. Specify how the LED[0] should behave.
> > +   Allowed values is listed in the 'PHY LED Mode' -
> > +   Table 2 (below).  Default value is 1.
> > +- vsc8531,led-1-mode : LED mode. Specify how the LED[1] should behave.
> > +   Allowed values is listed in the 'PHY LED Mode' -
> > +   Table 2 (below).  Default value is 2.
> >
> >  Table: 1 - Edge rate change
> >  |
> > @@ -54,10 +60,43 @@ Table: 1 - Edge rate change
> >  | (slowest)  |
> >  |---|
> >
> > +Table: 2 - PHY LED Mode
> > +|---|
> > +| LINK_ACTIVITY  | 0 |
> > +|---|
> > +| LINK_1000_ACTIVITY | 1 |
> > +|---|
> > +| LINK_100_ACTIVITY  | 2 |
> > +|---|
> > +| LINK_10_ACTIVITY   | 3 |
> > +|---|
> > +| LINK_100_1000_ACTIVITY | 4 |
> > +|---|
> > +| LINK_10_1000_ACTIVITY  | 5 |
> > +|---|
> > +| LINK_10_100_ACTIVITY   | 6 |
> > +|---|
> > +| DUPLEX_COLLISION   | 8 |
> > +|---|
> > +| COLLISION  | 9 |
> > +|---|
> > +| ACTIVITY   | 10|
> > +|---|
> > +| AUTONEG_FAULT  | 12|
> > +|---|
> > +| SERIAL_MODE| 13|
> > +|---|
> > +| FORCE_LED_OFF  | 14|
> > +|---|
> > +| FORCE_LED_ON   | 15|
> > +|---|
> > +
> >  Example:
> >
> >  vsc8531_0: ethernet-phy@0 {
> >  compatible = "ethernet-phy-id0007.0570";
> >  vsc8531,vddmac   = <3300>;
> >  vsc8531,edge-slowdown= <7>;
> > +vsc8531,led-0-mode   = <1>;
> > +vsc8531,led-1-mode   = <2>;
> 
> Numbers like this are pretty unreadable. I would suggest adding a header file 
> in
> include/dt-bindings/net/
> 

Accpeted. I will create new header file for DT Macros.

> > +static int vsc85xx_led_cntl_set(struct phy_device *phydev,
> > + u8 

[PATCH net-next] net: phy: Add LED mode driver for Microsemi PHYs

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

LED Mode:
Microsemi PHY support 2 LEDs (LED[0] and LED[1]) to display different
status information that can be selected by setting LED mode.

LED Mode parameter (vddmac, led-0-mode) and (vddmac, led-1-mode) get
from Device Tree.

Tested on Beaglebone Black with VSC 8531 PHY.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>

Raju Lakkaraju (1):
  net: phy: Add LED mode driver for Microsemi PHYs.

 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   | 39 
 drivers/net/phy/mscc.c | 72 ++
 2 files changed, 111 insertions(+)

-- 
2.7.4

[PATCH net-next] net: phy: Add LED mode driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

LED Mode:
Microsemi PHY support 2 LEDs (LED[0] and LED[1]) to display different
status information that can be selected by setting LED mode.

LED Mode parameter (vddmac, led-0-mode) and (vddmac, led-1-mode) get
from Device Tree.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   | 39 
 drivers/net/phy/mscc.c | 72 ++
 2 files changed, 111 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt 
b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
index bdefefc6..1abf4b6 100644
--- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
+++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
@@ -27,6 +27,12 @@ Optional properties:
  'vddmac'.
  Default value is 0%.
  Ref: Table:1 - Edge rate change (below).
+- vsc8531,led-0-mode   : LED mode. Specify how the LED[0] should behave.
+ Allowed values is listed in the 'PHY LED Mode' -
+ Table 2 (below).  Default value is 1.
+- vsc8531,led-1-mode   : LED mode. Specify how the LED[1] should behave.
+ Allowed values is listed in the 'PHY LED Mode' -
+ Table 2 (below).  Default value is 2.
 
 Table: 1 - Edge rate change
 |
@@ -54,10 +60,43 @@ Table: 1 - Edge rate change
 | (slowest)|
 |---|
 
+Table: 2 - PHY LED Mode
+|---|
+| LINK_ACTIVITY| 0 |
+|---|
+| LINK_1000_ACTIVITY   | 1 |
+|---|
+| LINK_100_ACTIVITY| 2 |
+|---|
+| LINK_10_ACTIVITY | 3 |
+|---|
+| LINK_100_1000_ACTIVITY   | 4 |
+|---|
+| LINK_10_1000_ACTIVITY| 5 |
+|---|
+| LINK_10_100_ACTIVITY | 6 |
+|---|
+| DUPLEX_COLLISION | 8 |
+|---|
+| COLLISION| 9 |
+|---|
+| ACTIVITY | 10|
+|---|
+| AUTONEG_FAULT| 12|
+|---|
+| SERIAL_MODE  | 13|
+|---|
+| FORCE_LED_OFF| 14|
+|---|
+| FORCE_LED_ON | 15|
+|---|
+
 Example:
 
 vsc8531_0: ethernet-phy@0 {
 compatible = "ethernet-phy-id0007.0570";
 vsc8531,vddmac = <3300>;
 vsc8531,edge-slowdown  = <7>;
+vsc8531,led-0-mode = <1>;
+vsc8531,led-1-mode = <2>;
 };
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index e03ead8..ec808bf 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -25,6 +25,25 @@ enum rgmii_rx_clock_delay {
RGMII_RX_CLK_DELAY_3_4_NS = 7
 };
 
+enum phy_led_mode {
+   LINK_ACTIVITY   = 0,
+   LINK_1000_ACTIVITY  = 1,
+   LINK_100_ACTIVITY   = 2,
+   LINK_10_ACTIVITY= 3,
+   LINK_100_1000_ACTIVITY  = 4,
+   LINK_10_1000_ACTIVITY   = 5,
+   LINK_10_100_ACTIVITY= 6,
+   LINK_RESERVED   = 7,
+   DUPLEX_COLLISION= 8,
+   COLLISION   = 9,
+   ACTIVITY= 10,
+   LINK_RESERVED_1 = 11,
+   AUTONEG_FAULT   = 12,
+   SERIAL_MODE = 13,
+   FORCE_LED_OFF   = 14,
+   FORCE_LED_ON= 15,
+};
+
 /* Microsemi VSC85xx PHY registers */
 /* IEEE 802. Std Registers */
 #define MSCC_PHY_BYPASS_CONTROL  18
@@ -52,6 +71,11 @@ enum rgmii_rx_clock_delay {
 #define MSCC_PHY_DEV_AUX_CNTL28
 #define HP_AUTO_MDIX_X_OVER_IND_MASK 0x2000
 
+#define MSCC_PHY_LED_MODE_SEL29
+#define LED_1_MODE_SEL_MASK  0x00F0
+#define LED_0_MODE_SEL_MASK  0x000F
+#define LED_1_MODE_SEL_POS   4
+
 #define MSCC_EXT_PAGE_ACCESS 31
 #define MSCC_PHY_PAGE_S

[PATCH v2 net-next 4/4] net: phy: Fix the mdix_ctrl changes

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

PHY drivers to have an eth_tp_mdix_ctrl to indicate what is the configured
MDI setting, and read eth_tp_mdi to indicate what is the current status,

Add new parameter mdix_ctrl in phy_device structure and fix driver.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
 drivers/net/phy/marvell.c   | 4 ++--
 drivers/net/phy/microchip.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index fa31f50..e269262 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -268,7 +268,7 @@ static int marvell_config_aneg(struct phy_device *phydev)
if (err < 0)
return err;
 
-   err = marvell_set_polarity(phydev, phydev->mdix);
+   err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
if (err < 0)
return err;
 
@@ -311,7 +311,7 @@ static int m88e_config_aneg(struct phy_device *phydev)
 */
err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 
-   err = marvell_set_polarity(phydev, phydev->mdix);
+   err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
if (err < 0)
return err;
 
diff --git a/drivers/net/phy/microchip.c b/drivers/net/phy/microchip.c
index eb4db22..12825a5 100644
--- a/drivers/net/phy/microchip.c
+++ b/drivers/net/phy/microchip.c
@@ -111,7 +111,7 @@ static void lan88xx_set_mdix(struct phy_device *phydev)
int buf;
int val;
 
-   switch (phydev->mdix) {
+   switch (phydev->mdix_ctrl) {
case ETH_TP_MDI:
val = LAN88XX_EXT_MODE_CTRL_MDI_;
break;
-- 
2.7.4

[PATCH v2 net-next 0/4] Adding PHY MDI(X) support

[Raju Lakkaraju]

Hi All,

I updated all review comments which were given by Andrew and Florian.

This series add support for PHY MDI(X), and implement it for MSCC phys.

Tested on Beaglebone Black with VSC 8531 PHY.

Please review.

Thanks and regards
Raju.

---
Change set:
v1:
- Initial patch submit the WoL and MDI-X in single set of patches

v2:
- Split the mdi(x) as signal set of patches.
- Remove the out_unlock as suggested by Andrew.
- Add mdix_ctrl parameter in "phy_device" to handle the user configure
  mdi(x). Proposed implementation accepted by Florian.
- phydev->mdix_ctrl initialize with ETH_TP_MDI_AUTO. Ethernet controller
  never initialize this parameter. 
- Fix the mdix changes in marvell and microchip driver.

Raju Lakkaraju (4):
  net: phy: add mdix_ctrl to hold the user configuration.
  net: phy: update the mdix_ctrl with correct value.
  net: phy: Add mdi(x) support in Microsemi PHYs driver
  net: phy: Fix the mdix_ctrl changes

 drivers/net/phy/marvell.c   |   4 +-
 drivers/net/phy/microchip.c |   2 +-
 drivers/net/phy/mscc.c  | 105 
 drivers/net/phy/phy.c   |  10 +++--
 include/linux/phy.h |   1 +
 5 files changed, 107 insertions(+), 15 deletions(-)

-- 
2.7.4

[PATCH v2 net-next 3/4] net: phy: Add mdi(x) support in Microsemi PHYs driver

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

To connect two ports of the same configuration (MDI to MDI or
MDI-X to MDI-X) with a 10/100/1000 Mbit/s connection, an
Ethernet crossover cable is needed to cross over the transmit
and receive signals in the cable, so that they are matched at
the connector level.
When connecting an MDI port to an MDI-X port a straight through
cable is used while to connect two MDI ports or two MDI-X ports
a crossover cable must be used. Conventionally MDI is used on end
devices while MDI-X is used on hubs and switches

Auto MDI-X automatically detects the required cable connection
type and configures the connection appropriately, removing the
need for crossover cables to interconnect switches or connecting
PCs peer-to-peer.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
 drivers/net/phy/mscc.c | 105 +
 1 file changed, 97 insertions(+), 8 deletions(-)

diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index 92018ba..d1e26e1 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -27,6 +27,11 @@ enum rgmii_rx_clock_delay {
 
 /* Microsemi VSC85xx PHY registers */
 /* IEEE 802. Std Registers */
+#define MSCC_PHY_BYPASS_CONTROL  18
+#define DISABLE_HP_AUTO_MDIX_MASK0x0080
+#define DISABLE_PAIR_SWAP_CORR_MASK  0x0020
+#define DISABLE_POLARITY_CORR_MASK   0x0010
+
 #define MSCC_PHY_EXT_PHY_CNTL_1   23
 #define MAC_IF_SELECTION_MASK 0x1800
 #define MAC_IF_SELECTION_GMII 0
@@ -44,12 +49,20 @@ enum rgmii_rx_clock_delay {
 #define EDGE_RATE_CNTL_POS5
 #define EDGE_RATE_CNTL_MASK   0x00E0
 
+#define MSCC_PHY_DEV_AUX_CNTL28
+#define HP_AUTO_MDIX_X_OVER_IND_MASK 0x2000
+
 #define MSCC_EXT_PAGE_ACCESS 31
 #define MSCC_PHY_PAGE_STANDARD   0x /* Standard registers */
 #define MSCC_PHY_PAGE_EXTENDED   0x0001 /* Extended registers */
 #define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
 
 /* Extended Page 1 Registers */
+#define MSCC_PHY_EXT_MODE_CNTL   19
+#define FORCE_MDI_CROSSOVER_MASK 0x000C
+#define FORCE_MDI_CROSSOVER_MDIX 0x000C
+#define FORCE_MDI_CROSSOVER_MDI  0x0008
+
 #define MSCC_PHY_ACTIPHY_CNTL20
 #define DOWNSHIFT_CNTL_MASK  0x001C
 #define DOWNSHIFT_EN 0x0010
@@ -110,6 +123,59 @@ static int vsc85xx_phy_page_set(struct phy_device *phydev, 
u8 page)
return rc;
 }
 
+static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
+{
+   u16 reg_val;
+
+   reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);
+   if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK)
+   *mdix = ETH_TP_MDI_X;
+   else
+   *mdix = ETH_TP_MDI;
+
+   return 0;
+}
+
+static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix)
+{
+   int rc;
+   u16 reg_val;
+
+   reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
+   if ((mdix == ETH_TP_MDI) || (mdix == ETH_TP_MDI_X)) {
+   reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |
+   DISABLE_POLARITY_CORR_MASK  |
+   DISABLE_HP_AUTO_MDIX_MASK);
+   } else {
+   reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |
+DISABLE_POLARITY_CORR_MASK  |
+DISABLE_HP_AUTO_MDIX_MASK);
+   }
+   rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
+   if (rc != 0)
+   return rc;
+
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED);
+   if (rc != 0)
+   return rc;
+
+   reg_val = phy_read(phydev, MSCC_PHY_EXT_MODE_CNTL);
+   reg_val &= ~(FORCE_MDI_CROSSOVER_MASK);
+   if (mdix == ETH_TP_MDI)
+   reg_val |= FORCE_MDI_CROSSOVER_MDI;
+   else if (mdix == ETH_TP_MDI_X)
+   reg_val |= FORCE_MDI_CROSSOVER_MDIX;
+   rc = phy_write(phydev, MSCC_PHY_EXT_MODE_CNTL, reg_val);
+   if (rc != 0)
+   return rc;
+
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
+   if (rc != 0)
+   return rc;
+
+   return genphy_restart_aneg(phydev);
+}
+
 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count)
 {
int rc;
@@ -381,6 +447,7 @@ static int vsc85xx_default_config(struct phy_device *phydev)
int rc;
u16 reg_val;
 
+   phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
mutex_lock(>lock);
rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
if (rc != 0)
@@ -470,6 +537,28 @@ static int vsc85xx_config_intr(struct phy_device *phydev)
return rc;
 }
 
+static int vsc85xx_config_aneg(struct phy_device *phydev)
+{
+   int rc;
+
+   rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl);
+   if (rc < 0)
+   return rc;

[PATCH v2 net-next 2/4] net: phy: update the mdix_ctrl with correct value.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

Update the mdix and mdix_ctrl with corresponding ethtool configuration
parameters.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
 drivers/net/phy/phy.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 73adbaa..ee7e1aa 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -389,7 +389,7 @@ int phy_ethtool_sset(struct phy_device *phydev, struct 
ethtool_cmd *cmd)
 
phydev->duplex = cmd->duplex;
 
-   phydev->mdix = cmd->eth_tp_mdix_ctrl;
+   phydev->mdix_ctrl = cmd->eth_tp_mdix_ctrl;
 
/* Restart the PHY */
phy_start_aneg(phydev);
@@ -443,7 +443,7 @@ int phy_ethtool_ksettings_set(struct phy_device *phydev,
 
phydev->duplex = duplex;
 
-   phydev->mdix = cmd->base.eth_tp_mdix_ctrl;
+   phydev->mdix_ctrl = cmd->base.eth_tp_mdix_ctrl;
 
/* Restart the PHY */
phy_start_aneg(phydev);
@@ -469,7 +469,8 @@ int phy_ethtool_gset(struct phy_device *phydev, struct 
ethtool_cmd *cmd)
cmd->transceiver = phy_is_internal(phydev) ?
XCVR_INTERNAL : XCVR_EXTERNAL;
cmd->autoneg = phydev->autoneg;
-   cmd->eth_tp_mdix_ctrl = phydev->mdix;
+   cmd->eth_tp_mdix_ctrl = phydev->mdix_ctrl;
+   cmd->eth_tp_mdix = phydev->mdix;
 
return 0;
 }
@@ -496,7 +497,8 @@ int phy_ethtool_ksettings_get(struct phy_device *phydev,
 
cmd->base.phy_address = phydev->mdio.addr;
cmd->base.autoneg = phydev->autoneg;
-   cmd->base.eth_tp_mdix_ctrl = phydev->mdix;
+   cmd->base.eth_tp_mdix_ctrl = phydev->mdix_ctrl;
+   cmd->base.eth_tp_mdix = phydev->mdix;
 
return 0;
 }
-- 
2.7.4

[PATCH v2 net-next 1/4] net: phy: add mdix_ctrl to hold the user configuration.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

Add new parameter mdix_ctrl to hold the user configuration.
Existing mdix maintain the current status of MDI(X) crossover performed or
not.
mdix_ctrl can configure either ETH_TP_MDI or ETH_TP_MDI_X orETH_TP_MDI_AUTO.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
 include/linux/phy.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/phy.h b/include/linux/phy.h
index edde28c..bd4e2d6 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -447,6 +447,7 @@ struct phy_device {
struct net_device *attached_dev;
 
u8 mdix;
+   u8 mdix_ctrl;
 
void (*adjust_link)(struct net_device *dev);
 };
-- 
2.7.4

Re: [PATCH net-next 2/2] net: phy: Add Fast Link Failure - 2 set driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

On Tue, Oct 18, 2016 at 12:58:20PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> > > In fact, this looks a lot like netdev features (e.g: checksum
> > > offload), and there seems to be some commonality here between at
> > > least Marvell and Microsemi (for the faster link down reporting),
> > > so maybe we should start adding PHY features similar to netdev
> > > features?
> 
> > Sure.
> >
> > I would like add one flag in phy_device structure:
> > u64 phy_features;
> >
> > In phy_driver structure, i would like to add 2 function pointer as
> >
> > int (*phy_featues_set)(struct phy_device *phydev);
> > int (*phy_featues_get)(struct phy_device *phydev);
> >
> > All the PHY specific features i.e. Fast link failure -2, Downshift, 
> > Loopback etc
> > are the case in feature_set/feature_get functions.
> 
> Please follow how the ethertool features are implemented. So you need
> to extend net/core/ethtool.c to pass these call down, etc.
> 

Sure. I will do.
Do i need to change Ethtool application and submit along with 
downshift driver patch (i.e. ethtool.c, phy.c, cpsw.c and mscc.c changes) ? 
>Andrew

---
Thanks,
Raju.

Re: [PATCH net-next 1/2] net: phy: Add Speed downshift set driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Florian,

Thank you for review comments.

On Mon, Oct 17, 2016 at 05:38:46AM -0700, Florian Fainelli wrote:
> EXTERNAL EMAIL
> 
> 
> On October 17, 2016 12:31:54 AM PDT, Raju Lakkaraju 
> <raju.lakkar...@microsemi.com> wrote:
> >Hi Andrew,
> >
> >Thank you for code review and comments.
> >
> >On Fri, Oct 14, 2016 at 02:12:32PM +0200, Andrew Lunn wrote:
> >> EXTERNAL EMAIL
> >>
> >>
> >> On Fri, Oct 14, 2016 at 05:10:32PM +0530, Raju Lakkaraju wrote:
> >> > From: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> >> >
> >> > For operation in cabling environments that are incompatible with
> >> > 1000BAST-T, VSC8531 device provides an automatic link speed
> >> > downshift operation. When enabled, the device automatically changes
> >> > its 1000BAST-T auto-negotiation to the next slower speed after
> >> > a configured number of failed attempts at 1000BAST-T.
> >> > This feature is useful in setting up in networks using older cable
> >> > installations that include only pairs A and B, and not pairs C and
> >D.
> >>
> >> Any reason not to just turn this on by default when auto-neg is
> >> enabled?
> >>
> >Downshift can enable by default when auto-neg enabled. This is good
> >idea.
> >But we would like to provide option to customer can choose whether this
> >feature need to enable or disable and also configure failure attempts.
> >
> >Do you have any other suggestion how to configure failure attempts?
> 
> Is the speed downshift feature similar to what Intel and Broadcom refer to as 
> wirespeed? I have seen cases with Broadcom PHYs where we had to turn such a 
> feature on to allow auto-negotiation to complete with 4-wire cables, but this 
> had the downside of impacting normal autoneg, so it is left disabled.
> 

Yes. I check the Broadcom wirespeed code. Downshift is similar to wirespeed.
But Broadcom wirespeed configuration in Ethernet controller. 

> I would expect the number of customers using this feature to be fairly 
> limited, so having a tunable to turn this downshift on/off may be acceptable. 
> Ethtool supports a number of tunable parameters now (such as rx_copybreak), 
> there may be room for using something similar for boolean flags like these.
> 

This implementation shows little bit specific to Ethernet controller.
Do you have any PHY specific examples?

In another mail thread, you proposed similar to net device features.
Shall i implement that suggestion here?

> --
> Florian

---
Thanks,
Raju.

Re: [PATCH net-next 2/2] net: phy: Add Fast Link Failure - 2 set driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Florian,

Thank you for review comments.

On Mon, Oct 17, 2016 at 05:51:11AM -0700, Florian Fainelli wrote:
> EXTERNAL EMAIL
> 
> 
> On October 17, 2016 1:13:14 AM PDT, Raju Lakkaraju 
> <raju.lakkar...@microsemi.com> wrote:
> >Hi Andrew,
> >
> >Thank you for code review and comments.
> >
> >On Fri, Oct 14, 2016 at 02:02:28PM +0200, Andrew Lunn wrote:
> >> EXTERNAL EMAIL
> >>
> >>
> >> > On Fri, Oct 14, 2016 at 05:10:33PM +0530, Raju Lakkaraju wrote:
> >> > From: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> >> >
> >> > VSC8531 Fast Link Failure 2 feature enables the PHY to indicate the
> >> > onset of a potential link failure in < 100 usec for 100BASE-TX
> >> > operation. FLF2 is supported through the MDINT (active low) pin.
> >>
> >> Is the MDINT pin specific to this feature, or a general interrupt
> >pin?
> >>
> >
> >MDINT pin is general interrupt. MDINT pin share the interrupt with
> >FLF2 along with another 13 interrupts.
> >
> >> Device tree is used to describe the hardware. It should not really
> >> describe software or configuration. But the borders are a bit
> >> fluffly. Signal edge rates is near to hardware. This is a lot more
> >> towards configuration. So i'm not sure a device tree property is the
> >> correct way to describe this.
> >>
> >> This is also a feature i know other PHYs support. The Marvell PHY has
> >> a "Metro Ethernet" extension which allows it to report link failures
> >> for 1000BASE-T in 10, 20 or 40ms, instead of the usual 750ms. So we
> >> need a generic solution other PHYs can implement.
> >>
> >> As with cable testing, i think it should be an ethtool option.
> >
> >I agree with you.
> >I thought this is one time initialization either enable or disable.
> >if customer need this feature, they can enable in DT.
> >Do you want me to implement through IOCTL instead of Device tree?
> >Do you have any other suggestions?
> 
> As indicated in the other email about speed downshift, we may want to utilize 
> ethtool's ability to modify tunable parameters (small integer, boolean, 
> values) and extend it to cover features offered by PHYs in a way that an user 
> can dynamically turn these features on or off.
> 
> In fact, this looks a lot like netdev features (e.g: checksum offload), and 
> there seems to be some commonality here between at least Marvell and 
> Microsemi (for the faster link down reporting), so maybe we should start 
> adding PHY features similar to netdev features?
> 

Sure. 

I would like add one flag in phy_device structure:
u64 phy_features;

In phy_driver structure, i would like to add 2 function pointer as

int (*phy_featues_set)(struct phy_device *phydev);
int (*phy_featues_get)(struct phy_device *phydev);

All the PHY specific features i.e. Fast link failure -2, Downshift, Loopback etc
are the case in feature_set/feature_get functions.

Is it ok?

> --
> Florian

---
Thanks,
Raju.

Re: [PATCH net-next 2/2] net: phy: Add PHY Auto/Mdi/Mdix set driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Florian/Andrew,

Thank you for review comments.

On Thu, Oct 06, 2016 at 04:09:56AM -0700, Florian Fainelli wrote:
> EXTERNAL EMAIL
> 
> 
> On 10/05/2016 12:18 AM, Andrew Lunn wrote:
>  + phydev->mdix = ETH_TP_MDI_AUTO;
> >>>
> >>> Humm, interesting. The only other driver supporting mdix is the
> >>> Marvell one. It does not do this, it leaves it to its default value of
> >>> ETH_TP_MDI_INVALID. It does however interpret ETH_TP_MDI_INVALID as
> >>> meaning as ETH_TP_MDI_AUTO.
> >>>
> >>> There needs to be consistency here. You either need to do the same as
> >>> the Marvell driver, or you need to modify the Marvell driver to also
> >>> set phydev->mdix to ETH_TP_MDI_AUTO.
> >>>
> >> In Ethtool two variable i.e. eth_tp_mdix_ctrl, eth_tp_mdix use to update
> >> the status. But, driver header is having one variable i.e. mdix.
> >> Driver header should also have another variabl like mdix_ctrl.
> >> Then, Ethtool can get/set the Auto MDIX/MDI.
> >> In case, mdix is not configure with ETH_TP_MDI_AUTO, Ethtool shows error as
> >> "setting MDI not supported"
> 
> Agreed, we currently report eth_tp_mdi and eth_tp_mdi_ctrl using
> phydev->mdix, but this is too limiting.
> 
> >>
> >> Please suggest me if you have any better method to fix this issue.
> >
> > Maybe we should add a new flag for the .flags member of the
> > phy_driver. If PHY_HAS_MDIX is set, the phy core will set phydev->mdix
> > to ETH_TP_MDI_AUTO?
> 
> I agree with Raju here, like most other Ethernet drivers, we should
> allow PHY drivers to have an eth_tp_mdix_ctrl to indicate what is the
> configured MDI setting, and read eth_tp_mdi to indicate what is the
> current status, then ethtool can properly differentiate what is going on.
> 

Andrew, Do you want me to add new flag (mdix_ctrl) or keep it as it is?
These changes are more relevant for mdix get status function.
Do you want to me implement along with mdix get status function? 

> Raju, Andrew, does that work for you?
> --
> Florian

---
Thanks,
Raju.

Re: [PATCH net-next 2/2] net: phy: Add PHY Auto/Mdi/Mdix set driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for code review and valuable comments.

On Wed, Sep 28, 2016 at 10:24:51PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> > + reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
> > + if ((mdix == ETH_TP_MDI) || (mdix == ETH_TP_MDI_X)) {
> > + reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |
> > + DISABLE_POLARITY_CORR_MASK  |
> > + DISABLE_HP_AUTO_MDIX_MASK);
> > + } else {
> > + reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |
> > +  DISABLE_POLARITY_CORR_MASK  |
> > +  DISABLE_HP_AUTO_MDIX_MASK);
> > + }
> > + rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
> > + if (rc != 0)
> > + goto out_unlock;
> > +
> > + rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED);
> > + if (rc != 0)
> > + goto out_unlock;
> > +
> > + reg_val = phy_read(phydev, MSCC_PHY_EXT_MODE_CNTL);
> > + reg_val &= ~(FORCE_MDI_CROSSOVER_MASK);
> > + if (mdix == ETH_TP_MDI)
> > + reg_val |= FORCE_MDI_CROSSOVER_MDI;
> > + else if (mdix == ETH_TP_MDI_X)
> > + reg_val |= FORCE_MDI_CROSSOVER_MDIX;
> > + rc = phy_write(phydev, MSCC_PHY_EXT_MODE_CNTL, reg_val);
> > + if (rc != 0)
> > + goto out_unlock;
> > +
> > + rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
> > +
> > +out_unlock:
> 
> out_unlock seems a bit of an odd name, since you are not unlocking
> anything.
> 

Accepted. I will change.

> I also wonder if you should try to reset to MSCC_PHY_PAGE_STANDARD in
> the error condition?
> 

In case of PHY write error, then PHY page set will also return error.
I would like to return error condition, so return after write failure.

> > +
> > + return rc;
> > +}
> > +
> >  static int vsc85xx_wol_set(struct phy_device *phydev,
> >  struct ethtool_wolinfo *wol)
> >  {
> > @@ -227,6 +281,7 @@ static int vsc85xx_default_config(struct phy_device 
> > *phydev)
> >   int rc;
> >   u16 reg_val;
> >
> > + phydev->mdix = ETH_TP_MDI_AUTO;
> 
> Humm, interesting. The only other driver supporting mdix is the
> Marvell one. It does not do this, it leaves it to its default value of
> ETH_TP_MDI_INVALID. It does however interpret ETH_TP_MDI_INVALID as
> meaning as ETH_TP_MDI_AUTO.
> 
> There needs to be consistency here. You either need to do the same as
> the Marvell driver, or you need to modify the Marvell driver to also
> set phydev->mdix to ETH_TP_MDI_AUTO.
> 
> I don't yet know which of these two is the right thing to do.
> 
> Florian?
> 
> Andrew

For this comment, I responded in another thread.

---
Thanks,
Raju.

Re: [PATCH net-next 2/2] net: phy: Add PHY Auto/Mdi/Mdix set driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Florian/Andrew,

Thank you for review comments.

On Thu, Oct 06, 2016 at 03:57:32AM -0700, Florian Fainelli wrote:
> EXTERNAL EMAIL
> 
> 
> On 09/28/2016 01:24 PM, Andrew Lunn wrote:
> >>  static int vsc85xx_wol_set(struct phy_device *phydev,
> >> struct ethtool_wolinfo *wol)
> >>  {
> >> @@ -227,6 +281,7 @@ static int vsc85xx_default_config(struct phy_device 
> >> *phydev)
> >>  int rc;
> >>  u16 reg_val;
> >>
> >> +phydev->mdix = ETH_TP_MDI_AUTO;
> >
> > Humm, interesting. The only other driver supporting mdix is the
> > Marvell one. It does not do this, it leaves it to its default value of
> > ETH_TP_MDI_INVALID. It does however interpret ETH_TP_MDI_INVALID as
> > meaning as ETH_TP_MDI_AUTO.
> >
> > There needs to be consistency here. You either need to do the same as
> > the Marvell driver, or you need to modify the Marvell driver to also
> > set phydev->mdix to ETH_TP_MDI_AUTO.
> >
> > I don't yet know which of these two is the right thing to do.
> >
> > Florian?
> 
> It's really hard to tell because the other drivers I looked at do not
> necessarily seem to be consistent either. Here, if the MDI status is
> really auto, then this is the correct value to return, if it is unknown,
> it should be ETH_TP_MDI_INVALID.
> 

In mdix get status function, This value will be update as per 
PHY mdix current status.

Shall i configure "phydev->mdix = ETH_TP_MDI_AUTO" as default ?

Andrew, do you have any comments?

> For the Marvell PHY, it sounds like we should be able to determine what
> was configured and return the correct MDI status value
> --
> Florian

---
Thanks,
Raju.

Re: [PATCH net-next 2/2] net: phy: Add Fast Link Failure - 2 set driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for code review and comments.

On Fri, Oct 14, 2016 at 02:02:28PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> > On Fri, Oct 14, 2016 at 05:10:33PM +0530, Raju Lakkaraju wrote:
> > From: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> >
> > VSC8531 Fast Link Failure 2 feature enables the PHY to indicate the
> > onset of a potential link failure in < 100 usec for 100BASE-TX
> > operation. FLF2 is supported through the MDINT (active low) pin.
> 
> Is the MDINT pin specific to this feature, or a general interrupt pin?
> 

MDINT pin is general interrupt. MDINT pin share the interrupt with
FLF2 along with another 13 interrupts.

> Device tree is used to describe the hardware. It should not really
> describe software or configuration. But the borders are a bit
> fluffly. Signal edge rates is near to hardware. This is a lot more
> towards configuration. So i'm not sure a device tree property is the
> correct way to describe this.
> 
> This is also a feature i know other PHYs support. The Marvell PHY has
> a "Metro Ethernet" extension which allows it to report link failures
> for 1000BASE-T in 10, 20 or 40ms, instead of the usual 750ms. So we
> need a generic solution other PHYs can implement.
> 
> As with cable testing, i think it should be an ethtool option.

I agree with you.
I thought this is one time initialization either enable or disable.
if customer need this feature, they can enable in DT.
Do you want me to implement through IOCTL instead of Device tree?
Do you have any other suggestions?

> 
>Andrew

---
Thanks,
Raju.

Re: [PATCH net-next 1/2] net: phy: Add Speed downshift set driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for code review and comments.

On Fri, Oct 14, 2016 at 02:12:32PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> On Fri, Oct 14, 2016 at 05:10:32PM +0530, Raju Lakkaraju wrote:
> > From: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> >
> > For operation in cabling environments that are incompatible with
> > 1000BAST-T, VSC8531 device provides an automatic link speed
> > downshift operation. When enabled, the device automatically changes
> > its 1000BAST-T auto-negotiation to the next slower speed after
> > a configured number of failed attempts at 1000BAST-T.
> > This feature is useful in setting up in networks using older cable
> > installations that include only pairs A and B, and not pairs C and D.
> 
> Any reason not to just turn this on by default when auto-neg is
> enabled?
> 
Downshift can enable by default when auto-neg enabled. This is good idea.
But we would like to provide option to customer can choose whether this
feature need to enable or disable and also configure failure attempts.

Do you have any other suggestion how to configure failure attempts?

> Andrew

---

Thanks,
Raju.

[PATCH net-next 0/2] net: phy: Add Downshift, FLF2 drivers for Microsemi

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

This series adds support to the Speed downshift, Fast Link Failure 2,
set drivers for Microsemi PHYs.

Patch 1/4: Link Speed downshift:
For operation in cabling environments that are incompatible with
1000BAST-T, VSC8531 device provides an automatic link speed
downshift operation. When enabled, the device automatically changes
its 1000BAST-T auto-negotiation to the next slower speed after
a set number of failed attempts at 1000BAST-T.
This feature is useful in setting up in networks using older cable
installations that include only pairs A and B, and not pairs C and D.

Patch 2/4: Fast Link Failure 2:
VSC8531 Fast Link Failure 2 feature enables the PHY to indicate the
onset of a potential link failure in < 100 usec for 100BASE-TX
operation. FLF2 is supported through the MDINT (active low) pin.

All these features tested on Beaglebone Black with VSC 8531 PHY.

Raju Lakkaraju (2):
  net: phy: Add Speed downshift set driver for Microsemi PHYs.
  net: phy: Add Fast Link Failure - 2 set driver for Microsemi PHYs.

 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   |  12 +++
 drivers/net/phy/mscc.c | 120 -
 2 files changed, 131 insertions(+), 1 deletion(-)

-- 
2.7.4

[PATCH net-next 1/2] net: phy: Add Speed downshift set driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

For operation in cabling environments that are incompatible with
1000BAST-T, VSC8531 device provides an automatic link speed
downshift operation. When enabled, the device automatically changes
its 1000BAST-T auto-negotiation to the next slower speed after
a configured number of failed attempts at 1000BAST-T.
This feature is useful in setting up in networks using older cable
installations that include only pairs A and B, and not pairs C and D.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
Signed-off-by: Allan W. Nielsen <allan.niel...@microsemi.com>
---
 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   |  6 ++
 drivers/net/phy/mscc.c | 75 +-
 2 files changed, 80 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt 
b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
index bdefefc6..062d115 100644
--- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
+++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
@@ -27,6 +27,11 @@ Optional properties:
  'vddmac'.
  Default value is 0%.
  Ref: Table:1 - Edge rate change (below).
+- downshift-cnt: When enabled, the device automatically 
changes its
+ 1000BAST-T auto-negotiation to the next slower speed
+ after a 'downshift-cnt' of failed attempts at
+ 1000BAST-T. Allowed values: 0, 2, 3, 4, 5.
+ 0 is default and will disable downshifting.
 
 Table: 1 - Edge rate change
 |
@@ -60,4 +65,5 @@ Example:
 compatible = "ethernet-phy-id0007.0570";
 vsc8531,vddmac = <3300>;
 vsc8531,edge-slowdown  = <7>;
+vsc8531,downshift-cnt   = <3>;
 };
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index 43a7545..e87d9f0 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -46,8 +46,15 @@ enum rgmii_rx_clock_delay {
 
 #define MSCC_EXT_PAGE_ACCESS 31
 #define MSCC_PHY_PAGE_STANDARD   0x /* Standard registers */
+#define MSCC_PHY_PAGE_EXTENDED   0x0001 /* Extended registers */
 #define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
 
+/* Extended Page 1 Registers */
+#define MSCC_PHY_ACTIPHY_CNTL20
+#define DOWNSHIFT_CNTL_MASK  0x000C
+#define DOWNSHIFT_EN 0x0010
+#define DOWNSHIFT_CNTL_POS   2
+
 /* Extended Page 2 Registers */
 #define MSCC_PHY_RGMII_CNTL  20
 #define RGMII_RX_CLK_DELAY_MASK  0x0070
@@ -75,6 +82,7 @@ enum rgmii_rx_clock_delay {
 
 struct vsc8531_private {
int rate_magic;
+   u8  downshift_magic;
 };
 
 #ifdef CONFIG_OF_MDIO
@@ -99,6 +107,31 @@ static int vsc85xx_phy_page_set(struct phy_device *phydev, 
u8 page)
return rc;
 }
 
+static int vsc85xx_downshift_set(struct phy_device *phydev, u8 magic)
+{
+   int rc;
+   u16 reg_val;
+
+   mutex_lock(>lock);
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED);
+   if (rc != 0)
+   goto out_unlock;
+
+   reg_val = phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
+   reg_val &= ~(DOWNSHIFT_CNTL_MASK);
+   reg_val |= magic;
+   rc = phy_write(phydev, MSCC_PHY_ACTIPHY_CNTL, reg_val);
+   if (rc != 0)
+   goto out_unlock;
+
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
+
+out_unlock:
+   mutex_unlock(>lock);
+
+   return rc;
+}
+
 static int vsc85xx_wol_set(struct phy_device *phydev,
   struct ethtool_wolinfo *wol)
 {
@@ -239,11 +272,42 @@ static int vsc85xx_edge_rate_magic_get(struct phy_device 
*phydev)
 
return -EINVAL;
 }
+
+static int vsc85xx_downshift_magic_get(struct phy_device *phydev)
+{
+   int rc;
+   u8 ds;
+   struct device *dev = >mdio.dev;
+   struct device_node *of_node = dev->of_node;
+
+   if (!of_node)
+   return -ENODEV;
+
+   rc = of_property_read_u8(of_node, "vsc8531,downshift-cnt", );
+   if ((rc == -EINVAL) || (ds == 0))
+   return 0;
+   if (ds == 1 || ds > 5) {
+   phydev_err(phydev, "Invalid downshift count\n");
+   return -EINVAL;
+   }
+
+   /* ds is either 2,3,4 or 5 */
+   ds -= 2;
+   ds <<= DOWNSHIFT_CNTL_POS;
+   ds |= DOWNSHIFT_EN;
+
+   return ds;
+}
 #else
 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
 {
return 0;
 }
+
+static int vsc85xx_downshift_magic_get(struct phy_device *phydev)
+{
+   return 0;
+}
 #endif /* CONFIG_OF_MDIO */
 
 stati

[PATCH net-next 2/2] net: phy: Add Fast Link Failure - 2 set driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

VSC8531 Fast Link Failure 2 feature enables the PHY to indicate the
onset of a potential link failure in < 100 usec for 100BASE-TX
operation. FLF2 is supported through the MDINT (active low) pin.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
Signed-off-by: Allan W. Nielsen <allan.niel...@microsemi.com>
---
 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   |  6 +++
 drivers/net/phy/mscc.c | 45 ++
 2 files changed, 51 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt 
b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
index 062d115..472fc68 100644
--- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
+++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
@@ -32,6 +32,11 @@ Optional properties:
  after a 'downshift-cnt' of failed attempts at
  1000BAST-T. Allowed values: 0, 2, 3, 4, 5.
  0 is default and will disable downshifting.
+- flf2 : Fast Link Failure 2 (FLF2) feature enables the PHY
+ to indicate the onset of a potential link failure in
+ < 100 usec for 100BASE-TX operation. FLF2 is
+ supported through the MDINT (active low) pin.
+ Default will be disable flf2.
 
 Table: 1 - Edge rate change
 |
@@ -66,4 +71,5 @@ Example:
 vsc8531,vddmac = <3300>;
 vsc8531,edge-slowdown  = <7>;
 vsc8531,downshift-cnt   = <3>;
+   vsc8531,flf2;
 };
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index e87d9f0..57bd628 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -57,6 +57,7 @@ enum rgmii_rx_clock_delay {
 
 /* Extended Page 2 Registers */
 #define MSCC_PHY_RGMII_CNTL  20
+#define FLF2_ENABLE  0x8000
 #define RGMII_RX_CLK_DELAY_MASK  0x0070
 #define RGMII_RX_CLK_DELAY_POS   4
 
@@ -83,6 +84,7 @@ enum rgmii_rx_clock_delay {
 struct vsc8531_private {
int rate_magic;
u8  downshift_magic;
+   bool flf2;  /* Fast Link Failure-2 Enable/Disable */
 };
 
 #ifdef CONFIG_OF_MDIO
@@ -107,6 +109,33 @@ static int vsc85xx_phy_page_set(struct phy_device *phydev, 
u8 page)
return rc;
 }
 
+static int vsc85xx_flf2_set(struct phy_device *phydev, bool op)
+{
+   int rc;
+   u16 reg_val;
+
+   mutex_lock(>lock);
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
+   if (rc != 0)
+   goto out_unlock;
+
+   reg_val = phy_read(phydev, MSCC_PHY_RGMII_CNTL);
+   if (op)
+   reg_val |= FLF2_ENABLE;
+   else
+   reg_val &= ~FLF2_ENABLE;
+   rc = phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val);
+   if (rc != 0)
+   goto out_unlock;
+
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
+
+out_unlock:
+   mutex_unlock(>lock);
+
+   return rc;
+}
+
 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 magic)
 {
int rc;
@@ -412,6 +441,10 @@ static int vsc85xx_config_init(struct phy_device *phydev)
if (rc)
return rc;
 
+   rc = vsc85xx_flf2_set(phydev, vsc8531->flf2);
+   if (rc)
+   return rc;
+
rc = genphy_config_init(phydev);
 
return rc;
@@ -449,6 +482,11 @@ static int vsc85xx_probe(struct phy_device *phydev)
int rate_magic;
int downshift_magic;
struct vsc8531_private *vsc8531;
+   struct device *dev = >mdio.dev;
+   struct device_node *of_node = dev->of_node;
+
+   if (!of_node)
+   return -ENODEV;
 
rate_magic = vsc85xx_edge_rate_magic_get(phydev);
if (rate_magic < 0)
@@ -466,6 +504,13 @@ static int vsc85xx_probe(struct phy_device *phydev)
vsc8531->rate_magic = rate_magic;
vsc8531->downshift_magic = downshift_magic;
 
+#ifdef CONFIG_OF_MDIO
+   /* Fast Link Failure 2 */
+   vsc8531->flf2 = of_property_read_bool(of_node, "vsc8531,flf2");
+#else
+   vsc8531->flf2 = 0;
+#endif
+
return 0;
 }
 
-- 
2.7.4

[PATCH v8 net-next] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.

Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.

Tested on Beaglebone Black with VSC 8531 PHY.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>

---
All the review comments updated and resending for review.

Change set:
v1:
- Initial version of Edge-rate driver add by using IOCTL.
v2:
- Changed edge-rate parameter to Device Tree with magic number.
v3:
- Added Device Tree documentati0n and edge-rate parameter table.
  Added probe function initialize the vsc8531 private data structure.
v4:
- As per review comment, Device Tree parameters (vddmac, edge-slowdown)
  added.
v5:
- As per review comment, Device Tree Document parameters (vddmac, 
  edge-slowdown) real numbers added. Table number changed from 5 to 1.
v6:
- As per review comment, Removed Device Tree header file. Removed MACROs
  and add ARRAYSIZE
v7:
- As per review comment, Removed '-'s (minus) sign in Edge rate table. 
v8:
- As per review comment, Added DT vddmac, slowdown value error check. 

---

 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   | 22 +++
 drivers/net/phy/mscc.c | 69 +++---
 include/dt-bindings/net/mscc-phy-vsc8531.h | 21 ---
 3 files changed, 59 insertions(+), 53 deletions(-)
 delete mode 100644 include/dt-bindings/net/mscc-phy-vsc8531.h

diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt 
b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
index 99c7eb0..1173498 100644
--- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
+++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
@@ -8,8 +8,7 @@ Required properties:
 Optional properties:
 - vsc8531,vddmac   : The vddmac in mV.
 - vsc8531,edge-slowdown: % the edge should be slowed down relative to
- the fastest possible edge time. Native sign
- need not enter.
+ the fastest possible edge time.
  Edge rate sets the drive strength of the MAC
  interface output signals.  Changing the drive
  strength will affect the edge rate of the output
@@ -18,7 +17,8 @@ Optional properties:
  to reprogram drive strength and in effect slow
  down the edge rate if desired.  Table 1 shows the
  impact to the edge rate per VDDMAC supply for each
- drive strength setting.
+ drive strength setting. VDDMAC supply voltage
+ should be one of the value in Table-1 first row.
  Ref: Table:1 - Edge rate change below.
 
 Note: see dt-bindings/net/mscc-phy-vsc8531.h for applicable values
@@ -29,23 +29,25 @@ Table: 1 - Edge rate change
 |  |
 | 3300 mV  2500 mV 1800 mV 1500 mV |
 |---|
+| 0%   0%  0%  0%  |
+|  |
 | Default  Deafult Default Default |
 | (Fastest)(recommended)   (recommended)   |
 |---|
-| -2%  -3% -5% -6% |
+| 2%   3%  5%  6%  |
 |---|
-| -4%  -6% -9% -14%|
+| 4%   6%  9%  14% |
 |---|
-| -7%  -10%-16%-21%|
+| 7%   10% 16% 21% |
 |(recommended) 

[PATCH v2 net-next] net: phy: Add Wake-on-LAN driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

Wake-on-LAN (WoL) is an Ethernet networking standard that allows 
a computer/device to be turned on or awakened by a network message.

VSC8531 PHY can support this feature configure by driver set function.
WoL status get by driver get function.

Tested on Beaglebone Black with VSC 8531 PHY.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>

---

All the review comments updated and resending for review.

Change set:
v1:
- Initial version of Wake-on-LAN (WoL) driver.
v2:
- As per review comments, code optimized.

---

 drivers/net/phy/mscc.c | 128 +
 1 file changed, 128 insertions(+)

diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index a17573e..77a6671 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 
 enum rgmii_rx_clock_delay {
RGMII_RX_CLK_DELAY_0_2_NS = 0,
@@ -37,6 +38,7 @@ enum rgmii_rx_clock_delay {
 
 #define MII_VSC85XX_INT_MASK 25
 #define MII_VSC85XX_INT_MASK_MASK0xa000
+#define MII_VSC85XX_INT_MASK_WOL 0x0040
 #define MII_VSC85XX_INT_STATUS   26
 
 #define MSCC_PHY_WOL_MAC_CONTROL  27
@@ -52,6 +54,17 @@ enum rgmii_rx_clock_delay {
 #define RGMII_RX_CLK_DELAY_MASK  0x0070
 #define RGMII_RX_CLK_DELAY_POS   4
 
+#define MSCC_PHY_WOL_LOWER_MAC_ADDR  21
+#define MSCC_PHY_WOL_MID_MAC_ADDR22
+#define MSCC_PHY_WOL_UPPER_MAC_ADDR  23
+#define MSCC_PHY_WOL_LOWER_PASSWD24
+#define MSCC_PHY_WOL_MID_PASSWD  25
+#define MSCC_PHY_WOL_UPPER_PASSWD26
+
+#define MSCC_PHY_WOL_MAC_CONTROL 27
+#define SECURE_ON_ENABLE 0x8000
+#define SECURE_ON_PASSWD_LEN_4   0x4000
+
 /* Microsemi PHY ID's */
 #define PHY_ID_VSC8531   0x00070570
 #define PHY_ID_VSC8541   0x00070770
@@ -81,6 +94,117 @@ static int vsc85xx_phy_page_set(struct phy_device *phydev, 
u8 page)
return rc;
 }
 
+static int vsc85xx_wol_set(struct phy_device *phydev,
+  struct ethtool_wolinfo *wol)
+{
+   int rc;
+   u16 reg_val;
+   u8  i;
+   u16 pwd[3] = {0, 0, 0};
+   struct ethtool_wolinfo *wol_conf = wol;
+   u8 *mac_addr = phydev->attached_dev->dev_addr;
+
+   mutex_lock(>lock);
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
+   if (rc != 0)
+   goto out_unlock;
+
+   if (wol->wolopts & WAKE_MAGIC) {
+   /* Store the device address for the magic packet */
+   for (i = 0; i < ARRAY_SIZE(pwd); i++)
+   pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 |
+mac_addr[5 - i * 2];
+   phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]);
+   phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]);
+   phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]);
+   } else {
+   phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
+   phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
+   phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
+   }
+
+   if (wol_conf->wolopts & WAKE_MAGICSECURE) {
+   for (i = 0; i < ARRAY_SIZE(pwd); i++)
+   pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 |
+wol_conf->sopass[5 - i * 2];
+   phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]);
+   phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]);
+   phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]);
+   } else {
+   phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
+   phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
+   phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
+   }
+
+   reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
+   if (wol_conf->wolopts & WAKE_MAGICSECURE)
+   reg_val |= SECURE_ON_ENABLE;
+   else
+   reg_val &= ~SECURE_ON_ENABLE;
+   phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
+
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
+   if (rc != 0)
+   goto out_unlock;
+
+   if (wol->wolopts & WAKE_MAGIC) {
+   /* Enable the WOL interrupt */
+   reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
+   reg_val |= MII_VSC85XX_INT_MASK_WOL;
+   rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
+   if (rc != 0)
+   goto out_unlock;
+   } else {
+   /* Disable the WOL interrupt */
+   reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
+   reg_val &= (~MII_VSC85XX_INT_MASK_WOL);
+   r

Re: [PATCH v7 net-next] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for review comment.

On Tue, Oct 04, 2016 at 04:34:50PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> > v7:
> > - As per review comment, Removed '-'s (minus) sign in Edge rate table.
> 
> Still no exact match on the table.
> 
> So if i specify a voltage of 3301, 53% slowdown it looks i will
> actually get 0% slowdown and no error message. That is not very
> helpful.
> 

According to my understanding, User should choose the right VDDMAC voltage
(i.e. 3.3V or 2.5V or 1.8V or 1.5V).

Do you want me to add an error trace which will inform the user that the 
configured values can not be supported - or if the driver should pick 
the "closest" value it can support (or both).

Please suggest me.

> Andrew

---
Thanks,
Raju.

Re: [PATCH net-next 2/2] net: phy: Add PHY Auto/Mdi/Mdix set driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for code review and valuable comments.

On Wed, Sep 28, 2016 at 10:24:51PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> > + reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
> > + if ((mdix == ETH_TP_MDI) || (mdix == ETH_TP_MDI_X)) {
> > + reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |
> > + DISABLE_POLARITY_CORR_MASK  |
> > + DISABLE_HP_AUTO_MDIX_MASK);
> > + } else {
> > + reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |
> > +  DISABLE_POLARITY_CORR_MASK  |
> > +  DISABLE_HP_AUTO_MDIX_MASK);
> > + }
> > + rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
> > + if (rc != 0)
> > + goto out_unlock;
> > +
> > + rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED);
> > + if (rc != 0)
> > + goto out_unlock;
> > +
> > + reg_val = phy_read(phydev, MSCC_PHY_EXT_MODE_CNTL);
> > + reg_val &= ~(FORCE_MDI_CROSSOVER_MASK);
> > + if (mdix == ETH_TP_MDI)
> > + reg_val |= FORCE_MDI_CROSSOVER_MDI;
> > + else if (mdix == ETH_TP_MDI_X)
> > + reg_val |= FORCE_MDI_CROSSOVER_MDIX;
> > + rc = phy_write(phydev, MSCC_PHY_EXT_MODE_CNTL, reg_val);
> > + if (rc != 0)
> > + goto out_unlock;
> > +
> > + rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
> > +
> > +out_unlock:
> 
> out_unlock seems a bit of an odd name, since you are not unlocking
> anything.
> 

It's my mistake. Mutex should be there. I will add mutex.

> I also wonder if you should try to reset to MSCC_PHY_PAGE_STANDARD in
> the error condition?
> 

> > +
> > + return rc;
> > +}
> > +
> >  static int vsc85xx_wol_set(struct phy_device *phydev,
> >  struct ethtool_wolinfo *wol)
> >  {
> > @@ -227,6 +281,7 @@ static int vsc85xx_default_config(struct phy_device 
> > *phydev)
> >   int rc;
> >   u16 reg_val;
> >
> > + phydev->mdix = ETH_TP_MDI_AUTO;
> 
> Humm, interesting. The only other driver supporting mdix is the
> Marvell one. It does not do this, it leaves it to its default value of
> ETH_TP_MDI_INVALID. It does however interpret ETH_TP_MDI_INVALID as
> meaning as ETH_TP_MDI_AUTO.
> 
> There needs to be consistency here. You either need to do the same as
> the Marvell driver, or you need to modify the Marvell driver to also
> set phydev->mdix to ETH_TP_MDI_AUTO.
> 
In Ethtool two variable i.e. eth_tp_mdix_ctrl, eth_tp_mdix use to update
the status. But, driver header is having one variable i.e. mdix.
Driver header should also have another variabl like mdix_ctrl.
Then, Ethtool can get/set the Auto MDIX/MDI.
In case, mdix is not configure with ETH_TP_MDI_AUTO, Ethtool shows error as
"setting MDI not supported"

Please suggest me if you have any better method to fix this issue.

> I don't yet know which of these two is the right thing to do.
> 
> Florian?
> 
> Andrew

---
Thanks,
Raju.

Re: [PATCH net-next 1/2] net: phy: Add Wake-on-LAN driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Florian,

Thank you for code review and valuable comments.


On Wed, Sep 28, 2016 at 10:37:07AM -0700, Florian Fainelli wrote:
> EXTERNAL EMAIL
> 
> 
> On 09/28/2016 05:01 AM, Raju Lakkaraju wrote:
> > From: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> >
> > Wake-on-LAN (WoL) is an Ethernet networking standard that allows
> > a computer/device to be turned on or awakened by a network message.
> > VSC8531 PHY can support this feature configure by driver set function.
> > WoL status get by driver get function.
> >
> > Tested on Beaglebone Black with VSC 8531 PHY.
> >
> > Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> > ---
> >  drivers/net/phy/mscc.c | 132 
> > +
> >  1 file changed, 132 insertions(+)
> >
> > diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
> > index d350deb..ca6ea23 100644
> > --- a/drivers/net/phy/mscc.c
> > +++ b/drivers/net/phy/mscc.c
> > @@ -11,6 +11,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >
> >  enum rgmii_rx_clock_delay {
> >   RGMII_RX_CLK_DELAY_0_2_NS = 0,
> > @@ -35,6 +36,7 @@ enum rgmii_rx_clock_delay {
> >
> >  #define MII_VSC85XX_INT_MASK   25
> >  #define MII_VSC85XX_INT_MASK_MASK  0xa000
> > +#define MII_VSC85XX_INT_MASK_WOL   0x0040
> >  #define MII_VSC85XX_INT_STATUS 26
> >
> >  #define MSCC_EXT_PAGE_ACCESS   31
> > @@ -46,6 +48,19 @@ enum rgmii_rx_clock_delay {
> >  #define RGMII_RX_CLK_DELAY_MASK0x0070
> >  #define RGMII_RX_CLK_DELAY_POS 4
> >
> > +#define MSCC_PHY_WOL_LOWER_MAC_ADDR21
> > +#define MSCC_PHY_WOL_MID_MAC_ADDR  22
> > +#define MSCC_PHY_WOL_UPPER_MAC_ADDR23
> > +#define MSCC_PHY_WOL_LOWER_PASSWD  24
> > +#define MSCC_PHY_WOL_MID_PASSWD25
> > +#define MSCC_PHY_WOL_UPPER_PASSWD  26
> > +
> > +#define MSCC_PHY_WOL_MAC_CONTROL   27
> > +#define EDGE_RATE_CNTL_POS 5
> > +#define EDGE_RATE_CNTL_MASK0x00E0
> > +#define SECURE_ON_ENABLE   0x8000
> > +#define SECURE_ON_PASSWD_LEN_4 0x4000
> > +
> >  /* Microsemi PHY ID's */
> >  #define PHY_ID_VSC8531 0x00070570
> >  #define PHY_ID_VSC8541 0x00070770
> > @@ -58,6 +73,119 @@ static int vsc85xx_phy_page_set(struct phy_device 
> > *phydev, u8 page)
> >   return rc;
> >  }
> >
> > +static int vsc85xx_wol_set(struct phy_device *phydev,
> > +struct ethtool_wolinfo *wol)
> > +{
> > + int rc;
> > + u16 reg_val;
> > + struct ethtool_wolinfo *wol_conf = wol;
> > +
> > + mutex_lock(>lock);
> 
> This mutex is used here because you are using an indirect page access,
> right? This is not to protect against multiple calls of wol_set from
> different executing threads?
> 

Correct. mutex is used for indirect page access.

I did find any protect against multiple calls of wol_set in other vendors.
Do you have any suggestions?

> > + rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
> > + if (rc != 0)
> > + goto out_unlock;
> > +
> > + if (wol->wolopts & WAKE_MAGIC) {
> > + /* Store the device address for the magic packet */
> > + reg_val = phydev->attached_dev->dev_addr[4] << 8;
> > + reg_val |= phydev->attached_dev->dev_addr[5];
> > + phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, reg_val);
> > + reg_val = phydev->attached_dev->dev_addr[2] << 8;
> > + reg_val |= phydev->attached_dev->dev_addr[3];
> > + phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, reg_val);
> > + reg_val = phydev->attached_dev->dev_addr[0] << 8;
> > + reg_val |= phydev->attached_dev->dev_addr[1];
> > + phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, reg_val);
> > + } else {
> > + phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
> > + phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
> > + phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
> > + }
> > +
> > + reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
> > + if (wol_conf->wolopts & WAKE_MAGICSECURE)
> > + reg_val |= SECURE_ON_ENABLE;
> > + else
> > + reg_va

Re: [PATCH net-next 1/2] net: phy: Add Wake-on-LAN driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for code review and valuable comments.

On Wed, Sep 28, 2016 at 06:27:05PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> > +#define MSCC_PHY_WOL_MAC_CONTROL   27
> > +#define EDGE_RATE_CNTL_POS 5
> > +#define EDGE_RATE_CNTL_MASK0x00E0
> 
> This patch does not require these two #defines.
> 
> Please indicate in the cover note if the patches depends on other
> patches in order to cleanly apply. Or if these patches are going to
> conflict with some other patches.
> 

Accepted. I will remove those 2 defines.

> > + reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
> > + if (wol_conf->wolopts & WAKE_MAGICSECURE)
> > + reg_val |= SECURE_ON_ENABLE;
> > + else
> > + reg_val &= ~SECURE_ON_ENABLE;
> > + phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
> > +
> > + if (wol_conf->wolopts & WAKE_MAGICSECURE) {
> > + reg_val = wol_conf->sopass[4] << 8;
> > + reg_val |= wol_conf->sopass[5];
> > + phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, reg_val);
> > + reg_val = wol_conf->sopass[2] << 8;
> > + reg_val |= wol_conf->sopass[3];
> > + phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, reg_val);
> > + reg_val = wol_conf->sopass[0] << 8;
> > + reg_val |= wol_conf->sopass[1];
> > + phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, reg_val);
> > + } else {
> > + phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
> > + phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
> > + phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
> > + }
> 
> Wouldn't it be better to set the password, and then enable the
> password feature?
> 

Accepted. I will change.

> I don't know much about WOL. Hopefully Florian will add further
> comments.
> 
>  Andrew

---
Thanks,
Raju.

Re: [PATCH v6 net-next] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for review comments.
I accepted your review comment and change the code.
I resent for code review.

Thanks,
Raju.

On Tue, Oct 04, 2016 at 02:53:19PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> > Regarding remove the -'s in table, PHY data sheet descript the
> > concept of edge rate with table. I would like to keep the same table
> > in driver.
> 
> The double negative makes the code ugly. Plus a negative slowdown is a
> speed up! The kernel maintainability and sanity comes first, and if
> the data sheet is crazy, because it uses negative slows downs, it
> should be ignored. Get the data sheet fixed
> 
>Andrew

[PATCH v7 net-next] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.

Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.

Tested on Beaglebone Black with VSC 8531 PHY.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>

---
All the review comments updated and resending for review.

Change set:
v1:
- Initial version of Edge-rate driver add by using IOCTL.
v2:
- Changed edge-rate parameter to Device Tree with magic number.
v3:
- Added Device Tree documentati0n and edge-rate parameter table.
  Added probe function initialize the vsc8531 private data structure.
v4:
- As per review comment, Device Tree parameters (vddmac, edge-slowdown)
  added.
v5:
- As per review comment, Device Tree Document parameters (vddmac, 
  edge-slowdown) real numbers added. Table number changed from 5 to 1.
v6:
- As per review comment, Removed Device Tree header file. Removed MACROs
  and add ARRAYSIZE
v7:
- As per review comment, Removed '-'s (minus) sign in Edge rate table. 

---

 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   |  3 +-
 drivers/net/phy/mscc.c | 43 --
 include/dt-bindings/net/mscc-phy-vsc8531.h | 21 ---
 3 files changed, 26 insertions(+), 41 deletions(-)
 delete mode 100644 include/dt-bindings/net/mscc-phy-vsc8531.h

diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt 
b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
index 99c7eb0..241841c 100644
--- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
+++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
@@ -18,7 +18,8 @@ Optional properties:
  to reprogram drive strength and in effect slow
  down the edge rate if desired.  Table 1 shows the
  impact to the edge rate per VDDMAC supply for each
- drive strength setting.
+ drive strength setting. VDDMAC supply voltage
+ should be one of the value in Table-1 first row.
  Ref: Table:1 - Edge rate change below.
 
 Note: see dt-bindings/net/mscc-phy-vsc8531.h for applicable values
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index a17573e..b40cf18c 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -12,7 +12,6 @@
 #include 
 #include 
 #include 
-#include 
 
 enum rgmii_rx_clock_delay {
RGMII_RX_CLK_DELAY_0_2_NS = 0,
@@ -56,16 +55,18 @@ enum rgmii_rx_clock_delay {
 #define PHY_ID_VSC8531   0x00070570
 #define PHY_ID_VSC8541   0x00070770
 
+#define MSCC_SLOWDOWN_MAX8
+
 struct edge_rate_table {
u16 vddmac;
-   int slowdown[MSCC_SLOWDOWN_MAX];
+   u8 slowdown[MSCC_SLOWDOWN_MAX];
 };
 
-struct edge_rate_table edge_table[MSCC_VDDMAC_MAX] = {
-   {3300, { 0, -2, -4,  -7,  -10, -17, -29, -53} },
-   {2500, { 0, -3, -6,  -10, -14, -23, -37, -63} },
-   {1800, { 0, -5, -9,  -16, -23, -35, -52, -76} },
-   {1500, { 0, -6, -14, -21, -29, -42, -58, -77} },
+static const struct edge_rate_table edge_table[] = {
+   {3300, { 0, 2, 4,  7,  10, 17, 29, 53} },
+   {2500, { 0, 3, 6,  10, 14, 23, 37, 63} },
+   {1800, { 0, 5, 9,  16, 23, 35, 52, 76} },
+   {1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
 };
 
 struct vsc8531_private {
@@ -81,21 +82,26 @@ static int vsc85xx_phy_page_set(struct phy_device *phydev, 
u8 page)
return rc;
 }
 
-static u8 edge_rate_magic_get(u16 vddmac,
- int slowdown)
+static u8 vsc85xx_edge_rate_magic_get(u16 vddmac,
+ u8 slowdown)
 {
-   int rc = (MSCC_SLOWDOWN_MAX - 1);
+   int rc = (ARRAY_SIZE(edge_table[0].slowdown) - 1);
u8 vdd;
u8 sd;
 
-   for (vdd = 0; vdd < MSCC_VDDMAC_MAX; vdd++) {
+   for (vdd = 0; vdd < ARRAY_SIZE(edge_table); vdd++) {
if (edge_table[vdd].vddmac == vddmac) {
-

Re: [PATCH v6 net-next] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for review comment.
In another thread, I wrote my comment as below.

-
> In edge_table, remove the -'s and call edge_rate_magic_get with 
> positive values. The table is also missing "static const".
> edge_rate_magic_get is missing its prefix, so keeping the name space 
> clean.
> 

I will add "static const" to table and also add prefix vsc85xx_ to 
edge_rate_magic_get function.

Regarding remove the -'s in table, PHY data sheet descript the concept of edge 
rate with table. I would like to keep the same table in driver.

> Since you are using real values, you can remove mscc-phy-vsc8531.h.
-

But I did not see your comment. I though you accepted to keep the table
as in PHY Data sheet. 

Is any thing wrong if i keep in table with '-' (minus) values?

Thanks,
Raju.

On Tue, Oct 04, 2016 at 01:51:32PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> On Tue, Oct 04, 2016 at 05:11:12PM +0530, Raju Lakkaraju wrote:
> > From: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> >
> > Edge-rate:
> > As system and networking speeds increase, a signal's output transition,
> > also know as the edge rate or slew rate (V/ns), takes on greater importance
> > because high-speed signals come with a price. That price is an assortment of
> > interference problems like ringing on the line, signal overshoot and
> > undershoot, extended signal settling times, crosstalk noise, transmission
> > line reflections, false signal detection by the receiving device and
> > electromagnetic interference (EMI) -- all of which can negate the potential
> > gains designers are seeking when they try to increase system speeds through
> > the use of higher performance logic devices. The fact is, faster signaling
> > edge rates can cause a higher level of electrical noise or other type of
> > interference that can actually lead to slower line speeds and lower maximum
> > system frequencies. This parameter allow the board designers to change the
> > driving strange, and thereby change the EMI behavioral.
> >
> > Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
> >
> > Tested on Beaglebone Black with VSC 8531 PHY.
> >
> > Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> >
> > ---
> > All the review comments updated and resending for review.
> >
> > Change set:
> > v1:
> > - Initial version of Edge-rate driver add by using IOCTL.
> > v2:
> > - Changed edge-rate parameter to Device Tree with magic number.
> > v3:
> > - Added Device Tree documentati0n and edge-rate parameter table.
> >   Added probe function initialize the vsc8531 private data structure.
> > v4:
> > - As per review comment, Device Tree parameters (vddmac, edge-slowdown)
> >   added.
> > v5:
> > - As per review comment, Device Tree Document parameters (vddmac,
> >   edge-slowdown) real numbers added. Table number changed from 5 to 1.
> > v6:
> > - As per review comment, Removed Device Tree header file. Removed MACROs
> >   and add ARRAYSIZE
> 
> But you ignored my request to make the table values positive, and to
> enforce an exact match in the table.
> 
> NACK
> 
> Andrew

[PATCH v6 net-next] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.

Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.

Tested on Beaglebone Black with VSC 8531 PHY.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>

---
All the review comments updated and resending for review.

Change set:
v1:
- Initial version of Edge-rate driver add by using IOCTL.
v2:
- Changed edge-rate parameter to Device Tree with magic number.
v3:
- Added Device Tree documentati0n and edge-rate parameter table.
  Added probe function initialize the vsc8531 private data structure.
v4:
- As per review comment, Device Tree parameters (vddmac, edge-slowdown)
  added.
v5:
- As per review comment, Device Tree Document parameters (vddmac, 
  edge-slowdown) real numbers added. Table number changed from 5 to 1.
v6:
- As per review comment, Removed Device Tree header file. Removed MACROs
  and add ARRAYSIZE 

---

 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   |  3 ++-
 drivers/net/phy/mscc.c | 29 --
 include/dt-bindings/net/mscc-phy-vsc8531.h | 21 
 3 files changed, 18 insertions(+), 35 deletions(-)
 delete mode 100644 include/dt-bindings/net/mscc-phy-vsc8531.h

diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt 
b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
index 99c7eb0..241841c 100644
--- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
+++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
@@ -18,7 +18,8 @@ Optional properties:
  to reprogram drive strength and in effect slow
  down the edge rate if desired.  Table 1 shows the
  impact to the edge rate per VDDMAC supply for each
- drive strength setting.
+ drive strength setting. VDDMAC supply voltage
+ should be one of the value in Table-1 first row.
  Ref: Table:1 - Edge rate change below.
 
 Note: see dt-bindings/net/mscc-phy-vsc8531.h for applicable values
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index a17573e..e25786e 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -12,7 +12,6 @@
 #include 
 #include 
 #include 
-#include 
 
 enum rgmii_rx_clock_delay {
RGMII_RX_CLK_DELAY_0_2_NS = 0,
@@ -56,12 +55,14 @@ enum rgmii_rx_clock_delay {
 #define PHY_ID_VSC8531   0x00070570
 #define PHY_ID_VSC8541   0x00070770
 
+#define MSCC_SLOWDOWN_MAX8
+
 struct edge_rate_table {
u16 vddmac;
int slowdown[MSCC_SLOWDOWN_MAX];
 };
 
-struct edge_rate_table edge_table[MSCC_VDDMAC_MAX] = {
+static const struct edge_rate_table edge_table[] = {
{3300, { 0, -2, -4,  -7,  -10, -17, -29, -53} },
{2500, { 0, -3, -6,  -10, -14, -23, -37, -63} },
{1800, { 0, -5, -9,  -16, -23, -35, -52, -76} },
@@ -81,18 +82,21 @@ static int vsc85xx_phy_page_set(struct phy_device *phydev, 
u8 page)
return rc;
 }
 
-static u8 edge_rate_magic_get(u16 vddmac,
- int slowdown)
+static u8 vsc85xx_edge_rate_magic_get(u16 vddmac,
+ int slowdown)
 {
-   int rc = (MSCC_SLOWDOWN_MAX - 1);
+   int rc = (ARRAY_SIZE(edge_table[0].slowdown) - 1);
u8 vdd;
u8 sd;
 
-   for (vdd = 0; vdd < MSCC_VDDMAC_MAX; vdd++) {
+   for (vdd = 0; vdd < ARRAY_SIZE(edge_table); vdd++) {
if (edge_table[vdd].vddmac == vddmac) {
-   for (sd = 0; sd < MSCC_SLOWDOWN_MAX; sd++) {
+   for (sd = 0;
+sd < ARRAY_SIZE(edge_table[0].slowdown);
+sd++) {
if (edge_table[vdd].slowdown[sd] <= slowdown) {
-   rc = (MSCC_SLOWDOWN_MAX - sd - 1);
+   rc = (ARRAY_

Re: [PATCH v5 net-next] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for comments. I will fix and send the patch.

Thanks,
Raju.

On Tue, Oct 04, 2016 at 08:54:01AM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> On Tue, Oct 04, 2016 at 12:48:59AM -0400, David Miller wrote:
> > From: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> > Date: Mon, 3 Oct 2016 12:53:13 +0530
> >
> > > From: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> > >
> > > Edge-rate:
> > > As system and networking speeds increase, a signal's output transition,
> > > also know as the edge rate or slew rate (V/ns), takes on greater 
> > > importance
> > > because high-speed signals come with a price. That price is an assortment 
> > > of
> > > interference problems like ringing on the line, signal overshoot and
> > > undershoot, extended signal settling times, crosstalk noise, transmission
> > > line reflections, false signal detection by the receiving device and
> > > electromagnetic interference (EMI) -- all of which can negate the 
> > > potential
> > > gains designers are seeking when they try to increase system speeds 
> > > through
> > > the use of higher performance logic devices. The fact is, faster signaling
> > > edge rates can cause a higher level of electrical noise or other type of
> > > interference that can actually lead to slower line speeds and lower 
> > > maximum
> > > system frequencies. This parameter allow the board designers to change the
> > > driving strange, and thereby change the EMI behavioral.
> > >
> > > Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
> > >
> > > Tested on Beaglebone Black with VSC 8531 PHY.
> > >
> > > Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> >
> > Applied, thanks.
> 
> Oh dear. It was not ready for acceptance yet. I guess you missed all
> the discussion because it was attached to the previous version of the
> patch.
> 
> Raju you now need to submit fixup patches relative to the version
> David has accepted, to fix the issues we were discussing.
> 

Accepted.

>   Andrew
> 

Re: [PATCH v4 net-next] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,


On Mon, Oct 03, 2016 at 09:56:56AM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> > > > +vsc8531_0: ethernet-phy@0 {
> > > > +compatible = "ethernet-phy-id0007.0570";
> > > > +vsc8531,vddmac   = /bits/ 16 
> > > > ;
> > > > +vsc8531,edge-slowdown= /bits/ 8  <17>;
> > >
> > > No, real values please:
> > >
> > > vsc8531,vddmac  = <2000>;
> > > vsc8531,edge-slowdown   = <21>;
> > >
> > > The driver should then do the maths to figure out the nearest magic
> > > value to write to the register, or complain the settings are out of
> > > range with an -EINVAL.
> 
> I think you missed my point. Notice my example does not use values
> from the table. Is there a reason not to use the PHY with 2000mv? Or
> does it break when you don't use one of the 4 listed voltages?
> 
As per PHY data sheet, It should use one of the voltage in list.
i.e. 3.3V (3300 mV) or 2.5V (2500 mV) or 1.8V (1800 mV) or 1.5V (1500).
Other voltages are not accepted. Drivr considers default as 3.3V (3300 mV).

> I was wanting you to implement some formula, which given the voltage
> and percentage slowdown, returns the magic number. Hence the comment:
> 

Based on Voltage selection and percentage slowdown, Driver pick the
magic number from Edge rate table.

> > > FYI: No floating point maths are allowed in the kernel.
> 
> You need to do integer arithmetic, which is why i suggested mV, not V.
> 
I understood your suggestion and used voltage in milli Volts.

>   Andrew

Thanks,
Raju.

Re: [PATCH v4 net-next] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for code review and valuable comments.

On Wed, Sep 28, 2016 at 06:16:53PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> > +Optional properties:
> > +- vsc8531,vddmac : The vddmac in mV.
> > +- vsc8531,edge-slowdown  : % the edge should be slowed down relative to
> > +   the fastest possible edge time. Native sign
> > +   need not enter.
> > +   Edge rate sets the drive strength of the MAC
> > +   interface output signals.  Changing the drive
> > +   strength will affect the edge rate of the output
> > +   signal.  The goal of this setting is to help
> > +   reduce electrical emission (EMI) by being able
> > +   to reprogram drive strength and in effect slow
> > +   down the edge rate if desired.  Table 5 shows the
> 
> Hi Raju
> 
> There is no table five here? Is that a reference to a data sheet
> table?
> 

I accepted your comment.
It was typo. It should be Table 1.
Yes. In datasheet Edge rate control is Table 5.

> > +Example:
> > +
> > +vsc8531_0: ethernet-phy@0 {
> > +compatible = "ethernet-phy-id0007.0570";
> > +vsc8531,vddmac   = /bits/ 16 
> > ;
> > +vsc8531,edge-slowdown= /bits/ 8  <17>;
> 
> No, real values please:
> 
> vsc8531,vddmac  = <2000>;
> vsc8531,edge-slowdown   = <21>;
> 
> The driver should then do the maths to figure out the nearest magic
> value to write to the register, or complain the settings are out of
> range with an -EINVAL.
> 
> FYI: No floating point maths are allowed in the kernel.
> 

I accepted your review comment. I will change and resend again.

>Andrew

---
Thanks,
Raju.

[PATCH v5 net-next] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.

Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.

Tested on Beaglebone Black with VSC 8531 PHY.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>

---
All the review comments updated and resending for review.

Change set:
v1:
- Initial version of Edge-rate driver add by using IOCTL.
v2:
- Changed edge-rate parameter to Device Tree with magic number.
v3:
- Added Device Tree documentati0n and edge-rate parameter table.
  Added probe function initialize the vsc8531 private data structure.
v4:
- As per review comment, Device Tree parameters (vddmac, edge-slowdown)
  added.
v5:
- As per review comment, Device Tree Document parameters (vddmac, 
  edge-slowdown) real numbers added. Table number changed from 5 to 1.

---

 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   |  58 ++
 drivers/net/phy/mscc.c | 125 +
 include/dt-bindings/net/mscc-phy-vsc8531.h |  21 
 3 files changed, 204 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
 create mode 100644 include/dt-bindings/net/mscc-phy-vsc8531.h

diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt 
b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
new file mode 100644
index 000..99c7eb0
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
@@ -0,0 +1,58 @@
+* Microsemi - vsc8531 Giga bit ethernet phy
+
+Required properties:
+- compatible   : Should contain phy id as "ethernet-phy-id."
+ The PHY device uses the binding described in
+ Documentation/devicetree/bindings/net/phy.txt
+
+Optional properties:
+- vsc8531,vddmac   : The vddmac in mV.
+- vsc8531,edge-slowdown: % the edge should be slowed down relative to
+ the fastest possible edge time. Native sign
+ need not enter.
+ Edge rate sets the drive strength of the MAC
+ interface output signals.  Changing the drive
+ strength will affect the edge rate of the output
+ signal.  The goal of this setting is to help
+ reduce electrical emission (EMI) by being able
+ to reprogram drive strength and in effect slow
+ down the edge rate if desired.  Table 1 shows the
+ impact to the edge rate per VDDMAC supply for each
+ drive strength setting.
+ Ref: Table:1 - Edge rate change below.
+
+Note: see dt-bindings/net/mscc-phy-vsc8531.h for applicable values
+
+Table: 1 - Edge rate change
+|
+|  Edge Rate Change (VDDMAC)   |
+|  |
+| 3300 mV  2500 mV 1800 mV 1500 mV |
+|---|
+| Default  Deafult Default Default |
+| (Fastest)(recommended)   (recommended)   |
+|---|
+| -2%  -3% -5% -6% |
+|---|
+| -4%  -6% -9% -14%|
+|---|
+| -7%  -10%-16%-21%|
+|(recommended) (recommended)   |
+|---|
+| -10% -14%-23%-29%|
+|---|
+| -17% -23% 

[PATCH net-next 1/2] net: phy: Add Wake-on-LAN driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

Wake-on-LAN (WoL) is an Ethernet networking standard that allows
a computer/device to be turned on or awakened by a network message.
VSC8531 PHY can support this feature configure by driver set function.
WoL status get by driver get function.

Tested on Beaglebone Black with VSC 8531 PHY.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
 drivers/net/phy/mscc.c | 132 +
 1 file changed, 132 insertions(+)

diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index d350deb..ca6ea23 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 enum rgmii_rx_clock_delay {
RGMII_RX_CLK_DELAY_0_2_NS = 0,
@@ -35,6 +36,7 @@ enum rgmii_rx_clock_delay {
 
 #define MII_VSC85XX_INT_MASK 25
 #define MII_VSC85XX_INT_MASK_MASK0xa000
+#define MII_VSC85XX_INT_MASK_WOL 0x0040
 #define MII_VSC85XX_INT_STATUS   26
 
 #define MSCC_EXT_PAGE_ACCESS 31
@@ -46,6 +48,19 @@ enum rgmii_rx_clock_delay {
 #define RGMII_RX_CLK_DELAY_MASK  0x0070
 #define RGMII_RX_CLK_DELAY_POS   4
 
+#define MSCC_PHY_WOL_LOWER_MAC_ADDR  21
+#define MSCC_PHY_WOL_MID_MAC_ADDR22
+#define MSCC_PHY_WOL_UPPER_MAC_ADDR  23
+#define MSCC_PHY_WOL_LOWER_PASSWD24
+#define MSCC_PHY_WOL_MID_PASSWD  25
+#define MSCC_PHY_WOL_UPPER_PASSWD26
+
+#define MSCC_PHY_WOL_MAC_CONTROL 27
+#define EDGE_RATE_CNTL_POS   5
+#define EDGE_RATE_CNTL_MASK  0x00E0
+#define SECURE_ON_ENABLE 0x8000
+#define SECURE_ON_PASSWD_LEN_4   0x4000
+
 /* Microsemi PHY ID's */
 #define PHY_ID_VSC8531   0x00070570
 #define PHY_ID_VSC8541   0x00070770
@@ -58,6 +73,119 @@ static int vsc85xx_phy_page_set(struct phy_device *phydev, 
u8 page)
return rc;
 }
 
+static int vsc85xx_wol_set(struct phy_device *phydev,
+  struct ethtool_wolinfo *wol)
+{
+   int rc;
+   u16 reg_val;
+   struct ethtool_wolinfo *wol_conf = wol;
+
+   mutex_lock(>lock);
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
+   if (rc != 0)
+   goto out_unlock;
+
+   if (wol->wolopts & WAKE_MAGIC) {
+   /* Store the device address for the magic packet */
+   reg_val = phydev->attached_dev->dev_addr[4] << 8;
+   reg_val |= phydev->attached_dev->dev_addr[5];
+   phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, reg_val);
+   reg_val = phydev->attached_dev->dev_addr[2] << 8;
+   reg_val |= phydev->attached_dev->dev_addr[3];
+   phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, reg_val);
+   reg_val = phydev->attached_dev->dev_addr[0] << 8;
+   reg_val |= phydev->attached_dev->dev_addr[1];
+   phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, reg_val);
+   } else {
+   phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
+   phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
+   phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
+   }
+
+   reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
+   if (wol_conf->wolopts & WAKE_MAGICSECURE)
+   reg_val |= SECURE_ON_ENABLE;
+   else
+   reg_val &= ~SECURE_ON_ENABLE;
+   phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
+
+   if (wol_conf->wolopts & WAKE_MAGICSECURE) {
+   reg_val = wol_conf->sopass[4] << 8;
+   reg_val |= wol_conf->sopass[5];
+   phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, reg_val);
+   reg_val = wol_conf->sopass[2] << 8;
+   reg_val |= wol_conf->sopass[3];
+   phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, reg_val);
+   reg_val = wol_conf->sopass[0] << 8;
+   reg_val |= wol_conf->sopass[1];
+   phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, reg_val);
+   } else {
+   phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
+   phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
+   phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
+   }
+
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
+   if (rc != 0)
+   goto out_unlock;
+
+   if (wol->wolopts & WAKE_MAGIC) {
+   /* Enable the WOL interrupt */
+   reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
+   reg_val |= MII_VSC85XX_INT_MASK_WOL;
+   rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
+   if (rc != 0)
+   goto out_unlock;
+   } else {

[PATCH net-next 2/2] net: phy: Add PHY Auto/Mdi/Mdix set driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

To connect two ports of the same configuration (MDI to MDI or
MDI-X to MDI-X) with a 10/100/1000 Mbit/s connection, an
Ethernet crossover cable is needed to cross over the transmit
and receive signals in the cable, so that they are matched at
the connector level.
When connecting an MDI port to an MDI-X port a straight through
cable is used while to connect two MDI ports or two MDI-X ports
a crossover cable must be used. Conventionally MDI is used on end
devices while MDI-X is used on hubs and switches

Auto MDI-X automatically detects the required cable connection
type and configures the connection appropriately, removing the
need for crossover cables to interconnect switches or connecting
PCs peer-to-peer.

VSC8531 PHY supports Auto MDI-x, MDI and MDI-X configuraion by
driver set mdix function.

Tested on Beaglebone Black with VSC 8531 PHY.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
 drivers/net/phy/mscc.c | 72 --
 1 file changed, 70 insertions(+), 2 deletions(-)

diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index ca6ea23..dbf8434 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -26,6 +26,11 @@ enum rgmii_rx_clock_delay {
 
 /* Microsemi VSC85xx PHY registers */
 /* IEEE 802. Std Registers */
+#define MSCC_PHY_BYPASS_CONTROL  18
+#define DISABLE_HP_AUTO_MDIX_MASK0x0080
+#define DISABLE_PAIR_SWAP_CORR_MASK  0x0020
+#define DISABLE_POLARITY_CORR_MASK   0x0010
+
 #define MSCC_PHY_EXT_PHY_CNTL_1   23
 #define MAC_IF_SELECTION_MASK 0x1800
 #define MAC_IF_SELECTION_GMII 0
@@ -41,8 +46,16 @@ enum rgmii_rx_clock_delay {
 
 #define MSCC_EXT_PAGE_ACCESS 31
 #define MSCC_PHY_PAGE_STANDARD   0x /* Standard registers */
+#define MSCC_PHY_PAGE_EXTENDED   0x0001 /* Extended registers */
 #define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
 
+/* Extended Page 1 Registers */
+#define MSCC_PHY_EXT_MODE_CNTL   19
+#define FORCE_MDI_CROSSOVER_MASK 0x000C
+#define FORCE_MDI_CROSSOVER_MDIX 0x000C
+#define FORCE_MDI_CROSSOVER_MDI  0x0008
+#define FORCE_MDI_CROSSOVER_NORMAL   0x
+
 /* Extended Page 2 Registers */
 #define MSCC_PHY_RGMII_CNTL  20
 #define RGMII_RX_CLK_DELAY_MASK  0x0070
@@ -73,6 +86,47 @@ static int vsc85xx_phy_page_set(struct phy_device *phydev, 
u8 page)
return rc;
 }
 
+static int vsc85xx_mdix_set(struct phy_device *phydev,
+   u8 mdix)
+{
+   int rc;
+   u16 reg_val;
+
+   reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
+   if ((mdix == ETH_TP_MDI) || (mdix == ETH_TP_MDI_X)) {
+   reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |
+   DISABLE_POLARITY_CORR_MASK  |
+   DISABLE_HP_AUTO_MDIX_MASK);
+   } else {
+   reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |
+DISABLE_POLARITY_CORR_MASK  |
+DISABLE_HP_AUTO_MDIX_MASK);
+   }
+   rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
+   if (rc != 0)
+   goto out_unlock;
+
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED);
+   if (rc != 0)
+   goto out_unlock;
+
+   reg_val = phy_read(phydev, MSCC_PHY_EXT_MODE_CNTL);
+   reg_val &= ~(FORCE_MDI_CROSSOVER_MASK);
+   if (mdix == ETH_TP_MDI)
+   reg_val |= FORCE_MDI_CROSSOVER_MDI;
+   else if (mdix == ETH_TP_MDI_X)
+   reg_val |= FORCE_MDI_CROSSOVER_MDIX;
+   rc = phy_write(phydev, MSCC_PHY_EXT_MODE_CNTL, reg_val);
+   if (rc != 0)
+   goto out_unlock;
+
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
+
+out_unlock:
+
+   return rc;
+}
+
 static int vsc85xx_wol_set(struct phy_device *phydev,
   struct ethtool_wolinfo *wol)
 {
@@ -227,6 +281,7 @@ static int vsc85xx_default_config(struct phy_device *phydev)
int rc;
u16 reg_val;
 
+   phydev->mdix = ETH_TP_MDI_AUTO;
mutex_lock(>lock);
rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
if (rc != 0)
@@ -288,6 +343,19 @@ static int vsc85xx_config_intr(struct phy_device *phydev)
return rc;
 }
 
+static int vsc85xx_config_aneg(struct phy_device *phydev)
+{
+   int rc;
+
+   rc = vsc85xx_mdix_set(phydev, phydev->mdix);
+   if (rc < 0)
+   return rc;
+
+   rc = genphy_config_aneg(phydev);
+
+   return rc;
+}
+
 /* Microsemi VSC85xx PHYs */
 static struct phy_driver vsc85xx_driver[] = {
 {
@@ -298,7 +366,7 @@ static struct phy_driver vsc85xx_driver[] = {
.flags  = PHY_HAS_INTERRUPT,
.soft_reset = _soft_reset,
.config_init= _c

[PATCH net-next 0/2] net: phy: Add WoL and Auto Mdix drivers for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

This series adds support to the Wake-on-LAN and Auto/Mdi-x set drivers
for Microsemi PHYs.

Patch 1/2:
Wake-on-LAN (WoL) is an Ethernet networking standard that allows
a computer/device to be turned on or awakened by a network message.
VSC8531 PHY can support this feature configure by driver set function.
WoL status get by driver get function.

Patch 2/2:
To connect two ports of the same configuration (MDI to MDI or
MDI-X to MDI-X) with a 10/100/1000 Mbit/s connection, an
Ethernet crossover cable is needed to cross over the transmit
and receive signals in the cable, so that they are matched at
the connector level.
When connecting an MDI port to an MDI-X port a straight through
cable is used while to connect two MDI ports or two MDI-X ports
a crossover cable must be used. Conventionally MDI is used on end
devices while MDI-X is used on hubs and switches

Auto MDI-X automatically detects the required cable connection
type and configures the connection appropriately, removing the
need for crossover cables to interconnect switches or connecting
PCs peer-to-peer.

VSC8531 PHY supports Auto MDI-x, MDI and MDI-X configuraion by
driver set loopback function.

Tested on Beaglebone Black with VSC 8531 PHY.

Raju Lakkaraju (2):
  net: phy: Add Wake-on-LAN driver for Microsemi PHYs.
  net: phy: Add PHY Auto/Mdi/Mdix set driver for Microsemi PHYs.

 drivers/net/phy/mscc.c | 204 -
 1 file changed, 202 insertions(+), 2 deletions(-)

-- 
2.7.4

[PATCH v4 net-next] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.

Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.

Tested on Beaglebone Black with VSC 8531 PHY.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>

---

All the review comments updated and resending for review.

Change set:
v1:
- Initial version of Edge-rate driver add by using IOCTL.
v2:
- Changed edge-rate parameter to Device Tree with magic number.
v3:
- Added Device Tree documentati0n and edge-rate parameter table.
  Added probe function initialize the vsc8531 private data structure.
v4:
- As per review comment, Device Tree parameters (vddmac, edge-slowdowni)
  added.

---

 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   |  58 ++
 drivers/net/phy/mscc.c | 125 +
 include/dt-bindings/net/mscc-phy-vsc8531.h |  21 
 3 files changed, 204 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
 create mode 100644 include/dt-bindings/net/mscc-phy-vsc8531.h

diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt 
b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
new file mode 100644
index 000..951043e
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
@@ -0,0 +1,58 @@
+* Microsemi - vsc8531 Giga bit ethernet phy
+
+Required properties:
+- compatible   : Should contain phy id as "ethernet-phy-id."
+ The PHY device uses the binding described in
+ Documentation/devicetree/bindings/net/phy.txt
+
+Optional properties:
+- vsc8531,vddmac   : The vddmac in mV.
+- vsc8531,edge-slowdown: % the edge should be slowed down relative to
+ the fastest possible edge time. Native sign
+ need not enter.
+ Edge rate sets the drive strength of the MAC
+ interface output signals.  Changing the drive
+ strength will affect the edge rate of the output
+ signal.  The goal of this setting is to help
+ reduce electrical emission (EMI) by being able
+ to reprogram drive strength and in effect slow
+ down the edge rate if desired.  Table 5 shows the
+ impact to the edge rate per VDDMAC supply for each
+ drive strength setting.
+ Ref: Table:1 - Edge rate change below.
+
+Note: see dt-bindings/net/mscc-phy-vsc8531.h for applicable values
+
+Table: 1 - Edge rate change
+|
+|  Edge Rate Change (VDDMAC)   |
+|  |
+| 3300 mV  2500 mV 1800 mV 1500 mV |
+|---|
+| Default  Deafult Default Default |
+| (Fastest)(recommended)   (recommended)   |
+|---|
+| -2%  -3% -5% -6% |
+|---|
+| -4%  -6% -9% -14%|
+|---|
+| -7%  -10%-16%-21%|
+|(recommended) (recommended)   |
+|---|
+| -10% -14%-23%-29%|
+|---|
+| -17% -23%-35%-42%|
+|---|
+| -29% -37% 

Re: [v3,net-next] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for review and valuable comments.
I will implement below suggestion and resend for review.

Thanks,
Raju.

On Tue, Sep 27, 2016 at 11:14:36PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> I just realised the possibly correct binding was starring me in the
> face.
> 
> --|
> |  3.3V 2.5V1.8V1.5V  |
> |-|
> |-2%-3% -5% -6%   |
> |-|
> |-4%-6% -9% -14%  |
> |-|
> |-7%-10%-16%-21%  |
> |-|
> |-10%   -14%-23%-29%  |
> |-|
> |-17%   -23%-35%-42%  |
> |-|
> |-29%   -37%-52%-58%  |
> |-|
> |-53%   -63%-76%-77%  |
> |-|
> 
> So the binding is:
> 
> vsc8531,vddmac  : The vddmac in mV.
> vsc8531,edge-slowdown   : % the edge should be slowed down relative to
>   the fastest possible edge time.
> 
> Given those two values, the driver can work out the magic value to put
> into the register that nobody knows the true meaning of.
> 

Accepted.

>  Andrew

---
Raju.

Re: [PATCH v3 net-next] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for review and valuable comments.

Thanks,
Raju.
On Tue, Sep 27, 2016 at 04:16:33PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> > index 000..7ba3855
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
> > @@ -0,0 +1,61 @@
> > +* Microsemi - vsc8531 Giga bit ethernet phy
> > +
> > +Required properties:
> > +- compatible : Should contain phy id as "ethernet-phy-id."
> > +   If the phy's identifier is known then the list may contain 
> > an entry
> > +   of the form: "ethernet-phy-id." where
> > +    - The value of the 16 bit Phy Identifier 1 register as
> > +  4 hex digits. This is the chip vendor OUI bits 3:18
> > +    - The value of the 16 bit Phy Identifier 2 register as
> > +  4 hex digits. This is the chip vendor OUI bits 19:24,
> > +  followed by 10 bits of a vendor specific ID.
> > +- reg: The ID number for the phy, usually a small integer
> 
> Please don't copy phy.txt. Just refer to it. Use text like:
> 
> The PHY device uses the binding described in
> Documentation/devicetree/bindings/net/phy.txt
> 
> It may additionally have the following properties
> 

Accepted. 

> > +Optional properties:
> > +- vsc8531,edge-rate  : Edge rate sets the drive strength of the MAC
> > +   interface output signals.  Changing the drive
> > +   strength will affect the edge rate of the output
> > +   signal.
> 
> Are we specifying a rate or a strength? It is called edge-rate, so it
> expect it to be a rate, mV/pS or something similar.
> 

Accepted.

>Andrew

[PATCH v3 net-next] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

All the review comments updated and resending for review.

Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the 
driving strange, and thereby change the EMI behavioral.

Edge-rate value get from Device Tree.

Tested on Beaglebone Black with VSC 8531 PHY.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>

---
Change set:
v1:
- Initial version of Edge-rate driver add by using IOCTL.
v2: 
- Changed edge-rate parameter to Device Tree with magic number.
v3: 
- Added Device Tree documentati0n and edge-rate parameter table.
  Added probe function initialize the vsc8531 private data structure.
---

 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   | 61 
 drivers/net/phy/mscc.c | 85 ++
 include/dt-bindings/net/mscc-phy-vsc8531.h | 23 ++
 3 files changed, 169 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
 create mode 100644 include/dt-bindings/net/mscc-phy-vsc8531.h

diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt 
b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
new file mode 100644
index 000..7ba3855
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
@@ -0,0 +1,61 @@
+* Microsemi - vsc8531 Giga bit ethernet phy
+
+Required properties:
+- compatible   : Should contain phy id as "ethernet-phy-id."
+ If the phy's identifier is known then the list may contain an 
entry
+ of the form: "ethernet-phy-id." where
+  - The value of the 16 bit Phy Identifier 1 register as
+4 hex digits. This is the chip vendor OUI bits 3:18
+  - The value of the 16 bit Phy Identifier 2 register as
+4 hex digits. This is the chip vendor OUI bits 19:24,
+followed by 10 bits of a vendor specific ID.
+- reg  : The ID number for the phy, usually a small integer
+
+Optional properties:
+- vsc8531,edge-rate: Edge rate sets the drive strength of the MAC
+ interface output signals.  Changing the drive
+ strength will affect the edge rate of the output
+ signal.  The goal of this setting is to help
+ reduce electrical emission (EMI) by being able
+ to reprogram drive strength and in effect slow
+ down the edge rate if desired.  Table 5 shows the
+ impact to the edge rate per VDDMAC supply for each
+ drive strength setting. Default edge rate is set as
+ Fastest edge rate (i.e. 7).
+ Ref: Table:1 - Edge rate change below.
+
+Note: see dt-bindings/net/mscc-vsc8531.h for applicable values
+
+Table: 1 - Edge rate change
+-|
+| Edge Rate Change (VDDMAC)  |
+|   |
+| Reg Setting  3.3V2.5V1.8V1.5V |
+||
+| 111  Default Deafult Default Default  |
+| (Fastest)(recommended)   (recommended)|
+||
+| 110  -2% -3% -5% -6%  |
+||
+| 101  -4% -6% -9% -14% |
+||
+| 100  -7% -10%-16%-21% |
+|  

[PATCH v3 net-next] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi,

Thank you for review the code and valuable comments.
Summary of changes:
V1: Initial version of Edge-rate driver add by using IOCTL.
V2: Changed edge-rate parameter to Device Tree with magic number.
V3: Added Device Tree documentatoin and edge-rate parameter table.
Added probe function initialize the vsc8531 private datastructure.
Thanks,
Raju.

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

---
All the review comments updated and resending for review.

Summary:
V1: Initial version of Edge-rate driver add by using IOCTL.
V2: Changed edge-rate parameter to Device Tree with magic number.
V3: Added Device Tree documentatoin and edge-rate parameter table.
Added probe function initialize the vsc8531 private datastructure.

Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the 
driving strange, and thereby change the EMI behavioral.

Edge-rate value get from Device Tree.

Tested on Beaglebone Black with VSC 8531 PHY.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
 .../devicetree/bindings/net/mscc-phy-vsc8531.txt   | 61 
 drivers/net/phy/mscc.c | 85 ++
 include/dt-bindings/net/mscc-phy-vsc8531.h | 23 ++
 3 files changed, 169 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
 create mode 100644 include/dt-bindings/net/mscc-phy-vsc8531.h

diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt 
b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
new file mode 100644
index 000..7ba3855
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
@@ -0,0 +1,61 @@
+* Microsemi - vsc8531 Giga bit ethernet phy
+
+Required properties:
+- compatible   : Should contain phy id as "ethernet-phy-id."
+ If the phy's identifier is known then the list may contain an 
entry
+ of the form: "ethernet-phy-id." where
+  - The value of the 16 bit Phy Identifier 1 register as
+4 hex digits. This is the chip vendor OUI bits 3:18
+  - The value of the 16 bit Phy Identifier 2 register as
+4 hex digits. This is the chip vendor OUI bits 19:24,
+followed by 10 bits of a vendor specific ID.
+- reg  : The ID number for the phy, usually a small integer
+
+Optional properties:
+- vsc8531,edge-rate: Edge rate sets the drive strength of the MAC
+ interface output signals.  Changing the drive
+ strength will affect the edge rate of the output
+ signal.  The goal of this setting is to help
+ reduce electrical emission (EMI) by being able
+ to reprogram drive strength and in effect slow
+ down the edge rate if desired.  Table 5 shows the
+ impact to the edge rate per VDDMAC supply for each
+ drive strength setting. Default edge rate is set as
+ Fastest edge rate (i.e. 7).
+ Ref: Table:1 - Edge rate change below.
+
+Note: see dt-bindings/net/mscc-vsc8531.h for applicable values
+
+Table: 1 - Edge rate change
+-|
+| Edge Rate Change (VDDMAC)  |
+|   |
+| Reg Setting  3.3V2.5V1.8V1.5V |
+||
+| 111  Default Deafult Default Default  |
+| (Fastest)(recommended)   (recommended)|
+||
+| 110  -2% -3

[PATCH v3 net-next] net: phy: Add MAC-IF driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

All the review comments updated and resending for review.

This is MAC interface feature.
Microsemi PHY can support RGMII, RMII or GMII/MII interface between MAC and PHY.
MAC-IF function program the right value based on Device tree configuration.

Tested on Beaglebone Black with VSC 8531 PHY.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
 drivers/net/phy/mscc.c | 51 ++
 1 file changed, 51 insertions(+)

diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index c09cc4a..d350deb 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -23,6 +23,16 @@ enum rgmii_rx_clock_delay {
RGMII_RX_CLK_DELAY_3_4_NS = 7
 };
 
+/* Microsemi VSC85xx PHY registers */
+/* IEEE 802. Std Registers */
+#define MSCC_PHY_EXT_PHY_CNTL_1   23
+#define MAC_IF_SELECTION_MASK 0x1800
+#define MAC_IF_SELECTION_GMII 0
+#define MAC_IF_SELECTION_RMII 1
+#define MAC_IF_SELECTION_RGMII2
+#define MAC_IF_SELECTION_POS  11
+#define FAR_END_LOOPBACK_MODE_MASK0x0008
+
 #define MII_VSC85XX_INT_MASK 25
 #define MII_VSC85XX_INT_MASK_MASK0xa000
 #define MII_VSC85XX_INT_STATUS   26
@@ -48,6 +58,42 @@ static int vsc85xx_phy_page_set(struct phy_device *phydev, 
u8 page)
return rc;
 }
 
+static int vsc85xx_mac_if_set(struct phy_device *phydev,
+ phy_interface_t interface)
+{
+   int rc;
+   u16 reg_val;
+
+   mutex_lock(>lock);
+   reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
+   reg_val &= ~(MAC_IF_SELECTION_MASK);
+   switch (interface) {
+   case PHY_INTERFACE_MODE_RGMII:
+   reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
+   break;
+   case PHY_INTERFACE_MODE_RMII:
+   reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
+   break;
+   case PHY_INTERFACE_MODE_MII:
+   case PHY_INTERFACE_MODE_GMII:
+   reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);
+   break;
+   default:
+   rc = -EINVAL;
+   goto out_unlock;
+   }
+   rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
+   if (rc != 0)
+   goto out_unlock;
+
+   rc = genphy_soft_reset(phydev);
+
+out_unlock:
+   mutex_unlock(>lock);
+
+   return rc;
+}
+
 static int vsc85xx_default_config(struct phy_device *phydev)
 {
int rc;
@@ -77,6 +123,11 @@ static int vsc85xx_config_init(struct phy_device *phydev)
rc = vsc85xx_default_config(phydev);
if (rc)
return rc;
+
+   rc = vsc85xx_mac_if_set(phydev, phydev->interface);
+   if (rc)
+   return rc;
+
rc = genphy_config_init(phydev);
 
return rc;
-- 
2.7.4

Re: [PATCH v2 net-next 2/2] net: phy: Add MAC-IF driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for review the code.
I accepted all your review comments.
I will send the update patch for review again.

Thanks,
Raju.
On Fri, Sep 09, 2016 at 02:03:46PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> On Fri, Sep 09, 2016 at 11:23:52AM +0530, Raju Lakkaraju wrote:
> > Hi Andrew,
> >
> > Thank you for review the code and valuable comments.
> >
> > On Thu, Sep 08, 2016 at 03:27:27PM +0200, Andrew Lunn wrote:
> > > EXTERNAL EMAIL
> > >
> > >
> > > On Thu, Sep 08, 2016 at 02:47:22PM +0530, Raju Lakkaraju wrote:
> > > > From: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> > > >
> > > > Used Device Tree to configure the MAC Interface as per review comments 
> > > > and
> > > > re-sending code for review
> > >
> > > I don't see anything about device tree in this patch...
> > >
> > Ethernet driver (in my BBB environment, TI cpsw driver) read the device tree
> > phy interface parameter and update in phydev structure.
> >
> > In device tree the following code holds the phy interface configuration.
> > _emac0 {
> > phy_id = <_mdio>, <0>;
> > phy-mode = "rgmii";
> > };
> 
> O.K, that is one place it can come from. But it is not the only,
> e.g. platform data or ACPI. A better comment might be:
> 
> Configure the MAC/PHY interface as indicated in phydev->interface,
> eg. GMII, RMII, RGMII.
> 
> Andrew

Re: [PATCH v2 net-next 1/2] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for review the code.

On Fri, Sep 09, 2016 at 03:18:32PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> > > > +static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev,
> > > > +   u8 edge_rate)
> > >
> > > No spaces place.
> > >
> > I ran the checkpatch. I did not find any error. I created another workspace 
> > and
> > applied the same patch. It shows the correct alignement. I have used tabs 
> > (8 space width).
> > then some spaces to align braces.
> 
> Sorry, i worded that poorly. I was meaning between the u8 and edge. A
> single space is enough.
> 
I accepted your suggestion.

> > > > +#ifdef CONFIG_OF_MDIO
> > > > +static int vsc8531_of_init(struct phy_device *phydev)
> > > > +{
> > > > + int rc;
> > > > + struct vsc8531_private *vsc8531 = phydev->priv;
> > > > + struct device *dev = >mdio.dev;
> > > > + struct device_node *of_node = dev->of_node;
> > > > +
> > > > + if (!of_node)
> > > > + return -ENODEV;
> > > > +
> > > > + rc = of_property_read_u8(of_node, "vsc8531,edge-rate",
> > > > +  >edge_rate);
> > >
> > > Until you have written the Documentation, it is hard for me to tell,
> > > but device tree bindings should use real units, like seconds, Ohms,
> > > Farads, etc. Is the edge rate in nS? Or is it some magic value which
> > > just gets written into the register?
> > >
> >
> > This is some magic value which just gets written into the register.
> 
> Magic values are generally not accepted in device tree bindings. Both
> Micrel and Renesas define their clock skew in ps, for example. Since
> this is rise time, it should also be possible to define it in a unit
> of time.
> 

I accepted your comment. I had discussion with my hardware team and explained
the code review comments.
They asked me to define as picoseconds as units.

> > > >  static int vsc85xx_config_init(struct phy_device *phydev)
> > > >  {
> > > >   int rc;
> > > > + struct vsc8531_private *vsc8531;
> > > > +
> > > > + if (!phydev->priv) {
> > >
> > > How can this happen?
> > >
> >
> > VSC 8531 driver don't have any private structure assigned initially.
> > Allways priv points to NULL.
> 
> So if it cannot happen, don't check for it.
> 
> Also, by convention, you allocate memory in the .probe() function of a
> driver. Please do it there.
> 
I accepted your review comment. 
I will re-send the patch with updates.

> Andrew

---
Thanks,
Raju.

Re: [PATCH v2 net-next 1/2] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for review the code and valuable comments.

On Thu, Sep 08, 2016 at 03:14:15PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> On Thu, Sep 08, 2016 at 02:47:21PM +0530, Raju Lakkaraju wrote:
> > From: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> >
> > Used Device Tree to configure the Edge-rate as per review comments and
> > re-sending code for review
> >
> > Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> > ---
> >  drivers/net/phy/mscc.c | 76 
> > ++
> 
> Hi Raju
> 
> You need to also document the new property in the device tree binding
> documentation.
> 
Sure. I will do.
I created device tree binding header file. i will submit in different patch.

> > +static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev,
> > +   u8 edge_rate)
> 
> No spaces place.
> 
I ran the checkpatch. I did not find any error. I created another workspace and
applied the same patch. It shows the correct alignement. I have used tabs (8 
space width).
then some spaces to align braces.

> > +#ifdef CONFIG_OF_MDIO
> > +static int vsc8531_of_init(struct phy_device *phydev)
> > +{
> > + int rc;
> > + struct vsc8531_private *vsc8531 = phydev->priv;
> > + struct device *dev = >mdio.dev;
> > + struct device_node *of_node = dev->of_node;
> > +
> > + if (!of_node)
> > + return -ENODEV;
> > +
> > + rc = of_property_read_u8(of_node, "vsc8531,edge-rate",
> > +  >edge_rate);
> 
> Until you have written the Documentation, it is hard for me to tell,
> but device tree bindings should use real units, like seconds, Ohms,
> Farads, etc. Is the edge rate in nS? Or is it some magic value which
> just gets written into the register?
> 

This is some magic value which just gets written into the register.

In device tree file, defined in davinci_mdio structure:

vsc8531_0: ethernet-phy@0 {
compatible = "ethernet-phy-id0007.0570";
reg = <0>;
vsc8531,edge-rate = /bits/ 8 ;
};

In device tree binding header file, MACRO has defined as
i.e. include/dt-bindings/net/mscc-vsc8531.h

/* MAC interface Edge rate control pad */
#define MSCC_EDGE_RATE_CNTL_SLOWEST  0x0
#define MSCC_EDGE_RATE_CNTL_PLUS_1   0x1
#define MSCC_EDGE_RATE_CNTL_PLUS_2   0x2
#define MSCC_EDGE_RATE_CNTL_PLUS_3   0x3
#define MSCC_EDGE_RATE_CNTL_PLUS_4   0x4
#define MSCC_EDGE_RATE_CNTL_PLUS_5   0x5
#define MSCC_EDGE_RATE_CNTL_PLUS_6   0x6
#define MSCC_EDGE_RATE_CNTL_FASTEST  0x7

> > +
> > + return rc;
> > +}
> > +#else
> > +static int vsc8531_of_init(struct phy_device *phydev)
> > +{
> > + return 0;
> > +}
> > +#endif /* CONFIG_OF_MDIO */
> > +
> >  static int vsc85xx_config_init(struct phy_device *phydev)
> >  {
> >   int rc;
> > + struct vsc8531_private *vsc8531;
> > +
> > + if (!phydev->priv) {
> 
> How can this happen?
> 

VSC 8531 driver don't have any private structure assigned initially.
Allways priv points to NULL. 
Allocate vsc8531 private structure and initialize by calling vsc8531_of_init( )
function.

> > + vsc8531 = devm_kzalloc(>mdio.dev, sizeof(*vsc8531),
> > +GFP_KERNEL);
> > + if (!vsc8531)
> > + return -ENOMEM;
> > +
> > + phydev->priv = vsc8531;
> > + rc = vsc8531_of_init(phydev);
> > + if (rc)
> > + return rc;
> > + } else {
> > + vsc8531 = (struct vsc8531_private *)phydev->priv;
> > + }
> >
> >   rc = vsc85xx_default_config(phydev);
> >   if (rc)
> >   return rc;
> > +
> > + rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->edge_rate);
> 
> If there is no vsc8531,edge-rate property in device tree, is the phy
> going to work O.K, if you configure it for 0nS edges? Or should there
> be some default value assigned?
> 
Yes. Default values configured as Fast Edge rate control (i.e.0b111).
Edge rate control has defined 3 bits (Bit 7:5) in register.
Hardware default value is 3 (i.e. 0b111)


> Thanks
> Andrew

Thanks
Raju.

Re: [PATCH v2 net-next 2/2] net: phy: Add MAC-IF driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for review the code and valuable comments.

On Thu, Sep 08, 2016 at 03:27:27PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> On Thu, Sep 08, 2016 at 02:47:22PM +0530, Raju Lakkaraju wrote:
> > From: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> >
> > Used Device Tree to configure the MAC Interface as per review comments and
> > re-sending code for review
> 
> I don't see anything about device tree in this patch...
> 
Ethernet driver (in my BBB environment, TI cpsw driver) read the device tree 
phy interface parameter and update in phydev structure.

In device tree the following code holds the phy interface configuration.
_emac0 {
phy_id = <_mdio>, <0>;
phy-mode = "rgmii";
};

I tested with different modes by changing device tree parameter (i.e. 
rmii/rgmii/mii).
I have used this parameter to configure the MAC interface.

> >
> > Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
> > ---
> >  drivers/net/phy/mscc.c | 60 
> > ++
> >  1 file changed, 60 insertions(+)
> >
> > diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
> > index f0a0e8d..dfbf4f3 100644
> > --- a/drivers/net/phy/mscc.c
> > +++ b/drivers/net/phy/mscc.c
> > @@ -24,6 +24,16 @@ enum rgmii_rx_clock_delay {
> >   RGMII_RX_CLK_DELAY_3_4_NS = 7
> >  };
> >
> > +/* Microsemi VSC85xx PHY registers */
> > +/* IEEE 802. Std Registers */
> > +#define MSCC_PHY_EXT_PHY_CNTL_1   23
> > +#define MAC_IF_SELECTION_MASK 0x1800
> > +#define MAC_IF_SELECTION_GMII 0
> > +#define MAC_IF_SELECTION_RMII 1
> > +#define MAC_IF_SELECTION_RGMII2
> > +#define MAC_IF_SELECTION_POS  11
> > +#define FAR_END_LOOPBACK_MODE_MASK0x0008
> > +
> >  #define MII_VSC85XX_INT_MASK   25
> >  #define MII_VSC85XX_INT_MASK_MASK  0xa000
> >  #define MII_VSC85XX_INT_STATUS 26
> > @@ -59,6 +69,52 @@ static int vsc85xx_phy_page_set(struct phy_device 
> > *phydev, u8 page)
> >   return rc;
> >  }
> >
> > +static int vsc85xx_soft_reset(struct phy_device *phydev)
> > +{
> > + int rc;
> > + u16 reg_val;
> > +
> > + reg_val = phy_read(phydev, MII_BMCR);
> > + reg_val |= BMCR_RESET;
> > + rc = phy_write(phydev, MII_BMCR, reg_val);
> > +
> > + return rc;
> > +}
> 
> Do you need to wait for the reset to complete?
> 
> Does it make sense to call genphy_soft_reset() which will poll the phy
> waiting for the BMCR_RESET bit to clear?
> 
I accepted your review comment.
I can use genphy_soft_reset( ) instead of creating another same function.

> > +
> > +static int vsc85xx_mac_if_set(struct phy_device *phydev,
> > +   phy_interface_t   interface)
> > +{
> > + int rc;
> > + u16 reg_val;
> > +
> > + mutex_lock(>lock);
> > + reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
> > + reg_val &= ~(MAC_IF_SELECTION_MASK);
> > + switch (interface) {
> > + case PHY_INTERFACE_MODE_RGMII:
> > + reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
> > + break;
> > + case PHY_INTERFACE_MODE_RMII:
> > + reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
> > + break;
> > + case PHY_INTERFACE_MODE_MII:
> > + case PHY_INTERFACE_MODE_GMII:
> > + default:
> 
> So somebody asks you to configure the phy as PHY_INTERFACE_MODE_NA or
> PHY_INTERFACE_MODE_TBI, you are going to use GMII. Maybe returning
> -EINVAL would be better?
> 
Microsemi PHY can support only 3 modes (RGMII/RMII/GMII). Default configuration 
should be GMII
in PHY hardware.
I accepted your review comment. 
In default switch case i will return -EINVAL.

> Andrew

Thanks,
Raju.

Re: [PATCH 3/4] net: phy: Add read driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for review the code and valuable comments.

On Wed, Aug 24, 2016 at 03:13:47PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> On Wed, Aug 24, 2016 at 12:27:07PM +, Raju Lakkaraju wrote:
> > From: Nagaraju Lakkaraju <raju.lakkar...@microsemi.com>
> >
> > PHY Read support will be added for VSC 85xx Microsemi PHYs.
> 
> Why do i need this, when we have SIOCGMIIREG?
> 
Microsemi PHY have different pages i.e. Std IEEE, Extended, Extended_2, 
Extended_3 and
GPIO pages.
When I want to use SIOCGMIIREG, I can read Std IEEE only with SIOCGMIIREG and 
not other 
pages.
phy_read_reg function is debug function where I can read entair PHY registers.
In this function, I set the page number and register address then read register 
value
as atomic operation.

Do you have any suggestions to implement this function in different ways?

Thanks,
Raju.

[PATCH v2 net-next 0/2] net: phy: Add Edge-rate, MAC-IF driver for Microsemi PHYs

[Raju Lakkaraju]

Patch 1/2:

This is Edge rate control feature.
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission line
reflections, false signal detection by the receiving device and electromagnetic
interference (EMI) -- all of which can negate the potential gains designers are
seeking when they try to increase system speeds through the use of higher
performance logic devices. The fact is, faster signaling edge rates can cause
a higher level of electrical noise or other type of interference that can
actually lead to slower line speeds and lower maximum system frequencies.

Microsemi PHY have the provision to configure the edge rate. Edge-rate function
program the right value based on Device Tree configuration.

Tested on Beaglebone Black with VSC 8531 PHY.

Patch 2/2:

This is MAC interface feature.
Microsemi PHY can support RGMII, RMII or GMII/MII interface between MAC and PHY.
MAC-IF function program the right value based on Device tree configuration.

Tested on Beaglebone Black with VSC 8531 PHY.

Raju Lakkaraju (2):
  net: phy: Add Edge-rate driver for Microsemi PHYs.
  net: phy: Add MAC-IF driver for Microsemi PHYs.

 drivers/net/phy/mscc.c | 136 +
 1 file changed, 136 insertions(+)

-- 
2.7.4

[PATCH v2 net-next 2/2] net: phy: Add MAC-IF driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

Used Device Tree to configure the MAC Interface as per review comments and
re-sending code for review

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
 drivers/net/phy/mscc.c | 60 ++
 1 file changed, 60 insertions(+)

diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index f0a0e8d..dfbf4f3 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -24,6 +24,16 @@ enum rgmii_rx_clock_delay {
RGMII_RX_CLK_DELAY_3_4_NS = 7
 };
 
+/* Microsemi VSC85xx PHY registers */
+/* IEEE 802. Std Registers */
+#define MSCC_PHY_EXT_PHY_CNTL_1   23
+#define MAC_IF_SELECTION_MASK 0x1800
+#define MAC_IF_SELECTION_GMII 0
+#define MAC_IF_SELECTION_RMII 1
+#define MAC_IF_SELECTION_RGMII2
+#define MAC_IF_SELECTION_POS  11
+#define FAR_END_LOOPBACK_MODE_MASK0x0008
+
 #define MII_VSC85XX_INT_MASK 25
 #define MII_VSC85XX_INT_MASK_MASK0xa000
 #define MII_VSC85XX_INT_STATUS   26
@@ -59,6 +69,52 @@ static int vsc85xx_phy_page_set(struct phy_device *phydev, 
u8 page)
return rc;
 }
 
+static int vsc85xx_soft_reset(struct phy_device *phydev)
+{
+   int rc;
+   u16 reg_val;
+
+   reg_val = phy_read(phydev, MII_BMCR);
+   reg_val |= BMCR_RESET;
+   rc = phy_write(phydev, MII_BMCR, reg_val);
+
+   return rc;
+}
+
+static int vsc85xx_mac_if_set(struct phy_device *phydev,
+ phy_interface_t   interface)
+{
+   int rc;
+   u16 reg_val;
+
+   mutex_lock(>lock);
+   reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
+   reg_val &= ~(MAC_IF_SELECTION_MASK);
+   switch (interface) {
+   case PHY_INTERFACE_MODE_RGMII:
+   reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
+   break;
+   case PHY_INTERFACE_MODE_RMII:
+   reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
+   break;
+   case PHY_INTERFACE_MODE_MII:
+   case PHY_INTERFACE_MODE_GMII:
+   default:
+   reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);
+   break;
+   }
+   rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
+   if (rc != 0)
+   goto out_unlock;
+
+   rc = vsc85xx_soft_reset(phydev);
+
+out_unlock:
+   mutex_unlock(>lock);
+
+   return rc;
+}
+
 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev,
  u8 edge_rate)
 {
@@ -153,6 +209,10 @@ static int vsc85xx_config_init(struct phy_device *phydev)
if (rc)
return rc;
 
+   rc = vsc85xx_mac_if_set(phydev, phydev->interface);
+   if (rc)
+   return rc;
+
rc = genphy_config_init(phydev);
 
return rc;
-- 
2.7.4

[PATCH v2 net-next 1/2] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

Used Device Tree to configure the Edge-rate as per review comments and
re-sending code for review

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
 drivers/net/phy/mscc.c | 76 ++
 1 file changed, 76 insertions(+)

diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index c09cc4a..f0a0e8d 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 enum rgmii_rx_clock_delay {
RGMII_RX_CLK_DELAY_0_2_NS = 0,
@@ -36,10 +37,20 @@ enum rgmii_rx_clock_delay {
 #define RGMII_RX_CLK_DELAY_MASK  0x0070
 #define RGMII_RX_CLK_DELAY_POS   4
 
+#define MSCC_PHY_WOL_MAC_CONTROL 27
+#define EDGE_RATE_CNTL_POS   5
+#define EDGE_RATE_CNTL_MASK  0x00E0
+#define SECURE_ON_ENABLE 0x8000
+#define SECURE_ON_PASSWD_LEN_4   0x4000
+
 /* Microsemi PHY ID's */
 #define PHY_ID_VSC8531   0x00070570
 #define PHY_ID_VSC8541   0x00070770
 
+struct vsc8531_private {
+   u8 edge_rate;
+};
+
 static int vsc85xx_phy_page_set(struct phy_device *phydev, u8 page)
 {
int rc;
@@ -48,6 +59,28 @@ static int vsc85xx_phy_page_set(struct phy_device *phydev, 
u8 page)
return rc;
 }
 
+static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev,
+ u8 edge_rate)
+{
+   int rc;
+   u16 reg_val;
+
+   mutex_lock(>lock);
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
+   if (rc != 0)
+   goto out_unlock;
+   reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
+   reg_val &= ~(EDGE_RATE_CNTL_MASK);
+   reg_val |= (edge_rate << EDGE_RATE_CNTL_POS);
+   phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
+
+out_unlock:
+   mutex_unlock(>lock);
+
+   return rc;
+}
+
 static int vsc85xx_default_config(struct phy_device *phydev)
 {
int rc;
@@ -70,13 +103,56 @@ out_unlock:
return rc;
 }
 
+#ifdef CONFIG_OF_MDIO
+static int vsc8531_of_init(struct phy_device *phydev)
+{
+   int rc;
+   struct vsc8531_private *vsc8531 = phydev->priv;
+   struct device *dev = >mdio.dev;
+   struct device_node *of_node = dev->of_node;
+
+   if (!of_node)
+   return -ENODEV;
+
+   rc = of_property_read_u8(of_node, "vsc8531,edge-rate",
+>edge_rate);
+
+   return rc;
+}
+#else
+static int vsc8531_of_init(struct phy_device *phydev)
+{
+   return 0;
+}
+#endif /* CONFIG_OF_MDIO */
+
 static int vsc85xx_config_init(struct phy_device *phydev)
 {
int rc;
+   struct vsc8531_private *vsc8531;
+
+   if (!phydev->priv) {
+   vsc8531 = devm_kzalloc(>mdio.dev, sizeof(*vsc8531),
+  GFP_KERNEL);
+   if (!vsc8531)
+   return -ENOMEM;
+
+   phydev->priv = vsc8531;
+   rc = vsc8531_of_init(phydev);
+   if (rc)
+   return rc;
+   } else {
+   vsc8531 = (struct vsc8531_private *)phydev->priv;
+   }
 
rc = vsc85xx_default_config(phydev);
if (rc)
return rc;
+
+   rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->edge_rate);
+   if (rc)
+   return rc;
+
rc = genphy_config_init(phydev);
 
return rc;
-- 
2.7.4

Re: [PATCH 0/4] net: phy: Register header file for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for review the code and given valuable comments.
Other driver is not yet complete.

I accepted your review comment. I will keep all Register defined MACRO's in 
mscc.c file.

Thanks,
Raju.
On Fri, Aug 26, 2016 at 03:40:28PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> > I would like to share these register definitions share between
> > Microsemi multiple drivers.
> 
> Hi Raju
> 
> Please post a patch which does this, i.e. modifies multiple drivers to
> share the header file.
> 
> However, just be aware, if it turns out these multiple drivers are
> very similar, we might actually ask you to merge them into one driver.
> 
>  Andrew

Re: [PATCH 2/4] net: phy: Add MAC-IF driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for review the code and valuable comments.
I accepted your review comments.
I will re-send the code.

Thanks,
Raju.

On Wed, Aug 24, 2016 at 03:06:44PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> > +static int vsc85xx_mac_if_set(struct phy_device *phydev,
> > + phy_interface_t   *interface)
> > +{
> > +   int rc;
> > +   u16 reg_val;
> > +
> > +   mutex_lock(>lock);
> > +   reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
> > +   switch (*interface) {
> > +   case PHY_INTERFACE_MODE_RGMII:
> > +   reg_val &= ~(MAC_IF_SELECTION_MASK);
> > +   reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
> > +   break;
> > +   case PHY_INTERFACE_MODE_RMII:
> > +   reg_val &= ~(MAC_IF_SELECTION_MASK);
> > +   reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
> > +   break;
> > +   case PHY_INTERFACE_MODE_MII:
> > +   case PHY_INTERFACE_MODE_GMII:
> > +   default:
> > +   reg_val &= ~(MAC_IF_SELECTION_MASK);
> > +   reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);
> > +   break;
> > +   }
> > +   rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
> > +   if (rc != 0)
> > +   goto out_unlock;
> > +
> > +   rc = vsc85xx_soft_reset(phydev);
> > +
> > +out_unlock:
> > +   mutex_unlock(>lock);
> > +
> > +   return rc;
> > +}
> 
> Again, you need to justify why you are doing something completely
> different to all other phy drivers. You cannot you do what
> m88e1121_config_aneg(), mv88e111_config_init(), dp83867_config_init()
> does?
> 
> Andrew

Re: [PATCH 1/4] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

Hi Andrew,

Thank you for review the code and valuable comments.
I accepted your review comments.
I too use the Device Tree for Edge-rate and MAC interface 
configuration.

Thanks,
Raju.

On Wed, Aug 24, 2016 at 02:59:34PM +0200, Andrew Lunn wrote:
> EXTERNAL EMAIL
> 
> 
> On Wed, Aug 24, 2016 at 12:20:03PM +, Raju Lakkaraju wrote:
> > From: Nagaraju Lakkaraju <raju.lakkar...@microsemi.com>
> >
> > Edge rate control support will be added for VSC 85xx Microsemi PHYs.
> 
> > diff --git a/include/linux/phy.h b/include/linux/phy.h
> > index 2d24b28..8ec4c09 100644
> > --- a/include/linux/phy.h
> > +++ b/include/linux/phy.h
> > @@ -586,6 +586,8 @@ struct phy_driver {
> > void (*get_strings)(struct phy_device *dev, u8 *data);
> > void (*get_stats)(struct phy_device *dev,
> >   struct ethtool_stats *stats, u64 *data);
> > +   int (*phy_features_set)(struct phy_device *dev);
> > +   int (*phy_features_get)(struct phy_device *dev);
> >  };
> 
> Now we need the missing cover note what should be in 0/4.  What is the
> big picture? How are these two functions supposed to be used? Is there
> going to be a user space API via netlink? Should the MAC driver
> somehow call these functions? Are you going to extend the phylib with
> code to call these?
> 
> Those are all general questions for these two functions.
> 
> Now specifically for edge control, why did you decide not to use
> device tree? Both the micrel and renesas phy driver uses device tree
> for skew control. You need to explain why you need to do something
> different to other drivers.
> 
>   Thanks
> Andrew
> 
> 

[PATCH net-next 1/1] net: phy: Fixed checkpatch errors for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju <raju.lakkar...@microsemi.com>

The existing VSC85xx PHY driver did not follow the coding style and caused 
"checkpatch" to complain. This commit fixes this.

Signed-off-by: Raju Lakkaraju <raju.lakkar...@microsemi.com>
---
 drivers/net/phy/Kconfig |   6 +-
 drivers/net/phy/mscc.c  | 178 
 2 files changed, 92 insertions(+), 92 deletions(-)

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 1c3e07c..87b566f 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -274,9 +274,9 @@ config MICROCHIP_PHY
  Supports the LAN88XX PHYs.
 
 config MICROSEMI_PHY
-tristate "Microsemi PHYs"
----help---
-  Currently supports the VSC8531 and VSC8541 PHYs
+   tristate "Microsemi PHYs"
+   ---help---
+ Currently supports the VSC8531 and VSC8541 PHYs
 
 config NATIONAL_PHY
tristate "National Semiconductor PHYs"
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index ad33390..c09cc4a 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -13,135 +13,135 @@
 #include 
 
 enum rgmii_rx_clock_delay {
-   RGMII_RX_CLK_DELAY_0_2_NS = 0,
-   RGMII_RX_CLK_DELAY_0_8_NS = 1,
-   RGMII_RX_CLK_DELAY_1_1_NS = 2,
-   RGMII_RX_CLK_DELAY_1_7_NS = 3,
-   RGMII_RX_CLK_DELAY_2_0_NS = 4,
-   RGMII_RX_CLK_DELAY_2_3_NS = 5,
-   RGMII_RX_CLK_DELAY_2_6_NS = 6,
-   RGMII_RX_CLK_DELAY_3_4_NS = 7
+   RGMII_RX_CLK_DELAY_0_2_NS = 0,
+   RGMII_RX_CLK_DELAY_0_8_NS = 1,
+   RGMII_RX_CLK_DELAY_1_1_NS = 2,
+   RGMII_RX_CLK_DELAY_1_7_NS = 3,
+   RGMII_RX_CLK_DELAY_2_0_NS = 4,
+   RGMII_RX_CLK_DELAY_2_3_NS = 5,
+   RGMII_RX_CLK_DELAY_2_6_NS = 6,
+   RGMII_RX_CLK_DELAY_3_4_NS = 7
 };
 
-#define MII_VSC85XX_INT_MASK  25
-#define MII_VSC85XX_INT_MASK_MASK 0xa000
-#define MII_VSC85XX_INT_STATUS26
+#define MII_VSC85XX_INT_MASK 25
+#define MII_VSC85XX_INT_MASK_MASK0xa000
+#define MII_VSC85XX_INT_STATUS   26
 
-#define MSCC_EXT_PAGE_ACCESS  31
-#define MSCC_PHY_PAGE_STANDARD0x /* Standard registers */
-#define MSCC_PHY_PAGE_EXTENDED_2  0x0002 /* Extended reg - page 2 */
+#define MSCC_EXT_PAGE_ACCESS 31
+#define MSCC_PHY_PAGE_STANDARD   0x /* Standard registers */
+#define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
 
 /* Extended Page 2 Registers */
-#define MSCC_PHY_RGMII_CNTL   20
-#define RGMII_RX_CLK_DELAY_MASK   0x0070
-#define RGMII_RX_CLK_DELAY_POS4
+#define MSCC_PHY_RGMII_CNTL  20
+#define RGMII_RX_CLK_DELAY_MASK  0x0070
+#define RGMII_RX_CLK_DELAY_POS   4
 
 /* Microsemi PHY ID's */
-#define PHY_ID_VSC85310x00070570
-#define PHY_ID_VSC85410x00070770
+#define PHY_ID_VSC8531   0x00070570
+#define PHY_ID_VSC8541   0x00070770
 
 static int vsc85xx_phy_page_set(struct phy_device *phydev, u8 page)
 {
-   int rc;
+   int rc;
 
-   rc = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
-   return rc;
+   rc = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
+   return rc;
 }
 
 static int vsc85xx_default_config(struct phy_device *phydev)
 {
-   int rc;
-   u16 reg_val;
+   int rc;
+   u16 reg_val;
 
-   mutex_lock(>lock);
-   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
-   if (rc != 0)
-   goto out_unlock;
+   mutex_lock(>lock);
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
+   if (rc != 0)
+   goto out_unlock;
 
-   reg_val = phy_read(phydev, MSCC_PHY_RGMII_CNTL);
-   reg_val &= ~(RGMII_RX_CLK_DELAY_MASK);
-   reg_val |= (RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS);
-   phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val);
-   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
+   reg_val = phy_read(phydev, MSCC_PHY_RGMII_CNTL);
+   reg_val &= ~(RGMII_RX_CLK_DELAY_MASK);
+   reg_val |= (RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS);
+   phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val);
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
 
 out_unlock:
-   mutex_unlock(>lock);
+   mutex_unlock(>lock);
 
-   return rc;
+   return rc;
 }
 
 static int vsc85xx_config_init(struct phy_device *phydev)
 {
-   int rc;
+   int rc;
 
-   rc = vsc85xx_default_config(phydev);
-   if (rc)
-   return rc;
-   rc = genphy_config_init(phydev);
+   rc = vsc85xx_default_config(phydev);
+   if (rc)
+   return rc;
+   rc = genphy_config_init(phydev);
 
-   return rc;
+   return rc;
 }
 
 static int vs

Re: [PATCH 0/4] net: phy: Register header file for Microsemi PHYs.

[Raju Lakkaraju]

Hi Florian,

I would like to share these register definitions share between Microsemi 
multiple drivers.
I refer the existing PHY drivers and follow the similar to "dp83640_reg.h" for 
register definitions.

Thanks,
Raju. 
On Wed, Aug 24, 2016 at 10:15:33AM -0700, Florian Fainelli wrote:
> EXTERNAL EMAIL
> 
> 
> On 08/24/2016 04:58 AM, Raju Lakkaraju wrote:
> > From: Nagaraju Lakkaraju <raju.lakkar...@microsemi.com>
> >
> > This is Microsemi's VSC 85xx PHY register definitions header file.
> 
> Please keep these register definitions local to the code using them
> unless they are shared between multiple drivers.
> --
> Florian

[PATCH 3/4] net: phy: Add read driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Nagaraju Lakkaraju 

PHY Read support will be added for VSC 85xx Microsemi PHYs.

Signed-off-by: Nagaraju Lakkaraju 
---
 drivers/net/phy/mscc.c | 25 +
 include/linux/mscc.h   |  8 
 2 files changed, 33 insertions(+)

diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index 60d9d5f..5a74f81 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -194,6 +194,28 @@ static int vsc85xx_mac_if_get(struct phy_device *phydev,
return rc;
 }

+static int vsc85xx_phy_read_reg(struct phy_device *phydev,
+   struct phy_reg_op *data)
+{
+   int rc = 0;
+   u16 reg_addr = data->reg;
+   u8  page = data->pg;
+   u16 reg_val;
+
+   if (page != 0) {
+   mutex_lock(>lock);
+   rc = vsc85xx_phy_page_set(phydev, page);
+   reg_val = phy_read(phydev, reg_addr);
+   rc = vsc85xx_phy_page_set(phydev, 0);
+   mutex_unlock(>lock);
+   } else {
+   reg_val = phy_read(phydev, reg_addr);
+   }
+   data->val = reg_val;
+
+   return rc;
+}
+
 static int vsc85xx_features_set(struct phy_device *phydev)
 {
int rc = 0;
@@ -225,6 +247,9 @@ static int vsc85xx_features_get(struct phy_device *phydev)
case PHY_MAC_IF:
rc = vsc85xx_mac_if_get(phydev, >mac_if);
break;
+   case PHY_READ_REG:
+   rc = vsc85xx_phy_read_reg(phydev, ftrs->data);
+   break;
default:
break;
}
diff --git a/include/linux/mscc.h b/include/linux/mscc.h
index dcfd0ae..4265da7 100644
--- a/include/linux/mscc.h
+++ b/include/linux/mscc.h
@@ -12,6 +12,7 @@
 enum phy_features {
PHY_EDGE_RATE_CONTROL = 0,
PHY_MAC_IF= 1,
+   PHY_READ_REG  = 2,
PHY_SUPPORTED_FEATURES_MAX
 };

@@ -26,10 +27,17 @@ enum rgmii_rx_clock_delay {
RGMII_RX_CLK_DELAY_3_4_NS = 7
 };

+struct phy_reg_op {
+   u16 reg;
+   u16 val;
+   u8  pg;
+};
+
 struct phy_features_t {
enum phy_features cmd;   /* PHY Supported Features */
u8   rate;   /* Edge rate control */
phy_interface_t mac_if;  /* MAC interface config */
+   struct phy_reg_op *data; /* Read/Write register operatioins */
 };

 #endif /*  __LINUX_MSCC_H */
-- 
2.7.4

[PATCH 1/4] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Nagaraju Lakkaraju 

Edge rate control support will be added for VSC 85xx Microsemi PHYs.

Signed-off-by: Nagaraju Lakkaraju 
---
 drivers/net/phy/mscc.c | 109 +
 include/linux/mscc.h   |  34 +++
 include/linux/phy.h|   2 +
 3 files changed, 118 insertions(+), 27 deletions(-)
 create mode 100644 include/linux/mscc.h

diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index 6cc3036..963bf64 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -11,34 +11,9 @@
 #include 
 #include 
 #include 
+#include 

-enum rgmii_rx_clock_delay {
-   RGMII_RX_CLK_DELAY_0_2_NS = 0,
-   RGMII_RX_CLK_DELAY_0_8_NS = 1,
-   RGMII_RX_CLK_DELAY_1_1_NS = 2,
-   RGMII_RX_CLK_DELAY_1_7_NS = 3,
-   RGMII_RX_CLK_DELAY_2_0_NS = 4,
-   RGMII_RX_CLK_DELAY_2_3_NS = 5,
-   RGMII_RX_CLK_DELAY_2_6_NS = 6,
-   RGMII_RX_CLK_DELAY_3_4_NS = 7
-};
-
-#define MII_VSC85XX_INT_MASK  25
-#define MII_VSC85XX_INT_MASK_MASK 0xa000
-#define MII_VSC85XX_INT_STATUS26
-
-#define MSCC_EXT_PAGE_ACCESS  31
-#define MSCC_PHY_PAGE_STANDARD0x /* Standard registers */
-#define MSCC_PHY_PAGE_EXTENDED_2  0x0002 /* Extended reg - page 2 */
-
-/* Extended Page 2 Registers */
-#define MSCC_PHY_RGMII_CNTL   20
-#define RGMII_RX_CLK_DELAY_MASK   0x0070
-#define RGMII_RX_CLK_DELAY_POS4
-
-/* Microsemi PHY ID's */
-#define PHY_ID_VSC85310x00070570
-#define PHY_ID_VSC85410x00070770
+#include "mscc_reg.h"

 static int vsc85xx_phy_page_set(struct phy_device *phydev, u8 page)
 {
@@ -109,6 +84,82 @@ static int vsc85xx_config_intr(struct phy_device *phydev)
return rc;
 }

+static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev,
+ u8 *rate)
+{
+   int rc;
+   u16 reg_val;
+   u8  edge_rate = *rate;
+
+   mutex_lock(>lock);
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
+   if (rc != 0)
+   goto out_unlock;
+   reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
+   reg_val &= ~(EDGE_RATE_CNTL_MASK);
+   reg_val |= (edge_rate << EDGE_RATE_CNTL_POS);
+   phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
+
+out_unlock:
+   mutex_unlock(>lock);
+
+   return rc;
+}
+
+static int vsc85xx_edge_rate_cntl_get(struct phy_device *phydev,
+ u8 *rate)
+{
+   int rc;
+   u16 reg_val;
+
+   mutex_lock(>lock);
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
+   if (rc != 0)
+   goto out_unlock;
+   reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
+   reg_val &= EDGE_RATE_CNTL_MASK;
+   *rate = reg_val >> EDGE_RATE_CNTL_POS;
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
+
+out_unlock:
+   mutex_unlock(>lock);
+
+   return rc;
+}
+
+static int vsc85xx_features_set(struct phy_device *phydev)
+{
+   int rc = 0;
+   struct phy_features_t *ftrs = (struct phy_features_t *)phydev->priv;
+
+   switch (ftrs->cmd) {
+   case PHY_EDGE_RATE_CONTROL:
+   rc = vsc85xx_edge_rate_cntl_set(phydev, >rate);
+   break;
+   default:
+   break;
+   }
+
+   return rc;
+}
+
+static int vsc85xx_features_get(struct phy_device *phydev)
+{
+   int rc = 0;
+   struct phy_features_t *ftrs = (struct phy_features_t *)phydev->priv;
+
+   switch (ftrs->cmd) {
+   case PHY_EDGE_RATE_CONTROL:
+   rc = vsc85xx_edge_rate_cntl_get(phydev, >rate);
+   break;
+   default:
+   break;
+   }
+
+   return rc;
+}
+
 /* Microsemi VSC85xx PHYs */
 static struct phy_driver vsc85xx_driver[] = {
 {
@@ -126,6 +177,8 @@ static struct phy_driver vsc85xx_driver[] = {
.config_intr= _config_intr,
.suspend= _suspend,
.resume = _resume,
+   .phy_features_set = _features_set,
+   .phy_features_get = _features_get,
 },
 {
.phy_id = PHY_ID_VSC8541,
@@ -142,6 +195,8 @@ static struct phy_driver vsc85xx_driver[] = {
.config_intr= _config_intr,
.suspend= _suspend,
.resume = _resume,
+   .phy_features_set = _features_set,
+   .phy_features_get = _features_get,
 }

 };
diff --git a/include/linux/mscc.h b/include/linux/mscc.h
new file mode 100644
index 000..b80a2ac
--- /dev/null
+++ b/include/linux/mscc.h
@@ -0,0 +1,34 @@
+/*
+ * Driver for Microsemi VSC85xx PHYs
+ *
+ * Author: Nagaraju Lakkaraju
+ * License: Dual MIT/GPL
+ * Copyright (c) 2016 Microsemi Corporation
+ */
+
+#ifndef 

[PATCH 4/4] net: phy: Add write driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Nagaraju Lakkaraju 

PHY write register support will be added for VSC 85xx Microsemi PHYs.

Signed-off-by: Nagaraju Lakkaraju 
---
 drivers/net/phy/mscc.c | 24 
 include/linux/mscc.h   |  1 +
 2 files changed, 25 insertions(+)

diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index 5a74f81..9315fde 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -194,6 +194,27 @@ static int vsc85xx_mac_if_get(struct phy_device *phydev,
return rc;
 }

+static int vsc85xx_phy_write_reg(struct phy_device *phydev,
+struct phy_reg_op *data)
+{
+   int rc;
+   u16 reg_addr = data->reg;
+   u16 reg_val = data->val;
+   u8  page = data->pg;
+
+   if (page != 0) {
+   mutex_lock(>lock);
+   vsc85xx_phy_page_set(phydev, page);
+   rc = phy_write(phydev, reg_addr, reg_val);
+   vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
+   mutex_unlock(>lock);
+   } else {
+   rc = phy_write(phydev, reg_addr, reg_val);
+   }
+
+   return rc;
+}
+
 static int vsc85xx_phy_read_reg(struct phy_device *phydev,
struct phy_reg_op *data)
 {
@@ -228,6 +249,9 @@ static int vsc85xx_features_set(struct phy_device *phydev)
case PHY_MAC_IF:
rc = vsc85xx_mac_if_set(phydev, >mac_if);
break;
+   case PHY_WRITE_REG:
+   rc = vsc85xx_phy_write_reg(phydev, ftrs->data);
+   break;
default:
break;
}
diff --git a/include/linux/mscc.h b/include/linux/mscc.h
index 4265da7..b2cf373 100644
--- a/include/linux/mscc.h
+++ b/include/linux/mscc.h
@@ -13,6 +13,7 @@ enum phy_features {
PHY_EDGE_RATE_CONTROL = 0,
PHY_MAC_IF= 1,
PHY_READ_REG  = 2,
+   PHY_WRITE_REG = 3,
PHY_SUPPORTED_FEATURES_MAX
 };

-- 
2.7.4

[PATCH 2/4] net: phy: Add MAC-IF driver for Microsemi PHYs.

[Raju Lakkaraju]

From: Nagaraju Lakkaraju 

MAC Interface support will be added for VSC 85xx Microsemi PHYs.

Signed-off-by: Nagaraju Lakkaraju 
---
 drivers/net/phy/mscc.c | 72 ++
 include/linux/mscc.h   |  2 ++
 2 files changed, 74 insertions(+)

diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index 963bf64..60d9d5f 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -84,6 +84,18 @@ static int vsc85xx_config_intr(struct phy_device *phydev)
return rc;
 }

+static int vsc85xx_soft_reset(struct phy_device *phydev)
+{
+   int rc;
+   u16 reg_val;
+
+   reg_val = phy_read(phydev, MII_BMCR);
+   reg_val |= BMCR_RESET;
+   rc = phy_write(phydev, MII_BMCR, reg_val);
+
+   return rc;
+}
+
 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev,
  u8 *rate)
 {
@@ -128,6 +140,60 @@ out_unlock:
return rc;
 }

+static int vsc85xx_mac_if_set(struct phy_device *phydev,
+ phy_interface_t   *interface)
+{
+   int rc;
+   u16 reg_val;
+
+   mutex_lock(>lock);
+   reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
+   switch (*interface) {
+   case PHY_INTERFACE_MODE_RGMII:
+   reg_val &= ~(MAC_IF_SELECTION_MASK);
+   reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
+   break;
+   case PHY_INTERFACE_MODE_RMII:
+   reg_val &= ~(MAC_IF_SELECTION_MASK);
+   reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
+   break;
+   case PHY_INTERFACE_MODE_MII:
+   case PHY_INTERFACE_MODE_GMII:
+   default:
+   reg_val &= ~(MAC_IF_SELECTION_MASK);
+   reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);
+   break;
+   }
+   rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
+   if (rc != 0)
+   goto out_unlock;
+
+   rc = vsc85xx_soft_reset(phydev);
+
+out_unlock:
+   mutex_unlock(>lock);
+
+   return rc;
+}
+
+static int vsc85xx_mac_if_get(struct phy_device *phydev,
+ phy_interface_t   *interface)
+{
+   int rc = 0;
+   u16 reg_val;
+
+   reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
+   reg_val = ((reg_val & MAC_IF_SELECTION_MASK) >> MAC_IF_SELECTION_POS);
+   if (reg_val == MAC_IF_SELECTION_RGMII)
+   *interface = PHY_INTERFACE_MODE_RGMII;
+   else if (reg_val == MAC_IF_SELECTION_RMII)
+   *interface = PHY_INTERFACE_MODE_RMII;
+   else
+   *interface = PHY_INTERFACE_MODE_GMII;
+
+   return rc;
+}
+
 static int vsc85xx_features_set(struct phy_device *phydev)
 {
int rc = 0;
@@ -137,6 +203,9 @@ static int vsc85xx_features_set(struct phy_device *phydev)
case PHY_EDGE_RATE_CONTROL:
rc = vsc85xx_edge_rate_cntl_set(phydev, >rate);
break;
+   case PHY_MAC_IF:
+   rc = vsc85xx_mac_if_set(phydev, >mac_if);
+   break;
default:
break;
}
@@ -153,6 +222,9 @@ static int vsc85xx_features_get(struct phy_device *phydev)
case PHY_EDGE_RATE_CONTROL:
rc = vsc85xx_edge_rate_cntl_get(phydev, >rate);
break;
+   case PHY_MAC_IF:
+   rc = vsc85xx_mac_if_get(phydev, >mac_if);
+   break;
default:
break;
}
diff --git a/include/linux/mscc.h b/include/linux/mscc.h
index b80a2ac..dcfd0ae 100644
--- a/include/linux/mscc.h
+++ b/include/linux/mscc.h
@@ -11,6 +11,7 @@

 enum phy_features {
PHY_EDGE_RATE_CONTROL = 0,
+   PHY_MAC_IF= 1,
PHY_SUPPORTED_FEATURES_MAX
 };

@@ -28,6 +29,7 @@ enum rgmii_rx_clock_delay {
 struct phy_features_t {
enum phy_features cmd;   /* PHY Supported Features */
u8   rate;   /* Edge rate control */
+   phy_interface_t mac_if;  /* MAC interface config */
 };

 #endif /*  __LINUX_MSCC_H */
-- 
2.7.4

[PATCH 0/4] net: phy: Register header file for Microsemi PHYs.

[Raju Lakkaraju]

From: Nagaraju Lakkaraju 

This is Microsemi's VSC 85xx PHY register definitions header file.

Signed-off-by: Nagaraju Lakkaraju 
---
 drivers/net/phy/mscc_reg.h | 135 +
 1 file changed, 135 insertions(+)
 create mode 100644 drivers/net/phy/mscc_reg.h

diff --git a/drivers/net/phy/mscc_reg.h b/drivers/net/phy/mscc_reg.h
new file mode 100644
index 000..ddb825c
--- /dev/null
+++ b/drivers/net/phy/mscc_reg.h
@@ -0,0 +1,135 @@
+/*
+ * Driver for Microsemi VSC85xx PHYs
+ *
+ * Author: Nagaraju Lakkaraju
+ * License: Dual MIT/GPL
+ * Copyright (c) 2016 Microsemi Corporation
+ */
+
+#ifndef __MSCC_REG_H
+#define __MSCC_REG_H
+
+/* Microsemi VSC85xx PHY registers */
+/* IEEE 802. Std Registers */
+#define MSCC_PHY_BYPASS_CONTROL18
+#define DISABLE_HP_AUTO_MDIX_MASK  0x0080
+#define DISABLE_PAIR_SWAP_CORR_MASK0x0020
+#define DISABLE_POLARITY_CORR_MASK 0x0010
+
+#define MSCC_PHY_EXT_PHY_CNTL_123
+#define MAC_IF_SELECTION_MASK  0x1800
+#define MAC_IF_SELECTION_GMII  0
+#define MAC_IF_SELECTION_RMII  1
+#define MAC_IF_SELECTION_RGMII 2
+#define MAC_IF_SELECTION_POS   11
+#define FAR_END_LOOPBACK_MODE_MASK 0x0008
+
+#define MSCC_PHY_EXT_PHY_CNTL_224
+#define CONNECTOR_LOOPBACK_MASK0x0001
+#define JUMBO_PACKET_MODE_MASK 0x0030
+#define JUMBO_PACKET_MODE_POS  4
+
+#define MII_VSC85XX_INT_MASK   25
+#define MII_VSC85XX_INT_MASK_MDINT 0x8000
+#define MII_VSC85XX_INT_MASK_SPEED 0x4000
+#define MII_VSC85XX_INT_MASK_LINK  0x2000
+#define MII_VSC85XX_INT_MASK_DUPLEX0x1000
+#define MII_VSC85XX_INT_MASK_ANEG_ERR  0x0800
+#define MII_VSC85XX_INT_MASK_ANEG_COM  0x0400
+#define MII_VSC85XX_INT_MASK_POE   0x0200
+#define MII_VSC85XX_INT_MASK_SYM   0x0100
+#define MII_VSC85XX_INT_MASK_FLF   0x0080
+#define MII_VSC85XX_INT_MASK_WOL   0x0040
+#define MII_VSC85XX_INT_MASK_EXT   0x0020
+#define MII_VSC85XX_INT_MASK_RESV  0x0010
+#define MII_VSC85XX_INT_MASK_FCI   0x0008
+#define MII_VSC85XX_INT_MASK_LDI   0x0004
+#define MII_VSC85XX_INT_MASK_MSE   0x0002
+#define MII_VSC85XX_INT_MASK_RX_ER 0x0001
+#define MII_VSC85XX_INT_MASK_MASK  0xa000
+
+#define MII_VSC85XX_INT_STATUS 26
+#define MSCC_PHY_DEV_AUX_CNTL  28
+#define HP_AUTO_MDIX_X_OVER_IND_MASK   0x2000
+#define ACTIPHY_TIME_OUT_BIT_7 0x0080
+#define ACTIPHY_TIME_OUT_BIT_2 0x0004
+#define ACTIPHY_TIME_OUT_MASK  0x0084
+#define ACTIPHY_MODE_ENT   0x0040
+
+#define MSCC_EXT_PAGE_ACCESS   31
+#define MSCC_PHY_PAGE_STANDARD 0x /* Standard registers */
+#define MSCC_PHY_PAGE_EXTENDED 0x0001 /* Extended registers */
+#define MSCC_PHY_PAGE_EXTENDED_2   0x0002 /* Extended registers - page 2 */
+#define MSCC_PHY_PAGE_EXTENDED_3   0x0003 /* Extended registers - page 3 */
+#define MSCC_PHY_PAGE_EXTENDED_4   0x0004 /* Extended registers - page 4 */
+#define MSCC_PHY_PAGE_GPIO 0x0010 /* GPIO registers */
+
+/* Extended Page 1 Registers */
+#define MSCC_PHY_EXT_MODE_CNTL 19
+#define FORCE_MDI_CROSSOVER_MASK   0x000C
+#define FORCE_MDI_CROSSOVER_NORMAL 0
+#define FORCE_MDI_CROSSOVER_MDI2
+#define FORCE_MDI_CROSSOVER_MDIX   3
+#define FORCE_MDI_CROSSOVER_POS2
+
+#define MSCC_PHY_ACTIPHY_CNTL  20
+#define ACTIPHY_SLEEP_TIMER_MASK   0x6000
+#define ACTIPHY_SLEEP_TIMER_POS13
+#define ACTIPHY_WAKEUP_TIMER_MASK  0x1800
+#define ACTIPHY_WAKEUP_TIMER_POS   11
+#define LINK_SPD_DOWNSHIFT_EN  0x0010
+#define LINK_SPD_DOWNSHIFT_CNTL_POS2
+#define LINK_SPD_DOWNSHIFT_CNTL_MASK   0x000C
+
+#define MSCC_PHY_POE_MISC  23
+#define INLINE_POE_DETECTION   0x0400
+#define INLINE_POE_STATUS_MASK 0x0300
+#define INLINE_POE_STATUS_POS  8
+
+/* Extended Page 2 Registers */
+#define MSCC_PHY_RGMII_CNTL20
+#define FLF2_ENABLE0x8000
+#define SOF_ENABLE 0x1000
+#define RGMII_RX_CLK_DELAY_MASK0x0070
+#define RGMII_RX_CLK_DELAY_POS 4
+
+#define MSCC_PHY_WOL_LOWER_MAC_ADDR21
+#define MSCC_PHY_WOL_MID_MAC_ADDR  22
+#define MSCC_PHY_WOL_UPPER_MAC_ADDR23
+#define MSCC_PHY_WOL_LOWER_PASSWD  24
+#define MSCC_PHY_WOL_MID_PASSWD25
+#define MSCC_PHY_WOL_UPPER_PASSWD  26
+
+#define MSCC_PHY_WOL_MAC_CONTROL   27
+#define EDGE_RATE_CNTL_POS 5
+#define EDGE_RATE_CNTL_MASK0x00E0
+#define SECURE_ON_ENABLE   0x8000
+#define SECURE_ON_PASSWD_LEN_4 0x4000
+
+#define MSCC_PHY_RING_RESI_CONTROL 30
+#define RR_STARTUP_ENABLE  0x8000
+#define RR_ADVERTISE_ENABLE0x4000
+#define RR_LP_ADVERTISE0x2000
+#define RR_FORCE_ENABLE0x1000
+#define RR_STATUS_MASK 

[PATCH v1 1/1] net: phy: Add Edge-rate driver for Microsemi PHYs.

[Raju Lakkaraju]

Hello,

The Microsemi PHY (VSC 85xx) device includes programmable control of the 
rise/fall times for the MAC interface signals.
The default setting will select the fastest rise/fall times. With the 
edge_rate_cntl_set( ) function control the rise/fall time.
Edge rate control status will get by edge_rate_cntl_get( ) function.

Test Setup:
-
This feature tested on Beagle bone Black with VSC 8531 PHY hardware.

Please review and code and send your comments.

Thanks,
Raju.

>From bf25b48bebb896b5dd489294d144c0dfdfa788f1 Mon Sep 17 00:00:00 2001
From: Nagaraju Lakkaraju 
Date: Tue, 23 Aug 2016 18:29:17 +0530
Subject: [PATCH v1 1/1] net: phy: Add Edge-rate driver for Microsemi PHYs.

Signed-off-by: Nagaraju Lakkaraju 
---
 drivers/net/phy/mscc.c | 109 +
 include/linux/mscc.h   |  34 +++
 include/linux/phy.h|   2 +
 3 files changed, 118 insertions(+), 27 deletions(-)
 create mode 100644 include/linux/mscc.h

diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index 6cc3036..963bf64 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -11,34 +11,9 @@
 #include 
 #include 
 #include 
+#include 

-enum rgmii_rx_clock_delay {
-   RGMII_RX_CLK_DELAY_0_2_NS = 0,
-   RGMII_RX_CLK_DELAY_0_8_NS = 1,
-   RGMII_RX_CLK_DELAY_1_1_NS = 2,
-   RGMII_RX_CLK_DELAY_1_7_NS = 3,
-   RGMII_RX_CLK_DELAY_2_0_NS = 4,
-   RGMII_RX_CLK_DELAY_2_3_NS = 5,
-   RGMII_RX_CLK_DELAY_2_6_NS = 6,
-   RGMII_RX_CLK_DELAY_3_4_NS = 7
-};
-
-#define MII_VSC85XX_INT_MASK  25
-#define MII_VSC85XX_INT_MASK_MASK 0xa000
-#define MII_VSC85XX_INT_STATUS26
-
-#define MSCC_EXT_PAGE_ACCESS  31
-#define MSCC_PHY_PAGE_STANDARD0x /* Standard registers */
-#define MSCC_PHY_PAGE_EXTENDED_2  0x0002 /* Extended reg - page 2 */
-
-/* Extended Page 2 Registers */
-#define MSCC_PHY_RGMII_CNTL   20
-#define RGMII_RX_CLK_DELAY_MASK   0x0070
-#define RGMII_RX_CLK_DELAY_POS4
-
-/* Microsemi PHY ID's */
-#define PHY_ID_VSC85310x00070570
-#define PHY_ID_VSC85410x00070770
+#include "mscc_reg.h"

 static int vsc85xx_phy_page_set(struct phy_device *phydev, u8 page)
 {
@@ -109,6 +84,82 @@ static int vsc85xx_config_intr(struct phy_device *phydev)
return rc;
 }

+static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev,
+ u8 *rate)
+{
+   int rc;
+   u16 reg_val;
+   u8  edge_rate = *rate;
+
+   mutex_lock(>lock);
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
+   if (rc != 0)
+   goto out_unlock;
+   reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
+   reg_val &= ~(EDGE_RATE_CNTL_MASK);
+   reg_val |= (edge_rate << EDGE_RATE_CNTL_POS);
+   phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
+
+out_unlock:
+   mutex_unlock(>lock);
+
+   return rc;
+}
+
+static int vsc85xx_edge_rate_cntl_get(struct phy_device *phydev,
+ u8 *rate)
+{
+   int rc;
+   u16 reg_val;
+
+   mutex_lock(>lock);
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
+   if (rc != 0)
+   goto out_unlock;
+   reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
+   reg_val &= EDGE_RATE_CNTL_MASK;
+   *rate = reg_val >> EDGE_RATE_CNTL_POS;
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
+
+out_unlock:
+   mutex_unlock(>lock);
+
+   return rc;
+}
+
+static int vsc85xx_features_set(struct phy_device *phydev)
+{
+   int rc = 0;
+   struct phy_features_t *ftrs = (struct phy_features_t *)phydev->priv;
+
+   switch (ftrs->cmd) {
+   case PHY_EDGE_RATE_CONTROL:
+   rc = vsc85xx_edge_rate_cntl_set(phydev, >rate);
+   break;
+   default:
+   break;
+   }
+
+   return rc;
+}
+
+static int vsc85xx_features_get(struct phy_device *phydev)
+{
+   int rc = 0;
+   struct phy_features_t *ftrs = (struct phy_features_t *)phydev->priv;
+
+   switch (ftrs->cmd) {
+   case PHY_EDGE_RATE_CONTROL:
+   rc = vsc85xx_edge_rate_cntl_get(phydev, >rate);
+   break;
+   default:
+   break;
+   }
+
+   return rc;
+}
+
 /* Microsemi VSC85xx PHYs */
 static struct phy_driver vsc85xx_driver[] = {
 {
@@ -126,6 +177,8 @@ static struct phy_driver vsc85xx_driver[] = {
.config_intr= _config_intr,
.suspend= _suspend,
.resume = _resume,
+   .phy_features_set = _features_set,
+   .phy_features_get = _features_get,
 },
 {
.phy_id = PHY_ID_VSC8541,
@@ -142,6 

RE: Microsemi VSC 8531/41 PHY Driver

[Raju Lakkaraju]

Hello Andrew,

Thank you for given valuable comments.
Please see the my responses inline.

Thanks,
Raju

-Original Message-
From: Andrew Lunn [mailto:and...@lunn.ch] 
Sent: Tuesday, July 26, 2016 6:14 PM
To: Raju Lakkaraju
Cc: netdev@vger.kernel.org; f.faine...@gmail.com; Allan Nielsen
Subject: Re: Microsemi VSC 8531/41 PHY Driver

EXTERNAL EMAIL


> +/* RGMII Rx Clock delay value change with board lay-out */ static u8 
> +rgmii_rx_clk_delay = RGMII_RX_CLK_DELAY_1_1_NS;

Doesn't this stop you from having a board with two PHYs with different layouts? 
You should be getting this value from the device tree.

Raju: As of now, RGMII Rx clock delay value should be 1.1 nsec as 
optimized/recommended value. 
We tested on Beaglebone Black with VSC 8531 PHY.
We would like to provide new function to configure correct/require value based 
on PHY layouts 
alone with other RGMII configuration parameters as part of our next 
implementation.

> + phydev->supported = (SUPPORTED_1000baseT_Full |
> +  SUPPORTED_1000baseT_Half |
> +  SUPPORTED_100baseT_Full  |
> +  SUPPORTED_100baseT_Half  |
> +  SUPPORTED_10baseT_Full   |
> +  SUPPORTED_10baseT_Half   |
> +  SUPPORTED_Autoneg|
> +  SUPPORTED_Pause  |
> +  SUPPORTED_Asym_Pause |
> +  SUPPORTED_TP);
> +
> + phydev->speed = SPEED_1000;
> + phydev->duplex = DUPLEX_FULL;
> + phydev->pause = 0;
> + phydev->asym_pause = 0;
> + phydev->interface = PHY_INTERFACE_MODE_RGMII;
> + phydev->mdix = ETH_TP_MDI_AUTO;

Why are you setting all these? This is not normal, if you look at other drivers.

Raju: I would like to update the default values in software data structure 
(phydev). 
Our PHY is 1G speed support device and RGMII supported device.

> +
> + mutex_lock(>lock);

What are you locking against?

Raju: VSC 8531 has different PAGEs. Whenever MDC/MDIO access the PHY control 
registers, 
first set the page number then read/write the register address. Default page 
should be Page 0.
When I want to access not default page register, I have to lock phy device 
access and change 
the page number and register access as atomic operation. 

> + rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
> + if (rc != 0) {
> + rc = -EINVAL;

Why do you overwrite the error code vsc85xx_phy_page_set gives you?

Raju: initially I would like to create new type of Error code. Then, I decided 
to use existing one. 
I accept your comment. I will remove the code.

> + goto out_unlock;
> + }
> + reg_val = phy_read(phydev, MSCC_PHY_RGMII_CNTL);
> + reg_val &= ~(RGMII_RX_CLK_DELAY_MASK);
> + reg_val |= (rgmii_rx_clk_delay << RGMII_RX_CLK_DELAY_POS);
> + phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val);
> + rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
> + if (rc != 0)
> + rc = -EINVAL;

Same here.

Raju: I accept your comment. I will remove the code.

> +
> +out_unlock:
> + mutex_unlock(>lock);
> +
> + return rc;
> +}
> +
> +static int vsc85xx_config_init(struct phy_device *phydev) {
> + int rc = 0;

No need to initialise rc.

Raju: I accept your comment. I will remove the code.

> + rc = vsc85xx_default_config(phydev);

if (rc)
return rc;

> + rc = genphy_config_init(phydev);
> +
> + return rc;

Or just
return genphy_config_init(phydev);

Raju: I accept your comment. I will remove the code.

> +}
> +
> +static int vsc85xx_ack_interrupt(struct phy_device *phydev) {
> + int rc = 0;
> +
> + if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
> + rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
> +
> + return (rc < 0) ? rc : 0;
> +}
> +
> +static int vsc85xx_config_intr(struct phy_device *phydev) {
> + int rc;
> +
> + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
> + rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
> +MII_VSC85XX_INT_MASK_MASK);
> + } else {
> + rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
> + if (rc < 0)
> + return rc;

And the purpose of this read is? I assume it clears an outstanding interrupt? 
If so, shouldn't you do it after disabling interrupts, not before? Otherwise 
you have a race condition.

Raju: The Interrupt status register is read on clean. When, 
PHY_INTERRUPT_DISABLE case, 
I should make sure that status should be clear. If I read the Interrupt status 
registers, it clears all preexisting interrupts.

> + rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
> + }
> +
> + return rc;

  Andrew

RE: Microsemi VSC 8531/41 PHY Driver

[Raju Lakkaraju]

al);
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
+   if (rc != 0)
+   rc = -EINVAL;
+
+out_unlock:
+   mutex_unlock(>lock);
+
+   return rc;
+}
+
+static int vsc85xx_config_init(struct phy_device *phydev)
+{
+   int rc = 0;
+
+   rc = vsc85xx_default_config(phydev);
+   rc = genphy_config_init(phydev);
+
+   return rc;
+}
+
+static int vsc85xx_ack_interrupt(struct phy_device *phydev)
+{
+   int rc = 0;
+
+   if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
+   rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
+
+   return (rc < 0) ? rc : 0;
+}
+
+static int vsc85xx_config_intr(struct phy_device *phydev)
+{
+   int rc;
+
+   if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+   rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
+  MII_VSC85XX_INT_MASK_MASK);
+   } else {
+   rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
+   if (rc < 0)
+   return rc;
+   rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
+   }
+
+   return rc;
+}
+
+/* Microsemi VSC85xx PHYs */
+static struct phy_driver vsc85xx_driver[] = {
+{
+   .phy_id = PHY_ID_VSC8531,
+   .name   = "Microsemi VSC8531",
+   .phy_id_mask= 0xfff0,
+   .features   = PHY_GBIT_FEATURES,
+   .flags  = PHY_HAS_INTERRUPT,
+   .soft_reset = _soft_reset,
+   .config_init= _config_init,
+   .config_aneg= _config_aneg,
+   .aneg_done  = _aneg_done,
+   .read_status= _read_status,
+   .ack_interrupt  = _ack_interrupt,
+   .config_intr= _config_intr,
+   .suspend= _suspend,
+   .resume = _resume,
+},
+{
+   .phy_id = PHY_ID_VSC8541,
+   .name   = "Microsemi VSC8541 SyncE",
+   .phy_id_mask= 0xfff0,
+   .features   = PHY_GBIT_FEATURES,
+   .flags  = PHY_HAS_INTERRUPT,
+   .soft_reset = _soft_reset,
+   .config_init= _config_init,
+   .config_aneg= _config_aneg,
+   .aneg_done  = _aneg_done,
+   .read_status= _read_status,
+   .ack_interrupt  = _ack_interrupt,
+   .config_intr= _config_intr,
+   .suspend= _suspend,
+   .resume = _resume,
+}
+
+};
+
+module_phy_driver(vsc85xx_driver);
+
+static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
+   { PHY_ID_VSC8531, 0xfff0, },
+   { PHY_ID_VSC8541, 0xfff0, },
+   { }
+};
+
+MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl);
+
+MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver");
+MODULE_AUTHOR("Nagaraju Lakkaraju");
+MODULE_LICENSE("Dual MIT/GPL");
-- 
2.7.3


Thanks and regards,
Raju
(Nagaraju Lakkaraju)
Sr. Staff Engg.
Microsemi Communications India Pvt Ltd.
Ph: +91 040 6686 0132

-Original Message-
From: Andrew Lunn [mailto:and...@lunn.ch] 
Sent: Tuesday, July 26, 2016 5:26 PM
To: Raju Lakkaraju
Cc: netdev@vger.kernel.org; f.faine...@gmail.com; Allan Nielsen
Subject: Re: Microsemi VSC 8531/41 PHY Driver

EXTERNAL EMAIL


On Tue, Jul 26, 2016 at 09:49:53AM +, Raju Lakkaraju wrote:
> Hello All,
>
> I would like to introduce myself as Nagaraju Lakkaraju (Raju), is working in 
> Microsemi Communications India Pvt. Ltd (Formerly known as Vitesse 
> Semiconductors Limited) - Hyderabad as Sr. Staff Engineer.
> I do work on Microsemi PHY drivers development.
> Microsemi is developing the new Physical Layer (PHY) chips for Internet Of 
> Things (IoT) products with 1 Gbps link speed.
> As part of the development, Microsemi would like to contribute the new PHYs 
> (i.e. VSC 8531 / VSC 8541) chip drivers in Linux Kernel Open source.
> VSC 8531 / 8541 PHYs will have the following features a part of the basic 
> features like Auto-neg, Speed, Duplex etc.
> 1. Wake on LAN
> 2. Auto MDIX/MDI
> 3. Link Speed Down shift
> 4. Fast Link Failure-2
> 5. Loopbacks (FAR-END, NEAR-END and Connector) 6. Ethernet Packet 
> Generator (EPG) 7. Serial Management Interface (SMI) Interrupt 8. 
> Clock Squelch configuration (SyncE) 9. Jumbo Frame Support 10. In-line 
> Power On Ethernet (PoE) status 11. Acti PHY power Management 12. 
> Energy Efficiency Ethenet (EEE) 13. VeriPHY (Cable Diagnostics) 14. 
> LED configuration 15. Ring Resiliency 16. Start Of Frame Detection 
> (SOF) 17. COMA mode

Some interesting features. Is the datasheet publicly available?

> As part of Initial submission of the Linux Kernel Open source drivers, 
> I developed the VSC 8531 driver basic features and built the Linux Kernel 
> image for Beaglebone Black hardware.
> Also developed Ethtool enhancement for VSC 8531 register access 
> functionality to test the VSC 8531
>
> Test Setup:
> -
> Hardware Details: Beaglebone Black with 

Microsemi VSC 8531/41 PHY Driver

[Raju Lakkaraju]

Hello All,

I would like to introduce myself as Nagaraju Lakkaraju (Raju), is working in 
Microsemi Communications India Pvt. Ltd (Formerly known as Vitesse 
Semiconductors Limited) - Hyderabad as Sr. Staff Engineer.
I do work on Microsemi PHY drivers development.
Microsemi is developing the new Physical Layer (PHY) chips for Internet Of 
Things (IoT) products with 1 Gbps link speed. 
As part of the development, Microsemi would like to contribute the new PHYs 
(i.e. VSC 8531 / VSC 8541) chip drivers in Linux Kernel Open source.
VSC 8531 / 8541 PHYs will have the following features a part of the basic 
features like Auto-neg, Speed, Duplex etc.
1. Wake on LAN 
2. Auto MDIX/MDI 
3. Link Speed Down shift
4. Fast Link Failure-2
5. Loopbacks (FAR-END, NEAR-END and Connector)
6. Ethernet Packet Generator (EPG)
7. Serial Management Interface (SMI) Interrupt
8. Clock Squelch configuration (SyncE)
9. Jumbo Frame Support
10. In-line Power On Ethernet (PoE) status
11. Acti PHY power Management 
12. Energy Efficiency Ethenet (EEE)
13. VeriPHY (Cable Diagnostics)
14. LED configuration
15. Ring Resiliency
16. Start Of Frame Detection (SOF)
17. COMA mode 

As part of Initial submission of the Linux Kernel Open source drivers,
I developed the VSC 8531 driver basic features and built the Linux Kernel image 
for Beaglebone Black hardware.
Also developed Ethtool enhancement for VSC 8531 register access functionality 
to test the VSC 8531 

Test Setup:
-
Hardware Details: Beaglebone Black with VSC 8531 PHY
Software Linux Kernel version: 4.6.4

Microsemi VSC 8531 chip is mount on Beaglebone Black hardware (replaced the 
Microchip PHY) and tested the following features.
1. Auto negotiation
2. Speed change ( 10 Mbps, 100 Mbps and 1 Gbps)
3. Full/Half Duplex
4. Ping 
5. Line rate traffic with Test center

I would like you to review my code and provide me the valuable comments.
Please find the attached git code diff patch.

Thanks and regards,
Raju
(Nagaraju Lakkaraju)
Sr. Staff Engg.
Microsemi Communications India Pvt Ltd.
Ph: +91 040  6686 0132



0001-net-phy-Add-drivers-for-Microsemi-PHYs.patch
Description: 0001-net-phy-Add-drivers-for-Microsemi-PHYs.patch