Add support for SoCs from the rt3050 family. This include rt3050, rt3052,
rt3352 and rt5350. These all have a builtin 5 port 100mbit switch. This patch
includes rudimentary code to power up the switch. There are a lot of magic
values that get written to the switch and the internal phys. These values
come straight from the SDK driver and we do not know the meaning of most of
them.
Signed-off-by: John Crispin
Signed-off-by: Felix Fietkau
Signed-off-by: Michael Lee
---
drivers/net/ethernet/ralink/esw_rt3050.c | 682 ++
drivers/net/ethernet/ralink/esw_rt3050.h | 29 ++
drivers/net/ethernet/ralink/soc_rt3050.c | 154 +++
3 files changed, 865 insertions(+)
create mode 100644 drivers/net/ethernet/ralink/esw_rt3050.c
create mode 100644 drivers/net/ethernet/ralink/esw_rt3050.h
create mode 100644 drivers/net/ethernet/ralink/soc_rt3050.c
diff --git a/drivers/net/ethernet/ralink/esw_rt3050.c
b/drivers/net/ethernet/ralink/esw_rt3050.c
new file mode 100644
index 000..aae6dac
--- /dev/null
+++ b/drivers/net/ethernet/ralink/esw_rt3050.c
@@ -0,0 +1,682 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2015 John Crispin
+ * Copyright (C) 2009-2015 Felix Fietkau
+ * Copyright (C) 2013-2015 Michael Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "ralink_soc_eth.h"
+
+#include
+#include
+
+#include
+
+/* HW limitations for this switch:
+ * - No large frame support (PKT_MAX_LEN at most 1536)
+ * - Can't have untagged vlan and tagged vlan on one port at the same time,
+ * though this might be possible using the undocumented PPE.
+ */
+
+#define RT305X_ESW_REG_ISR 0x00
+#define RT305X_ESW_REG_IMR 0x04
+#define RT305X_ESW_REG_FCT00x08
+#define RT305X_ESW_REG_PFC10x14
+#define RT305X_ESW_REG_ATS 0x24
+#define RT305X_ESW_REG_ATS00x28
+#define RT305X_ESW_REG_ATS10x2c
+#define RT305X_ESW_REG_ATS20x30
+#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
+#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
+#define RT305X_ESW_REG_VMSC(_n)(0x70 + 4 * (_n))
+#define RT305X_ESW_REG_POA 0x80
+#define RT305X_ESW_REG_FPA 0x84
+#define RT305X_ESW_REG_SOCPC 0x8c
+#define RT305X_ESW_REG_POC00x90
+#define RT305X_ESW_REG_POC10x94
+#define RT305X_ESW_REG_POC20x98
+#define RT305X_ESW_REG_SGC 0x9c
+#define RT305X_ESW_REG_STRT0xa0
+#define RT305X_ESW_REG_PCR00xc0
+#define RT305X_ESW_REG_PCR10xc4
+#define RT305X_ESW_REG_FPA20xc8
+#define RT305X_ESW_REG_FCT20xcc
+#define RT305X_ESW_REG_SGC20xe4
+#define RT305X_ESW_REG_P0LED 0xa4
+#define RT305X_ESW_REG_P1LED 0xa8
+#define RT305X_ESW_REG_P2LED 0xac
+#define RT305X_ESW_REG_P3LED 0xb0
+#define RT305X_ESW_REG_P4LED 0xb4
+#define RT305X_ESW_REG_PXPC(_x)(0xe8 + (4 * _x))
+#define RT305X_ESW_REG_P1PC0xec
+#define RT305X_ESW_REG_P2PC0xf0
+#define RT305X_ESW_REG_P3PC0xf4
+#define RT305X_ESW_REG_P4PC0xf8
+#define RT305X_ESW_REG_P5PC0xfc
+
+#define RT305X_ESW_LED_LINK0
+#define RT305X_ESW_LED_100M1
+#define RT305X_ESW_LED_DUPLEX 2
+#define RT305X_ESW_LED_ACTIVITY3
+#define RT305X_ESW_LED_COLLISION 4
+#define RT305X_ESW_LED_LINKACT 5
+#define RT305X_ESW_LED_DUPLCOLL6
+#define RT305X_ESW_LED_10MACT 7
+#define RT305X_ESW_LED_100MACT 8
+/* Additional led states not in datasheet: */
+#define RT305X_ESW_LED_BLINK 10
+#define RT305X_ESW_LED_ON 12
+
+#define RT305X_ESW_LINK_S 25
+#define RT305X_ESW_DUPLEX_S9
+#define RT305X_ESW_SPD_S 0
+
+#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
+#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
+#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
+
+#define RT305X_ESW_PCR1_WT_DONEBIT(0)
+
+#define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
+#define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
+
+#define RT305X_ESW_PVIDC_PVID_M0xfff
+#define RT305X_ESW_PVIDC_PVID_S12