Re: [PATCH] net: phy: Fix mask value write on gmii2rgmii converter speed register.

2017-09-15 Thread Andrew Lunn 
> Can you please point me to that email?

I assume you can search the email lists just as well as i can.

  Andrew

Re: [PATCH] net: phy: Fix mask value write on gmii2rgmii converter speed register.

2017-09-15 Thread Michal Simek 
On 14.9.2017 16:34, Andrew Lunn wrote:
> On Thu, Sep 14, 2017 at 12:46:31PM +0530, Fahad Kunnathadi wrote:
>> To clear Speed Selection in MDIO control register(0x10),
>> ie, clear bits 6 and 13 to zero while keeping other bits same.
>> Before AND operation,The Mask value has to be perform with bitwise NOT
>> operation (ie, ~ operator)
>>
>> This patch clears current speed selection before writing the
>> new speed settings to gmii2rgmii converter
> 
> Hi Fahad
> 
> I expect you will find other issues with this driver. I pointed some
> out at the time it is submitted, but the developers went quiet as soon
> as it was accepted.

Can you please point me to that email?
I will create ticket about it in our system to get them resolved.

Thanks,
Michal

Re: [PATCH] net: phy: Fix mask value write on gmii2rgmii converter speed register.

2017-09-15 Thread Fahad Kunnathadi 
Hi Andrew,

Thank you for review and comments.

I will review this driver code with any review comments before, and update you 
if I could find any..

Best Regards
Fahad K  

- Original Message -
From: "Andrew Lunn" <and...@lunn.ch>
To: "Fahad Kunnathadi" <fahad.kunnath...@dexceldesigns.com>
Cc: "f fainelli" <f.faine...@gmail.com>, netdev@vger.kernel.org, "Michal Simek" 
<michal.si...@xilinx.com>, linux-ker...@vger.kernel.org, "soren brinkmann" 
<soren.brinkm...@xilinx.com>, linux-arm-ker...@lists.infradead.org
Sent: Thursday, September 14, 2017 8:04:54 PM
Subject: Re: [PATCH] net: phy: Fix mask value write on gmii2rgmii converter 
speed register.

On Thu, Sep 14, 2017 at 12:46:31PM +0530, Fahad Kunnathadi wrote:
> To clear Speed Selection in MDIO control register(0x10),
> ie, clear bits 6 and 13 to zero while keeping other bits same.
> Before AND operation,The Mask value has to be perform with bitwise NOT
> operation (ie, ~ operator)
> 
> This patch clears current speed selection before writing the
> new speed settings to gmii2rgmii converter

Hi Fahad

I expect you will find other issues with this driver. I pointed some
out at the time it is submitted, but the developers went quiet as soon
as it was accepted.

Anyway, please ensure David Miller <da...@davemloft.net> gets a copy.

The subject line should be:

[PATCH net] net: phy: Fix mask value write on gmii2rgmii converter speed 
register.

and include a fixes tag:

Fixes: f411a6160bd4 ("net: phy: Add gmiitorgmii converter support")

Reviewed-by: Andrew Lunn <and...@lunn.ch>

Andrew

Re: [PATCH] net: phy: Fix mask value write on gmii2rgmii converter speed register.

2017-09-14 Thread Andrew Lunn 
On Thu, Sep 14, 2017 at 12:46:31PM +0530, Fahad Kunnathadi wrote:
> To clear Speed Selection in MDIO control register(0x10),
> ie, clear bits 6 and 13 to zero while keeping other bits same.
> Before AND operation,The Mask value has to be perform with bitwise NOT
> operation (ie, ~ operator)
> 
> This patch clears current speed selection before writing the
> new speed settings to gmii2rgmii converter

Hi Fahad

I expect you will find other issues with this driver. I pointed some
out at the time it is submitted, but the developers went quiet as soon
as it was accepted.

Anyway, please ensure David Miller  gets a copy.

The subject line should be:

[PATCH net] net: phy: Fix mask value write on gmii2rgmii converter speed 
register.

and include a fixes tag:

Fixes: f411a6160bd4 ("net: phy: Add gmiitorgmii converter support")

Reviewed-by: Andrew Lunn 

Andrew