Re: [OpenWrt-Devel] [PATCH] ar71xx: fix ar724x clock calculation

[Alban]

On Wed,  9 Sep 2015 11:19:31 +0800
Weijie Gao  wrote:

Hi,

I'm working a bit on mainline support for the ATH79 and I would really
like to see such patch making it there. I added this patch to my
tree[1] with a few fixes to the log message. Would you mind submitting
it to mainline?

> Signed-off-by: Weijie Gao 

Signed-off-by should be after the log message.
 
> According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz
> input clock as the REF_CLK instead of 5MHz.

I have a similar problem on AR9132, the board I use (WR1043ND) have a
40MHz oscillator however the computation for the clocks assume a 5MHz
input. Sadly I have no datasheet for the AR9132 so I can't fix the
problem myself :/

> The correct CPU PLL calculation procedure is as follows:
> CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2.

In the patch in my tree I replaced DIV with FB (for feedback i think,
see [2]) as it then match with the register name used in the patch.

Alban

[1] https://github.com/AlbanBedel/linux/tree/ath79
[2] 
https://en.wikipedia.org/wiki/Phase-locked_loop#Feedback_path_and_optional_divider
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Re: [OpenWrt-Devel] [PATCH] ar71xx: fix ar724x clock calculation

[Karl Palsson]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

Weijie Gao  wrote:
> Signed-off-by: Weijie Gao 
> 
> According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz
> input clock as the REF_CLK instead of 5MHz.
> 
> The correct CPU PLL calculation procedure is as follows:
> CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2.
> 
> This patch is compatible with the current calculation procedure with
> default
> DIV and REF_DIV values.
> 
> Test on both AR7240, AR7241 and AR7242.


So, what was the behaviour before?

Cheers,
Karl P

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[OpenWrt-Devel] [PATCH] ar71xx: fix ar724x clock calculation

[Weijie Gao]

Signed-off-by: Weijie Gao 

According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz
input clock as the REF_CLK instead of 5MHz.

The correct CPU PLL calculation procedure is as follows:
CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2.

This patch is compatible with the current calculation procedure with default
DIV and REF_DIV values.

Test on both AR7240, AR7241 and AR7242.
---
 ...MIPS-ath79-ar724x-clock-calculation-fixes.patch | 22 ++
 1 file changed, 22 insertions(+)
 create mode 100644 
target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch

diff --git 
a/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch
 
b/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch
new file mode 100644
index 000..16d4621
--- /dev/null
+++ 
b/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch
@@ -0,0 +1,22 @@
+--- a/arch/mips/ath79/clock.c
 b/arch/mips/ath79/clock.c
+@@ -25,7 +25,7 @@
+ #include "common.h"
+ 
+ #define AR71XX_BASE_FREQ  4000
+-#define AR724X_BASE_FREQ  500
++#define AR724X_BASE_FREQ  4000
+ #define AR913X_BASE_FREQ  500
+ 
+ struct clk {
+@@ -99,8 +99,8 @@
+   div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
+   freq = div * ref_rate;
+ 
+-  div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
+-  freq *= div;
++  div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
++  freq /= div;
+ 
+   cpu_rate = freq;
+ 
-- 
2.1.4
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