Re: [OpenWrt-Devel] [PATCH] octeon: Add MMC support for EdgeRouter ER8
On 18/03/2015 21:04, Jonathan Thibault wrote: On 18/03/15 09:53 AM, John Crispin wrote: Hi Jonathan, nice one, i saw the patch on the lmo mailing list and had this on my todo list for the next days, will give it a shot later on my ER8. do you fancy also sending a version that we can apply to trunk ? John Here you go. Hi Jonathan, just pushed this to trunk and added the sysupgarde fluff around it. the board now boots using blck2mtd and does a squashfs overlay. John ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] [PATCH] octeon: Add MMC support for EdgeRouter ER8
This adds in-kernel support for the octeon mmc controller so that Ubiquiti ER8 are now bootable from their internal storage. Aimed at the BB branch but should work on trunk as well. Pay attention to the change in default value for bb_size in octeon_mmc.c, default was too large (256KB) and caused devm_kzalloc() to fail. Otherwise, those are all patches released by Cavium themselves and adapted to BB. diff --git a/target/linux/octeon/config-default b/target/linux/octeon/config-default index f83daac..f6c0e27 100644 --- a/target/linux/octeon/config-default +++ b/target/linux/octeon/config-default @@ -139,6 +139,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=7 # CONFIG_MIPS_MACHINE is not set CONFIG_MIPS_MT_DISABLED=y CONFIG_MIPS_PGD_C0_CONTEXT=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_OCTEON=y +# CONFIG_MMC_TIFM_SD is not set CONFIG_MODULES_USE_ELF_REL=y CONFIG_MODULES_USE_ELF_RELA=y # CONFIG_MTD_CFI_INTELEXT is not set diff --git a/target/linux/octeon/patches-3.10/0012-MIPS-octeon-add-semaphore-to-serialize-bootbus-access.patch b/target/linux/octeon/patches-3.10/0012-MIPS-octeon-add-semaphore-to-serialize-bootbus-access.patch new file mode 100644 index 000..6650c5b --- /dev/null +++ b/target/linux/octeon/patches-3.10/0012-MIPS-octeon-add-semaphore-to-serialize-bootbus-access.patch @@ -0,0 +1,25 @@ +diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c +index a42110e..01130e9 100644 +--- a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c +@@ -51,6 +51,9 @@ extern void pci_console_init(const char *arg); + + static unsigned long long MAX_MEMORY = 512ull 20; + ++DEFINE_SEMAPHORE(octeon_bootbus_sem); ++EXPORT_SYMBOL(octeon_bootbus_sem); ++ + struct octeon_boot_descriptor *octeon_boot_desc_ptr; + + struct cvmx_bootinfo *octeon_bootinfo; +diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h +index 0415965..de9f74e 100644 +--- a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h +@@ -335,4 +335,6 @@ void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t); + + extern void octeon_fixup_irqs(void); + ++extern struct semaphore octeon_bootbus_sem; ++ + #endif /* __ASM_OCTEON_OCTEON_H */ diff --git a/target/linux/octeon/patches-3.10/0013-MIPS-OCTEON-Update-octeon-model.h-code-for-new-SoCs.patch b/target/linux/octeon/patches-3.10/0013-MIPS-OCTEON-Update-octeon-model.h-code-for-new-SoCs.patch new file mode 100644 index 000..c4d7347 --- /dev/null +++ b/target/linux/octeon/patches-3.10/0013-MIPS-OCTEON-Update-octeon-model.h-code-for-new-SoCs.patch @@ -0,0 +1,105 @@ +diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h +index e2c122c..35d7cbd 100644 +--- a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h +@@ -45,6 +45,7 @@ + */ + + #define OCTEON_FAMILY_MASK 0x0000 ++#define OCTEON_PRID_MASK 0x00ff + + /* Flag bits in top byte */ + /* Ignores revision in model checks */ +@@ -63,6 +64,46 @@ + #define OM_MATCH_6XXX_FAMILY_MODELS 0x4000 + /* Match all cnf7XXX Octeon models. */ + #define OM_MATCH_F7XXX_FAMILY_MODELS 0x8000 ++/* Match all cn7XXX Octeon models. */ ++#define OM_MATCH_7XXX_FAMILY_MODELS 0x1000 ++#define OM_MATCH_FAMILY_MODELS (OM_MATCH_5XXX_FAMILY_MODELS | \ ++ OM_MATCH_6XXX_FAMILY_MODELS | \ ++ OM_MATCH_F7XXX_FAMILY_MODELS | \ ++ OM_MATCH_7XXX_FAMILY_MODELS) ++/* ++ * CN7XXX models with new revision encoding ++ */ ++ ++#define OCTEON_CN73XX_PASS1_0 0x000d9700 ++#define OCTEON_CN73XX (OCTEON_CN73XX_PASS1_0 | OM_IGNORE_REVISION) ++#define OCTEON_CN73XX_PASS1_X (OCTEON_CN73XX_PASS1_0 | \ ++ OM_IGNORE_MINOR_REVISION) ++ ++#define OCTEON_CN70XX_PASS1_0 0x000d9600 ++#define OCTEON_CN70XX_PASS1_1 0x000d9601 ++#define OCTEON_CN70XX_PASS1_2 0x000d9602 ++ ++#define OCTEON_CN70XX_PASS2_0 0x000d9608 ++ ++#define OCTEON_CN70XX (OCTEON_CN70XX_PASS1_0 | OM_IGNORE_REVISION) ++#define OCTEON_CN70XX_PASS1_X (OCTEON_CN70XX_PASS1_0 | \ ++ OM_IGNORE_MINOR_REVISION) ++#define OCTEON_CN70XX_PASS2_X (OCTEON_CN70XX_PASS2_0 | \ ++ OM_IGNORE_MINOR_REVISION) ++ ++#define OCTEON_CN71XX OCTEON_CN70XX ++ ++#define OCTEON_CN78XX_PASS1_0 0x000d9500 ++#define OCTEON_CN78XX_PASS1_1 0x000d9501 ++#define OCTEON_CN78XX_PASS2_0 0x000d9508 ++ ++#define OCTEON_CN78XX (OCTEON_CN78XX_PASS1_0 | OM_IGNORE_REVISION) ++#define OCTEON_CN78XX_PASS1_X (OCTEON_CN78XX_PASS1_0 | \ ++ OM_IGNORE_MINOR_REVISION) ++#define OCTEON_CN78XX_PASS2_X (OCTEON_CN78XX_PASS2_0 | \ ++ OM_IGNORE_MINOR_REVISION) ++ ++#define OCTEON_CN76XX (0x000d9540 | OM_CHECK_SUBMODEL) + + /* + * CNF7XXX models with new revision encoding +@@ -217,6 +258,10 @@ + #define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION) + #define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS) + #define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
Re: [OpenWrt-Devel] [PATCH] octeon: Add MMC support for EdgeRouter ER8
On 18/03/2015 14:50, Jonathan Thibault wrote: This adds in-kernel support for the octeon mmc controller so that Ubiquiti ER8 are now bootable from their internal storage. Aimed at the BB branch but should work on trunk as well. Pay attention to the change in default value for bb_size in octeon_mmc.c, default was too large (256KB) and caused devm_kzalloc() to fail. Otherwise, those are all patches released by Cavium themselves and adapted to BB. Hi Jonathan, nice one, i saw the patch on the lmo mailing list and had this on my todo list for the next days, will give it a shot later on my ER8. do you fancy also sending a version that we can apply to trunk ? John ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] [PATCH] octeon: Add MMC support for EdgeRouter ER8
On 18/03/15 09:53 AM, John Crispin wrote: Hi Jonathan, nice one, i saw the patch on the lmo mailing list and had this on my todo list for the next days, will give it a shot later on my ER8. do you fancy also sending a version that we can apply to trunk ? John Here you go. diff --git a/target/linux/octeon/config-3.18 b/target/linux/octeon/config-3.18 index e68292f..032146e 100644 --- a/target/linux/octeon/config-3.18 +++ b/target/linux/octeon/config-3.18 @@ -148,6 +148,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT_7=y # CONFIG_MIPS_MACHINE is not set # CONFIG_MIPS_PARAVIRT is not set CONFIG_MIPS_PGD_C0_CONTEXT=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_OCTEON=y +# CONFIG_MMC_TIFM_SD is not set CONFIG_MODULES_USE_ELF_REL=y CONFIG_MODULES_USE_ELF_RELA=y # CONFIG_MTD_CFI_INTELEXT is not set diff --git a/target/linux/octeon/patches-3.18/130-MIPS-octeon-add-semaphore-to-serialize-bootbus-access.patch b/target/linux/octeon/patches-3.18/130-MIPS-octeon-add-semaphore-to-serialize-bootbus-access.patch new file mode 100644 index 000..6650c5b --- /dev/null +++ b/target/linux/octeon/patches-3.18/130-MIPS-octeon-add-semaphore-to-serialize-bootbus-access.patch @@ -0,0 +1,25 @@ +diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c +index a42110e..01130e9 100644 +--- a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c +@@ -51,6 +51,9 @@ extern void pci_console_init(const char *arg); + + static unsigned long long MAX_MEMORY = 512ull 20; + ++DEFINE_SEMAPHORE(octeon_bootbus_sem); ++EXPORT_SYMBOL(octeon_bootbus_sem); ++ + struct octeon_boot_descriptor *octeon_boot_desc_ptr; + + struct cvmx_bootinfo *octeon_bootinfo; +diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h +index 0415965..de9f74e 100644 +--- a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h +@@ -335,4 +335,6 @@ void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t); + + extern void octeon_fixup_irqs(void); + ++extern struct semaphore octeon_bootbus_sem; ++ + #endif /* __ASM_OCTEON_OCTEON_H */ diff --git a/target/linux/octeon/patches-3.18/140-MIPS-OCTEON-Update-octeon-model.h-code-for-new-SoCs.patch b/target/linux/octeon/patches-3.18/140-MIPS-OCTEON-Update-octeon-model.h-code-for-new-SoCs.patch new file mode 100644 index 000..c4d7347 --- /dev/null +++ b/target/linux/octeon/patches-3.18/140-MIPS-OCTEON-Update-octeon-model.h-code-for-new-SoCs.patch @@ -0,0 +1,105 @@ +diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h +index e2c122c..35d7cbd 100644 +--- a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h +@@ -45,6 +45,7 @@ + */ + + #define OCTEON_FAMILY_MASK0x0000 ++#define OCTEON_PRID_MASK 0x00ff + + /* Flag bits in top byte */ + /* Ignores revision in model checks */ +@@ -63,6 +64,46 @@ + #define OM_MATCH_6XXX_FAMILY_MODELS 0x4000 + /* Match all cnf7XXX Octeon models. */ + #define OM_MATCH_F7XXX_FAMILY_MODELS 0x8000 ++/* Match all cn7XXX Octeon models. */ ++#define OM_MATCH_7XXX_FAMILY_MODELS 0x1000 ++#define OM_MATCH_FAMILY_MODELS(OM_MATCH_5XXX_FAMILY_MODELS | \ ++ OM_MATCH_6XXX_FAMILY_MODELS | \ ++ OM_MATCH_F7XXX_FAMILY_MODELS | \ ++ OM_MATCH_7XXX_FAMILY_MODELS) ++/* ++ * CN7XXX models with new revision encoding ++ */ ++ ++#define OCTEON_CN73XX_PASS1_0 0x000d9700 ++#define OCTEON_CN73XX (OCTEON_CN73XX_PASS1_0 | OM_IGNORE_REVISION) ++#define OCTEON_CN73XX_PASS1_X (OCTEON_CN73XX_PASS1_0 | \ ++ OM_IGNORE_MINOR_REVISION) ++ ++#define OCTEON_CN70XX_PASS1_0 0x000d9600 ++#define OCTEON_CN70XX_PASS1_1 0x000d9601 ++#define OCTEON_CN70XX_PASS1_2 0x000d9602 ++ ++#define OCTEON_CN70XX_PASS2_0 0x000d9608 ++ ++#define OCTEON_CN70XX (OCTEON_CN70XX_PASS1_0 | OM_IGNORE_REVISION) ++#define OCTEON_CN70XX_PASS1_X (OCTEON_CN70XX_PASS1_0 | \ ++ OM_IGNORE_MINOR_REVISION) ++#define OCTEON_CN70XX_PASS2_X (OCTEON_CN70XX_PASS2_0 | \ ++ OM_IGNORE_MINOR_REVISION) ++ ++#define OCTEON_CN71XX OCTEON_CN70XX ++ ++#define OCTEON_CN78XX_PASS1_0 0x000d9500 ++#define OCTEON_CN78XX_PASS1_1 0x000d9501 ++#define OCTEON_CN78XX_PASS2_0 0x000d9508 ++ ++#define OCTEON_CN78XX (OCTEON_CN78XX_PASS1_0 | OM_IGNORE_REVISION) ++#define OCTEON_CN78XX_PASS1_X (OCTEON_CN78XX_PASS1_0 | \ ++ OM_IGNORE_MINOR_REVISION) ++#define OCTEON_CN78XX_PASS2_X (OCTEON_CN78XX_PASS2_0 | \ ++ OM_IGNORE_MINOR_REVISION) ++ ++#define OCTEON_CN76XX (0x000d9540 | OM_CHECK_SUBMODEL) + + /* + * CNF7XXX models with new revision encoding +@@ -217,6 +258,10 @@ + #define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS |
