Re: [PATCH 4/4] ath79: add support of Mikrotik RouterBoard 91xG series
On Thu, May 6, 2021 at 7:32 PM Denis Kalashnikov wrote:
> + /*
> +* MFD: NAND plus GPIO-controller. They use/share SoC GPIO lines.
> Some of the
> +* GPIO lines are multiplexed by a 8-bit latch (LVC573).
> +* NAND is controlled by GPIO lines (bitbang), also some NAND control
> lines
> +* (nCE, ALE, CLE, READ) and data lines are multiplexed by a latch.
> So driver
> +* set control lines, enable latch ("latched them") and then transfer
> data.
> +* Several lines of the latch (not used for NAND control lines) are
> used
> +* as general-purpose GPIO. NAND ECC format is Mikrotik specific.
> +*/
> + /*
> +
> +---+
> +
> | |
> ++-+
> | |
> +| |
> | |
> +| |
> | |
> +| |
> | | 3-4 lines
> +| |
> | +
> +| G | 8 lines
> | 8-bit |GPIO
> +| P
> +---+-+ |
> (leds, SSR nCS)
> +| I | |
> | Latch |
> +| O | |
> | |
> +| s | |
> | LVC573 | 4 lines
> +| | |
> | +---+
> +| | |
> | | |
> +| | |
> | | |
> +| | |
> | | |
> +| | |
> | | |
> +| | |
> | | |
> +| | | 8
> +---+ |
> +| | |
>|
> +| | | l
>|
> +| | | i
>|
> +| SoC| | n
>|
> +| | | e
>|
> +| | | s
> +--+|
> +| | | |
> ||
> +| | | |
> C ||
> +| | | |
> | nCE, CLE, ALE, |
> +| | | |
> O ++
> +| | | | D
> | READ
> +| | | |
> N |
> +| | | | A
> |
> +| | | | N A N D
> T |
> +| | +-+ T
> |
> +| | |
> R | nRW, RDY
> +| | | A
> +--+
> +| | |
> O | |
> +| | |
> | |
> +| | |
> L | |
> +| | |
> | |
> +| G | |
> | |
> +| P |
> +--+ |
> +| I | 2 lines
> |
> +|
RE: [PATCH 4/4] ath79: add support of Mikrotik RouterBoard 91xG series
Hi,
nitpick, but if this is only for 912G, it should also say that in the commit
title.
Other comments below.
> .../dts/ar9342_mikrotik_routerboard-912g.dts | 314 ++
> target/linux/ath79/image/mikrotik.mk | 9 +
> .../base-files/etc/board.d/02_network | 2 +
> .../etc/hotplug.d/firmware/10-ath9k-eeprom| 1 +
> .../base-files/lib/upgrade/platform.sh| 1 +
> 5 files changed, 327 insertions(+)
> create mode 100644 target/linux/ath79/dts/ar9342_mikrotik_routerboard-
> 912g.dts
>
> diff --git a/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912g.dts
> b/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912g.dts
> new file mode 100644
> index 00..bc4aeeb6d0
> --- /dev/null
> +++ b/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912g.dts
> @@ -0,0 +1,314 @@
> +#include "ar9344.dtsi"
Please add an SPDX license header.
> +
> +#include
> +#include
> +
> +/*
> + * TODO list:
> + * - Enable beeper/buzzer,
> + * - Enable button/key,
> + * - Enable usb EHCI and export GPIOs for
> + * turning on/off power for USB port and mPCIe slot,
> + * - Test Wi-Fi working,
> + * - Test Gigabit Ethernet working (see pll settings),
> + */
> +
> +/ {
> + compatible = "mikrotik,routerboard-912g";
> + model = "Mikrotik RB912G";
Please be consistent and also call it "Mikrotik RouterBOARD 912G" here.
> +};
> +
> + {
> + /*
> + * MFD: NAND plus GPIO-controller. They use/share SoC GPIO lines.
> Some of the
> + * GPIO lines are multiplexed by a 8-bit latch (LVC573).
> + * NAND is controlled by GPIO lines (bitbang), also some NAND
> control lines
> + * (nCE, ALE, CLE, READ) and data lines are multiplexed by a latch. So
> driver
> + * set control lines, enable latch ("latched them") and then transfer
> data.
> + * Several lines of the latch (not used for NAND control lines) are
> used
> + * as general-purpose GPIO. NAND ECC format is Mikrotik specific.
> + */
> + /*
> +
> +---+
> +
> | |
> ++-+
> | |
> +| |
> | |
> +| |
> | |
> +| |
> | | 3-4 lines
> +| |
> | +
> +| G | 8 lines
> | 8-bit |GPIO
> +| P
> +---+-+ |
> (leds,
> SSR nCS)
> +| I | |
> | Latch |
> +| O | |
> | |
> +| s | |
> | LVC573 | 4 lines
> +| | |
> | +---+
> +| | |
> | | |
> +| | |
> | | |
> +| | |
> | | |
> +| | |
> | | |
> +| | |
> | | |
> +| | | 8
> +---+ |
> +| | |
>|
> +| | | l
>|
> +| | | i
>|
> +| SoC| | n
>|
> +| | | e
>|
> +| | | s
> +--+|
> +| | | |
> ||
> +| | | |
> C ||
> +| | | |
> | nCE, CLE, ALE, |
> +| | | |
> O ++
> +|
Re: [PATCH 4/4] ath79: add support of Mikrotik RouterBoard 91xG series
On 06.05.21 18:25, Denis Kalashnikov wrote:
What is not working:
* USB port and mPCIe slot,
* Beeper,
you will need to add kmod-gpio-beeper
+/*
+ * TODO list:
+ * - Enable beeper/buzzer,
+ * - Enable button/key,
+ * - Enable usb EHCI and export GPIOs for
+ * turning on/off power for USB port and mPCIe slot,
fyi, The GPIO nr required for the USB target (USB type A or mini pcie
slot) control is 61
+ * - Test Wi-Fi working,
+ * - Test Gigabit Ethernet working (see pll settings),
+ */
+
+/ {
+ compatible = "mikrotik,routerboard-912g";
+ model = "Mikrotik RB912G";
+};
+
+ {
+ /*
+* MFD: NAND plus GPIO-controller. They use/share SoC GPIO lines. Some
of the
+* GPIO lines are multiplexed by a 8-bit latch (LVC573).
+* NAND is controlled by GPIO lines (bitbang), also some NAND control
lines
+* (nCE, ALE, CLE, READ) and data lines are multiplexed by a latch. So
driver
+* set control lines, enable latch ("latched them") and then transfer
data.
+* Several lines of the latch (not used for NAND control lines) are used
+* as general-purpose GPIO. NAND ECC format is Mikrotik specific.
+*/
+ /*
+
+---+
+|
|
++-+ |
|
+| | |
|
+| | |
|
+| | |
| 3-4 lines
+| | |
+
+| G | 8 lines |
8-bit |GPIO
+| P +---+-+
| (leds, SSR nCS)
+| I | | |
Latch |
+| O | | |
|
+| s | | |
LVC573 | 4 lines
+| | | |
+---+
+| | | |
| |
+| | | |
| |
+| | | |
| |
+| | | |
| |
+| | | |
| |
+| | | 8
+---+ |
+| | |
|
+| | | l
|
+| | | i
|
+| SoC| | n
|
+| | | e
|
+| | | s
+--+|
+| | | |
||
+| | | | C
||
+| | | |
| nCE, CLE, ALE, |
+| | | | O
++
+| | | | D
| READ
+| | | | N
|
+| | | | A
|
+| | | | N A N D T
|
+| | +-+ T
|
+| | | R
| nRW, RDY
+| | | A
+--+
+| | | O
| |
+| | |
| |
+| | | L
| |
+| |
Re: [PATCH 4/4] ath79: add support of Mikrotik RouterBoard 91xG series
On 06.05.21 18:25, Denis Kalashnikov wrote:
What is not working:
* USB port and mPCIe slot,
* Beeper,
* Button,
+
+/* SoC Wi-Fi MAC managed by ath9k driver (RB912UAG-2HPnD) */
+ {
+ status = "okay";
+ /*
+* Wireless calibration data is in SPI NOR flash
+* hard_config partition. In OpenWrt you can also
+* read it from sysfs file
+* /sys/firmware/mikrotik/hard_config/wlan_data
+* from offset 0x1000
+* (/etc/hotplug.d/firmware/10-ath9k-eeprom script
+* does this).
+*/
+ qca,no-eeprom;
+};
Add the following here in the dts to enable USB controller (tested and
working)
{
status = "okay";
};
_phy {
status = "okay";
};
___
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[PATCH 4/4] ath79: add support of Mikrotik RouterBoard 91xG series
This board has been supported in the ar71xx.
Links:
* https://mikrotik.com/product/RB912UAG-2HPnD
* https://openwrt.org/toh/hwdata/mikrotik/mikrotik_rb912uag-2hpnd
Hardware:
* SoC: Atheros AR9342, 1 core, 600MHz, MIPS, code name "Wasp"
(like AR9341, AR9344, AR9350),
* RAM: DDR 64MB,
* Storage:
* 64KB SPI NOR: chip Winbond 25X05. With Mikrotik first-stage Bootloader
and hardware config (Ethernet MAC addr, wireless calibration data, etc).
Driver: upstream m25p80/spi-nor.
* 128MB NAND: chip Winbond W29N01GV. With Mikrotik second-stage Bootloader,
kernel, initramfs, rootfs and user data. Driver: ad-hoc rb91x-nand,
since Mikrotik guys doesn't use a SoC NAND controller on this board and
controls NAND chip through gpio lines multiplexed with data lines by a
latch,
* Ethernet: x1 10/10/1000 port with POE, MAC is embedded in SoC and is
managed by upstream ag71xx driver. PHY is on the separate chip AR8033,
connected through RGMII and MDIO and controlled by upstream at803x driver,
* Wi-Fi: 802.11bgn, MAC in SoC, driver: ath9k, wireless calibration data
is in SPI NOR flash in hard_config partition (offset 0x1000),
* PCIe: host controller embedded in SoC. Driver: ar724x. On PCIe there is
only USB 2.0 ECHI host controller, connected to USB port and mPCIe slot,
that can be used for LTE cell modem. Only one can be powerd at the same
time.
* SoC GPIO: 23 lines, driver: ath79-gpio,
* SPI bus: SPI controller is embedded in SoC. 3 nCS lines. Devices:
SPI NOR flash (nCS 0) and a Shift Register (see below, uses gpio line as
nCS). Driver: ath79-spi.
* Shift register: 8-bit, on SPI bus, chip 74HC595, driver: 74x164,
nCS is on gpio line,
* Latch: 8-bit latch, chip NXP LVC573A. Used for multiplaction of
NAND control and data lines (NAND connected to SoC GPIO lines).
Several lines of the latch, that is not used for NAND control lines,
are used for power LED and user LED and nCS of a shift register,
* Button: controlled by ???
* Beeper/buzzer: controller by SoC gpio line ???
* LEDs: 5 general purpose LEDs connected to the shift register,
power LED and user LED, connected to the latch. All them can be
controlled by software. Ethernet phy LED,
What is working:
* Gigabit Ethernet (should be tested more under load),
* SPI NOR and NAND flash (sysupgrade can be used),
* 2.4 GHz Wi-Fi ('iw dev wlan0 scan' is working),
* LEDs,
What is not working:
* USB port and mPCIe slot,
* Beeper,
* Button,
You can flash image by sysupgrade utility or load it by net
(by DHCP/TFTP, hold the button while booting).
Signed-off-by: Denis Kalashnikov
---
.../dts/ar9342_mikrotik_routerboard-912g.dts | 314 ++
target/linux/ath79/image/mikrotik.mk | 9 +
.../base-files/etc/board.d/02_network | 2 +
.../etc/hotplug.d/firmware/10-ath9k-eeprom| 1 +
.../base-files/lib/upgrade/platform.sh| 1 +
5 files changed, 327 insertions(+)
create mode 100644 target/linux/ath79/dts/ar9342_mikrotik_routerboard-912g.dts
diff --git a/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912g.dts
b/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912g.dts
new file mode 100644
index 00..bc4aeeb6d0
--- /dev/null
+++ b/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912g.dts
@@ -0,0 +1,314 @@
+#include "ar9344.dtsi"
+
+#include
+#include
+
+/*
+ * TODO list:
+ * - Enable beeper/buzzer,
+ * - Enable button/key,
+ * - Enable usb EHCI and export GPIOs for
+ * turning on/off power for USB port and mPCIe slot,
+ * - Test Wi-Fi working,
+ * - Test Gigabit Ethernet working (see pll settings),
+ */
+
+/ {
+ compatible = "mikrotik,routerboard-912g";
+ model = "Mikrotik RB912G";
+};
+
+ {
+ /*
+* MFD: NAND plus GPIO-controller. They use/share SoC GPIO lines. Some
of the
+* GPIO lines are multiplexed by a 8-bit latch (LVC573).
+* NAND is controlled by GPIO lines (bitbang), also some NAND control
lines
+* (nCE, ALE, CLE, READ) and data lines are multiplexed by a latch. So
driver
+* set control lines, enable latch ("latched them") and then transfer
data.
+* Several lines of the latch (not used for NAND control lines) are used
+* as general-purpose GPIO. NAND ECC format is Mikrotik specific.
+*/
+ /*
+
+---+
+|
|
++-+ |
|
+| | |
|
+| | |
|
+| | |
| 3-4 lines
+| |
