[Qemu-devel] [PATCH] Check fread() results to avoid gcc 4.6 warnings
When compiling with gcc 4.6, some code in fw_cfg.c complains that fop_ret
is assigned but not used (which is true). However, it looks like the
meaningless assignments to fop_ret were done to suppress other gcc warnings
due to the fact that fread() is labelled as warn_unused_result in glibc.
This patch avoids both errors, by actually checking the fread() result code
and dropping out with an error message if it fails.
Signed-off-by: David Gibson
---
hw/fw_cfg.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/hw/fw_cfg.c b/hw/fw_cfg.c
index a29db90..e4847b7 100644
--- a/hw/fw_cfg.c
+++ b/hw/fw_cfg.c
@@ -87,6 +87,13 @@ static FILE *probe_splashfile(char *filename, int
*file_sizep, int *file_typep)
/* check magic ID */
fseek(fp, 0L, SEEK_SET);
fop_ret = fread(buf, 1, 2, fp);
+if (fop_ret != 2) {
+error_report("Could not read header from '%s': %s",
+ filename, strerror(errno));
+fclose(fp);
+fp = NULL;
+return fp;
+}
filehead_value = (buf[0] + (buf[1] << 8)) & 0x;
if (filehead_value == 0xd8ff) {
file_type = JPG_FILE;
@@ -181,6 +188,12 @@ static void fw_cfg_bootsplash(FWCfgState *s)
boot_splash_filedata_size = file_size;
fseek(fp, 0L, SEEK_SET);
fop_ret = fread(boot_splash_filedata, 1, file_size, fp);
+if (fop_ret != file_size) {
+error_report("failed to read data from '%s'.",
+ boot_splash_filename);
+fclose(fp);
+return;
+}
fclose(fp);
/* insert data */
if (file_type == JPG_FILE) {
--
1.7.5.4
[Qemu-devel] [PATCH] Correctly assign PCI domain numbers
qemu already almost supports PCI domains; that is, several entirely independent PCI host bridges on the same machine. However, a bug in pci_bus_new_inplace() means that every host bridge gets assigned domain number zero and so can't be properly distinguished. This patch fixes the bug, giving each new host bridge a new domain number. Signed-off-by: David Gibson --- hw/pci.c |5 - 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/hw/pci.c b/hw/pci.c index 36db58b..2b4aecb 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -262,6 +262,8 @@ int pci_find_domain(const PCIBus *bus) return -1; } +static int pci_next_domain; /* = 0 */ + void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, const char *name, MemoryRegion *address_space, @@ -274,7 +276,8 @@ void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, /* host bridge */ QLIST_INIT(&bus->child); -pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */ + +pci_host_bus_register(pci_next_domain++, bus); vmstate_register(NULL, -1, &vmstate_pcibus, bus); } -- 1.7.5.4
Re: [Qemu-devel] [PATCH v3 0/2] The intro for QEMU disk I/O limits
On Mon, Aug 1, 2011 at 3:09 AM, Ryan Harper wrote: > * Zhi Yong Wu [2011-07-28 05:53]: >> The main goal of the patch is to effectively cap the disk I/O speed or >> counts of one single VM.It is only one draft, so it unavoidably has some >> drawbacks, if you catch them, please let me know. >> >> The patch will mainly introduce one block I/O throttling algorithm, one >> timer and one block queue for each I/O limits enabled drive. >> >> When a block request is coming in, the throttling algorithm will check if >> its I/O rate or counts exceed the limits; if yes, then it will enqueue to >> the block queue; The timer will periodically handle the I/O requests in it. >> >> Some available features follow as below: >> (1) global bps limit. >> -drive bps=xxx in bytes/s >> (2) only read bps limit >> -drive bps_rd=xxx in bytes/s >> (3) only write bps limit >> -drive bps_wr=xxx in bytes/s >> (4) global iops limit >> -drive iops=xxx in ios/s >> (5) only read iops limit >> -drive iops_rd=xxx in ios/s >> (6) only write iops limit >> -drive iops_wr=xxx in ios/s >> (7) the combination of some limits. >> -drive bps=xxx,iops=xxx >> >> Known Limitations: >> (1) #1 can not coexist with #2, #3 >> (2) #4 can not coexist with #5, #6 >> (3) When bps/iops limits are specified to a small value such as 511 bytes/s, >> this VM will hang up. We are considering how to handle this senario. >> > > I don't yet have detailed info , but we've got a memory leak in the > code. After running the VM with a 1MB r and w limit for 8 hours or > so: > > -drive bps_rd=$((1*1024*1024)),bps_wr=$((1*1024*1024)) > > I've got my system swapping with 43G resident in memory: > > 9913 root 20 0 87.3g 43g 548 D 9.6 34.5 44:00.87 qemu-system-x86 > > > would be worth looking through the code and maybe a valgrind run to > catch the leak. Sorry, it doesn't free the acb structure mallocated in block queue. For this issue, after the testing is done, the code V4 has sent out. I will apply your trace testing. thanks. Regards, Zhiyong Wu > > > -- > Ryan Harper > Software Engineer; Linux Technology Center > IBM Corp., Austin, Tx > ry...@us.ibm.com > -- Regards, Zhi Yong Wu
[Qemu-devel] [PATCH v4 3/3] The support for queue timer and throttling algorithm
Note:
1.) When bps/iops limits are specified to a small value such as 511
bytes/s, this VM will hang up. We are considering how to handle this senario.
2.) When "dd" command is issued in guest, if its option bs is set to a
large value such as "bs=1024K", the result speed will slightly bigger than the
limits.
For these problems, if you have nice thought, pls let us know.:)
Signed-off-by: Zhi Yong Wu
---
block.c | 302 +--
block.h |1 -
block_int.h | 29 ++
3 files changed, 323 insertions(+), 9 deletions(-)
diff --git a/block.c b/block.c
index 24a25d5..42763a3 100644
--- a/block.c
+++ b/block.c
@@ -29,6 +29,9 @@
#include "module.h"
#include "qemu-objects.h"
+#include "qemu-timer.h"
+#include "block/blk-queue.h"
+
#ifdef CONFIG_BSD
#include
#include
@@ -58,6 +61,13 @@ static int bdrv_read_em(BlockDriverState *bs, int64_t
sector_num,
static int bdrv_write_em(BlockDriverState *bs, int64_t sector_num,
const uint8_t *buf, int nb_sectors);
+static bool bdrv_exceed_bps_limits(BlockDriverState *bs, int nb_sectors,
+bool is_write, double elapsed_time, uint64_t *wait);
+static bool bdrv_exceed_iops_limits(BlockDriverState *bs, bool is_write,
+double elapsed_time, uint64_t *wait);
+static bool bdrv_exceed_io_limits(BlockDriverState *bs, int nb_sectors,
+bool is_write, uint64_t *wait);
+
static QTAILQ_HEAD(, BlockDriverState) bdrv_states =
QTAILQ_HEAD_INITIALIZER(bdrv_states);
@@ -90,6 +100,20 @@ int is_windows_drive(const char *filename)
}
#endif
+static int bdrv_io_limits_enable(BlockIOLimit *io_limits)
+{
+if ((io_limits->bps[0] == 0)
+ && (io_limits->bps[1] == 0)
+ && (io_limits->bps[2] == 0)
+ && (io_limits->iops[0] == 0)
+ && (io_limits->iops[1] == 0)
+ && (io_limits->iops[2] == 0)) {
+return 0;
+}
+
+return 1;
+}
+
/* check if the path starts with ":" */
static int path_has_protocol(const char *path)
{
@@ -167,6 +191,28 @@ void path_combine(char *dest, int dest_size,
}
}
+static void bdrv_block_timer(void *opaque)
+{
+BlockDriverState *bs = opaque;
+BlockQueue *queue = bs->block_queue;
+
+while (!QTAILQ_EMPTY(&queue->requests)) {
+BlockIORequest *request = NULL;
+int ret = 0;
+
+request = QTAILQ_FIRST(&queue->requests);
+QTAILQ_REMOVE(&queue->requests, request, entry);
+
+ret = qemu_block_queue_handler(request);
+if (ret == 0) {
+QTAILQ_INSERT_HEAD(&queue->requests, request, entry);
+break;
+}
+
+qemu_free(request);
+}
+}
+
void bdrv_register(BlockDriver *bdrv)
{
if (!bdrv->bdrv_aio_readv) {
@@ -642,6 +688,19 @@ int bdrv_open(BlockDriverState *bs, const char *filename,
int flags,
bs->change_cb(bs->change_opaque, CHANGE_MEDIA);
}
+/* throttling disk I/O limits */
+if (bdrv_io_limits_enable(&bs->io_limits)) {
+bs->req_from_queue = false;
+bs->block_queue= qemu_new_block_queue();
+bs->block_timer= qemu_new_timer_ns(vm_clock, bdrv_block_timer, bs);
+
+bs->slice_start[0] = qemu_get_clock_ns(vm_clock);
+bs->slice_start[1] = qemu_get_clock_ns(vm_clock);
+
+bs->slice_end[0] = qemu_get_clock_ns(vm_clock) + BLOCK_IO_SLICE_TIME;
+bs->slice_end[1] = qemu_get_clock_ns(vm_clock) + BLOCK_IO_SLICE_TIME;
+}
+
return 0;
unlink_and_fail:
@@ -680,6 +739,16 @@ void bdrv_close(BlockDriverState *bs)
if (bs->change_cb)
bs->change_cb(bs->change_opaque, CHANGE_MEDIA);
}
+
+/* throttling disk I/O limits */
+if (bs->block_queue) {
+qemu_del_block_queue(bs->block_queue);
+}
+
+if (bs->block_timer) {
+qemu_del_timer(bs->block_timer);
+qemu_free_timer(bs->block_timer);
+}
}
void bdrv_close_all(void)
@@ -1312,6 +1381,14 @@ void bdrv_get_geometry_hint(BlockDriverState *bs,
*psecs = bs->secs;
}
+/* throttling disk io limits */
+void bdrv_set_io_limits(BlockDriverState *bs,
+BlockIOLimit *io_limits)
+{
+memset(&bs->io_limits, 0, sizeof(BlockIOLimit));
+bs->io_limits = *io_limits;
+}
+
/* Recognize floppy formats */
typedef struct FDFormat {
FDriveType drive;
@@ -2111,6 +2188,165 @@ char *bdrv_snapshot_dump(char *buf, int buf_size,
QEMUSnapshotInfo *sn)
return buf;
}
+static bool bdrv_exceed_bps_limits(BlockDriverState *bs, int nb_sectors,
+ bool is_write, double elapsed_time, uint64_t *wait) {
+uint64_t bps_limit = 0;
+double bytes_limit, bytes_disp, bytes_res;
+double slice_time, wait_time;
+
+if (bs->io_limits.bps[BLOCK_IO_LIMIT_TOTAL]) {
+bps_limit = bs->io_limits.bps[BLOCK_IO_LIMIT_TOTAL];
+} else if (bs->io_limits.bps[is_write]) {
+bps_limit = bs->io_limits.bps[is_write];
+} else {
+if (wait
[Qemu-devel] [PATCH v4 2/3] The support for block queue
Signed-off-by: Zhi Yong Wu
---
block/blk-queue.c | 122 +
block/blk-queue.h | 71 +++
2 files changed, 193 insertions(+), 0 deletions(-)
create mode 100644 block/blk-queue.c
create mode 100644 block/blk-queue.h
diff --git a/block/blk-queue.c b/block/blk-queue.c
new file mode 100644
index 000..332ff13
--- /dev/null
+++ b/block/blk-queue.c
@@ -0,0 +1,122 @@
+/*
+ * QEMU System Emulator queue definition for block layer
+ *
+ * Copyright (c) 2011 Zhi Yong Wu
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "block_int.h"
+#include "qemu-queue.h"
+#include "block/blk-queue.h"
+
+/* The APIs for block request queue on qemu block layer.
+ */
+
+static void qemu_block_queue_cancel(BlockDriverAIOCB *acb)
+{
+qemu_aio_release(acb);
+}
+
+static AIOPool block_queue_pool = {
+.aiocb_size = sizeof(struct BlockDriverAIOCB),
+.cancel = qemu_block_queue_cancel,
+};
+
+static void qemu_block_queue_callback(void *opaque, int ret)
+{
+BlockDriverAIOCB *acb = opaque;
+
+qemu_aio_release(acb);
+}
+
+BlockQueue *qemu_new_block_queue(void)
+{
+BlockQueue *queue;
+
+queue = qemu_mallocz(sizeof(BlockQueue));
+
+QTAILQ_INIT(&queue->requests);
+
+return queue;
+}
+
+void qemu_del_block_queue(BlockQueue *queue)
+{
+BlockIORequest *request, *next;
+
+QTAILQ_FOREACH_SAFE(request, &queue->requests, entry, next) {
+QTAILQ_REMOVE(&queue->requests, request, entry);
+qemu_free(request);
+}
+
+qemu_free(queue);
+}
+
+BlockDriverAIOCB *qemu_block_queue_enqueue(BlockQueue *queue,
+BlockDriverState *bs,
+BlockRequestHandler *handler,
+int64_t sector_num,
+QEMUIOVector *qiov,
+int nb_sectors,
+BlockDriverCompletionFunc *cb,
+void *opaque)
+{
+BlockIORequest *request;
+BlockDriverAIOCB *acb;
+
+request = qemu_malloc(sizeof(BlockIORequest));
+request->bs = bs;
+request->handler = handler;
+request->sector_num = sector_num;
+request->qiov = qiov;
+request->nb_sectors = nb_sectors;
+request->cb = cb;
+request->opaque = opaque;
+
+QTAILQ_INSERT_TAIL(&queue->requests, request, entry);
+
+acb = qemu_aio_get(&block_queue_pool, bs,
+ qemu_block_queue_callback, opaque);
+
+request->acb = acb;
+
+return acb;
+}
+
+int qemu_block_queue_handler(BlockIORequest *request)
+{
+int ret;
+BlockDriverAIOCB *res;
+
+/* indicate this req is from block queue */
+request->bs->req_from_queue = true;
+
+res = request->handler(request->bs, request->sector_num,
+ request->qiov, request->nb_sectors,
+ request->cb, request->opaque);
+
+if (request->acb) {
+qemu_block_queue_callback(request->acb, 0);
+}
+
+ret = (res == NULL) ? 0 : 1;
+
+return ret;
+}
diff --git a/block/blk-queue.h b/block/blk-queue.h
new file mode 100644
index 000..72a5b24
--- /dev/null
+++ b/block/blk-queue.h
@@ -0,0 +1,71 @@
+/*
+ * QEMU System Emulator queue declaration for block layer
+ *
+ * Copyright (c) 2011 Zhi Yong Wu
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVID
[Qemu-devel] [PATCH v4 1/3] The cmd support for QEMU block I/O throttling
Signed-off-by: Zhi Yong Wu
---
Makefile.objs |2 +-
blockdev.c | 22 ++
qemu-config.c | 24
qemu-option.c | 17 +
qemu-option.h |1 +
qemu-options.hx |1 +
6 files changed, 66 insertions(+), 1 deletions(-)
diff --git a/Makefile.objs b/Makefile.objs
index 9f99ed4..06f2033 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -23,7 +23,7 @@ block-nested-y += raw.o cow.o qcow.o vdi.o vmdk.o cloop.o
dmg.o bochs.o vpc.o vv
block-nested-y += qcow2.o qcow2-refcount.o qcow2-cluster.o qcow2-snapshot.o
qcow2-cache.o
block-nested-y += qed.o qed-gencb.o qed-l2-cache.o qed-table.o qed-cluster.o
block-nested-y += qed-check.o
-block-nested-y += parallels.o nbd.o blkdebug.o sheepdog.o blkverify.o
+block-nested-y += parallels.o nbd.o blkdebug.o sheepdog.o blkverify.o
blk-queue.o
block-nested-$(CONFIG_WIN32) += raw-win32.o
block-nested-$(CONFIG_POSIX) += raw-posix.o
block-nested-$(CONFIG_CURL) += curl.o
diff --git a/blockdev.c b/blockdev.c
index c263663..aff6bb2 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -238,6 +238,10 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)
int on_read_error, on_write_error;
const char *devaddr;
DriveInfo *dinfo;
+BlockIOLimit io_limits;
+bool iol_flag = false;
+const char *iol_opts[7] = {"bps", "bps_rd", "bps_wr",
+"iops", "iops_rd", "iops_wr"};
int is_extboot = 0;
int snapshot = 0;
int ret;
@@ -372,6 +376,19 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)
return NULL;
}
+/* disk io limits */
+iol_flag = qemu_opt_io_limits_enable_flag(opts, iol_opts);
+if (iol_flag) {
+memset(&io_limits, 0, sizeof(BlockIOLimit));
+
+io_limits.bps[2] = qemu_opt_get_number(opts, "bps", 0);
+io_limits.bps[0] = qemu_opt_get_number(opts, "bps_rd", 0);
+io_limits.bps[1] = qemu_opt_get_number(opts, "bps_wr", 0);
+io_limits.iops[2] = qemu_opt_get_number(opts, "iops", 0);
+io_limits.iops[0] = qemu_opt_get_number(opts, "iops_rd", 0);
+io_limits.iops[1] = qemu_opt_get_number(opts, "iops_wr", 0);
+}
+
on_write_error = BLOCK_ERR_STOP_ENOSPC;
if ((buf = qemu_opt_get(opts, "werror")) != NULL) {
if (type != IF_IDE && type != IF_SCSI && type != IF_VIRTIO && type !=
IF_NONE) {
@@ -483,6 +500,11 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)
bdrv_set_on_error(dinfo->bdrv, on_read_error, on_write_error);
+/* throttling disk io limits */
+if (iol_flag) {
+bdrv_set_io_limits(dinfo->bdrv, &io_limits);
+}
+
switch(type) {
case IF_IDE:
case IF_SCSI:
diff --git a/qemu-config.c b/qemu-config.c
index efa892c..9232bbb 100644
--- a/qemu-config.c
+++ b/qemu-config.c
@@ -82,6 +82,30 @@ static QemuOptsList qemu_drive_opts = {
.name = "boot",
.type = QEMU_OPT_BOOL,
.help = "make this a boot drive",
+},{
+.name = "iops",
+.type = QEMU_OPT_NUMBER,
+.help = "limit total I/O operations per second",
+},{
+.name = "iops_rd",
+.type = QEMU_OPT_NUMBER,
+.help = "limit read operations per second",
+},{
+.name = "iops_wr",
+.type = QEMU_OPT_NUMBER,
+.help = "limit write operations per second",
+},{
+.name = "bps",
+.type = QEMU_OPT_NUMBER,
+.help = "limit total bytes per second",
+},{
+.name = "bps_rd",
+.type = QEMU_OPT_NUMBER,
+.help = "limit read bytes per second",
+},{
+.name = "bps_wr",
+.type = QEMU_OPT_NUMBER,
+.help = "limit write bytes per second",
},
{ /* end of list */ }
},
diff --git a/qemu-option.c b/qemu-option.c
index 65db542..c5aa96a 100644
--- a/qemu-option.c
+++ b/qemu-option.c
@@ -562,6 +562,23 @@ uint64_t qemu_opt_get_number(QemuOpts *opts, const char
*name, uint64_t defval)
return opt->value.uint;
}
+bool qemu_opt_io_limits_enable_flag(QemuOpts *opts, const char **iol_opts)
+{
+int i;
+uint64_t opt_val = 0;
+bool iol_flag= false;
+
+for (i = 0; iol_opts[i]; i++) {
+opt_val = qemu_opt_get_number(opts, iol_opts[i], 0);
+if (opt_val != 0) {
+iol_flag = true;
+break;
+}
+}
+
+return iol_flag;
+}
+
uint64_t qemu_opt_get_size(QemuOpts *opts, const char *name, uint64_t defval)
{
QemuOpt *opt = qemu_opt_find(opts, name);
diff --git a/qemu-option.h b/qemu-option.h
index b515813..fc909f9 100644
--- a/qemu-option.h
+++ b/qemu-option.h
@@ -107,6 +107,7 @@ struct QemuOptsList {
const char *qemu_opt_get(QemuOpts *opts, const char *name);
int qemu_opt_get_bool(QemuOpts *opts, const char *name, int defval);
uint64_t qemu_opt_get_number(QemuOpts *opts, const char *name, uint
[Qemu-devel] [PATCH v4 0/3] The intro for QEMU disk I/O limits
The main goal of the patch is to effectively cap the disk I/O speed or counts of one single VM.It is only one draft, so it unavoidably has some drawbacks, if you catch them, please let me know. The patch will mainly introduce one block I/O throttling algorithm, one timer and one block queue for each I/O limits enabled drive. When a block request is coming in, the throttling algorithm will check if its I/O rate or counts exceed the limits; if yes, then it will enqueue to the block queue; The timer will handle the I/O requests in it. Some available features follow as below: (1) global bps limit. -drive bps=xxxin bytes/s (2) only read bps limit -drive bps_rd=xxx in bytes/s (3) only write bps limit -drive bps_wr=xxx in bytes/s (4) global iops limit -drive iops=xxx in ios/s (5) only read iops limit -drive iops_rd=xxxin ios/s (6) only write iops limit -drive iops_wr=xxxin ios/s (7) the combination of some limits. -drive bps=xxx,iops=xxx Known Limitations: (1) #1 can not coexist with #2, #3 (2) #4 can not coexist with #5, #6 (3) When bps/iops limits are specified to a small value such as 511 bytes/s, this VM will hang up. We are considering how to handle this senario. Zhi Yong Wu (3): v4: fix memory leaking based on ryan's feedback. The cmd support for QEMU block I/O throttling The support for block queue The support for queue timer and throttling algorithm v3: Added the code for extending slice time, and modified the method to compute wait time for the timer. v2: The codes V2 for QEMU disk I/O limits. Modified the codes mainly based on stefan's comments. v1: Submit the codes for QEMU disk I/O limits. Only a code draft. Makefile.objs |2 +- block.c | 302 +++-- block.h |1 - block/blk-queue.c | 122 + block/blk-queue.h | 71 + block_int.h | 29 + blockdev.c| 22 qemu-config.c | 24 qemu-option.c | 17 +++ qemu-option.h |1 + qemu-options.hx |1 + 11 files changed, 582 insertions(+), 10 deletions(-) create mode 100644 block/blk-queue.c create mode 100644 block/blk-queue.h -- 1.7.2.3
Re: [Qemu-devel] [PATCH 09/39] Integrate I/O memory regions into qemu
On 08/01/2011 03:19 AM, Richard Henderson wrote: On 07/31/2011 10:57 AM, Avi Kivity wrote: > +system_io = qemu_malloc(sizeof(*system_io)); > +memory_region_init(system_memory, "io", 65536); > +set_system_io_map(system_io); Cut-paste error on that second line. Well spotted; the cpu also saw this and the fix is in patch 10, which I forgot to squash into this. I'll post a squashed version. -- I have a truly marvellous patch that fixes the bug which this signature is too narrow to contain.
[Qemu-devel] OpenBSD/macppc and sparc64 failing to boot with similar error.
I know sparc64 had little chance of actually working but I thought I'd take it for a spin with 0.15.0-rc1 and see how it fared in addition to macppc which has a good chance of working nowdays with modern QEMU. Lets see what QEMU and related bugs are left.. I noticed the bootblocks for each respective arch are failing in a very similar manner. I would guess that this is most likely a bug with the OpenBIOS Open Firmware implementation? Any assistance with this? Blue? $ qemu-system-ppc -nographic -cdrom cd50.iso -boot d >> = >> OpenBIOS 1.0 [Jun 16 2011 08:02] >> Configuration device id QEMU version 1 machine id 2 >> CPUs: 1 >> Memory: 128M >> UUID: ---- >> CPU type PowerPC,750 Welcome to OpenBIOS v1.0 built on Jun 16 2011 08:02 Trying cd:,\\:tbxi... >> OpenBSD/macppc BOOT 1.1 open(cd:/etc/boot.conf): Unknown error: code 24 boot> ? $ qemu-system-sparc64 -nographic -cdrom cd50.iso -boot d OpenBIOS for Sparc64 Configuration device id QEMU version 1 machine id 0 kernel cmdline CPUs: 1 x SUNW,UltraSPARC-IIi UUID: ---- Welcome to OpenBIOS v1.0 built on Jul 20 2011 21:17 Type 'help' for detailed information Trying cdrom:f... Not a bootable ELF image Not a bootable a.out image Loading FCode image... Loaded 4829 bytes entry point is 0x4000 OpenBSD IEEE 1275 Bootblock 1.3 .. Jumping to entry point 0010 for type 0001... switching to new context: entry point 0x10 stack 0xffe86b49 >> OpenBSD BOOT 1.4 Trying bsd... open : Unknown error: code 24 Boot: -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
Re: [Qemu-devel] [PATCH] Fix gcc-4.6 compiler error
On 07/29/2011 07:18 PM, Peter Maydell wrote: On 29 July 2011 20:30, Stefan Weil wrote: Commit 3d3b8303c6f83b9b245bc774af530a6403cc4ce6 breaks builds with gcc-4.6: hw/fw_cfg.c: In function ‘probe_splashfile’: hw/fw_cfg.c:66:9: error: variable ‘fop_ret’ set but not used [-Werror=unused-but-set-variable] hw/fw_cfg.c: In function ‘fw_cfg_bootsplash’: hw/fw_cfg.c:130:9: error: variable ‘fop_ret’ set but not used [-Werror=unused-but-set-variable] Remove fop_ret. Testing the result of fread() is normally a good idea, but I don't think it is needed here. @@ -86,7 +85,7 @@ static FILE *probe_splashfile(char *filename, int *file_sizep, int *file_typep) } /* check magic ID */ fseek(fp, 0L, SEEK_SET); -fop_ret = fread(buf, 1, 2, fp); +(void)fread(buf, 1, 2, fp); Usually this kind of thing is added in order to stop gcc complaining about you ignoring the return value of a function which has been marked (by libc) as 'don't-ignore-return-value'. In such cases a "(void)" is not sufficient to suppress the "return value ignored" warning. At least some of these cases really should be checking fread return values; I see we also don't check fseek() return values either in all places. So the easiest fix is just to check all the fread() calls. Alternative suggestion: it would be easier to just slurp the whole file into memory (which is what we do once we've figured out it's an image) and then check the magic numbers in the memory buffer, which removes a lot of these unchecked function calls altogether. Since we're linking against glib anyway it looks like g_file_get_contents() would do 95% of the work for us. [disclaimer: I haven't used that API myself but it looks the right shape...g_malloc vs qemu_malloc issues, maybe?] Failing that, fopen/fstat/fread/fclose/check magic numbers. As long as it's not mixed, it shouldn't be a problem. I think using g_file_get_contents would make sense here. Regards, Anthony Liguori -- PMM
Re: [Qemu-devel] [PATCH 00/15] sdl: Usability improvements
On 07/30/2011 04:39 AM, Jan Kiszka wrote: As SDL is my preferred way of working ad-hoc with guests, I had a closer look at oddities and shortcomings that this GUI exposed, at least here on Linux hosts. The result is a series of patches I've now finally polished and completed. Highlights: - fix termination in -no-shutdown mode - fix various issues when switching to/from full screen mode - polish mouse grabbing in full screen mode, under text console and when in absolute mouse mode - dynamically grab keyboard input in absolute mouse mode, enabling e.g. ALT+TAB in the guest - add zoom hot keys to make window scaling more attractive - refactor some ugly functions Please review/merge. Reviewed-by: Anthony Liguori For the whole series. I'll merge tomorrow after some testing. At some point, I need to rebase my gtk backend... Regards, Anthony Liguori CC: Stefano Stabellini Jan Kiszka (15): sdl: Fix termination in -no-shutdown mode sdl: Do not make full screen mode resizable sdl: Avoid redundant scaling deactivation sdl: Properly mark modifier+u as hotkey sdl: Fix full screen toggling from scaled mode sdl: Restore scaling mode on return from full screen sdl: Drop bogus gui_fullscreen_initial_grab sdl: Initialize gui_fullscreen earlier during setup sdl: Consistently avoid grabbing input for text consoles sdl: Never release input while in full screen mode sdl: Fix cursor handling when switching consoles in absolute mouse mode sdl: Dynamically grab input in absolute mouse mode sdl: Add zoom hot keys sdl: Factor out event handlers from sdl_refresh sdl: Refactor sdl_send_mouse_event qemu-doc.texi |8 + ui/sdl.c | 547 - 2 files changed, 355 insertions(+), 200 deletions(-)
Re: [Qemu-devel] [PATCH 09/39] Integrate I/O memory regions into qemu
On 07/31/2011 10:57 AM, Avi Kivity wrote: > +system_io = qemu_malloc(sizeof(*system_io)); > +memory_region_init(system_memory, "io", 65536); > +set_system_io_map(system_io); Cut-paste error on that second line. r~
Re: [Qemu-devel] [RFC PATCH 0/4] Fix subsection ambiguity in the migration format
On 07/31/2011 06:10 PM, Christoph Hellwig wrote: On Sun, Jul 31, 2011 at 11:43:08PM +0300, Dor Laor wrote: /me caught off guard. I wonder why it wasn't converted to VMSTATE before? virtio is one of the key devices, it's not just random forgotten one that might not care about migration. It just shows the extent of incomplete transitions in qemu. Given how much burden incomplete transitions have on software projects we should try to minimize them in qemu. That is if people add a new API we need to have a clear roadmap when it's going to be finished, and more importantly what the consequence of not finishing it are instead of leaving it half done. I think the way the Linux kernel handles API transitions is something qemu could borrow from. For most of them it's simply expected to do a simple conversion of all users of an API to the new equivalent, maybe it in simplistic and dumb way, but at least a transition. Combined with a deprectation schedule for unused drivers that seems to do wonders, although of course even the Linux kernel is slacking in some areas. One of the things I think the kernel is good at, is making relatively large changes outside of the tree and then merging it in a way that makes sense when it makes sense. I think we've set the bar too low historically for introducing new interfaces. I think Avi's new memory API is a good example of how we should approach these things--do the vast majority of the thankless work up front before initial merge. Besides making sure we don't have incomplete interfaces, it also helps validate the interface before committing to it. Regards, Anthony Liguori
[Qemu-devel] [0.15][PATCH] alpha-softmmu: Disable for the 0.15 release branch.
The system emulation code was not merged before the branch. Let's leave that work for the next release. Signed-off-by: Richard Henderson --- configure |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/configure b/configure index 38e3724..91b8652 100755 --- a/configure +++ b/configure @@ -840,7 +840,6 @@ if [ "$softmmu" = "yes" ] ; then default_target_list="\ i386-softmmu \ x86_64-softmmu \ -alpha-softmmu \ arm-softmmu \ cris-softmmu \ lm32-softmmu \ -- 1.7.6
Re: [Qemu-devel] [RFC PATCH 0/4] Fix subsection ambiguity in the migration format
On Sun, Jul 31, 2011 at 11:43:08PM +0300, Dor Laor wrote: > /me caught off guard. I wonder why it wasn't converted to VMSTATE before? > virtio is one of the key devices, it's not just random forgotten one that > might not care about migration. It just shows the extent of incomplete transitions in qemu. Given how much burden incomplete transitions have on software projects we should try to minimize them in qemu. That is if people add a new API we need to have a clear roadmap when it's going to be finished, and more importantly what the consequence of not finishing it are instead of leaving it half done. I think the way the Linux kernel handles API transitions is something qemu could borrow from. For most of them it's simply expected to do a simple conversion of all users of an API to the new equivalent, maybe it in simplistic and dumb way, but at least a transition. Combined with a deprectation schedule for unused drivers that seems to do wonders, although of course even the Linux kernel is slacking in some areas.
Re: [Qemu-devel] [RFC PATCH 0/4] Fix subsection ambiguity in the migration format
On 07/31/2011 04:25 PM, Dor Laor wrote:
On 08/01/2011 12:03 AM, Anthony Liguori wrote:
On 07/31/2011 03:57 PM, Dor Laor wrote:
On 07/31/2011 11:43 PM, Anthony Liguori wrote:
ps: how hard is to finish the vmstate conversion? Can't we just assume
not converted code is not functional and just remove all of it?
No. VMState is a solution looking for a problem. Many important device
The initial target solved some rare bugs, that tend not to bite us with
virtio. On the way, it got enhanced with subsections that was a major
improvement.
I should have qualified my statement. VMState did solve many real
problems. I meant that at this point in time, we've gotten pretty much
what we can get out it.
models are still not converted and ultimately, it doesn't solve the
problem we're really trying to solve.
From the start I supported Michael Tisrkin's idea for ASN.1 protocol.
The question is how visitors and ability to translate from one
representation to another will help us.
Because with Visitors you can do:
Devices -> internal QObject representation -> ASN.1 -> wire -> ASN.1 ->
internal QObject representation -> Device.
I admit that QObject sounds more appealing than VMState, we can convert
all into it. I'm not sure what's the difference between visitor and the
load/save functions, potentially with enhanced parameters like name
which can be part of QObject anyway.
VMStateInfo contains
struct VMStateInfo {
const char *name;
int (*get)(QEMUFile *f, void *pv, size_t size);
void (*put)(QEMUFile *f, void *pv, size_t size);
};
It needs to change to:
struct VMStateInfo {
const char *name;
void (*visit)(Visitor *v, const char *name, void *pv, size_t size,
Error **errp);
};
For each VMStateInfo, like vmstate_info_bool, we go from:
static int get_bool(QEMUFile *f, void *pv, size_t size)
{
bool *v = pv;
*v = qemu_get_byte(f);
return 0;
}
static void put_bool(QEMUFile *f, void *pv, size_t size)
{
bool *v = pv;
qemu_put_byte(f, *v);
}
To:
static void visit_bool(Visitor *v, const char *name, void *pv,
size_t size, Error **errp)
{
bool *v = pv;
visit_type_bool(v, name, v, errp);
}
For non-converted devices, like virtio, we change:
int virtio_load(VirtIODevice *vdev, QEMUFile *f)
{
int num, i, ret;
uint32_t features;
uint32_t supported_features =
vdev->binding->get_features(vdev->binding_opaque);
if (vdev->binding->load_config) {
ret = vdev->binding->load_config(vdev->binding_opaque, f);
if (ret)
return ret;
}
qemu_get_8s(f, &vdev->status);
qemu_get_8s(f, &vdev->isr);
...
To:
void visit_type_virtio(Visitor *v, VirtIODevice *vdev,
const char *name, Error **errp)
{
int num, i, ret;
uint32_t features;
uint32_t supported_features =
vdev->binding->get_features(vdev->binding_opaque);
if (vdev->binding->load_config) {
ret = vdev->binding->load_config(vdev->binding_opaque, f);
if (ret)
return ret;
}
visit_start_struct(v, "VirtIODevice", name, errp);
visit_type_u8(v, "status", &vdev->status);
visit_type_u8(v, "isr", &vdev->isr);
...
You'll notice it's almost entirely mechanical. It can probably be done
with a few seds and an afternoons worth of grunt work.
I'm resisting the urge to do this myself because it's a good intro task
and we've got a number of folks looking for those.
While it's in an internal representation, we can make large changes like
translating entire device state structures to new formats, splitting one
device into two, etc.
It's sort of the ultimate mechanism to make compatibility changes. If
you just go Devices -> ASN.1, you miss out on that.
What's important in ASN.1 is not the data representation itself but the
ability to have a flexible protocol. We can have it with VMState and
QObject as well. I do admit that QObject+ASN.1 will ease the way to make
it right so you convinced me :).
I still don't see have using ASN.1 will easily join/split several
devices into few and some other magics. Not that it is not possible but
it is way too hard.
ASN.1 doesn't do it but having an object representation that we can
manipulate will. Think of it like a compiler optimization phase, you
write a visitor that can identify a node, and transform it into a
different set of nodes.
The main 'real' problems you're trying to solve are migration from one
release to the other while most of our problems were forgotten fields
here and there (floppy/ide/rtl/kvmclock/etc). I doubt that live
migration of the same release worked on upstream for the random git
head. Verifying save(i)== load(i)+save(i+1) is simple but no one
executing it.
Because it's not easily automated. I know it's preaching to the choir,
but we need better unit tests. We're getting there though, we know have
a handful of tests in the tree with hopefully more growing now
[Qemu-devel] [PATCH] introduce environment variables for all qemu-user options
Rework option parsing code for linux-user in a table-driven manner to allow
environment variables for all commandline options.
Also generate usage() output from option table.
Signed-off-by: Johannes Schauer
---
linux-user/main.c | 518 ++---
1 files changed, 331 insertions(+), 187 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index dbba8be..95e8651 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -40,6 +40,10 @@
char *exec_path;
int singlestep;
+const char *filename;
+const char *argv0 = NULL;
+int gdbstub_port = 0;
+const char *cpu_model;
unsigned long mmap_min_addr;
#if defined(CONFIG_USE_GUEST_BASE)
unsigned long guest_base;
@@ -47,6 +51,8 @@ int have_guest_base;
unsigned long reserved_va;
#endif
+static void usage(void);
+
static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
@@ -2624,50 +2630,6 @@ void cpu_loop (CPUState *env)
}
#endif /* TARGET_ALPHA */
-static void usage(void)
-{
-printf("qemu-" TARGET_ARCH " version " QEMU_VERSION QEMU_PKGVERSION ",
Copyright (c) 2003-2008 Fabrice Bellard\n"
- "usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n"
- "Linux CPU emulator (compiled for %s emulation)\n"
- "\n"
- "Standard options:\n"
- "-hprint this help\n"
- "-g port wait gdb connection to port\n"
- "-L path set the elf interpreter prefix (default=%s)\n"
- "-s size set the stack size in bytes (default=%ld)\n"
- "-cpu modelselect CPU (-cpu ? for list)\n"
- "-drop-ld-preload drop LD_PRELOAD for target process\n"
- "-E var=value sets/modifies targets environment variable(s)\n"
- "-U varunsets targets environment variable(s)\n"
- "-0 argv0 forces target process argv[0] to be argv0\n"
-#if defined(CONFIG_USE_GUEST_BASE)
- "-B addressset guest_base address to address\n"
- "-R size reserve size bytes for guest virtual address
space\n"
-#endif
- "\n"
- "Debug options:\n"
- "-d options activate log (logfile=%s)\n"
- "-p pagesize set the host page size to 'pagesize'\n"
- "-singlestep always run in singlestep mode\n"
- "-strace log system calls\n"
- "\n"
- "Environment variables:\n"
- "QEMU_STRACE Print system calls and arguments similar to
the\n"
- " 'strace' program. Enable by setting to any
value.\n"
- "You can use -E and -U options to set/unset environment variables\n"
- "for target process. It is possible to provide several variables\n"
- "by repeating the option. For example:\n"
- "-E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
- "Note that if you provide several changes to single variable\n"
- "last change will stay in effect.\n"
- ,
- TARGET_ARCH,
- interp_prefix,
- guest_stack_size,
- DEBUG_LOGFILE);
-exit(1);
-}
-
THREAD CPUState *thread_env;
void task_settid(TaskState *ts)
@@ -2703,24 +2665,342 @@ void init_task_state(TaskState *ts)
}
ts->sigqueue_table[i].next = NULL;
}
-
+
+static void handle_arg_help(const char *arg, envlist_t *envlist)
+{
+usage();
+}
+
+static void handle_arg_log(const char *arg, envlist_t *envlist)
+{
+int mask;
+const CPULogItem *item;
+
+mask = cpu_str_to_log_mask(arg);
+if (!mask) {
+printf("Log items (comma separated):\n");
+for(item = cpu_log_items; item->mask != 0; item++) {
+printf("%-10s %s\n", item->name, item->help);
+}
+exit(1);
+}
+cpu_set_log(mask);
+}
+
+static void handle_arg_set_env(const char *arg, envlist_t *envlist)
+{
+char *r, *p, *token;
+r = p = strdup(arg);
+while ((token = strsep(&p, ",")) != NULL) {
+if (envlist_setenv(envlist, token) != 0)
+usage();
+}
+free(r);
+}
+
+static void handle_arg_unset_env(const char *arg, envlist_t *envlist)
+{
+char *r, *p, *token;
+r = p = strdup(arg);
+while ((token = strsep(&p, ",")) != NULL) {
+if (envlist_unsetenv(envlist, token) != 0)
+usage();
+}
+free(r);
+}
+
+static void handle_arg_argv0(const char *arg, envlist_t *envlist)
+{
+argv0 = strdup(arg);
+}
+
+static void handle_arg_stack_size(const char *arg, envlist_t *envlist)
+{
+char *p;
+guest_stack_size = strtoul(arg, &p, 0);
+if (guest_stack_size == 0)
+usage();
+if (*p == 'M')
+guest_stack_size *= 1024 * 1024;
+else if (*p == 'k' || *p == 'K')
+guest_stack_size *= 1024;
+}
+
+static void handle_arg_ld_prefix(const char *arg, envlist_t *envlist)
+{
+interp_prefix =
Re: [Qemu-devel] [Bug 818647] [NEW] Getting segmentation fault when trying to boot FreeBSD
On Sat, Jul 30, 2011 at 9:13 PM, Wojciech Koszek <818...@bugs.launchpad.net> wrote: > Public bug reported: > > wkoszek@wkoszek:~/bin/qemu/qemu$ git log | head -1 > commit c886edfb851c0c590d4e77f058f2ec8ed95ad1b5 > > wkoszek@wkoszek:~/o/freebsd/sys/boot/i386$ qemu-system-sparc64 --version > QEMU emulator version 0.15.50, Copyright (c) 2003-2008 Fabrice Bellard > > wkoszek@wkoszek:~/o/freebsd/sys/boot/i386$ uname -a > Linux wkoszek 2.6.38-10-generic #46-Ubuntu SMP Tue Jun 28 15:05:41 UTC 2011 > i686 i686 i386 GNU/Linux > > Qemu built with default settings (./configure --prefix= && make && > make install) > > I run FreeBSD ISO image: > /home/wkoszek/bin/qemu-dynamic/bin/qemu-system-sparc64 -m 1024 -cdrom > ~/Pulpit/iso/FreeBSD-7.4-RELEASE-sparc64-bootonly.iso -hda > ~/Pulpit/iso/freebsd_sparc64.qcow2 -nographic -boot d > > Configuration device id QEMU version 1 machine id 0 > kernel cmdline > CPUs: 1 x SUNW,UltraSPARC-IIi > UUID: ---- > Welcome to OpenBIOS v1.0 built on Jul 20 2011 21:17 > Type 'help' for detailed information > Trying cdrom:f... > Not a bootable ELF image > Loading a.out image... > Loaded 7680 bytes > entry point is 0x4000 > > Jumping to entry point 4000 for type 0005... > switching to new context: entry point 0x4000 stack 0xffe86b49 > >>> FreeBSD/sparc64 boot block > Boot path: cdrom:f > Boot loader: /boot/loader > Consoles: Open Firmware console > > Booting with sun4u support. > Boot path set to cdrom:a > > FreeBSD/sparc64 bootstrap loader, Revision 1.0 > (r...@warner.cse.buffalo.edu, Fri Feb 18 05:38:31 UTC 2011) > bootpath="cdrom:a" > Loading /boot/defaults/loader.conf > /boot/kernel/kernel data=0x8d1f48+0x82f88 syms=[0x8+0x88ec0+0x8+0x76966] > | > Unimplemented service milliseconds ([0] -- [1]) > Hit [Enter] to boot immediately, or any other key for command prompt. > Unimplemented service milliseconds ([0] -- [1]) > Unimplemented service milliseconds ([0] -- [1]) > Unimplemented service milliseconds ([0] -- [1]) > Unimplemented service milliseconds ([0] -- [1]) > Unimplemented service milliseconds ([0] -- [1]) > Unimplemented service milliseconds ([0] -- [1]) > > I press CTRL + C and I get out of the looped warning about > "unimplemented service". Then I see: > > Type '?' for a list of commands, 'help' for more detailed help. > OK boot > jumping to kernel entry at 0xc0078000. > BOOTUnhandled Exception 0x0034 > PC = 0xc0637454 NPC = 0xc0637458 > > I wanted to start FreeBSD debugging here - I pressed 'CTRL+A c', I was > dropped to the monitor. > > FRom the monitor I typed: > > Stopping execution > QEMU 0.15.50 monitor - type 'help' for more information > (qemu) x 0xc0078000 > c0078000: Cannot access memory > (qemu) x 0xc0637454 > c0637454: Cannot access memory > (qemu) x 0xc0637458 > c0637458: Cannot access memory > (qemu) xp 0xc0078000 > Segmentation fault > > IMO it shouldn't have crashed. Right. FYI: the virtual to physical translations can be examined (before the exception printout) with 'info tlb': jumping to kernel entry at 0xc0078000. QEMU 0.15.50 monitor - type 'help' for more information (qemu) info tlb MMU contexts: Primary: 0, Secondary: 0 DMMU dump [00] VA: ffe0, PA: 7e8, 512k, priv, RW, locked, ctx 0 local [01] VA: ffe8, PA: 7f0, 512k, priv, RW, locked, ctx 0 local [02] VA: fff0, PA: 7f8, 512k, priv, RW, locked, ctx 0 local [03] VA: ffd0, PA: 1fff000, 512k, priv, RO, locked, ctx 0 local [04] VA: ffd8, PA: 1fff008, 512k, priv, RO, locked, ctx 0 local [05] VA: c864e000, PA: 580c000, 8k, priv, RW, unlocked, ctx 0 local [06] VA: fe00, PA: 1ff0080, 4M, priv, RW, locked, ctx 0 local [07] VA: fe40, PA: 1ff00c0, 4M, priv, RW, locked, ctx 0 local [08] VA: bfc0, PA: 0, 4M, priv, RW, locked, ctx 0 local [09] VA: c8658000, PA: 5814000, 8k, priv, RW, unlocked, ctx 0 local [10] VA: c408, PA: 548, 8k, priv, RW, unlocked, ctx 0 local [11] VA: c4082000, PA: 5482000, 8k, priv, RW, unlocked, ctx 0 local [12] VA: c4084000, PA: 5484000, 8k, priv, RW, unlocked, ctx 0 local [13] VA: c4086000, PA: 5486000, 8k, priv, RW, unlocked, ctx 0 local [14] VA: c4088000, PA: 5488000, 8k, priv, RW, unlocked, ctx 0 local [15] VA: f80005a52000, PA: 580, 4M, user, RW, unlocked, ctx 0 local [16] VA: c3fc8000, PA: 53c8000, 8k, priv, RW, unlocked, ctx 0 local [17] VA: c3fca000, PA: 53ca000, 8k, priv, RW, unlocked, ctx 0 local [18] VA: c3fcc000, PA: 53cc000, 8k, priv, RW, unlocked, ctx 0 local [19] VA: c3fce000, PA: 53ce000, 8k, priv, RW, unlocked, ctx 0 local [20] VA: c3fd, PA: 53d, 8k, priv, RW, unlocked, ctx 0 local [21] VA: c3fd2000, PA: 53d2000, 8k, priv, RW, unlocked, ctx 0 local [22] VA: c3fd4000, PA: 53d4000, 8k, priv, RW, unlocked, ctx 0 local [23] VA: c3fd6000, PA: 53d6000, 8k, priv, RW, unlocked, ctx 0 local [24] VA: c3fd8000, PA: 53d8000, 8k, p
Re: [Qemu-devel] [RFC PATCH 0/4] Fix subsection ambiguity in the migration format
On 08/01/2011 12:03 AM, Anthony Liguori wrote: On 07/31/2011 03:57 PM, Dor Laor wrote: On 07/31/2011 11:43 PM, Anthony Liguori wrote: ps: how hard is to finish the vmstate conversion? Can't we just assume not converted code is not functional and just remove all of it? No. VMState is a solution looking for a problem. Many important device The initial target solved some rare bugs, that tend not to bite us with virtio. On the way, it got enhanced with subsections that was a major improvement. I should have qualified my statement. VMState did solve many real problems. I meant that at this point in time, we've gotten pretty much what we can get out it. models are still not converted and ultimately, it doesn't solve the problem we're really trying to solve. From the start I supported Michael Tisrkin's idea for ASN.1 protocol. The question is how visitors and ability to translate from one representation to another will help us. Because with Visitors you can do: Devices -> internal QObject representation -> ASN.1 -> wire -> ASN.1 -> internal QObject representation -> Device. I admit that QObject sounds more appealing than VMState, we can convert all into it. I'm not sure what's the difference between visitor and the load/save functions, potentially with enhanced parameters like name which can be part of QObject anyway. While it's in an internal representation, we can make large changes like translating entire device state structures to new formats, splitting one device into two, etc. It's sort of the ultimate mechanism to make compatibility changes. If you just go Devices -> ASN.1, you miss out on that. What's important in ASN.1 is not the data representation itself but the ability to have a flexible protocol. We can have it with VMState and QObject as well. I do admit that QObject+ASN.1 will ease the way to make it right so you convinced me :). I still don't see have using ASN.1 will easily join/split several devices into few and some other magics. Not that it is not possible but it is way too hard. The main 'real' problems you're trying to solve are migration from one release to the other while most of our problems were forgotten fields here and there (floppy/ide/rtl/kvmclock/etc). I doubt that live migration of the same release worked on upstream for the random git head. Verifying save(i)== load(i)+save(i+1) is simple but no one executing it. Looks like we might be ready to go with your suggestion, I'm just worried that there are too many other non migration open issues. If the above work won't get complete we're better off with the current machine type + VMState + subsections. If it will be all completed, we're better with your suggestion. BTW, another really useful thing that Visitor would enable is the ability to read an individual device to a QObject and implement the equivalent of 'show devicename' which dumps the state of arbitrary devices via QMP. This could be very useful for debugging. I do see value in it but I don't think it is that important. If we have one real device serialization method that is flexible enough we can stick with it w/o translation. If we define qdev serialization into vmstate/asn.1/json/other and add some capability negotiation and various other goodies it should be enough. btw: separating the live migration protocol from the machine state is even more important if we take a gradual approach. Yeah, I think the critical technical requirement to achieve this is that the devices need to generate their own serialization format, and then another layer translates that to the "live migration protocol" format. Regards, Anthony Liguori Regards, Anthony Liguori Regards, Anthony Liguori
Re: [Qemu-devel] [Bug 818645] [NEW] Unhandled OF service in FreeBSD loader - "unimplemented service milliseconds"
On Sat, Jul 30, 2011 at 9:03 PM, Wojciech Koszek <818...@bugs.launchpad.net> wrote: > Public bug reported: > > wkoszek@wkoszek:~/bin/qemu/qemu$ git log | head -1 > commit c886edfb851c0c590d4e77f058f2ec8ed95ad1b5 > > built with default settings. > > Run like that: > /home/wkoszek/bin/qemu-dynamic/bin/qemu-system-sparc64 -m 1024 -cdrom > ~/Pulpit/iso/FreeBSD-7.4-RELEASE-sparc64-bootonly.iso -hda > ~/Pulpit/iso/freebsd_sparc64.qcow2 -nographic -boot d > > Configuration device id QEMU version 1 machine id 0 > kernel cmdline > CPUs: 1 x SUNW,UltraSPARC-IIi > UUID: ---- > Welcome to OpenBIOS v1.0 built on Jul 20 2011 21:17 > Type 'help' for detailed information > Trying cdrom:f... > Not a bootable ELF image > Loading a.out image... > Loaded 7680 bytes > entry point is 0x4000 > > Jumping to entry point 4000 for type 0005... > switching to new context: entry point 0x4000 stack 0xffe86b49 > >>> FreeBSD/sparc64 boot block > Boot path: cdrom:f > Boot loader: /boot/loader > Consoles: Open Firmware console > > Booting with sun4u support. > Boot path set to cdrom:a > > FreeBSD/sparc64 bootstrap loader, Revision 1.0 > (r...@warner.cse.buffalo.edu, Fri Feb 18 05:38:31 UTC 2011) > bootpath="cdrom:a" > Loading /boot/defaults/loader.conf > /boot/kernel/kernel data=0x8d1f48+0x82f88 syms=[0x8+0x88ec0+0x8+0x76966] > | > Unimplemented service milliseconds ([0] -- [1]) > Hit [Enter] to boot immediately, or any other key for command prompt. > Unimplemented service milliseconds ([0] -- [1]) > Unimplemented service milliseconds ([0] -- [1]) > Unimplemented service milliseconds ([0] -- [1]) > Unimplemented service milliseconds ([0] -- [1]) > Unimplemented service milliseconds ([0] -- [1]) > > This basically loops here unless I press CTRL+C. > > Was there any OpenBIOS release that didn't have this problem? "milliseconds" has not implemented for Sparc, but there is a similar service for PPC machines which could be used as a starting point. > > ** Affects: qemu > Importance: Undecided > Status: New > > > ** Tags: freebsd > > -- > You received this bug notification because you are a member of qemu- > devel-ml, which is subscribed to QEMU. > https://bugs.launchpad.net/bugs/818645 > > Title: > Unhandled OF service in FreeBSD loader - "unimplemented service > milliseconds" > > Status in QEMU: > New > > Bug description: > wkoszek@wkoszek:~/bin/qemu/qemu$ git log | head -1 > commit c886edfb851c0c590d4e77f058f2ec8ed95ad1b5 > > built with default settings. > > Run like that: > /home/wkoszek/bin/qemu-dynamic/bin/qemu-system-sparc64 -m 1024 -cdrom > ~/Pulpit/iso/FreeBSD-7.4-RELEASE-sparc64-bootonly.iso -hda > ~/Pulpit/iso/freebsd_sparc64.qcow2 -nographic -boot d > > Configuration device id QEMU version 1 machine id 0 > kernel cmdline > CPUs: 1 x SUNW,UltraSPARC-IIi > UUID: ---- > Welcome to OpenBIOS v1.0 built on Jul 20 2011 21:17 > Type 'help' for detailed information > Trying cdrom:f... > Not a bootable ELF image > Loading a.out image... > Loaded 7680 bytes > entry point is 0x4000 > > Jumping to entry point 4000 for type 0005... > switching to new context: entry point 0x4000 stack 0xffe86b49 > > >> FreeBSD/sparc64 boot block > Boot path: cdrom:f > Boot loader: /boot/loader > Consoles: Open Firmware console > > Booting with sun4u support. > Boot path set to cdrom:a > > FreeBSD/sparc64 bootstrap loader, Revision 1.0 > (r...@warner.cse.buffalo.edu, Fri Feb 18 05:38:31 UTC 2011) > bootpath="cdrom:a" > Loading /boot/defaults/loader.conf > /boot/kernel/kernel data=0x8d1f48+0x82f88 syms=[0x8+0x88ec0+0x8+0x76966] > | > Unimplemented service milliseconds ([0] -- [1]) > Hit [Enter] to boot immediately, or any other key for command prompt. > Unimplemented service milliseconds ([0] -- [1]) > Unimplemented service milliseconds ([0] -- [1]) > Unimplemented service milliseconds ([0] -- [1]) > Unimplemented service milliseconds ([0] -- [1]) > Unimplemented service milliseconds ([0] -- [1]) > > This basically loops here unless I press CTRL+C. > > Was there any OpenBIOS release that didn't have this problem? > > To manage notifications about this bug go to: > https://bugs.launchpad.net/qemu/+bug/818645/+subscriptions > >
Re: [Qemu-devel] [PATCH 00/39] Memory API, batch 2: PCI devices
On 07/31/2011 01:02 PM, Avi Kivity wrote: 79 files changed, 1654 insertions(+), 2082 deletions(-) Unexpected side effect... But always welcome :-) Regards, Anthony Liguori
Re: [Qemu-devel] [RFC PATCH 0/4] Fix subsection ambiguity in the migration format
On 07/31/2011 03:57 PM, Dor Laor wrote: On 07/31/2011 11:43 PM, Anthony Liguori wrote: ps: how hard is to finish the vmstate conversion? Can't we just assume not converted code is not functional and just remove all of it? No. VMState is a solution looking for a problem. Many important device The initial target solved some rare bugs, that tend not to bite us with virtio. On the way, it got enhanced with subsections that was a major improvement. I should have qualified my statement. VMState did solve many real problems. I meant that at this point in time, we've gotten pretty much what we can get out it. models are still not converted and ultimately, it doesn't solve the problem we're really trying to solve. From the start I supported Michael Tisrkin's idea for ASN.1 protocol. The question is how visitors and ability to translate from one representation to another will help us. Because with Visitors you can do: Devices -> internal QObject representation -> ASN.1 -> wire -> ASN.1 -> internal QObject representation -> Device. While it's in an internal representation, we can make large changes like translating entire device state structures to new formats, splitting one device into two, etc. It's sort of the ultimate mechanism to make compatibility changes. If you just go Devices -> ASN.1, you miss out on that. BTW, another really useful thing that Visitor would enable is the ability to read an individual device to a QObject and implement the equivalent of 'show devicename' which dumps the state of arbitrary devices via QMP. This could be very useful for debugging. I do see value in it but I don't think it is that important. If we have one real device serialization method that is flexible enough we can stick with it w/o translation. If we define qdev serialization into vmstate/asn.1/json/other and add some capability negotiation and various other goodies it should be enough. btw: separating the live migration protocol from the machine state is even more important if we take a gradual approach. Yeah, I think the critical technical requirement to achieve this is that the devices need to generate their own serialization format, and then another layer translates that to the "live migration protocol" format. Regards, Anthony Liguori Regards, Anthony Liguori Regards, Anthony Liguori
Re: [Qemu-devel] [ANNOUNCE] QEMU 0.15.0-rc1 Release
On 07/31/2011 11:31 AM, Avi Kivity wrote: On 07/30/2011 03:39 AM, Anthony Liguori wrote: Hi, On behalf of the entire QEMU team, I'm please to announce the release of QEMU 0.15.0-rc1. This is the second release candidate for the 0.15.0 release. make -jlarge fails with: cc1: warning: qapi-generated: No such file or directory [enabled by default] In file included from ./bswap.h:4:0, from ./qemu-common.h:98, from ./qlist.h:18, from ./qdict.h:17, from ./qapi/qmp-core.h:18, from ./qga/guest-agent-core.h:13, from qga/guest-agent-command-state.c:13: ./config-host.h:52:0: warning: "CONFIG_IOVEC" redefined [enabled by default] ./qemu-common.h:65:0: note: this is the location of the previous definition In file included from ./qlist.h:18:0, from ./qdict.h:17, from ./qapi/qmp-core.h:18, from ./qga/guest-agent-core.h:13, from qga/guest-agent-command-state.c:13: ./qemu-common.h:66:8: error: redefinition of ‘struct iovec’ /usr/include/bits/uio.h:44:8: note: originally defined here make: *** [qga/guest-agent-command-state.o] Error 1 make: *** Waiting for unfinished jobs A subsequent make makes it through, so it appears to be a missing dependency. We're missing: 88ca9f047bf8df20ae0a6305d99cbad1e893777f Author: Michael Roth Date: Tue Jul 26 11:39:24 2011 -0500 Makefile: add missing deps on $(GENERATED_HEADERS) This fixes a build issue with make -j6+ due to qapi-generated files being built before $(GENERATED_HEADERS) have been created. In stable. I'll cherry pick and make sure it's in -rc2. Regards, Anthony Liguori
Re: [Qemu-devel] [RFC PATCH 0/4] Fix subsection ambiguity in the migration format
On 07/31/2011 11:43 PM, Anthony Liguori wrote: On 07/31/2011 05:48 AM, Dor Laor wrote: On 07/30/2011 01:28 AM, Anthony Liguori wrote: No, not at all. Just that converting everything to VMState isn't a prerequisite for building a more robust migration protocol. The main thing is to priorities the problems we're facing with. - Live migration protocol: - VMState conversion is not complete But this is not a problem because it doesn't gate anything. That's my point. The VMState might be an exception but in general we have too many unfinished businesses going on. - Live migration is not flexible enough (even with subsections) To make it more flexible, we need to be able to marshal to an internal data structure that we can transform in more flexible ways. - Simplify destination cmdline for machine creation This needs qdev fixing. - Qdev - conversion is not complete - Machine + devices description are complex and have hidden glue This is a hard problem. - Qapi - Needs merging We merged the first part (which includes the new QMP server). The work is done for converting the actual QMP commands. - QOB - Only the beginning So overall there are many parallel projects, probably more than the above. The RightThink(tm) would be to pick the ones that we can converge on and not try to handle all in parallel. There are problems we can live with. Engineering wise it might not be a beauty but they can wait (for instance dark magic to create the machines). There are some that prevent adding new features or make the code hard to support w/o them. Cheers, Dor ps: how hard is to finish the vmstate conversion? Can't we just assume not converted code is not functional and just remove all of it? No. VMState is a solution looking for a problem. Many important device The initial target solved some rare bugs, that tend not to bite us with virtio. On the way, it got enhanced with subsections that was a major improvement. models are still not converted and ultimately, it doesn't solve the problem we're really trying to solve. From the start I supported Michael Tisrkin's idea for ASN.1 protocol. The question is how visitors and ability to translate from one representation to another will help us. I do see value in it but I don't think it is that important. If we have one real device serialization method that is flexible enough we can stick with it w/o translation. If we define qdev serialization into vmstate/asn.1/json/other and add some capability negotiation and various other goodies it should be enough. btw: separating the live migration protocol from the machine state is even more important if we take a gradual approach. Regards, Anthony Liguori Regards, Anthony Liguori
Re: [Qemu-devel] [RFC PATCH 0/4] Fix subsection ambiguity in the migration format
On 07/31/2011 03:43 PM, Dor Laor wrote: On 07/31/2011 09:46 PM, Christoph Hellwig wrote: On Sun, Jul 31, 2011 at 02:45:07PM +0300, Dor Laor wrote: No, definitely not. I think most people using non-x86 architectures don't use the vmsave/vmload/migration features at all, but would be annoyed if the perfectly functional device models they were using got deleted... I didn't mean to erase the entire device, just the code for save/load which as you say, might not be used at all. Like the one in virtio? /me caught off guard. I wonder why it wasn't converted to VMSTATE before? virtio is one of the key devices, it's not just random forgotten one that might not care about migration. It's worth to utilize this discussion to realize whether vmstate is significant enough. VMState does two things. It provides a common code path for save/load. This is wonderful and it absolutely has prevent numerous bugs from happening. Undeniably, it's made migration better and more robust because of that. It also provides a declarative description of the serialization state. The declarative language has gotten complex and it's still not quite covering everything we do (there's a lot of one-off marshalling handlers to handle corner cases). I think we've basically gotten as much as we can with the declarative approach. I think we have to take the next logical step which is to use the declarative descriptions (or imperative marshallers) to generate a richer internal representation that we can manipulate in a high level fashion. We could keep trying to make everything declarative but that in and of itself does not get us to the next step with improving migration. And it shouldn't gate us either. From my brief browsing it looks like vmstate helps to reduce some plain errors with double save/load coding, ease the field encoding and handles subsections (which imho is the most important). I think we need to really step back and look at the larger picture. What do we really need to "fix" migration? I've given this a ton of thought, and I think there's really two classes of problems: 1) Creating the same guest visible device model in two, potentially different, versions of QEMU. 2) Given an identical guest visible device model, coping with variations in the internal implementation and state serialization. Subsections and versions are solutions to (2), but limited to the scope of an individual device (and really, individual fields). We completely punt (1) to management tools. You need a comprehensive object model to solve (1). I'm convinced of that. To solve (2), we need to be able to separate compatibility from internal implementation. To me, this means migrating to an internal data structure and then manipulating that data structure before/after transferring it over the wire. It's true that we need to introduce capabilities to the live migration protocol and some other goodies but we might be able to do that with the existing method of gradual enhancement for VMSTATE to whatever form it may be. I've already written this up: http://wiki.qemu.org/Features/Migration/Next Regards, Anthony Liguori
Re: [Qemu-devel] [RFC PATCH 0/4] Fix subsection ambiguity in the migration format
On 07/31/2011 05:48 AM, Dor Laor wrote: On 07/30/2011 01:28 AM, Anthony Liguori wrote: No, not at all. Just that converting everything to VMState isn't a prerequisite for building a more robust migration protocol. The main thing is to priorities the problems we're facing with. - Live migration protocol: - VMState conversion is not complete But this is not a problem because it doesn't gate anything. That's my point. - Live migration is not flexible enough (even with subsections) To make it more flexible, we need to be able to marshal to an internal data structure that we can transform in more flexible ways. - Simplify destination cmdline for machine creation This needs qdev fixing. - Qdev - conversion is not complete - Machine + devices description are complex and have hidden glue This is a hard problem. - Qapi - Needs merging We merged the first part (which includes the new QMP server). The work is done for converting the actual QMP commands. - QOB - Only the beginning So overall there are many parallel projects, probably more than the above. The RightThink(tm) would be to pick the ones that we can converge on and not try to handle all in parallel. There are problems we can live with. Engineering wise it might not be a beauty but they can wait (for instance dark magic to create the machines). There are some that prevent adding new features or make the code hard to support w/o them. Cheers, Dor ps: how hard is to finish the vmstate conversion? Can't we just assume not converted code is not functional and just remove all of it? No. VMState is a solution looking for a problem. Many important device models are still not converted and ultimately, it doesn't solve the problem we're really trying to solve. Regards, Anthony Liguori Regards, Anthony Liguori
Re: [Qemu-devel] [RFC PATCH 0/4] Fix subsection ambiguity in the migration format
On 07/31/2011 09:46 PM, Christoph Hellwig wrote: On Sun, Jul 31, 2011 at 02:45:07PM +0300, Dor Laor wrote: No, definitely not. I think most people using non-x86 architectures don't use the vmsave/vmload/migration features at all, but would be annoyed if the perfectly functional device models they were using got deleted... I didn't mean to erase the entire device, just the code for save/load which as you say, might not be used at all. Like the one in virtio? /me caught off guard. I wonder why it wasn't converted to VMSTATE before? virtio is one of the key devices, it's not just random forgotten one that might not care about migration. It's worth to utilize this discussion to realize whether vmstate is significant enough. From my brief browsing it looks like vmstate helps to reduce some plain errors with double save/load coding, ease the field encoding and handles subsections (which imho is the most important). It's true that we need to introduce capabilities to the live migration protocol and some other goodies but we might be able to do that with the existing method of gradual enhancement for VMSTATE to whatever form it may be.
Re: [Qemu-devel] [ANNOUNCE] QEMU 0.15.0-rc1 Release
On 07/31/2011 03:06 AM, Avi Kivity wrote: On 07/30/2011 03:39 AM, Anthony Liguori wrote: Hi, On behalf of the entire QEMU team, I'm please to announce the release of QEMU 0.15.0-rc1. This is the second release candidate for the 0.15.0 release. Unfortunately, it identifies itself as 1.0 development: $ git show v0.15.0-rc1:VERSION | cat 0.15.51 Hrm, somehow an extra commit made it to the stable branch. I assumed it came through a merge and confused myself with the numbering. Justin, I pushed a commit to set the version to 0.14.92, please sync up with the stable branch of qemu.git. Thanks for catching this! Regards, Anthony Liguori
[Qemu-devel] [PATCH 13/39] rtl8139: convert to memory API
Signed-off-by: Avi Kivity
---
hw/rtl8139.c | 72 ++---
1 files changed, 38 insertions(+), 34 deletions(-)
diff --git a/hw/rtl8139.c b/hw/rtl8139.c
index 5214b8c..dfbab90 100644
--- a/hw/rtl8139.c
+++ b/hw/rtl8139.c
@@ -474,7 +474,6 @@ typedef struct RTL8139State {
NICState *nic;
NICConf conf;
-int rtl8139_mmio_io_addr;
/* C ring mode */
uint32_t currTxDesc;
@@ -506,6 +505,9 @@ typedef struct RTL8139State {
QEMUTimer *timer;
int64_t TimerExpire;
+MemoryRegion bar_io;
+MemoryRegion bar_mem;
+
/* Support migration to/from old versions */
int rtl8139_mmio_io_addr_dummy;
} RTL8139State;
@@ -3283,7 +3285,7 @@ static void rtl8139_pre_save(void *opaque)
rtl8139_set_next_tctr_time(s, current_time);
s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
get_ticks_per_sec());
-s->rtl8139_mmio_io_addr_dummy = s->rtl8139_mmio_io_addr;
+s->rtl8139_mmio_io_addr_dummy = 0;
}
static const VMStateDescription vmstate_rtl8139 = {
@@ -3379,31 +3381,35 @@ static const VMStateDescription vmstate_rtl8139 = {
/***/
/* PCI RTL8139 definitions */
-static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
- pcibus_t addr, pcibus_t size, int type)
-{
-RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
-
-register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
-register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
-
-register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
-register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
-
-register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
-register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
-}
+static const MemoryRegionPortio rtl8139_portio[] = {
+{ 0, 0x100, 1, .read = rtl8139_ioport_readb, },
+{ 0, 0x100, 1, .write = rtl8139_ioport_writeb, },
+{ 0, 0x100, 2, .read = rtl8139_ioport_readw, },
+{ 0, 0x100, 2, .write = rtl8139_ioport_writew, },
+{ 0, 0x100, 4, .read = rtl8139_ioport_readl, },
+{ 0, 0x100, 4, .write = rtl8139_ioport_writel, },
+PORTIO_END
+};
-static CPUReadMemoryFunc * const rtl8139_mmio_read[3] = {
-rtl8139_mmio_readb,
-rtl8139_mmio_readw,
-rtl8139_mmio_readl,
+static const MemoryRegionOps rtl8139_io_ops = {
+.old_portio = rtl8139_portio,
+.endianness = DEVICE_LITTLE_ENDIAN,
};
-static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = {
-rtl8139_mmio_writeb,
-rtl8139_mmio_writew,
-rtl8139_mmio_writel,
+static const MemoryRegionOps rtl8139_mmio_ops = {
+.old_mmio = {
+.read = {
+rtl8139_mmio_readb,
+rtl8139_mmio_readw,
+rtl8139_mmio_readl,
+},
+.write = {
+rtl8139_mmio_writeb,
+rtl8139_mmio_writew,
+rtl8139_mmio_writel,
+},
+},
+.endianness = DEVICE_LITTLE_ENDIAN,
};
static void rtl8139_timer(void *opaque)
@@ -3432,7 +3438,8 @@ static int pci_rtl8139_uninit(PCIDevice *dev)
{
RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
-cpu_unregister_io_memory(s->rtl8139_mmio_io_addr);
+memory_region_destroy(&s->bar_io);
+memory_region_destroy(&s->bar_mem);
if (s->cplus_txbuffer) {
qemu_free(s->cplus_txbuffer);
s->cplus_txbuffer = NULL;
@@ -3462,15 +3469,12 @@ static int pci_rtl8139_init(PCIDevice *dev)
* list bit in status register, and offset 0xdc seems unused. */
pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
-/* I/O handler for memory-mapped I/O */
-s->rtl8139_mmio_io_addr =
-cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s,
- DEVICE_LITTLE_ENDIAN);
-
-pci_register_bar(&s->dev, 0, 0x100,
- PCI_BASE_ADDRESS_SPACE_IO, rtl8139_ioport_map);
-
-pci_register_bar_simple(&s->dev, 1, 0x100, 0, s->rtl8139_mmio_io_addr);
+memory_region_init_io(&s->bar_io, &rtl8139_io_ops, s, "rtl8139", 0x100);
+memory_region_init_io(&s->bar_mem, &rtl8139_mmio_ops, s, "rtl8139", 0x100);
+pci_register_bar_region(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO,
+&s->bar_io);
+pci_register_bar_region(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY,
+&s->bar_mem);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
--
1.7.5.3
[Qemu-devel] [PATCH 26/39] pcnet: convert to memory API
Also related chips.
Signed-off-by: Avi Kivity
---
hw/lance.c | 31 ++-
hw/pcnet-pci.c | 74 +--
hw/pcnet.h |4 ++-
3 files changed, 61 insertions(+), 48 deletions(-)
diff --git a/hw/lance.c b/hw/lance.c
index ddb1cbb..8e20360 100644
--- a/hw/lance.c
+++ b/hw/lance.c
@@ -55,8 +55,8 @@ static void parent_lance_reset(void *opaque, int irq, int
level)
pcnet_h_reset(&d->state);
}
-static void lance_mem_writew(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void lance_mem_write(void *opaque, target_phys_addr_t addr,
+uint64_t val, unsigned size)
{
SysBusPCNetState *d = opaque;
@@ -64,7 +64,8 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t
addr,
pcnet_ioport_writew(&d->state, addr, val & 0x);
}
-static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
+static uint64_t lance_mem_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
SysBusPCNetState *d = opaque;
uint32_t val;
@@ -74,16 +75,14 @@ static uint32_t lance_mem_readw(void *opaque,
target_phys_addr_t addr)
return val & 0x;
}
-static CPUReadMemoryFunc * const lance_mem_read[3] = {
-NULL,
-lance_mem_readw,
-NULL,
-};
-
-static CPUWriteMemoryFunc * const lance_mem_write[3] = {
-NULL,
-lance_mem_writew,
-NULL,
+static const MemoryRegionOps lance_mem_ops = {
+.read = lance_mem_read,
+.write = lance_mem_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+.valid = {
+.min_access_size = 2,
+.max_access_size = 2,
+},
};
static void lance_cleanup(VLANClientState *nc)
@@ -117,13 +116,11 @@ static int lance_init(SysBusDevice *dev)
SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev);
PCNetState *s = &d->state;
-s->mmio_index =
-cpu_register_io_memory(lance_mem_read, lance_mem_write, d,
- DEVICE_NATIVE_ENDIAN);
+memory_region_init_io(&s->mmio, &lance_mem_ops, s, "lance-mmio", 4);
qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1);
-sysbus_init_mmio(dev, 4, s->mmio_index);
+sysbus_init_mmio_region(dev, &s->mmio);
sysbus_init_irq(dev, &s->irq);
diff --git a/hw/pcnet-pci.c b/hw/pcnet-pci.c
index 216cf81..a25f565 100644
--- a/hw/pcnet-pci.c
+++ b/hw/pcnet-pci.c
@@ -46,6 +46,7 @@
typedef struct {
PCIDevice pci_dev;
PCNetState state;
+MemoryRegion io_bar;
} PCIPCNetState;
static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
@@ -69,25 +70,41 @@ static uint32_t pcnet_aprom_readb(void *opaque, uint32_t
addr)
return val;
}
-static void pcnet_ioport_map(PCIDevice *pci_dev, int region_num,
- pcibus_t addr, pcibus_t size, int type)
+static uint64_t pcnet_ioport_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
-PCNetState *d = &DO_UPCAST(PCIPCNetState, pci_dev, pci_dev)->state;
+PCNetState *d = opaque;
-#ifdef PCNET_DEBUG_IO
-printf("pcnet_ioport_map addr=0x%04"FMT_PCIBUS" size=0x%04"FMT_PCIBUS"\n",
- addr, size);
-#endif
+if (addr < 16 && size == 1) {
+return pcnet_aprom_readb(d, addr);
+} else if (addr >= 0x10 && addr < 0x20 && size == 2) {
+return pcnet_ioport_readw(d, addr);
+} else if (addr >= 0x10 && addr < 0x20 && size == 4) {
+return pcnet_ioport_readl(d, addr);
+}
+return ((uint64_t)1 << (size * 8)) - 1;
+}
-register_ioport_write(addr, 16, 1, pcnet_aprom_writeb, d);
-register_ioport_read(addr, 16, 1, pcnet_aprom_readb, d);
+static void pcnet_ioport_write(void *opaque, target_phys_addr_t addr,
+ uint64_t data, unsigned size)
+{
+PCNetState *d = opaque;
-register_ioport_write(addr + 0x10, 0x10, 2, pcnet_ioport_writew, d);
-register_ioport_read(addr + 0x10, 0x10, 2, pcnet_ioport_readw, d);
-register_ioport_write(addr + 0x10, 0x10, 4, pcnet_ioport_writel, d);
-register_ioport_read(addr + 0x10, 0x10, 4, pcnet_ioport_readl, d);
+if (addr < 16 && size == 1) {
+return pcnet_aprom_writeb(d, addr, data);
+} else if (addr >= 0x10 && addr < 0x20 && size == 2) {
+return pcnet_ioport_writew(d, addr, data);
+} else if (addr >= 0x10 && addr < 0x20 && size == 4) {
+return pcnet_ioport_writel(d, addr, data);
+}
}
+static const MemoryRegionOps pcnet_io_ops = {
+.read = pcnet_ioport_read,
+.write = pcnet_ioport_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t
val)
{
PCNetState *d = opaque;
@@ -202,16 +219,12 @@ static const VMStateDescription vmstate_pci_pcnet = {
/* PCI interface */
-static CPUWriteMemoryFunc * const pcnet_mmio_write[] = {
-&pcnet_mmio_writeb,
-
[Qemu-devel] [PATCH 17/39] es1370: convert to memory API
Signed-off-by: Avi Kivity
---
hw/es1370.c | 43 +--
1 files changed, 25 insertions(+), 18 deletions(-)
diff --git a/hw/es1370.c b/hw/es1370.c
index 1ed62b7..6a01797 100644
--- a/hw/es1370.c
+++ b/hw/es1370.c
@@ -268,6 +268,7 @@ struct chan {
typedef struct ES1370State {
PCIDevice dev;
QEMUSoundCard card;
+MemoryRegion io;
struct chan chan[NB_CHANNELS];
SWVoiceOut *dac_voice[2];
SWVoiceIn *adc_voice;
@@ -775,7 +776,6 @@ IO_READ_PROTO (es1370_readl)
return val;
}
-
static void es1370_transfer_audio (ES1370State *s, struct chan *d, int
loop_sel,
int max, int *irq)
{
@@ -906,23 +906,20 @@ static void es1370_adc_callback (void *opaque, int avail)
es1370_run_channel (s, ADC_CHANNEL, avail);
}
-static void es1370_map (PCIDevice *pci_dev, int region_num,
-pcibus_t addr, pcibus_t size, int type)
-{
-ES1370State *s = DO_UPCAST (ES1370State, dev, pci_dev);
-
-(void) region_num;
-(void) size;
-(void) type;
-
-register_ioport_write (addr, 0x40 * 4, 1, es1370_writeb, s);
-register_ioport_write (addr, 0x40 * 2, 2, es1370_writew, s);
-register_ioport_write (addr, 0x40, 4, es1370_writel, s);
+static const MemoryRegionPortio es1370_portio[] = {
+{ 0, 0x40 * 4, 1, .write = es1370_writeb, },
+{ 0, 0x40 * 2, 2, .write = es1370_writew, },
+{ 0, 0x40, 4, .write = es1370_writel, },
+{ 0, 0x40 * 4, 1, .read = es1370_readb, },
+{ 0, 0x40 * 2, 2, .read = es1370_readw, },
+{ 0, 0x40, 4, .read = es1370_readl, },
+PORTIO_END
+};
-register_ioport_read (addr, 0x40 * 4, 1, es1370_readb, s);
-register_ioport_read (addr, 0x40 * 2, 2, es1370_readw, s);
-register_ioport_read (addr, 0x40, 4, es1370_readl, s);
-}
+static const MemoryRegionOps es1370_io_ops = {
+.old_portio = es1370_portio,
+.endianness = DEVICE_LITTLE_ENDIAN,
+};
static const VMStateDescription vmstate_es1370_channel = {
.name = "es1370_channel",
@@ -1011,7 +1008,8 @@ static int es1370_initfn (PCIDevice *dev)
c[PCI_MIN_GNT] = 0x0c;
c[PCI_MAX_LAT] = 0x80;
-pci_register_bar (&s->dev, 0, 256, PCI_BASE_ADDRESS_SPACE_IO, es1370_map);
+memory_region_init_io(&s->io, &es1370_io_ops, s, "es1370", 256);
+pci_register_bar_region(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
qemu_register_reset (es1370_on_reset, s);
AUD_register_card ("es1370", &s->card);
@@ -1019,6 +1017,14 @@ static int es1370_initfn (PCIDevice *dev)
return 0;
}
+static int es1370_exitfn(PCIDevice *dev)
+{
+ES1370State *s = DO_UPCAST (ES1370State, dev, dev);
+
+memory_region_destroy(&s->io);
+return 0;
+}
+
int es1370_init (PCIBus *bus)
{
pci_create_simple (bus, -1, "ES1370");
@@ -1031,6 +1037,7 @@ static PCIDeviceInfo es1370_info = {
.qdev.size= sizeof (ES1370State),
.qdev.vmsd= &vmstate_es1370,
.init = es1370_initfn,
+.exit = es1370_exitfn,
.vendor_id= PCI_VENDOR_ID_ENSONIQ,
.device_id= PCI_DEVICE_ID_ENSONIQ_ES1370,
.class_id = PCI_CLASS_MULTIMEDIA_AUDIO,
--
1.7.5.3
[Qemu-devel] [PATCH 10/39] exec.c: fix initialization of system I/O memory region
Signed-off-by: Avi Kivity --- exec.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/exec.c b/exec.c index 2fd4adb..11f6641 100644 --- a/exec.c +++ b/exec.c @@ -3823,7 +3823,7 @@ static void memory_map_init(void) set_system_memory_map(system_memory); system_io = qemu_malloc(sizeof(*system_io)); -memory_region_init(system_memory, "io", 65536); +memory_region_init(system_io, "io", 65536); set_system_io_map(system_io); } -- 1.7.5.3
[Qemu-devel] [PATCH 35/39] pci: convert pci rom to memory API
Signed-off-by: Avi Kivity
---
hw/pci.c | 20 +++-
hw/pci.h |3 ++-
2 files changed, 9 insertions(+), 14 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 6aca1af..481eb7e 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1857,11 +1857,6 @@ static uint8_t pci_find_capability_list(PCIDevice *pdev,
uint8_t cap_id,
return next;
}
-static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr,
pcibus_t size, int type)
-{
-cpu_register_physical_memory(addr, size, pdev->rom_offset);
-}
-
/* Patch the PCI vendor and device ids in a PCI rom image if necessary.
This is needed for an option rom which is used for more than one device. */
static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
@@ -1965,9 +1960,9 @@ static int pci_add_option_rom(PCIDevice *pdev, bool
is_default_rom)
snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
else
snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
-pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
-
-ptr = qemu_get_ram_ptr(pdev->rom_offset);
+pdev->has_rom = true;
+memory_region_init_ram(&pdev->rom, &pdev->qdev, name, size);
+ptr = memory_region_get_ram_ptr(&pdev->rom);
load_image(path, ptr);
qemu_free(path);
@@ -1978,19 +1973,18 @@ static int pci_add_option_rom(PCIDevice *pdev, bool
is_default_rom)
qemu_put_ram_ptr(ptr);
-pci_register_bar(pdev, PCI_ROM_SLOT, size,
- 0, pci_map_option_rom);
+pci_register_bar_region(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
return 0;
}
static void pci_del_option_rom(PCIDevice *pdev)
{
-if (!pdev->rom_offset)
+if (!pdev->has_rom)
return;
-qemu_ram_free(pdev->rom_offset);
-pdev->rom_offset = 0;
+memory_region_destroy(&pdev->rom);
+pdev->has_rom = false;
}
/*
diff --git a/hw/pci.h b/hw/pci.h
index 25e28b1..6e2bcea 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -191,7 +191,8 @@ struct PCIDevice {
/* Location of option rom */
char *romfile;
-ram_addr_t rom_offset;
+bool has_rom;
+MemoryRegion rom;
uint32_t rom_bar;
};
--
1.7.5.3
[Qemu-devel] [PATCH 22/39] intel-hda: convert to memory API
Signed-off-by: Avi Kivity
---
hw/intel-hda.c | 35 +++
1 files changed, 19 insertions(+), 16 deletions(-)
diff --git a/hw/intel-hda.c b/hw/intel-hda.c
index 5a2bc3a..1e4c71e 100644
--- a/hw/intel-hda.c
+++ b/hw/intel-hda.c
@@ -177,7 +177,7 @@ struct IntelHDAState {
IntelHDAStream st[8];
/* state */
-int mmio_addr;
+MemoryRegion mmio;
uint32_t rirb_count;
int64_t wall_base_ns;
@@ -1084,16 +1084,20 @@ static uint32_t intel_hda_mmio_readl(void *opaque,
target_phys_addr_t addr)
return intel_hda_reg_read(d, reg, 0x);
}
-static CPUReadMemoryFunc * const intel_hda_mmio_read[3] = {
-intel_hda_mmio_readb,
-intel_hda_mmio_readw,
-intel_hda_mmio_readl,
-};
-
-static CPUWriteMemoryFunc * const intel_hda_mmio_write[3] = {
-intel_hda_mmio_writeb,
-intel_hda_mmio_writew,
-intel_hda_mmio_writel,
+static const MemoryRegionOps intel_hda_mmio_ops = {
+.old_mmio = {
+.read = {
+intel_hda_mmio_readb,
+intel_hda_mmio_readw,
+intel_hda_mmio_readl,
+},
+.write = {
+intel_hda_mmio_writeb,
+intel_hda_mmio_writew,
+intel_hda_mmio_writel,
+},
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
};
/* - */
@@ -1130,10 +1134,9 @@ static int intel_hda_init(PCIDevice *pci)
/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
conf[0x40] = 0x01;
-d->mmio_addr = cpu_register_io_memory(intel_hda_mmio_read,
- intel_hda_mmio_write, d,
- DEVICE_NATIVE_ENDIAN);
-pci_register_bar_simple(&d->pci, 0, 0x4000, 0, d->mmio_addr);
+memory_region_init_io(&d->mmio, &intel_hda_mmio_ops, d,
+ "intel-hda", 0x4000);
+pci_register_bar_region(&d->pci, 0, 0, &d->mmio);
if (d->msi) {
msi_init(&d->pci, 0x50, 1, true, false);
}
@@ -1149,7 +1152,7 @@ static int intel_hda_exit(PCIDevice *pci)
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
msi_uninit(&d->pci);
-cpu_unregister_io_memory(d->mmio_addr);
+memory_region_destroy(&d->mmio);
return 0;
}
--
1.7.5.3
[Qemu-devel] [PATCH 31/39] uhci: convert to memory API
Signed-off-by: Avi Kivity
---
hw/usb-uhci.c | 42 --
1 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c
index da74c57..96a17bd 100644
--- a/hw/usb-uhci.c
+++ b/hw/usb-uhci.c
@@ -132,6 +132,7 @@ typedef struct UHCIPort {
struct UHCIState {
PCIDevice dev;
+MemoryRegion io_bar;
USBBus bus; /* Note unused when we're a companion controller */
uint16_t cmd; /* cmd register */
uint16_t status;
@@ -1101,18 +1102,19 @@ static void uhci_frame_timer(void *opaque)
qemu_mod_timer(s->frame_timer, s->expire_time);
}
-static void uhci_map(PCIDevice *pci_dev, int region_num,
-pcibus_t addr, pcibus_t size, int type)
-{
-UHCIState *s = (UHCIState *)pci_dev;
-
-register_ioport_write(addr, 32, 2, uhci_ioport_writew, s);
-register_ioport_read(addr, 32, 2, uhci_ioport_readw, s);
-register_ioport_write(addr, 32, 4, uhci_ioport_writel, s);
-register_ioport_read(addr, 32, 4, uhci_ioport_readl, s);
-register_ioport_write(addr, 32, 1, uhci_ioport_writeb, s);
-register_ioport_read(addr, 32, 1, uhci_ioport_readb, s);
-}
+static const MemoryRegionPortio uhci_portio[] = {
+{ 0, 32, 2, .write = uhci_ioport_writew, },
+{ 0, 32, 2, .read = uhci_ioport_readw, },
+{ 0, 32, 4, .write = uhci_ioport_writel, },
+{ 0, 32, 4, .read = uhci_ioport_readl, },
+{ 0, 32, 1, .write = uhci_ioport_writeb, },
+{ 0, 32, 1, .read = uhci_ioport_readb, },
+PORTIO_END
+};
+
+static const MemoryRegionOps uhci_ioport_ops = {
+.old_portio = uhci_portio,
+};
static USBPortOps uhci_port_ops = {
.attach = uhci_attach,
@@ -1159,10 +1161,11 @@ static int usb_uhci_common_initfn(PCIDevice *dev)
qemu_register_reset(uhci_reset, s);
+memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20);
/* Use region 4 for consistency with real hardware. BSD guests seem
to rely on this. */
-pci_register_bar(&s->dev, 4, 0x20,
- PCI_BASE_ADDRESS_SPACE_IO, uhci_map);
+pci_register_bar_region(&s->dev, 4,
+PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
return 0;
}
@@ -1182,6 +1185,14 @@ static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
return usb_uhci_common_initfn(dev);
}
+static int usb_uhci_exit(PCIDevice *dev)
+{
+UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
+
+memory_region_destroy(&s->io_bar);
+return 0;
+}
+
static Property uhci_properties[] = {
DEFINE_PROP_STRING("masterbus", UHCIState, masterbus),
DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0),
@@ -1194,6 +1205,7 @@ static PCIDeviceInfo uhci_info[] = {
.qdev.size= sizeof(UHCIState),
.qdev.vmsd= &vmstate_uhci,
.init = usb_uhci_common_initfn,
+.exit = usb_uhci_exit,
.vendor_id= PCI_VENDOR_ID_INTEL,
.device_id= PCI_DEVICE_ID_INTEL_82371SB_2,
.revision = 0x01,
@@ -1204,6 +1216,7 @@ static PCIDeviceInfo uhci_info[] = {
.qdev.size= sizeof(UHCIState),
.qdev.vmsd= &vmstate_uhci,
.init = usb_uhci_common_initfn,
+.exit = usb_uhci_exit,
.vendor_id= PCI_VENDOR_ID_INTEL,
.device_id= PCI_DEVICE_ID_INTEL_82371AB_2,
.revision = 0x01,
@@ -1214,6 +1227,7 @@ static PCIDeviceInfo uhci_info[] = {
.qdev.size= sizeof(UHCIState),
.qdev.vmsd= &vmstate_uhci,
.init = usb_uhci_vt82c686b_initfn,
+.exit = usb_uhci_exit,
.vendor_id= PCI_VENDOR_ID_VIA,
.device_id= PCI_DEVICE_ID_VIA_UHCI,
.revision = 0x01,
--
1.7.5.3
[Qemu-devel] [PATCH 21/39] ahci: convert to memory API
Signed-off-by: Avi Kivity
---
hw/ide/ahci.c | 31 +--
hw/ide/ahci.h |2 +-
hw/ide/ich.c |3 +--
3 files changed, 15 insertions(+), 21 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 1f008a3..e207ca0 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -276,12 +276,12 @@ static void ahci_port_write(AHCIState *s, int port, int
offset, uint32_t val)
}
}
-static uint32_t ahci_mem_readl(void *ptr, target_phys_addr_t addr)
+static uint64_t ahci_mem_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
-AHCIState *s = ptr;
+AHCIState *s = opaque;
uint32_t val = 0;
-addr = addr & 0xfff;
if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
switch (addr) {
case HOST_CAP:
@@ -314,10 +314,10 @@ static uint32_t ahci_mem_readl(void *ptr,
target_phys_addr_t addr)
-static void ahci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
+static void ahci_mem_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
-AHCIState *s = ptr;
-addr = addr & 0xfff;
+AHCIState *s = opaque;
/* Only aligned reads are allowed on AHCI */
if (addr & 3) {
@@ -364,16 +364,10 @@ static void ahci_mem_writel(void *ptr, target_phys_addr_t
addr, uint32_t val)
}
-static CPUReadMemoryFunc * const ahci_readfn[3]={
-ahci_mem_readl,
-ahci_mem_readl,
-ahci_mem_readl
-};
-
-static CPUWriteMemoryFunc * const ahci_writefn[3]={
-ahci_mem_writel,
-ahci_mem_writel,
-ahci_mem_writel
+static MemoryRegionOps ahci_mem_ops = {
+.read = ahci_mem_read,
+.write = ahci_mem_write,
+.endianness = DEVICE_LITTLE_ENDIAN,
};
static void ahci_reg_init(AHCIState *s)
@@ -1131,8 +1125,8 @@ void ahci_init(AHCIState *s, DeviceState *qdev, int ports)
s->ports = ports;
s->dev = qemu_mallocz(sizeof(AHCIDevice) * ports);
ahci_reg_init(s);
-s->mem = cpu_register_io_memory(ahci_readfn, ahci_writefn, s,
-DEVICE_LITTLE_ENDIAN);
+/* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
+memory_region_init_io(&s->mem, &ahci_mem_ops, s, "ahci", 0x1000);
irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);
for (i = 0; i < s->ports; i++) {
@@ -1151,6 +1145,7 @@ void ahci_init(AHCIState *s, DeviceState *qdev, int ports)
void ahci_uninit(AHCIState *s)
{
+memory_region_destroy(&s->mem);
qemu_free(s->dev);
}
diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
index dc86951..e456193 100644
--- a/hw/ide/ahci.h
+++ b/hw/ide/ahci.h
@@ -289,7 +289,7 @@ struct AHCIDevice {
typedef struct AHCIState {
AHCIDevice *dev;
AHCIControlRegs control_regs;
-int mem;
+MemoryRegion mem;
int ports;
qemu_irq irq;
} AHCIState;
diff --git a/hw/ide/ich.c b/hw/ide/ich.c
index d241ea8..698b5f6 100644
--- a/hw/ide/ich.c
+++ b/hw/ide/ich.c
@@ -98,8 +98,7 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
msi_init(dev, 0x50, 1, true, false);
d->ahci.irq = d->card.irq[0];
-/* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
-pci_register_bar_simple(&d->card, 5, 0x1000, 0, d->ahci.mem);
+pci_register_bar_region(&d->card, 5, 0, &d->ahci.mem);
return 0;
}
--
1.7.5.3
[Qemu-devel] [PATCH 28/39] isa-mmio: concert to memory API
Signed-off-by: Avi Kivity
---
hw/isa.h |2 ++
hw/isa_mmio.c | 30 +++---
2 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/hw/isa.h b/hw/isa.h
index d2b6126..f1f2181 100644
--- a/hw/isa.h
+++ b/hw/isa.h
@@ -4,6 +4,7 @@
/* ISA bus */
#include "ioport.h"
+#include "memory.h"
#include "qdev.h"
typedef struct ISABus ISABus;
@@ -37,6 +38,7 @@ ISADevice *isa_create_simple(const char *name);
extern target_phys_addr_t isa_mem_base;
+void isa_mmio_setup(MemoryRegion *mr, target_phys_addr_t size);
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
/* dma.c */
diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c
index ca957fb..600225f 100644
--- a/hw/isa_mmio.c
+++ b/hw/isa_mmio.c
@@ -58,25 +58,25 @@ static uint32_t isa_mmio_readl(void *opaque,
target_phys_addr_t addr)
return cpu_inl(addr & IOPORTS_MASK);
}
-static CPUWriteMemoryFunc * const isa_mmio_write[] = {
-&isa_mmio_writeb,
-&isa_mmio_writew,
-&isa_mmio_writel,
+static const MemoryRegionOps isa_mmio_ops = {
+.old_mmio = {
+.write = { isa_mmio_writeb, isa_mmio_writew, isa_mmio_writel },
+.read = { isa_mmio_readb, isa_mmio_readw, isa_mmio_readl, },
+},
+.endianness = DEVICE_LITTLE_ENDIAN,
};
-static CPUReadMemoryFunc * const isa_mmio_read[] = {
-&isa_mmio_readb,
-&isa_mmio_readw,
-&isa_mmio_readl,
-};
+void isa_mmio_setup(MemoryRegion *mr, target_phys_addr_t size)
+{
+memory_region_init_io(mr, &isa_mmio_ops, NULL, "isa-mmio", size);
+}
+
+#include "exec-memory.h"
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)
{
-int isa_mmio_iomemtype;
+MemoryRegion *mr = qemu_malloc(sizeof(*mr));
-isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read,
-isa_mmio_write,
-NULL,
-DEVICE_LITTLE_ENDIAN);
-cpu_register_physical_memory(base, size, isa_mmio_iomemtype);
+isa_mmio_setup(mr, size);
+memory_region_add_subregion(get_system_memory(), base, mr);
}
--
1.7.5.3
[Qemu-devel] [PATCH 18/39] ide: convert to memory API
Signed-off-by: Avi Kivity
---
hw/ide/cmd646.c | 208 +++
hw/ide/pci.c| 25 ---
hw/ide/pci.h| 19 -
hw/ide/piix.c | 64 +
hw/ide/via.c| 65 +
5 files changed, 261 insertions(+), 120 deletions(-)
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index 56302b5..699ad6b 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -44,35 +44,95 @@
static void cmd646_update_irq(PCIIDEState *d);
-static void ide_map(PCIDevice *pci_dev, int region_num,
-pcibus_t addr, pcibus_t size, int type)
+static uint64_t cmd646_cmd_read(void *opaque, target_phys_addr_t addr,
+unsigned size)
{
-PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
-IDEBus *bus;
-
-if (region_num <= 3) {
-bus = &d->bus[(region_num >> 1)];
-if (region_num & 1) {
-register_ioport_read(addr + 2, 1, 1, ide_status_read, bus);
-register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus);
+CMD646BAR *cmd646bar = opaque;
+
+if (addr != 2 || size != 1) {
+return ((uint64_t)1 << (size * 8)) - 1;
+}
+return ide_status_read(cmd646bar->bus, addr + 2);
+}
+
+static void cmd646_cmd_write(void *opaque, target_phys_addr_t addr,
+ uint64_t data, unsigned size)
+{
+CMD646BAR *cmd646bar = opaque;
+
+if (addr != 2 || size != 1) {
+return;
+}
+ide_cmd_write(cmd646bar->bus, addr + 2, data);
+}
+
+static MemoryRegionOps cmd646_cmd_ops = {
+.read = cmd646_cmd_read,
+.write = cmd646_cmd_write,
+.endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static uint64_t cmd646_data_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
+{
+CMD646BAR *cmd646bar = opaque;
+
+if (size == 1) {
+return ide_ioport_read(cmd646bar->bus, addr);
+} else if (addr == 0) {
+if (size == 2) {
+return ide_data_readw(cmd646bar->bus, addr);
} else {
-register_ioport_write(addr, 8, 1, ide_ioport_write, bus);
-register_ioport_read(addr, 8, 1, ide_ioport_read, bus);
-
-/* data ports */
-register_ioport_write(addr, 2, 2, ide_data_writew, bus);
-register_ioport_read(addr, 2, 2, ide_data_readw, bus);
-register_ioport_write(addr, 4, 4, ide_data_writel, bus);
-register_ioport_read(addr, 4, 4, ide_data_readl, bus);
+return ide_data_readl(cmd646bar->bus, addr);
}
}
+return ((uint64_t)1 << (size * 8)) - 1;
}
-static uint32_t bmdma_readb_common(PCIIDEState *pci_dev, BMDMAState *bm,
- uint32_t addr)
+static void cmd646_data_write(void *opaque, target_phys_addr_t addr,
+ uint64_t data, unsigned size)
{
+CMD646BAR *cmd646bar = opaque;
+
+if (size == 1) {
+return ide_ioport_write(cmd646bar->bus, addr, data);
+} else if (addr == 0) {
+if (size == 2) {
+return ide_data_writew(cmd646bar->bus, addr, data);
+} else {
+return ide_data_writel(cmd646bar->bus, addr, data);
+}
+}
+}
+
+static MemoryRegionOps cmd646_data_ops = {
+.read = cmd646_data_read,
+.write = cmd646_data_write,
+.endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
+{
+IDEBus *bus = &d->bus[bus_num];
+CMD646BAR *bar = &d->cmd646_bar[bus_num];
+
+bar->bus = bus;
+bar->pci_dev = d;
+memory_region_init_io(&bar->cmd, &cmd646_cmd_ops, bar, "cmd646-cmd", 4);
+memory_region_init_io(&bar->data, &cmd646_data_ops, bar, "cmd646-data", 8);
+}
+
+static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
+{
+BMDMAState *bm = opaque;
+PCIIDEState *pci_dev = bm->pci_dev;
uint32_t val;
+if (size != 1) {
+return ((uint64_t)1 << (size * 8)) - 1;
+}
+
switch(addr & 3) {
case 0:
val = bm->cmd;
@@ -100,31 +160,22 @@ static uint32_t bmdma_readb_common(PCIIDEState *pci_dev,
BMDMAState *bm,
return val;
}
-static uint32_t bmdma_readb_0(void *opaque, uint32_t addr)
+static void bmdma_write(void *opaque, target_phys_addr_t addr,
+uint64_t val, unsigned size)
{
-PCIIDEState *pci_dev = opaque;
-BMDMAState *bm = &pci_dev->bmdma[0];
-
-return bmdma_readb_common(pci_dev, bm, addr);
-}
+BMDMAState *bm = opaque;
+PCIIDEState *pci_dev = bm->pci_dev;
-static uint32_t bmdma_readb_1(void *opaque, uint32_t addr)
-{
-PCIIDEState *pci_dev = opaque;
-BMDMAState *bm = &pci_dev->bmdma[1];
-
-return bmdma_readb_common(pci_dev, bm, addr);
-}
+if (size != 1) {
+return;
+}
-static void bmdma_writeb_common(PCIIDEState *pci_dev, BMDMAState *bm,
-uint32_t addr, uint32_t val)
-{
#if
[Qemu-devel] [PATCH 05/39] cirrus: simplify bitblt BAR access functions
Make use of the memory API's ability to satisfy multi-byte accesses via
multiple single-byte accesses.
Signed-off-by: Avi Kivity
---
hw/cirrus_vga.c | 81 +--
1 files changed, 13 insertions(+), 68 deletions(-)
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index 6e1aa75..b8a51b4 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -2445,37 +2445,23 @@ static void cirrus_linear_write(void *opaque,
target_phys_addr_t addr,
***/
-static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t
addr)
+static uint64_t cirrus_linear_bitblt_read(void *opaque,
+ target_phys_addr_t addr,
+ unsigned size)
{
+CirrusVGAState *s = opaque;
uint32_t ret;
/* XXX handle bitblt */
+(void)s;
ret = 0xff;
return ret;
}
-static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t
addr)
-{
-uint32_t v;
-
-v = cirrus_linear_bitblt_readb(opaque, addr);
-v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
-return v;
-}
-
-static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t
addr)
-{
-uint32_t v;
-
-v = cirrus_linear_bitblt_readb(opaque, addr);
-v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
-v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
-v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
-return v;
-}
-
-static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
-uint32_t val)
+static void cirrus_linear_bitblt_write(void *opaque,
+ target_phys_addr_t addr,
+ uint64_t val,
+ unsigned size)
{
CirrusVGAState *s = opaque;
@@ -2488,55 +2474,14 @@ static void cirrus_linear_bitblt_writeb(void *opaque,
target_phys_addr_t addr,
}
}
-static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
-uint32_t val)
-{
-cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
-cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
-}
-
-static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
-uint32_t val)
-{
-cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
-cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
-cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
-cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
-}
-
-static uint64_t cirrus_linear_bitblt_read(void *opaque,
- target_phys_addr_t addr,
- unsigned size)
-{
-CirrusVGAState *s = opaque;
-
-switch (size) {
-case 1: return cirrus_linear_bitblt_readb(s, addr);
-case 2: return cirrus_linear_bitblt_readw(s, addr);
-case 4: return cirrus_linear_bitblt_readl(s, addr);
-default: abort();
-}
-};
-
-static void cirrus_linear_bitblt_write(void *opaque,
- target_phys_addr_t addr,
- uint64_t data,
- unsigned size)
-{
-CirrusVGAState *s = opaque;
-
-switch (size) {
-case 1: return cirrus_linear_bitblt_writeb(s, addr, data);
-case 2: return cirrus_linear_bitblt_writew(s, addr, data);
-case 4: return cirrus_linear_bitblt_writel(s, addr, data);
-default: abort();
-}
-};
-
static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
.read = cirrus_linear_bitblt_read,
.write = cirrus_linear_bitblt_write,
.endianness = DEVICE_LITTLE_ENDIAN,
+.impl = {
+.min_access_size = 1,
+.max_access_size = 1,
+},
};
#include "exec-memory.h"
--
1.7.5.3
[Qemu-devel] [PATCH] memory: synchronize dirty bitmap before unmapping a range
When a range is being unmapped, ask accelerators (e.g. kvm) to synchronize the
dirty bitmap to avoid losing information forever.
Fixes grub2 screen update.
Signed-off-by: Avi Kivity
---
Please apply before the PCI batch to avoid bisectability issues (and don't
pull, since that removes ordering).
memory.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/memory.c b/memory.c
index 5c6e63d..5f20320 100644
--- a/memory.c
+++ b/memory.c
@@ -245,6 +245,10 @@ static void as_memory_range_add(AddressSpace *as,
FlatRange *fr)
static void as_memory_range_del(AddressSpace *as, FlatRange *fr)
{
+if (fr->dirty_log_mask) {
+cpu_physical_sync_dirty_bitmap(fr->addr.start,
+ fr->addr.start + fr->addr.size);
+}
cpu_register_physical_memory(fr->addr.start, fr->addr.size,
IO_MEM_UNASSIGNED);
}
--
1.7.5.3
[Qemu-devel] [PATCH 19/39] ivshmem: convert to memory API
excluding msix.
Signed-off-by: Avi Kivity
---
hw/ivshmem.c | 148 --
1 files changed, 50 insertions(+), 98 deletions(-)
diff --git a/hw/ivshmem.c b/hw/ivshmem.c
index 3055dd2..f80e7b6 100644
--- a/hw/ivshmem.c
+++ b/hw/ivshmem.c
@@ -56,11 +56,15 @@ typedef struct IVShmemState {
CharDriverState **eventfd_chr;
CharDriverState *server_chr;
-int ivshmem_mmio_io_addr;
+MemoryRegion ivshmem_mmio;
pcibus_t mmio_addr;
-pcibus_t shm_pci_addr;
-uint64_t ivshmem_offset;
+/* We might need to register the BAR before we actually have the memory.
+ * So prepare a container MemoryRegion for the BAR immediately and
+ * add a subregion when we have the memory.
+ */
+MemoryRegion bar;
+MemoryRegion ivshmem;
uint64_t ivshmem_size; /* size of shared memory region */
int shm_fd; /* shared memory file descriptor */
@@ -96,23 +100,6 @@ static inline bool is_power_of_two(uint64_t x) {
return (x & (x - 1)) == 0;
}
-static void ivshmem_map(PCIDevice *pci_dev, int region_num,
-pcibus_t addr, pcibus_t size, int type)
-{
-IVShmemState *s = DO_UPCAST(IVShmemState, dev, pci_dev);
-
-s->shm_pci_addr = addr;
-
-if (s->ivshmem_offset > 0) {
-cpu_register_physical_memory(s->shm_pci_addr, s->ivshmem_size,
-s->ivshmem_offset);
-}
-
-IVSHMEM_DPRINTF("guest pci addr = %" FMT_PCIBUS ", guest h/w addr = %"
-PRIu64 ", size = %" FMT_PCIBUS "\n", addr, s->ivshmem_offset, size);
-
-}
-
/* accessing registers - based on rtl8139 */
static void ivshmem_update_irq(IVShmemState *s, int val)
{
@@ -168,15 +155,8 @@ static uint32_t ivshmem_IntrStatus_read(IVShmemState *s)
return ret;
}
-static void ivshmem_io_writew(void *opaque, target_phys_addr_t addr,
-uint32_t val)
-{
-
-IVSHMEM_DPRINTF("We shouldn't be writing words\n");
-}
-
-static void ivshmem_io_writel(void *opaque, target_phys_addr_t addr,
-uint32_t val)
+static void ivshmem_io_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
IVShmemState *s = opaque;
@@ -219,20 +199,8 @@ static void ivshmem_io_writel(void *opaque,
target_phys_addr_t addr,
}
}
-static void ivshmem_io_writeb(void *opaque, target_phys_addr_t addr,
-uint32_t val)
-{
-IVSHMEM_DPRINTF("We shouldn't be writing bytes\n");
-}
-
-static uint32_t ivshmem_io_readw(void *opaque, target_phys_addr_t addr)
-{
-
-IVSHMEM_DPRINTF("We shouldn't be reading words\n");
-return 0;
-}
-
-static uint32_t ivshmem_io_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t ivshmem_io_read(void *opaque, target_phys_addr_t addr,
+unsigned size)
{
IVShmemState *s = opaque;
@@ -265,23 +233,14 @@ static uint32_t ivshmem_io_readl(void *opaque,
target_phys_addr_t addr)
return ret;
}
-static uint32_t ivshmem_io_readb(void *opaque, target_phys_addr_t addr)
-{
-IVSHMEM_DPRINTF("We shouldn't be reading bytes\n");
-
-return 0;
-}
-
-static CPUReadMemoryFunc * const ivshmem_mmio_read[3] = {
-ivshmem_io_readb,
-ivshmem_io_readw,
-ivshmem_io_readl,
-};
-
-static CPUWriteMemoryFunc * const ivshmem_mmio_write[3] = {
-ivshmem_io_writeb,
-ivshmem_io_writew,
-ivshmem_io_writel,
+static const MemoryRegionOps ivshmem_mmio_ops = {
+.read = ivshmem_io_read,
+.write = ivshmem_io_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
};
static void ivshmem_receive(void *opaque, const uint8_t *buf, int size)
@@ -371,12 +330,12 @@ static void create_shared_memory_BAR(IVShmemState *s, int
fd) {
ptr = mmap(0, s->ivshmem_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
-s->ivshmem_offset = qemu_ram_alloc_from_ptr(&s->dev.qdev, "ivshmem.bar2",
-s->ivshmem_size, ptr);
+memory_region_init_ram_ptr(&s->ivshmem, &s->dev.qdev, "ivshmem.bar2",
+ s->ivshmem_size, ptr);
+memory_region_add_subregion(&s->bar, 0, &s->ivshmem);
/* region for shared memory */
-pci_register_bar(&s->dev, 2, s->ivshmem_size,
-PCI_BASE_ADDRESS_SPACE_MEMORY, ivshmem_map);
+pci_register_bar_region(&s->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY,
&s->bar);
}
static void close_guest_eventfds(IVShmemState *s, int posn)
@@ -401,8 +360,12 @@ static void setup_ioeventfds(IVShmemState *s) {
for (i = 0; i <= s->max_peer; i++) {
for (j = 0; j < s->peers[i].nb_eventfds; j++) {
-kvm_set_ioeventfd_mmio_long(s->peers[i].eventfds[j],
-s->m
[Qemu-devel] [PATCH 30/39] ehci: convert to memory API
Signed-off-by: Avi Kivity
---
hw/usb-ehci.c | 36 +---
1 files changed, 9 insertions(+), 27 deletions(-)
diff --git a/hw/usb-ehci.c b/hw/usb-ehci.c
index 8b0dcc3..025ed1f 100644
--- a/hw/usb-ehci.c
+++ b/hw/usb-ehci.c
@@ -368,8 +368,7 @@ struct EHCIState {
PCIDevice dev;
USBBus bus;
qemu_irq irq;
-target_phys_addr_t mem_base;
-int mem;
+MemoryRegion mem;
int companion_count;
/* properties */
@@ -2207,29 +2206,15 @@ static void ehci_frame_timer(void *opaque)
qemu_mod_timer(ehci->frame_timer, expire_time);
}
-static CPUReadMemoryFunc *ehci_readfn[3]={
-ehci_mem_readb,
-ehci_mem_readw,
-ehci_mem_readl
-};
-static CPUWriteMemoryFunc *ehci_writefn[3]={
-ehci_mem_writeb,
-ehci_mem_writew,
-ehci_mem_writel
+static const MemoryRegionOps ehci_mem_ops = {
+.old_mmio = {
+.read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl },
+.write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel },
+},
+.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void ehci_map(PCIDevice *pci_dev, int region_num,
- pcibus_t addr, pcibus_t size, int type)
-{
-EHCIState *s =(EHCIState *)pci_dev;
-
-DPRINTF("ehci_map: region %d, addr %08" PRIx64 ", size %" PRId64 ", s->mem
%08X\n",
-region_num, addr, size, s->mem);
-s->mem_base = addr;
-cpu_register_physical_memory(addr, size, s->mem);
-}
-
static int usb_ehci_initfn(PCIDevice *dev);
static USBPortOps ehci_port_ops = {
@@ -2344,11 +2329,8 @@ static int usb_ehci_initfn(PCIDevice *dev)
qemu_register_reset(ehci_reset, s);
-s->mem = cpu_register_io_memory(ehci_readfn, ehci_writefn, s,
-DEVICE_LITTLE_ENDIAN);
-
-pci_register_bar(&s->dev, 0, MMIO_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
-ehci_map);
+memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE);
+pci_register_bar_region(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
&s->mem);
fprintf(stderr, "*** EHCI support is under development ***\n");
--
1.7.5.3
[Qemu-devel] [PATCH 00/39] Memory API, batch 2: PCI devices
This is a mostly mindless conversion of all QEMU PCI devices to the memory API. After this patchset is applied, it is no longer possible to create a PCI device using the old API. An immediate benefit is that PCI BARs that overlap each other are now handled correctly: currently, the sequence map BAR 0 map BAR 1 at an overlapping address unmap either BAR 0 or BAR 1 will leave a hole where the overlap exists. With the patchset, the memory map is restored correctly. Note that overlaps of PCI BARs with memory or non-PCI resources are still not resolved correctly; this will be fixed later on. The vga patches have ugly intermediate states; however the result is fairly clean. Also available from: git://git.kernel.org/pub/scm/virt/kvm/qemu-kvm.git memory-region-b2 Avi Kivity (39): pci: add API to get a BAR's mapped address vmsvga: don't remember pci BAR address in callback any more vga: convert vga and its derivatives to the memory API cirrus: simplify mmio BAR access functions cirrus: simplify bitblt BAR access functions cirrus: simplify vga window mmio access functions vga: simplify vga window mmio access functions cirrus: simplify linear framebuffer access functions Integrate I/O memory regions into qemu exec.c: fix initialization of system I/O memory region pci: pass I/O address space to new PCI bus pci: allow I/O BARs to be registered with pci_register_bar_region() rtl8139: convert to memory API ac97: convert to memory API e1000: convert to memory API eepro100: convert to memory API es1370: convert to memory API ide: convert to memory API ivshmem: convert to memory API virtio-pci: convert to memory API ahci: convert to memory API intel-hda: convert to memory API lsi53c895a: convert to memory API ppc: convert to memory API ne2000: convert to memory API pcnet: convert to memory API i6300esb: convert to memory API isa-mmio: concert to memory API sun4u: convert to memory API ehci: convert to memory API uhci: convert to memory API xen-platform: convert to memory API msix: convert to memory API pci: remove pci_register_bar_simple() pci: convert pci rom to memory API pci: remove pci_register_bar() pci: fold BAR mapping function into its caller pci: rename pci_register_bar_region() to pci_register_bar() pci: remove support for pre memory API BARs exec-memory.h |2 + exec.c | 10 ++ hw/ac97.c | 88 ++- hw/apb_pci.c |1 + hw/bonito.c|1 + hw/cirrus_vga.c| 458 --- hw/cuda.c |6 +- hw/e1000.c | 113 ++ hw/eepro100.c | 181 - hw/es1370.c| 43 +++-- hw/escc.c | 42 +++--- hw/escc.h |2 +- hw/grackle_pci.c |8 +- hw/gt64xxx.c |4 +- hw/heathrow_pic.c | 29 ++-- hw/ide.h |2 +- hw/ide/ahci.c | 31 ++-- hw/ide/ahci.h |2 +- hw/ide/cmd646.c| 204 +++- hw/ide/ich.c |3 +- hw/ide/macio.c | 36 +++-- hw/ide/pci.c | 25 ++-- hw/ide/pci.h | 19 ++- hw/ide/piix.c | 63 ++-- hw/ide/via.c | 64 ++-- hw/intel-hda.c | 35 +++-- hw/isa.h |2 + hw/isa_mmio.c | 30 ++-- hw/ivshmem.c | 158 +++ hw/lance.c | 31 ++-- hw/lsi53c895a.c| 257 +++--- hw/mac_dbdma.c | 32 ++-- hw/mac_dbdma.h |4 +- hw/mac_nvram.c | 39 ++--- hw/macio.c | 73 - hw/msix.c | 64 +++- hw/msix.h |6 +- hw/ne2000-isa.c| 14 +-- hw/ne2000.c| 77 ++--- hw/ne2000.h|8 +- hw/openpic.c | 81 +- hw/openpic.h |2 +- hw/pc.h|4 +- hw/pc_piix.c |6 +- hw/pci.c | 133 +--- hw/pci.h | 26 ++-- hw/pci_internals.h |3 +- hw/pcnet-pci.c | 74 + hw/pcnet.h |4 +- hw/piix_pci.c | 14 +- hw/ppc4xx_pci.c|1 + hw/ppc_mac.h | 27 ++-- hw/ppc_newworld.c | 34 ++-- hw/ppc_oldworld.c | 27 ++-- hw/ppc_prep.c |2 +- hw/ppce500_pci.c |7 +- hw/prep_pci.c |8 +- hw/prep_pci.h |4 +- hw/qxl-render.c|2 +- hw/qxl.c | 129 ++-- hw/qxl.h |6 +- hw/rtl8139.c | 70 hw/sh_pci.c|4 +- hw/sun4u.c | 53 +++ hw/unin_pci.c | 16 ++- hw/usb-ehci.c | 36 +--- hw/usb-ohci.c |2 +- hw/usb-uhci.c | 41 +++-- hw/versatile_pci.c |2 +- hw/vga-isa-mm.c| 45 -- hw/vga-isa.c | 11 +- hw/vga-pci.c | 27 +--- hw/vga.c | 179 - hw/vga_int.h | 18 +-- hw/virtio-pci.c| 89 +-- hw/virtio-pci.h|3 +- hw/vmware_vga.c| 153
[Qemu-devel] [PATCH 08/39] cirrus: simplify linear framebuffer access functions
Make use of the memory API's ability to satisfy multi-byte accesses via
multiple single-byte accesses.
Signed-off-by: Avi Kivity
---
hw/cirrus_vga.c | 74 ++-
1 files changed, 8 insertions(+), 66 deletions(-)
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index 3db15bf..15ccf4a 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -2249,7 +2249,8 @@ static void cirrus_cursor_draw_line(VGACommonState *s1,
uint8_t *d1, int scr_y)
*
***/
-static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t cirrus_linear_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
CirrusVGAState *s = opaque;
uint32_t ret;
@@ -2277,28 +2278,8 @@ static uint32_t cirrus_linear_readb(void *opaque,
target_phys_addr_t addr)
return ret;
}
-static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
-{
-uint32_t v;
-
-v = cirrus_linear_readb(opaque, addr);
-v |= cirrus_linear_readb(opaque, addr + 1) << 8;
-return v;
-}
-
-static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
-{
-uint32_t v;
-
-v = cirrus_linear_readb(opaque, addr);
-v |= cirrus_linear_readb(opaque, addr + 1) << 8;
-v |= cirrus_linear_readb(opaque, addr + 2) << 16;
-v |= cirrus_linear_readb(opaque, addr + 3) << 24;
-return v;
-}
-
-static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
-uint32_t val)
+static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,
+uint64_t val, unsigned size)
{
CirrusVGAState *s = opaque;
unsigned mode;
@@ -2338,49 +2319,6 @@ static void cirrus_linear_writeb(void *opaque,
target_phys_addr_t addr,
}
}
-static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
-uint32_t val)
-{
-cirrus_linear_writeb(opaque, addr, val & 0xff);
-cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
-}
-
-static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
-uint32_t val)
-{
-cirrus_linear_writeb(opaque, addr, val & 0xff);
-cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
-cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
-cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
-}
-
-
-static uint64_t cirrus_linear_read(void *opaque, target_phys_addr_t addr,
- unsigned size)
-{
-CirrusVGAState *s = opaque;
-
-switch (size) {
-case 1: return cirrus_linear_readb(s, addr);
-case 2: return cirrus_linear_readw(s, addr);
-case 4: return cirrus_linear_readl(s, addr);
-default: abort();
-}
-}
-
-static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,
-uint64_t data, unsigned size)
-{
-CirrusVGAState *s = opaque;
-
-switch (size) {
-case 1: return cirrus_linear_writeb(s, addr, data);
-case 2: return cirrus_linear_writew(s, addr, data);
-case 4: return cirrus_linear_writel(s, addr, data);
-default: abort();
-}
-}
-
/***
*
* system to screen memory access
@@ -2860,6 +2798,10 @@ static const MemoryRegionOps cirrus_linear_io_ops = {
.read = cirrus_linear_read,
.write = cirrus_linear_write,
.endianness = DEVICE_LITTLE_ENDIAN,
+.impl = {
+.min_access_size = 1,
+.max_access_size = 1,
+},
};
static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
--
1.7.5.3
[Qemu-devel] [PATCH 33/39] msix: convert to memory API
The msix table is defined as a subregion, to allow for a BAR that
mixes device specific regions with the msix table.
Signed-off-by: Avi Kivity
---
hw/ivshmem.c| 11 +
hw/msix.c | 64 +++
hw/msix.h |6 +---
hw/pci.h|2 +-
hw/virtio-pci.c | 16 -
hw/virtio-pci.h |1 +
6 files changed, 42 insertions(+), 58 deletions(-)
diff --git a/hw/ivshmem.c b/hw/ivshmem.c
index f80e7b6..bacba60 100644
--- a/hw/ivshmem.c
+++ b/hw/ivshmem.c
@@ -65,6 +65,7 @@ typedef struct IVShmemState {
*/
MemoryRegion bar;
MemoryRegion ivshmem;
+MemoryRegion msix_bar;
uint64_t ivshmem_size; /* size of shared memory region */
int shm_fd; /* shared memory file descriptor */
@@ -540,11 +541,11 @@ static void ivshmem_setup_msi(IVShmemState * s) {
/* allocate the MSI-X vectors */
-if (!msix_init(&s->dev, s->vectors, 1, 0)) {
-pci_register_bar(&s->dev, 1,
- msix_bar_size(&s->dev),
- PCI_BASE_ADDRESS_SPACE_MEMORY,
- msix_mmio_map);
+memory_region_init(&s->msix_bar, "ivshmem-msix", 4096);
+if (!msix_init(&s->dev, s->vectors, &s->msix_bar, 1, 0)) {
+pci_register_bar_region(&s->dev, 1,
+PCI_BASE_ADDRESS_SPACE_MEMORY,
+&s->msix_bar);
IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors);
} else {
IVSHMEM_DPRINTF("msix initialization failed\n");
diff --git a/hw/msix.c b/hw/msix.c
index e67e700..8536c3f 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -82,7 +82,8 @@ static int msix_add_config(struct PCIDevice *pdev, unsigned
short nentries,
return 0;
}
-static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t msix_mmio_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
PCIDevice *dev = opaque;
unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
@@ -91,12 +92,6 @@ static uint32_t msix_mmio_readl(void *opaque,
target_phys_addr_t addr)
return pci_get_long(page + offset);
}
-static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
-{
-fprintf(stderr, "MSI-X: only dword read is allowed!\n");
-return 0;
-}
-
static uint8_t msix_pending_mask(int vector)
{
return 1 << (vector % 8);
@@ -169,8 +164,8 @@ void msix_write_config(PCIDevice *dev, uint32_t addr,
}
}
-static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
+uint64_t val, unsigned size)
{
PCIDevice *dev = opaque;
unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
@@ -179,37 +174,25 @@ static void msix_mmio_writel(void *opaque,
target_phys_addr_t addr,
msix_handle_mask_update(dev, vector);
}
-static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
-fprintf(stderr, "MSI-X: only dword write is allowed!\n");
-}
-
-static CPUWriteMemoryFunc * const msix_mmio_write[] = {
-msix_mmio_write_unallowed, msix_mmio_write_unallowed, msix_mmio_writel
-};
-
-static CPUReadMemoryFunc * const msix_mmio_read[] = {
-msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl
+static const MemoryRegionOps msix_mmio_ops = {
+.read = msix_mmio_read,
+.write = msix_mmio_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+.valid = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
};
-/* Should be called from device's map method. */
-void msix_mmio_map(PCIDevice *d, int region_num,
- pcibus_t addr, pcibus_t size, int type)
+static void msix_mmio_setup(PCIDevice *d, MemoryRegion *bar)
{
uint8_t *config = d->config + d->msix_cap;
uint32_t table = pci_get_long(config + PCI_MSIX_TABLE);
uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
/* TODO: for assigned devices, we'll want to make it possible to map
* pending bits separately in case they are in a separate bar. */
-int table_bir = table & PCI_MSIX_FLAGS_BIRMASK;
-if (table_bir != region_num)
-return;
-if (size <= offset)
-return;
-cpu_register_physical_memory(addr + offset, size - offset,
- d->msix_mmio_index);
+memory_region_add_subregion(bar, offset, &d->msix_mmio);
}
static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
@@ -225,6 +208,7 @@ static void msix_mask_all(struct PCIDevice *dev, unsigned
nentries)
/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
* modified, it should be retrieved with msix_bar_size. */
int msix_init(struct PCIDevice *dev, unsigned short nentries,
+ MemoryRegion *bar,
[Qemu-devel] [PATCH 37/39] pci: fold BAR mapping function into its caller
There is only one function, so no need for a function pointer.
Signed-off-by: Avi Kivity
---
hw/pci.c | 25 +
hw/pci.h |1 -
2 files changed, 9 insertions(+), 17 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index e9e4874..e6a759a 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -881,18 +881,6 @@ static int pci_unregister_device(DeviceState *dev)
return 0;
}
-static void pci_simple_bar_mapfunc_region(PCIDevice *pci_dev, int region_num,
- pcibus_t addr, pcibus_t size,
- int type)
-{
-PCIIORegion *r = &pci_dev->io_regions[region_num];
-
-memory_region_add_subregion_overlap(r->address_space,
-addr,
-r->memory,
-1);
-}
-
void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
uint8_t type, MemoryRegion *memory)
{
@@ -914,7 +902,6 @@ void pci_register_bar_region(PCIDevice *pci_dev, int
region_num,
r->size = size;
r->filtered_size = size;
r->type = type;
-r->map_func = pci_simple_bar_mapfunc_region;
r->memory = NULL;
wmask = ~(size - 1);
@@ -1102,10 +1089,16 @@ static void pci_update_mappings(PCIDevice *d)
* addr & (size - 1) != 0.
*/
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
-r->map_func(d, i, r->addr, r->filtered_size, r->type);
+memory_region_add_subregion_overlap(r->address_space,
+r->addr,
+r->memory,
+1);
} else {
-r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
-r->filtered_size, r->type);
+memory_region_add_subregion_overlap(r->address_space,
+pci_to_cpu_addr(d->bus,
+r->addr),
+r->memory,
+1);
}
}
}
diff --git a/hw/pci.h b/hw/pci.h
index 8028176..8d1662a 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -92,7 +92,6 @@ typedef struct PCIIORegion {
pcibus_t size;
pcibus_t filtered_size;
uint8_t type;
-PCIMapIORegionFunc *map_func;
MemoryRegion *memory;
MemoryRegion *address_space;
} PCIIORegion;
--
1.7.5.3
[Qemu-devel] [PATCH 24/39] ppc: convert to memory API
Signed-off-by: Avi Kivity
---
hw/cuda.c |6 ++-
hw/escc.c | 42 +--
hw/escc.h |2 +-
hw/heathrow_pic.c | 29 --
hw/ide.h |2 +-
hw/ide/macio.c| 36 ---
hw/mac_dbdma.c| 32 ++--
hw/mac_dbdma.h|4 ++-
hw/mac_nvram.c| 39 ++---
hw/macio.c| 74 +++-
hw/openpic.c | 81 +
hw/openpic.h |2 +-
hw/ppc_mac.h | 16 ++
hw/ppc_newworld.c | 30 +--
hw/ppc_oldworld.c | 23 +++
15 files changed, 201 insertions(+), 217 deletions(-)
diff --git a/hw/cuda.c b/hw/cuda.c
index 065c362..5c92d81 100644
--- a/hw/cuda.c
+++ b/hw/cuda.c
@@ -117,6 +117,7 @@ typedef struct CUDATimer {
} CUDATimer;
typedef struct CUDAState {
+MemoryRegion mem;
/* cuda registers */
uint8_t b; /* B-side data */
uint8_t a; /* A-side data */
@@ -722,7 +723,7 @@ static void cuda_reset(void *opaque)
set_counter(s, &s->timers[1], 0x);
}
-void cuda_init (int *cuda_mem_index, qemu_irq irq)
+void cuda_init (MemoryRegion **cuda_mem, qemu_irq irq)
{
struct tm tm;
CUDAState *s = &cuda_state;
@@ -738,8 +739,9 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq)
s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
s->adb_poll_timer = qemu_new_timer_ns(vm_clock, cuda_adb_poll, s);
-*cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s,
+cpu_register_io_memory(cuda_read, cuda_write, s,
DEVICE_NATIVE_ENDIAN);
+*cuda_mem = &s->mem;
vmstate_register(NULL, -1, &vmstate_cuda, s);
qemu_register_reset(cuda_reset, s);
}
diff --git a/hw/escc.c b/hw/escc.c
index f6fd919..bea5873 100644
--- a/hw/escc.c
+++ b/hw/escc.c
@@ -126,7 +126,7 @@ struct SerialState {
SysBusDevice busdev;
struct ChannelState chn[2];
uint32_t it_shift;
-int mmio_index;
+MemoryRegion mmio;
uint32_t disabled;
uint32_t frequency;
};
@@ -490,7 +490,8 @@ static void escc_update_parameters(ChannelState *s)
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
-static void escc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t
val)
+static void escc_mem_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
SerialState *serial = opaque;
ChannelState *s;
@@ -592,7 +593,8 @@ static void escc_mem_writeb(void *opaque,
target_phys_addr_t addr, uint32_t val)
}
}
-static uint32_t escc_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t escc_mem_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
SerialState *serial = opaque;
ChannelState *s;
@@ -627,6 +629,16 @@ static uint32_t escc_mem_readb(void *opaque,
target_phys_addr_t addr)
return 0;
}
+static const MemoryRegionOps escc_mem_ops = {
+.read = escc_mem_read,
+.write = escc_mem_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+.valid = {
+.min_access_size = 1,
+.max_access_size = 1,
+},
+};
+
static int serial_can_receive(void *opaque)
{
ChannelState *s = opaque;
@@ -668,18 +680,6 @@ static void serial_event(void *opaque, int event)
serial_receive_break(s);
}
-static CPUReadMemoryFunc * const escc_mem_read[3] = {
-escc_mem_readb,
-NULL,
-NULL,
-};
-
-static CPUWriteMemoryFunc * const escc_mem_write[3] = {
-escc_mem_writeb,
-NULL,
-NULL,
-};
-
static const VMStateDescription vmstate_escc_chn = {
.name ="escc_chn",
.version_id = 2,
@@ -712,7 +712,7 @@ static const VMStateDescription vmstate_escc = {
}
};
-int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
+MemoryRegion *escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift)
{
@@ -737,7 +737,7 @@ int escc_init(target_phys_addr_t base, qemu_irq irqA,
qemu_irq irqB,
}
d = FROM_SYSBUS(SerialState, s);
-return d->mmio_index;
+return &d->mmio;
}
static const uint8_t keycodes[128] = {
@@ -901,7 +901,6 @@ void slavio_serial_ms_kbd_init(target_phys_addr_t base,
qemu_irq irq,
static int escc_init1(SysBusDevice *dev)
{
SerialState *s = FROM_SYSBUS(SerialState, dev);
-int io;
unsigned int i;
s->chn[0].disabled = s->disabled;
@@ -918,10 +917,9 @@ static int escc_init1(SysBusDevice *dev)
s->chn[0].otherchn = &s->chn[1];
s->chn[1].otherchn = &s->chn[0];
-io = cpu_register_io_memory(escc_mem_read, escc_mem_write, s,
-DEVICE_NATIVE_ENDIAN);
-sysbus_init_mmio(dev, ESCC_SIZE << s->it_shift, io);
-s->mmio_index = io;
+memory_regio
[Qemu-devel] [PATCH 23/39] lsi53c895a: convert to memory API
An optimization that fast-pathed DMA reads from the SCRIPTS memory
was removed int the process. Likely it breaks with iommus anyway.
Signed-off-by: Avi Kivity
---
hw/lsi53c895a.c | 258 ---
1 files changed, 56 insertions(+), 202 deletions(-)
diff --git a/hw/lsi53c895a.c b/hw/lsi53c895a.c
index e9904c4..0ab8c78 100644
--- a/hw/lsi53c895a.c
+++ b/hw/lsi53c895a.c
@@ -185,9 +185,9 @@ typedef struct lsi_request {
typedef struct {
PCIDevice dev;
-int mmio_io_addr;
-int ram_io_addr;
-uint32_t script_ram_base;
+MemoryRegion mmio_io;
+MemoryRegion ram_io;
+MemoryRegion io_io;
int carry; /* ??? Should this be an a visible register somewhere? */
int status;
@@ -391,10 +391,9 @@ static inline uint32_t read_dword(LSIState *s, uint32_t
addr)
{
uint32_t buf;
-/* Optimize reading from SCRIPTS RAM. */
-if ((addr & 0xe000) == s->script_ram_base) {
-return s->script_ram[(addr & 0x1fff) >> 2];
-}
+/* XXX: an optimization here used to fast-path the read from scripts
+ * memory. But that bypasses any iommu.
+ */
cpu_physical_memory_read(addr, (uint8_t *)&buf, 4);
return cpu_to_le32(buf);
}
@@ -1899,232 +1898,90 @@ static void lsi_reg_writeb(LSIState *s, int offset,
uint8_t val)
#undef CASE_SET_REG32
}
-static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t
val)
+static void lsi_mmio_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
LSIState *s = opaque;
lsi_reg_writeb(s, addr & 0xff, val);
}
-static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t
val)
-{
-LSIState *s = opaque;
-
-addr &= 0xff;
-lsi_reg_writeb(s, addr, val & 0xff);
-lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
-}
-
-static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t
val)
-{
-LSIState *s = opaque;
-
-addr &= 0xff;
-lsi_reg_writeb(s, addr, val & 0xff);
-lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
-lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
-lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
-}
-
-static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t lsi_mmio_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
LSIState *s = opaque;
return lsi_reg_readb(s, addr & 0xff);
}
-static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr)
-{
-LSIState *s = opaque;
-uint32_t val;
-
-addr &= 0xff;
-val = lsi_reg_readb(s, addr);
-val |= lsi_reg_readb(s, addr + 1) << 8;
-return val;
-}
-
-static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr)
-{
-LSIState *s = opaque;
-uint32_t val;
-addr &= 0xff;
-val = lsi_reg_readb(s, addr);
-val |= lsi_reg_readb(s, addr + 1) << 8;
-val |= lsi_reg_readb(s, addr + 2) << 16;
-val |= lsi_reg_readb(s, addr + 3) << 24;
-return val;
-}
-
-static CPUReadMemoryFunc * const lsi_mmio_readfn[3] = {
-lsi_mmio_readb,
-lsi_mmio_readw,
-lsi_mmio_readl,
-};
-
-static CPUWriteMemoryFunc * const lsi_mmio_writefn[3] = {
-lsi_mmio_writeb,
-lsi_mmio_writew,
-lsi_mmio_writel,
+static const MemoryRegionOps lsi_mmio_ops = {
+.read = lsi_mmio_read,
+.write = lsi_mmio_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+.impl = {
+.min_access_size = 1,
+.max_access_size = 1,
+},
};
-static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void lsi_ram_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
LSIState *s = opaque;
uint32_t newval;
+uint32_t mask;
int shift;
-addr &= 0x1fff;
newval = s->script_ram[addr >> 2];
shift = (addr & 3) * 8;
-newval &= ~(0xff << shift);
+mask = ((uint64_t)1 << (size * 8)) - 1;
+newval &= ~(mask << shift);
newval |= val << shift;
s->script_ram[addr >> 2] = newval;
}
-static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-LSIState *s = opaque;
-uint32_t newval;
-
-addr &= 0x1fff;
-newval = s->script_ram[addr >> 2];
-if (addr & 2) {
-newval = (newval & 0x) | (val << 16);
-} else {
-newval = (newval & 0x) | val;
-}
-s->script_ram[addr >> 2] = newval;
-}
-
-
-static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-LSIState *s = opaque;
-
-addr &= 0x1fff;
-s->script_ram[addr >> 2] = val;
-}
-
-static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t lsi_ram_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
LSIState *s = opaque;
uint32_t val;
+uint32_t mask;
-addr &= 0x1fff;
val = s->script_ram[addr >> 2];
+
[Qemu-devel] [PATCH 25/39] ne2000: convert to memory API
Signed-off-by: Avi Kivity
---
hw/ne2000-isa.c | 14 +++---
hw/ne2000.c | 77 +-
hw/ne2000.h |8 +
3 files changed, 59 insertions(+), 40 deletions(-)
diff --git a/hw/ne2000-isa.c b/hw/ne2000-isa.c
index e41dbba..ce7b365 100644
--- a/hw/ne2000-isa.c
+++ b/hw/ne2000-isa.c
@@ -61,24 +61,18 @@ static const VMStateDescription vmstate_isa_ne2000 = {
}
};
+#include "exec-memory.h"
+
static int isa_ne2000_initfn(ISADevice *dev)
{
ISANE2000State *isa = DO_UPCAST(ISANE2000State, dev, dev);
NE2000State *s = &isa->ne2000;
-register_ioport_write(isa->iobase, 16, 1, ne2000_ioport_write, s);
-register_ioport_read(isa->iobase, 16, 1, ne2000_ioport_read, s);
+ne2000_setup_io(s, 0x20);
isa_init_ioport_range(dev, isa->iobase, 16);
-
-register_ioport_write(isa->iobase + 0x10, 1, 1, ne2000_asic_ioport_write,
s);
-register_ioport_read(isa->iobase + 0x10, 1, 1, ne2000_asic_ioport_read, s);
-register_ioport_write(isa->iobase + 0x10, 2, 2, ne2000_asic_ioport_write,
s);
-register_ioport_read(isa->iobase + 0x10, 2, 2, ne2000_asic_ioport_read, s);
isa_init_ioport_range(dev, isa->iobase + 0x10, 2);
-
-register_ioport_write(isa->iobase + 0x1f, 1, 1, ne2000_reset_ioport_write,
s);
-register_ioport_read(isa->iobase + 0x1f, 1, 1, ne2000_reset_ioport_read,
s);
isa_init_ioport(dev, isa->iobase + 0x1f);
+memory_region_add_subregion(get_system_io(), isa->iobase, &s->io);
isa_init_irq(dev, &s->irq, isa->isairq);
diff --git a/hw/ne2000.c b/hw/ne2000.c
index f8acaae..5b76acf 100644
--- a/hw/ne2000.c
+++ b/hw/ne2000.c
@@ -297,7 +297,7 @@ ssize_t ne2000_receive(VLANClientState *nc, const uint8_t
*buf, size_t size_)
return size_;
}
-void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
+static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
NE2000State *s = opaque;
int offset, page, index;
@@ -394,7 +394,7 @@ void ne2000_ioport_write(void *opaque, uint32_t addr,
uint32_t val)
}
}
-uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
+static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
{
NE2000State *s = opaque;
int offset, page, ret;
@@ -544,7 +544,7 @@ static inline void ne2000_dma_update(NE2000State *s, int
len)
}
}
-void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
+static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
NE2000State *s = opaque;
@@ -564,7 +564,7 @@ void ne2000_asic_ioport_write(void *opaque, uint32_t addr,
uint32_t val)
}
}
-uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
+static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
{
NE2000State *s = opaque;
int ret;
@@ -612,12 +612,12 @@ static uint32_t ne2000_asic_ioport_readl(void *opaque,
uint32_t addr)
return ret;
}
-void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
+static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t
val)
{
/* nothing to do (end of reset pulse) */
}
-uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
+static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
{
NE2000State *s = opaque;
ne2000_reset(s);
@@ -676,27 +676,55 @@ static const VMStateDescription vmstate_pci_ne2000 = {
}
};
-/***/
-/* PCI NE2000 definitions */
+static uint64_t ne2000_read(void *opaque, target_phys_addr_t addr,
+unsigned size)
+{
+NE2000State *s = opaque;
-static void ne2000_map(PCIDevice *pci_dev, int region_num,
- pcibus_t addr, pcibus_t size, int type)
+if (addr < 0x10 && size == 1) {
+return ne2000_ioport_read(s, addr);
+} else if (addr == 0x10) {
+if (size <= 2) {
+return ne2000_asic_ioport_read(s, addr);
+} else {
+return ne2000_asic_ioport_readl(s, addr);
+}
+} else if (addr == 0x1f && size == 1) {
+return ne2000_reset_ioport_read(s, addr);
+}
+return ((uint64_t)1 << (size * 8)) - 1;
+}
+
+static void ne2000_write(void *opaque, target_phys_addr_t addr,
+ uint64_t data, unsigned size)
{
-PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
-NE2000State *s = &d->ne2000;
+NE2000State *s = opaque;
+
+if (addr < 0x10 && size == 1) {
+return ne2000_ioport_write(s, addr, data);
+} else if (addr == 0x10) {
+if (size <= 2) {
+return ne2000_asic_ioport_write(s, addr, data);
+} else {
+return ne2000_asic_ioport_writel(s, addr, data);
+}
+} else if (addr == 0x1f && size == 1) {
+return ne2000_reset_ioport_write(s, addr, data);
+}
+}
-register_ioport_write(addr, 16, 1, ne2000_ioport_write, s);
-
[Qemu-devel] [PATCH 36/39] pci: remove pci_register_bar()
Superceded by pci_register_bar_region(). The implementations
are folded together.
Signed-off-by: Avi Kivity
---
hw/pci.c | 42 +-
hw/pci.h |3 ---
2 files changed, 17 insertions(+), 28 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 481eb7e..e9e4874 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -881,13 +881,25 @@ static int pci_unregister_device(DeviceState *dev)
return 0;
}
-void pci_register_bar(PCIDevice *pci_dev, int region_num,
-pcibus_t size, uint8_t type,
-PCIMapIORegionFunc *map_func)
+static void pci_simple_bar_mapfunc_region(PCIDevice *pci_dev, int region_num,
+ pcibus_t addr, pcibus_t size,
+ int type)
+{
+PCIIORegion *r = &pci_dev->io_regions[region_num];
+
+memory_region_add_subregion_overlap(r->address_space,
+addr,
+r->memory,
+1);
+}
+
+void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
+ uint8_t type, MemoryRegion *memory)
{
PCIIORegion *r;
uint32_t addr;
uint64_t wmask;
+pcibus_t size = memory_region_size(memory);
assert(region_num >= 0);
assert(region_num < PCI_NUM_REGIONS);
@@ -902,7 +914,7 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
r->size = size;
r->filtered_size = size;
r->type = type;
-r->map_func = map_func;
+r->map_func = pci_simple_bar_mapfunc_region;
r->memory = NULL;
wmask = ~(size - 1);
@@ -920,29 +932,9 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
pci_set_long(pci_dev->wmask + addr, wmask & 0x);
pci_set_long(pci_dev->cmask + addr, 0x);
}
-}
-
-static void pci_simple_bar_mapfunc_region(PCIDevice *pci_dev, int region_num,
- pcibus_t addr, pcibus_t size,
- int type)
-{
-PCIIORegion *r = &pci_dev->io_regions[region_num];
-
-memory_region_add_subregion_overlap(r->address_space,
-addr,
-r->memory,
-1);
-}
-
-void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
- uint8_t attr, MemoryRegion *memory)
-{
-pci_register_bar(pci_dev, region_num, memory_region_size(memory),
- attr,
- pci_simple_bar_mapfunc_region);
pci_dev->io_regions[region_num].memory = memory;
pci_dev->io_regions[region_num].address_space
-= attr & PCI_BASE_ADDRESS_SPACE_IO
+= type & PCI_BASE_ADDRESS_SPACE_IO
? pci_dev->bus->address_space_io
: pci_dev->bus->address_space_mem;
}
diff --git a/hw/pci.h b/hw/pci.h
index 6e2bcea..8028176 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -201,9 +201,6 @@ PCIDevice *pci_register_device(PCIBus *bus, const char
*name,
PCIConfigReadFunc *config_read,
PCIConfigWriteFunc *config_write);
-void pci_register_bar(PCIDevice *pci_dev, int region_num,
-pcibus_t size, uint8_t type,
-PCIMapIORegionFunc *map_func);
void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
uint8_t attr, MemoryRegion *memory);
pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
--
1.7.5.3
[Qemu-devel] [PATCH 12/39] pci: allow I/O BARs to be registered with pci_register_bar_region()
Signed-off-by: Avi Kivity
---
hw/pci.c | 43 +++
hw/pci.h |1 +
hw/pci_internals.h |3 ++-
3 files changed, 26 insertions(+), 21 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 2659d96..980840f 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -271,7 +271,8 @@ void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
assert(PCI_FUNC(devfn_min) == 0);
bus->devfn_min = devfn_min;
-bus->address_space = address_space_mem;
+bus->address_space_mem = address_space_mem;
+bus->address_space_io = address_space_io;
/* host bridge */
QLIST_INIT(&bus->child);
@@ -847,12 +848,11 @@ static void pci_unregister_io_regions(PCIDevice *pci_dev)
r = &pci_dev->io_regions[i];
if (!r->size || r->addr == PCI_BAR_UNMAPPED)
continue;
-if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
-isa_unassign_ioport(r->addr, r->filtered_size);
+if (r->memory) {
+memory_region_del_subregion(r->address_space, r->memory);
} else {
-if (r->memory) {
-memory_region_del_subregion(pci_dev->bus->address_space,
-r->memory);
+if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
+isa_unassign_ioport(r->addr, r->filtered_size);
} else {
cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
r->addr),
@@ -934,9 +934,11 @@ static void pci_simple_bar_mapfunc_region(PCIDevice
*pci_dev, int region_num,
pcibus_t addr, pcibus_t size,
int type)
{
-memory_region_add_subregion_overlap(pci_dev->bus->address_space,
+PCIIORegion *r = &pci_dev->io_regions[region_num];
+
+memory_region_add_subregion_overlap(r->address_space,
addr,
-pci_dev->io_regions[region_num].memory,
+r->memory,
1);
}
@@ -953,9 +955,13 @@ void pci_register_bar_region(PCIDevice *pci_dev, int
region_num,
uint8_t attr, MemoryRegion *memory)
{
pci_register_bar(pci_dev, region_num, memory_region_size(memory),
- PCI_BASE_ADDRESS_SPACE_MEMORY | attr,
+ attr,
pci_simple_bar_mapfunc_region);
pci_dev->io_regions[region_num].memory = memory;
+pci_dev->io_regions[region_num].address_space
+= attr & PCI_BASE_ADDRESS_SPACE_IO
+? pci_dev->bus->address_space_io
+: pci_dev->bus->address_space_mem;
}
pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
@@ -1090,7 +1096,9 @@ static void pci_update_mappings(PCIDevice *d)
/* now do the real mapping */
if (r->addr != PCI_BAR_UNMAPPED) {
-if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
+if (r->memory) {
+memory_region_del_subregion(r->address_space, r->memory);
+} else if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
int class;
/* NOTE: specific hack for IDE in PC case:
only one byte must be mapped. */
@@ -1101,16 +1109,11 @@ static void pci_update_mappings(PCIDevice *d)
isa_unassign_ioport(r->addr, r->filtered_size);
}
} else {
-if (r->memory) {
-memory_region_del_subregion(d->bus->address_space,
-r->memory);
-} else {
-cpu_register_physical_memory(pci_to_cpu_addr(d->bus,
- r->addr),
- r->filtered_size,
- IO_MEM_UNASSIGNED);
-qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
-}
+cpu_register_physical_memory(pci_to_cpu_addr(d->bus,
+ r->addr),
+ r->filtered_size,
+ IO_MEM_UNASSIGNED);
+qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
}
}
r->addr = new_addr;
diff --git a/hw/pci.h b/hw/pci.h
index 45b30fa..928e96c 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -95,6 +95,7 @@ typedef struct PCIIORegion {
PCIMapIORegionFunc *map_func;
ram_addr_t ram_addr;
MemoryRegion *memory;
+MemoryRegion *address_space;
} PCIIORegion;
#define PCI_ROM_SLOT 6
diff --git a/hw/pci_internals.h b/hw/pci_internals.h
index c3a463a..c7fd23d 100644
--- a/hw/pci_i
[Qemu-devel] [PATCH 39/39] pci: remove support for pre memory API BARs
Not used anymore.
Signed-off-by: Avi Kivity
---
hw/pci.c | 33 ++---
1 files changed, 2 insertions(+), 31 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 6ed08ae..e6a3e56 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -848,18 +848,7 @@ static void pci_unregister_io_regions(PCIDevice *pci_dev)
r = &pci_dev->io_regions[i];
if (!r->size || r->addr == PCI_BAR_UNMAPPED)
continue;
-if (r->memory) {
-memory_region_del_subregion(r->address_space, r->memory);
-} else {
-if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
-isa_unassign_ioport(r->addr, r->filtered_size);
-} else {
-cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
- r->addr),
- r->filtered_size,
- IO_MEM_UNASSIGNED);
-}
-}
+memory_region_del_subregion(r->address_space, r->memory);
}
}
@@ -1058,25 +1047,7 @@ static void pci_update_mappings(PCIDevice *d)
/* now do the real mapping */
if (r->addr != PCI_BAR_UNMAPPED) {
-if (r->memory) {
-memory_region_del_subregion(r->address_space, r->memory);
-} else if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
-int class;
-/* NOTE: specific hack for IDE in PC case:
- only one byte must be mapped. */
-class = pci_get_word(d->config + PCI_CLASS_DEVICE);
-if (class == 0x0101 && r->size == 4) {
-isa_unassign_ioport(r->addr + 2, 1);
-} else {
-isa_unassign_ioport(r->addr, r->filtered_size);
-}
-} else {
-cpu_register_physical_memory(pci_to_cpu_addr(d->bus,
- r->addr),
- r->filtered_size,
- IO_MEM_UNASSIGNED);
-qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
-}
+memory_region_del_subregion(r->address_space, r->memory);
}
r->addr = new_addr;
r->filtered_size = filtered_size;
--
1.7.5.3
[Qemu-devel] [PATCH 15/39] e1000: convert to memory API
Signed-off-by: Avi Kivity
---
hw/e1000.c | 114 +--
1 files changed, 48 insertions(+), 66 deletions(-)
diff --git a/hw/e1000.c b/hw/e1000.c
index 96d84f9..dfc082b 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -82,7 +82,8 @@ typedef struct E1000State_st {
PCIDevice dev;
NICState *nic;
NICConf conf;
-int mmio_index;
+MemoryRegion mmio;
+MemoryRegion io;
uint32_t mac_reg[0x8000];
uint16_t phy_reg[0x20];
@@ -151,14 +152,6 @@ static const char phy_regcap[0x20] = {
};
static void
-ioport_map(PCIDevice *pci_dev, int region_num, pcibus_t addr,
- pcibus_t size, int type)
-{
-DBGOUT(IO, "e1000_ioport_map addr=0x%04"FMT_PCIBUS
- " size=0x%08"FMT_PCIBUS"\n", addr, size);
-}
-
-static void
set_interrupt_cause(E1000State *s, int index, uint32_t val)
{
if (val)
@@ -905,7 +898,8 @@ static void (*macreg_writeops[])(E1000State *, int,
uint32_t) = {
enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
static void
-e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
+ unsigned size)
{
E1000State *s = opaque;
unsigned int index = (addr & 0x1) >> 2;
@@ -913,31 +907,15 @@ e1000_mmio_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
if (index < NWRITEOPS && macreg_writeops[index]) {
macreg_writeops[index](s, index, val);
} else if (index < NREADOPS && macreg_readops[index]) {
-DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val);
+DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n", index<<2,
val);
} else {
-DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08x\n",
+DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n",
index<<2, val);
}
}
-static void
-e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-// emulate hw without byte enables: no RMW
-e1000_mmio_writel(opaque, addr & ~3,
- (val & 0x) << (8*(addr & 3)));
-}
-
-static void
-e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-// emulate hw without byte enables: no RMW
-e1000_mmio_writel(opaque, addr & ~3,
- (val & 0xff) << (8*(addr & 3)));
-}
-
-static uint32_t
-e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t
+e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
E1000State *s = opaque;
unsigned int index = (addr & 0x1) >> 2;
@@ -950,20 +928,39 @@ e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
return 0;
}
-static uint32_t
-e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
+static const MemoryRegionOps e1000_mmio_ops = {
+.read = e1000_mmio_read,
+.write = e1000_mmio_write,
+.endianness = DEVICE_LITTLE_ENDIAN,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+};
+
+static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
-return ((e1000_mmio_readl(opaque, addr & ~3)) >>
-(8 * (addr & 3))) & 0xff;
+E1000State *s = opaque;
+
+(void)s;
+return 0;
}
-static uint32_t
-e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
+static void e1000_io_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
-return ((e1000_mmio_readl(opaque, addr & ~3)) >>
-(8 * (addr & 3))) & 0x;
+E1000State *s = opaque;
+
+(void)s;
}
+static const MemoryRegionOps e1000_io_ops = {
+.read = e1000_io_read,
+.write = e1000_io_write,
+.endianness = DEVICE_LITTLE_ENDIAN,
+};
+
static bool is_version_1(void *opaque, int version_id)
{
return version_id == 1;
@@ -1083,36 +1080,22 @@ static const uint32_t mac_reg_init[] = {
/* PCI interface */
-static CPUWriteMemoryFunc * const e1000_mmio_write[] = {
-e1000_mmio_writeb, e1000_mmio_writew, e1000_mmio_writel
-};
-
-static CPUReadMemoryFunc * const e1000_mmio_read[] = {
-e1000_mmio_readb, e1000_mmio_readw, e1000_mmio_readl
-};
-
static void
-e1000_mmio_map(PCIDevice *pci_dev, int region_num,
-pcibus_t addr, pcibus_t size, int type)
+e1000_mmio_setup(E1000State *d)
{
-E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
int i;
const uint32_t excluded_regs[] = {
E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
};
-
-DBGOUT(MMIO, "e1000_mmio_map addr=0x%08"FMT_PCIBUS" 0x%08"FMT_PCIBUS"\n",
- addr, size);
-
-cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
-qemu_register_coalesced_mmio(addr, excluded_regs[0]);
-
+memory_region_init_io(&d->mmio, &e1000_mmio_ops, d, "e1000-mmio",
+ P
[Qemu-devel] [PATCH 32/39] xen-platform: convert to memory API
Since this device bypasses PCI and registers I/O ports directly with
the system bus, it needs further attention.
Signed-off-by: Avi Kivity
---
hw/xen_platform.c | 84 -
1 files changed, 51 insertions(+), 33 deletions(-)
diff --git a/hw/xen_platform.c b/hw/xen_platform.c
index fb6be6a..239eefe 100644
--- a/hw/xen_platform.c
+++ b/hw/xen_platform.c
@@ -32,7 +32,6 @@
#include "xen_common.h"
#include "net.h"
#include "xen_backend.h"
-#include "rwhandler.h"
#include "trace.h"
#include
@@ -51,6 +50,9 @@
typedef struct PCIXenPlatformState {
PCIDevice pci_dev;
+MemoryRegion fixed_io;
+MemoryRegion bar;
+MemoryRegion mmio_bar;
uint8_t flags; /* used only for version_id == 2 */
int drivers_blacklisted;
uint16_t driver_product_version;
@@ -221,21 +223,34 @@ static void platform_fixed_ioport_reset(void *opaque)
platform_fixed_ioport_writeb(s, XEN_PLATFORM_IOPORT, 0);
}
+const MemoryRegionPortio xen_platform_ioport[] = {
+{ 0, 16, 4, .write = platform_fixed_ioport_writel, },
+{ 0, 16, 2, .write = platform_fixed_ioport_writew, },
+{ 0, 16, 1, .write = platform_fixed_ioport_writeb, },
+{ 0, 16, 2, .read = platform_fixed_ioport_readw, },
+{ 0, 16, 1, .read = platform_fixed_ioport_readb, },
+PORTIO_END
+};
+
+static const MemoryRegionOps platform_fixed_io_ops = {
+.old_portio = xen_platform_ioport,
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+#include "exec-memory.h"
+
static void platform_fixed_ioport_init(PCIXenPlatformState* s)
{
-register_ioport_write(XEN_PLATFORM_IOPORT, 16, 4,
platform_fixed_ioport_writel, s);
-register_ioport_write(XEN_PLATFORM_IOPORT, 16, 2,
platform_fixed_ioport_writew, s);
-register_ioport_write(XEN_PLATFORM_IOPORT, 16, 1,
platform_fixed_ioport_writeb, s);
-register_ioport_read(XEN_PLATFORM_IOPORT, 16, 2,
platform_fixed_ioport_readw, s);
-register_ioport_read(XEN_PLATFORM_IOPORT, 16, 1,
platform_fixed_ioport_readb, s);
+memory_region_init_io(&s->fixed_io, &platform_fixed_io_ops, s,
+ "xen-fixed", 16);
+memory_region_add_subregion(get_system_io(), XEN_PLATFORM_IOPORT,
+&s->fixed_io);
}
/* Xen Platform PCI Device */
static uint32_t xen_platform_ioport_readb(void *opaque, uint32_t addr)
{
-addr &= 0xff;
-
if (addr == 0) {
return platform_fixed_ioport_readb(opaque, XEN_PLATFORM_IOPORT);
} else {
@@ -247,9 +262,6 @@ static void xen_platform_ioport_writeb(void *opaque,
uint32_t addr, uint32_t val
{
PCIXenPlatformState *s = opaque;
-addr &= 0xff;
-val &= 0xff;
-
switch (addr) {
case 0: /* Platform flags */
platform_fixed_ioport_writeb(opaque, XEN_PLATFORM_IOPORT, val);
@@ -262,15 +274,23 @@ static void xen_platform_ioport_writeb(void *opaque,
uint32_t addr, uint32_t val
}
}
-static void platform_ioport_map(PCIDevice *pci_dev, int region_num, pcibus_t
addr, pcibus_t size, int type)
-{
-PCIXenPlatformState *d = DO_UPCAST(PCIXenPlatformState, pci_dev, pci_dev);
+static MemoryRegionPortio xen_pci_portio[] = {
+{ 0, 0x100, 1, .read = xen_platform_ioport_readb, },
+{ 0, 0x100, 1, .write = xen_platform_ioport_writeb, },
+PORTIO_END
+};
+
+static const MemoryRegionOps xen_pci_io_ops = {
+.old_portio = xen_pci_portio,
+};
-register_ioport_write(addr, size, 1, xen_platform_ioport_writeb, d);
-register_ioport_read(addr, size, 1, xen_platform_ioport_readb, d);
+static void platform_ioport_bar_setup(PCIXenPlatformState *d)
+{
+memory_region_init_io(&d->bar, &xen_pci_io_ops, d, "xen-pci", 0x100);
}
-static uint32_t platform_mmio_read(ReadWriteHandler *handler, pcibus_t addr,
int len)
+static uint64_t platform_mmio_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
DPRINTF("Warning: attempted read from physical address "
"0x" TARGET_FMT_plx " in xen platform mmio space\n", addr);
@@ -278,28 +298,24 @@ static uint32_t platform_mmio_read(ReadWriteHandler
*handler, pcibus_t addr, int
return 0;
}
-static void platform_mmio_write(ReadWriteHandler *handler, pcibus_t addr,
-uint32_t val, int len)
+static void platform_mmio_write(void *opaque, target_phys_addr_t addr,
+uint64_t val, unsigned size)
{
-DPRINTF("Warning: attempted write of 0x%x to physical "
+DPRINTF("Warning: attempted write of 0x%"PRIx64" to physical "
"address 0x" TARGET_FMT_plx " in xen platform mmio space\n",
val, addr);
}
-static ReadWriteHandler platform_mmio_handler = {
+static const MemoryRegionOps platform_mmio_handler = {
.read = &platform_mmio_read,
.write = &platform_mmio_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void platform_mmio_map(PCIDevice *d, int region_num,
- pcibus_t
[Qemu-devel] [PATCH 09/39] Integrate I/O memory regions into qemu
get_system_io() returns the root I/O memory region.
Signed-off-by: Avi Kivity
---
exec-memory.h |2 ++
exec.c| 10 ++
2 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/exec-memory.h b/exec-memory.h
index c439aba..999fd69 100644
--- a/exec-memory.h
+++ b/exec-memory.h
@@ -28,6 +28,8 @@
*/
MemoryRegion *get_system_memory(void);
+MemoryRegion *get_system_io(void);
+
/* Set the root memory region. This region is the system memory map. */
void set_system_memory_map(MemoryRegion *mr);
diff --git a/exec.c b/exec.c
index 476b507..2fd4adb 100644
--- a/exec.c
+++ b/exec.c
@@ -113,6 +113,7 @@ static int in_migration;
RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list) };
static MemoryRegion *system_memory;
+static MemoryRegion *system_io;
#endif
@@ -3820,6 +3821,10 @@ static void memory_map_init(void)
system_memory = qemu_malloc(sizeof(*system_memory));
memory_region_init(system_memory, "system", UINT64_MAX);
set_system_memory_map(system_memory);
+
+system_io = qemu_malloc(sizeof(*system_io));
+memory_region_init(system_memory, "io", 65536);
+set_system_io_map(system_io);
}
MemoryRegion *get_system_memory(void)
@@ -3827,6 +3832,11 @@ MemoryRegion *get_system_memory(void)
return system_memory;
}
+MemoryRegion *get_system_io(void)
+{
+return system_io;
+}
+
#endif /* !defined(CONFIG_USER_ONLY) */
/* physical memory access (slow version, mainly for debug) */
--
1.7.5.3
[Qemu-devel] [PATCH 14/39] ac97: convert to memory API
fixes BAR sizing as well.
Signed-off-by: Avi Kivity
---
hw/ac97.c | 88 +++-
1 files changed, 51 insertions(+), 37 deletions(-)
diff --git a/hw/ac97.c b/hw/ac97.c
index 0b59896..bcddaa6 100644
--- a/hw/ac97.c
+++ b/hw/ac97.c
@@ -160,8 +160,9 @@ typedef struct AC97LinkState {
SWVoiceIn *voice_mc;
int invalid_freq[3];
uint8_t silence[128];
-uint32_t base[2];
int bup_flag;
+MemoryRegion io_nam;
+MemoryRegion io_nabm;
} AC97LinkState;
enum {
@@ -583,7 +584,7 @@ static uint32_t nam_readw (void *opaque, uint32_t addr)
{
AC97LinkState *s = opaque;
uint32_t val = ~0U;
-uint32_t index = addr - s->base[0];
+uint32_t index = addr;
s->cas = 0;
val = mixer_load (s, index);
return val;
@@ -611,7 +612,7 @@ static void nam_writeb (void *opaque, uint32_t addr,
uint32_t val)
static void nam_writew (void *opaque, uint32_t addr, uint32_t val)
{
AC97LinkState *s = opaque;
-uint32_t index = addr - s->base[0];
+uint32_t index = addr;
s->cas = 0;
switch (index) {
case AC97_Reset:
@@ -714,7 +715,7 @@ static uint32_t nabm_readb (void *opaque, uint32_t addr)
{
AC97LinkState *s = opaque;
AC97BusMasterRegs *r = NULL;
-uint32_t index = addr - s->base[1];
+uint32_t index = addr;
uint32_t val = ~0U;
switch (index) {
@@ -769,7 +770,7 @@ static uint32_t nabm_readw (void *opaque, uint32_t addr)
{
AC97LinkState *s = opaque;
AC97BusMasterRegs *r = NULL;
-uint32_t index = addr - s->base[1];
+uint32_t index = addr;
uint32_t val = ~0U;
switch (index) {
@@ -798,7 +799,7 @@ static uint32_t nabm_readl (void *opaque, uint32_t addr)
{
AC97LinkState *s = opaque;
AC97BusMasterRegs *r = NULL;
-uint32_t index = addr - s->base[1];
+uint32_t index = addr;
uint32_t val = ~0U;
switch (index) {
@@ -848,7 +849,7 @@ static void nabm_writeb (void *opaque, uint32_t addr,
uint32_t val)
{
AC97LinkState *s = opaque;
AC97BusMasterRegs *r = NULL;
-uint32_t index = addr - s->base[1];
+uint32_t index = addr;
switch (index) {
case PI_LVI:
case PO_LVI:
@@ -904,7 +905,7 @@ static void nabm_writew (void *opaque, uint32_t addr,
uint32_t val)
{
AC97LinkState *s = opaque;
AC97BusMasterRegs *r = NULL;
-uint32_t index = addr - s->base[1];
+uint32_t index = addr;
switch (index) {
case PI_SR:
case PO_SR:
@@ -924,7 +925,7 @@ static void nabm_writel (void *opaque, uint32_t addr,
uint32_t val)
{
AC97LinkState *s = opaque;
AC97BusMasterRegs *r = NULL;
-uint32_t index = addr - s->base[1];
+uint32_t index = addr;
switch (index) {
case PI_BDBAR:
case PO_BDBAR:
@@ -1230,31 +1231,33 @@ static const VMStateDescription vmstate_ac97 = {
}
};
-static void ac97_map (PCIDevice *pci_dev, int region_num,
- pcibus_t addr, pcibus_t size, int type)
-{
-AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, pci_dev);
-PCIDevice *d = &s->dev;
-
-if (!region_num) {
-s->base[0] = addr;
-register_ioport_read (addr, 256 * 1, 1, nam_readb, d);
-register_ioport_read (addr, 256 * 2, 2, nam_readw, d);
-register_ioport_read (addr, 256 * 4, 4, nam_readl, d);
-register_ioport_write (addr, 256 * 1, 1, nam_writeb, d);
-register_ioport_write (addr, 256 * 2, 2, nam_writew, d);
-register_ioport_write (addr, 256 * 4, 4, nam_writel, d);
-}
-else {
-s->base[1] = addr;
-register_ioport_read (addr, 64 * 1, 1, nabm_readb, d);
-register_ioport_read (addr, 64 * 2, 2, nabm_readw, d);
-register_ioport_read (addr, 64 * 4, 4, nabm_readl, d);
-register_ioport_write (addr, 64 * 1, 1, nabm_writeb, d);
-register_ioport_write (addr, 64 * 2, 2, nabm_writew, d);
-register_ioport_write (addr, 64 * 4, 4, nabm_writel, d);
-}
-}
+static const MemoryRegionPortio nam_portio[] = {
+{ 0, 256 * 1, 1, .read = nam_readb, },
+{ 0, 256 * 2, 2, .read = nam_readw, },
+{ 0, 256 * 4, 4, .read = nam_readl, },
+{ 0, 256 * 1, 1, .write = nam_writeb, },
+{ 0, 256 * 2, 2, .write = nam_writew, },
+{ 0, 256 * 4, 4, .write = nam_writel, },
+PORTIO_END,
+};
+
+static const MemoryRegionOps ac97_io_nam_ops = {
+.old_portio = nam_portio,
+};
+
+static const MemoryRegionPortio nabm_portio[] = {
+{ 0, 64 * 1, 1, .read = nabm_readb, },
+{ 0, 64 * 2, 2, .read = nabm_readw, },
+{ 0, 64 * 4, 4, .read = nabm_readl, },
+{ 0, 64 * 1, 1, .write = nabm_writeb, },
+{ 0, 64 * 2, 2, .write = nabm_writew, },
+{ 0, 64 * 4, 4, .write = nabm_writel, },
+PORTIO_END
+};
+
+static const MemoryRegionOps ac97_io_nabm_ops = {
+.old_portio = nabm_portio,
+};
static void ac97_on_reset (void *opaque)
{
@@ -1311,15 +1314,25 @@ static int ac97_initfn (PCIDevice *dev)
/* TODO: RST# value should be 0. */
c[P
[Qemu-devel] [PATCH 06/39] cirrus: simplify vga window mmio access functions
Make use of the memory API's ability to satisfy multi-byte accesses via
multiple single-byte accesses.
Signed-off-by: Avi Kivity
---
hw/cirrus_vga.c | 79 +++---
1 files changed, 11 insertions(+), 68 deletions(-)
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index b8a51b4..92696d9 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -1955,7 +1955,9 @@ static void
cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
*
***/
-static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t cirrus_vga_mem_read(void *opaque,
+target_phys_addr_t addr,
+uint32_t size)
{
CirrusVGAState *s = opaque;
unsigned bank_index;
@@ -1966,8 +1968,6 @@ static uint32_t cirrus_vga_mem_readb(void *opaque,
target_phys_addr_t addr)
return vga_mem_readb(s, addr);
}
-addr &= 0x1;
-
if (addr < 0x1) {
/* XXX handle bitblt */
/* video memory */
@@ -1999,28 +1999,10 @@ static uint32_t cirrus_vga_mem_readb(void *opaque,
target_phys_addr_t addr)
return val;
}
-static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
-{
-uint32_t v;
-
-v = cirrus_vga_mem_readb(opaque, addr);
-v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
-return v;
-}
-
-static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
-{
-uint32_t v;
-
-v = cirrus_vga_mem_readb(opaque, addr);
-v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
-v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
-v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
-return v;
-}
-
-static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
- uint32_t mem_value)
+static void cirrus_vga_mem_write(void *opaque,
+ target_phys_addr_t addr,
+ uint64_t mem_value,
+ uint32_t size)
{
CirrusVGAState *s = opaque;
unsigned bank_index;
@@ -2032,8 +2014,6 @@ static void cirrus_vga_mem_writeb(void *opaque,
target_phys_addr_t addr,
return;
}
-addr &= 0x1;
-
if (addr < 0x1) {
if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
/* bitblt */
@@ -2083,51 +2063,14 @@ static void cirrus_vga_mem_writeb(void *opaque,
target_phys_addr_t addr,
}
}
-static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
-{
-cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
-cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
-}
-
-static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
-{
-cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
-cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
-cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
-cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
-}
-
-static uint64_t cirrus_vga_mem_read(void *opaque,
-target_phys_addr_t addr,
-uint32_t size)
-{
-CirrusVGAState *s = opaque;
-
-switch (size) {
-case 1: return cirrus_vga_mem_readb(s, addr);
-case 2: return cirrus_vga_mem_readw(s, addr);
-case 4: return cirrus_vga_mem_readl(s, addr);
-default: abort();
-}
-}
-
-static void cirrus_vga_mem_write(void *opaque, target_phys_addr_t addr,
- uint64_t data, unsigned size)
-{
-CirrusVGAState *s = opaque;
-
-switch (size) {
-case 1: return cirrus_vga_mem_writeb(s, addr, data);
-case 2: return cirrus_vga_mem_writew(s, addr, data);
-case 4: return cirrus_vga_mem_writel(s, addr, data);
-default: abort();
-}
-};
-
static const MemoryRegionOps cirrus_vga_mem_ops = {
.read = cirrus_vga_mem_read,
.write = cirrus_vga_mem_write,
.endianness = DEVICE_LITTLE_ENDIAN,
+.impl = {
+.min_access_size = 1,
+.max_access_size = 1,
+},
};
/***
--
1.7.5.3
Re: [Qemu-devel] [PATCH v3 0/2] The intro for QEMU disk I/O limits
* Zhi Yong Wu [2011-07-28 05:53]: > The main goal of the patch is to effectively cap the disk I/O speed or counts > of one single VM.It is only one draft, so it unavoidably has some drawbacks, > if you catch them, please let me know. > > The patch will mainly introduce one block I/O throttling algorithm, one timer > and one block queue for each I/O limits enabled drive. > > When a block request is coming in, the throttling algorithm will check if its > I/O rate or counts exceed the limits; if yes, then it will enqueue to the > block queue; The timer will periodically handle the I/O requests in it. > > Some available features follow as below: > (1) global bps limit. > -drive bps=xxxin bytes/s > (2) only read bps limit > -drive bps_rd=xxx in bytes/s > (3) only write bps limit > -drive bps_wr=xxx in bytes/s > (4) global iops limit > -drive iops=xxx in ios/s > (5) only read iops limit > -drive iops_rd=xxxin ios/s > (6) only write iops limit > -drive iops_wr=xxxin ios/s > (7) the combination of some limits. > -drive bps=xxx,iops=xxx > > Known Limitations: > (1) #1 can not coexist with #2, #3 > (2) #4 can not coexist with #5, #6 > (3) When bps/iops limits are specified to a small value such as 511 bytes/s, > this VM will hang up. We are considering how to handle this senario. > I don't yet have detailed info , but we've got a memory leak in the code. After running the VM with a 1MB r and w limit for 8 hours or so: -drive bps_rd=$((1*1024*1024)),bps_wr=$((1*1024*1024)) I've got my system swapping with 43G resident in memory: 9913 root 20 0 87.3g 43g 548 D 9.6 34.5 44:00.87 qemu-system-x86 would be worth looking through the code and maybe a valgrind run to catch the leak. -- Ryan Harper Software Engineer; Linux Technology Center IBM Corp., Austin, Tx ry...@us.ibm.com
Re: [Qemu-devel] [PATCH 03/39] vga: convert vga and its derivatives to the memory API
On 07/31/2011 09:48 PM, Jan Kiszka wrote: > > I haven't. How does "unconditionally dirty the remapped slot" sound? > > I think it isn't introduced by this patchset, yes? The patch removes the explicit sync from the cirrus code. But the underlying issue is older of course. Ah. So I'll detect that condition in memory.c; we get that bug fixed for all potential callers. I'll leave the race condition until later, since it wasn't introduced by this patchset. -- I have a truly marvellous patch that fixes the bug which this signature is too narrow to contain.
[Qemu-devel] [PATCH 34/39] pci: remove pci_register_bar_simple()
Superceded by pci_register_bar_region().
---
hw/pci.c | 17 -
hw/pci.h |3 ---
2 files changed, 0 insertions(+), 20 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 980840f..6aca1af 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -903,7 +903,6 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
r->filtered_size = size;
r->type = type;
r->map_func = map_func;
-r->ram_addr = IO_MEM_UNASSIGNED;
r->memory = NULL;
wmask = ~(size - 1);
@@ -923,13 +922,6 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
}
}
-static void pci_simple_bar_mapfunc(PCIDevice *pci_dev, int region_num,
- pcibus_t addr, pcibus_t size, int type)
-{
-cpu_register_physical_memory(addr, size,
- pci_dev->io_regions[region_num].ram_addr);
-}
-
static void pci_simple_bar_mapfunc_region(PCIDevice *pci_dev, int region_num,
pcibus_t addr, pcibus_t size,
int type)
@@ -942,15 +934,6 @@ static void pci_simple_bar_mapfunc_region(PCIDevice
*pci_dev, int region_num,
1);
}
-void pci_register_bar_simple(PCIDevice *pci_dev, int region_num,
- pcibus_t size, uint8_t attr, ram_addr_t ram_addr)
-{
-pci_register_bar(pci_dev, region_num, size,
- PCI_BASE_ADDRESS_SPACE_MEMORY | attr,
- pci_simple_bar_mapfunc);
-pci_dev->io_regions[region_num].ram_addr = ram_addr;
-}
-
void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
uint8_t attr, MemoryRegion *memory)
{
diff --git a/hw/pci.h b/hw/pci.h
index a95e2ad..25e28b1 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -93,7 +93,6 @@ typedef struct PCIIORegion {
pcibus_t filtered_size;
uint8_t type;
PCIMapIORegionFunc *map_func;
-ram_addr_t ram_addr;
MemoryRegion *memory;
MemoryRegion *address_space;
} PCIIORegion;
@@ -204,8 +203,6 @@ PCIDevice *pci_register_device(PCIBus *bus, const char
*name,
void pci_register_bar(PCIDevice *pci_dev, int region_num,
pcibus_t size, uint8_t type,
PCIMapIORegionFunc *map_func);
-void pci_register_bar_simple(PCIDevice *pci_dev, int region_num,
- pcibus_t size, uint8_t attr, ram_addr_t ram_addr);
void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
uint8_t attr, MemoryRegion *memory);
pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
--
1.7.5.3
[Qemu-devel] [PATCH 38/39] pci: rename pci_register_bar_region() to pci_register_bar()
Signed-off-by: Avi Kivity
---
hw/ac97.c |4 ++--
hw/cirrus_vga.c |5 ++---
hw/e1000.c|5 ++---
hw/eepro100.c |7 +++
hw/es1370.c |2 +-
hw/ide/cmd646.c | 14 +-
hw/ide/ich.c |2 +-
hw/ide/piix.c |3 +--
hw/ide/via.c |3 +--
hw/intel-hda.c|2 +-
hw/ivshmem.c | 15 +++
hw/lsi53c895a.c |7 +++
hw/macio.c|3 +--
hw/ne2000.c |2 +-
hw/openpic.c |4 ++--
hw/pci.c |6 +++---
hw/pci.h |4 ++--
hw/pcnet-pci.c|4 ++--
hw/qxl.c | 16
hw/rtl8139.c |6 ++
hw/sun4u.c|6 ++
hw/usb-ehci.c |2 +-
hw/usb-ohci.c |2 +-
hw/usb-uhci.c |3 +--
hw/vga-pci.c |3 +--
hw/virtio-pci.c |9 -
hw/vmware_vga.c |8
hw/wdt_i6300esb.c |2 +-
hw/xen_platform.c |7 +++
29 files changed, 68 insertions(+), 88 deletions(-)
diff --git a/hw/ac97.c b/hw/ac97.c
index bcddaa6..48ad2ec 100644
--- a/hw/ac97.c
+++ b/hw/ac97.c
@@ -1316,8 +1316,8 @@ static int ac97_initfn (PCIDevice *dev)
memory_region_init_io(&s->io_nam, &ac97_io_nam_ops, s, "ac97-nam", 1024);
memory_region_init_io(&s->io_nabm, &ac97_io_nabm_ops, s, "ac97-nabm", 256);
-pci_register_bar_region(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam);
-pci_register_bar_region(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO,
&s->io_nabm);
+pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam);
+pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm);
qemu_register_reset (ac97_on_reset, s);
AUD_register_card ("ac97", &s->card);
ac97_on_reset (s);
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index 15ccf4a..033822e 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -2949,10 +2949,9 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
/* memory #0 LFB */
/* memory #1 memory-mapped I/O */
/* XXX: s->vga.vram_size must be a power of two */
- pci_register_bar_region(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH,
- &s->pci_bar);
+ pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
if (device_id == CIRRUS_ID_CLGD5446) {
- pci_register_bar_region(&d->dev, 1, 0, &s->cirrus_mmio_io);
+ pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
}
return 0;
}
diff --git a/hw/e1000.c b/hw/e1000.c
index dfc082b..29b453f 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -1158,10 +1158,9 @@ static int pci_e1000_init(PCIDevice *pci_dev)
e1000_mmio_setup(d);
-pci_register_bar_region(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
-&d->mmio);
+pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
-pci_register_bar_region(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
+pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
memmove(d->eeprom_data, e1000_eeprom_template,
sizeof e1000_eeprom_template);
diff --git a/hw/eepro100.c b/hw/eepro100.c
index 04723f3..a636d30 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
@@ -1879,15 +1879,14 @@ static int e100_nic_init(PCIDevice *pci_dev)
/* Handler for memory-mapped I/O */
memory_region_init_io(&s->mmio_bar, &eepro100_ops, s, "eepro100-mmio",
PCI_MEM_SIZE);
-pci_register_bar_region(&s->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH,
-&s->mmio_bar);
+pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->mmio_bar);
memory_region_init_io(&s->io_bar, &eepro100_ops, s, "eepro100-io",
PCI_IO_SIZE);
-pci_register_bar_region(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
+pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
/* FIXME: flash aliases to mmio?! */
memory_region_init_io(&s->flash_bar, &eepro100_ops, s, "eepro100-flash",
PCI_FLASH_SIZE);
-pci_register_bar_region(&s->dev, 2, 0, &s->flash_bar);
+pci_register_bar(&s->dev, 2, 0, &s->flash_bar);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
diff --git a/hw/es1370.c b/hw/es1370.c
index 6a01797..f2c2d4d 100644
--- a/hw/es1370.c
+++ b/hw/es1370.c
@@ -1009,7 +1009,7 @@ static int es1370_initfn (PCIDevice *dev)
c[PCI_MAX_LAT] = 0x80;
memory_region_init_io(&s->io, &es1370_io_ops, s, "es1370", 256);
-pci_register_bar_region(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
+pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
qemu_register_reset (es1370_on_reset, s);
AUD_register_card ("es1370", &s->card);
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index 699ad6b..904febb 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -270,16 +270,12 @@ static int pci_cmd646_i
[Qemu-devel] [PATCH 03/39] vga: convert vga and its derivatives to the memory API
Convert all vga memory to the memory API. Note we need to fall back to
get_system_memory(), since the various buses don't pass the vga window
as a memory region.
We no longer need to sync the dirty bitmap of the cirrus mapped memory
banks, since the memory API takes care of that for us.
[jan: fix vga-pci logging]
Signed-off-by: Avi Kivity
---
hw/cirrus_vga.c | 343 --
hw/qxl-render.c |2 +-
hw/qxl.c| 135 --
hw/qxl.h|6 +-
hw/vga-isa-mm.c | 45 +---
hw/vga-isa.c| 11 +-
hw/vga-pci.c| 28 +
hw/vga.c| 147 +++-
hw/vga_int.h| 14 +--
hw/vmware_vga.c | 143 ---
10 files changed, 440 insertions(+), 434 deletions(-)
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index f39d1f8..d1475dd 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -200,9 +200,14 @@ typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
typedef struct CirrusVGAState {
VGACommonState vga;
-int cirrus_linear_io_addr;
-int cirrus_linear_bitblt_io_addr;
-int cirrus_mmio_io_addr;
+MemoryRegion cirrus_linear_io;
+MemoryRegion cirrus_linear_bitblt_io;
+MemoryRegion cirrus_mmio_io;
+MemoryRegion pci_bar;
+bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
+MemoryRegion low_mem_container; /* container for 0xa-0xc */
+MemoryRegion low_mem; /* always mapped, overridden by: */
+MemoryRegion *cirrus_bank[2]; /* aliases at 0xa-0xb */
uint32_t cirrus_addr_mask;
uint32_t linear_mmio_mask;
uint8_t cirrus_shadow_gr0;
@@ -612,7 +617,7 @@ static void cirrus_invalidate_region(CirrusVGAState * s,
int off_begin,
off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
off_cur &= TARGET_PAGE_MASK;
while (off_cur < off_cur_end) {
- cpu_physical_memory_set_dirty(s->vga.vram_offset + off_cur);
+ memory_region_set_dirty(&s->vga.vram, off_cur);
off_cur += TARGET_PAGE_SIZE;
}
off_begin += off_pitch;
@@ -1177,12 +1182,6 @@ static void cirrus_update_bank_ptr(CirrusVGAState * s,
unsigned bank_index)
}
if (limit > 0) {
-/* Thinking about changing bank base? First, drop the dirty bitmap
information
- * on the current location, otherwise we lose this pointer forever */
-if (s->vga.lfb_vram_mapped) {
-target_phys_addr_t base_addr = isa_mem_base + 0xa + bank_index
* 0x8000;
-cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
-}
s->cirrus_bank_base[bank_index] = offset;
s->cirrus_bank_limit[bank_index] = limit;
} else {
@@ -1921,8 +1920,8 @@ static void
cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
val <<= 1;
dst++;
}
-cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
-cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 7);
+memory_region_set_dirty(&s->vga.vram, offset);
+memory_region_set_dirty(&s->vga.vram, offset + 7);
}
static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
@@ -1946,8 +1945,8 @@ static void
cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
val <<= 1;
dst += 2;
}
-cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
-cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 15);
+memory_region_set_dirty(&s->vga.vram, offset);
+memory_region_set_dirty(&s->vga.vram, offset + 15);
}
/***
@@ -2057,8 +2056,7 @@ static void cirrus_vga_mem_writeb(void *opaque,
target_phys_addr_t addr,
mode = s->vga.gr[0x05] & 0x7;
if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
*(s->vga.vram_ptr + bank_offset) = mem_value;
- cpu_physical_memory_set_dirty(s->vga.vram_offset +
- bank_offset);
+ memory_region_set_dirty(&s->vga.vram, bank_offset);
} else {
if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
cirrus_mem_writeb_mode4and5_8bpp(s, mode,
@@ -2099,16 +2097,37 @@ static void cirrus_vga_mem_writel(void *opaque,
target_phys_addr_t addr, uint32_
cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
}
-static CPUReadMemoryFunc * const cirrus_vga_mem_read[3] = {
-cirrus_vga_mem_readb,
-cirrus_vga_mem_readw,
-cirrus_vga_mem_readl,
+static uint64_t cirrus_vga_mem_read(void *opaque,
+target_phys_addr_t addr,
+uint32_t size)
+{
+CirrusVGAState *s = opaque;
+
+switch (size) {
+case 1: return cirrus_vga_mem_readb(s, addr);
+case 2: return cirrus_vga_mem_readw(s, addr);
+case 4: return cirrus_vga_mem_readl(s, addr);
+default: abort();
Re: [Qemu-devel] [PATCH 03/39] vga: convert vga and its derivatives to the memory API
On 2011-07-31 20:46, Avi Kivity wrote: > On 07/31/2011 09:42 PM, Jan Kiszka wrote: >> On 2011-07-31 19:57, Avi Kivity wrote: >> > Convert all vga memory to the memory API. Note we need to fall >> back to >> > get_system_memory(), since the various buses don't pass the vga window >> > as a memory region. >> > >> > We no longer need to sync the dirty bitmap of the cirrus mapped memory >> > banks, since the memory API takes care of that for us. >> > >> > [jan: fix vga-pci logging] >> >> grub2 in graphical mode (likely via VBE) is still broken under kvm. > > Sorry, I forgot about it. Will take a look. > >> How >> did you try to address the flush-before-remap issue? >> > > I haven't. How does "unconditionally dirty the remapped slot" sound? > > I think it isn't introduced by this patchset, yes? The patch removes the explicit sync from the cirrus code. But the underlying issue is older of course. Jan signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] [RFC PATCH 0/4] Fix subsection ambiguity in the migration format
On Sun, Jul 31, 2011 at 02:45:07PM +0300, Dor Laor wrote: >> No, definitely not. I think most people using non-x86 architectures >> don't use the vmsave/vmload/migration features at all, but would >> be annoyed if the perfectly functional device models they were >> using got deleted... > > I didn't mean to erase the entire device, just the code for save/load which > as you say, might not be used at all. Like the one in virtio?
Re: [Qemu-devel] [PATCH 03/39] vga: convert vga and its derivatives to the memory API
On 07/31/2011 09:42 PM, Jan Kiszka wrote: On 2011-07-31 19:57, Avi Kivity wrote: > Convert all vga memory to the memory API. Note we need to fall back to > get_system_memory(), since the various buses don't pass the vga window > as a memory region. > > We no longer need to sync the dirty bitmap of the cirrus mapped memory > banks, since the memory API takes care of that for us. > > [jan: fix vga-pci logging] grub2 in graphical mode (likely via VBE) is still broken under kvm. Sorry, I forgot about it. Will take a look. How did you try to address the flush-before-remap issue? I haven't. How does "unconditionally dirty the remapped slot" sound? I think it isn't introduced by this patchset, yes? -- I have a truly marvellous patch that fixes the bug which this signature is too narrow to contain.
Re: [Qemu-devel] [Bug 818673] [NEW] virtio: trying to map MMIO memory
On Sun, 2011-07-31 at 18:54 +0100, Stefan Hajnoczi wrote: > On Sun, Jul 31, 2011 at 12:01 AM, Rick Vernam <818...@bugs.launchpad.net> > wrote: > > Public bug reported: > > > > Qemu host is Core i7, running Linux. Guest is Windows XP sp3. > > Often, qemu will crash shortly after starting (1-5 minutes) with a > > statement "qemu-system-x86_64: virtio: trying to map MMIO memory" > > This has occured with qemu-kvm 0.14, qemu-kvm 0.14.1, qemu-0.15.0-rc0 and > > qemu 0.15.0-rc1. > > Qemu is started as such: > > qemu-system-x86_64 -cpu host -enable-kvm -pidfile > > /home/rick/qemu/hds/wxp.pid -drive > > file=/home/rick/qemu/hds/wxp.raw,if=virtio -m 768 -name WinXP -net > > nic,model=virtio -net user -localtime -usb -vga qxl -device virtio-serial > > -chardev spicevmc,name=vdagent,id=vdagent -device > > virtserialport,chardev=vdagent,name=com.redhat.spice.0 -spice > > port=1234,disable-ticketing -daemonize -monitor > > telnet:localhost:12341,server,nowait > > The WXP guest has virtio 1.1.16 drivers for net and scsi, and the most > > current spice binaries from spice-space.org. > > This is probably a guest virtio driver bug. > > Vadim: Any known issues like this with 1.1.16? No, it something new to me. Will try to reproduce and fix it. Thank you, Vadim. > > Stefan
Re: [Qemu-devel] [PATCH 03/39] vga: convert vga and its derivatives to the memory API
On 2011-07-31 19:57, Avi Kivity wrote: > Convert all vga memory to the memory API. Note we need to fall back to > get_system_memory(), since the various buses don't pass the vga window > as a memory region. > > We no longer need to sync the dirty bitmap of the cirrus mapped memory > banks, since the memory API takes care of that for us. > > [jan: fix vga-pci logging] grub2 in graphical mode (likely via VBE) is still broken under kvm. How did you try to address the flush-before-remap issue? Jan signature.asc Description: OpenPGP digital signature
[Qemu-devel] [PATCH 16/39] eepro100: convert to memory API
Note: the existing code aliases the flash BAR into the MMIO bar. This is
probably a bug. This patch does not correct the problem.
Signed-off-by: Avi Kivity
---
hw/eepro100.c | 182 -
1 files changed, 37 insertions(+), 145 deletions(-)
diff --git a/hw/eepro100.c b/hw/eepro100.c
index 9b6f4a5..04723f3 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
@@ -228,13 +228,14 @@ typedef struct {
PCIDevice dev;
/* Hash register (multicast mask array, multiple individual addresses). */
uint8_t mult[8];
-int mmio_index;
+MemoryRegion mmio_bar;
+MemoryRegion io_bar;
+MemoryRegion flash_bar;
NICState *nic;
NICConf conf;
uint8_t scb_stat; /* SCB stat/ack byte */
uint8_t int_stat; /* PCI interrupt status */
/* region must not be saved by nic_save. */
-uint32_t region1; /* PCI region 1 address */
uint16_t mdimem[32];
eeprom_t *eeprom;
uint32_t device;/* device variant */
@@ -1584,147 +1585,36 @@ static void eepro100_write4(EEPRO100State * s,
uint32_t addr, uint32_t val)
}
}
-/*
- *
- * Port mapped I/O.
- *
- /
-
-static uint32_t ioport_read1(void *opaque, uint32_t addr)
-{
-EEPRO100State *s = opaque;
-#if 0
-logout("addr=%s\n", regname(addr));
-#endif
-return eepro100_read1(s, addr - s->region1);
-}
-
-static uint32_t ioport_read2(void *opaque, uint32_t addr)
-{
-EEPRO100State *s = opaque;
-return eepro100_read2(s, addr - s->region1);
-}
-
-static uint32_t ioport_read4(void *opaque, uint32_t addr)
-{
-EEPRO100State *s = opaque;
-return eepro100_read4(s, addr - s->region1);
-}
-
-static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
-{
-EEPRO100State *s = opaque;
-#if 0
-logout("addr=%s val=0x%02x\n", regname(addr), val);
-#endif
-eepro100_write1(s, addr - s->region1, val);
-}
-
-static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
-{
-EEPRO100State *s = opaque;
-eepro100_write2(s, addr - s->region1, val);
-}
-
-static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
-{
-EEPRO100State *s = opaque;
-eepro100_write4(s, addr - s->region1, val);
-}
-
-/***/
-/* PCI EEPRO100 definitions */
-
-static void pci_map(PCIDevice * pci_dev, int region_num,
-pcibus_t addr, pcibus_t size, int type)
-{
-EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
-
-TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
- "size=0x%08"FMT_PCIBUS", type=%d\n",
- region_num, addr, size, type));
-
-assert(region_num == 1);
-register_ioport_write(addr, size, 1, ioport_write1, s);
-register_ioport_read(addr, size, 1, ioport_read1, s);
-register_ioport_write(addr, size, 2, ioport_write2, s);
-register_ioport_read(addr, size, 2, ioport_read2, s);
-register_ioport_write(addr, size, 4, ioport_write4, s);
-register_ioport_read(addr, size, 4, ioport_read4, s);
-
-s->region1 = addr;
-}
-
-/*
- *
- * Memory mapped I/O.
- *
- /
-
-static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t
val)
-{
-EEPRO100State *s = opaque;
-#if 0
-logout("addr=%s val=0x%02x\n", regname(addr), val);
-#endif
-eepro100_write1(s, addr, val);
-}
-
-static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t
val)
+static uint64_t eepro100_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
EEPRO100State *s = opaque;
-#if 0
-logout("addr=%s val=0x%02x\n", regname(addr), val);
-#endif
-eepro100_write2(s, addr, val);
-}
-static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t
val)
-{
-EEPRO100State *s = opaque;
-#if 0
-logout("addr=%s val=0x%02x\n", regname(addr), val);
-#endif
-eepro100_write4(s, addr, val);
-}
-
-static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
-{
-EEPRO100State *s = opaque;
-#if 0
-logout("addr=%s\n", regname(addr));
-#endif
-return eepro100_read1(s, addr);
+switch (size) {
+case 1: return eepro100_read1(s, addr);
+case 2: return eepro100_read2(s, addr);
+case 4: return eepro100_read4(s, addr);
+default: abort();
+}
}
-static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
+static void eepro100_write(void *opaque, target_phys_addr_t addr,
+ uint64_t data, unsigned size)
{
EEPRO100State *s = opaque;
-#if 0
-logout("addr=%s\n", regname(addr));
-#endif
-return eepro100_read2(s, addr);
-}
-static uint32_
[Qemu-devel] [PATCH 20/39] virtio-pci: convert to memory API
except msix.
[jan: fix build]
Signed-off-by: Avi Kivity
---
hw/virtio-pci.c | 74 ++
hw/virtio-pci.h |2 +-
2 files changed, 31 insertions(+), 45 deletions(-)
diff --git a/hw/virtio-pci.c b/hw/virtio-pci.c
index d685243..c114e1a 100644
--- a/hw/virtio-pci.c
+++ b/hw/virtio-pci.c
@@ -161,7 +161,8 @@ static int
virtio_pci_set_host_notifier_internal(VirtIOPCIProxy *proxy,
{
VirtQueue *vq = virtio_get_queue(proxy->vdev, n);
EventNotifier *notifier = virtio_queue_get_host_notifier(vq);
-int r;
+int r = 0;
+
if (assign) {
r = event_notifier_init(notifier, 1);
if (r < 0) {
@@ -169,24 +170,11 @@ static int
virtio_pci_set_host_notifier_internal(VirtIOPCIProxy *proxy,
__func__, r);
return r;
}
-r = kvm_set_ioeventfd_pio_word(event_notifier_get_fd(notifier),
- proxy->addr + VIRTIO_PCI_QUEUE_NOTIFY,
- n, assign);
-if (r < 0) {
-error_report("%s: unable to map ioeventfd: %d",
- __func__, r);
-event_notifier_cleanup(notifier);
-}
+memory_region_add_eventfd(&proxy->bar, VIRTIO_PCI_QUEUE_NOTIFY, 2,
+ true, n, event_notifier_get_fd(notifier));
} else {
-r = kvm_set_ioeventfd_pio_word(event_notifier_get_fd(notifier),
- proxy->addr + VIRTIO_PCI_QUEUE_NOTIFY,
- n, assign);
-if (r < 0) {
-error_report("%s: unable to unmap ioeventfd: %d",
- __func__, r);
-return r;
-}
-
+memory_region_del_eventfd(&proxy->bar, VIRTIO_PCI_QUEUE_NOTIFY, 2,
+ true, n, event_notifier_get_fd(notifier));
/* Handle the race condition where the guest kicked and we deassigned
* before we got around to handling the kick.
*/
@@ -423,7 +411,6 @@ static uint32_t virtio_pci_config_readb(void *opaque,
uint32_t addr)
{
VirtIOPCIProxy *proxy = opaque;
uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev);
-addr -= proxy->addr;
if (addr < config)
return virtio_ioport_read(proxy, addr);
addr -= config;
@@ -434,7 +421,6 @@ static uint32_t virtio_pci_config_readw(void *opaque,
uint32_t addr)
{
VirtIOPCIProxy *proxy = opaque;
uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev);
-addr -= proxy->addr;
if (addr < config)
return virtio_ioport_read(proxy, addr);
addr -= config;
@@ -445,7 +431,6 @@ static uint32_t virtio_pci_config_readl(void *opaque,
uint32_t addr)
{
VirtIOPCIProxy *proxy = opaque;
uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev);
-addr -= proxy->addr;
if (addr < config)
return virtio_ioport_read(proxy, addr);
addr -= config;
@@ -456,7 +441,6 @@ static void virtio_pci_config_writeb(void *opaque, uint32_t
addr, uint32_t val)
{
VirtIOPCIProxy *proxy = opaque;
uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev);
-addr -= proxy->addr;
if (addr < config) {
virtio_ioport_write(proxy, addr, val);
return;
@@ -469,7 +453,6 @@ static void virtio_pci_config_writew(void *opaque, uint32_t
addr, uint32_t val)
{
VirtIOPCIProxy *proxy = opaque;
uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev);
-addr -= proxy->addr;
if (addr < config) {
virtio_ioport_write(proxy, addr, val);
return;
@@ -482,7 +465,6 @@ static void virtio_pci_config_writel(void *opaque, uint32_t
addr, uint32_t val)
{
VirtIOPCIProxy *proxy = opaque;
uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev);
-addr -= proxy->addr;
if (addr < config) {
virtio_ioport_write(proxy, addr, val);
return;
@@ -491,30 +473,26 @@ static void virtio_pci_config_writel(void *opaque,
uint32_t addr, uint32_t val)
virtio_config_writel(proxy->vdev, addr, val);
}
-static void virtio_map(PCIDevice *pci_dev, int region_num,
- pcibus_t addr, pcibus_t size, int type)
-{
-VirtIOPCIProxy *proxy = container_of(pci_dev, VirtIOPCIProxy, pci_dev);
-VirtIODevice *vdev = proxy->vdev;
-unsigned config_len = VIRTIO_PCI_REGION_SIZE(pci_dev) + vdev->config_len;
-
-proxy->addr = addr;
-
-register_ioport_write(addr, config_len, 1, virtio_pci_config_writeb,
proxy);
-register_ioport_write(addr, config_len, 2, virtio_pci_config_writew,
proxy);
-register_ioport_write(addr, config_len, 4, virtio_pci_config_writel,
proxy);
-register_ioport_read(addr, config_len, 1, virtio_pci_config_readb, proxy);
-register_ioport_read(addr, config_len, 2, virtio_pci_config_readw, proxy);
-register_ioport_read(addr, config_len, 4, virtio_pci_config_readl, proxy);
+const MemoryRegionPortio virtio_portio[] = {
+{ 0,
[Qemu-devel] [PATCH 27/39] i6300esb: convert to memory API
Also add missing destructor.
Signed-off-by: Avi Kivity
---
hw/wdt_i6300esb.c | 43 +--
1 files changed, 29 insertions(+), 14 deletions(-)
diff --git a/hw/wdt_i6300esb.c b/hw/wdt_i6300esb.c
index 53786ce..abc2e17 100644
--- a/hw/wdt_i6300esb.c
+++ b/hw/wdt_i6300esb.c
@@ -66,6 +66,7 @@
/* Device state. */
struct I6300State {
PCIDevice dev;
+MemoryRegion io_mem;
int reboot_enabled; /* "Reboot" on timer expiry. The real action
* performed depends on the -watchdog-action
@@ -355,6 +356,22 @@ static void i6300esb_mem_writel(void *vp,
target_phys_addr_t addr, uint32_t val)
}
}
+static const MemoryRegionOps i6300esb_ops = {
+.old_mmio = {
+.read = {
+i6300esb_mem_readb,
+i6300esb_mem_readw,
+i6300esb_mem_readl,
+},
+.write = {
+i6300esb_mem_writeb,
+i6300esb_mem_writew,
+i6300esb_mem_writel,
+},
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
static const VMStateDescription vmstate_i6300esb = {
.name = "i6300esb_wdt",
.version_id = sizeof(I6300State),
@@ -381,31 +398,28 @@ static const VMStateDescription vmstate_i6300esb = {
static int i6300esb_init(PCIDevice *dev)
{
I6300State *d = DO_UPCAST(I6300State, dev, dev);
-int io_mem;
-static CPUReadMemoryFunc * const mem_read[3] = {
-i6300esb_mem_readb,
-i6300esb_mem_readw,
-i6300esb_mem_readl,
-};
-static CPUWriteMemoryFunc * const mem_write[3] = {
-i6300esb_mem_writeb,
-i6300esb_mem_writew,
-i6300esb_mem_writel,
-};
i6300esb_debug("I6300State = %p\n", d);
d->timer = qemu_new_timer_ns(vm_clock, i6300esb_timer_expired, d);
d->previous_reboot_flag = 0;
-io_mem = cpu_register_io_memory(mem_read, mem_write, d,
-DEVICE_NATIVE_ENDIAN);
-pci_register_bar_simple(&d->dev, 0, 0x10, 0, io_mem);
+memory_region_init_io(&d->io_mem, &i6300esb_ops, d, "i6300esb", 0x10);
+pci_register_bar_region(&d->dev, 0, 0, &d->io_mem);
/* qemu_register_coalesced_mmio (addr, 0x10); ? */
return 0;
}
+static int i6300esb_exit(PCIDevice *dev)
+{
+I6300State *d = DO_UPCAST(I6300State, dev, dev);
+
+memory_region_destroy(&d->io_mem);
+
+return 0;
+}
+
static WatchdogTimerModel model = {
.wdt_name = "i6300esb",
.wdt_description = "Intel 6300ESB",
@@ -419,6 +433,7 @@ static PCIDeviceInfo i6300esb_info = {
.config_read = i6300esb_config_read,
.config_write = i6300esb_config_write,
.init = i6300esb_init,
+.exit = i6300esb_exit,
.vendor_id= PCI_VENDOR_ID_INTEL,
.device_id= PCI_DEVICE_ID_INTEL_ESB_9,
.class_id = PCI_CLASS_SYSTEM_OTHER,
--
1.7.5.3
[Qemu-devel] [PATCH 04/39] cirrus: simplify mmio BAR access functions
Make use of the memory API's ability to satisfy multi-byte accesses via
multiple single-byte accesses.
Signed-off-by: Avi Kivity
---
hw/cirrus_vga.c | 78 +-
1 files changed, 8 insertions(+), 70 deletions(-)
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index d1475dd..6e1aa75 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -2828,12 +2828,11 @@ static void cirrus_vga_ioport_write(void *opaque,
uint32_t addr, uint32_t val)
*
***/
-static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
CirrusVGAState *s = opaque;
-addr &= CIRRUS_PNPMMIO_SIZE - 1;
-
if (addr >= 0x100) {
return cirrus_mmio_blt_read(s, addr - 0x100);
} else {
@@ -2841,33 +2840,11 @@ static uint32_t cirrus_mmio_readb(void *opaque,
target_phys_addr_t addr)
}
}
-static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
-{
-uint32_t v;
-
-v = cirrus_mmio_readb(opaque, addr);
-v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
-return v;
-}
-
-static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
-{
-uint32_t v;
-
-v = cirrus_mmio_readb(opaque, addr);
-v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
-v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
-v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
-return v;
-}
-
-static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
CirrusVGAState *s = opaque;
-addr &= CIRRUS_PNPMMIO_SIZE - 1;
-
if (addr >= 0x100) {
cirrus_mmio_blt_write(s, addr - 0x100, val);
} else {
@@ -2875,53 +2852,14 @@ static void cirrus_mmio_writeb(void *opaque,
target_phys_addr_t addr,
}
}
-static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
-cirrus_mmio_writeb(opaque, addr, val & 0xff);
-cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
-}
-
-static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
-cirrus_mmio_writeb(opaque, addr, val & 0xff);
-cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
-cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
-cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
-}
-
-
-static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr,
- unsigned size)
-{
-CirrusVGAState *s = opaque;
-
-switch (size) {
-case 1: return cirrus_mmio_readb(s, addr);
-case 2: return cirrus_mmio_readw(s, addr);
-case 4: return cirrus_mmio_readl(s, addr);
-default: abort();
-}
-};
-
-static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr,
- uint64_t data, unsigned size)
-{
-CirrusVGAState *s = opaque;
-
-switch (size) {
-case 1: return cirrus_mmio_writeb(s, addr, data);
-case 2: return cirrus_mmio_writew(s, addr, data);
-case 4: return cirrus_mmio_writel(s, addr, data);
-default: abort();
-}
-};
-
static const MemoryRegionOps cirrus_mmio_io_ops = {
.read = cirrus_mmio_read,
.write = cirrus_mmio_write,
.endianness = DEVICE_LITTLE_ENDIAN,
+.impl = {
+.min_access_size = 1,
+.max_access_size = 1,
+},
};
/* load/save state */
--
1.7.5.3
[Qemu-devel] [PATCH 07/39] vga: simplify vga window mmio access functions
Make use of the memory API's ability to satisfy multi-byte accesses via
multiple single-byte accesses.
We have to keep vga_mem_{read,write}b() since they're used by cirrus.
Signed-off-by: Avi Kivity
---
hw/cirrus_vga.c |4 +-
hw/vga.c| 56 +++---
hw/vga_int.h|4 +-
3 files changed, 12 insertions(+), 52 deletions(-)
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index 92696d9..3db15bf 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -1965,7 +1965,7 @@ static uint64_t cirrus_vga_mem_read(void *opaque,
uint32_t val;
if ((s->vga.sr[0x07] & 0x01) == 0) {
- return vga_mem_readb(s, addr);
+return vga_mem_readb(&s->vga, addr);
}
if (addr < 0x1) {
@@ -2010,7 +2010,7 @@ static void cirrus_vga_mem_write(void *opaque,
unsigned mode;
if ((s->vga.sr[0x07] & 0x01) == 0) {
- vga_mem_writeb(s, addr, mem_value);
+vga_mem_writeb(&s->vga, addr, mem_value);
return;
}
diff --git a/hw/vga.c b/hw/vga.c
index cdd8255..f5dd519 100644
--- a/hw/vga.c
+++ b/hw/vga.c
@@ -707,9 +707,8 @@ static void vbe_ioport_write_data(void *opaque, uint32_t
addr, uint32_t val)
#endif
/* called for accesses between 0xa and 0xc */
-uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
+uint32_t vga_mem_readb(VGACommonState *s, target_phys_addr_t addr)
{
-VGACommonState *s = opaque;
int memory_map_mode, plane;
uint32_t ret;
@@ -763,28 +762,9 @@ uint32_t vga_mem_readb(void *opaque, target_phys_addr_t
addr)
return ret;
}
-static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
-{
-uint32_t v;
-v = vga_mem_readb(opaque, addr);
-v |= vga_mem_readb(opaque, addr + 1) << 8;
-return v;
-}
-
-static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
-{
-uint32_t v;
-v = vga_mem_readb(opaque, addr);
-v |= vga_mem_readb(opaque, addr + 1) << 8;
-v |= vga_mem_readb(opaque, addr + 2) << 16;
-v |= vga_mem_readb(opaque, addr + 3) << 24;
-return v;
-}
-
/* called for accesses between 0xa and 0xc */
-void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+void vga_mem_writeb(VGACommonState *s, target_phys_addr_t addr, uint32_t val)
{
-VGACommonState *s = opaque;
int memory_map_mode, plane, write_mode, b, func_select, mask;
uint32_t write_mask, bit_mask, set_mask;
@@ -916,20 +896,6 @@ void vga_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
}
}
-static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-vga_mem_writeb(opaque, addr, val & 0xff);
-vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
-}
-
-static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-vga_mem_writeb(opaque, addr, val & 0xff);
-vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
-vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
-vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
-}
-
typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
const uint8_t *font_ptr, int h,
uint32_t fgcol, uint32_t bgcol);
@@ -2104,12 +2070,7 @@ static uint64_t vga_mem_read(void *opaque,
target_phys_addr_t addr,
{
VGACommonState *s = opaque;
-switch (size) {
-case 1: return vga_mem_readb(s, addr);
-case 2: return vga_mem_readw(s, addr);
-case 4: return vga_mem_readl(s, addr);
-default: abort();
-}
+return vga_mem_readb(s, addr);
}
static void vga_mem_write(void *opaque, target_phys_addr_t addr,
@@ -2117,18 +2078,17 @@ static void vga_mem_write(void *opaque,
target_phys_addr_t addr,
{
VGACommonState *s = opaque;
-switch (size) {
-case 1: return vga_mem_writeb(s, addr, data);
-case 2: return vga_mem_writew(s, addr, data);
-case 4: return vga_mem_writel(s, addr, data);
-default: abort();
-}
+return vga_mem_writeb(s, addr, data);
}
const MemoryRegionOps vga_mem_ops = {
.read = vga_mem_read,
.write = vga_mem_write,
.endianness = DEVICE_LITTLE_ENDIAN,
+.impl = {
+.min_access_size = 1,
+.max_access_size = 1,
+},
};
static int vga_common_post_load(void *opaque, int version_id)
diff --git a/hw/vga_int.h b/hw/vga_int.h
index 4592d2c..100d98c 100644
--- a/hw/vga_int.h
+++ b/hw/vga_int.h
@@ -198,8 +198,8 @@ void vga_dirty_log_restart(VGACommonState *s);
extern const VMStateDescription vmstate_vga_common;
uint32_t vga_ioport_read(void *opaque, uint32_t addr);
void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val);
-uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
-void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
+uint32_t vga_mem_readb(VGACommonState *s, target_phys_addr_t addr);
+void vga_mem_writeb(VGACommonState *s, target_phys_addr_t addr, uint32_t val);
void vga_inval
Re: [Qemu-devel] [PATCH 00/39] Memory API, batch 2: PCI devices
> 79 files changed, 1654 insertions(+), 2082 deletions(-) Unexpected side effect...
[Qemu-devel] [PATCH 11/39] pci: pass I/O address space to new PCI bus
This lets us register BARs in the I/O address space.
Signed-off-by: Avi Kivity
---
hw/apb_pci.c |1 +
hw/bonito.c|1 +
hw/grackle_pci.c |8 ++--
hw/gt64xxx.c |4 +++-
hw/pc.h|4 +++-
hw/pc_piix.c |6 +-
hw/pci.c | 18 --
hw/pci.h | 10 +++---
hw/piix_pci.c | 14 +-
hw/ppc4xx_pci.c|1 +
hw/ppc_mac.h | 11 ---
hw/ppc_newworld.c |4 ++--
hw/ppc_oldworld.c |4 +++-
hw/ppc_prep.c |2 +-
hw/ppce500_pci.c |7 ---
hw/prep_pci.c |8 ++--
hw/prep_pci.h |4 +++-
hw/sh_pci.c|4 +++-
hw/unin_pci.c | 16
hw/versatile_pci.c |2 +-
20 files changed, 91 insertions(+), 38 deletions(-)
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index 8b9939c..1638226 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -348,6 +348,7 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
d->bus = pci_register_bus(&d->busdev.qdev, "pci",
pci_apb_set_irq, pci_pbm_map_irq, d,
get_system_memory(),
+ get_system_io(),
0, 32);
pci_bus_set_mem_base(d->bus, mem_base);
diff --git a/hw/bonito.c b/hw/bonito.c
index 5f62dda..8708e95 100644
--- a/hw/bonito.c
+++ b/hw/bonito.c
@@ -775,6 +775,7 @@ PCIBus *bonito_init(qemu_irq *pic)
pcihost = FROM_SYSBUS(BonitoState, sysbus_from_qdev(dev));
b = pci_register_bus(&pcihost->busdev.qdev, "pci", pci_bonito_set_irq,
pci_bonito_map_irq, pic, get_system_memory(),
+ get_system_io(),
0x28, 32);
pcihost->bus = b;
qdev_init_nofail(dev);
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index da67cf9..9a823e1 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -62,7 +62,8 @@ static void pci_grackle_reset(void *opaque)
}
PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
- MemoryRegion *address_space)
+ MemoryRegion *address_space_mem,
+ MemoryRegion *address_space_io)
{
DeviceState *dev;
SysBusDevice *s;
@@ -75,7 +76,10 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
pci_grackle_set_irq,
pci_grackle_map_irq,
- pic, address_space, 0, 4);
+ pic,
+ address_space_mem,
+ address_space_io,
+ 0, 4);
pci_create_simple(d->host_state.bus, 0, "grackle");
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index 65e63dd..d541558 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -1093,7 +1093,9 @@ PCIBus *gt64120_register(qemu_irq *pic)
d = FROM_SYSBUS(GT64120State, s);
d->pci.bus = pci_register_bus(&d->busdev.qdev, "pci",
gt64120_pci_set_irq, gt64120_pci_map_irq,
- pic, get_system_memory(),
+ pic,
+ get_system_memory(),
+ get_system_io(),
PCI_DEVFN(18, 0), 4);
d->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, d,
DEVICE_NATIVE_ENDIAN);
diff --git a/hw/pc.h b/hw/pc.h
index a2de0fe..ec34db7 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -179,7 +179,9 @@ struct PCII440FXState;
typedef struct PCII440FXState PCII440FXState;
PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
-qemu_irq *pic, MemoryRegion *address_space,
+qemu_irq *pic,
+MemoryRegion *address_space_mem,
+MemoryRegion *address_space_io,
ram_addr_t ram_size);
void i440fx_init_memory_mappings(PCII440FXState *d);
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index c0a2abe..7dd5008 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -69,6 +69,7 @@ static void ioapic_init(IsaIrqState *isa_irq_state)
/* PC hardware initialisation */
static void pc_init1(MemoryRegion *system_memory,
+ MemoryRegion *system_io,
ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
@@ -129,7 +130,7 @@ static void pc_init1(MemoryRegion *system_memory,
if (pci_enabled) {
pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq,
- system_memory, ram_size);
+ system_memory, system_io, ram_s
[Qemu-devel] [PATCH 29/39] sun4u: convert to memory API
fixes memory leak on repeated BAR map/unmap
Signed-off-by: Avi Kivity
---
hw/sun4u.c | 55 +--
1 files changed, 25 insertions(+), 30 deletions(-)
diff --git a/hw/sun4u.c b/hw/sun4u.c
index d7dcaf0..74a06a8 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -91,6 +91,12 @@ struct hwdef {
uint64_t console_serial_base;
};
+typedef struct EbusState {
+PCIDevice pci_dev;
+MemoryRegion bar0;
+MemoryRegion bar1;
+} EbusState;
+
int DMA_get_channel_mode (int nchan)
{
return 0;
@@ -518,21 +524,6 @@ void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
}
}
-static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
- pcibus_t addr, pcibus_t size, int type)
-{
-EBUS_DPRINTF("Mapping region %d registers at %" FMT_PCIBUS "\n",
- region_num, addr);
-switch (region_num) {
-case 0:
-isa_mmio_init(addr, 0x100);
-break;
-case 1:
-isa_mmio_init(addr, 0x80);
-break;
-}
-}
-
static void dummy_isa_irq_handler(void *opaque, int n, int level)
{
}
@@ -549,27 +540,31 @@ pci_ebus_init(PCIBus *bus, int devfn)
}
static int
-pci_ebus_init1(PCIDevice *s)
+pci_ebus_init1(PCIDevice *pci_dev)
{
-isa_bus_new(&s->qdev);
+EbusState *s = container_of(pci_dev, EbusState, pci_dev);
+
+isa_bus_new(&pci_dev->qdev);
-s->config[0x04] = 0x06; // command = bus master, pci mem
-s->config[0x05] = 0x00;
-s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
-s->config[0x07] = 0x03; // status = medium devsel
-s->config[0x09] = 0x00; // programming i/f
-s->config[0x0D] = 0x0a; // latency_timer
+pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
+pci_dev->config[0x05] = 0x00;
+pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no
error
+pci_dev->config[0x07] = 0x03; // status = medium devsel
+pci_dev->config[0x09] = 0x00; // programming i/f
+pci_dev->config[0x0D] = 0x0a; // latency_timer
-pci_register_bar(s, 0, 0x100, PCI_BASE_ADDRESS_SPACE_MEMORY,
- ebus_mmio_mapfunc);
-pci_register_bar(s, 1, 0x80, PCI_BASE_ADDRESS_SPACE_MEMORY,
- ebus_mmio_mapfunc);
+isa_mmio_setup(&s->bar0, 0x100);
+pci_register_bar_region(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
+&s->bar0);
+isa_mmio_setup(&s->bar1, 0x80);
+pci_register_bar_region(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY,
+&s->bar1);
return 0;
}
static PCIDeviceInfo ebus_info = {
.qdev.name = "ebus",
-.qdev.size = sizeof(PCIDevice),
+.qdev.size = sizeof(EbusState),
.init = pci_ebus_init1,
.vendor_id = PCI_VENDOR_ID_SUN,
.device_id = PCI_DEVICE_ID_SUN_EBUS,
--
1.7.5.3
[Qemu-devel] [PATCH 02/39] vmsvga: don't remember pci BAR address in callback any more
We're going to remove the callback, so we can't use it to save the
address. Use the pci API instead.
Signed-off-by: Avi Kivity
---
hw/vmware_vga.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c
index 354c221..190b005 100644
--- a/hw/vmware_vga.c
+++ b/hw/vmware_vga.c
@@ -52,8 +52,6 @@ struct vmsvga_state_s {
int on;
} cursor;
-target_phys_addr_t vram_base;
-
int index;
int scratch_size;
uint32_t *scratch;
@@ -761,8 +759,11 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t
address)
case SVGA_REG_BYTES_PER_LINE:
return ((s->depth + 7) >> 3) * s->new_width;
-case SVGA_REG_FB_START:
-return s->vram_base;
+case SVGA_REG_FB_START: {
+struct pci_vmsvga_state_s *pci_vmsvga
+= container_of(s, struct pci_vmsvga_state_s, chip);
+return pci_get_bar_addr(&pci_vmsvga->card, 1);
+}
case SVGA_REG_FB_OFFSET:
return 0x0;
@@ -1247,14 +1248,13 @@ static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int
region_num,
struct vmsvga_state_s *s = &d->chip;
ram_addr_t iomemtype;
-s->vram_base = addr;
#ifdef DIRECT_VRAM
iomemtype = cpu_register_io_memory(vmsvga_vram_read,
vmsvga_vram_write, s, DEVICE_NATIVE_ENDIAN);
#else
iomemtype = s->vga.vram_offset | IO_MEM_RAM;
#endif
-cpu_register_physical_memory(s->vram_base, s->vga.vram_size,
+cpu_register_physical_memory(addr, s->vga.vram_size,
iomemtype);
s->vga.map_addr = addr;
--
1.7.5.3
[Qemu-devel] [PATCH 01/39] pci: add API to get a BAR's mapped address
This is a hack, for devices that have a back-channel to read this
address back outside the normal configuration mechanisms, such
as VMware svga.
Signed-off-by: Avi Kivity
---
hw/pci.c |5 +
hw/pci.h |1 +
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 36db58b..912f849 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -952,6 +952,11 @@ void pci_register_bar_region(PCIDevice *pci_dev, int
region_num,
pci_dev->io_regions[region_num].memory = memory;
}
+pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
+{
+return pci_dev->io_regions[region_num].addr;
+}
+
static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
uint8_t type)
{
diff --git a/hw/pci.h b/hw/pci.h
index c51156d..64282ad 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -207,6 +207,7 @@ void pci_register_bar_simple(PCIDevice *pci_dev, int
region_num,
pcibus_t size, uint8_t attr, ram_addr_t ram_addr);
void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
uint8_t attr, MemoryRegion *memory);
+pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
uint8_t offset, uint8_t size);
--
1.7.5.3
Re: [Qemu-devel] [Bug 818673] [NEW] virtio: trying to map MMIO memory
On Sun, Jul 31, 2011 at 12:01 AM, Rick Vernam <818...@bugs.launchpad.net> wrote: > Public bug reported: > > Qemu host is Core i7, running Linux. Guest is Windows XP sp3. > Often, qemu will crash shortly after starting (1-5 minutes) with a statement > "qemu-system-x86_64: virtio: trying to map MMIO memory" > This has occured with qemu-kvm 0.14, qemu-kvm 0.14.1, qemu-0.15.0-rc0 and > qemu 0.15.0-rc1. > Qemu is started as such: > qemu-system-x86_64 -cpu host -enable-kvm -pidfile /home/rick/qemu/hds/wxp.pid > -drive file=/home/rick/qemu/hds/wxp.raw,if=virtio -m 768 -name WinXP -net > nic,model=virtio -net user -localtime -usb -vga qxl -device virtio-serial > -chardev spicevmc,name=vdagent,id=vdagent -device > virtserialport,chardev=vdagent,name=com.redhat.spice.0 -spice > port=1234,disable-ticketing -daemonize -monitor > telnet:localhost:12341,server,nowait > The WXP guest has virtio 1.1.16 drivers for net and scsi, and the most > current spice binaries from spice-space.org. This is probably a guest virtio driver bug. Vadim: Any known issues like this with 1.1.16? Stefan
Re: [Qemu-devel] Is there any qemu imag
On Sat, Jul 30, 2011 at 4:29 PM, bala suru wrote: > Hi, > Is there any qemu image (small OS which support , gcc, ssh, and networking > ) , like linux-0.2.img.bz2 . > > I want this for KVM hyeprvisor .. TinyCoreLinux is small distro that pulls in packages like web browsers and development tools over the network: http://distro.ibiblio.org/tinycorelinux/intro.html http://distro.ibiblio.org/tinycorelinux/3.x/release/tinycore-current.iso I've sometimes tested with it when I wanted a lightweight guest. It runs live from the ISO but you can also install it onto a disk image and preserve files across reboot. Stefan
Re: [Qemu-devel] [ANNOUNCE] QEMU 0.15.0-rc1 Release
On 07/30/2011 03:39 AM, Anthony Liguori wrote: Hi, On behalf of the entire QEMU team, I'm please to announce the release of QEMU 0.15.0-rc1. This is the second release candidate for the 0.15.0 release. make -jlarge fails with: cc1: warning: qapi-generated: No such file or directory [enabled by default] In file included from ./bswap.h:4:0, from ./qemu-common.h:98, from ./qlist.h:18, from ./qdict.h:17, from ./qapi/qmp-core.h:18, from ./qga/guest-agent-core.h:13, from qga/guest-agent-command-state.c:13: ./config-host.h:52:0: warning: "CONFIG_IOVEC" redefined [enabled by default] ./qemu-common.h:65:0: note: this is the location of the previous definition In file included from ./qlist.h:18:0, from ./qdict.h:17, from ./qapi/qmp-core.h:18, from ./qga/guest-agent-core.h:13, from qga/guest-agent-command-state.c:13: ./qemu-common.h:66:8: error: redefinition of ‘struct iovec’ /usr/include/bits/uio.h:44:8: note: originally defined here make: *** [qga/guest-agent-command-state.o] Error 1 make: *** Waiting for unfinished jobs A subsequent make makes it through, so it appears to be a missing dependency. -- error compiling committee.c: too many arguments to function
Re: [Qemu-devel] [PATCH] introduce environment variables for all qemu-user options
On 31 July 2011 12:51, wrote:
> + if ((r = getenv("QEMU_STACK_SIZE")) != NULL) {
> + guest_stack_size = strtoul(r, (char **)&r, 0);
> + if (guest_stack_size == 0)
> + usage();
> + if (*r == 'M')
> + guest_stack_size *= 1024 * 1024;
> + else if (*r == 'k' || *r == 'K')
> + guest_stack_size *= 1024;
> + }
[etc]
This is all basically duplicating the existing command line
argument parsing code, which (a) makes it very easy for the
two to drift out of sync in future and (b) means command line
options added in future might end up without a corresponding
environment variable.
I think it would be much nicer to have this be table-driven,
to avoid the code duplication. It ought to be possible to
derive most of the extra --help text from the table too.
-- PMM
[Qemu-devel] [PATCH] introduce environment variables for all qemu-user options
From: Johannes Schauer
A first try to introduce a generic setup for mapping environment variables to
command line options.
I'm afraid to code something for platforms I can't do runtime tests on, so this
is only for linux-user for now.
Signed-off-by: Johannes Schauer
---
linux-user/main.c | 147 +++-
1 files changed, 144 insertions(+), 3 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index dbba8be..fb986e3 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -2640,26 +2640,51 @@ static void usage(void)
"-E var=value sets/modifies targets environment variable(s)\n"
"-U varunsets targets environment variable(s)\n"
"-0 argv0 forces target process argv[0] to be argv0\n"
+ "-r uname set qemu uname release string\n"
#if defined(CONFIG_USE_GUEST_BASE)
"-B addressset guest_base address to address\n"
"-R size reserve size bytes for guest virtual address
space\n"
#endif
"\n"
+ "Standard environment variables:\n"
+ "QEMU_GDB see the -g option\n"
+ "QEMU_LD_PREFIXsee the -L option\n"
+ "QEMU_STACK_SIZE see the -s option\n"
+ "QEMU_CPU see the -cpu option\n"
+ "QEMU_SET_ENV see the -E option, comma separated list of
arguments\n"
+ "QEMU_UNSET_ENVsee the -U option, comma separated list of
arguments\n"
+ "QEMU_ARGV0see the -0 option\n"
+ "QEMU_UNAMEsee the -r option\n"
+#if defined(CONFIG_USE_GUEST_BASE)
+ "QEMU_GUEST_BASE see the -B option\n"
+ "QEMU_RESERVED_VA see the -R option\n"
+#endif
+ "\n"
"Debug options:\n"
"-d options activate log (logfile=%s)\n"
"-p pagesize set the host page size to 'pagesize'\n"
"-singlestep always run in singlestep mode\n"
"-strace log system calls\n"
"\n"
- "Environment variables:\n"
- "QEMU_STRACE Print system calls and arguments similar to
the\n"
- " 'strace' program. Enable by setting to any
value.\n"
+ "Debug environment variables:\n"
+ "QEMU_LOG see the -d option\n"
+ "QEMU_PAGESIZE see the -p option\n"
+ "QEMU_SINGLESTEP see the -singlestep option\n"
+ "QEMU_STRACE see the -strace option\n"
+ "\n"
"You can use -E and -U options to set/unset environment variables\n"
"for target process. It is possible to provide several variables\n"
"by repeating the option. For example:\n"
"-E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
"Note that if you provide several changes to single variable\n"
"last change will stay in effect.\n"
+ "Using the environment variables QEMU_SET_ENV and QEMU_UNSET_ENV\n"
+ "to set/unset environment variables for target process is\n"
+ "possible by a comma separated list of values in getsubopt(3)\n"
+ "style. For example:\n"
+ "QEMU_SET_ENV=var1=val2,var2=val2
QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
+ "Note that if you provide several changes to single variable\n"
+ "last change will stay in effect.\n"
,
TARGET_ARCH,
interp_prefix,
@@ -2758,6 +2783,122 @@ int main(int argc, char **argv, char **envp)
cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
#endif
+if ((r = getenv("QEMU_LOG")) != NULL) {
+int mask;
+const CPULogItem *item;
+mask = cpu_str_to_log_mask(r);
+if (!mask) {
+printf("Log items (comma separated):\n");
+for(item = cpu_log_items; item->mask != 0; item++) {
+printf("%-10s %s\n", item->name, item->help);
+}
+exit(1);
+}
+cpu_set_log(mask);
+}
+if ((r = getenv("QEMU_SET_ENV")) != NULL) {
+char *p, *token;
+p = strdup(r);
+while ((token = strsep(&p, ",")) != NULL) {
+if (envlist_setenv(envlist, token) != 0)
+usage();
+}
+free(p);
+}
+if ((r = getenv("QEMU_UNSET_ENV")) != NULL) {
+char *p, *token;
+p = strdup(r);
+while ((token = strsep(&p, ",")) != NULL) {
+if (envlist_unsetenv(envlist, token) != 0)
+usage();
+}
+free(p);
+}
+if ((r = getenv("QEMU_ARGV0")) != NULL) {
+argv0 = strdup(r);
+}
+if ((r = getenv("QEMU_STACK_SIZE")) != NULL) {
+guest_stack_size = strtoul(r, (char **)&r, 0);
+if (guest_stack_size == 0)
+usage();
+if (*r == 'M')
+guest_stack_size *= 1024 * 1024;
+else if (*r == 'k' || *r ==
Re: [Qemu-devel] [RFC PATCH 0/4] Fix subsection ambiguity in the migration format
On 07/31/2011 02:37 PM, Peter Maydell wrote: On 31 July 2011 11:48, Dor Laor wrote: ps: how hard is to finish the vmstate conversion? Can't we just assume not converted code is not functional and just remove all of it? No, definitely not. I think most people using non-x86 architectures don't use the vmsave/vmload/migration features at all, but would be annoyed if the perfectly functional device models they were using got deleted... I didn't mean to erase the entire device, just the code for save/load which as you say, might not be used at all. -- PMM
Re: [Qemu-devel] [RFC PATCH 0/4] Fix subsection ambiguity in the migration format
On 31 July 2011 11:48, Dor Laor wrote: > ps: how hard is to finish the vmstate conversion? Can't we just assume > not converted code is not functional and just remove all of it? No, definitely not. I think most people using non-x86 architectures don't use the vmsave/vmload/migration features at all, but would be annoyed if the perfectly functional device models they were using got deleted... -- PMM
Re: [Qemu-devel] [RFC PATCH 0/4] Fix subsection ambiguity in the migration format
On 07/30/2011 01:28 AM, Anthony Liguori wrote: No, not at all. Just that converting everything to VMState isn't a prerequisite for building a more robust migration protocol. The main thing is to priorities the problems we're facing with. - Live migration protocol: - VMState conversion is not complete - Live migration is not flexible enough (even with subsections) - Simplify destination cmdline for machine creation - Qdev - conversion is not complete - Machine + devices description are complex and have hidden glue - Qapi - Needs merging - QOB - Only the beginning So overall there are many parallel projects, probably more than the above. The RightThink(tm) would be to pick the ones that we can converge on and not try to handle all in parallel. There are problems we can live with. Engineering wise it might not be a beauty but they can wait (for instance dark magic to create the machines). There are some that prevent adding new features or make the code hard to support w/o them. Cheers, Dor ps: how hard is to finish the vmstate conversion? Can't we just assume not converted code is not functional and just remove all of it? Regards, Anthony Liguori
Re: [Qemu-devel] [ANNOUNCE] QEMU 0.15.0-rc1 Release
On 07/30/2011 03:39 AM, Anthony Liguori wrote: Hi, On behalf of the entire QEMU team, I'm please to announce the release of QEMU 0.15.0-rc1. This is the second release candidate for the 0.15.0 release. Unfortunately, it identifies itself as 1.0 development: $ git show v0.15.0-rc1:VERSION | cat 0.15.51 -- error compiling committee.c: too many arguments to function
