Re: [PATCH] hw/riscv: spike: Allow using binary firmware as bios

[Anup Patel]

On Tue, Jan 18, 2022 at 11:24 AM Alistair Francis  wrote:
>
> On Tue, Jan 18, 2022 at 3:27 PM Anup Patel  wrote:
> >
> > On Tue, Jan 18, 2022 at 10:50 AM Alistair Francis  
> > wrote:
> > >
> > > On Sat, Jan 15, 2022 at 2:18 AM Anup Patel  
> > > wrote:
> > > >
> > > > Currently, we have to use OpenSBI firmware ELF as bios for the spike
> > > > machine because the HTIF console requires ELF for parsing "fromhost"
> > > > and "tohost" symbols.
> > > >
> > > > The latest OpenSBI can now optionally pick-up HTIF register address
> > > > from HTIF DT node so using this feature spike machine can now use
> > > > OpenSBI firmware BIN as bios.
> > >
> > > Cool!
> > >
> > > I think that means we can remove the elfs from QEMU.
> >
> > Yes, we can definitely remove the ELFs from QEMU.
>
> Ha, I mostly meant can you do that? :P

Okay, let me take a stab at it in the next revision.

Regards,
Anup

>
> Alistair
>
> >
> > >
> > > >
> > > > Signed-off-by: Anup Patel 
> > > > ---
> > > >  hw/char/riscv_htif.c | 33 +++--
> > > >  hw/riscv/spike.c | 41 ++--
> > > >  include/hw/char/riscv_htif.h |  5 -
> > > >  include/hw/riscv/spike.h |  1 +
> > > >  4 files changed, 52 insertions(+), 28 deletions(-)
> > > >
> > > > diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
> > > > index ddae738d56..b59d321fb7 100644
> > > > --- a/hw/char/riscv_htif.c
> > > > +++ b/hw/char/riscv_htif.c
> > > > @@ -228,13 +228,25 @@ static const MemoryRegionOps htif_mm_ops = {
> > > >  .write = htif_mm_write,
> > > >  };
> > > >
> > > > +bool htif_uses_elf_symbols(void)
> > > > +{
> > > > +return (address_symbol_set == 3) ? true : false;
> > > > +}
> > > > +
> > > >  HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion 
> > > > *main_mem,
> > > > -CPURISCVState *env, Chardev *chr)
> > > > +CPURISCVState *env, Chardev *chr, uint64_t nonelf_base)
> > > >  {
> > > > -uint64_t base = MIN(tohost_addr, fromhost_addr);
> > > > -uint64_t size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
> > > > -uint64_t tohost_offset = tohost_addr - base;
> > > > -uint64_t fromhost_offset = fromhost_addr - base;
> > > > +uint64_t base, size, tohost_offset, fromhost_offset;
> > > > +
> > > > +if (address_symbol_set != 3) {
> > >
> > > Why not use htif_uses_elf_symbols() ?
> >
> > Ahh, yes.
> >
> > I should have used htif_uses_elf_symbols() here. I will update
> > it in the next revision.
> >
> > Regards,
> > Anup
> >
> > >
> > > Alistair
> > >
> > > > +fromhost_addr = nonelf_base;
> > > > +tohost_addr = nonelf_base + 8;
> > > > +}
> > > > +
> > > > +base = MIN(tohost_addr, fromhost_addr);
> > > > +size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
> > > > +tohost_offset = tohost_addr - base;
> > > > +fromhost_offset = fromhost_addr - base;
> > > >
> > > >  HTIFState *s = g_malloc0(sizeof(HTIFState));
> > > >  s->address_space = address_space;
> > > > @@ -249,12 +261,11 @@ HTIFState *htif_mm_init(MemoryRegion 
> > > > *address_space, MemoryRegion *main_mem,
> > > >  qemu_chr_fe_init(>chr, chr, _abort);
> > > >  qemu_chr_fe_set_handlers(>chr, htif_can_recv, htif_recv, 
> > > > htif_event,
> > > >  htif_be_change, s, NULL, true);
> > > > -if (address_symbol_set == 3) {
> > > > -memory_region_init_io(>mmio, NULL, _mm_ops, s,
> > > > -  TYPE_HTIF_UART, size);
> > > > -memory_region_add_subregion_overlap(address_space, base,
> > > > ->mmio, 1);
> > > > -}
> > > > +
> > > > +memory_region_init_io(>mmio, NULL, _mm_ops, s,
> > > > +  TYPE_HTIF_UART, size);
> > > > +memory_region_add_subregion_overlap(address_space, base,
> > > > +>mmio, 1);
> > > >
> > > >  return s;
> > > >  }
> > > > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> > > > index 288d69cd9f..597df4c288 100644
> > > > --- a/hw/riscv/spike.c
> > > > +++ b/hw/riscv/spike.c
> > > > @@ -42,6 +42,7 @@
> > > >
> > > >  static const MemMapEntry spike_memmap[] = {
> > > >  [SPIKE_MROM] = { 0x1000, 0xf000 },
> > > > +[SPIKE_HTIF] = {  0x100, 0x1000 },
> > > >  [SPIKE_CLINT] ={  0x200,0x1 },
> > > >  [SPIKE_DRAM] = { 0x8000,0x0 },
> > > >  };
> > > > @@ -75,6 +76,10 @@ static void create_fdt(SpikeState *s, const 
> > > > MemMapEntry *memmap,
> > > >
> > > >  qemu_fdt_add_subnode(fdt, "/htif");
> > > >  qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
> > > > +if (!htif_uses_elf_symbols()) {
> > > > +qemu_fdt_setprop_cells(fdt, "/htif", "reg",
> > > > +0x0, memmap[SPIKE_HTIF].base, 0x0, 
> > > > memmap[SPIKE_HTIF].size);
> > > > +}
> > > >
> > > >  qemu_fdt_add_subnode(fdt, "/soc");
> > > >  qemu_fdt_setprop(fdt, "/soc", 

Re: [PATCH v7 18/23] hw/intc: Add RISC-V AIA APLIC device emulation

[Frank Chang]

Anup Patel  於 2022年1月17日 週一 下午10:18寫道：

> From: Anup Patel 
>
> The RISC-V AIA (Advanced Interrupt Architecture) defines a new
> interrupt controller for wired interrupts called APLIC (Advanced
> Platform Level Interrupt Controller). The APLIC is capabable of
> forwarding wired interupts to RISC-V HARTs directly or as MSIs
> (Message Signaled Interupts).
>
> This patch adds device emulation for RISC-V AIA APLIC.
>
> Signed-off-by: Anup Patel 
> Signed-off-by: Anup Patel 
> ---
>  hw/intc/Kconfig   |   3 +
>  hw/intc/meson.build   |   1 +
>  hw/intc/riscv_aplic.c | 975 ++
>  include/hw/intc/riscv_aplic.h |  79 +++
>  4 files changed, 1058 insertions(+)
>  create mode 100644 hw/intc/riscv_aplic.c
>  create mode 100644 include/hw/intc/riscv_aplic.h
>
> diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
> index 010ded7eae..528e77b4a6 100644
> --- a/hw/intc/Kconfig
> +++ b/hw/intc/Kconfig
> @@ -70,6 +70,9 @@ config LOONGSON_LIOINTC
>  config RISCV_ACLINT
>  bool
>
> +config RISCV_APLIC
> +bool
> +
>  config SIFIVE_PLIC
>  bool
>
> diff --git a/hw/intc/meson.build b/hw/intc/meson.build
> index 70080bc161..7466024402 100644
> --- a/hw/intc/meson.build
> +++ b/hw/intc/meson.build
> @@ -50,6 +50,7 @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true:
> files('s390_flic.c'))
>  specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true:
> files('s390_flic_kvm.c'))
>  specific_ss.add(when: 'CONFIG_SH_INTC', if_true: files('sh_intc.c'))
>  specific_ss.add(when: 'CONFIG_RISCV_ACLINT', if_true:
> files('riscv_aclint.c'))
> +specific_ss.add(when: 'CONFIG_RISCV_APLIC', if_true:
> files('riscv_aplic.c'))
>  specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true:
> files('sifive_plic.c'))
>  specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
>  specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XICS'],
> diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
> new file mode 100644
> index 00..885c1de2af
> --- /dev/null
> +++ b/hw/intc/riscv_aplic.c
> @@ -0,0 +1,975 @@
> +/*
> + * RISC-V APLIC (Advanced Platform Level Interrupt Controller)
> + *
> + * Copyright (c) 2021 Western Digital Corporation or its affiliates.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
> for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> along with
> + * this program.  If not, see .
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "qemu/log.h"
> +#include "qemu/module.h"
> +#include "qemu/error-report.h"
> +#include "qemu/bswap.h"
> +#include "exec/address-spaces.h"
> +#include "hw/sysbus.h"
> +#include "hw/pci/msi.h"
> +#include "hw/boards.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/intc/riscv_aplic.h"
> +#include "hw/irq.h"
> +#include "target/riscv/cpu.h"
> +#include "sysemu/sysemu.h"
> +#include "migration/vmstate.h"
> +
> +#define APLIC_MAX_IDC  (1UL << 14)
> +#define APLIC_MAX_SOURCE   1024
> +#define APLIC_MIN_IPRIO_BITS   1
> +#define APLIC_MAX_IPRIO_BITS   8
> +#define APLIC_MAX_CHILDREN 1024
> +
> +#define APLIC_DOMAINCFG0x
> +#define APLIC_DOMAINCFG_RDONLY 0x8000
> +#define APLIC_DOMAINCFG_IE (1 << 8)
> +#define APLIC_DOMAINCFG_DM (1 << 2)
> +#define APLIC_DOMAINCFG_BE (1 << 0)
> +
> +#define APLIC_SOURCECFG_BASE   0x0004
> +#define APLIC_SOURCECFG_D  (1 << 10)
> +#define APLIC_SOURCECFG_CHILDIDX_MASK  0x03ff
> +#define APLIC_SOURCECFG_SM_MASK0x0007
> +#define APLIC_SOURCECFG_SM_INACTIVE0x0
> +#define APLIC_SOURCECFG_SM_DETACH  0x1
> +#define APLIC_SOURCECFG_SM_EDGE_RISE   0x4
> +#define APLIC_SOURCECFG_SM_EDGE_FALL   0x5
> +#define APLIC_SOURCECFG_SM_LEVEL_HIGH  0x6
> +#define APLIC_SOURCECFG_SM_LEVEL_LOW   0x7
> +
> +#define APLIC_MMSICFGADDR  0x1bc0
> +#define APLIC_MMSICFGADDRH 0x1bc4
> +#define APLIC_SMSICFGADDR  0x1bc8
> +#define APLIC_SMSICFGADDRH 0x1bcc
> +
> +#define APLIC_xMSICFGADDRH_L   (1UL << 31)
> +#define APLIC_xMSICFGADDRH_HHXS_MASK   0x1f
> +#define APLIC_xMSICFGADDRH_HHXS_SHIFT  24
> +#define APLIC_xMSICFGADDRH_LHXS_MASK   0x7
> +#define APLIC_xMSICFGADDRH_LHXS_SHIFT  20
> +#define APLIC_xMSICFGADDRH_HHXW_MASK   0x7
> +#define APLIC_xMSICFGADDRH_HHXW_SHIFT  16
> +#define APLIC_xMSICFGADDRH_LHXW_MASK   0xf
> +#define APLIC_xMSICFGADDRH_LHXW_SHIFT  12
> +#define APLIC_xMSICFGADDRH_BAPPN_MASK  

Re: [PATCH v3] hw/dma: Let dma_buf_read() / dma_buf_write() propagate MemTxResult

[Philippe Mathieu-Daudé via]

On 1/17/22 13:51, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé 
> 
> Since commit 292e13142d2, dma_buf_rw() returns a MemTxResult type.
> Do not discard it, return it to the caller. Pass the previously
> returned value (the QEMUSGList residual size, which was rarely used)
> as an optional argument.
> 
> With this new API, SCSIRequest::residual might now be accessed via
> a pointer. Since the size_t type does not have the same size on
> 32 and 64-bit host architectures, convert it to a uint64_t, which
> is big enough to hold the residual size, and the type is constant
> on both 32/64-bit hosts.
> 
> Update the few dma_buf_read() / dma_buf_write() callers to the new
> API.
> 
> Reviewed-by: Klaus Jensen 
> Signed-off-by: Philippe Mathieu-Daudé 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
> v3:
> - Reworded to precise the SCSIRequest::residual type change
> - Posted out of the "Use dma_addr_t type definition when relevant"
>   series (dhildenb)
> ---
>  include/hw/scsi/scsi.h |  2 +-
>  include/sysemu/dma.h   |  4 +--
>  hw/ide/ahci.c  |  8 +++---
>  hw/nvme/ctrl.c |  4 +--
>  hw/scsi/megasas.c  | 59 ++
>  hw/scsi/scsi-bus.c |  6 +++--
>  softmmu/dma-helpers.c  | 16 +++-
>  7 files changed, 59 insertions(+), 40 deletions(-)

Queued via memory-api.

Re: [RFC PATCH 6/6] docs/devel: add some clarifying text for aliases

[Philippe Mathieu-Daudé via]

On 1/10/22 18:51, Alex Bennée wrote:
> We do mention the limitation of single parenthood for
> memory_region_add_subregion but lets also make it clear how aliases
> help solve that conundrum.
> 
> Signed-off-by: Alex Bennée 
> ---
>  docs/devel/memory.rst | 14 +-
>  1 file changed, 9 insertions(+), 5 deletions(-)

Thanks, queued via memory-api.

Re: [PATCH v3 00/10] hw/dma: Use dma_addr_t type definition when relevant

[Philippe Mathieu-Daudé via]

On 1/11/22 19:42, Philippe Mathieu-Daudé wrote:

> Philippe Mathieu-Daudé (10):
>   stubs: Restrict fw_cfg to system emulation
>   hw/nvram: Restrict fw_cfg QOM interface to sysemu and tools
>   hw/pci: Restrict pci-bus stub to sysemu
>   hw/pci: Document pci_dma_map()
>   hw/dma: Remove CONFIG_USER_ONLY check
>   hw/rdma/rdma_utils: Rename rdma_pci_dma_map 'len' argument
>   hw/scsi: Rename SCSIRequest::resid as 'residual'
>   hw/dma: Fix format string issues using dma_addr_t
>   hw/dma: Move ScatterGatherEntry / QEMUSGList declarations around
>   hw/dma: Use dma_addr_t type definition when relevant

Queued via memory-api.

Re: [PATCH v7 0/2] memory: Have 'info mtree' remove duplicated Address Space information

[Philippe Mathieu-Daudé via]

On 9/5/21 01:10, Philippe Mathieu-Daudé wrote:

> Philippe Mathieu-Daudé (2):
>   memory: Split mtree_info() as mtree_info_flatview() + mtree_info_as()
>   memory: Have 'info mtree' remove duplicated Address Space information

Queued via memory-api.

Re: [PATCH RESEND] tests/avocado: ppc: Add smoke tests for MPC7400 and MPC7450 families

[Cédric Le Goater]

On 1/17/22 21:08, Daniel Henrique Barboza wrote:



On 1/17/22 11:47, Fabiano Rosas wrote:

These tests ensure that our emulation for these cpus is not completely
broken and we can at least run OpenBIOS on them.

$ make check-avocado AVOCADO_TESTS=../tests/avocado/ppc_74xx.py

Signed-off-by: Fabiano Rosas 
Reviewed-by: Willian Rampazzo 
---
---
  tests/avocado/ppc_74xx.py | 123 ++
  1 file changed, 123 insertions(+)
  create mode 100644 tests/avocado/ppc_74xx.py

diff --git a/tests/avocado/ppc_74xx.py b/tests/avocado/ppc_74xx.py
new file mode 100644
index 00..556a9a7da9
--- /dev/null
+++ b/tests/avocado/ppc_74xx.py
@@ -0,0 +1,123 @@
+# Smoke tests for 74xx cpus (aka G4).
+#
+# Copyright (c) 2021, IBM Corp.



Not sure if the copyright year must be changed to 2022 (the year that this is 
going to
be published) or 2021 (the year that it was developed). GNU docs isn't clear 
about
it. Our COPYING file is also not clear about whether we should put the code 
creation
or code publishing year in this header.

I don't mind leaving it as 2021. I'm just curious about what is the semantics 
involved
here.


Here is a brief summary of the IBM rules :

   Copyright IBM Corp. Year 1, Year 2

Year 1 is the year of first external delivery.

Year 2 is the year of the first external distribution of the latest
substantial changes (Only added when changes have been made).

I think we are fine with the above Copyright statement.

Thanks,

C.
 



Reviewed-by: Daniel Henrique Barboza 


+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later.  See the COPYING file in the top-level directory.
+
+from avocado_qemu import QemuSystemTest
+from avocado_qemu import wait_for_console_pattern
+
+class ppc74xxCpu(QemuSystemTest):
+    """
+    :avocado: tags=arch:ppc
+    """
+    timeout = 5
+
+    def test_ppc_7400(self):
+    """
+    :avocado: tags=cpu:7400
+    """
+    self.vm.set_console()
+    self.vm.launch()
+    wait_for_console_pattern(self, '>> OpenBIOS')
+    wait_for_console_pattern(self, '>> CPU type PowerPC,G4')
+
+    def test_ppc_7410(self):
+    """
+    :avocado: tags=cpu:7410
+    """
+    self.vm.set_console()
+    self.vm.launch()
+    wait_for_console_pattern(self, '>> OpenBIOS')
+    wait_for_console_pattern(self, '>> CPU type PowerPC,74xx')
+
+    def test_ppc_7441(self):
+    """
+    :avocado: tags=cpu:7441
+    """
+    self.vm.set_console()
+    self.vm.launch()
+    wait_for_console_pattern(self, '>> OpenBIOS')
+    wait_for_console_pattern(self, '>> CPU type PowerPC,G4')
+
+    def test_ppc_7445(self):
+    """
+    :avocado: tags=cpu:7445
+    """
+    self.vm.set_console()
+    self.vm.launch()
+    wait_for_console_pattern(self, '>> OpenBIOS')
+    wait_for_console_pattern(self, '>> CPU type PowerPC,G4')
+
+    def test_ppc_7447(self):
+    """
+    :avocado: tags=cpu:7447
+    """
+    self.vm.set_console()
+    self.vm.launch()
+    wait_for_console_pattern(self, '>> OpenBIOS')
+    wait_for_console_pattern(self, '>> CPU type PowerPC,G4')
+
+    def test_ppc_7447a(self):
+    """
+    :avocado: tags=cpu:7447a
+    """
+    self.vm.set_console()
+    self.vm.launch()
+    wait_for_console_pattern(self, '>> OpenBIOS')
+    wait_for_console_pattern(self, '>> CPU type PowerPC,G4')
+
+    def test_ppc_7448(self):
+    """
+    :avocado: tags=cpu:7448
+    """
+    self.vm.set_console()
+    self.vm.launch()
+    wait_for_console_pattern(self, '>> OpenBIOS')
+    wait_for_console_pattern(self, '>> CPU type PowerPC,MPC86xx')
+
+    def test_ppc_7450(self):
+    """
+    :avocado: tags=cpu:7450
+    """
+    self.vm.set_console()
+    self.vm.launch()
+    wait_for_console_pattern(self, '>> OpenBIOS')
+    wait_for_console_pattern(self, '>> CPU type PowerPC,G4')
+
+    def test_ppc_7451(self):
+    """
+    :avocado: tags=cpu:7451
+    """
+    self.vm.set_console()
+    self.vm.launch()
+    wait_for_console_pattern(self, '>> OpenBIOS')
+    wait_for_console_pattern(self, '>> CPU type PowerPC,G4')
+
+    def test_ppc_7455(self):
+    """
+    :avocado: tags=cpu:7455
+    """
+    self.vm.set_console()
+    self.vm.launch()
+    wait_for_console_pattern(self, '>> OpenBIOS')
+    wait_for_console_pattern(self, '>> CPU type PowerPC,G4')
+
+    def test_ppc_7457(self):
+    """
+    :avocado: tags=cpu:7457
+    """
+    self.vm.set_console()
+    self.vm.launch()
+    wait_for_console_pattern(self, '>> OpenBIOS')
+    wait_for_console_pattern(self, '>> CPU type PowerPC,G4')
+
+    def test_ppc_7457a(self):
+    """
+    :avocado: tags=cpu:7457a
+    """
+    self.vm.set_console()
+    self.vm.launch()
+    

Re: [PATCH 3/3] Link new ppc-spapr-uv-hcalls.rst to pseries.rst.

[Cédric Le Goater]

On 1/17/22 21:53, Daniel Henrique Barboza wrote:



On 1/17/22 16:19, lagar...@linux.ibm.com wrote:

From: Leonardo Garcia 

Signed-off-by: Leonardo Garcia 
---


It is worth noticing that this patch applies cleanly only if the

"[PATCH 0/3] rSTify ppc-spapr-hotplug.txt" [1]

series is applied first. The reason is that docs/system/ppc/pseries.rst being 
changed
here already has the ppc-spapr-hotplug.rst link.


yes. That's fine. I have queued the first series already.

Thanks,

C.

Re: [PATCH 3/3] ppc/pnv: Remove PHB4 version property

[Cédric Le Goater]

On 1/17/22 20:50, Daniel Henrique Barboza wrote:



On 1/17/22 09:27, Cédric Le Goater wrote:

and grab the PHB version from the PEC class directly when needed.


I guess we want a capital "A" when starting the commit msg


I just removed the 'and'.

Thanks,

C.






Signed-off-by: Cédric Le Goater 
---



This change also makes pnv-phb4s a little closer with pnv-phb3s, given that we 
don't
have a "Version" attribute exposed in the QOM for pnv-phb3s as well.


Reviewed-by: Daniel Henrique Barboza 


  hw/pci-host/pnv_phb4.c | 9 +
  hw/pci-host/pnv_phb4_pec.c | 3 ---
  2 files changed, 1 insertion(+), 11 deletions(-)

diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index c688976caec9..a78add75b043 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -672,7 +672,7 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, 
unsigned size)
  switch (off) {
  case PHB_VERSION:
-    return phb->version;
+    return PNV_PHB4_PEC_GET_CLASS(phb->pec)->version;
  /* Read-only */
  case PHB_PHB4_GEN_CAP:
@@ -1575,7 +1575,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error 
**errp)
  if (!phb->pec) {
  PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
  PnvChip *chip = pnv_get_chip(pnv, phb->chip_id);
-    PnvPhb4PecClass *pecc;
  BusState *s;
  if (!chip) {
@@ -1589,11 +1588,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error 
**errp)
  return;
  }
-    /* All other phb properties are already set */
-    pecc = PNV_PHB4_PEC_GET_CLASS(phb->pec);
-    object_property_set_int(OBJECT(phb), "version", pecc->version,
-    _fatal);
-
  /*
   * Reparent user created devices to the chip to build
   * correctly the device tree.
@@ -1688,7 +1682,6 @@ static void pnv_phb4_xive_notify(XiveNotifier *xf, 
uint32_t srcno)
  static Property pnv_phb4_properties[] = {
  DEFINE_PROP_UINT32("index", PnvPHB4, phb_id, 0),
  DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0),
-    DEFINE_PROP_UINT64("version", PnvPHB4, version, 0),
  DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC,
   PnvPhb4PecState *),
  DEFINE_PROP_END_OF_LIST(),
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index a3c4b4ef850c..40d89fda56e5 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -117,7 +117,6 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState 
*pec,
  Error **errp)
  {
  PnvPHB4 *phb = PNV_PHB4(qdev_new(TYPE_PNV_PHB4));
-    PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
  int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no);
  object_property_set_link(OBJECT(phb), "pec", OBJECT(pec),
@@ -126,8 +125,6 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState 
*pec,
  _fatal);
  object_property_set_int(OBJECT(phb), "index", phb_id,
  _fatal);
-    object_property_set_int(OBJECT(phb), "version", pecc->version,
-    _fatal);
  if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
  return;

Re: [PATCH] hw/riscv: spike: Allow using binary firmware as bios

[Alistair Francis]

On Tue, Jan 18, 2022 at 3:27 PM Anup Patel  wrote:
>
> On Tue, Jan 18, 2022 at 10:50 AM Alistair Francis  
> wrote:
> >
> > On Sat, Jan 15, 2022 at 2:18 AM Anup Patel  wrote:
> > >
> > > Currently, we have to use OpenSBI firmware ELF as bios for the spike
> > > machine because the HTIF console requires ELF for parsing "fromhost"
> > > and "tohost" symbols.
> > >
> > > The latest OpenSBI can now optionally pick-up HTIF register address
> > > from HTIF DT node so using this feature spike machine can now use
> > > OpenSBI firmware BIN as bios.
> >
> > Cool!
> >
> > I think that means we can remove the elfs from QEMU.
>
> Yes, we can definitely remove the ELFs from QEMU.

Ha, I mostly meant can you do that? :P

Alistair

>
> >
> > >
> > > Signed-off-by: Anup Patel 
> > > ---
> > >  hw/char/riscv_htif.c | 33 +++--
> > >  hw/riscv/spike.c | 41 ++--
> > >  include/hw/char/riscv_htif.h |  5 -
> > >  include/hw/riscv/spike.h |  1 +
> > >  4 files changed, 52 insertions(+), 28 deletions(-)
> > >
> > > diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
> > > index ddae738d56..b59d321fb7 100644
> > > --- a/hw/char/riscv_htif.c
> > > +++ b/hw/char/riscv_htif.c
> > > @@ -228,13 +228,25 @@ static const MemoryRegionOps htif_mm_ops = {
> > >  .write = htif_mm_write,
> > >  };
> > >
> > > +bool htif_uses_elf_symbols(void)
> > > +{
> > > +return (address_symbol_set == 3) ? true : false;
> > > +}
> > > +
> > >  HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion 
> > > *main_mem,
> > > -CPURISCVState *env, Chardev *chr)
> > > +CPURISCVState *env, Chardev *chr, uint64_t nonelf_base)
> > >  {
> > > -uint64_t base = MIN(tohost_addr, fromhost_addr);
> > > -uint64_t size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
> > > -uint64_t tohost_offset = tohost_addr - base;
> > > -uint64_t fromhost_offset = fromhost_addr - base;
> > > +uint64_t base, size, tohost_offset, fromhost_offset;
> > > +
> > > +if (address_symbol_set != 3) {
> >
> > Why not use htif_uses_elf_symbols() ?
>
> Ahh, yes.
>
> I should have used htif_uses_elf_symbols() here. I will update
> it in the next revision.
>
> Regards,
> Anup
>
> >
> > Alistair
> >
> > > +fromhost_addr = nonelf_base;
> > > +tohost_addr = nonelf_base + 8;
> > > +}
> > > +
> > > +base = MIN(tohost_addr, fromhost_addr);
> > > +size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
> > > +tohost_offset = tohost_addr - base;
> > > +fromhost_offset = fromhost_addr - base;
> > >
> > >  HTIFState *s = g_malloc0(sizeof(HTIFState));
> > >  s->address_space = address_space;
> > > @@ -249,12 +261,11 @@ HTIFState *htif_mm_init(MemoryRegion 
> > > *address_space, MemoryRegion *main_mem,
> > >  qemu_chr_fe_init(>chr, chr, _abort);
> > >  qemu_chr_fe_set_handlers(>chr, htif_can_recv, htif_recv, 
> > > htif_event,
> > >  htif_be_change, s, NULL, true);
> > > -if (address_symbol_set == 3) {
> > > -memory_region_init_io(>mmio, NULL, _mm_ops, s,
> > > -  TYPE_HTIF_UART, size);
> > > -memory_region_add_subregion_overlap(address_space, base,
> > > ->mmio, 1);
> > > -}
> > > +
> > > +memory_region_init_io(>mmio, NULL, _mm_ops, s,
> > > +  TYPE_HTIF_UART, size);
> > > +memory_region_add_subregion_overlap(address_space, base,
> > > +>mmio, 1);
> > >
> > >  return s;
> > >  }
> > > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> > > index 288d69cd9f..597df4c288 100644
> > > --- a/hw/riscv/spike.c
> > > +++ b/hw/riscv/spike.c
> > > @@ -42,6 +42,7 @@
> > >
> > >  static const MemMapEntry spike_memmap[] = {
> > >  [SPIKE_MROM] = { 0x1000, 0xf000 },
> > > +[SPIKE_HTIF] = {  0x100, 0x1000 },
> > >  [SPIKE_CLINT] ={  0x200,0x1 },
> > >  [SPIKE_DRAM] = { 0x8000,0x0 },
> > >  };
> > > @@ -75,6 +76,10 @@ static void create_fdt(SpikeState *s, const 
> > > MemMapEntry *memmap,
> > >
> > >  qemu_fdt_add_subnode(fdt, "/htif");
> > >  qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
> > > +if (!htif_uses_elf_symbols()) {
> > > +qemu_fdt_setprop_cells(fdt, "/htif", "reg",
> > > +0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size);
> > > +}
> > >
> > >  qemu_fdt_add_subnode(fdt, "/soc");
> > >  qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
> > > @@ -172,6 +177,7 @@ static void create_fdt(SpikeState *s, const 
> > > MemMapEntry *memmap,
> > >  if (cmdline) {
> > >  qemu_fdt_add_subnode(fdt, "/chosen");
> > >  qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> > > +qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
> > >  }
> > >  }
> > >
> > > @@ -241,10 

Re: [PATCH] hw/riscv: spike: Allow using binary firmware as bios

[Anup Patel]

On Tue, Jan 18, 2022 at 10:50 AM Alistair Francis  wrote:
>
> On Sat, Jan 15, 2022 at 2:18 AM Anup Patel  wrote:
> >
> > Currently, we have to use OpenSBI firmware ELF as bios for the spike
> > machine because the HTIF console requires ELF for parsing "fromhost"
> > and "tohost" symbols.
> >
> > The latest OpenSBI can now optionally pick-up HTIF register address
> > from HTIF DT node so using this feature spike machine can now use
> > OpenSBI firmware BIN as bios.
>
> Cool!
>
> I think that means we can remove the elfs from QEMU.

Yes, we can definitely remove the ELFs from QEMU.

>
> >
> > Signed-off-by: Anup Patel 
> > ---
> >  hw/char/riscv_htif.c | 33 +++--
> >  hw/riscv/spike.c | 41 ++--
> >  include/hw/char/riscv_htif.h |  5 -
> >  include/hw/riscv/spike.h |  1 +
> >  4 files changed, 52 insertions(+), 28 deletions(-)
> >
> > diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
> > index ddae738d56..b59d321fb7 100644
> > --- a/hw/char/riscv_htif.c
> > +++ b/hw/char/riscv_htif.c
> > @@ -228,13 +228,25 @@ static const MemoryRegionOps htif_mm_ops = {
> >  .write = htif_mm_write,
> >  };
> >
> > +bool htif_uses_elf_symbols(void)
> > +{
> > +return (address_symbol_set == 3) ? true : false;
> > +}
> > +
> >  HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion 
> > *main_mem,
> > -CPURISCVState *env, Chardev *chr)
> > +CPURISCVState *env, Chardev *chr, uint64_t nonelf_base)
> >  {
> > -uint64_t base = MIN(tohost_addr, fromhost_addr);
> > -uint64_t size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
> > -uint64_t tohost_offset = tohost_addr - base;
> > -uint64_t fromhost_offset = fromhost_addr - base;
> > +uint64_t base, size, tohost_offset, fromhost_offset;
> > +
> > +if (address_symbol_set != 3) {
>
> Why not use htif_uses_elf_symbols() ?

Ahh, yes.

I should have used htif_uses_elf_symbols() here. I will update
it in the next revision.

Regards,
Anup

>
> Alistair
>
> > +fromhost_addr = nonelf_base;
> > +tohost_addr = nonelf_base + 8;
> > +}
> > +
> > +base = MIN(tohost_addr, fromhost_addr);
> > +size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
> > +tohost_offset = tohost_addr - base;
> > +fromhost_offset = fromhost_addr - base;
> >
> >  HTIFState *s = g_malloc0(sizeof(HTIFState));
> >  s->address_space = address_space;
> > @@ -249,12 +261,11 @@ HTIFState *htif_mm_init(MemoryRegion *address_space, 
> > MemoryRegion *main_mem,
> >  qemu_chr_fe_init(>chr, chr, _abort);
> >  qemu_chr_fe_set_handlers(>chr, htif_can_recv, htif_recv, htif_event,
> >  htif_be_change, s, NULL, true);
> > -if (address_symbol_set == 3) {
> > -memory_region_init_io(>mmio, NULL, _mm_ops, s,
> > -  TYPE_HTIF_UART, size);
> > -memory_region_add_subregion_overlap(address_space, base,
> > ->mmio, 1);
> > -}
> > +
> > +memory_region_init_io(>mmio, NULL, _mm_ops, s,
> > +  TYPE_HTIF_UART, size);
> > +memory_region_add_subregion_overlap(address_space, base,
> > +>mmio, 1);
> >
> >  return s;
> >  }
> > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> > index 288d69cd9f..597df4c288 100644
> > --- a/hw/riscv/spike.c
> > +++ b/hw/riscv/spike.c
> > @@ -42,6 +42,7 @@
> >
> >  static const MemMapEntry spike_memmap[] = {
> >  [SPIKE_MROM] = { 0x1000, 0xf000 },
> > +[SPIKE_HTIF] = {  0x100, 0x1000 },
> >  [SPIKE_CLINT] ={  0x200,0x1 },
> >  [SPIKE_DRAM] = { 0x8000,0x0 },
> >  };
> > @@ -75,6 +76,10 @@ static void create_fdt(SpikeState *s, const MemMapEntry 
> > *memmap,
> >
> >  qemu_fdt_add_subnode(fdt, "/htif");
> >  qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
> > +if (!htif_uses_elf_symbols()) {
> > +qemu_fdt_setprop_cells(fdt, "/htif", "reg",
> > +0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size);
> > +}
> >
> >  qemu_fdt_add_subnode(fdt, "/soc");
> >  qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
> > @@ -172,6 +177,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry 
> > *memmap,
> >  if (cmdline) {
> >  qemu_fdt_add_subnode(fdt, "/chosen");
> >  qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> > +qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
> >  }
> >  }
> >
> > @@ -241,10 +247,6 @@ static void spike_board_init(MachineState *machine)
> >  memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
> >  machine->ram);
> >
> > -/* create device tree */
> > -create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
> > -   riscv_is_32bit(>soc[0]));
> > -
> >  /* boot rom */
> >  

Re: [PATCH] hw/riscv: spike: Allow using binary firmware as bios

[Alistair Francis]

On Sat, Jan 15, 2022 at 2:18 AM Anup Patel  wrote:
>
> Currently, we have to use OpenSBI firmware ELF as bios for the spike
> machine because the HTIF console requires ELF for parsing "fromhost"
> and "tohost" symbols.
>
> The latest OpenSBI can now optionally pick-up HTIF register address
> from HTIF DT node so using this feature spike machine can now use
> OpenSBI firmware BIN as bios.

Cool!

I think that means we can remove the elfs from QEMU.

>
> Signed-off-by: Anup Patel 
> ---
>  hw/char/riscv_htif.c | 33 +++--
>  hw/riscv/spike.c | 41 ++--
>  include/hw/char/riscv_htif.h |  5 -
>  include/hw/riscv/spike.h |  1 +
>  4 files changed, 52 insertions(+), 28 deletions(-)
>
> diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
> index ddae738d56..b59d321fb7 100644
> --- a/hw/char/riscv_htif.c
> +++ b/hw/char/riscv_htif.c
> @@ -228,13 +228,25 @@ static const MemoryRegionOps htif_mm_ops = {
>  .write = htif_mm_write,
>  };
>
> +bool htif_uses_elf_symbols(void)
> +{
> +return (address_symbol_set == 3) ? true : false;
> +}
> +
>  HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
> -CPURISCVState *env, Chardev *chr)
> +CPURISCVState *env, Chardev *chr, uint64_t nonelf_base)
>  {
> -uint64_t base = MIN(tohost_addr, fromhost_addr);
> -uint64_t size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
> -uint64_t tohost_offset = tohost_addr - base;
> -uint64_t fromhost_offset = fromhost_addr - base;
> +uint64_t base, size, tohost_offset, fromhost_offset;
> +
> +if (address_symbol_set != 3) {

Why not use htif_uses_elf_symbols() ?

Alistair

> +fromhost_addr = nonelf_base;
> +tohost_addr = nonelf_base + 8;
> +}
> +
> +base = MIN(tohost_addr, fromhost_addr);
> +size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
> +tohost_offset = tohost_addr - base;
> +fromhost_offset = fromhost_addr - base;
>
>  HTIFState *s = g_malloc0(sizeof(HTIFState));
>  s->address_space = address_space;
> @@ -249,12 +261,11 @@ HTIFState *htif_mm_init(MemoryRegion *address_space, 
> MemoryRegion *main_mem,
>  qemu_chr_fe_init(>chr, chr, _abort);
>  qemu_chr_fe_set_handlers(>chr, htif_can_recv, htif_recv, htif_event,
>  htif_be_change, s, NULL, true);
> -if (address_symbol_set == 3) {
> -memory_region_init_io(>mmio, NULL, _mm_ops, s,
> -  TYPE_HTIF_UART, size);
> -memory_region_add_subregion_overlap(address_space, base,
> ->mmio, 1);
> -}
> +
> +memory_region_init_io(>mmio, NULL, _mm_ops, s,
> +  TYPE_HTIF_UART, size);
> +memory_region_add_subregion_overlap(address_space, base,
> +>mmio, 1);
>
>  return s;
>  }
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 288d69cd9f..597df4c288 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -42,6 +42,7 @@
>
>  static const MemMapEntry spike_memmap[] = {
>  [SPIKE_MROM] = { 0x1000, 0xf000 },
> +[SPIKE_HTIF] = {  0x100, 0x1000 },
>  [SPIKE_CLINT] ={  0x200,0x1 },
>  [SPIKE_DRAM] = { 0x8000,0x0 },
>  };
> @@ -75,6 +76,10 @@ static void create_fdt(SpikeState *s, const MemMapEntry 
> *memmap,
>
>  qemu_fdt_add_subnode(fdt, "/htif");
>  qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
> +if (!htif_uses_elf_symbols()) {
> +qemu_fdt_setprop_cells(fdt, "/htif", "reg",
> +0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size);
> +}
>
>  qemu_fdt_add_subnode(fdt, "/soc");
>  qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
> @@ -172,6 +177,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry 
> *memmap,
>  if (cmdline) {
>  qemu_fdt_add_subnode(fdt, "/chosen");
>  qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> +qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
>  }
>  }
>
> @@ -241,10 +247,6 @@ static void spike_board_init(MachineState *machine)
>  memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
>  machine->ram);
>
> -/* create device tree */
> -create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
> -   riscv_is_32bit(>soc[0]));
> -
>  /* boot rom */
>  memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
> memmap[SPIKE_MROM].size, _fatal);
> @@ -266,6 +268,7 @@ static void spike_board_init(MachineState *machine)
>  htif_symbol_callback);
>  }
>
> +/* Load kernel */
>  if (machine->kernel_filename) {
>  kernel_start_addr = riscv_calc_kernel_start_addr(>soc[0],
>   firmware_end_addr);
> 

Re: [PATCH 1/2] python: introduce qmp-shell-wrap convenience tool

[Philippe Mathieu-Daudé via]

On 18/1/22 00:27, John Snow wrote:

On Mon, Jan 17, 2022 at 9:11 AM Daniel P. Berrangé  wrote:


With the current 'qmp-shell' tool developers must first spawn QEMU with
a suitable -qmp arg and then spawn qmp-shell in a separate terminal
pointing to the right socket.

With 'qmp-shell-wrap' developers can ignore QMP sockets entirely and
just pass the QEMU command and arguments they want. The program will
listen on a UNIX socket and tell QEMU to connect QMP to that.

For example, this:

  # qmp-shell-wrap -- qemu-system-x86_64 -display none

Is roughly equivalent of running:

  # qemu-system-x86_64 -display none -qmp qmp-shell-1234 &
  # qmp-shell qmp-shell-1234

Except that 'qmp-shell-wrap' switches the socket peers around so that
it is the UNIX socket server and QEMU is the socket client. This makes
QEMU reliably go away when qmp-shell-wrap exits, closing the server
socket.

Signed-off-by: Daniel P. Berrangé 
---
  python/qemu/qmp/qmp_shell.py | 61 +---
  scripts/qmp/qmp-shell-wrap   | 11 +++
  2 files changed, 68 insertions(+), 4 deletions(-)
  create mode 100755 scripts/qmp/qmp-shell-wrap



diff --git a/scripts/qmp/qmp-shell-wrap b/scripts/qmp/qmp-shell-wrap
new file mode 100755
index 00..9e94da114f
--- /dev/null
+++ b/scripts/qmp/qmp-shell-wrap
@@ -0,0 +1,11 @@
+#!/usr/bin/env python3
+
+import os
+import sys
+
+sys.path.append(os.path.join(os.path.dirname(__file__), '..', '..', 'python'))
+from qemu.qmp import qmp_shell
+
+
+if __name__ == '__main__':
+qmp_shell.main_wrap()
--
2.33.1



Adds some new failures to the python linters; try "make check-dev" in
the python sub-dir.

... Though, due to a bug in avocado, this helpfully doesn't actually
show you the failure output right now ...

making this little edit should fix that, sorry for the inconvenience here.

diff --git a/python/avocado.cfg b/python/avocado.cfg
index c7722e7ecd..a460420059 100644
--- a/python/avocado.cfg
+++ b/python/avocado.cfg
@@ -1,5 +1,5 @@
  [run]
-test_runner = runner
+test_runner = nrunner


Cc'ing Beraldo, Willian once told me the nrunner switch was scheduled
for QEMU next release.

Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64

[Alistair Francis]

On Tue, Jan 18, 2022 at 1:31 PM Anup Patel  wrote:
>
> On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li  wrote:
> >
> > From: Guo Ren 
> >
> > Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
> > need to ignore them. They cannot be a part of ppn.
> >
> > 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
> >4.4 Sv39: Page-Based 39-bit Virtual-Memory System
> >4.5 Sv48: Page-Based 48-bit Virtual-Memory System
> >
> > 2: 
> > https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf
> >
> > Signed-off-by: Guo Ren 
> > Tested-by: Bin Meng 
> > Reviewed-by: Liu Zhiwei 
> > Reviewed-by: Bin Meng 
> > Reviewed-by: Alistair Francis 
> > ---
> >  target/riscv/cpu_bits.h   | 7 +++
> >  target/riscv/cpu_helper.c | 2 +-
> >  2 files changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > index 5a6d49aa64..282cd8eecd 100644
> > --- a/target/riscv/cpu_bits.h
> > +++ b/target/riscv/cpu_bits.h
> > @@ -490,6 +490,13 @@ typedef enum {
> >  /* Page table PPN shift amount */
> >  #define PTE_PPN_SHIFT   10
> >
> > +/* Page table PPN mask */
> > +#if defined(TARGET_RISCV32)
> > +#define PTE_PPN_MASK0xUL
> > +#elif defined(TARGET_RISCV64)
> > +#define PTE_PPN_MASK0x3fULL
> > +#endif
> > +
>
> Going forward we should avoid using target specific "#if"
> so that we can use the same qemu-system-riscv64 for both
> RV32 and RV64.
>
> >  /* Leaf page shift amount */
> >  #define PGSHIFT 12
> >
> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > index 434a83e66a..26608ddf1c 100644
> > --- a/target/riscv/cpu_helper.c
> > +++ b/target/riscv/cpu_helper.c
> > @@ -619,7 +619,7 @@ restart:
> >  return TRANSLATE_FAIL;
> >  }
> >
> > -hwaddr ppn = pte >> PTE_PPN_SHIFT;
> > +hwaddr ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;
>
> Rather than using "#if", please use "xlen" comparison to extract
> PPN correctly from PTE.

This will need to be dynamic based on get_xl()

It does look like we should check the existence of the extensions though:

"Bit 63 is reserved for use by the Svnapot extension in Chapter 5. If
Svnapot is not implemented, bit 63 remains reserved and must be zeroed
by software for forward compatibility, or else a page-fault exception
is raised. Bits 62–61 are reserved for use by the Svpbmt extension in
Chapter 6. If Svpbmt is not implemented, bits 62–61 remain reserved
and must be zeroed by software for forward compatibility, or else a
page-fault exception is raised."

Alistair

>
> Regards,
> Anup
>
> >
> >  if (!(pte & PTE_V)) {
> >  /* Invalid PTE */
> > --
> > 2.17.1
> >
>

Re: [PATCH] target/riscv: Ignore reserved bits in PTE for RV64

[Alistair Francis]

On Mon, Jan 17, 2022 at 5:18 PM  wrote:
>
> From: Guo Ren 
>
> Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
> need to ignore them. They cannot be a part of ppn.
>
> 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
>4.4 Sv39: Page-Based 39-bit Virtual-Memory System
>4.5 Sv48: Page-Based 48-bit Virtual-Memory System
>
> 2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf
>
> Signed-off-by: Guo Ren 
> Tested-by: Bin Meng 
> Reviewed-by: Liu Zhiwei 
> Reviewed-by: Bin Meng 
> Reviewed-by: Alistair Francis 
> Cc: Weiwei Li 
> Cc: Junqiang Wang 
>
> ---
>  Changelog V7:
>   - Update svpbmt reason in commit log
>
>  Changelog V6:
>   - Add Reviewer: Alistair Francis
>
>  Changelog V5:
>   - Add Reviewer and Tester: Bin Meng
>
>  Changelog V4:
>   - Change title to Ignore not Bugfix
>   - Use PTE_PPN_MASK for RV32 and RV64
>
>  Changelog V3:
>   - Use UUL define for PTE_RESERVED
>   - Keep ppn >> PTE_PPN_SHIFT
>
>  Changelog V2:
>   - Bugfix pte destroyed cause boot fail
>   - Change to AND with a mask instead of shifting both directions
> ---
>  target/riscv/cpu_bits.h   | 7 +++
>  target/riscv/cpu_helper.c | 2 +-
>  2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 5106f0e769..fa22839d54 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -479,6 +479,13 @@ typedef enum {
>  /* Page table PPN shift amount */
>  #define PTE_PPN_SHIFT   10
>
> +/* Page table PPN mask */
> +#if defined(TARGET_RISCV32)
> +#define PTE_PPN_MASK0xUL
> +#elif defined(TARGET_RISCV64)
> +#define PTE_PPN_MASK0x3fULL
> +#endif
> +
>  /* Leaf page shift amount */
>  #define PGSHIFT 12
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 7945f687b4..06c5403fdd 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -619,7 +619,7 @@ restart:
>  return TRANSLATE_FAIL;
>  }
>
> -hwaddr ppn = pte >> PTE_PPN_SHIFT;
> +hwaddr ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;

This will need to be dynamic based on get_xl()

It does look like we should check the existence of the extensions though:

"Bit 63 is reserved for use by the Svnapot extension in Chapter 5. If
Svnapot is not implemented, bit 63 remains reserved and must be zeroed
by software for forward compatibility, or else a page-fault exception
is raised. Bits 62–61 are reserved for use by the Svpbmt extension in
Chapter 6. If Svpbmt is not implemented, bits 62–61 remain reserved
and must be zeroed by software for forward compatibility, or else a
page-fault exception is raised."

Alistair

>
>  if (!(pte & PTE_V)) {
>  /* Invalid PTE */
> --
> 2.25.1
>
>

Re: [PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns

[Alistair Francis]

On Tue, Jan 18, 2022 at 11:59 AM  wrote:
>
> From: Frank Chang 
>
> All Zve* extensions support all vector load and store instructions,
> except Zve64* extensions do not support EEW=64 for index values when
> XLEN=32.
>
> Signed-off-by: Frank Chang 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 19 +++
>  1 file changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 5b47729a21..0bf41aaa1e 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -263,10 +263,21 @@ static bool vext_check_st_index(DisasContext *s, int 
> vd, int vs2, int nf,
>  uint8_t eew)
>  {
>  int8_t emul = eew - s->sew + s->lmul;
> -return (emul >= -3 && emul <= 3) &&
> -require_align(vs2, emul) &&
> -require_align(vd, s->lmul) &&
> -require_nf(vd, nf, s->lmul);
> +bool ret = (emul >= -3 && emul <= 3) &&
> +   require_align(vs2, emul) &&
> +   require_align(vd, s->lmul) &&
> +   require_nf(vd, nf, s->lmul);
> +
> +/*
> + * All Zve* extensions support all vector load and store instructions,
> + * except Zve64* extensions do not support EEW=64 for index values
> + * when XLEN=32. (Section 18.2)
> + */
> +if (get_xl(s) == MXL_RV32) {
> +ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true);
> +}
> +
> +return ret;
>  }
>
>  /*
> --
> 2.31.1
>
>

Re: [PATCH v4 0/7] support subsets of scalar crypto extension

[Alistair Francis]

On Tue, Jan 11, 2022 at 1:54 PM Weiwei Li  wrote:
>
> This patchset implements RISC-V scalar crypto extension v1.0.0 version 
> instructions.
> Partial instructions are reused from B-extension.
>
> Specification:
> https://github.com/riscv/riscv-crypto
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v4
>
> To test rvk implementation,  specify cpu argument with 'zks=true,zkn=true'
> or
> "zbkb=true,zbkc=true,zbkx=true,zknd=true,zkne=true,zknh=true,zksed=true,zksh=true,zkr=true"
>  to enable  K-extension support.  This implementation can pass the ACT tests
> for K with our extended act support for qemu (available at
> https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v4-with-act)
>
> v4:
> * drop "x-" in exposed properties
> * delete unrelated changes
>
> v3:
> * add extension check for SEED csr access
>
> v2:
> * optimize implementation for brev8, xperm, zip, unzip
> * use aes related sbox array from crypto/aes.h
> * move sm4_sbox to crypto/sm4.c, and share it with target/arm
>
> Weiwei Li (7):
>   target/riscv: rvk: add cfg properties for zbk* and zk*
>   target/riscv: rvk: add implementation of instructions for Zbk*
>   crypto include/crypto target/arm: move sm4_sbox to crypto
>   target/riscv: rvk: add implementation of instructions for Zk*
>   target/riscv: rvk: add CSR support for Zkr
>   disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
>   target/riscv: rvk: expose zbk* and zk* properties

Thanks for the patches!

Overall this looks good, just some small comments on the individual patches.

For the next version do you mind splitting the patches up a little bit
more? That will make it easier and faster to review

Alistair

>
>  crypto/meson.build  |   1 +
>  crypto/sm4.c|  49 +++
>  disas/riscv.c   | 170 +
>  include/crypto/sm4.h|   6 +
>  target/arm/crypto_helper.c  |  36 +-
>  target/riscv/bitmanip_helper.c  |  74 
>  target/riscv/cpu.c  |  37 ++
>  target/riscv/cpu.h  |  13 +
>  target/riscv/cpu_bits.h |   9 +
>  target/riscv/crypto_helper.c| 446 ++
>  target/riscv/csr.c  |  74 
>  target/riscv/helper.h   |  42 +++
>  target/riscv/insn32.decode  |  94 -
>  target/riscv/insn_trans/trans_rvb.c.inc | 127 ++-
>  target/riscv/insn_trans/trans_rvk.c.inc | 467 
>  target/riscv/meson.build|   3 +-
>  target/riscv/pmp.h  |   8 +-
>  target/riscv/translate.c|   8 +
>  18 files changed, 1594 insertions(+), 70 deletions(-)
>  create mode 100644 crypto/sm4.c
>  create mode 100644 include/crypto/sm4.h
>  create mode 100644 target/riscv/crypto_helper.c
>  create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
>
> --
> 2.17.1
>
>

Re: [PATCH v4 2/7] target/riscv: rvk: add implementation of instructions for Zbk*

[Alistair Francis]

On Tue, Jan 11, 2022 at 1:56 PM Weiwei Li  wrote:
>
>- reuse partial instructions of Zbb/Zbc extensions
>- add brev8, packh, unzip, zip, etc.
>
> Signed-off-by: Weiwei Li 
> Signed-off-by: Junqiang Wang 
> ---
>  target/riscv/bitmanip_helper.c  |  74 ++
>  target/riscv/helper.h   |   5 +
>  target/riscv/insn32.decode  |  52 ++
>  target/riscv/insn_trans/trans_rvb.c.inc | 127 +---
>  target/riscv/translate.c|   7 ++
>  5 files changed, 234 insertions(+), 31 deletions(-)
>
> diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
> index f1b5e5549f..dc3dcf685a 100644
> --- a/target/riscv/bitmanip_helper.c
> +++ b/target/riscv/bitmanip_helper.c
> @@ -49,3 +49,77 @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong 
> rs2)
>
>  return result;
>  }
> +
> +static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
> +{
> +return ((x & mask) << shift) | ((x & ~mask) >> shift);
> +}
> +
> +target_ulong HELPER(brev8)(target_ulong rs1)
> +{
> +target_ulong x = rs1;
> +x = do_swap(x, 0xull, 1);
> +x = do_swap(x, 0xull, 2);
> +x = do_swap(x, 0x0f0f0f0f0f0f0f0full, 4);
> +return x;
> +}
> +
> +static inline target_ulong do_xperm(target_ulong rs1, target_ulong rs2,
> +uint32_t sz_log2)
> +{
> +target_ulong r = 0;
> +target_ulong sz = 1LL << sz_log2;
> +target_ulong mask = (1LL << sz) - 1;
> +for (int i = 0; i < TARGET_LONG_BITS; i += sz) {
> +target_ulong pos = ((rs2 >> i) & mask) << sz_log2;
> +if (pos < sizeof(target_ulong) * 8) {
> +r |= ((rs1 >> pos) & mask) << i;
> +}
> +}
> +return r;
> +}
> +
> +target_ulong HELPER(xperm4)(target_ulong rs1, target_ulong rs2)
> +{
> +return do_xperm(rs1, rs2, 2);
> +}
> +
> +target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
> +{
> +return do_xperm(rs1, rs2, 3);
> +}
> +
> +static const uint64_t shuf_masks[] = {
> +dup_const(MO_8, 0x44),
> +dup_const(MO_8, 0x30),
> +dup_const(MO_16, 0x0f00),
> +dup_const(MO_32, 0xff)
> +};
> +
> +static inline target_ulong do_shuf_stage(target_ulong src, uint64_t maskL,
> + uint64_t maskR, int shift)
> +{
> +target_ulong x = src & ~(maskL | maskR);
> +x |= ((src << shift) & maskL) | ((src >> shift) & maskR);
> +return x;
> +}
> +
> +target_ulong HELPER(unzip)(target_ulong rs1)
> +{
> +target_ulong x = rs1;
> +x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
> +x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
> +x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
> +x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
> +return x;
> +}
> +
> +target_ulong HELPER(zip)(target_ulong rs1)
> +{
> +target_ulong x = rs1;
> +x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
> +x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
> +x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
> +x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
> +return x;
> +}
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 6cf6d6ce98..2bd6ac8280 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -66,6 +66,11 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
>  /* Bitmanip */
>  DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
>  DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> +DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> +DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> +DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
> +DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
> +DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
>
>  /* Floating Point - Half Precision */
>  DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 5bbedc254c..7491b2d562 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -717,8 +717,22 @@ sh2add_uw  001 .. 100 . 0111011 @r
>  sh3add_uw  001 .. 110 . 0111011 @r
>  slli_uw1  001 . 0011011 @sh
>
> -# *** RV32 Zbb Standard Extension ***
> +# *** RV32 Zbb/Zbkb Standard Extension ***
>  andn   010 .. 111 . 0110011 @r
> +rol011 .. 001 . 0110011 @r
> +ror011 .. 101 . 0110011 @r
> +rori   01100  101 . 0010011 @sh
> +# The encoding for rev8 differs between RV32 and RV64.
> +# rev8_32 denotes the RV32 variant.
> +rev8_32011010 011000 . 101 . 0010011 @r2

Why move these?

Alistair

> +# The encoding for zext.h differs between RV32 and RV64.
> +# zext_h_32 denotes the RV32 

Re: [PATCH v4 5/7] target/riscv: rvk: add CSR support for Zkr

[Alistair Francis]

On Tue, Jan 11, 2022 at 1:53 PM Weiwei Li  wrote:
>
>- add SEED CSR
>- add USEED, SSEED fields for MSECCFG CSR
>
> Co-authored-by: Ruibo Lu 
> Co-authored-by: Zewen Ye 
> Signed-off-by: Weiwei Li 
> Signed-off-by: Junqiang Wang 
> ---
>  target/riscv/cpu_bits.h |  9 +
>  target/riscv/csr.c  | 74 +
>  target/riscv/pmp.h  |  8 +++--
>  3 files changed, 88 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 5a6d49aa64..65c708622b 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -374,6 +374,9 @@
>  #define CSR_VSPMMASK0x2c1
>  #define CSR_VSPMBASE0x2c2
>
> +/* Crypto Extension */
> +#define CSR_SEED   0x015
> +
>  /* mstatus CSR bits */
>  #define MSTATUS_UIE 0x0001
>  #define MSTATUS_SIE 0x0002
> @@ -628,4 +631,10 @@ typedef enum RISCVException {
>  #define UMTE_U_PM_INSN  U_PM_INSN
>  #define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
>
> +/* seed CSR bits */
> +#define SEED_OPST(0b11 << 30)
> +#define SEED_OPST_BIST   (0b00 << 30)
> +#define SEED_OPST_WAIT   (0b01 << 30)
> +#define SEED_OPST_ES16   (0b10 << 30)
> +#define SEED_OPST_DEAD   (0b11 << 30)
>  #endif
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index adb3d4381d..9d93e72f68 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -22,6 +22,8 @@
>  #include "cpu.h"
>  #include "qemu/main-loop.h"
>  #include "exec/exec-all.h"
> +#include "qemu/guest-random.h"
> +#include "qapi/error.h"
>
>  /* CSR function table public API */
>  void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
> @@ -222,6 +224,38 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
>  }
>  #endif
>
> +/* Predicates */
> +static RISCVException seed(CPURISCVState *env, int csrno)
> +{
> +RISCVCPU *cpu = env_archcpu(env);

New line between declarations and code please

> +if (!cpu->cfg.ext_zkr) {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +#if !defined(CONFIG_USER_ONLY)
> +if (riscv_has_ext(env, RVS) && riscv_has_ext(env, RVH)) {
> +/* Hypervisor extension is supported */
> +if (riscv_cpu_virt_enabled(env) && (env->priv != PRV_M)) {
> +if (env->mseccfg & MSECCFG_SSEED) {
> +return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> +} else {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +}
> +}
> +if (env->priv == PRV_M) {
> +return RISCV_EXCP_NONE;
> +} else if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) {
> +return RISCV_EXCP_NONE;
> +} else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) {
> +return RISCV_EXCP_NONE;
> +} else {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +#else
> +return RISCV_EXCP_NONE;
> +#endif
> +}
> +
>  /* User Floating-Point CSRs */
>  static RISCVException read_fflags(CPURISCVState *env, int csrno,
>target_ulong *val)
> @@ -1785,6 +1819,39 @@ static RISCVException write_upmbase(CPURISCVState 
> *env, int csrno,
>
>  #endif
>
> +/* Crypto Extension */
> +static int read_seed(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> +*val = 0;
> +uint32_t return_status =  SEED_OPST_ES16;

Keep variable declarations first please

> +*val = (*val) | return_status;
> +if (return_status == SEED_OPST_ES16) {
> +uint16_t random_number;
> +Error *err = NULL;
> +if (qemu_guest_getrandom(_number, sizeof(random_number),
> + ) < 0) {

You can use qemu_guest_getrandom_nofail() instead and then not worry
about this error handling.



> +qemu_log_mask(LOG_UNIMP, "Seed: Crypto failure: %s",
> +  error_get_pretty(err));
> +error_free(err);
> +return -1;
> +}
> +*val = (*val) | random_number;
> +} else if (return_status == SEED_OPST_BIST) {
> +/* Do nothing */
> +} else if (return_status == SEED_OPST_WAIT) {
> +/* Do nothing */
> +} else if (return_status == SEED_OPST_DEAD) {
> +/* Do nothing */
> +}
> +return 0;

RISCV_EXCP_NONE instead of 0

> +}
> +
> +static RISCVException write_seed(CPURISCVState *env, int csrno,
> +target_ulong val)
> +{
> +return RISCV_EXCP_NONE;
> +}
> +
>  /*
>   * riscv_csrrw - read and/or update control and status register
>   *
> @@ -1823,6 +1890,10 @@ static inline RISCVException 
> riscv_csrrw_check(CPURISCVState *env,
>  return RISCV_EXCP_ILLEGAL_INST;
>  }
>
> +if (!write_mask && (csrno == CSR_SEED)) {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}

I think it would be better to remove this and use a rmw_*() function
instead. Then the read/write 

Re: [PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties

[Alistair Francis]

On Tue, Jan 11, 2022 at 1:53 PM Weiwei Li  wrote:
>
> Signed-off-by: Weiwei Li 
> Signed-off-by: Junqiang Wang 
> ---
>  target/riscv/cpu.c | 14 ++
>  1 file changed, 14 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b487a8282c..628a782ba9 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -694,9 +694,23 @@ static Property riscv_cpu_properties[] = {
>  DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
>  DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
>  DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
> +DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
> +DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
> +DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
>  DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> +DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
> +DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
> +DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
> +DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
> +DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
> +DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
> +DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
> +DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
> +DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
> +DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
>
>  /* These are experimental so mark with 'x-' */
> +DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),

Looks like a rebase error

Alistair

>  DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
>  /* ePMP 0.9.3 */
>  DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> --
> 2.17.1
>
>

Re: [PATCH v4 4/7] target/riscv: rvk: add implementation of instructions for Zk*

[Alistair Francis]

On Tue, Jan 11, 2022 at 2:01 PM Weiwei Li  wrote:
>
> Co-authored-by: Ruibo Lu 
> Co-authored-by: Zewen Ye 
> Signed-off-by: Weiwei Li 
> Signed-off-by: Junqiang Wang 
> ---
>  target/riscv/crypto_helper.c| 446 ++
>  target/riscv/helper.h   |  37 ++
>  target/riscv/insn32.decode  |  42 +++
>  target/riscv/insn_trans/trans_rvk.c.inc | 467 
>  target/riscv/meson.build|   3 +-
>  target/riscv/translate.c|   1 +
>  6 files changed, 995 insertions(+), 1 deletion(-)
>  create mode 100644 target/riscv/crypto_helper.c
>  create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
>
> diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
> new file mode 100644
> index 00..344eea4287
> --- /dev/null
> +++ b/target/riscv/crypto_helper.c
> @@ -0,0 +1,446 @@
> +/*
> + * RISC-V Crypto Emulation Helpers for QEMU.
> + *
> + * Copyright (c) 2021 Ruibo Lu, luruibo2...@163.com
> + * Copyright (c) 2021 Zewen Ye, lust...@foxmail.com
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along 
> with
> + * this program.  If not, see .
> + */
> +
> +#include "qemu/osdep.h"
> +#include "cpu.h"
> +#include "exec/exec-all.h"
> +#include "exec/helper-proto.h"
> +#include "crypto/aes.h"
> +#include "crypto/sm4.h"
> +
> +#define AES_XTIME(a) \
> +((a << 1) ^ ((a & 0x80) ? 0x1b : 0))
> +
> +#define AES_GFMUL(a, b) (( \
> +(((b) & 0x1) ?  (a)   : 0) ^ \
> +(((b) & 0x2) ? AES_XTIME(a)   : 0) ^ \
> +(((b) & 0x4) ?   AES_XTIME(AES_XTIME(a))  : 0) ^ \
> +(((b) & 0x8) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0)) & 0xFF)
> +
> +#define BY(X, I) ((X >> (8 * I)) & 0xFF)
> +
> +#define AES_SHIFROWS_LO(RS1, RS2) ( \
> +(((RS1 >> 24) & 0xFF) << 56) | \
> +(((RS2 >> 48) & 0xFF) << 48) | \
> +(((RS2 >>  8) & 0xFF) << 40) | \
> +(((RS1 >> 32) & 0xFF) << 32) | \
> +(((RS2 >> 56) & 0xFF) << 24) | \
> +(((RS2 >> 16) & 0xFF) << 16) | \
> +(((RS1 >> 40) & 0xFF) <<  8) | \
> +(((RS1 >>  0) & 0xFF) <<  0))
> +
> +#define AES_INVSHIFROWS_LO(RS1, RS2) ( \
> +(((RS2 >> 24) & 0xFF) << 56) | \
> +(((RS2 >> 48) & 0xFF) << 48) | \
> +(((RS1 >>  8) & 0xFF) << 40) | \
> +(((RS1 >> 32) & 0xFF) << 32) | \
> +(((RS1 >> 56) & 0xFF) << 24) | \
> +(((RS2 >> 16) & 0xFF) << 16) | \
> +(((RS2 >> 40) & 0xFF) <<  8) | \
> +(((RS1 >>  0) & 0xFF) <<  0))
> +
> +#define AES_MIXBYTE(COL, B0, B1, B2, B3) ( \
> +  BY(COL, B3) ^ \
> +  BY(COL, B2) ^ \
> +AES_GFMUL(BY(COL, B1), 3) ^ \
> +AES_GFMUL(BY(COL, B0), 2)   \
> +)
> +
> +#define AES_MIXCOLUMN(COL) ( \
> +AES_MIXBYTE(COL, 3, 0, 1, 2) << 24 | \
> +AES_MIXBYTE(COL, 2, 3, 0, 1) << 16 | \
> +AES_MIXBYTE(COL, 1, 2, 3, 0) <<  8 | \
> +AES_MIXBYTE(COL, 0, 1, 2, 3) <<  0   \
> +)
> +
> +#define AES_INVMIXBYTE(COL, B0, B1, B2, B3) ( \
> +AES_GFMUL(BY(COL, B3), 0x9) ^ \
> +AES_GFMUL(BY(COL, B2), 0xd) ^ \
> +AES_GFMUL(BY(COL, B1), 0xb) ^ \
> +AES_GFMUL(BY(COL, B0), 0xe)   \
> +)
> +
> +#define AES_INVMIXCOLUMN(COL) ( \
> +AES_INVMIXBYTE(COL, 3, 0, 1, 2) << 24 | \
> +AES_INVMIXBYTE(COL, 2, 3, 0, 1) << 16 | \
> +AES_INVMIXBYTE(COL, 1, 2, 3, 0) <<  8 | \
> +AES_INVMIXBYTE(COL, 0, 1, 2, 3) <<  0   \
> +)
> +
> +static inline uint32_t aes_mixcolumn_byte(uint8_t x, bool fwd)
> +{
> +uint32_t u;
> +if (fwd) {
> +u = (AES_GFMUL(x, 3) << 24) |
> +  (x << 16) |
> +  (x <<  8) |
> +(AES_GFMUL(x, 2) <<  0);
> +} else {
> +u = (AES_GFMUL(x, 0xb) << 24) |
> +(AES_GFMUL(x, 0xd) << 16) |
> +(AES_GFMUL(x, 0x9) <<  8) |
> +(AES_GFMUL(x, 0xe) <<  0);
> +}
> +return u;
> +}
> +
> +#define XLEN (8 * sizeof(target_ulong))

I don't think this is used, but please don't hard coded xlen's.
Everything should be dynamic based on the CPU xlen.

It would also be great if you could split this patch up more. There is
a lot being added here.

Alistair

Re: [PATCH v7 15/23] target/riscv: Implement AIA IMSIC interface CSRs

[Frank Chang]

Anup Patel  於 2022年1月17日 週一 下午10:18寫道：

> From: Anup Patel 
>
> The AIA specification defines IMSIC interface CSRs for easy access
> to the per-HART IMSIC registers without using indirect xiselect and
> xireg CSRs. This patch implements the AIA IMSIC interface CSRs.
>
> Signed-off-by: Anup Patel 
> Signed-off-by: Anup Patel 
> ---
>  target/riscv/csr.c | 203 +
>  1 file changed, 203 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 7a787d3a3f..68e6009006 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -923,6 +923,16 @@ static int aia_xlate_vs_csrno(CPURISCVState *env, int
> csrno)
>  return CSR_VSISELECT;
>  case CSR_SIREG:
>  return CSR_VSIREG;
> +case CSR_SSETEIPNUM:
> +return CSR_VSSETEIPNUM;
> +case CSR_SCLREIPNUM:
> +return CSR_VSCLREIPNUM;
> +case CSR_SSETEIENUM:
> +return CSR_VSSETEIENUM;
> +case CSR_SCLREIENUM:
> +return CSR_VSCLREIENUM;
> +case CSR_STOPEI:
> +return CSR_VSTOPEI;
>  default:
>  return csrno;
>  };
> @@ -1075,6 +1085,178 @@ done:
>  return RISCV_EXCP_NONE;
>  }
>
> +static int rmw_xsetclreinum(CPURISCVState *env, int csrno, target_ulong
> *val,
> +target_ulong new_val, target_ulong wr_mask)
> +{
> +int ret = -EINVAL;
> +bool set, pend, virt;
> +target_ulong priv, isel, vgein, xlen, nval, wmask;
> +
> +/* Translate CSR number for VS-mode */
> +csrno = aia_xlate_vs_csrno(env, csrno);
> +
> +/* Decode register details from CSR number */
> +virt = set = pend = false;
> +switch (csrno) {
> +case CSR_MSETEIPNUM:
> +priv = PRV_M;
> +set = true;
> +pend = true;
> +break;
> +case CSR_MCLREIPNUM:
> +priv = PRV_M;
> +pend = true;
> +break;
> +case CSR_MSETEIENUM:
> +priv = PRV_M;
> +set = true;
> +break;
> +case CSR_MCLREIENUM:
> +priv = PRV_M;
> +break;
> +case CSR_SSETEIPNUM:
> +priv = PRV_S;
> +set = true;
> +pend = true;
> +break;
> +case CSR_SCLREIPNUM:
> +priv = PRV_S;
> +pend = true;
> +break;
> +case CSR_SSETEIENUM:
> +priv = PRV_S;
> +set = true;
> +break;
> +case CSR_SCLREIENUM:
> +priv = PRV_S;
> +break;
> +case CSR_VSSETEIPNUM:
> +priv = PRV_S;
> +virt = true;
> +set = true;
> +pend = true;
> +break;
> +case CSR_VSCLREIPNUM:
> +priv = PRV_S;
> +virt = true;
> +pend = true;
> +break;
> +case CSR_VSSETEIENUM:
> +priv = PRV_S;
> +virt = true;
> +set = true;
> +break;
> +case CSR_VSCLREIENUM:
> +priv = PRV_S;
> +virt = true;
> +break;
> +default:
> + goto done;
> +};
> +
> +/* IMSIC CSRs only available when machine implements IMSIC. */
> +if (!env->aia_ireg_rmw_fn[priv]) {
> +goto done;
> +}
> +
> +/* Find the selected guest interrupt file */
> +vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
> +
> +/* Selected guest interrupt file should be valid */
> +if (virt && (!vgein || env->geilen < vgein)) {
> +goto done;
> +}
> +
> +/* Set/Clear CSRs always read zero */
> +if (val) {
> +*val = 0;
> +}
> +
> +if (wr_mask) {
> +/* Get interrupt number */
> +new_val &= wr_mask;
> +
> +/* Find target interrupt pending/enable register */
> +xlen = riscv_cpu_mxl_bits(env);
> +isel = (new_val / xlen);
> +isel *= (xlen / IMSIC_EIPx_BITS);
> +isel += (pend) ? ISELECT_IMSIC_EIP0 : ISELECT_IMSIC_EIE0;
> +
> +/* Find the interrupt bit to be set/clear */
> +wmask = ((target_ulong)1) << (new_val % xlen);
> +nval = (set) ? wmask : 0;
> +
> +/* Call machine specific IMSIC register emulation */
> +ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
> + AIA_MAKE_IREG(isel, priv, virt,
> +   vgein, xlen),
> + NULL, nval, wmask);
> +} else {
> +ret = 0;
> +}
> +
> +done:
> +if (ret) {
> +return (riscv_cpu_virt_enabled(env) && virt) ?
> +   RISCV_EXCP_VIRT_INSTRUCTION_FAULT :
> RISCV_EXCP_ILLEGAL_INST;
> +}
> +return RISCV_EXCP_NONE;
> +}
> +
> +static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val,
> +  target_ulong new_val, target_ulong wr_mask)
> +{
> +bool virt;
> +int ret = -EINVAL;
> +target_ulong priv, vgein;
> +
> +/* Translate CSR number for VS-mode */
> +csrno = aia_xlate_vs_csrno(env, csrno);
> +
> +/* Decode register details from CSR number */
> +

Re: [PATCH v7 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation

[Frank Chang]

Anup Patel  於 2022年1月17日 週一 下午10:29寫道：

> From: Anup Patel 
>
> The RISC-V AIA (Advanced Interrupt Architecture) defines a new
> interrupt controller for MSIs (message signal interrupts) called
> IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC
> is per-HART device and also suppport virtualizaiton of MSIs using
> dedicated VS-level guest interrupt files.
>
> This patch adds device emulation for RISC-V AIA IMSIC which
> supports M-level, S-level, and VS-level MSIs.
>
> Signed-off-by: Anup Patel 
> Signed-off-by: Anup Patel 
> ---
>  hw/intc/Kconfig   |   3 +
>  hw/intc/meson.build   |   1 +
>  hw/intc/riscv_imsic.c | 448 ++
>  include/hw/intc/riscv_imsic.h |  68 ++
>  4 files changed, 520 insertions(+)
>  create mode 100644 hw/intc/riscv_imsic.c
>  create mode 100644 include/hw/intc/riscv_imsic.h
>
> diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
> index 528e77b4a6..ec8d4cec29 100644
> --- a/hw/intc/Kconfig
> +++ b/hw/intc/Kconfig
> @@ -73,6 +73,9 @@ config RISCV_ACLINT
>  config RISCV_APLIC
>  bool
>
> +config RISCV_IMSIC
> +bool
> +
>  config SIFIVE_PLIC
>  bool
>
> diff --git a/hw/intc/meson.build b/hw/intc/meson.build
> index 7466024402..5caa337654 100644
> --- a/hw/intc/meson.build
> +++ b/hw/intc/meson.build
> @@ -51,6 +51,7 @@ specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true:
> files('s390_flic_kvm.c'))
>  specific_ss.add(when: 'CONFIG_SH_INTC', if_true: files('sh_intc.c'))
>  specific_ss.add(when: 'CONFIG_RISCV_ACLINT', if_true:
> files('riscv_aclint.c'))
>  specific_ss.add(when: 'CONFIG_RISCV_APLIC', if_true:
> files('riscv_aplic.c'))
> +specific_ss.add(when: 'CONFIG_RISCV_IMSIC', if_true:
> files('riscv_imsic.c'))
>  specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true:
> files('sifive_plic.c'))
>  specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
>  specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XICS'],
> diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
> new file mode 100644
> index 00..18d2877832
> --- /dev/null
> +++ b/hw/intc/riscv_imsic.c
> @@ -0,0 +1,448 @@
> +/*
> + * RISC-V IMSIC (Incoming Message Signaled Interrupt Controller)
> + *
> + * Copyright (c) 2021 Western Digital Corporation or its affiliates.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
> for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> along with
> + * this program.  If not, see .
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "qemu/log.h"
> +#include "qemu/module.h"
> +#include "qemu/error-report.h"
> +#include "qemu/bswap.h"
> +#include "exec/address-spaces.h"
> +#include "hw/sysbus.h"
> +#include "hw/pci/msi.h"
> +#include "hw/boards.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/intc/riscv_imsic.h"
> +#include "hw/irq.h"
> +#include "target/riscv/cpu.h"
> +#include "target/riscv/cpu_bits.h"
> +#include "sysemu/sysemu.h"
> +#include "migration/vmstate.h"
> +
> +#define IMSIC_MMIO_PAGE_LE 0x00
> +#define IMSIC_MMIO_PAGE_BE 0x04
> +
> +#define IMSIC_MIN_ID   ((IMSIC_EIPx_BITS * 2) - 1)
> +#define IMSIC_MAX_ID   (IMSIC_TOPEI_IID_MASK)
> +
> +#define IMSIC_EISTATE_PENDING  (1U << 0)
> +#define IMSIC_EISTATE_ENABLED  (1U << 1)
> +#define IMSIC_EISTATE_ENPEND   (IMSIC_EISTATE_ENABLED | \
> +IMSIC_EISTATE_PENDING)
> +
> +static uint32_t riscv_imsic_topei(RISCVIMSICState *imsic, uint32_t page)
> +{
> +uint32_t i, max_irq, base;
> +
> +base = page * imsic->num_irqs;
> +max_irq = (imsic->eithreshold[page] &&
> +   (imsic->eithreshold[page] <= imsic->num_irqs)) ?
> +   imsic->eithreshold[page] : imsic->num_irqs;
> +for (i = 1; i < max_irq; i++) {
> +if ((imsic->eistate[base + i] & IMSIC_EISTATE_ENPEND) ==
> +IMSIC_EISTATE_ENPEND) {
> +return (i << IMSIC_TOPEI_IID_SHIFT) | i;
> +}
> +}
> +
> +return 0;
> +}
> +
> +static void riscv_imsic_update(RISCVIMSICState *imsic, uint32_t page)
> +{
> +if (imsic->eidelivery[page] && riscv_imsic_topei(imsic, page)) {
> +qemu_irq_raise(imsic->external_irqs[page]);
> +} else {
> +qemu_irq_lower(imsic->external_irqs[page]);
> +}
> +}
> +
> +static int riscv_imsic_eidelivery_rmw(RISCVIMSICState *imsic, uint32_t
> page,
> +  target_ulong *val,
> +  

Re: [PATCH v7 09/23] target/riscv: Implement AIA local interrupt priorities

[Frank Chang]

Anup Patel  於 2022年1月18日 週二 上午11:41寫道：

> On Tue, Jan 18, 2022 at 9:04 AM Frank Chang 
> wrote:
> >
> > Anup Patel  於 2022年1月17日 週一 下午10:28寫道：
> >>
> >> From: Anup Patel 
> >>
> >> The AIA spec defines programmable 8-bit priority for each local
> interrupt
> >> at M-level, S-level and VS-level so we extend local interrupt processing
> >> to consider AIA interrupt priorities. The AIA CSRs which help software
> >> configure local interrupt priorities will be added by subsequent
> patches.
> >>
> >> Signed-off-by: Anup Patel 
> >> Signed-off-by: Anup Patel 
> >> Reviewed-by: Alistair Francis 
> >> ---
> >>  target/riscv/cpu.c|  19 +++
> >>  target/riscv/cpu.h|  12 ++
> >>  target/riscv/cpu_helper.c | 242 ++
> >>  target/riscv/machine.c|   3 +
> >>  4 files changed, 255 insertions(+), 21 deletions(-)
> >>
> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> >> index 76f9786836..167d86eef7 100644
> >> --- a/target/riscv/cpu.c
> >> +++ b/target/riscv/cpu.c
> >> @@ -370,6 +370,10 @@ void restore_state_to_opc(CPURISCVState *env,
> TranslationBlock *tb,
> >>
> >>  static void riscv_cpu_reset(DeviceState *dev)
> >>  {
> >> +#ifndef CONFIG_USER_ONLY
> >> +uint8_t iprio;
> >> +int i, irq, rdzero;
> >> +#endif
> >>  CPUState *cs = CPU(dev);
> >>  RISCVCPU *cpu = RISCV_CPU(cs);
> >>  RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
> >> @@ -392,6 +396,21 @@ static void riscv_cpu_reset(DeviceState *dev)
> >>  env->miclaim = MIP_SGEIP;
> >>  env->pc = env->resetvec;
> >>  env->two_stage_lookup = false;
> >> +
> >> +/* Initialized default priorities of local interrupts. */
> >> +for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
> >> +iprio = riscv_cpu_default_priority(i);
> >> +env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio;
> >> +env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio;
> >> +env->hviprio[i] = 0;
> >> +}
> >> +i = 0;
> >> +while (!riscv_cpu_hviprio_index2irq(i, , )) {
> >> +if (!rdzero) {
> >> +env->hviprio[irq] = env->miprio[irq];
> >> +}
> >> +i++;
> >> +}
> >>  /* mmte is supposed to have pm.current hardwired to 1 */
> >>  env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
> >>  #endif
> >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> >> index cee70f8608..65d2b606fc 100644
> >> --- a/target/riscv/cpu.h
> >> +++ b/target/riscv/cpu.h
> >> @@ -190,6 +190,10 @@ struct CPURISCVState {
> >>  target_ulong mcause;
> >>  target_ulong mtval;  /* since: priv-1.10.0 */
> >>
> >> +/* Machine and Supervisor interrupt priorities */
> >> +uint8_t miprio[64];
> >> +uint8_t siprio[64];
> >> +
> >>  /* Hypervisor CSRs */
> >>  target_ulong hstatus;
> >>  target_ulong hedeleg;
> >> @@ -202,6 +206,9 @@ struct CPURISCVState {
> >>  target_ulong hgeip;
> >>  uint64_t htimedelta;
> >>
> >> +/* Hypervisor controlled virtual interrupt priorities */
> >> +uint8_t hviprio[64];
> >> +
> >>  /* Upper 64-bits of 128-bit CSRs */
> >>  uint64_t mscratchh;
> >>  uint64_t sscratchh;
> >> @@ -392,6 +399,11 @@ int
> riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
> >> int cpuid, void *opaque);
> >>  int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int
> reg);
> >>  int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
> >> +int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int
> *out_rdzero);
> >> +uint8_t riscv_cpu_default_priority(int irq);
> >> +int riscv_cpu_mirq_pending(CPURISCVState *env);
> >> +int riscv_cpu_sirq_pending(CPURISCVState *env);
> >> +int riscv_cpu_vsirq_pending(CPURISCVState *env);
> >>  bool riscv_cpu_fp_enabled(CPURISCVState *env);
> >>  target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
> >>  void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
> >> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> >> index 59c8f900df..3a36200780 100644
> >> --- a/target/riscv/cpu_helper.c
> >> +++ b/target/riscv/cpu_helper.c
> >> @@ -151,36 +151,236 @@ void cpu_get_tb_cpu_state(CPURISCVState *env,
> target_ulong *pc,
> >>  }
> >>
> >>  #ifndef CONFIG_USER_ONLY
> >> -static int riscv_cpu_local_irq_pending(CPURISCVState *env)
> >> +
> >> +/*
> >> + * The HS-mode is allowed to configure priority only for the
> >> + * following VS-mode local interrupts:
> >> + *
> >> + * 0  (Reserved interrupt, reads as zero)
> >> + * 1  Supervisor software interrupt
> >> + * 4  (Reserved interrupt, reads as zero)
> >> + * 5  Supervisor timer interrupt
> >> + * 8  (Reserved interrupt, reads as zero)
> >> + * 13 (Reserved interrupt)
> >> + * 14 "
> >> + * 15 "
> >> + * 16 "
> >> + * 18 Debug/trace interrupt
> >> + * 20 (Reserved interrupt)
> >> + * 22 "
> >> + * 24 "
> >> + * 26 "
> >> + * 28 "
> >> + * 30 (Reserved for standard reporting of bus or system errors)
> >> + */
> >> +
> 

Re: [PATCH v7 09/23] target/riscv: Implement AIA local interrupt priorities

[Anup Patel]

On Tue, Jan 18, 2022 at 9:04 AM Frank Chang  wrote:
>
> Anup Patel  於 2022年1月17日 週一 下午10:28寫道：
>>
>> From: Anup Patel 
>>
>> The AIA spec defines programmable 8-bit priority for each local interrupt
>> at M-level, S-level and VS-level so we extend local interrupt processing
>> to consider AIA interrupt priorities. The AIA CSRs which help software
>> configure local interrupt priorities will be added by subsequent patches.
>>
>> Signed-off-by: Anup Patel 
>> Signed-off-by: Anup Patel 
>> Reviewed-by: Alistair Francis 
>> ---
>>  target/riscv/cpu.c|  19 +++
>>  target/riscv/cpu.h|  12 ++
>>  target/riscv/cpu_helper.c | 242 ++
>>  target/riscv/machine.c|   3 +
>>  4 files changed, 255 insertions(+), 21 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 76f9786836..167d86eef7 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -370,6 +370,10 @@ void restore_state_to_opc(CPURISCVState *env, 
>> TranslationBlock *tb,
>>
>>  static void riscv_cpu_reset(DeviceState *dev)
>>  {
>> +#ifndef CONFIG_USER_ONLY
>> +uint8_t iprio;
>> +int i, irq, rdzero;
>> +#endif
>>  CPUState *cs = CPU(dev);
>>  RISCVCPU *cpu = RISCV_CPU(cs);
>>  RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
>> @@ -392,6 +396,21 @@ static void riscv_cpu_reset(DeviceState *dev)
>>  env->miclaim = MIP_SGEIP;
>>  env->pc = env->resetvec;
>>  env->two_stage_lookup = false;
>> +
>> +/* Initialized default priorities of local interrupts. */
>> +for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
>> +iprio = riscv_cpu_default_priority(i);
>> +env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio;
>> +env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio;
>> +env->hviprio[i] = 0;
>> +}
>> +i = 0;
>> +while (!riscv_cpu_hviprio_index2irq(i, , )) {
>> +if (!rdzero) {
>> +env->hviprio[irq] = env->miprio[irq];
>> +}
>> +i++;
>> +}
>>  /* mmte is supposed to have pm.current hardwired to 1 */
>>  env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
>>  #endif
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index cee70f8608..65d2b606fc 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -190,6 +190,10 @@ struct CPURISCVState {
>>  target_ulong mcause;
>>  target_ulong mtval;  /* since: priv-1.10.0 */
>>
>> +/* Machine and Supervisor interrupt priorities */
>> +uint8_t miprio[64];
>> +uint8_t siprio[64];
>> +
>>  /* Hypervisor CSRs */
>>  target_ulong hstatus;
>>  target_ulong hedeleg;
>> @@ -202,6 +206,9 @@ struct CPURISCVState {
>>  target_ulong hgeip;
>>  uint64_t htimedelta;
>>
>> +/* Hypervisor controlled virtual interrupt priorities */
>> +uint8_t hviprio[64];
>> +
>>  /* Upper 64-bits of 128-bit CSRs */
>>  uint64_t mscratchh;
>>  uint64_t sscratchh;
>> @@ -392,6 +399,11 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, 
>> CPUState *cs,
>> int cpuid, void *opaque);
>>  int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
>>  int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
>> +int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
>> +uint8_t riscv_cpu_default_priority(int irq);
>> +int riscv_cpu_mirq_pending(CPURISCVState *env);
>> +int riscv_cpu_sirq_pending(CPURISCVState *env);
>> +int riscv_cpu_vsirq_pending(CPURISCVState *env);
>>  bool riscv_cpu_fp_enabled(CPURISCVState *env);
>>  target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
>>  void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> index 59c8f900df..3a36200780 100644
>> --- a/target/riscv/cpu_helper.c
>> +++ b/target/riscv/cpu_helper.c
>> @@ -151,36 +151,236 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, 
>> target_ulong *pc,
>>  }
>>
>>  #ifndef CONFIG_USER_ONLY
>> -static int riscv_cpu_local_irq_pending(CPURISCVState *env)
>> +
>> +/*
>> + * The HS-mode is allowed to configure priority only for the
>> + * following VS-mode local interrupts:
>> + *
>> + * 0  (Reserved interrupt, reads as zero)
>> + * 1  Supervisor software interrupt
>> + * 4  (Reserved interrupt, reads as zero)
>> + * 5  Supervisor timer interrupt
>> + * 8  (Reserved interrupt, reads as zero)
>> + * 13 (Reserved interrupt)
>> + * 14 "
>> + * 15 "
>> + * 16 "
>> + * 18 Debug/trace interrupt
>> + * 20 (Reserved interrupt)
>> + * 22 "
>> + * 24 "
>> + * 26 "
>> + * 28 "
>> + * 30 (Reserved for standard reporting of bus or system errors)
>> + */
>> +
>> +static int hviprio_index2irq[] =
>> +{ 0, 1, 4, 5, 8, 13, 14, 15, 16, 18, 20, 22, 24, 26, 28, 30 };
>> +static int hviprio_index2rdzero[] =
>> +{ 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
>> +
>> +int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero)
>>  {
>> 

Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension

[Anup Patel]

On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li  wrote:
>
> - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on 
> QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
> - add PTE_PBMT bit check for inner PTE
>
> Signed-off-by: Weiwei Li 
> Signed-off-by: Junqiang Wang 
> Cc: Heiko Stuebner 
> Cc: Anup Patel 
> ---
>  target/riscv/cpu.c| 1 +
>  target/riscv/cpu.h| 1 +
>  target/riscv/cpu_bits.h   | 2 ++
>  target/riscv/cpu_helper.c | 4 +++-
>  4 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 45ac98e06b..4f82bd00a3 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -670,6 +670,7 @@ static Property riscv_cpu_properties[] = {
>
>  DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
>  DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> +DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
>
>  DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
>  DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index c3d1845ca1..53f314c752 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -329,6 +329,7 @@ struct RISCVCPU {
>  bool ext_icsr;
>  bool ext_svinval;
>  bool ext_svnapot;
> +bool ext_svpbmt;
>  bool ext_zfh;
>  bool ext_zfhmin;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 5501e9698b..24b7eb2b1f 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -486,7 +486,9 @@ typedef enum {
>  #define PTE_A   0x040 /* Accessed */
>  #define PTE_D   0x080 /* Dirty */
>  #define PTE_SOFT0x300 /* Reserved for Software */
> +#define PTE_PBMT0x6000 /* Page-based memory types */
>  #define PTE_N   0x8000 /* NAPOT translation */
> +#define PTE_ATTR(PTE_N | PTE_PBMT) /* All attributes bits */
>
>  /* Page table PPN shift amount */
>  #define PTE_PPN_SHIFT   10
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index c276760c7f..9fffaccffb 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -625,9 +625,11 @@ restart:
>  if (!(pte & PTE_V)) {
>  /* Invalid PTE */
>  return TRANSLATE_FAIL;
> +} else if (!cpu->cfg.ext_svpbmt && (pte & (target_ulong)PTE_PBMT)) {

Rather than, type-casting defines here you can simply define
ULL constants. E.g.
#define PTE_PBMT0x6000ULL

> +return TRANSLATE_FAIL;
>  } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
>  /* Inner PTE, continue walking */
> -if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_N)) {
> +if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
>  return TRANSLATE_FAIL;
>  }
>  base = ppn << PGSHIFT;
> --
> 2.17.1
>

Regards,
Anup

Re: [PATCH v7 09/23] target/riscv: Implement AIA local interrupt priorities

[Frank Chang]

Anup Patel  於 2022年1月17日 週一 下午10:28寫道：

> From: Anup Patel 
>
> The AIA spec defines programmable 8-bit priority for each local interrupt
> at M-level, S-level and VS-level so we extend local interrupt processing
> to consider AIA interrupt priorities. The AIA CSRs which help software
> configure local interrupt priorities will be added by subsequent patches.
>
> Signed-off-by: Anup Patel 
> Signed-off-by: Anup Patel 
> Reviewed-by: Alistair Francis 
> ---
>  target/riscv/cpu.c|  19 +++
>  target/riscv/cpu.h|  12 ++
>  target/riscv/cpu_helper.c | 242 ++
>  target/riscv/machine.c|   3 +
>  4 files changed, 255 insertions(+), 21 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 76f9786836..167d86eef7 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -370,6 +370,10 @@ void restore_state_to_opc(CPURISCVState *env,
> TranslationBlock *tb,
>
>  static void riscv_cpu_reset(DeviceState *dev)
>  {
> +#ifndef CONFIG_USER_ONLY
> +uint8_t iprio;
> +int i, irq, rdzero;
> +#endif
>  CPUState *cs = CPU(dev);
>  RISCVCPU *cpu = RISCV_CPU(cs);
>  RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
> @@ -392,6 +396,21 @@ static void riscv_cpu_reset(DeviceState *dev)
>  env->miclaim = MIP_SGEIP;
>  env->pc = env->resetvec;
>  env->two_stage_lookup = false;
> +
> +/* Initialized default priorities of local interrupts. */
> +for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
> +iprio = riscv_cpu_default_priority(i);
> +env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio;
> +env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio;
> +env->hviprio[i] = 0;
> +}
> +i = 0;
> +while (!riscv_cpu_hviprio_index2irq(i, , )) {
> +if (!rdzero) {
> +env->hviprio[irq] = env->miprio[irq];
> +}
> +i++;
> +}
>  /* mmte is supposed to have pm.current hardwired to 1 */
>  env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
>  #endif
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index cee70f8608..65d2b606fc 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -190,6 +190,10 @@ struct CPURISCVState {
>  target_ulong mcause;
>  target_ulong mtval;  /* since: priv-1.10.0 */
>
> +/* Machine and Supervisor interrupt priorities */
> +uint8_t miprio[64];
> +uint8_t siprio[64];
> +
>  /* Hypervisor CSRs */
>  target_ulong hstatus;
>  target_ulong hedeleg;
> @@ -202,6 +206,9 @@ struct CPURISCVState {
>  target_ulong hgeip;
>  uint64_t htimedelta;
>
> +/* Hypervisor controlled virtual interrupt priorities */
> +uint8_t hviprio[64];
> +
>  /* Upper 64-bits of 128-bit CSRs */
>  uint64_t mscratchh;
>  uint64_t sscratchh;
> @@ -392,6 +399,11 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction
> f, CPUState *cs,
> int cpuid, void *opaque);
>  int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
>  int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
> +int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
> +uint8_t riscv_cpu_default_priority(int irq);
> +int riscv_cpu_mirq_pending(CPURISCVState *env);
> +int riscv_cpu_sirq_pending(CPURISCVState *env);
> +int riscv_cpu_vsirq_pending(CPURISCVState *env);
>  bool riscv_cpu_fp_enabled(CPURISCVState *env);
>  target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
>  void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 59c8f900df..3a36200780 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -151,36 +151,236 @@ void cpu_get_tb_cpu_state(CPURISCVState *env,
> target_ulong *pc,
>  }
>
>  #ifndef CONFIG_USER_ONLY
> -static int riscv_cpu_local_irq_pending(CPURISCVState *env)
> +
> +/*
> + * The HS-mode is allowed to configure priority only for the
> + * following VS-mode local interrupts:
> + *
> + * 0  (Reserved interrupt, reads as zero)
> + * 1  Supervisor software interrupt
> + * 4  (Reserved interrupt, reads as zero)
> + * 5  Supervisor timer interrupt
> + * 8  (Reserved interrupt, reads as zero)
> + * 13 (Reserved interrupt)
> + * 14 "
> + * 15 "
> + * 16 "
> + * 18 Debug/trace interrupt
> + * 20 (Reserved interrupt)
> + * 22 "
> + * 24 "
> + * 26 "
> + * 28 "
> + * 30 (Reserved for standard reporting of bus or system errors)
> + */
> +
> +static int hviprio_index2irq[] =
> +{ 0, 1, 4, 5, 8, 13, 14, 15, 16, 18, 20, 22, 24, 26, 28, 30 };
> +static int hviprio_index2rdzero[] =
> +{ 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
> +
> +int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero)
>  {
> -target_ulong virt_enabled = riscv_cpu_virt_enabled(env);
> +if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) {
> +return -EINVAL;
> +}
> +
> +if (out_irq) {
> +  

Re: [PATCH v5 3/5] target/riscv: add support for svnapot extension

[Anup Patel]

On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li  wrote:
>
> - add PTE_N bit
> - add PTE_N bit check for inner PTE
> - update address translation to support 64KiB continuous region (napot_bits = 
> 4)
>
> Signed-off-by: Weiwei Li 
> Signed-off-by: Junqiang Wang 
> Cc: Anup Patel 

I did review this patch previously.

In any case, this looks good to me.

Reviewed-by: Anup Patel 

Regards,
Anup

> ---
>  target/riscv/cpu.c|  2 ++
>  target/riscv/cpu.h|  1 +
>  target/riscv/cpu_bits.h   |  1 +
>  target/riscv/cpu_helper.c | 18 +++---
>  4 files changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9bc25d3055..ff6c86c85b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -668,6 +668,8 @@ static Property riscv_cpu_properties[] = {
>  DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
>  DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
>
> +DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> +
>  DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
>  DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
>  DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 4d63086765..d3d17cde82 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -327,6 +327,7 @@ struct RISCVCPU {
>  bool ext_counters;
>  bool ext_ifencei;
>  bool ext_icsr;
> +bool ext_svnapot;
>  bool ext_zfh;
>  bool ext_zfhmin;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 282cd8eecd..5501e9698b 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -486,6 +486,7 @@ typedef enum {
>  #define PTE_A   0x040 /* Accessed */
>  #define PTE_D   0x080 /* Dirty */
>  #define PTE_SOFT0x300 /* Reserved for Software */
> +#define PTE_N   0x8000 /* NAPOT translation */
>
>  /* Page table PPN shift amount */
>  #define PTE_PPN_SHIFT   10
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 1820188f41..c276760c7f 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -621,12 +621,13 @@ restart:
>
>  hwaddr ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;
>
> +RISCVCPU *cpu = env_archcpu(env);
>  if (!(pte & PTE_V)) {
>  /* Invalid PTE */
>  return TRANSLATE_FAIL;
>  } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
>  /* Inner PTE, continue walking */
> -if (pte & (PTE_D | PTE_A | PTE_U)) {
> +if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_N)) {
>  return TRANSLATE_FAIL;
>  }
>  base = ppn << PGSHIFT;
> @@ -702,8 +703,19 @@ restart:
>  /* for superpage mappings, make a fake leaf PTE for the TLB's
> benefit. */
>  target_ulong vpn = addr >> PGSHIFT;
> -*physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
> -(addr & ~TARGET_PAGE_MASK);
> +
> +int napot_bits = 0;
> +if (cpu->cfg.ext_svnapot && (pte & (target_ulong)PTE_N)) {
> +napot_bits = ctzl(ppn) + 1;
> +if ((i != (levels - 1)) || (napot_bits != 4)) {
> +return TRANSLATE_FAIL;
> +}
> +}
> +
> +*physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) |
> +  (vpn & (((target_ulong)1 << napot_bits) - 1)) |
> +  (vpn & (((target_ulong)1 << ptshift) - 1))
> +) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
>
>  /* set permissions on the TLB entry */
>  if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
> --
> 2.17.1
>

Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64

[Anup Patel]

On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li  wrote:
>
> From: Guo Ren 
>
> Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
> need to ignore them. They cannot be a part of ppn.
>
> 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
>4.4 Sv39: Page-Based 39-bit Virtual-Memory System
>4.5 Sv48: Page-Based 48-bit Virtual-Memory System
>
> 2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf
>
> Signed-off-by: Guo Ren 
> Tested-by: Bin Meng 
> Reviewed-by: Liu Zhiwei 
> Reviewed-by: Bin Meng 
> Reviewed-by: Alistair Francis 
> ---
>  target/riscv/cpu_bits.h   | 7 +++
>  target/riscv/cpu_helper.c | 2 +-
>  2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 5a6d49aa64..282cd8eecd 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -490,6 +490,13 @@ typedef enum {
>  /* Page table PPN shift amount */
>  #define PTE_PPN_SHIFT   10
>
> +/* Page table PPN mask */
> +#if defined(TARGET_RISCV32)
> +#define PTE_PPN_MASK0xUL
> +#elif defined(TARGET_RISCV64)
> +#define PTE_PPN_MASK0x3fULL
> +#endif
> +

Going forward we should avoid using target specific "#if"
so that we can use the same qemu-system-riscv64 for both
RV32 and RV64.

>  /* Leaf page shift amount */
>  #define PGSHIFT 12
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 434a83e66a..26608ddf1c 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -619,7 +619,7 @@ restart:
>  return TRANSLATE_FAIL;
>  }
>
> -hwaddr ppn = pte >> PTE_PPN_SHIFT;
> +hwaddr ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;

Rather than using "#if", please use "xlen" comparison to extract
PPN correctly from PTE.

Regards,
Anup

>
>  if (!(pte & PTE_V)) {
>  /* Invalid PTE */
> --
> 2.17.1
>

Re: [RFC PATCH 2/2] hw/i386/sgx: Attach SGX-EPC to its memory backend

[Yang Zhong]

On Mon, Jan 17, 2022 at 12:48:10PM +0100, Paolo Bonzini wrote:
> On 1/17/22 00:53, Philippe Mathieu-Daudé via wrote:
> >We have one SGX-EPC address/size/node per memory backend,
> >make it child of the backend in the QOM composition tree.
> >
> >Cc: Yang Zhong 
> >Signed-off-by: Philippe Mathieu-Daudé 
> >---
> >  hw/i386/sgx.c | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> >diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c
> >index 5de5dd08936..6362e5e9d02 100644
> >--- a/hw/i386/sgx.c
> >+++ b/hw/i386/sgx.c
> >@@ -300,6 +300,9 @@ void pc_machine_init_sgx_epc(PCMachineState *pcms)
> >  /* set the memdev link with memory backend */
> >  object_property_parse(obj, SGX_EPC_MEMDEV_PROP, 
> > list->value->memdev,
> >_fatal);
> >+object_property_add_child(OBJECT(list->value->memdev), "sgx-epc",
> >+  OBJECT(obj));
> >+
> >  /* set the numa node property for sgx epc object */
> >  object_property_set_uint(obj, SGX_EPC_NUMA_NODE_PROP, 
> > list->value->node,
> >   _fatal);
> 
> I don't think this is a good idea; only list->value->memdev should
> add something below itself in the tree.
> 
> However, I think obj can be added under the machine itself as
> /machine/sgx-epc-device[*].
> 

  Thanks Philippe, calling object_property_add_child() in the hw/i386/sgx.c is 
more
  reasonable than in device_set_realized(), thanks!

  Yang

> Paolo

[PATCH] hw/sd: Correct the CURRENT_STATE bits in SPI-mode response

[frank . chang]

From: Frank Chang 

In SPI-mode, type B ("cleared on valid command") clear condition is not
supported, and as the "In idle state" bit in SPI-mode has type A
("according to current state") clear condition, the CURRENT_STATE bits
in an SPI-mode response should be the SD card's state after the command
is executed, instead of the state when it received the preceding
command.

Also, we don't need to clear the type B ("clear on valid command")
status bits after the response is updated in SPI-mode.

Signed-off-by: Frank Chang 
---
 hw/sd/sd.c | 26 ++
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index cd67a7bac8..9736b8912d 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -1757,12 +1757,20 @@ int sd_do_command(SDState *sd, SDRequest *req,
 if (rtype == sd_illegal) {
 sd->card_status |= ILLEGAL_COMMAND;
 } else {
-/* Valid command, we can update the 'state before command' bits.
- * (Do this now so they appear in r1 responses.)
- */
 sd->current_cmd = req->cmd;
 sd->card_status &= ~CURRENT_STATE;
-sd->card_status |= (last_state << 9);
+
+if (!sd->spi) {
+/* Valid command, we can update the 'state before command' bits.
+ * (Do this now so they appear in r1 responses.)
+ */
+sd->card_status |= (last_state << 9);
+} else {
+/* Type B ("clear on valid command") is not supported
+ * in SPI-mode.
+ */
+sd->card_status |= (sd->state << 9);
+}
 }
 
 send_response:
@@ -1808,10 +1816,12 @@ send_response:
 trace_sdcard_response(sd_response_name(rtype), rsplen);
 
 if (rtype != sd_illegal) {
-/* Clear the "clear on valid command" status bits now we've
- * sent any response
- */
-sd->card_status &= ~CARD_STATUS_B;
+if (!sd->spi) {
+/* Clear the "clear on valid command" status bits now we've
+ * sent any response
+ */
+sd->card_status &= ~CARD_STATUS_B;
+}
 }
 
 #ifdef DEBUG_SD
-- 
2.31.1

Re: [PATCH 1/2] hw/i386/x86: Attach CPUs to machine

[Yang Zhong]

On Mon, Jan 17, 2022 at 01:48:46PM +, Daniel P. Berrangé wrote:
> On Mon, Jan 17, 2022 at 12:53:30AM +0100, Philippe Mathieu-Daudé via wrote:
> > Avoid having CPUs objects dangling as unattached QOM ones,
> > directly attach them to the machine.
> 
> Lets be more explicit here
> 
> [quote]
>   Previously CPUs were exposed in the QOM tree at a path
> 
> /machine/unattached/device[nn]
> 
>   where the 'nn' of the first CPU is usually zero, but can
>   vary depending on what devices were already created.
> 
>   With this change the CPUs are now at
> 
> /machine/cpu[nn]
> 
>   where the 'nn' of the first CPU is always zero
> [/quote]
> 
> to  /machine/unattached/device[0->$SMP-COUNT]
> 
> > 
> > Signed-off-by: Philippe Mathieu-Daudé 
> > ---
> >  hw/i386/x86.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/hw/i386/x86.c b/hw/i386/x86.c
> > index b84840a1bb9..50bf249c700 100644
> > --- a/hw/i386/x86.c
> > +++ b/hw/i386/x86.c
> > @@ -108,6 +108,7 @@ void x86_cpu_new(X86MachineState *x86ms, int64_t 
> > apic_id, Error **errp)
> >  {
> >  Object *cpu = object_new(MACHINE(x86ms)->cpu_type);
> >  
> > +object_property_add_child(OBJECT(x86ms), "cpu[*]", OBJECT(cpu));
> >  if (!object_property_set_uint(cpu, "apic-id", apic_id, errp)) {
> >  goto out;
> >  }
> > -- 
> > 2.34.1
> > 
> > 


  Thanks Philippe, if we change /machine/unattached/device[nn] to 
/machine/cpu[nn],
  the related changes should also be done in the Libvirt side, which still check
  /machine/unattached/device[0] to get unvailable-features. thanks!

  Yang

> 
> Regards,
> Daniel
> -- 
> |: https://berrange.com  -o-https://www.flickr.com/photos/dberrange :|
> |: https://libvirt.org -o-https://fstop138.berrange.com :|
> |: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|

[PATCH v2 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns

[frank . chang]

From: Frank Chang 

All Zve* extensions support the vector configuration instructions.

Signed-off-by: Frank Chang 
Reviewed-by: Alistair Francis 
---
 target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 9fa3862620..fd6e74c232 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -152,7 +152,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, 
TCGv s2)
 TCGv s1, dst;
 
 if (!require_rvv(s) ||
-!(has_ext(s, RVV) || s->ext_zve64f)) {
+!(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
 return false;
 }
 
@@ -188,7 +188,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, 
TCGv s2)
 TCGv dst;
 
 if (!require_rvv(s) ||
-!(has_ext(s, RVV) || s->ext_zve64f)) {
+!(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
 return false;
 }
 
-- 
2.31.1

[PATCH v2 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V

[frank . chang]

From: Frank Chang 

Signed-off-by: Frank Chang 
Reviewed-by: Alistair Francis 
---
 target/riscv/cpu.c| 4 ++--
 target/riscv/cpu.h| 1 +
 target/riscv/cpu_helper.c | 2 +-
 target/riscv/csr.c| 2 +-
 target/riscv/translate.c  | 2 ++
 5 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4bca1cd289..0898954c02 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -589,8 +589,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
**errp)
 }
 set_vext_version(env, vext_version);
 }
-if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) {
-error_setg(errp, "Zve64f extension depends upon RVF.");
+if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
+error_setg(errp, "Zve32f/Zve64f extension depends upon RVF.");
 return;
 }
 if (cpu->cfg.ext_j) {
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 86cc94d3bb..21772496b3 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -329,6 +329,7 @@ struct RISCVCPU {
 bool ext_icsr;
 bool ext_zfh;
 bool ext_zfhmin;
+bool ext_zve32f;
 bool ext_zve64f;
 
 char *priv_spec;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 43d498aae1..afee770951 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -77,7 +77,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong 
*pc,
 *pc = env->pc;
 *cs_base = 0;
 
-if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) {
+if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) 
{
 /*
  * If env->vl equals to VLMAX, we can use generic vector operation
  * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e9311cfd9d..a9e7ac903b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -51,7 +51,7 @@ static RISCVException vs(CPURISCVState *env, int csrno)
 RISCVCPU *cpu = RISCV_CPU(cs);
 
 if (env->misa_ext & RVV ||
-cpu->cfg.ext_zve64f) {
+cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
 #if !defined(CONFIG_USER_ONLY)
 if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
 return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d3c0d44e2e..330904265e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -79,6 +79,7 @@ typedef struct DisasContext {
 bool ext_ifencei;
 bool ext_zfh;
 bool ext_zfhmin;
+bool ext_zve32f;
 bool ext_zve64f;
 bool hlsx;
 /* vector extension */
@@ -895,6 +896,7 @@ static void riscv_tr_init_disas_context(DisasContextBase 
*dcbase, CPUState *cs)
 ctx->ext_ifencei = cpu->cfg.ext_ifencei;
 ctx->ext_zfh = cpu->cfg.ext_zfh;
 ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
+ctx->ext_zve32f = cpu->cfg.ext_zve32f;
 ctx->ext_zve64f = cpu->cfg.ext_zve64f;
 ctx->vlen = cpu->cfg.vlen;
 ctx->elen = cpu->cfg.elen;
-- 
2.31.1

Re: [PATCH v11 3/4] softmmu/dirtylimit: implement virtual CPU throttle

[Hyman Huang]

在 2022/1/18 9:00, Peter Xu 写道:

On Mon, Jan 17, 2022 at 10:00:57PM +0800, Hyman Huang wrote:

This algorithm seems works even worse than the previous version, could you have
a look on what's wrong?

What number the dirty-ring-size of qemu be configured? is it the same as
previous version test?


It should be the same 4096.

The test environment can be slightly different, I used a larger guest this time
(20G, 40 cores), though.  Previously it should be a few gig only with a few 
cores.


Ok, i'll work this out.

Side note: would you also consider picking up this patch along with the series?

Of course yes, i think this patch can reduce time overhead of 
memory_global_dirty_log_start/memory_global_dirty_log_stop but need some 
migration tests, i'll do that and once all these be ready, i'll cherry 
pick the series before dirtylimit patchset.

https://lore.kernel.org/qemu-devel/20211130080028.6474-1-pet...@redhat.com/

I wanted to make sure it lands before this series, e.g., when enabled both
dirty limit and migration, disabling dirty limit might trigger the bug already.
 > Thanks,



--
Best regard

Hyman Huang(黄勇)

[PATCH v2 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on

[frank . chang]

From: Frank Chang 

Signed-off-by: Frank Chang 
Reviewed-by: Alistair Francis 
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2ba22503da..4bca1cd289 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -664,6 +664,7 @@ static Property riscv_cpu_properties[] = {
 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
+DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
 
-- 
2.31.1

[PATCH v2 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns

[frank . chang]

From: Frank Chang 

Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.

Signed-off-by: Frank Chang 
Reviewed-by: Alistair Francis 
---
 target/riscv/insn_trans/trans_rvv.c.inc | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index b02bb555a6..f2d3c9e8b9 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -77,6 +77,17 @@ static bool require_zve32f(DisasContext *s)
 return s->ext_zve32f ? s->sew <= MO_32 : true;
 }
 
+static bool require_scale_zve32f(DisasContext *s)
+{
+/* RVV + Zve32f = RVV. */
+if (has_ext(s, RVV)) {
+return true;
+}
+
+/* Zve32f doesn't support FP64. (Section 18.2) */
+return s->ext_zve64f ? s->sew <= MO_16 : true;
+}
+
 static bool require_zve64f(DisasContext *s)
 {
 /* RVV + Zve64f = RVV. */
@@ -2358,6 +2369,7 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr 
*a)
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+   require_scale_zve32f(s) &&
require_scale_zve64f(s);
 }
 
@@ -2398,6 +2410,7 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr 
*a)
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+   require_scale_zve32f(s) &&
require_scale_zve64f(s);
 }
 
@@ -2429,6 +2442,7 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr 
*a)
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
+   require_scale_zve32f(s) &&
require_scale_zve64f(s);
 }
 
@@ -2469,6 +2483,7 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr 
*a)
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
vext_check_dd(s, a->rd, a->rs2, a->vm) &&
+   require_scale_zve32f(s) &&
require_scale_zve64f(s);
 }
 
@@ -2733,6 +2748,7 @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
 {
 return opfv_widen_check(s, a) &&
require_rvf(s) &&
+   require_zve32f(s) &&
require_zve64f(s);
 }
 
@@ -2741,6 +2757,7 @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 return opfv_widen_check(s, a) &&
require_scale_rvf(s) &&
(s->sew != MO_8) &&
+   require_scale_zve32f(s) &&
require_scale_zve64f(s);
 }
 
@@ -2793,6 +2810,7 @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
vext_check_isa_ill(s) &&
/* OPFV widening instructions ignore vs1 check */
vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+   require_scale_zve32f(s) &&
require_scale_zve64f(s);
 }
 
-- 
2.31.1

[PATCH v2 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns

[frank . chang]

From: Frank Chang 

Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.

Signed-off-by: Frank Chang 
Reviewed-by: Alistair Francis 
---
 target/riscv/insn_trans/trans_rvv.c.inc | 32 +++--
 1 file changed, 25 insertions(+), 7 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 08f25e3ce4..58f12366dd 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -77,6 +77,17 @@ static bool require_zve64f(DisasContext *s)
 return s->ext_zve64f ? s->sew <= MO_32 : true;
 }
 
+static bool require_scale_zve64f(DisasContext *s)
+{
+/* RVV + Zve64f = RVV. */
+if (has_ext(s, RVV)) {
+return true;
+}
+
+/* Zve64f doesn't support FP64. (Section 18.2) */
+return s->ext_zve64f ? s->sew <= MO_16 : true;
+}
+
 /* Destination vector register group cannot overlap source mask register. */
 static bool require_vm(int vm, int vd)
 {
@@ -2333,7 +2344,8 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr 
*a)
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
-   vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
+   vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+   require_scale_zve64f(s);
 }
 
 /* OPFVV with WIDEN */
@@ -2372,7 +2384,8 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr 
*a)
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
-   vext_check_ds(s, a->rd, a->rs2, a->vm);
+   vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+   require_scale_zve64f(s);
 }
 
 /* OPFVF with WIDEN */
@@ -2402,7 +2415,8 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr 
*a)
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
-   vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
+   vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
+   require_scale_zve64f(s);
 }
 
 /* WIDEN OPFVV with WIDEN */
@@ -2441,7 +2455,8 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr 
*a)
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
-   vext_check_dd(s, a->rd, a->rs2, a->vm);
+   vext_check_dd(s, a->rd, a->rs2, a->vm) &&
+   require_scale_zve64f(s);
 }
 
 /* WIDEN OPFVF with WIDEN */
@@ -2700,14 +2715,16 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr 
*a)
 static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
 {
 return opfv_widen_check(s, a) &&
-   require_rvf(s);
+   require_rvf(s) &&
+   require_zve64f(s);
 }
 
 static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 {
 return opfv_widen_check(s, a) &&
require_scale_rvf(s) &&
-   (s->sew != MO_8);
+   (s->sew != MO_8) &&
+   require_scale_zve64f(s);
 }
 
 #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \
@@ -2758,7 +2775,8 @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
require_scale_rvf(s) &&
vext_check_isa_ill(s) &&
/* OPFV widening instructions ignore vs1 check */
-   vext_check_ds(s, a->rd, a->rs2, a->vm);
+   vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+   require_scale_zve64f(s);
 }
 
 #define GEN_OPFXV_WIDEN_TRANS(NAME)\
-- 
2.31.1

[PATCH v2 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on

[frank . chang]

From: Frank Chang 

Signed-off-by: Frank Chang 
Reviewed-by: Alistair Francis 
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0898954c02..33c1df638b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -664,6 +664,7 @@ static Property riscv_cpu_properties[] = {
 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
+DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
-- 
2.31.1

[PATCH v2 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns

[frank . chang]

From: Frank Chang 

All Zve* extensions support all vector fixed-point arithmetic
instructions, except that vsmul.vv and vsmul.vx are not supported
for EEW=64 in Zve64*.

Signed-off-by: Frank Chang 
Reviewed-by: Alistair Francis 
---
 target/riscv/insn_trans/trans_rvv.c.inc | 27 +++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index e64a28..8e493b7933 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2123,8 +2123,31 @@ GEN_OPIVX_TRANS(vasub_vx,  opivx_check)
 GEN_OPIVX_TRANS(vasubu_vx,  opivx_check)
 
 /* Vector Single-Width Fractional Multiply with Rounding and Saturation */
-GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
-GEN_OPIVX_TRANS(vsmul_vx,  opivx_check)
+
+static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)
+{
+/*
+ * All Zve* extensions support all vector fixed-point arithmetic
+ * instructions, except that vsmul.vv and vsmul.vx are not supported
+ * for EEW=64 in Zve64*. (Section 18.2)
+ */
+return opivv_check(s, a) &&
+   (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+}
+
+static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
+{
+/*
+ * All Zve* extensions support all vector fixed-point arithmetic
+ * instructions, except that vsmul.vv and vsmul.vx are not supported
+ * for EEW=64 in Zve64*. (Section 18.2)
+ */
+return opivx_check(s, a) &&
+   (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+}
+
+GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)
+GEN_OPIVX_TRANS(vsmul_vx,  vsmul_vx_check)
 
 /* Vector Single-Width Scaling Shift Instructions */
 GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
-- 
2.31.1

[PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns

[frank . chang]

From: Frank Chang 

All Zve* extensions support all vector load and store instructions,
except Zve64* extensions do not support EEW=64 for index values when
XLEN=32.

Signed-off-by: Frank Chang 
---
 target/riscv/insn_trans/trans_rvv.c.inc | 19 +++
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 5b47729a21..0bf41aaa1e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -263,10 +263,21 @@ static bool vext_check_st_index(DisasContext *s, int vd, 
int vs2, int nf,
 uint8_t eew)
 {
 int8_t emul = eew - s->sew + s->lmul;
-return (emul >= -3 && emul <= 3) &&
-require_align(vs2, emul) &&
-require_align(vd, s->lmul) &&
-require_nf(vd, nf, s->lmul);
+bool ret = (emul >= -3 && emul <= 3) &&
+   require_align(vs2, emul) &&
+   require_align(vd, s->lmul) &&
+   require_nf(vd, nf, s->lmul);
+
+/*
+ * All Zve* extensions support all vector load and store instructions,
+ * except Zve64* extensions do not support EEW=64 for index values
+ * when XLEN=32. (Section 18.2)
+ */
+if (get_xl(s) == MXL_RV32) {
+ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true);
+}
+
+return ret;
 }
 
 /*
-- 
2.31.1

[PATCH v2 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns

[frank . chang]

From: Frank Chang 

Zve64f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).

Signed-off-by: Frank Chang 
Reviewed-by: Alistair Francis 
---
 target/riscv/insn_trans/trans_rvv.c.inc | 41 +++--
 1 file changed, 31 insertions(+), 10 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 8e493b7933..56246a5d88 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -66,6 +66,17 @@ static bool require_scale_rvf(DisasContext *s)
 }
 }
 
+static bool require_zve64f(DisasContext *s)
+{
+/* RVV + Zve64f = RVV. */
+if (has_ext(s, RVV)) {
+return true;
+}
+
+/* Zve64f doesn't support FP64. (Section 18.2) */
+return s->ext_zve64f ? s->sew <= MO_32 : true;
+}
+
 /* Destination vector register group cannot overlap source mask register. */
 static bool require_vm(int vm, int vd)
 {
@@ -2206,7 +2217,8 @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
 return require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s) &&
-   vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
+   vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+   require_zve64f(s);
 }
 
 /* OPFVV without GVEC IR */
@@ -2286,7 +2298,8 @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
 return require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s) &&
-   vext_check_ss(s, a->rd, a->rs2, a->vm);
+   vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+   require_zve64f(s);
 }
 
 /* OPFVF without GVEC IR */
@@ -2503,7 +2516,8 @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
require_rvf(s) &&
vext_check_isa_ill(s) &&
/* OPFV instructions ignore vs1 check */
-   vext_check_ss(s, a->rd, a->rs2, a->vm);
+   vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+   require_zve64f(s);
 }
 
 static bool do_opfv(DisasContext *s, arg_rmr *a,
@@ -2568,7 +2582,8 @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
 return require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s) &&
-   vext_check_mss(s, a->rd, a->rs1, a->rs2);
+   vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
+   require_zve64f(s);
 }
 
 GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
@@ -2581,7 +2596,8 @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
 return require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s) &&
-   vext_check_ms(s, a->rd, a->rs2);
+   vext_check_ms(s, a->rd, a->rs2) &&
+   require_zve64f(s);
 }
 
 GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
@@ -2602,7 +2618,8 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f 
*a)
 if (require_rvv(s) &&
 require_rvf(s) &&
 vext_check_isa_ill(s) &&
-require_align(a->rd, s->lmul)) {
+require_align(a->rd, s->lmul) &&
+require_zve64f(s)) {
 gen_set_rm(s, RISCV_FRM_DYN);
 
 TCGv_i64 t1;
@@ -3328,7 +3345,8 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s 
*a)
 {
 if (require_rvv(s) &&
 require_rvf(s) &&
-vext_check_isa_ill(s)) {
+vext_check_isa_ill(s) &&
+require_zve64f(s)) {
 gen_set_rm(s, RISCV_FRM_DYN);
 
 unsigned int ofs = (8 << s->sew);
@@ -3354,7 +3372,8 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f 
*a)
 {
 if (require_rvv(s) &&
 require_rvf(s) &&
-vext_check_isa_ill(s)) {
+vext_check_isa_ill(s) &&
+require_zve64f(s)) {
 gen_set_rm(s, RISCV_FRM_DYN);
 
 /* The instructions ignore LMUL and vector register group. */
@@ -3405,13 +3424,15 @@ GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, 
slidedown_check)
 static bool fslideup_check(DisasContext *s, arg_rmrr *a)
 {
 return slideup_check(s, a) &&
-   require_rvf(s);
+   require_rvf(s) &&
+   require_zve64f(s);
 }
 
 static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
 {
 return slidedown_check(s, a) &&
-   require_rvf(s);
+   require_rvf(s) &&
+   require_zve64f(s);
 }
 
 GEN_OPFVF_TRANS(vfslide1up_vf, fslideup_check)
-- 
2.31.1

[PATCH v2 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns

[frank . chang]

From: Frank Chang 

Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve32f extension.

Signed-off-by: Frank Chang 
Reviewed-by: Alistair Francis 
---
 target/riscv/insn_trans/trans_rvv.c.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index fe4ad5d008..b02bb555a6 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2976,6 +2976,7 @@ static bool freduction_check(DisasContext *s, arg_rmrr *a)
 {
 return reduction_check(s, a) &&
require_rvf(s) &&
+   require_zve32f(s) &&
require_zve64f(s);
 }
 
-- 
2.31.1

[PATCH v2 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns

[frank . chang]

From: Frank Chang 

Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.

Signed-off-by: Frank Chang 
Reviewed-by: Alistair Francis 
---
 target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index f2d3c9e8b9..7a040b3089 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2862,6 +2862,7 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr 
*a)
 return opfv_narrow_check(s, a) &&
require_rvf(s) &&
(s->sew != MO_64) &&
+   require_zve32f(s) &&
require_zve64f(s);
 }
 
@@ -2870,6 +2871,7 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr 
*a)
 return opfv_narrow_check(s, a) &&
require_scale_rvf(s) &&
(s->sew != MO_8) &&
+   require_scale_zve32f(s) &&
require_scale_zve64f(s);
 }
 
@@ -2920,6 +2922,7 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr 
*a)
vext_check_isa_ill(s) &&
/* OPFV narrowing instructions ignore vs1 check */
vext_check_sd(s, a->rd, a->rs2, a->vm) &&
+   require_scale_zve32f(s) &&
require_scale_zve64f(s);
 }
 
-- 
2.31.1

[PATCH v2 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns

[frank . chang]

From: Frank Chang 

Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve64f extension.

Signed-off-by: Frank Chang 
Reviewed-by: Alistair Francis 
---
 target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 56246a5d88..08f25e3ce4 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2937,7 +2937,8 @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
 static bool freduction_check(DisasContext *s, arg_rmrr *a)
 {
 return reduction_check(s, a) &&
-   require_rvf(s);
+   require_rvf(s) &&
+   require_zve64f(s);
 }
 
 GEN_OPFVV_TRANS(vfredsum_vs, freduction_check)
-- 
2.31.1

[PATCH v2 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns

[frank . chang]

From: Frank Chang 

Zve32f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).

Signed-off-by: Frank Chang 
Reviewed-by: Alistair Francis 
---
 target/riscv/insn_trans/trans_rvv.c.inc | 21 +
 1 file changed, 21 insertions(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index fd6e74c232..fe4ad5d008 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -66,6 +66,17 @@ static bool require_scale_rvf(DisasContext *s)
 }
 }
 
+static bool require_zve32f(DisasContext *s)
+{
+/* RVV + Zve32f = RVV. */
+if (has_ext(s, RVV)) {
+return true;
+}
+
+/* Zve32f doesn't support FP64. (Section 18.2) */
+return s->ext_zve32f ? s->sew <= MO_32 : true;
+}
+
 static bool require_zve64f(DisasContext *s)
 {
 /* RVV + Zve64f = RVV. */
@@ -2229,6 +2240,7 @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
require_rvf(s) &&
vext_check_isa_ill(s) &&
vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+   require_zve32f(s) &&
require_zve64f(s);
 }
 
@@ -2310,6 +2322,7 @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
require_rvf(s) &&
vext_check_isa_ill(s) &&
vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+   require_zve32f(s) &&
require_zve64f(s);
 }
 
@@ -2532,6 +2545,7 @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
vext_check_isa_ill(s) &&
/* OPFV instructions ignore vs1 check */
vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+   require_zve32f(s) &&
require_zve64f(s);
 }
 
@@ -2598,6 +2612,7 @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
require_rvf(s) &&
vext_check_isa_ill(s) &&
vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
+   require_zve32f(s) &&
require_zve64f(s);
 }
 
@@ -2612,6 +2627,7 @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
require_rvf(s) &&
vext_check_isa_ill(s) &&
vext_check_ms(s, a->rd, a->rs2) &&
+   require_zve32f(s) &&
require_zve64f(s);
 }
 
@@ -2634,6 +2650,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f 
*a)
 require_rvf(s) &&
 vext_check_isa_ill(s) &&
 require_align(a->rd, s->lmul) &&
+require_zve32f(s) &&
 require_zve64f(s)) {
 gen_set_rm(s, RISCV_FRM_DYN);
 
@@ -3368,6 +3385,7 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s 
*a)
 if (require_rvv(s) &&
 require_rvf(s) &&
 vext_check_isa_ill(s) &&
+require_zve32f(s) &&
 require_zve64f(s)) {
 gen_set_rm(s, RISCV_FRM_DYN);
 
@@ -3395,6 +3413,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f 
*a)
 if (require_rvv(s) &&
 require_rvf(s) &&
 vext_check_isa_ill(s) &&
+require_zve32f(s) &&
 require_zve64f(s)) {
 gen_set_rm(s, RISCV_FRM_DYN);
 
@@ -3447,6 +3466,7 @@ static bool fslideup_check(DisasContext *s, arg_rmrr *a)
 {
 return slideup_check(s, a) &&
require_rvf(s) &&
+   require_zve32f(s) &&
require_zve64f(s);
 }
 
@@ -3454,6 +3474,7 @@ static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
 {
 return slidedown_check(s, a) &&
require_rvf(s) &&
+   require_zve32f(s) &&
require_zve64f(s);
 }
 
-- 
2.31.1

[PATCH v2 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V

[frank . chang]

From: Frank Chang 

Signed-off-by: Frank Chang 
Reviewed-by: Alistair Francis 
---
 target/riscv/cpu.c| 4 
 target/riscv/cpu.h| 1 +
 target/riscv/cpu_helper.c | 5 -
 target/riscv/csr.c| 6 +-
 target/riscv/translate.c  | 2 ++
 5 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9bc25d3055..2ba22503da 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -589,6 +589,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
**errp)
 }
 set_vext_version(env, vext_version);
 }
+if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) {
+error_setg(errp, "Zve64f extension depends upon RVF.");
+return;
+}
 if (cpu->cfg.ext_j) {
 ext |= RVJ;
 }
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4d63086765..86cc94d3bb 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -329,6 +329,7 @@ struct RISCVCPU {
 bool ext_icsr;
 bool ext_zfh;
 bool ext_zfhmin;
+bool ext_zve64f;
 
 char *priv_spec;
 char *user_spec;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 434a83e66a..43d498aae1 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -69,12 +69,15 @@ static RISCVMXL cpu_get_xl(CPURISCVState *env)
 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
   target_ulong *cs_base, uint32_t *pflags)
 {
+CPUState *cs = env_cpu(env);
+RISCVCPU *cpu = RISCV_CPU(cs);
+
 uint32_t flags = 0;
 
 *pc = env->pc;
 *cs_base = 0;
 
-if (riscv_has_ext(env, RVV)) {
+if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) {
 /*
  * If env->vl equals to VLMAX, we can use generic vector operation
  * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index adb3d4381d..e9311cfd9d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -47,7 +47,11 @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-if (env->misa_ext & RVV) {
+CPUState *cs = env_cpu(env);
+RISCVCPU *cpu = RISCV_CPU(cs);
+
+if (env->misa_ext & RVV ||
+cpu->cfg.ext_zve64f) {
 #if !defined(CONFIG_USER_ONLY)
 if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
 return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 615048ec87..d3c0d44e2e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -79,6 +79,7 @@ typedef struct DisasContext {
 bool ext_ifencei;
 bool ext_zfh;
 bool ext_zfhmin;
+bool ext_zve64f;
 bool hlsx;
 /* vector extension */
 bool vill;
@@ -894,6 +895,7 @@ static void riscv_tr_init_disas_context(DisasContextBase 
*dcbase, CPUState *cs)
 ctx->ext_ifencei = cpu->cfg.ext_ifencei;
 ctx->ext_zfh = cpu->cfg.ext_zfh;
 ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
+ctx->ext_zve64f = cpu->cfg.ext_zve64f;
 ctx->vlen = cpu->cfg.vlen;
 ctx->elen = cpu->cfg.elen;
 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
-- 
2.31.1

[PATCH v2 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns

[frank . chang]

From: Frank Chang 

All Zve* extensions support all vector integer instructions,
except that the vmulh integer multiply variants that return the
high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx,
vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.

Signed-off-by: Frank Chang 
Reviewed-by: Alistair Francis 
---
 target/riscv/insn_trans/trans_rvv.c.inc | 39 +
 1 file changed, 33 insertions(+), 6 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 0bf41aaa1e..e64a28 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1908,14 +1908,41 @@ GEN_OPIVX_TRANS(vmaxu_vx, opivx_check)
 GEN_OPIVX_TRANS(vmax_vx,  opivx_check)
 
 /* Vector Single-Width Integer Multiply Instructions */
+
+static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a)
+{
+/*
+ * All Zve* extensions support all vector integer instructions,
+ * except that the vmulh integer multiply variants
+ * that return the high word of the product
+ * (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx)
+ * are not included for EEW=64 in Zve64*. (Section 18.2)
+ */
+return opivv_check(s, a) &&
+   (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+}
+
+static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
+{
+/*
+ * All Zve* extensions support all vector integer instructions,
+ * except that the vmulh integer multiply variants
+ * that return the high word of the product
+ * (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx)
+ * are not included for EEW=64 in Zve64*. (Section 18.2)
+ */
+return opivx_check(s, a) &&
+   (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+}
+
 GEN_OPIVV_GVEC_TRANS(vmul_vv,  mul)
-GEN_OPIVV_TRANS(vmulh_vv, opivv_check)
-GEN_OPIVV_TRANS(vmulhu_vv, opivv_check)
-GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check)
+GEN_OPIVV_TRANS(vmulh_vv, vmulh_vv_check)
+GEN_OPIVV_TRANS(vmulhu_vv, vmulh_vv_check)
+GEN_OPIVV_TRANS(vmulhsu_vv, vmulh_vv_check)
 GEN_OPIVX_GVEC_TRANS(vmul_vx,  muls)
-GEN_OPIVX_TRANS(vmulh_vx, opivx_check)
-GEN_OPIVX_TRANS(vmulhu_vx, opivx_check)
-GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check)
+GEN_OPIVX_TRANS(vmulh_vx, vmulh_vx_check)
+GEN_OPIVX_TRANS(vmulhu_vx, vmulh_vx_check)
+GEN_OPIVX_TRANS(vmulhsu_vx, vmulh_vx_check)
 
 /* Vector Integer Divide Instructions */
 GEN_OPIVV_TRANS(vdivu_vv, opivv_check)
-- 
2.31.1

[PATCH v2 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns

[frank . chang]

From: Frank Chang 

Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.

Signed-off-by: Frank Chang 
Reviewed-by: Alistair Francis 
---
 target/riscv/insn_trans/trans_rvv.c.inc | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 58f12366dd..9fa3862620 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2826,14 +2826,16 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr 
*a)
 {
 return opfv_narrow_check(s, a) &&
require_rvf(s) &&
-   (s->sew != MO_64);
+   (s->sew != MO_64) &&
+   require_zve64f(s);
 }
 
 static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
 {
 return opfv_narrow_check(s, a) &&
require_scale_rvf(s) &&
-   (s->sew != MO_8);
+   (s->sew != MO_8) &&
+   require_scale_zve64f(s);
 }
 
 #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)\
@@ -2882,7 +2884,8 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr 
*a)
require_scale_rvf(s) &&
vext_check_isa_ill(s) &&
/* OPFV narrowing instructions ignore vs1 check */
-   vext_check_sd(s, a->rd, a->rs2, a->vm);
+   vext_check_sd(s, a->rd, a->rs2, a->vm) &&
+   require_scale_zve64f(s);
 }
 
 #define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM)  \
-- 
2.31.1

[PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions

[frank . chang]

From: Frank Chang 

In RVV v1.0 spec, several Zve* vector extensions for embedded processors
are defined in Chapter 18.2:
https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#zve-vector-extensions-for-embedded-processors

This patchset implements Zve32f and Zve64f extensions.

The port is available at:
https://github.com/sifive/qemu/tree/rvv-zve32f-zve64f-upstream-v2

Zve32f can be enabled with -cpu option: Zve32f=true and
Zve64f can be enabled with -cpu option: Zve64f=true.
V is not required to be enabled explicitly.

Here's the inclusion diagram for the six standard vector extensions
quoted from Nick Knight :

  V
  |
Zve64d
  |
Zve64f
   /  \
Zve64x   Zve32f
   \  /
Zve32x

Changelog:

v2:
  * Replace hardcoded TARGET_RISCV32 macro with get_xl().

Frank Chang (17):
  target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
  target/riscv: rvv-1.0: Add Zve64f support for configuration insns
  target/riscv: rvv-1.0: Add Zve64f support for load and store insns
  target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
  target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx
insns
  target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
  target/riscv: rvv-1.0: Add Zve64f support for single-width fp
reduction insns
  target/riscv: rvv-1.0: Add Zve64f support for widening type-convert
insns
  target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert
insns
  target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
  target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
  target/riscv: rvv-1.0: Add Zve32f support for configuration insns
  target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
  target/riscv: rvv-1.0: Add Zve32f support for single-width fp
reduction insns
  target/riscv: rvv-1.0: Add Zve32f support for widening type-convert
insns
  target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert
insns
  target/riscv: rvv-1.0: Allow Zve32f extension to be turned on

 target/riscv/cpu.c  |   6 +
 target/riscv/cpu.h  |   2 +
 target/riscv/cpu_helper.c   |   5 +-
 target/riscv/csr.c  |   6 +-
 target/riscv/insn_trans/trans_rvv.c.inc | 219 
 target/riscv/translate.c|   4 +
 6 files changed, 205 insertions(+), 37 deletions(-)

--
2.31.1

[PATCH v2 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns

[frank . chang]

From: Frank Chang 

All Zve* extensions support the vector configuration instructions.

Signed-off-by: Frank Chang 
Reviewed-by: Alistair Francis 
---
 target/riscv/insn_trans/trans_rvv.c.inc | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 6c285c958b..5b47729a21 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -129,7 +129,8 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, 
TCGv s2)
 {
 TCGv s1, dst;
 
-if (!require_rvv(s) || !has_ext(s, RVV)) {
+if (!require_rvv(s) ||
+!(has_ext(s, RVV) || s->ext_zve64f)) {
 return false;
 }
 
@@ -164,7 +165,8 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, 
TCGv s2)
 {
 TCGv dst;
 
-if (!require_rvv(s) || !has_ext(s, RVV)) {
+if (!require_rvv(s) ||
+!(has_ext(s, RVV) || s->ext_zve64f)) {
 return false;
 }
 
-- 
2.31.1

Re: [PATCH v3] hw/dma: Let dma_buf_read() / dma_buf_write() propagate MemTxResult

[Peter Xu]

On Mon, Jan 17, 2022 at 01:51:30PM +0100, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé 
> 
> Since commit 292e13142d2, dma_buf_rw() returns a MemTxResult type.
> Do not discard it, return it to the caller. Pass the previously
> returned value (the QEMUSGList residual size, which was rarely used)
> as an optional argument.
> 
> With this new API, SCSIRequest::residual might now be accessed via
> a pointer. Since the size_t type does not have the same size on
> 32 and 64-bit host architectures, convert it to a uint64_t, which
> is big enough to hold the residual size, and the type is constant
> on both 32/64-bit hosts.
> 
> Update the few dma_buf_read() / dma_buf_write() callers to the new
> API.
> 
> Reviewed-by: Klaus Jensen 
> Signed-off-by: Philippe Mathieu-Daudé 
> Signed-off-by: Philippe Mathieu-Daudé 

Acked-by: Peter Xu 

-- 
Peter Xu

Re: [PATCH 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns

[Frank Chang]

On Tue, Jan 18, 2022 at 6:27 AM Alistair Francis 
wrote:

> On Wed, Dec 29, 2021 at 12:34 PM  wrote:
> >
> > From: Frank Chang 
> >
> > All Zve* extensions support all vector load and store instructions,
> > except Zve64* extensions do not support EEW=64 for index values when
> > XLEN=32.
> >
> > Signed-off-by: Frank Chang 
> > ---
> >  target/riscv/insn_trans/trans_rvv.c.inc | 17 +
> >  1 file changed, 13 insertions(+), 4 deletions(-)
> >
> > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> > index 5b47729a21..820a3387db 100644
> > --- a/target/riscv/insn_trans/trans_rvv.c.inc
> > +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> > @@ -263,10 +263,19 @@ static bool vext_check_st_index(DisasContext *s,
> int vd, int vs2, int nf,
> >  uint8_t eew)
> >  {
> >  int8_t emul = eew - s->sew + s->lmul;
> > -return (emul >= -3 && emul <= 3) &&
> > -require_align(vs2, emul) &&
> > -require_align(vd, s->lmul) &&
> > -require_nf(vd, nf, s->lmul);
> > +bool ret = (emul >= -3 && emul <= 3) &&
> > +   require_align(vs2, emul) &&
> > +   require_align(vd, s->lmul) &&
> > +   require_nf(vd, nf, s->lmul);
> > +#ifdef TARGET_RISCV32
>
> Don't use hardcoded macros for this, instead use get_xl()
>
> Alistair
>

Thanks for the review.
I'll fix it in my next revision patchset.

Regards,
Frank Chang


>
> > +/*
> > + * All Zve* extensions support all vector load and store
> instructions,
> > + * except Zve64* extensions do not support EEW=64 for index values
> > + * when XLEN=32. (Section 18.2)
> > + */
> > +ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true);
> > +#endif
> > +return ret;
> >  }
> >
> >  /*
> > --
> > 2.31.1
> >
> >
>

[PATCH v5 4/5] target/riscv: add support for svinval extension

[Weiwei Li]

- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, 
hfence.vvma and hfence.gvma except extension check
- do nothing other than extension check for sfence.w.inval and sfence.inval.ir

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Reviewed-by: Anup Patel 
---
 target/riscv/cpu.c  |  1 +
 target/riscv/cpu.h  |  1 +
 target/riscv/insn32.decode  |  7 ++
 target/riscv/insn_trans/trans_svinval.c.inc | 75 +
 target/riscv/translate.c|  1 +
 5 files changed, 85 insertions(+)
 create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ff6c86c85b..45ac98e06b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -668,6 +668,7 @@ static Property riscv_cpu_properties[] = {
 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 
+DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
 
 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d3d17cde82..c3d1845ca1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -327,6 +327,7 @@ struct RISCVCPU {
 bool ext_counters;
 bool ext_ifencei;
 bool ext_icsr;
+bool ext_svinval;
 bool ext_svnapot;
 bool ext_zfh;
 bool ext_zfhmin;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5bbedc254c..1d3ff1efe1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -809,3 +809,10 @@ fcvt_l_h   1100010  00010 . ... . 1010011 @r2_rm
 fcvt_lu_h  1100010  00011 . ... . 1010011 @r2_rm
 fcvt_h_l   1101010  00010 . ... . 1010011 @r2_rm
 fcvt_h_lu  1101010  00011 . ... . 1010011 @r2_rm
+
+# *** Svinval Standard Extension ***
+sinval_vma0001011 . . 000 0 1110011 @sfence_vma
+sfence_w_inval0001100 0 0 000 0 1110011
+sfence_inval_ir   0001100 1 0 000 0 1110011
+hinval_vvma   0010011 . . 000 0 1110011 @hfence_vvma
+hinval_gvma   0110011 . . 000 0 1110011 @hfence_gvma
diff --git a/target/riscv/insn_trans/trans_svinval.c.inc 
b/target/riscv/insn_trans/trans_svinval.c.inc
new file mode 100644
index 00..1dde665661
--- /dev/null
+++ b/target/riscv/insn_trans/trans_svinval.c.inc
@@ -0,0 +1,75 @@
+/*
+ * RISC-V translation routines for the Svinval Standard Instruction Set.
+ *
+ * Copyright (c) 2020-2021 PLCT lab
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#define REQUIRE_SVINVAL(ctx) do {\
+if (!RISCV_CPU(ctx->cs)->cfg.ext_svinval) {  \
+return false;\
+}\
+} while (0)
+
+static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
+{
+REQUIRE_SVINVAL(ctx);
+/* Do the same as sfence.vma currently */
+REQUIRE_EXT(ctx, RVS);
+#ifndef CONFIG_USER_ONLY
+gen_helper_tlb_flush(cpu_env);
+return true;
+#endif
+return false;
+}
+
+static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a)
+{
+REQUIRE_SVINVAL(ctx);
+REQUIRE_EXT(ctx, RVS);
+/* Do nothing currently */
+return true;
+}
+
+static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a)
+{
+REQUIRE_SVINVAL(ctx);
+REQUIRE_EXT(ctx, RVS);
+/* Do nothing currently */
+return true;
+}
+
+static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a)
+{
+REQUIRE_SVINVAL(ctx);
+/* Do the same as hfence.vvma currently */
+REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+gen_helper_hyp_tlb_flush(cpu_env);
+return true;
+#endif
+return false;
+}
+
+static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a)
+{
+REQUIRE_SVINVAL(ctx);
+/* Do the same as hfence.gvma currently */
+REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+gen_helper_hyp_gvma_tlb_flush(cpu_env);
+return true;
+#endif
+return false;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 615048ec87..4e5a9660a4 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -838,6 +838,7 @@ static uint32_t 

[PATCH v5 3/5] target/riscv: add support for svnapot extension

[Weiwei Li]

- add PTE_N bit
- add PTE_N bit check for inner PTE
- update address translation to support 64KiB continuous region (napot_bits = 4)

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Cc: Anup Patel 
---
 target/riscv/cpu.c|  2 ++
 target/riscv/cpu.h|  1 +
 target/riscv/cpu_bits.h   |  1 +
 target/riscv/cpu_helper.c | 18 +++---
 4 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9bc25d3055..ff6c86c85b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -668,6 +668,8 @@ static Property riscv_cpu_properties[] = {
 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 
+DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+
 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4d63086765..d3d17cde82 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -327,6 +327,7 @@ struct RISCVCPU {
 bool ext_counters;
 bool ext_ifencei;
 bool ext_icsr;
+bool ext_svnapot;
 bool ext_zfh;
 bool ext_zfhmin;
 
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 282cd8eecd..5501e9698b 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -486,6 +486,7 @@ typedef enum {
 #define PTE_A   0x040 /* Accessed */
 #define PTE_D   0x080 /* Dirty */
 #define PTE_SOFT0x300 /* Reserved for Software */
+#define PTE_N   0x8000 /* NAPOT translation */
 
 /* Page table PPN shift amount */
 #define PTE_PPN_SHIFT   10
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 1820188f41..c276760c7f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -621,12 +621,13 @@ restart:
 
 hwaddr ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;
 
+RISCVCPU *cpu = env_archcpu(env);
 if (!(pte & PTE_V)) {
 /* Invalid PTE */
 return TRANSLATE_FAIL;
 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
 /* Inner PTE, continue walking */
-if (pte & (PTE_D | PTE_A | PTE_U)) {
+if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_N)) {
 return TRANSLATE_FAIL;
 }
 base = ppn << PGSHIFT;
@@ -702,8 +703,19 @@ restart:
 /* for superpage mappings, make a fake leaf PTE for the TLB's
benefit. */
 target_ulong vpn = addr >> PGSHIFT;
-*physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
-(addr & ~TARGET_PAGE_MASK);
+
+int napot_bits = 0;
+if (cpu->cfg.ext_svnapot && (pte & (target_ulong)PTE_N)) {
+napot_bits = ctzl(ppn) + 1;
+if ((i != (levels - 1)) || (napot_bits != 4)) {
+return TRANSLATE_FAIL;
+}
+}
+
+*physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) |
+  (vpn & (((target_ulong)1 << napot_bits) - 1)) |
+  (vpn & (((target_ulong)1 << ptshift) - 1))
+) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
 
 /* set permissions on the TLB entry */
 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
-- 
2.17.1

[PATCH v5 5/5] target/riscv: add support for svpbmt extension

[Weiwei Li]

- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, 
since QEMU is sequentially consistent and doesn't model PMAs currently
- add PTE_PBMT bit check for inner PTE

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Cc: Heiko Stuebner 
Cc: Anup Patel 
---
 target/riscv/cpu.c| 1 +
 target/riscv/cpu.h| 1 +
 target/riscv/cpu_bits.h   | 2 ++
 target/riscv/cpu_helper.c | 4 +++-
 4 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 45ac98e06b..4f82bd00a3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -670,6 +670,7 @@ static Property riscv_cpu_properties[] = {
 
 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
 
 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c3d1845ca1..53f314c752 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -329,6 +329,7 @@ struct RISCVCPU {
 bool ext_icsr;
 bool ext_svinval;
 bool ext_svnapot;
+bool ext_svpbmt;
 bool ext_zfh;
 bool ext_zfhmin;
 
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 5501e9698b..24b7eb2b1f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -486,7 +486,9 @@ typedef enum {
 #define PTE_A   0x040 /* Accessed */
 #define PTE_D   0x080 /* Dirty */
 #define PTE_SOFT0x300 /* Reserved for Software */
+#define PTE_PBMT0x6000 /* Page-based memory types */
 #define PTE_N   0x8000 /* NAPOT translation */
+#define PTE_ATTR(PTE_N | PTE_PBMT) /* All attributes bits */
 
 /* Page table PPN shift amount */
 #define PTE_PPN_SHIFT   10
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index c276760c7f..9fffaccffb 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -625,9 +625,11 @@ restart:
 if (!(pte & PTE_V)) {
 /* Invalid PTE */
 return TRANSLATE_FAIL;
+} else if (!cpu->cfg.ext_svpbmt && (pte & (target_ulong)PTE_PBMT)) {
+return TRANSLATE_FAIL;
 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
 /* Inner PTE, continue walking */
-if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_N)) {
+if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
 return TRANSLATE_FAIL;
 }
 base = ppn << PGSHIFT;
-- 
2.17.1

[PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64

[Weiwei Li]

From: Guo Ren 

Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
need to ignore them. They cannot be a part of ppn.

1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
   4.4 Sv39: Page-Based 39-bit Virtual-Memory System
   4.5 Sv48: Page-Based 48-bit Virtual-Memory System

2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf

Signed-off-by: Guo Ren 
Tested-by: Bin Meng 
Reviewed-by: Liu Zhiwei 
Reviewed-by: Bin Meng 
Reviewed-by: Alistair Francis 
---
 target/riscv/cpu_bits.h   | 7 +++
 target/riscv/cpu_helper.c | 2 +-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 5a6d49aa64..282cd8eecd 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -490,6 +490,13 @@ typedef enum {
 /* Page table PPN shift amount */
 #define PTE_PPN_SHIFT   10
 
+/* Page table PPN mask */
+#if defined(TARGET_RISCV32)
+#define PTE_PPN_MASK0xUL
+#elif defined(TARGET_RISCV64)
+#define PTE_PPN_MASK0x3fULL
+#endif
+
 /* Leaf page shift amount */
 #define PGSHIFT 12
 
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 434a83e66a..26608ddf1c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -619,7 +619,7 @@ restart:
 return TRANSLATE_FAIL;
 }
 
-hwaddr ppn = pte >> PTE_PPN_SHIFT;
+hwaddr ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;
 
 if (!(pte & PTE_V)) {
 /* Invalid PTE */
-- 
2.17.1

[PATCH v5 0/5] support subsets of virtual memory extension

[Weiwei Li]

This patchset implements virtual memory related RISC-V extensions: Svnapot 
version 1.0, Svinval vesion 1.0, Svpbmt version 1.0. 

Specification:
https://github.com/riscv/virtual-memory/tree/main/specs

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-virtmem-upstream-v5

To test this implementation, specify cpu argument with 
'svinval=true,svnapot=true,svpbmt=true'.

This implementation can pass the riscv-tests for rv64ssvnapot.

v5:
* merge patch 
https://lore.kernel.org/qemu-devel/1569456861-8502-1-git-send-email-guo...@kernel.org/
* fix type compatibility in RV32

v4:
* fix encodings for hinval_vvma and hinval_gvma
* partition inner PTE check into several steps
* improve commit messages to describe changes

v3:
* drop "x-" in exposed properties

v2:
* add extension check for svnapot and svpbmt

Guo Ren (1):
  target/riscv: Ignore reserved bits in PTE for RV64

Weiwei Li (4):
  target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
  target/riscv: add support for svnapot extension
  target/riscv: add support for svinval extension
  target/riscv: add support for svpbmt extension

 target/riscv/cpu.c  |  4 ++
 target/riscv/cpu.h  |  3 +
 target/riscv/cpu_bits.h | 10 +++
 target/riscv/cpu_helper.c   | 23 ++-
 target/riscv/insn32.decode  |  7 ++
 target/riscv/insn_trans/trans_svinval.c.inc | 75 +
 target/riscv/translate.c|  1 +
 7 files changed, 120 insertions(+), 3 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc

-- 
2.17.1

[PATCH v5 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE

[Weiwei Li]

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Reviewed-by: Anup Patel 
---
 target/riscv/cpu_helper.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 26608ddf1c..1820188f41 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -626,6 +626,9 @@ restart:
 return TRANSLATE_FAIL;
 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
 /* Inner PTE, continue walking */
+if (pte & (PTE_D | PTE_A | PTE_U)) {
+return TRANSLATE_FAIL;
+}
 base = ppn << PGSHIFT;
 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
 /* Reserved leaf PTE flags: PTE_W */
-- 
2.17.1

Re: [PATCH v4 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto

[Weiwei Li]

在 2022/1/18 上午7:28, Alistair Francis 写道:

On Tue, Jan 11, 2022 at 1:57 PM Weiwei Li  wrote:

- share it between target/arm and target/riscv

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Reviewed-by: Philippe Mathieu-Daudé 

Do you mind fixing up the commit title?

Maybe something more like:

crypto: move sm4_sbox from target/arm

Otherwise:

Reviewed-by: Alistair Francis 

Alistair

Alistair


OK. I'll change this. Thanks for your comment.

Regards,

Weiwei Li


---
  crypto/meson.build |  1 +
  crypto/sm4.c   | 49 ++
  include/crypto/sm4.h   |  6 +
  target/arm/crypto_helper.c | 36 +---
  4 files changed, 57 insertions(+), 35 deletions(-)
  create mode 100644 crypto/sm4.c
  create mode 100644 include/crypto/sm4.h

diff --git a/crypto/meson.build b/crypto/meson.build
index 95a6a83504..f659fc9035 100644
--- a/crypto/meson.build
+++ b/crypto/meson.build
@@ -38,6 +38,7 @@ crypto_ss.add(when: 'CONFIG_SECRET_KEYRING', if_true: 
files('secret_keyring.c'))
  crypto_ss.add(when: 'CONFIG_AF_ALG', if_true: files('afalg.c', 
'cipher-afalg.c', 'hash-afalg.c'))
  crypto_ss.add(when: gnutls, if_true: files('tls-cipher-suites.c'))

+util_ss.add(files('sm4.c'))
  util_ss.add(files('aes.c'))
  util_ss.add(files('init.c'))
  if gnutls.found()
diff --git a/crypto/sm4.c b/crypto/sm4.c
new file mode 100644
index 00..9f0cd452c7
--- /dev/null
+++ b/crypto/sm4.c
@@ -0,0 +1,49 @@
+/*
+ * QEMU crypto sm4 support
+ *
+ * Copyright (C) 2013 - 2018 Linaro Ltd 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ */
+
+#include "qemu/osdep.h"
+#include "crypto/sm4.h"
+
+uint8_t const sm4_sbox[] = {
+0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
+0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
+0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
+0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
+0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
+0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
+0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
+0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
+0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
+0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
+0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
+0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
+0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
+0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
+0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
+0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
+0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
+0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
+0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
+0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
+0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
+0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
+0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
+0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
+0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
+0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
+0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
+0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
+0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
+0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
+0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
+0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
+};
+
diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
new file mode 100644
index 00..9bd3ebc62e
--- /dev/null
+++ b/include/crypto/sm4.h
@@ -0,0 +1,6 @@
+#ifndef QEMU_SM4_H
+#define QEMU_SM4_H
+
+extern const uint8_t sm4_sbox[256];
+
+#endif
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
index 28a84c2dbd..390020672a 100644
--- a/target/arm/crypto_helper.c
+++ b/target/arm/crypto_helper.c
@@ -15,6 +15,7 @@
  #include "exec/helper-proto.h"
  #include "tcg/tcg-gvec-desc.h"
  #include "crypto/aes.h"
+#include "crypto/sm4.h"
  #include "vec_internal.h"

  union CRYPTO_STATE {
@@ -694,41 +695,6 @@ DO_SM3TT(crypto_sm3tt2b, 3)

  #undef DO_SM3TT

-static uint8_t const sm4_sbox[] = {
-0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
-0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
-0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
-0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
-0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
-0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
-0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
-0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
-0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
-0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
-0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
-0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
-0x1e, 

Re: [PATCH v11 3/4] softmmu/dirtylimit: implement virtual CPU throttle

[Peter Xu]

On Mon, Jan 17, 2022 at 10:00:57PM +0800, Hyman Huang wrote:
> > This algorithm seems works even worse than the previous version, could you 
> > have
> > a look on what's wrong?
> What number the dirty-ring-size of qemu be configured? is it the same as
> previous version test?

It should be the same 4096.

The test environment can be slightly different, I used a larger guest this time
(20G, 40 cores), though.  Previously it should be a few gig only with a few 
cores.

Side note: would you also consider picking up this patch along with the series?

https://lore.kernel.org/qemu-devel/20211130080028.6474-1-pet...@redhat.com/

I wanted to make sure it lands before this series, e.g., when enabled both
dirty limit and migration, disabling dirty limit might trigger the bug already.

Thanks,

-- 
Peter Xu

[PATCH 2/2] python: use avocado's "new" runner

[John Snow]

The old legacy runner no longer seems to work with output logging, so we
can't see failure logs when a test case fails. The new runner doesn't
(seem to) support Coverage.py yet, but seeing error output is a more
important feature.

Signed-off-by: John Snow 
---
 python/avocado.cfg | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/python/avocado.cfg b/python/avocado.cfg
index c7722e7ecd..a460420059 100644
--- a/python/avocado.cfg
+++ b/python/avocado.cfg
@@ -1,5 +1,5 @@
 [run]
-test_runner = runner
+test_runner = nrunner
 
 [simpletests]
 # Don't show stdout/stderr in the test *summary*
-- 
2.31.1

[PATCH 1/2] python/aqmp: Fix negotiation with pre-"oob" QEMU

[John Snow]

QEMU versions prior to the "oob" capability *also* can't accept the
"enable" keyword argument at all. Fix the handshake process with older
QEMU versions.

Signed-off-by: John Snow 
---
 python/qemu/aqmp/qmp_client.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/python/qemu/aqmp/qmp_client.py b/python/qemu/aqmp/qmp_client.py
index 8105e29fa8..6b43e1dbbe 100644
--- a/python/qemu/aqmp/qmp_client.py
+++ b/python/qemu/aqmp/qmp_client.py
@@ -292,9 +292,9 @@ async def _negotiate(self) -> None:
 """
 self.logger.debug("Negotiating capabilities ...")
 
-arguments: Dict[str, List[str]] = {'enable': []}
+arguments: Dict[str, List[str]] = {}
 if self._greeting and 'oob' in self._greeting.QMP.capabilities:
-arguments['enable'].append('oob')
+arguments.setdefault('enable', []).append('oob')
 msg = self.make_execute_msg('qmp_capabilities', arguments=arguments)
 
 # It's not safe to use execute() here, because the reader/writers
-- 
2.31.1

[PATCH 0/2] Python: minor fixes

[John Snow]

GitLab: https://gitlab.com/jsnow/qemu/-/commits/python-aqmp-fixes
CI: https://gitlab.com/jsnow/qemu/-/pipelines/449959282

Fix a bug in async QMP, and fix a minor test annoyance.

John Snow (2):
  python/aqmp: Fix negotiation with pre-"oob" QEMU
  python: use avocado's "new" runner

 python/avocado.cfg | 2 +-
 python/qemu/aqmp/qmp_client.py | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

-- 
2.31.1

Re: [PATCH v4 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto

[Alistair Francis]

On Tue, Jan 11, 2022 at 1:57 PM Weiwei Li  wrote:
>
>- share it between target/arm and target/riscv
>
> Signed-off-by: Weiwei Li 
> Signed-off-by: Junqiang Wang 
> Reviewed-by: Philippe Mathieu-Daudé 

Do you mind fixing up the commit title?

Maybe something more like:

crypto: move sm4_sbox from target/arm

Otherwise:

Reviewed-by: Alistair Francis 

Alistair

Alistair

> ---
>  crypto/meson.build |  1 +
>  crypto/sm4.c   | 49 ++
>  include/crypto/sm4.h   |  6 +
>  target/arm/crypto_helper.c | 36 +---
>  4 files changed, 57 insertions(+), 35 deletions(-)
>  create mode 100644 crypto/sm4.c
>  create mode 100644 include/crypto/sm4.h
>
> diff --git a/crypto/meson.build b/crypto/meson.build
> index 95a6a83504..f659fc9035 100644
> --- a/crypto/meson.build
> +++ b/crypto/meson.build
> @@ -38,6 +38,7 @@ crypto_ss.add(when: 'CONFIG_SECRET_KEYRING', if_true: 
> files('secret_keyring.c'))
>  crypto_ss.add(when: 'CONFIG_AF_ALG', if_true: files('afalg.c', 
> 'cipher-afalg.c', 'hash-afalg.c'))
>  crypto_ss.add(when: gnutls, if_true: files('tls-cipher-suites.c'))
>
> +util_ss.add(files('sm4.c'))
>  util_ss.add(files('aes.c'))
>  util_ss.add(files('init.c'))
>  if gnutls.found()
> diff --git a/crypto/sm4.c b/crypto/sm4.c
> new file mode 100644
> index 00..9f0cd452c7
> --- /dev/null
> +++ b/crypto/sm4.c
> @@ -0,0 +1,49 @@
> +/*
> + * QEMU crypto sm4 support
> + *
> + * Copyright (C) 2013 - 2018 Linaro Ltd 
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "crypto/sm4.h"
> +
> +uint8_t const sm4_sbox[] = {
> +0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
> +0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
> +0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
> +0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
> +0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
> +0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
> +0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
> +0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
> +0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
> +0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
> +0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
> +0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
> +0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
> +0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
> +0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
> +0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
> +0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
> +0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
> +0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
> +0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
> +0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
> +0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
> +0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
> +0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
> +0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
> +0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
> +0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
> +0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
> +0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
> +0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
> +0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
> +0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
> +};
> +
> diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
> new file mode 100644
> index 00..9bd3ebc62e
> --- /dev/null
> +++ b/include/crypto/sm4.h
> @@ -0,0 +1,6 @@
> +#ifndef QEMU_SM4_H
> +#define QEMU_SM4_H
> +
> +extern const uint8_t sm4_sbox[256];
> +
> +#endif
> diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
> index 28a84c2dbd..390020672a 100644
> --- a/target/arm/crypto_helper.c
> +++ b/target/arm/crypto_helper.c
> @@ -15,6 +15,7 @@
>  #include "exec/helper-proto.h"
>  #include "tcg/tcg-gvec-desc.h"
>  #include "crypto/aes.h"
> +#include "crypto/sm4.h"
>  #include "vec_internal.h"
>
>  union CRYPTO_STATE {
> @@ -694,41 +695,6 @@ DO_SM3TT(crypto_sm3tt2b, 3)
>
>  #undef DO_SM3TT
>
> -static uint8_t const sm4_sbox[] = {
> -0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
> -0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
> -0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
> -0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
> -0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
> -0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
> -0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
> -0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
> -0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
> -0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
> -0x68, 

Re: [PATCH 1/2] python: introduce qmp-shell-wrap convenience tool

[John Snow]

On Mon, Jan 17, 2022 at 9:11 AM Daniel P. Berrangé  wrote:
>
> With the current 'qmp-shell' tool developers must first spawn QEMU with
> a suitable -qmp arg and then spawn qmp-shell in a separate terminal
> pointing to the right socket.
>
> With 'qmp-shell-wrap' developers can ignore QMP sockets entirely and
> just pass the QEMU command and arguments they want. The program will
> listen on a UNIX socket and tell QEMU to connect QMP to that.
>
> For example, this:
>
>  # qmp-shell-wrap -- qemu-system-x86_64 -display none
>
> Is roughly equivalent of running:
>
>  # qemu-system-x86_64 -display none -qmp qmp-shell-1234 &
>  # qmp-shell qmp-shell-1234
>
> Except that 'qmp-shell-wrap' switches the socket peers around so that
> it is the UNIX socket server and QEMU is the socket client. This makes
> QEMU reliably go away when qmp-shell-wrap exits, closing the server
> socket.
>
> Signed-off-by: Daniel P. Berrangé 
> ---
>  python/qemu/qmp/qmp_shell.py | 61 +---
>  scripts/qmp/qmp-shell-wrap   | 11 +++
>  2 files changed, 68 insertions(+), 4 deletions(-)
>  create mode 100755 scripts/qmp/qmp-shell-wrap
>
> diff --git a/python/qemu/qmp/qmp_shell.py b/python/qemu/qmp/qmp_shell.py
> index e7d7eb18f1..12f7d28afc 100644
> --- a/python/qemu/qmp/qmp_shell.py
> +++ b/python/qemu/qmp/qmp_shell.py
> @@ -86,6 +86,7 @@
>  import os
>  import re
>  import readline
> +from subprocess import Popen
>  import sys
>  from typing import (
>  Iterator,
> @@ -162,8 +163,10 @@ class QMPShell(qmp.QEMUMonitorProtocol):
>  :param verbose: Echo outgoing QMP messages to console.
>  """
>  def __init__(self, address: qmp.SocketAddrT,
> - pretty: bool = False, verbose: bool = False):
> -super().__init__(address)
> + pretty: bool = False,
> + verbose: bool = False,
> + server: bool = False):
> +super().__init__(address, server=server)
>  self._greeting: Optional[QMPMessage] = None
>  self._completer = QMPCompleter()
>  self._transmode = False
> @@ -404,8 +407,10 @@ class HMPShell(QMPShell):
>  :param verbose: Echo outgoing QMP messages to console.
>  """
>  def __init__(self, address: qmp.SocketAddrT,
> - pretty: bool = False, verbose: bool = False):
> -super().__init__(address, pretty, verbose)
> + pretty: bool = False,
> + verbose: bool = False,
> + server: bool = False):
> +super().__init__(address, pretty, verbose, server)
>  self._cpu_index = 0
>
>  def _cmd_completion(self) -> None:
> @@ -529,6 +534,54 @@ def main() -> None:
>  for _ in qemu.repl():
>  pass
>
> +def main_wrap() -> None:
> +"""
> +qmp-shell-wrap entry point: parse command line arguments and start the 
> REPL.
> +"""
> +parser = argparse.ArgumentParser()
> +parser.add_argument('-H', '--hmp', action='store_true',
> +help='Use HMP interface')
> +parser.add_argument('-v', '--verbose', action='store_true',
> +help='Verbose (echo commands sent and received)')
> +parser.add_argument('-p', '--pretty', action='store_true',
> +help='Pretty-print JSON')
> +
> +parser.add_argument('command', nargs=argparse.REMAINDER,
> +help='QEMU command line to invoke')
> +
> +args = parser.parse_args()
> +
> +cmd = args.command
> +if len(cmd) != 0 and cmd[0] == '--':
> +cmd = cmd[1:]
> +if len(cmd) == 0:
> +cmd = "qemu-system-x86_64"
> +
> +sockpath = "qmp-shell-wrap-%d" % os.getpid()
> +cmd += ["-qmp", "unix:%s" % sockpath]
> +
> +shell_class = HMPShell if args.hmp else QMPShell
> +
> +try:
> +address = shell_class.parse_address(sockpath)
> +except qmp.QMPBadPortError:
> +parser.error(f"Bad port number: {socketpath}")
> +return  # pycharm doesn't know error() is noreturn
> +
> +with shell_class(address, args.pretty, args.verbose, True) as qemu:
> +qemuproc = Popen(cmd)
> +
> +try:
> +qemu.accept()
> +except qmp.QMPConnectError:
> +die("Didn't get QMP greeting message")
> +except qmp.QMPCapabilitiesError:
> +die("Couldn't negotiate capabilities")
> +except OSError as err:
> +die(f"Couldn't connect to {sockpath}: {err!s}")
> +
> +for _ in qemu.repl():
> +pass
>
>  if __name__ == '__main__':
>  main()
> diff --git a/scripts/qmp/qmp-shell-wrap b/scripts/qmp/qmp-shell-wrap
> new file mode 100755
> index 00..9e94da114f
> --- /dev/null
> +++ b/scripts/qmp/qmp-shell-wrap
> @@ -0,0 +1,11 @@
> +#!/usr/bin/env python3
> +
> +import os
> +import sys
> +
> +sys.path.append(os.path.join(os.path.dirname(__file__), '..', '..', 
> 'python'))
> +from qemu.qmp import qmp_shell
> +
> +
> +if __name__ == '__main__':
> 

Re: iotest 040, 041, intermittent failure in netbsd VM

[John Snow]

On Mon, Jan 17, 2022 at 3:49 PM Peter Maydell  wrote:
>
> On Mon, 17 Jan 2022 at 20:35, John Snow  wrote:
>
> > Can you please try applying this temporary patch and running `./check
> > -qcow2 040 041` until you see a breakage and show me the output from
> > that?
>
> With this temporary patch the VM doesn't launch at all:

"Works for me", but I found out why.

>
> peter.mayd...@hackbox2.linaro.org:~/qemu-netbsd$ make -C build/
> vm-build-netbsd J=8 V=1 2>&1 | tee netbsd.log
> make: Entering directory '/home/peter.maydell/qemu-netbsd/build'
> /usr/bin/python3 -B /home/peter.maydell/qemu-netbsd/meson/meson.py
> introspect --targets --tests --benchmarks | /usr/bin/python3 -B
> scripts/mtest2m
> ake.py > Makefile.mtest
> { \
>   echo 'ninja-targets = \'; \
>   /usr/bin/ninja -t targets all | sed 's/:.*//; $!s/$/ \\/'; \
>   echo 'build-files = \'; \
>   /usr/bin/ninja -t query build.ninja | sed -n '1,/^  input:/d; /^
> outputs:/q; s/$/ \\/p'; \
> } > Makefile.ninja.tmp && mv Makefile.ninja.tmp Makefile.ninja
> (GIT="git" "/home/peter.maydell/qemu-netbsd/scripts/git-submodule.sh"
> update ui/keycodemapdb meson tests/fp/berkeley-testfloat-3
> tests/fp/berkeley-softfloat-3 dtc capstone slirp)
> (GIT="git" "/home/peter.maydell/qemu-netbsd/scripts/git-submodule.sh"
> update ui/keycodemapdb meson tests/fp/berkeley-testfloat-3
> tests/fp/berkeley-softfloat-3 dtc capstone slirp)
> /usr/bin/python3 -B /home/peter.maydell/qemu-netbsd/tests/vm/netbsd
> --debug  --jobs 8 --verbose--image
> "/home/peter.maydell/.cache/qemu-vm/images/netbsd.img"  --snapshot
> --build-qemu /home/peter.maydell/qemu-netbsd --
> DEBUG:root:Creating archive
> /home/peter.maydell/qemu-netbsd/build/vm-test-72ra6_8s.tmp/data-f706c.tar
> for src_dir dir: /home/peter.maydell/qemu-netbsd
> DEBUG:root:QEMU args: -nodefaults -m 4G -cpu max -netdev
> user,id=vnet,hostfwd=:127.0.0.1:0-:22,ipv6=no -device
> virtio-net-pci,netdev=vnet -vnc 127.0.0.1:0,to=20 -smp 8 -enable-kvm
> -drive 
> file=/home/peter.maydell/.cache/qemu-vm/images/netbsd.img,snapshot=on,if=none,id=drive0,cache=writeback
> -device virtio-blk,drive=drive0,bootindex=0 -drive
> file=/home/peter.maydell/qemu-netbsd/build/vm-test-72ra6_8s.tmp/data-f706c.tar,if=none,id=data-f706c,cache=writeback,format=raw
> -device virtio-blk,drive=data-f706c,serial=data-f706c,bootindex=1
> DEBUG:asyncio:Using selector: EpollSelector
> DEBUG:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:Registering
> .
> DEBUG:qemu.machine.machine:VM launch command: 'qemu-system-x86_64
> -display none -vga none -chardev
> socket,id=mon,path=/var/tmp/qemu-machine-0m15ou19/qemu-2335-7f3b78d7f128-monitor.sock
> -mon chardev=mon,mode=control -machine pc -chardev
> socket,id=console,path=/var/tmp/qemu-machine-0m15ou19/qemu-2335-7f3b78d7f128-console.sock,server=on,wait=off
> -serial chardev:console -nodefaults -m 4G -cpu max -netdev
> user,id=vnet,hostfwd=:127.0.0.1:0-:22,ipv6=no -device
> virtio-net-pci,netdev=vnet -vnc 127.0.0.1:0,to=20 -smp 8 -enable-kvm
> -drive 
> file=/home/peter.maydell/.cache/qemu-vm/images/netbsd.img,snapshot=on,if=none,id=drive0,cache=writeback
> -device virtio-blk,drive=drive0,bootindex=0 -drive
> file=/home/peter.maydell/qemu-netbsd/build/vm-test-72ra6_8s.tmp/data-f706c.tar,if=none,id=data-f706c,cache=writeback,format=raw
> -device virtio-blk,drive=data-f706c,serial=data-f706c,bootindex=1'
> DEBUG:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:Transitioning from
> 'Runstate.IDLE' to 'Runstate.CONNECTING'.
> DEBUG:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:Awaiting connection
> on /var/tmp/qemu-machine-0m15ou19/qemu-2335-7f3b78d7f128-monitor.sock
> ...
> DEBUG:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:Connection accepted.
> DEBUG:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:Awaiting greeting ...
> DEBUG:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:<-- {
>   "QMP": {
> "version": {
>   "qemu": {
> "micro": 1,
> "minor": 11,
> "major": 2
>   },
>   "package": "(Debian 1:2.11+dfsg-1ubuntu7.38)"
> },
> "capabilities": []
>   }
> }

Well, today I learned that:

(1) vm-build-XXX targets use your host system's QEMU to run that VM
(2) my QMP library cannot talk to QEMU 2.11.

That doesn't explain the intermittent netbsd failure yet, though.
(I guess this wasn't a failure point for you due to the aggressive
caching of the VM images? Unlucky.)

Here's another hotfix, this one I cannot easily test quickly (I don't
have 2.11 handy and it no longer builds for me),
but I think it'll fix the VM installation problem against older QEMU versions:

diff --git a/python/qemu/aqmp/qmp_client.py b/python/qemu/aqmp/qmp_client.py
index 8105e29fa8..6b43e1dbbe 100644
--- a/python/qemu/aqmp/qmp_client.py
+++ b/python/qemu/aqmp/qmp_client.py
@@ -292,9 +292,9 @@ async def _negotiate(self) -> None:
 """
 self.logger.debug("Negotiating capabilities ...")

-arguments: Dict[str, List[str]] = {'enable': []}
+arguments: Dict[str, List[str]] = {}
 if 

Re: [PATCH] softmmu: Provide a clue as to why device tree loading failed

[Alistair Francis]

On Sun, Jan 16, 2022 at 9:49 PM Bernhard Beschow  wrote:
>
> fdt_open_into() obligingly returns an error code in case the operation
> failed. So be obliging as well and use it in the error message.
>
> Signed-off-by: Bernhard Beschow 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  softmmu/device_tree.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/softmmu/device_tree.c b/softmmu/device_tree.c
> index 3965c834ca..31d1066940 100644
> --- a/softmmu/device_tree.c
> +++ b/softmmu/device_tree.c
> @@ -60,7 +60,8 @@ void *create_device_tree(int *sizep)
>  }
>  ret = fdt_open_into(fdt, fdt, *sizep);
>  if (ret) {
> -error_report("Unable to copy device tree in memory");
> +error_report("%s: Unable to copy device tree into memory: %s",
> + __func__, fdt_strerror(ret));
>  exit(1);
>  }
>
> @@ -104,7 +105,8 @@ void *load_device_tree(const char *filename_path, int 
> *sizep)
>
>  ret = fdt_open_into(fdt, fdt, dt_size);
>  if (ret) {
> -error_report("Unable to copy device tree in memory");
> +error_report("%s: Unable to copy device tree into memory: %s",
> + __func__, fdt_strerror(ret));
>  goto fail;
>  }
>
> --
> 2.34.1
>
>

Re: [PATCH 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:39 PM  wrote:
>
> From: Frank Chang 
>
> All Zve* extensions support the vector configuration instructions.
>
> Signed-off-by: Frank Chang 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 230c475d6c..c6280c7b0b 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -152,7 +152,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, 
> TCGv s2)
>  TCGv s1, dst;
>
>  if (!require_rvv(s) ||
> -!(has_ext(s, RVV) || s->ext_zve64f)) {
> +!(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
>  return false;
>  }
>
> @@ -188,7 +188,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, 
> TCGv s2)
>  TCGv dst;
>
>  if (!require_rvv(s) ||
> -!(has_ext(s, RVV) || s->ext_zve64f)) {
> +!(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
>  return false;
>  }
>
> --
> 2.31.1
>
>

Re: [PATCH 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:46 PM  wrote:
>
> From: Frank Chang 
>
> Vector narrowing conversion instructions are provided to and from all
> supported integer EEWs for Zve32f extension.
>
> Signed-off-by: Frank Chang 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index da0e501f85..5214cf08db 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2860,6 +2860,7 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr 
> *a)
>  return opfv_narrow_check(s, a) &&
> require_rvf(s) &&
> (s->sew != MO_64) &&
> +   require_zve32f(s) &&
> require_zve64f(s);
>  }
>
> @@ -2868,6 +2869,7 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr 
> *a)
>  return opfv_narrow_check(s, a) &&
> require_scale_rvf(s) &&
> (s->sew != MO_8) &&
> +   require_scale_zve32f(s) &&
> require_scale_zve64f(s);
>  }
>
> @@ -2918,6 +2920,7 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr 
> *a)
> vext_check_isa_ill(s) &&
> /* OPFV narrowing instructions ignore vs1 check */
> vext_check_sd(s, a->rd, a->rs2, a->vm) &&
> +   require_scale_zve32f(s) &&
> require_scale_zve64f(s);
>  }
>
> --
> 2.31.1
>
>

Re: [PATCH 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:50 PM  wrote:
>
> From: Frank Chang 
>
> Vector widening conversion instructions are provided to and from all
> supported integer EEWs for Zve32f extension.
>
> Signed-off-by: Frank Chang 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 18 ++
>  1 file changed, 18 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index c3f4dabf36..da0e501f85 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -77,6 +77,17 @@ static bool require_zve32f(DisasContext *s)
>  return s->ext_zve32f ? s->sew <= MO_32 : true;
>  }
>
> +static bool require_scale_zve32f(DisasContext *s)
> +{
> +/* RVV + Zve32f = RVV. */
> +if (has_ext(s, RVV)) {
> +return true;
> +}
> +
> +/* Zve32f doesn't support FP64. (Section 18.2) */
> +return s->ext_zve64f ? s->sew <= MO_16 : true;
> +}
> +
>  static bool require_zve64f(DisasContext *s)
>  {
>  /* RVV + Zve64f = RVV. */
> @@ -2356,6 +2367,7 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr 
> *a)
> (s->sew != MO_8) &&
> vext_check_isa_ill(s) &&
> vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
> +   require_scale_zve32f(s) &&
> require_scale_zve64f(s);
>  }
>
> @@ -2396,6 +2408,7 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr 
> *a)
> (s->sew != MO_8) &&
> vext_check_isa_ill(s) &&
> vext_check_ds(s, a->rd, a->rs2, a->vm) &&
> +   require_scale_zve32f(s) &&
> require_scale_zve64f(s);
>  }
>
> @@ -2427,6 +2440,7 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr 
> *a)
> (s->sew != MO_8) &&
> vext_check_isa_ill(s) &&
> vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
> +   require_scale_zve32f(s) &&
> require_scale_zve64f(s);
>  }
>
> @@ -2467,6 +2481,7 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr 
> *a)
> (s->sew != MO_8) &&
> vext_check_isa_ill(s) &&
> vext_check_dd(s, a->rd, a->rs2, a->vm) &&
> +   require_scale_zve32f(s) &&
> require_scale_zve64f(s);
>  }
>
> @@ -2731,6 +2746,7 @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr 
> *a)
>  {
>  return opfv_widen_check(s, a) &&
> require_rvf(s) &&
> +   require_zve32f(s) &&
> require_zve64f(s);
>  }
>
> @@ -2739,6 +2755,7 @@ static bool opffv_widen_check(DisasContext *s, arg_rmr 
> *a)
>  return opfv_widen_check(s, a) &&
> require_scale_rvf(s) &&
> (s->sew != MO_8) &&
> +   require_scale_zve32f(s) &&
> require_scale_zve64f(s);
>  }
>
> @@ -2791,6 +2808,7 @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr 
> *a)
> vext_check_isa_ill(s) &&
> /* OPFV widening instructions ignore vs1 check */
> vext_check_ds(s, a->rd, a->rs2, a->vm) &&
> +   require_scale_zve32f(s) &&
> require_scale_zve64f(s);
>  }
>
> --
> 2.31.1
>
>

Re: [PATCH 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:52 PM  wrote:
>
> From: Frank Chang 
>
> Signed-off-by: Frank Chang 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 5e98860a09..2b54c64f56 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -636,6 +636,7 @@ static Property riscv_cpu_properties[] = {
>  DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
>  DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
>  DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> +DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
>  DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
>  DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
>  DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> --
> 2.31.1
>
>

Re: [PATCH 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:45 PM  wrote:
>
> From: Frank Chang 
>
> Vector narrowing conversion instructions are provided to and from all
> supported integer EEWs for Zve64f extension.
>
> Signed-off-by: Frank Chang 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 9 ++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 9ca8d502b2..230c475d6c 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2824,14 +2824,16 @@ static bool opfxv_narrow_check(DisasContext *s, 
> arg_rmr *a)
>  {
>  return opfv_narrow_check(s, a) &&
> require_rvf(s) &&
> -   (s->sew != MO_64);
> +   (s->sew != MO_64) &&
> +   require_zve64f(s);
>  }
>
>  static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
>  {
>  return opfv_narrow_check(s, a) &&
> require_scale_rvf(s) &&
> -   (s->sew != MO_8);
> +   (s->sew != MO_8) &&
> +   require_scale_zve64f(s);
>  }
>
>  #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)\
> @@ -2880,7 +2882,8 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr 
> *a)
> require_scale_rvf(s) &&
> vext_check_isa_ill(s) &&
> /* OPFV narrowing instructions ignore vs1 check */
> -   vext_check_sd(s, a->rd, a->rs2, a->vm);
> +   vext_check_sd(s, a->rd, a->rs2, a->vm) &&
> +   require_scale_zve64f(s);
>  }
>
>  #define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM)  \
> --
> 2.31.1
>
>

Re: [PATCH 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:48 PM  wrote:
>
> From: Frank Chang 
>
> Vector single-width floating-point reduction operations for EEW=32 are
> supported for Zve32f extension.
>
> Signed-off-by: Frank Chang 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 1f5a75eca7..c3f4dabf36 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2974,6 +2974,7 @@ static bool freduction_check(DisasContext *s, arg_rmrr 
> *a)
>  {
>  return reduction_check(s, a) &&
> require_rvf(s) &&
> +   require_zve32f(s) &&
> require_zve64f(s);
>  }
>
> --
> 2.31.1
>
>

Re: [PATCH 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:34 PM  wrote:
>
> From: Frank Chang 
>
> Signed-off-by: Frank Chang 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c| 4 ++--
>  target/riscv/cpu.h| 1 +
>  target/riscv/cpu_helper.c | 2 +-
>  target/riscv/csr.c| 2 +-
>  target/riscv/translate.c  | 2 ++
>  5 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 38cd11a8ae..5e98860a09 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -562,8 +562,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>  }
>  set_vext_version(env, vext_version);
>  }
> -if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) {
> -error_setg(errp, "Zve64f extension depends upon RVF.");
> +if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) 
> {
> +error_setg(errp, "Zve32f/Zve64f extension depends upon RVF.");
>  return;
>  }
>  if (cpu->cfg.ext_j) {
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index d7b2db2b2f..3f3b3bb062 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -317,6 +317,7 @@ struct RISCVCPU {
>  bool ext_icsr;
>  bool ext_zfh;
>  bool ext_zfhmin;
> +bool ext_zve32f;
>  bool ext_zve64f;
>
>  char *priv_spec;
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 52d93a41fd..7d8b34cf1a 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -77,7 +77,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong 
> *pc,
>  *pc = env->pc;
>  *cs_base = 0;
>
> -if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) {
> +if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || 
> cpu->cfg.ext_zve64f) {
>  /*
>   * If env->vl equals to VLMAX, we can use generic vector operation
>   * expanders (GVEC) to accerlate the vector operations.
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 340b9661a8..7bd3a5d1af 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -51,7 +51,7 @@ static RISCVException vs(CPURISCVState *env, int csrno)
>  RISCVCPU *cpu = RISCV_CPU(cs);
>
>  if (env->misa_ext & RVV ||
> -cpu->cfg.ext_zve64f) {
> +cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
>  #if !defined(CONFIG_USER_ONLY)
>  if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
>  return RISCV_EXCP_ILLEGAL_INST;
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 8c3b0168b7..3d89a6650d 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -78,6 +78,7 @@ typedef struct DisasContext {
>  bool ext_ifencei;
>  bool ext_zfh;
>  bool ext_zfhmin;
> +bool ext_zve32f;
>  bool ext_zve64f;
>  bool hlsx;
>  /* vector extension */
> @@ -706,6 +707,7 @@ static void riscv_tr_init_disas_context(DisasContextBase 
> *dcbase, CPUState *cs)
>  ctx->ext_ifencei = cpu->cfg.ext_ifencei;
>  ctx->ext_zfh = cpu->cfg.ext_zfh;
>  ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
> +ctx->ext_zve32f = cpu->cfg.ext_zve32f;
>  ctx->ext_zve64f = cpu->cfg.ext_zve64f;
>  ctx->vlen = cpu->cfg.vlen;
>  ctx->elen = cpu->cfg.elen;
> --
> 2.31.1
>
>

Re: [PATCH 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:48 PM  wrote:
>
> From: Frank Chang 
>
> Zve32f extension requires the scalar processor to implement the F
> extension and implement all vector floating-point instructions for
> floating-point operands with EEW=32 (i.e., no widening floating-point
> operations).
>
> Signed-off-by: Frank Chang 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 21 +
>  1 file changed, 21 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index c6280c7b0b..1f5a75eca7 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -66,6 +66,17 @@ static bool require_scale_rvf(DisasContext *s)
>  }
>  }
>
> +static bool require_zve32f(DisasContext *s)
> +{
> +/* RVV + Zve32f = RVV. */
> +if (has_ext(s, RVV)) {
> +return true;
> +}
> +
> +/* Zve32f doesn't support FP64. (Section 18.2) */
> +return s->ext_zve32f ? s->sew <= MO_32 : true;
> +}
> +
>  static bool require_zve64f(DisasContext *s)
>  {
>  /* RVV + Zve64f = RVV. */
> @@ -2227,6 +2238,7 @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
> +   require_zve32f(s) &&
> require_zve64f(s);
>  }
>
> @@ -2308,6 +2320,7 @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> vext_check_ss(s, a->rd, a->rs2, a->vm) &&
> +   require_zve32f(s) &&
> require_zve64f(s);
>  }
>
> @@ -2530,6 +2543,7 @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
> vext_check_isa_ill(s) &&
> /* OPFV instructions ignore vs1 check */
> vext_check_ss(s, a->rd, a->rs2, a->vm) &&
> +   require_zve32f(s) &&
> require_zve64f(s);
>  }
>
> @@ -2596,6 +2610,7 @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr 
> *a)
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
> +   require_zve32f(s) &&
> require_zve64f(s);
>  }
>
> @@ -2610,6 +2625,7 @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr 
> *a)
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> vext_check_ms(s, a->rd, a->rs2) &&
> +   require_zve32f(s) &&
> require_zve64f(s);
>  }
>
> @@ -2632,6 +2648,7 @@ static bool trans_vfmv_v_f(DisasContext *s, 
> arg_vfmv_v_f *a)
>  require_rvf(s) &&
>  vext_check_isa_ill(s) &&
>  require_align(a->rd, s->lmul) &&
> +require_zve32f(s) &&
>  require_zve64f(s)) {
>  gen_set_rm(s, RISCV_FRM_DYN);
>
> @@ -3366,6 +3383,7 @@ static bool trans_vfmv_f_s(DisasContext *s, 
> arg_vfmv_f_s *a)
>  if (require_rvv(s) &&
>  require_rvf(s) &&
>  vext_check_isa_ill(s) &&
> +require_zve32f(s) &&
>  require_zve64f(s)) {
>  gen_set_rm(s, RISCV_FRM_DYN);
>
> @@ -3393,6 +3411,7 @@ static bool trans_vfmv_s_f(DisasContext *s, 
> arg_vfmv_s_f *a)
>  if (require_rvv(s) &&
>  require_rvf(s) &&
>  vext_check_isa_ill(s) &&
> +require_zve32f(s) &&
>  require_zve64f(s)) {
>  gen_set_rm(s, RISCV_FRM_DYN);
>
> @@ -3445,6 +3464,7 @@ static bool fslideup_check(DisasContext *s, arg_rmrr *a)
>  {
>  return slideup_check(s, a) &&
> require_rvf(s) &&
> +   require_zve32f(s) &&
> require_zve64f(s);
>  }
>
> @@ -3452,6 +3472,7 @@ static bool fslidedown_check(DisasContext *s, arg_rmrr 
> *a)
>  {
>  return slidedown_check(s, a) &&
> require_rvf(s) &&
> +   require_zve32f(s) &&
> require_zve64f(s);
>  }
>
> --
> 2.31.1
>
>

Re: [PATCH 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:42 PM  wrote:
>
> From: Frank Chang 
>
> Vector widening conversion instructions are provided to and from all
> supported integer EEWs for Zve64f extension.
>
> Signed-off-by: Frank Chang 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 32 +++--
>  1 file changed, 25 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index d7e288b87f..9ca8d502b2 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -77,6 +77,17 @@ static bool require_zve64f(DisasContext *s)
>  return s->ext_zve64f ? s->sew <= MO_32 : true;
>  }
>
> +static bool require_scale_zve64f(DisasContext *s)
> +{
> +/* RVV + Zve64f = RVV. */
> +if (has_ext(s, RVV)) {
> +return true;
> +}
> +
> +/* Zve64f doesn't support FP64. (Section 18.2) */
> +return s->ext_zve64f ? s->sew <= MO_16 : true;
> +}
> +
>  /* Destination vector register group cannot overlap source mask register. */
>  static bool require_vm(int vm, int vd)
>  {
> @@ -2331,7 +2342,8 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr 
> *a)
> require_scale_rvf(s) &&
> (s->sew != MO_8) &&
> vext_check_isa_ill(s) &&
> -   vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
> +   vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
> +   require_scale_zve64f(s);
>  }
>
>  /* OPFVV with WIDEN */
> @@ -2370,7 +2382,8 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr 
> *a)
> require_scale_rvf(s) &&
> (s->sew != MO_8) &&
> vext_check_isa_ill(s) &&
> -   vext_check_ds(s, a->rd, a->rs2, a->vm);
> +   vext_check_ds(s, a->rd, a->rs2, a->vm) &&
> +   require_scale_zve64f(s);
>  }
>
>  /* OPFVF with WIDEN */
> @@ -2400,7 +2413,8 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr 
> *a)
> require_scale_rvf(s) &&
> (s->sew != MO_8) &&
> vext_check_isa_ill(s) &&
> -   vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
> +   vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
> +   require_scale_zve64f(s);
>  }
>
>  /* WIDEN OPFVV with WIDEN */
> @@ -2439,7 +2453,8 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr 
> *a)
> require_scale_rvf(s) &&
> (s->sew != MO_8) &&
> vext_check_isa_ill(s) &&
> -   vext_check_dd(s, a->rd, a->rs2, a->vm);
> +   vext_check_dd(s, a->rd, a->rs2, a->vm) &&
> +   require_scale_zve64f(s);
>  }
>
>  /* WIDEN OPFVF with WIDEN */
> @@ -2698,14 +2713,16 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr 
> *a)
>  static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
>  {
>  return opfv_widen_check(s, a) &&
> -   require_rvf(s);
> +   require_rvf(s) &&
> +   require_zve64f(s);
>  }
>
>  static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
>  {
>  return opfv_widen_check(s, a) &&
> require_scale_rvf(s) &&
> -   (s->sew != MO_8);
> +   (s->sew != MO_8) &&
> +   require_scale_zve64f(s);
>  }
>
>  #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \
> @@ -2756,7 +2773,8 @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr 
> *a)
> require_scale_rvf(s) &&
> vext_check_isa_ill(s) &&
> /* OPFV widening instructions ignore vs1 check */
> -   vext_check_ds(s, a->rd, a->rs2, a->vm);
> +   vext_check_ds(s, a->rd, a->rs2, a->vm) &&
> +   require_scale_zve64f(s);
>  }
>
>  #define GEN_OPFXV_WIDEN_TRANS(NAME)\
> --
> 2.31.1
>
>

Re: [PATCH 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:44 PM  wrote:
>
> From: Frank Chang 
>
> Signed-off-by: Frank Chang 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 01239620ca..38cd11a8ae 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -636,6 +636,7 @@ static Property riscv_cpu_properties[] = {
>  DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
>  DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
>  DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> +DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
>  DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
>  DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
>
> --
> 2.31.1
>
>

Re: [PATCH v5 00/13] Add riscv kvm accel support

[Alistair Francis]

On Wed, Jan 12, 2022 at 6:20 PM Yifei Jiang via  wrote:
>
> This series adds both riscv32 and riscv64 kvm support, and implements
> migration based on riscv.
>
> Because of RISC-V KVM has been merged into the Linux master, so this
> series are changed from RFC to patch.
>
> Several steps to use this:
> 1. Build emulation
> $ ./configure --target-list=riscv64-softmmu
> $ make -j$(nproc)
>
> 2. Build kernel
>
> 3. Build QEMU VM
> Cross built in riscv toolchain.
> $ PKG_CONFIG_LIBDIR=
> $ export PKG_CONFIG_SYSROOT_DIR=
> $ ./configure --target-list=riscv64-softmmu --enable-kvm \
> --cross-prefix=riscv64-linux-gnu- --disable-libiscsi --disable-glusterfs \
> --disable-libusb --disable-usb-redir --audio-drv-list= --disable-opengl \
> --disable-libxml2
> $ make -j$(nproc)
>
> 4. Start emulation
> $ ./qemu-system-riscv64 -M virt -m 4096M -cpu rv64 -nographic \
> -name guest=riscv-hyp,debug-threads=on \
> -smp 4 \
> -bios ./fw_jump.bin \
> -kernel ./Image \
> -drive file=./hyp.img,format=raw,id=hd0 \
> -device virtio-blk-device,drive=hd0 \
> -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"
>
> 5. Start kvm-acceled QEMU VM in emulation
> $ ./qemu-system-riscv64 -M virt,accel=kvm -m 1024M -cpu host -nographic \
> -name guest=riscv-guset \
> -smp 2 \
> -bios none \
> -kernel ./Image \
> -drive file=./guest.img,format=raw,id=hd0 \
> -device virtio-blk-device,drive=hd0 \
> -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"
>
> Changes since patch v4
> - Commit enable kvm accel as an independent patch.
> - Bugfix some checkpatch errors.
> - Bugfix lost a interrupt in the sifive_u machine.
>
> Changes since patch v3
> - Re-write the for-loop in sifive_plic_create().
> - Drop unnecessary change in hw/riscv/virt.c.
> - Use serial to handle console sbi call.
>
> Changes since patch v2
> - Create a macro for get and put timer csr.
> - Remove M-mode PLIC contexts when kvm is enabled.
> - Add get timer frequency.
> - Move cpu_host_load to vmstate_kvmtimer.
>
> Changes since patch v1
> - Rebase on recent commit a216e7cf119c91ffdf5931834a1a030ebea40d70
> - Sync-up headers with Linux-5.16-rc4.
> - Fixbug in kvm_arch_init_vcpu.
> - Create a macro for get and put regs csr.
> - Start kernel directly when kvm_enabled.
> - Use riscv_cpu_set_irq to inject KVM interrupts.
> - Use the Semihosting Console API for RISC-V kvm handle sbi.
> - Update vmstate_riscv_cpu version id.
>   Placing kvm_timer into a subsection.
>
> Changes since RFC v6
> - Rebase on recent commit 8627edfb3f1fca24a96a0954148885c3241c10f8
> - Sync-up headers with Linux-5.16-rc1
>
> Changes since RFC v5
> - Rebase on QEMU v6.1.0-rc1 and kvm-riscv linux v19.
> - Move kvm interrupt setting to riscv_cpu_update_mip().
> - Replace __u64 with uint64_t.
>
> Changes since RFC v4
> - Rebase on QEMU v6.0.0-rc2 and kvm-riscv linux v17.
> - Remove time scaling support as software solution is incomplete.
>   Because it will cause unacceptable performance degradation. and
>   We will post a better solution.
> - Revise according to Alistair's review comments.
>   - Remove compile time XLEN checks in kvm_riscv_reg_id
>   - Surround TYPE_RISCV_CPU_HOST definition by CONFIG_KVM and share
> it between RV32 and RV64.
>   - Add kvm-stub.c for reduce unnecessary compilation checks.
>   - Add riscv_setup_direct_kernel() to direct boot kernel for KVM.
>
> Changes since RFC v3
> - Rebase on QEMU v5.2.0-rc2 and kvm-riscv linux v15.
> - Add time scaling support(New patches 13, 14 and 15).
> - Fix the bug that guest vm can't reboot.
>
> Changes since RFC v2
> - Fix checkpatch error at target/riscv/sbi_ecall_interface.h.
> - Add riscv migration support.
>
> Changes since RFC v1
> - Add separate SBI ecall interface header.
> - Add riscv32 kvm accel support.
>
> Yifei Jiang (13):
>   update-linux-headers: Add asm-riscv/kvm.h
>   target/riscv: Add target/riscv/kvm.c to place the public kvm interface
>   target/riscv: Implement function kvm_arch_init_vcpu
>   target/riscv: Implement kvm_arch_get_registers
>   target/riscv: Implement kvm_arch_put_registers
>   target/riscv: Support start kernel directly by KVM
>   target/riscv: Support setting external interrupt by KVM
>   target/riscv: Handle KVM_EXIT_RISCV_SBI exit
>   target/riscv: Add host cpu type
>   target/riscv: Add kvm_riscv_get/put_regs_timer
>   target/riscv: Implement virtual time adjusting with vm state changing
>   target/riscv: Support virtual time context synchronization
>   target/riscv: enable riscv kvm accel

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  hw/intc/sifive_plic.c  |  20 +-
>  hw/riscv/boot.c|  16 +-
>  hw/riscv/virt.c|  83 +++--
>  include/hw/riscv/boot.h|   1 +
>  linux-headers/asm-riscv/kvm.h  | 128 +++
>  meson.build|   2 +
>  target/riscv/cpu.c |  29 +-
>  target/riscv/cpu.h   

Re: [PATCH 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:41 PM  wrote:
>
> From: Frank Chang 
>
> Vector single-width floating-point reduction operations for EEW=32 are
> supported for Zve64f extension.
>
> Signed-off-by: Frank Chang 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 0aa8b7918f..d7e288b87f 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2935,7 +2935,8 @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, 
> reduction_widen_check)
>  static bool freduction_check(DisasContext *s, arg_rmrr *a)
>  {
>  return reduction_check(s, a) &&
> -   require_rvf(s);
> +   require_rvf(s) &&
> +   require_zve64f(s);
>  }
>
>  GEN_OPFVV_TRANS(vfredsum_vs, freduction_check)
> --
> 2.31.1
>
>

Re: [PATCH] softmmu/device_tree: Remove redundant pointer assignment

[Alistair Francis]

On Tue, Jan 11, 2022 at 1:28 PM Yanan Wang via  wrote:
>
> The pointer assignment "const char *p = path;" in function
> qemu_fdt_add_path is unnecessary. Let's remove it and just
> use the "path" passed in. No functional change.
>
> Suggested-by: Richard Henderson 
> Signed-off-by: Yanan Wang 

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
> Based on: softmmu/device_tree: Silence compiler warning with 
> --enable-sanitizers
> https://patchew.org/QEMU/20220107133844.145039-1-th...@redhat.com/
> ---
>  softmmu/device_tree.c | 9 -
>  1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/softmmu/device_tree.c b/softmmu/device_tree.c
> index 9e96f5ecd5..8897c79ea4 100644
> --- a/softmmu/device_tree.c
> +++ b/softmmu/device_tree.c
> @@ -556,7 +556,6 @@ int qemu_fdt_add_subnode(void *fdt, const char *name)
>  int qemu_fdt_add_path(void *fdt, const char *path)
>  {
>  const char *name;
> -const char *p = path;
>  int namelen, retval;
>  int parent = 0;
>
> @@ -565,9 +564,9 @@ int qemu_fdt_add_path(void *fdt, const char *path)
>  }
>
>  do {
> -name = p + 1;
> -p = strchr(name, '/');
> -namelen = p != NULL ? p - name : strlen(name);
> +name = path + 1;
> +path = strchr(name, '/');
> +namelen = path != NULL ? path - name : strlen(name);
>
>  retval = fdt_subnode_offset_namelen(fdt, parent, name, namelen);
>  if (retval < 0 && retval != -FDT_ERR_NOTFOUND) {
> @@ -584,7 +583,7 @@ int qemu_fdt_add_path(void *fdt, const char *path)
>  }
>
>  parent = retval;
> -} while (p);
> +} while (path);
>
>  return retval;
>  }
> --
> 2.27.0
>
>

Re: [PATCH 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:43 PM  wrote:
>
> From: Frank Chang 
>
> Zve64f extension requires the scalar processor to implement the F
> extension and implement all vector floating-point instructions for
> floating-point operands with EEW=32 (i.e., no widening floating-point
> operations).
>
> Signed-off-by: Frank Chang 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 41 +++--
>  1 file changed, 31 insertions(+), 10 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index a1e403fe86..0aa8b7918f 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -66,6 +66,17 @@ static bool require_scale_rvf(DisasContext *s)
>  }
>  }
>
> +static bool require_zve64f(DisasContext *s)
> +{
> +/* RVV + Zve64f = RVV. */
> +if (has_ext(s, RVV)) {
> +return true;
> +}
> +
> +/* Zve64f doesn't support FP64. (Section 18.2) */
> +return s->ext_zve64f ? s->sew <= MO_32 : true;
> +}
> +
>  /* Destination vector register group cannot overlap source mask register. */
>  static bool require_vm(int vm, int vd)
>  {
> @@ -2204,7 +2215,8 @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
>  return require_rvv(s) &&
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> -   vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
> +   vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
> +   require_zve64f(s);
>  }
>
>  /* OPFVV without GVEC IR */
> @@ -2284,7 +2296,8 @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
>  return require_rvv(s) &&
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> -   vext_check_ss(s, a->rd, a->rs2, a->vm);
> +   vext_check_ss(s, a->rd, a->rs2, a->vm) &&
> +   require_zve64f(s);
>  }
>
>  /* OPFVF without GVEC IR */
> @@ -2501,7 +2514,8 @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> /* OPFV instructions ignore vs1 check */
> -   vext_check_ss(s, a->rd, a->rs2, a->vm);
> +   vext_check_ss(s, a->rd, a->rs2, a->vm) &&
> +   require_zve64f(s);
>  }
>
>  static bool do_opfv(DisasContext *s, arg_rmr *a,
> @@ -2566,7 +2580,8 @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr 
> *a)
>  return require_rvv(s) &&
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> -   vext_check_mss(s, a->rd, a->rs1, a->rs2);
> +   vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
> +   require_zve64f(s);
>  }
>
>  GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
> @@ -2579,7 +2594,8 @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr 
> *a)
>  return require_rvv(s) &&
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> -   vext_check_ms(s, a->rd, a->rs2);
> +   vext_check_ms(s, a->rd, a->rs2) &&
> +   require_zve64f(s);
>  }
>
>  GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
> @@ -2600,7 +2616,8 @@ static bool trans_vfmv_v_f(DisasContext *s, 
> arg_vfmv_v_f *a)
>  if (require_rvv(s) &&
>  require_rvf(s) &&
>  vext_check_isa_ill(s) &&
> -require_align(a->rd, s->lmul)) {
> +require_align(a->rd, s->lmul) &&
> +require_zve64f(s)) {
>  gen_set_rm(s, RISCV_FRM_DYN);
>
>  TCGv_i64 t1;
> @@ -3326,7 +3343,8 @@ static bool trans_vfmv_f_s(DisasContext *s, 
> arg_vfmv_f_s *a)
>  {
>  if (require_rvv(s) &&
>  require_rvf(s) &&
> -vext_check_isa_ill(s)) {
> +vext_check_isa_ill(s) &&
> +require_zve64f(s)) {
>  gen_set_rm(s, RISCV_FRM_DYN);
>
>  unsigned int ofs = (8 << s->sew);
> @@ -3352,7 +3370,8 @@ static bool trans_vfmv_s_f(DisasContext *s, 
> arg_vfmv_s_f *a)
>  {
>  if (require_rvv(s) &&
>  require_rvf(s) &&
> -vext_check_isa_ill(s)) {
> +vext_check_isa_ill(s) &&
> +require_zve64f(s)) {
>  gen_set_rm(s, RISCV_FRM_DYN);
>
>  /* The instructions ignore LMUL and vector register group. */
> @@ -3403,13 +3422,15 @@ GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, 
> slidedown_check)
>  static bool fslideup_check(DisasContext *s, arg_rmrr *a)
>  {
>  return slideup_check(s, a) &&
> -   require_rvf(s);
> +   require_rvf(s) &&
> +   require_zve64f(s);
>  }
>
>  static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
>  {
>  return slidedown_check(s, a) &&
> -   require_rvf(s);
> +   require_rvf(s) &&
> +   require_zve64f(s);
>  }
>
>  GEN_OPFVF_TRANS(vfslide1up_vf, fslideup_check)
> --
> 2.31.1
>
>

Re: [PATCH 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:37 PM  wrote:
>
> From: Frank Chang 
>
> All Zve* extensions support all vector fixed-point arithmetic
> instructions, except that vsmul.vv and vsmul.vx are not supported
> for EEW=64 in Zve64*.
>
> Signed-off-by: Frank Chang 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 27 +++--
>  1 file changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 658cfbe10e..a1e403fe86 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2121,8 +2121,31 @@ GEN_OPIVX_TRANS(vasub_vx,  opivx_check)
>  GEN_OPIVX_TRANS(vasubu_vx,  opivx_check)
>
>  /* Vector Single-Width Fractional Multiply with Rounding and Saturation */
> -GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
> -GEN_OPIVX_TRANS(vsmul_vx,  opivx_check)
> +
> +static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)
> +{
> +/*
> + * All Zve* extensions support all vector fixed-point arithmetic
> + * instructions, except that vsmul.vv and vsmul.vx are not supported
> + * for EEW=64 in Zve64*. (Section 18.2)
> + */
> +return opivv_check(s, a) &&
> +   (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
> +}
> +
> +static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
> +{
> +/*
> + * All Zve* extensions support all vector fixed-point arithmetic
> + * instructions, except that vsmul.vv and vsmul.vx are not supported
> + * for EEW=64 in Zve64*. (Section 18.2)
> + */
> +return opivx_check(s, a) &&
> +   (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
> +}
> +
> +GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)
> +GEN_OPIVX_TRANS(vsmul_vx,  vsmul_vx_check)
>
>  /* Vector Single-Width Scaling Shift Instructions */
>  GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
> --
> 2.31.1
>
>

Re: [PATCH 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:36 PM  wrote:
>
> From: Frank Chang 
>
> All Zve* extensions support all vector integer instructions,
> except that the vmulh integer multiply variants that return the
> high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx,
> vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.
>
> Signed-off-by: Frank Chang 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 39 +
>  1 file changed, 33 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 820a3387db..658cfbe10e 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1906,14 +1906,41 @@ GEN_OPIVX_TRANS(vmaxu_vx, opivx_check)
>  GEN_OPIVX_TRANS(vmax_vx,  opivx_check)
>
>  /* Vector Single-Width Integer Multiply Instructions */
> +
> +static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a)
> +{
> +/*
> + * All Zve* extensions support all vector integer instructions,
> + * except that the vmulh integer multiply variants
> + * that return the high word of the product
> + * (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx)
> + * are not included for EEW=64 in Zve64*. (Section 18.2)
> + */
> +return opivv_check(s, a) &&
> +   (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
> +}
> +
> +static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
> +{
> +/*
> + * All Zve* extensions support all vector integer instructions,
> + * except that the vmulh integer multiply variants
> + * that return the high word of the product
> + * (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx)
> + * are not included for EEW=64 in Zve64*. (Section 18.2)
> + */
> +return opivx_check(s, a) &&
> +   (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
> +}
> +
>  GEN_OPIVV_GVEC_TRANS(vmul_vv,  mul)
> -GEN_OPIVV_TRANS(vmulh_vv, opivv_check)
> -GEN_OPIVV_TRANS(vmulhu_vv, opivv_check)
> -GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check)
> +GEN_OPIVV_TRANS(vmulh_vv, vmulh_vv_check)
> +GEN_OPIVV_TRANS(vmulhu_vv, vmulh_vv_check)
> +GEN_OPIVV_TRANS(vmulhsu_vv, vmulh_vv_check)
>  GEN_OPIVX_GVEC_TRANS(vmul_vx,  muls)
> -GEN_OPIVX_TRANS(vmulh_vx, opivx_check)
> -GEN_OPIVX_TRANS(vmulhu_vx, opivx_check)
> -GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check)
> +GEN_OPIVX_TRANS(vmulh_vx, vmulh_vx_check)
> +GEN_OPIVX_TRANS(vmulhu_vx, vmulh_vx_check)
> +GEN_OPIVX_TRANS(vmulhsu_vx, vmulh_vx_check)
>
>  /* Vector Integer Divide Instructions */
>  GEN_OPIVV_TRANS(vdivu_vv, opivv_check)
> --
> 2.31.1
>
>

Re: [PATCH 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:34 PM  wrote:
>
> From: Frank Chang 
>
> All Zve* extensions support all vector load and store instructions,
> except Zve64* extensions do not support EEW=64 for index values when
> XLEN=32.
>
> Signed-off-by: Frank Chang 
> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 17 +
>  1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 5b47729a21..820a3387db 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -263,10 +263,19 @@ static bool vext_check_st_index(DisasContext *s, int 
> vd, int vs2, int nf,
>  uint8_t eew)
>  {
>  int8_t emul = eew - s->sew + s->lmul;
> -return (emul >= -3 && emul <= 3) &&
> -require_align(vs2, emul) &&
> -require_align(vd, s->lmul) &&
> -require_nf(vd, nf, s->lmul);
> +bool ret = (emul >= -3 && emul <= 3) &&
> +   require_align(vs2, emul) &&
> +   require_align(vd, s->lmul) &&
> +   require_nf(vd, nf, s->lmul);
> +#ifdef TARGET_RISCV32

Don't use hardcoded macros for this, instead use get_xl()

Alistair

> +/*
> + * All Zve* extensions support all vector load and store instructions,
> + * except Zve64* extensions do not support EEW=64 for index values
> + * when XLEN=32. (Section 18.2)
> + */
> +ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true);
> +#endif
> +return ret;
>  }
>
>  /*
> --
> 2.31.1
>
>

Re: [PATCH 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:34 PM  wrote:
>
> From: Frank Chang 
>
> Signed-off-by: Frank Chang 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c| 4 
>  target/riscv/cpu.h| 1 +
>  target/riscv/cpu_helper.c | 5 -
>  target/riscv/csr.c| 6 +-
>  target/riscv/translate.c  | 2 ++
>  5 files changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6ef3314bce..01239620ca 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -562,6 +562,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>  }
>  set_vext_version(env, vext_version);
>  }
> +if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) {
> +error_setg(errp, "Zve64f extension depends upon RVF.");
> +return;
> +}
>  if (cpu->cfg.ext_j) {
>  ext |= RVJ;
>  }
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index dc10f27093..d7b2db2b2f 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -317,6 +317,7 @@ struct RISCVCPU {
>  bool ext_icsr;
>  bool ext_zfh;
>  bool ext_zfhmin;
> +bool ext_zve64f;
>
>  char *priv_spec;
>  char *user_spec;
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 10f3baba53..52d93a41fd 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -69,12 +69,15 @@ static RISCVMXL cpu_get_xl(CPURISCVState *env)
>  void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
>target_ulong *cs_base, uint32_t *pflags)
>  {
> +CPUState *cs = env_cpu(env);
> +RISCVCPU *cpu = RISCV_CPU(cs);
> +
>  uint32_t flags = 0;
>
>  *pc = env->pc;
>  *cs_base = 0;
>
> -if (riscv_has_ext(env, RVV)) {
> +if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) {
>  /*
>   * If env->vl equals to VLMAX, we can use generic vector operation
>   * expanders (GVEC) to accerlate the vector operations.
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 146447eac5..340b9661a8 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -47,7 +47,11 @@ static RISCVException fs(CPURISCVState *env, int csrno)
>
>  static RISCVException vs(CPURISCVState *env, int csrno)
>  {
> -if (env->misa_ext & RVV) {
> +CPUState *cs = env_cpu(env);
> +RISCVCPU *cpu = RISCV_CPU(cs);
> +
> +if (env->misa_ext & RVV ||
> +cpu->cfg.ext_zve64f) {
>  #if !defined(CONFIG_USER_ONLY)
>  if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
>  return RISCV_EXCP_ILLEGAL_INST;
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 5df6c0d800..8c3b0168b7 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -78,6 +78,7 @@ typedef struct DisasContext {
>  bool ext_ifencei;
>  bool ext_zfh;
>  bool ext_zfhmin;
> +bool ext_zve64f;
>  bool hlsx;
>  /* vector extension */
>  bool vill;
> @@ -705,6 +706,7 @@ static void riscv_tr_init_disas_context(DisasContextBase 
> *dcbase, CPUState *cs)
>  ctx->ext_ifencei = cpu->cfg.ext_ifencei;
>  ctx->ext_zfh = cpu->cfg.ext_zfh;
>  ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
> +ctx->ext_zve64f = cpu->cfg.ext_zve64f;
>  ctx->vlen = cpu->cfg.vlen;
>  ctx->elen = cpu->cfg.elen;
>  ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
> --
> 2.31.1
>
>

Re: [PATCH 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:36 PM  wrote:
>
> From: Frank Chang 
>
> All Zve* extensions support the vector configuration instructions.
>
> Signed-off-by: Frank Chang 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 6c285c958b..5b47729a21 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -129,7 +129,8 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, 
> TCGv s2)
>  {
>  TCGv s1, dst;
>
> -if (!require_rvv(s) || !has_ext(s, RVV)) {
> +if (!require_rvv(s) ||
> +!(has_ext(s, RVV) || s->ext_zve64f)) {
>  return false;
>  }
>
> @@ -164,7 +165,8 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, 
> TCGv s2)
>  {
>  TCGv dst;
>
> -if (!require_rvv(s) || !has_ext(s, RVV)) {
> +if (!require_rvv(s) ||
> +!(has_ext(s, RVV) || s->ext_zve64f)) {
>  return false;
>  }
>
> --
> 2.31.1
>
>

Re: [PATCH 1/8] target/ppc: 405: Add missing MSR bits to msr_mask

[Fabiano Rosas]

Fabiano Rosas  writes:

> Some bits described in the user manual are missing from msr_mask. Add
> them.
>
> Signed-off-by: Fabiano Rosas 
> ---
>  target/ppc/cpu_init.c | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index e30e86fe9d..a50ddaeaae 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -2535,15 +2535,19 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
> PPC_MEM_SYNC | PPC_MEM_EIEIO |
> PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
> PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
> -pcc->msr_mask = (1ull << MSR_POW) |
> +pcc->msr_mask = (1ull << MSR_AP) |
> +(1ull << MSR_POW) |
>  (1ull << MSR_CE) |
>  (1ull << MSR_EE) |
>  (1ull << MSR_PR) |
>  (1ull << MSR_FP) |
> +(1ull << MSR_ME) |
>  (1ull << MSR_DWE) |
>  (1ull << MSR_DE) |
> +(1ull << MSR_FE1) |
>  (1ull << MSR_IR) |
>  (1ull << MSR_DR);

This patch brings an unexpected complication:

MSR_AP here is not correct, it is defined as:

#define MSR_AP   23 /* Access privilege state on 602 */

That is bit 8. While MSR_AP in the 405 is bit 6. So I would need to
introduce a new MSR_AP_405 defined as:

#define MSR_AP_405   25 /* Auxiliar processor available on 405 */

But 25 is the same as MSR_SPE, so it triggers this code in
init_ppc_proc:

/* MSR bits & flags consistency checks */
if (env->msr_mask & (1 << 25)) {
switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
case POWERPC_FLAG_SPE:
case POWERPC_FLAG_VRE:
break;
default:
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
"Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
exit(1);
}
 ...

The commit that introduced that sanity check is 25ba3a6812 ("Remove
synonymous in PowerPC MSR bits definitions..."), which sort of assumes
that MSR bits will not have different purposes between any of the (now
47) CPUs, while itself leaving other duplicated bits around.
   
So my idea is to drop this patch and only include the MSR_ME that is of
practical effect at patch 6. I think going into the rabbit hole of
disambiguating MSR bits falls out of the scope of the exception series.

Re: [PATCH 3/3] Link new ppc-spapr-uv-hcalls.rst to pseries.rst.

[Daniel Henrique Barboza]

On 1/17/22 16:19, lagar...@linux.ibm.com wrote:

From: Leonardo Garcia 

Signed-off-by: Leonardo Garcia 
---


It is worth noticing that this patch applies cleanly only if the

"[PATCH 0/3] rSTify ppc-spapr-hotplug.txt" [1]

series is applied first. The reason is that docs/system/ppc/pseries.rst being 
changed
here already has the ppc-spapr-hotplug.rst link.


Reviewed-by: Daniel Henrique Barboza 



[1] https://lists.gnu.org/archive/html/qemu-devel/2022-01/msg02701.html


  docs/system/ppc/pseries.rst | 6 +-
  1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index d0aade3a31..569237dc0c 100644
--- a/docs/system/ppc/pseries.rst
+++ b/docs/system/ppc/pseries.rst
@@ -113,13 +113,9 @@ can  also be found in QEMU documentation:
 ../../specs/ppc-spapr-hotplug.rst
 ../../specs/ppc-spapr-hcalls.rst
 ../../specs/ppc-spapr-numa.rst
+   ../../specs/ppc-spapr-uv-hcalls.rst
 ../../specs/ppc-spapr-xive.rst
  
-Other documentation available in QEMU docs directory:

-
-* Hypervisor calls needed by the Ultravisor
-  (``/docs/specs/ppc-spapr-uv-hcalls.txt``).
-
  Switching between the KVM-PR and KVM-HV kernel module
  =
  

Re: [PATCH 2/3] Rename ppc-spapr-uv-hcalls.txt to ppc-spapr-uv-hcalls.rst.

[Daniel Henrique Barboza]

On 1/17/22 16:19, lagar...@linux.ibm.com wrote:

From: Leonardo Garcia 

Signed-off-by: Leonardo Garcia 
---


Reviewed-by: Daniel Henrique Barboza 


  docs/specs/{ppc-spapr-uv-hcalls.txt => ppc-spapr-uv-hcalls.rst} | 0
  1 file changed, 0 insertions(+), 0 deletions(-)
  rename docs/specs/{ppc-spapr-uv-hcalls.txt => ppc-spapr-uv-hcalls.rst} (100%)

diff --git a/docs/specs/ppc-spapr-uv-hcalls.txt 
b/docs/specs/ppc-spapr-uv-hcalls.rst
similarity index 100%
rename from docs/specs/ppc-spapr-uv-hcalls.txt
rename to docs/specs/ppc-spapr-uv-hcalls.rst

Re: [PATCH 1/3] rSTify ppc-spapr-uv-hcalls.txt.

[Daniel Henrique Barboza]

On 1/17/22 16:19, lagar...@linux.ibm.com wrote:

From: Leonardo Garcia 

Signed-off-by: Leonardo Garcia 
---


Reviewed-by: Daniel Henrique Barboza 


  docs/specs/ppc-spapr-uv-hcalls.txt | 165 -
  1 file changed, 89 insertions(+), 76 deletions(-)

diff --git a/docs/specs/ppc-spapr-uv-hcalls.txt 
b/docs/specs/ppc-spapr-uv-hcalls.txt
index 389c2740d7..a00288deb3 100644
--- a/docs/specs/ppc-spapr-uv-hcalls.txt
+++ b/docs/specs/ppc-spapr-uv-hcalls.txt
@@ -1,76 +1,89 @@
-On PPC64 systems supporting Protected Execution Facility (PEF), system
-memory can be placed in a secured region where only an "ultravisor"
-running in firmware can provide to access it. pseries guests on such
-systems can communicate with the ultravisor (via ultracalls) to switch to a
-secure VM mode (SVM) where the guest's memory is relocated to this secured
-region, making its memory inaccessible to normal processes/guests running on
-the host.
-
-The various ultracalls/hypercalls relating to SVM mode are currently
-only documented internally, but are planned for direct inclusion into the
-public OpenPOWER version of the PAPR specification (LoPAPR/LoPAR). An internal
-ACR has been filed to reserve a hypercall number range specific to this
-use-case to avoid any future conflicts with the internally-maintained PAPR
-specification. This document summarizes some of these details as they relate
-to QEMU.
-
-== hypercalls needed by the ultravisor ==
-
-Switching to SVM mode involves a number of hcalls issued by the ultravisor
-to the hypervisor to orchestrate the movement of guest memory to secure
-memory and various other aspects SVM mode. Numbers are assigned for these
-hcalls within the reserved range 0xEF00-0xEF80. The below documents the
-hcalls relevant to QEMU.
-
-- H_TPM_COMM (0xef10)
-
-  For TPM_COMM_OP_EXECUTE operation:
-Send a request to a TPM and receive a response, opening a new TPM session
-if one has not already been opened.
-
-  For TPM_COMM_OP_CLOSE_SESSION operation:
-Close the existing TPM session, if any.
-
-  Arguments:
-
-r3 : H_TPM_COMM (0xef10)
-r4 : TPM operation, one of:
- TPM_COMM_OP_EXECUTE (0x1)
- TPM_COMM_OP_CLOSE_SESSION (0x2)
-r5 : in_buffer, guest physical address of buffer containing the request
- - Caller may use the same address for both request and response
-r6 : in_size, size of the in buffer
- - Must be less than or equal to 4KB
-r7 : out_buffer, guest physical address of buffer to store the response
- - Caller may use the same address for both request and response
-r8 : out_size, size of the out buffer
- - Must be at least 4KB, as this is the maximum request/response size
-   supported by most TPM implementations, including the TPM Resource
-   Manager in the linux kernel.
-
-  Return values:
-
-r3 : H_Successrequest processed successfully
- H_PARAMETER  invalid TPM operation
- H_P2 in_buffer is invalid
- H_P3 in_size is invalid
- H_P4 out_buffer is invalid
- H_P5 out_size is invalid
- H_RESOURCE   problem communicating with TPM
- H_FUNCTION   TPM access is not currently allowed/configured
-r4 : For TPM_COMM_OP_EXECUTE, the size of the response will be stored here
- upon success.
-
-  Use-case/notes:
-
-SVM filesystems are encrypted using a symmetric key. This key is then
-wrapped/encrypted using the public key of a trusted system which has the
-private key stored in the system's TPM. An Ultravisor will use this
-hcall to unwrap/unseal the symmetric key using the system's TPM device
-or a TPM Resource Manager associated with the device.
-
-The Ultravisor sets up a separate session key with the TPM in advance
-during host system boot. All sensitive in and out values will be
-encrypted using the session key. Though the hypervisor will see the 'in'
-and 'out' buffers in raw form, any sensitive contents will generally be
-encrypted using this session key.
+===
+Hypervisor calls and the Ultravisor
+===
+
+On PPC64 systems supporting Protected Execution Facility (PEF), system memory
+can be placed in a secured region where only an ultravisor running in firmware
+can provide access to. pSeries guests on such systems can communicate with
+the ultravisor (via ultracalls) to switch to a secure virtual machine (SVM) 
mode
+where the guest's memory is relocated to this secured region, making its memory
+inaccessible to normal processes/guests running on the host.
+
+The various ultracalls/hypercalls relating to SVM mode are currently only
+documented internally, but are planned for direct inclusion into the Linux on
+Power Architecture Reference document ([LoPAR]_). An internal ACR has been 
filed
+to reserve a hypercall number range specific to this use case to avoid any

Re: iotest 040, 041, intermittent failure in netbsd VM

[Peter Maydell]

On Mon, 17 Jan 2022 at 20:35, John Snow  wrote:

> Can you please try applying this temporary patch and running `./check
> -qcow2 040 041` until you see a breakage and show me the output from
> that?

With this temporary patch the VM doesn't launch at all:

peter.mayd...@hackbox2.linaro.org:~/qemu-netbsd$ make -C build/
vm-build-netbsd J=8 V=1 2>&1 | tee netbsd.log
make: Entering directory '/home/peter.maydell/qemu-netbsd/build'
/usr/bin/python3 -B /home/peter.maydell/qemu-netbsd/meson/meson.py
introspect --targets --tests --benchmarks | /usr/bin/python3 -B
scripts/mtest2m
ake.py > Makefile.mtest
{ \
  echo 'ninja-targets = \'; \
  /usr/bin/ninja -t targets all | sed 's/:.*//; $!s/$/ \\/'; \
  echo 'build-files = \'; \
  /usr/bin/ninja -t query build.ninja | sed -n '1,/^  input:/d; /^
outputs:/q; s/$/ \\/p'; \
} > Makefile.ninja.tmp && mv Makefile.ninja.tmp Makefile.ninja
(GIT="git" "/home/peter.maydell/qemu-netbsd/scripts/git-submodule.sh"
update ui/keycodemapdb meson tests/fp/berkeley-testfloat-3
tests/fp/berkeley-softfloat-3 dtc capstone slirp)
(GIT="git" "/home/peter.maydell/qemu-netbsd/scripts/git-submodule.sh"
update ui/keycodemapdb meson tests/fp/berkeley-testfloat-3
tests/fp/berkeley-softfloat-3 dtc capstone slirp)
/usr/bin/python3 -B /home/peter.maydell/qemu-netbsd/tests/vm/netbsd
--debug  --jobs 8 --verbose--image
"/home/peter.maydell/.cache/qemu-vm/images/netbsd.img"  --snapshot
--build-qemu /home/peter.maydell/qemu-netbsd --
DEBUG:root:Creating archive
/home/peter.maydell/qemu-netbsd/build/vm-test-72ra6_8s.tmp/data-f706c.tar
for src_dir dir: /home/peter.maydell/qemu-netbsd
DEBUG:root:QEMU args: -nodefaults -m 4G -cpu max -netdev
user,id=vnet,hostfwd=:127.0.0.1:0-:22,ipv6=no -device
virtio-net-pci,netdev=vnet -vnc 127.0.0.1:0,to=20 -smp 8 -enable-kvm
-drive 
file=/home/peter.maydell/.cache/qemu-vm/images/netbsd.img,snapshot=on,if=none,id=drive0,cache=writeback
-device virtio-blk,drive=drive0,bootindex=0 -drive
file=/home/peter.maydell/qemu-netbsd/build/vm-test-72ra6_8s.tmp/data-f706c.tar,if=none,id=data-f706c,cache=writeback,format=raw
-device virtio-blk,drive=data-f706c,serial=data-f706c,bootindex=1
DEBUG:asyncio:Using selector: EpollSelector
DEBUG:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:Registering
.
DEBUG:qemu.machine.machine:VM launch command: 'qemu-system-x86_64
-display none -vga none -chardev
socket,id=mon,path=/var/tmp/qemu-machine-0m15ou19/qemu-2335-7f3b78d7f128-monitor.sock
-mon chardev=mon,mode=control -machine pc -chardev
socket,id=console,path=/var/tmp/qemu-machine-0m15ou19/qemu-2335-7f3b78d7f128-console.sock,server=on,wait=off
-serial chardev:console -nodefaults -m 4G -cpu max -netdev
user,id=vnet,hostfwd=:127.0.0.1:0-:22,ipv6=no -device
virtio-net-pci,netdev=vnet -vnc 127.0.0.1:0,to=20 -smp 8 -enable-kvm
-drive 
file=/home/peter.maydell/.cache/qemu-vm/images/netbsd.img,snapshot=on,if=none,id=drive0,cache=writeback
-device virtio-blk,drive=drive0,bootindex=0 -drive
file=/home/peter.maydell/qemu-netbsd/build/vm-test-72ra6_8s.tmp/data-f706c.tar,if=none,id=data-f706c,cache=writeback,format=raw
-device virtio-blk,drive=data-f706c,serial=data-f706c,bootindex=1'
DEBUG:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:Transitioning from
'Runstate.IDLE' to 'Runstate.CONNECTING'.
DEBUG:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:Awaiting connection
on /var/tmp/qemu-machine-0m15ou19/qemu-2335-7f3b78d7f128-monitor.sock
...
DEBUG:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:Connection accepted.
DEBUG:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:Awaiting greeting ...
DEBUG:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:<-- {
  "QMP": {
"version": {
  "qemu": {
"micro": 1,
"minor": 11,
"major": 2
  },
  "package": "(Debian 1:2.11+dfsg-1ubuntu7.38)"
},
"capabilities": []
  }
}
DEBUG:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:Negotiating capabilities ...
DEBUG:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:--> {
  "execute": "qmp_capabilities",
  "arguments": {
"enable": []
  }
}
DEBUG:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:<-- {
  "error": {
"class": "GenericError",
"desc": "Parameter 'enable' is unexpected"
  }
}
ERROR:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:Negotiation failed:
AssertionError
DEBUG:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:Negotiation failed:
  | Traceback (most recent call last):
  |   File 
"/home/peter.maydell/qemu-netbsd/tests/vm/../../python/qemu/aqmp/qmp_client.py",
line 306, in _negotiate
  | assert 'return' in reply
  | AssertionError

ERROR:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:Failed to establish
session: qemu.aqmp.qmp_client.NegotiationError: Negotiation failed:
DEBUG:qemu.aqmp.qmp_client.qemu-2335-7f3b78d7f128:Failed to establish session:
  | Traceback (most recent call last):
  |   File 
"/home/peter.maydell/qemu-netbsd/tests/vm/../../python/qemu/aqmp/qmp_client.py",
line 306, in _negotiate
  | assert 'return' in reply
  | AssertionError
  |
  | The above exception was the direct cause 

Re: iotest 040, 041, intermittent failure in netbsd VM

[Peter Maydell]

On Mon, 17 Jan 2022 at 20:35, John Snow  wrote:
>
> On Mon, Jan 17, 2022 at 5:05 AM Kevin Wolf  wrote:
> >
> > Am 10.01.2022 um 16:55 hat Peter Maydell geschrieben:
> > > Just saw this failure of iotests in a netbsd VM

> This trace says that we timed out while awaiting a connection from
> QEMU during the VM launch phase. i.e. python/qemu/qmp/machine.py line
> 340:
>
> def _post_launch(self) -> None:
> if self._qmp_connection:
> self._qmp.accept(self._qmp_timer)  <-- we timed out here.
>
> (Note to self: make this traceback look more obvious as to what was
> canceled and why. I think I can improve readability here a bit ...)
>
> Sky's the limit on why QEMU never connected to the socket, but:
>
> > > --- /home/qemu/qemu-test.MPWquy/src/tests/qemu-iotests/040.out
> > > fcntl(): Invalid argument
>
> That looks fairly suspicious, and I don't know which process was
> responsible for printing it (or when, relative to the other outputs).
> I assume you don't see any such output like this on a good run.

The NetBSD VM prints those fcntl messages all over the place.
I think something in the build system (make? ninja? who knows)
triggers them.

> > > -OK
> > > +FAILED (errors=1)
> > >   TEST   iotest-qcow2: 041 [fail]
> > > QEMU  --
> > > "/home/qemu/qemu-test.MPWquy/build/tests/qemu-iotests/../../qemu-system-aarch64"
> > > -nodefaults -display none -accel qtest -machine virt
> > > QEMU_IMG  --
> > > "/home/qemu/qemu-test.MPWquy/build/tests/qemu-iotests/../../qemu-img"
> > > QEMU_IO   --
> > > "/home/qemu/qemu-test.MPWquy/build/tests/qemu-iotests/../../qemu-io"
> > > --cache writeback --aio threads -f qcow2
> > > QEMU_NBD  --
> > > "/home/qemu/qemu-test.MPWquy/build/tests/qemu-iotests/../../qemu-nbd"
> > > IMGFMT-- qcow2
> > > IMGPROTO  -- file
> > > PLATFORM  -- NetBSD/amd64 localhost 9.2
> > > TEST_DIR  -- 
> > > /home/qemu/qemu-test.MPWquy/build/tests/qemu-iotests/scratch
> > > SOCK_DIR  -- /tmp/tmpuniuicbi
> > > GDB_OPTIONS   --
> > > VALGRIND_QEMU --
> > > PRINT_QEMU_OUTPUT --
> > >
> > > --- /home/qemu/qemu-test.MPWquy/src/tests/qemu-iotests/041.out
> > > +++ 041.out.bad
> > > @@ -1,5 +1,32 @@
> > > -...
> > > +..ERROR:qemu.aqmp.qmp_client.qemu-15252:Failed
> > > to establish connection: concurrent.futures._base.CancelledError
> > > +E
> > > +==
> > > +ERROR: test_small_buffer (__main__.TestSingleBlockdev)
> > > +--
> > > +Traceback (most recent call last):
> > > +  File "/home/qemu/qemu-test.MPWquy/src/tests/qemu-iotests/041", line
> > > 233, in setUp
> > > +TestSingleDrive.setUp(self)
> > > +  File "/home/qemu/qemu-test.MPWquy/src/tests/qemu-iotests/041", line
> > > 54, in setUp
> > > +self.vm.launch()
> > > +  File "/home/qemu/qemu-test.MPWquy/src/python/qemu/machine/machine.py",
> > > line 399, in launch
> > > +self._launch()
> > > +  File "/home/qemu/qemu-test.MPWquy/src/python/qemu/machine/machine.py",
> > > line 434, in _launch
> > > +self._post_launch()
> > > +  File "/home/qemu/qemu-test.MPWquy/src/python/qemu/machine/qtest.py",
> > > line 147, in _post_launch
> > > +super()._post_launch()
> > > +  File "/home/qemu/qemu-test.MPWquy/src/python/qemu/machine/machine.py",
> > > line 340, in _post_launch
> > > +self._qmp.accept(self._qmp_timer)
> > > +  File "/home/qemu/qemu-test.MPWquy/src/python/qemu/aqmp/legacy.py",
> > > line 69, in accept
> > > +timeout
> > > +  File "/home/qemu/qemu-test.MPWquy/src/python/qemu/aqmp/legacy.py",
> > > line 42, in _sync
> > > +asyncio.wait_for(future, timeout=timeout)
> > > +  File "/usr/pkg/lib/python3.7/asyncio/base_events.py", line 587, in
> > > run_until_complete
> > > +return future.result()
> > > +  File "/usr/pkg/lib/python3.7/asyncio/tasks.py", line 449, in wait_for
> > > +raise futures.TimeoutError()
> > > +concurrent.futures._base.TimeoutError
>
> Same problem here, except I don't see any output from QEMU to blame.
> As far as the Python code knows, it just never got a connection on the
> socket, so it timed out and died.

I think the NetBSD VM does for some reason get a bit slow to do
stuff. I've never worked out why. In the past we've had to bump
up various overoptimistic timeouts to help it out.

> I do expect this to print more information on failure than it
> currently is, though (bug somewhere in machine.py, I think).
> Can you please try applying this temporary patch and running `./check
> -qcow2 040 041` until you see a breakage and show me the output from
> that?
>
> diff --git a/python/qemu/machine/machine.py b/python/qemu/machine/machine.py
> index 67ab06ca2b..ca49e6fcd2 100644
> --- 

Re: [PATCH RESEND] tests/avocado: ppc: Add smoke tests for MPC7400 and MPC7450 families

[Philippe Mathieu-Daudé via]

On 17/1/22 21:08, Daniel Henrique Barboza wrote:

On 1/17/22 11:47, Fabiano Rosas wrote:

These tests ensure that our emulation for these cpus is not completely
broken and we can at least run OpenBIOS on them.

$ make check-avocado AVOCADO_TESTS=../tests/avocado/ppc_74xx.py

Signed-off-by: Fabiano Rosas 
Reviewed-by: Willian Rampazzo 
---
---
  tests/avocado/ppc_74xx.py | 123 ++
  1 file changed, 123 insertions(+)
  create mode 100644 tests/avocado/ppc_74xx.py

diff --git a/tests/avocado/ppc_74xx.py b/tests/avocado/ppc_74xx.py
new file mode 100644
index 00..556a9a7da9
--- /dev/null
+++ b/tests/avocado/ppc_74xx.py
@@ -0,0 +1,123 @@
+# Smoke tests for 74xx cpus (aka G4).
+#
+# Copyright (c) 2021, IBM Corp.



Not sure if the copyright year must be changed to 2022 (the year that 
this is going to
be published) or 2021 (the year that it was developed). GNU docs isn't 
clear about
it. Our COPYING file is also not clear about whether we should put the 
code creation

or code publishing year in this header.

I don't mind leaving it as 2021. I'm just curious about what is the 
semantics involved

here.


I think I read once "the date it was first published on the list", but
I am not sure and certainly IANAL ;)

Re: ppc pbr403 vmstate

[Peter Maydell]

On Mon, 17 Jan 2022 at 05:52, David Gibson  wrote:
> It is also touched in the *super* old cpu_load_old.  I suspect we
> could probably just drop that completely, since I don't think we
> realistically support migration from a version that old anyway.

This would be a nice thing to do, because the PPC CPU is the
only remaining in-tree user of the .load_state_old migration
hook, so if we declared that we don't support migrating from
those old versions of QEMU (1.5 and earlier, I think) then we
could delete the .load_state_old and .minimum_version_id_old
handling completely.

-- PMM

[PATCH v3 2/3] scripts/qapi-gen.py: add --add-trace-events option

[Vladimir Sementsov-Ogievskiy]

Add and option to generate trace events. We should generate both trace
events and trace-events files for further trace events code generation.

Signed-off-by: Vladimir Sementsov-Ogievskiy 
---
 scripts/qapi/commands.py | 91 ++--
 scripts/qapi/main.py | 10 +++--
 2 files changed, 85 insertions(+), 16 deletions(-)

diff --git a/scripts/qapi/commands.py b/scripts/qapi/commands.py
index 21001bbd6b..8cd1aa41ce 100644
--- a/scripts/qapi/commands.py
+++ b/scripts/qapi/commands.py
@@ -53,7 +53,8 @@ def gen_command_decl(name: str,
 def gen_call(name: str,
  arg_type: Optional[QAPISchemaObjectType],
  boxed: bool,
- ret_type: Optional[QAPISchemaType]) -> str:
+ ret_type: Optional[QAPISchemaType],
+ add_trace_events: bool) -> str:
 ret = ''
 
 argstr = ''
@@ -71,21 +72,65 @@ def gen_call(name: str,
 if ret_type:
 lhs = 'retval = '
 
-ret = mcgen('''
+name = c_name(name)
+upper = name.upper()
 
-%(lhs)sqmp_%(c_name)s(%(args)s);
-error_propagate(errp, err);
-''',
-c_name=c_name(name), args=argstr, lhs=lhs)
-if ret_type:
+if add_trace_events:
 ret += mcgen('''
+
+if (trace_event_get_state_backends(TRACE_QMP_ENTER_%(upper)s)) {
+g_autoptr(GString) req_json = qobject_to_json(QOBJECT(args));
+trace_qmp_enter_%(name)s(req_json->str);
+}
+''',
+ upper=upper, name=name)
+
+ret += mcgen('''
+
+%(lhs)sqmp_%(name)s(%(args)s);
+''',
+name=name, args=argstr, lhs=lhs)
+
+ret += mcgen('''
 if (err) {
+''')
+
+if add_trace_events:
+ret += mcgen('''
+trace_qmp_exit_%(name)s(error_get_pretty(err), false);
+''',
+ name=name)
+
+ret += mcgen('''
+error_propagate(errp, err);
 goto out;
 }
+''')
+
+if ret_type:
+ret += mcgen('''
 
 qmp_marshal_output_%(c_name)s(retval, ret, errp);
 ''',
  c_name=ret_type.c_name())
+
+if add_trace_events:
+if ret_type:
+ret += mcgen('''
+
+if (trace_event_get_state_backends(TRACE_QMP_EXIT_%(upper)s)) {
+g_autoptr(GString) ret_json = qobject_to_json(*ret);
+trace_qmp_exit_%(name)s(ret_json->str, true);
+}
+''',
+ upper=upper, name=name)
+else:
+ret += mcgen('''
+
+trace_qmp_exit_%(name)s("{}", true);
+''',
+ name=name)
+
 return ret
 
 
@@ -122,10 +167,17 @@ def gen_marshal_decl(name: str) -> str:
  proto=build_marshal_proto(name))
 
 
+def gen_trace(name: str) -> str:
+name = c_name(name)
+return f"""\
+qmp_enter_{name}(const char *json) "%s"\n
+qmp_exit_{name}(const char *result, bool succeeded) "%s %d"\n"""
+
 def gen_marshal(name: str,
 arg_type: Optional[QAPISchemaObjectType],
 boxed: bool,
-ret_type: Optional[QAPISchemaType]) -> str:
+ret_type: Optional[QAPISchemaType],
+add_trace_events: bool) -> str:
 have_args = boxed or (arg_type and not arg_type.is_empty())
 if have_args:
 assert arg_type is not None
@@ -180,7 +232,7 @@ def gen_marshal(name: str,
 }
 ''')
 
-ret += gen_call(name, arg_type, boxed, ret_type)
+ret += gen_call(name, arg_type, boxed, ret_type, add_trace_events)
 
 ret += mcgen('''
 
@@ -238,11 +290,12 @@ def gen_register_command(name: str,
 
 
 class QAPISchemaGenCommandVisitor(QAPISchemaModularCVisitor):
-def __init__(self, prefix: str):
+def __init__(self, prefix: str, add_trace_events: bool):
 super().__init__(
 prefix, 'qapi-commands',
 ' * Schema-defined QAPI/QMP commands', None, __doc__)
 self._visited_ret_types: Dict[QAPIGenC, Set[QAPISchemaType]] = {}
+self.add_trace_events = add_trace_events
 
 def _begin_user_module(self, name: str) -> None:
 self._visited_ret_types[self._genc] = set()
@@ -261,6 +314,15 @@ def _begin_user_module(self, name: str) -> None:
 
 ''',
  commands=commands, visit=visit))
+
+if self.add_trace_events and c_name(commands) != 'qapi_commands':
+self._genc.add(mcgen('''
+#include "trace/trace-qapi.h"
+#include "qapi/qmp/qjson.h"
+#include "trace/trace-%(nm)s_trace_events.h"
+''',
+ nm=c_name(commands)))
+
 self._genh.add(mcgen('''
 #include "%(types)s.h"
 
@@ -322,7 +384,9 @@ def visit_command(self,
 with ifcontext(ifcond, self._genh, self._genc):
 self._genh.add(gen_command_decl(name, arg_type, boxed, ret_type))
 self._genh.add(gen_marshal_decl(name))
-self._genc.add(gen_marshal(name, arg_type, boxed, ret_type))
+self._genc.add(gen_marshal(name, arg_type, boxed, ret_type,
+   self.add_trace_events))
+   

Re: iotest 040, 041, intermittent failure in netbsd VM

[John Snow]

On Mon, Jan 17, 2022 at 5:05 AM Kevin Wolf  wrote:
>
> Am 10.01.2022 um 16:55 hat Peter Maydell geschrieben:
> > Just saw this failure of iotests in a netbsd VM (the in-tree
> > tests/vm stuff). Pretty sure it's an intermittent as the
> > pulreq being tested has nothing io or block related.
> >
> >
> >   TEST   iotest-qcow2: 036
> >   TEST   iotest-qcow2: 037
> >   TEST   iotest-qcow2: 038 [not run]
> >   TEST   iotest-qcow2: 039 [not run]
> >   TEST   iotest-qcow2: 040 [fail]
> > QEMU  --
> > "/home/qemu/qemu-test.MPWquy/build/tests/qemu-iotests/../../qemu-system-aarch64"
> > -nodefaults -display none -accel qtest -machine
> > virt
> > QEMU_IMG  --
> > "/home/qemu/qemu-test.MPWquy/build/tests/qemu-iotests/../../qemu-img"
> > QEMU_IO   --
> > "/home/qemu/qemu-test.MPWquy/build/tests/qemu-iotests/../../qemu-io"
> > --cache writeback --aio threads -f qcow2
> > QEMU_NBD  --
> > "/home/qemu/qemu-test.MPWquy/build/tests/qemu-iotests/../../qemu-nbd"
> > IMGFMT-- qcow2
> > IMGPROTO  -- file
> > PLATFORM  -- NetBSD/amd64 localhost 9.2
> > TEST_DIR  -- 
> > /home/qemu/qemu-test.MPWquy/build/tests/qemu-iotests/scratch
> > SOCK_DIR  -- /tmp/tmpuniuicbi
> > GDB_OPTIONS   --
> > VALGRIND_QEMU --
> > PRINT_QEMU_OUTPUT --
> >
> > --- /home/qemu/qemu-test.MPWquy/src/tests/qemu-iotests/040.out
> > fcntl(): Invalid argument
> > +++ 040.out.bad
> > @@ -1,5 +1,30 @@
> > -.
> > +ERROR:qemu.aqmp.qmp_client.qemu-7648:Failed
> > to establish connection: concurrent.futures._base.CancelledError
> > +E
> > +==
> > +ERROR: test_top_is_default_active (__main__.TestSingleDrive)
> > +--
> > +Traceback (most recent call last):
> > +  File "/home/qemu/qemu-test.MPWquy/src/tests/qemu-iotests/040", line
> > 94, in setUp
> > +self.vm.launch()
> > +  File "/home/qemu/qemu-test.MPWquy/src/python/qemu/machine/machine.py",
> > line 399, in launch
> > +self._launch()
> > +  File "/home/qemu/qemu-test.MPWquy/src/python/qemu/machine/machine.py",
> > line 434, in _launch
> > +self._post_launch()
> > +  File "/home/qemu/qemu-test.MPWquy/src/python/qemu/machine/qtest.py",
> > line 147, in _post_launch
> > +super()._post_launch()
> > +  File "/home/qemu/qemu-test.MPWquy/src/python/qemu/machine/machine.py",
> > line 340, in _post_launch
> > +self._qmp.accept(self._qmp_timer)
> > +  File "/home/qemu/qemu-test.MPWquy/src/python/qemu/aqmp/legacy.py",
> > line 69, in accept
> > +timeout
> > +  File "/home/qemu/qemu-test.MPWquy/src/python/qemu/aqmp/legacy.py",
> > line 42, in _sync
> > +asyncio.wait_for(future, timeout=timeout)
> > +  File "/usr/pkg/lib/python3.7/asyncio/base_events.py", line 587, in
> > run_until_complete
> > +return future.result()
> > +  File "/usr/pkg/lib/python3.7/asyncio/tasks.py", line 449, in wait_for
> > +raise futures.TimeoutError()
> > +concurrent.futures._base.TimeoutError
> > +
> >  --
> >  Ran 65 tests
> >

This trace says that we timed out while awaiting a connection from
QEMU during the VM launch phase. i.e. python/qemu/qmp/machine.py line
340:

def _post_launch(self) -> None:
if self._qmp_connection:
self._qmp.accept(self._qmp_timer)  <-- we timed out here.

(Note to self: make this traceback look more obvious as to what was
canceled and why. I think I can improve readability here a bit ...)

Sky's the limit on why QEMU never connected to the socket, but:

> > --- /home/qemu/qemu-test.MPWquy/src/tests/qemu-iotests/040.out
> > fcntl(): Invalid argument

That looks fairly suspicious, and I don't know which process was
responsible for printing it (or when, relative to the other outputs).
I assume you don't see any such output like this on a good run.

> > -OK
> > +FAILED (errors=1)
> >   TEST   iotest-qcow2: 041 [fail]
> > QEMU  --
> > "/home/qemu/qemu-test.MPWquy/build/tests/qemu-iotests/../../qemu-system-aarch64"
> > -nodefaults -display none -accel qtest -machine virt
> > QEMU_IMG  --
> > "/home/qemu/qemu-test.MPWquy/build/tests/qemu-iotests/../../qemu-img"
> > QEMU_IO   --
> > "/home/qemu/qemu-test.MPWquy/build/tests/qemu-iotests/../../qemu-io"
> > --cache writeback --aio threads -f qcow2
> > QEMU_NBD  --
> > "/home/qemu/qemu-test.MPWquy/build/tests/qemu-iotests/../../qemu-nbd"
> > IMGFMT-- qcow2
> > IMGPROTO  -- file
> > PLATFORM  -- NetBSD/amd64 localhost 9.2
> > TEST_DIR  -- 
> > /home/qemu/qemu-test.MPWquy/build/tests/qemu-iotests/scratch
> > SOCK_DIR  -- /tmp/tmpuniuicbi
> > GDB_OPTIONS   --
> > VALGRIND_QEMU --
> > PRINT_QEMU_OUTPUT --
> >
> > --- /home/qemu/qemu-test.MPWquy/src/tests/qemu-iotests/041.out
> > +++ 041.out.bad
> > @@ -1,5 +1,32 @@

[PATCH v3 3/3] meson: generate trace events for qmp commands

[Vladimir Sementsov-Ogievskiy]

1. Use --add-trace-events when generate qmp commands
2. Add corresponding .trace-events files as outputs in qapi_files
   custom target
3. Define global qapi_trace_events list of .trace-events file targets,
   to fill in trace/qapi.build and to use in trace/meson.build
4. In trace/meson.build use the new array as an additional source of
   .trace_events files to be processed

Signed-off-by: Vladimir Sementsov-Ogievskiy 
---
 meson.build   |  5 +
 qapi/meson.build  |  9 -
 trace/meson.build | 11 ---
 3 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/meson.build b/meson.build
index 762d7cee85..effd66e4c2 100644
--- a/meson.build
+++ b/meson.build
@@ -41,6 +41,7 @@ qemu_icondir = get_option('datadir') / 'icons'
 
 config_host_data = configuration_data()
 genh = []
+qapi_trace_events = []
 
 target_dirs = config_host['TARGET_DIRS'].split()
 have_linux_user = false
@@ -2554,6 +2555,10 @@ if 'CONFIG_VHOST_USER' in config_host
   vhost_user = libvhost_user.get_variable('vhost_user_dep')
 endif
 
+# Please keep ordering between 'qapi' and 'trace' subdirs:
+# We should first handle 'qapi' subdir, so that all
+# generated trace events be generated prior handling 'trace'
+# subdir.
 subdir('qapi')
 subdir('qobject')
 subdir('stubs')
diff --git a/qapi/meson.build b/qapi/meson.build
index c0c49c15e4..b48125f8da 100644
--- a/qapi/meson.build
+++ b/qapi/meson.build
@@ -114,6 +114,7 @@ foreach module : qapi_all_modules
   'qapi-events-@0@.h'.format(module),
   'qapi-commands-@0@.c'.format(module),
   'qapi-commands-@0@.h'.format(module),
+  'qapi-commands-@0@.trace-events'.format(module),
 ]
   endif
   if module.endswith('-target')
@@ -126,7 +127,7 @@ endforeach
 qapi_files = custom_target('shared QAPI source files',
   output: qapi_util_outputs + qapi_specific_outputs + qapi_nonmodule_outputs,
   input: [ files('qapi-schema.json') ],
-  command: [ qapi_gen, '-o', 'qapi', '-b', '@INPUT0@' ],
+  command: [ qapi_gen, '-o', 'qapi', '-b', '@INPUT0@', '--add-trace-events' ],
   depend_files: [ qapi_inputs, qapi_gen_depends ])
 
 # Now go through all the outputs and add them to the right sourceset.
@@ -137,6 +138,9 @@ foreach output : qapi_util_outputs
   if output.endswith('.h')
 genh += qapi_files[i]
   endif
+  if output.endswith('.trace-events')
+qapi_trace_events += qapi_files[i]
+  endif
   util_ss.add(qapi_files[i])
   i = i + 1
 endforeach
@@ -145,6 +149,9 @@ foreach output : qapi_specific_outputs + 
qapi_nonmodule_outputs
   if output.endswith('.h')
 genh += qapi_files[i]
   endif
+  if output.endswith('.trace-events')
+qapi_trace_events += qapi_files[i]
+  endif
   specific_ss.add(when: 'CONFIG_SOFTMMU', if_true: qapi_files[i])
   i = i + 1
 endforeach
diff --git a/trace/meson.build b/trace/meson.build
index 573dd699c6..c4794a1f2a 100644
--- a/trace/meson.build
+++ b/trace/meson.build
@@ -2,10 +2,15 @@
 specific_ss.add(files('control-target.c'))
 
 trace_events_files = []
-foreach dir : [ '.' ] + trace_events_subdirs
-  trace_events_file = meson.project_source_root() / dir / 'trace-events'
+foreach item : [ '.' ] + trace_events_subdirs + qapi_trace_events
+  if item in qapi_trace_events
+trace_events_file = item
+group_name = item.full_path().split('/')[-1].underscorify()
+  else
+trace_events_file = meson.project_source_root() / item / 'trace-events'
+group_name = item == '.' ? 'root' : item.underscorify()
+  endif
   trace_events_files += [ trace_events_file ]
-  group_name = dir == '.' ? 'root' : dir.underscorify()
   group = '--group=' + group_name
   fmt = '@0@-' + group_name + '.@1@'
 
-- 
2.31.1

[PATCH v3 1/3] scripts/qapi/gen.py: add .trace-events file for module

[Vladimir Sementsov-Ogievskiy]

We are going to generate trace events for qmp commands. We should
generate both trace events and trace-events.

For now, add .trace-events file object, to be filled in further commit.

Signed-off-by: Vladimir Sementsov-Ogievskiy 
---
 scripts/qapi/gen.py | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/scripts/qapi/gen.py b/scripts/qapi/gen.py
index 995a97d2b8..605b3fe68a 100644
--- a/scripts/qapi/gen.py
+++ b/scripts/qapi/gen.py
@@ -251,7 +251,7 @@ def __init__(self,
 self._builtin_blurb = builtin_blurb
 self._pydoc = pydoc
 self._current_module: Optional[str] = None
-self._module: Dict[str, Tuple[QAPIGenC, QAPIGenH]] = {}
+self._module: Dict[str, Tuple[QAPIGenC, QAPIGenH, QAPIGen]] = {}
 self._main_module: Optional[str] = None
 
 @property
@@ -264,6 +264,11 @@ def _genh(self) -> QAPIGenH:
 assert self._current_module is not None
 return self._module[self._current_module][1]
 
+@property
+def _gent(self) -> QAPIGen:
+assert self._current_module is not None
+return self._module[self._current_module][2]
+
 @staticmethod
 def _module_dirname(name: str) -> str:
 if QAPISchemaModule.is_user_module(name):
@@ -293,7 +298,8 @@ def _add_module(self, name: str, blurb: str) -> None:
 basename = self._module_filename(self._what, name)
 genc = QAPIGenC(basename + '.c', blurb, self._pydoc)
 genh = QAPIGenH(basename + '.h', blurb, self._pydoc)
-self._module[name] = (genc, genh)
+gent = QAPIGen(basename + '.trace-events')
+self._module[name] = (genc, genh, gent)
 self._current_module = name
 
 @contextmanager
@@ -304,11 +310,12 @@ def _temp_module(self, name: str) -> Iterator[None]:
 self._current_module = old_module
 
 def write(self, output_dir: str, opt_builtins: bool = False) -> None:
-for name, (genc, genh) in self._module.items():
+for name, (genc, genh, gent) in self._module.items():
 if QAPISchemaModule.is_builtin_module(name) and not opt_builtins:
 continue
 genc.write(output_dir)
 genh.write(output_dir)
+gent.write(output_dir)
 
 def _begin_builtin_module(self) -> None:
 pass
-- 
2.31.1

[PATCH v3 0/3] trace qmp commands

[Vladimir Sementsov-Ogievskiy]

Hi all!

This series aims to add trace points for each qmp command with help of
qapi code generator.

v3:
 - don't drop old trace events
 - make pair of qmp_enter_ and qmp_exit_ trace events
 - improve patch splitting
 - use term "trace events" constantly instead of "trace points"
 - add comment on subdir ordering to last commit

Vladimir Sementsov-Ogievskiy (3):
  scripts/qapi/gen.py: add .trace-events file for module
  scripts/qapi-gen.py: add --add-trace-events option
  meson: generate trace events for qmp commands

 meson.build  |  5 +++
 qapi/meson.build |  9 +++-
 scripts/qapi/commands.py | 91 ++--
 scripts/qapi/gen.py  | 13 --
 scripts/qapi/main.py | 10 +++--
 trace/meson.build| 11 +++--
 6 files changed, 116 insertions(+), 23 deletions(-)

-- 
2.31.1