Re: [PATCH v4 1/6] hw/cxl: rename mailbox return code type from ret_code to CXLRetCode
On 3/3/23 16:09, Jonathan Cameron wrote: Given the increasing usage of this mailbox return code type, now is a good time to switch to QEMU style naming. Reviewed-by: Ira Weiny Reviewed-by: Fan Ni Signed-off-by: Jonathan Cameron --- v8: Picked up tag from Fan Ni --- hw/cxl/cxl-mailbox-utils.c | 64 +++--- 1 file changed, 32 insertions(+), 32 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 4/4] target/riscv: Simplify arguments for riscv_csrrw_check
On 9/3/23 08:13, Weiwei Li wrote: Remove RISCVCPU argument, and get cfg infomation from CPURISCVState directly. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/csr.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 2/4] target/riscv: Simplify getting RISCVCPU pointer from env
On 9/3/23 08:13, Weiwei Li wrote: Use env_archcpu() to get RISCVCPU pointer from env directly. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/pmu.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 4/4] target/riscv: Simplify arguments for riscv_csrrw_check
On Thu, Mar 9, 2023 at 5:14 PM Weiwei Li wrote:
>
> Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
> directly.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/csr.c | 12
> 1 file changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 53143f4d9a..80fc15e4d6 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3755,15 +3755,14 @@ static RISCVException rmw_seed(CPURISCVState *env,
> int csrno,
>
> static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
> int csrno,
> - bool write_mask,
> - RISCVCPU *cpu)
> + bool write_mask)
> {
> /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
> bool read_only = get_field(csrno, 0xC00) == 3;
> int csr_min_priv = csr_ops[csrno].min_priv_ver;
>
> /* ensure the CSR extension is enabled */
> -if (!cpu->cfg.ext_icsr) {
> +if (!riscv_cpu_cfg(env)->ext_icsr) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> @@ -3859,9 +3858,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int
> csrno,
> target_ulong *ret_value,
> target_ulong new_value, target_ulong write_mask)
> {
> -RISCVCPU *cpu = env_archcpu(env);
> -
> -RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
> +RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
> if (ret != RISCV_EXCP_NONE) {
> return ret;
> }
> @@ -3914,9 +3911,8 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int
> csrno,
> Int128 new_value, Int128 write_mask)
> {
> RISCVException ret;
> -RISCVCPU *cpu = env_archcpu(env);
>
> -ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
> +ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
> if (ret != RISCV_EXCP_NONE) {
> return ret;
> }
> --
> 2.25.1
>
>
Re: [PATCH 3/4] target/riscv: Simplify type conversion for CPURISCVState
On Thu, Mar 9, 2023 at 5:14 PM Weiwei Li wrote:
>
> Use CPURISCVState as argument directly in riscv_cpu_update_mip and
> riscv_timer_write_timecmp, since type converts from CPURISCVState to
> RISCVCPU in many caller of them and then back to CPURISCVState in them.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 6 +++---
> target/riscv/cpu.h | 3 ++-
> target/riscv/cpu_helper.c | 8
> target/riscv/csr.c | 35 +++
> target/riscv/pmu.c | 6 +++---
> target/riscv/time_helper.c | 15 +++
> target/riscv/time_helper.h | 2 +-
> 7 files changed, 31 insertions(+), 44 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1e97473af2..16e465a0ab 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1302,7 +1302,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq,
> int level)
> if (kvm_enabled()) {
> kvm_riscv_set_irq(cpu, irq, level);
> } else {
> -riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
> +riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level));
> }
> break;
> case IRQ_S_EXT:
> @@ -1310,7 +1310,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq,
> int level)
> kvm_riscv_set_irq(cpu, irq, level);
> } else {
> env->external_seip = level;
> -riscv_cpu_update_mip(cpu, 1 << irq,
> +riscv_cpu_update_mip(env, 1 << irq,
> BOOL_TO_MASK(level |
> env->software_seip));
> }
> break;
> @@ -1336,7 +1336,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq,
> int level)
> }
>
> /* Update mip.SGEIP bit */
> -riscv_cpu_update_mip(cpu, MIP_SGEIP,
> +riscv_cpu_update_mip(env, MIP_SGEIP,
> BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
> } else {
> g_assert_not_reached();
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 638e47c75a..5adefe4ab5 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -602,7 +602,8 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr
> addr);
> bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
> void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
> int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
> -uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
> +uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
> + uint64_t value);
> #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
> void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
> void *arg);
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index e677255f87..824f0cbd92 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -590,7 +590,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool
> enable)
> *
> * To solve this, we check and inject interrupt after setting V=1.
> */
> -riscv_cpu_update_mip(env_archcpu(env), 0, 0);
> +riscv_cpu_update_mip(env, 0, 0);
> }
> }
>
> @@ -610,10 +610,10 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t
> interrupts)
> }
> }
>
> -uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
> +uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
> + uint64_t value)
> {
> -CPURISCVState *env = >env;
> -CPUState *cs = CPU(cpu);
> +CPUState *cs = env_cpu(env);
> uint64_t gein, vsgein = 0, vstip = 0, old = env->mip;
>
> if (riscv_cpu_virt_enabled(env)) {
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index b453d8e8ca..53143f4d9a 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -990,15 +990,13 @@ static RISCVException read_vstimecmph(CPURISCVState
> *env, int csrno,
> static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
>target_ulong val)
> {
> -RISCVCPU *cpu = env_archcpu(env);
> -
> if (riscv_cpu_mxl(env) == MXL_RV32) {
> env->vstimecmp = deposit64(env->vstimecmp, 0, 32, (uint64_t)val);
> } else {
> env->vstimecmp = val;
> }
>
> -riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
> +riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
>env->htimedelta, MIP_VSTIP);
>
> return RISCV_EXCP_NONE;
> @@ -1007,10 +1005,8 @@ static RISCVException write_vstimecmp(CPURISCVState
> *env, int csrno,
> static RISCVException write_vstimecmph(CPURISCVState *env, int
Re: [PATCH 2/4] target/riscv: Simplify getting RISCVCPU pointer from env
On Thu, Mar 9, 2023 at 5:14 PM Weiwei Li wrote:
>
> Use env_archcpu() to get RISCVCPU pointer from env directly.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/pmu.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
> index b8e56d2b7b..a200741083 100644
> --- a/target/riscv/pmu.c
> +++ b/target/riscv/pmu.c
> @@ -223,7 +223,7 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState
> *env,
> return true;
> }
>
> -cpu = RISCV_CPU(env_cpu(env));
> +cpu = env_archcpu(env);
> if (!cpu->pmu_event_ctr_map) {
> return false;
> }
> @@ -249,7 +249,7 @@ bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env,
> uint32_t target_ctr)
> return true;
> }
>
> -cpu = RISCV_CPU(env_cpu(env));
> +cpu = env_archcpu(env);
> if (!cpu->pmu_event_ctr_map) {
> return false;
> }
> @@ -289,7 +289,7 @@ int riscv_pmu_update_event_map(CPURISCVState *env,
> uint64_t value,
> uint32_t ctr_idx)
> {
> uint32_t event_idx;
> -RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
> +RISCVCPU *cpu = env_archcpu(env);
>
> if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map) {
> return -1;
> @@ -390,7 +390,7 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t
> value, uint32_t ctr_idx)
> {
> uint64_t overflow_delta, overflow_at;
> int64_t overflow_ns, overflow_left = 0;
> -RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
> +RISCVCPU *cpu = env_archcpu(env);
> PMUCTRState *counter = >pmu_ctrs[ctr_idx];
>
> if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscofpmf) {
> --
> 2.25.1
>
>
Re: [PATCH 1/4] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
On Thu, Mar 9, 2023 at 5:14 PM Weiwei Li wrote:
>
> Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_helper.c | 9 -
> target/riscv/csr.c| 40 ---
> target/riscv/gdbstub.c| 4 ++--
> 3 files changed, 18 insertions(+), 35 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index f88c503cf4..e677255f87 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -314,7 +314,6 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
> int extirq, unsigned int extirq_def_prio,
> uint64_t pending, uint8_t *iprio)
> {
> -RISCVCPU *cpu = env_archcpu(env);
> int irq, best_irq = RISCV_EXCP_NONE;
> unsigned int prio, best_prio = UINT_MAX;
>
> @@ -323,7 +322,8 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
> }
>
> irq = ctz64(pending);
> -if (!((extirq == IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ssaia)) {
> +if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia :
> + riscv_cpu_cfg(env)->ext_ssaia)) {
> return irq;
> }
>
> @@ -765,7 +765,6 @@ static int get_physical_address(CPURISCVState *env,
> hwaddr *physical,
> int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
> bool use_background = false;
> hwaddr ppn;
> -RISCVCPU *cpu = env_archcpu(env);
> int napot_bits = 0;
> target_ulong napot_mask;
>
> @@ -946,7 +945,7 @@ restart:
>
> if (riscv_cpu_sxl(env) == MXL_RV32) {
> ppn = pte >> PTE_PPN_SHIFT;
> -} else if (pbmte || cpu->cfg.ext_svnapot) {
> +} else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) {
> ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
> } else {
> ppn = pte >> PTE_PPN_SHIFT;
> @@ -1043,7 +1042,7 @@ restart:
> benefit. */
> target_ulong vpn = addr >> PGSHIFT;
>
> -if (cpu->cfg.ext_svnapot && (pte & PTE_N)) {
> +if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
> napot_bits = ctzl(ppn) + 1;
> if ((i != (levels - 1)) || (napot_bits != 4)) {
> return TRANSLATE_FAIL;
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index ab566639e5..b453d8e8ca 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -88,9 +88,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
>
> static RISCVException vs(CPURISCVState *env, int csrno)
> {
> -RISCVCPU *cpu = env_archcpu(env);
> -
> -if (cpu->cfg.ext_zve32f) {
> +if (riscv_cpu_cfg(env)->ext_zve32f) {
> #if !defined(CONFIG_USER_ONLY)
> if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
> return RISCV_EXCP_ILLEGAL_INST;
> @@ -193,9 +191,7 @@ static RISCVException mctr32(CPURISCVState *env, int
> csrno)
>
> static RISCVException sscofpmf(CPURISCVState *env, int csrno)
> {
> -RISCVCPU *cpu = env_archcpu(env);
> -
> -if (!cpu->cfg.ext_sscofpmf) {
> +if (!riscv_cpu_cfg(env)->ext_sscofpmf) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> @@ -310,9 +306,7 @@ static RISCVException umode32(CPURISCVState *env, int
> csrno)
>
> static RISCVException mstateen(CPURISCVState *env, int csrno)
> {
> -RISCVCPU *cpu = env_archcpu(env);
> -
> -if (!cpu->cfg.ext_smstateen) {
> +if (!riscv_cpu_cfg(env)->ext_smstateen) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> @@ -321,9 +315,7 @@ static RISCVException mstateen(CPURISCVState *env, int
> csrno)
>
> static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
> {
> -RISCVCPU *cpu = env_archcpu(env);
> -
> -if (!cpu->cfg.ext_smstateen) {
> +if (!riscv_cpu_cfg(env)->ext_smstateen) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> @@ -390,10 +382,9 @@ static RISCVException sstateen(CPURISCVState *env, int
> csrno)
>
> static RISCVException sstc(CPURISCVState *env, int csrno)
> {
> -RISCVCPU *cpu = env_archcpu(env);
> bool hmode_check = false;
>
> -if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
> +if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> @@ -1170,27 +1161,21 @@ static RISCVException write_ignore(CPURISCVState
> *env, int csrno,
> static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> -RISCVCPU *cpu = env_archcpu(env);
> -
> -*val = cpu->cfg.mvendorid;
> +*val = riscv_cpu_cfg(env)->mvendorid;
> return RISCV_EXCP_NONE;
> }
>
> static RISCVException read_marchid(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> -RISCVCPU *cpu =
Re: [PATCH v2] Fix incorrect register name in disassembler for fmv,fabs,fneg instructions
On Sat, Mar 11, 2023 at 5:00 AM Mikhail Tyutin wrote:
>
> Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg
> instructions
>
> Signed-off-by: Mikhail Tyutin
> Reviewed-by: Alistair Francis
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> disas/riscv.c | 19 ++-
> 1 file changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 544558..882594c1be 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1014,6 +1014,7 @@ static const char rv_vreg_name_sym[32][4] = {
> #define rv_fmt_rd_offset "O\t0,o"
> #define rv_fmt_rd_rs1_rs2 "O\t0,1,2"
> #define rv_fmt_frd_rs1"O\t3,1"
> +#define rv_fmt_frd_frs1 "O\t3,4"
> #define rv_fmt_rd_frs1"O\t0,4"
> #define rv_fmt_rd_frs1_frs2 "O\t0,4,5"
> #define rv_fmt_frd_frs1_frs2 "O\t3,4,5"
> @@ -1580,15 +1581,15 @@ const rv_opcode_data opcode_data[] = {
> { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
> { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
> -{ "fmv.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -{ "fabs.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -{ "fneg.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -{ "fmv.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -{ "fabs.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -{ "fneg.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -{ "fmv.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -{ "fabs.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -{ "fneg.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> +{ "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +{ "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +{ "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +{ "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +{ "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +{ "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +{ "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +{ "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +{ "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
> { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
> { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
> --
> 2.34.1
>
>
>
Re: [PATCH qemu v2] linux-user: Emulate /proc/cpuinfo output for riscv
On Tue, Mar 14, 2023 at 6:28 AM ~abordado wrote:
>
> From: Afonso Bordado
>
> RISC-V does not expose all extensions via hwcaps, thus some userspace
> applications may want to query these via /proc/cpuinfo.
>
> Currently when querying this file the host's file is shown instead
> which is slightly confusing. Emulate a basic /proc/cpuinfo file
> with mmu info and an ISA string.
>
> Changes from V1:
>
> - Call `g_free` on ISA string.
> - Use `riscv_cpu_cfg` API.
> - Query `cpu_env->xl` to check for RV32.
>
> Signed-off-by: Afonso Bordado
> Reviewed-by: Palmer Dabbelt
> Acked-by: Palmer Dabbelt
> Reviewed-by: Laurent Vivier
> ---
With the changelog below these dashes:
Reviewed-by: Alistair Francis
Alistair
> linux-user/syscall.c | 34 +--
> tests/tcg/riscv64/Makefile.target | 1 +
> tests/tcg/riscv64/cpuinfo.c | 30 +++
> 3 files changed, 63 insertions(+), 2 deletions(-)
> create mode 100644 tests/tcg/riscv64/cpuinfo.c
>
> diff --git a/linux-user/syscall.c b/linux-user/syscall.c
> index 24cea6fb6a..0388f8b0b0 100644
> --- a/linux-user/syscall.c
> +++ b/linux-user/syscall.c
> @@ -8230,7 +8230,8 @@ void target_exception_dump(CPUArchState *env, const
> char *fmt, int code)
> }
>
> #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN || \
> -defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA)
> +defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA) ||
> \
> +defined(TARGET_RISCV)
> static int is_proc(const char *filename, const char *entry)
> {
> return strcmp(filename, entry) == 0;
> @@ -8308,6 +8309,35 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd)
> }
> #endif
>
> +#if defined(TARGET_RISCV)
> +static int open_cpuinfo(CPUArchState *cpu_env, int fd)
> +{
> +int i;
> +int num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
> +RISCVCPU *cpu = env_archcpu(cpu_env);
> +const RISCVCPUConfig *cfg = riscv_cpu_cfg((CPURISCVState *) cpu_env);
> +char *isa_string = riscv_isa_string(cpu);
> +const char *mmu;
> +
> +if (cfg->mmu) {
> +mmu = (cpu_env->xl == MXL_RV32) ? "sv32" : "sv48";
> +} else {
> +mmu = "none";
> +}
> +
> +for (i = 0; i < num_cpus; i++) {
> +dprintf(fd, "processor\t: %d\n", i);
> +dprintf(fd, "hart\t\t: %d\n", i);
> +dprintf(fd, "isa\t\t: %s\n", isa_string);
> +dprintf(fd, "mmu\t\t: %s\n", mmu);
> +dprintf(fd, "uarch\t\t: qemu\n\n");
> +}
> +
> +g_free(isa_string);
> +return 0;
> +}
> +#endif
> +
> #if defined(TARGET_M68K)
> static int open_hardware(CPUArchState *cpu_env, int fd)
> {
> @@ -8332,7 +8362,7 @@ static int do_openat(CPUArchState *cpu_env, int dirfd,
> const char *pathname, int
> #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
> { "/proc/net/route", open_net_route, is_proc },
> #endif
> -#if defined(TARGET_SPARC) || defined(TARGET_HPPA)
> +#if defined(TARGET_SPARC) || defined(TARGET_HPPA) || defined(TARGET_RISCV)
> { "/proc/cpuinfo", open_cpuinfo, is_proc },
> #endif
> #if defined(TARGET_M68K)
> diff --git a/tests/tcg/riscv64/Makefile.target
> b/tests/tcg/riscv64/Makefile.target
> index cc3ed65ffd..df93a2ce1f 100644
> --- a/tests/tcg/riscv64/Makefile.target
> +++ b/tests/tcg/riscv64/Makefile.target
> @@ -4,6 +4,7 @@
> VPATH += $(SRC_PATH)/tests/tcg/riscv64
> TESTS += test-div
> TESTS += noexec
> +TESTS += cpuinfo
>
> # Disable compressed instructions for test-noc
> TESTS += test-noc
> diff --git a/tests/tcg/riscv64/cpuinfo.c b/tests/tcg/riscv64/cpuinfo.c
> new file mode 100644
> index 00..296abd0a8c
> --- /dev/null
> +++ b/tests/tcg/riscv64/cpuinfo.c
> @@ -0,0 +1,30 @@
> +#include
> +#include
> +#include
> +#include
> +
> +#define BUFFER_SIZE 1024
> +
> +int main(void)
> +{
> +char buffer[BUFFER_SIZE];
> +FILE *fp = fopen("/proc/cpuinfo", "r");
> +assert(fp != NULL);
> +
> +while (fgets(buffer, BUFFER_SIZE, fp) != NULL) {
> +if (strstr(buffer, "processor") != NULL) {
> +assert(strstr(buffer, "processor\t: ") == buffer);
> +} else if (strstr(buffer, "hart") != NULL) {
> +assert(strstr(buffer, "hart\t\t: ") == buffer);
> +} else if (strstr(buffer, "isa") != NULL) {
> +assert(strcmp(buffer, "isa\t\t: rv64imafdc_zicsr_zifencei\n") ==
> 0);
> +} else if (strstr(buffer, "mmu") != NULL) {
> +assert(strcmp(buffer, "mmu\t\t: sv48\n") == 0);
> +} else if (strstr(buffer, "uarch") != NULL) {
> +assert(strcmp(buffer, "uarch\t\t: qemu\n") == 0);
> +}
> +}
> +
> +fclose(fp);
> +return 0;
> +}
> --
> 2.34.7
>
[PATCH v2 0/2] pci: slot_reserved_mask improvements
This patch series consists of two patches. The first provides accessor functions in pci.h to avoid direct access of slot_reserved_mask according to the comment at the top of include/hw/pci/pci_bus.h. No functional change is intended with this patch. The second patch allows a pci bus to be configured so slot_reserved_mask will only be enforced when the device to be added to the bus is configured for automatic slot assignment. The second patch also uses the new capability in the case of the pc/i440fx/xenfv machine types so the current behavior of reserving slot 2 for the Intel IGD for the xenfv machine will be ignored if an administrator manually configures another device to use the reserved slot. The current behavior of always reserving slots in the sun4u machine is preserved by this patch series; the patch series only changes how slot_reserved_mask works in the xenfv machine. Although the patch series can affect xenfv machines configured for igd-passthru if an administrator assigns some of the pci slot addresses manually, it does not affect the libxl default configuration for igd-passthru because libxl uses automatic slot assignment by default. Link: https://lore.kernel.org/qemu-devel/20230106064838-mutt-send-email-...@kernel.org/ Chuck Zmudzinski (2): pci: avoid accessing slot_reserved_mask directly outside of pci.c pci: allow slot_reserved_mask to be ignored with manual slot assignment Changelog v2: Add first patch and cover letter to make this a 2-patch series Make changes to the second patch (see second patch for changelog) hw/pci-host/i440fx.c | 1 + hw/pci/pci.c | 29 - hw/sparc64/sun4u.c | 7 +++ hw/xen/xen_pt.c | 7 +++ include/hw/pci/pci.h | 4 include/hw/pci/pci_bus.h | 1 + 6 files changed, 40 insertions(+), 9 deletions(-) -- 2.39.2
[PATCH v2 1/2] pci: avoid accessing slot_reserved_mask directly outside of pci.c
This patch provides accessor functions as replacements for direct
access to slot_reserved_mask according to the comment at the top
of include/hw/pci/pci_bus.h which advises that data structures for
PCIBus should not be directly accessed but instead be accessed using
accessor functions in pci.h.
Three accessor functions can conveniently replace all direct accesses
of slot_reserved_mask. With this patch, the new accessor functions are
used in hw/sparc64/sun4u.c and hw/xen/xen_pt.c and pci_bus.h is removed
from the included header files of the same two files.
No functional change intended.
Signed-off-by: Chuck Zmudzinski
---
v2: This is the first version of this patch, it did not exist in v1.
hw/pci/pci.c | 15 +++
hw/sparc64/sun4u.c | 7 +++
hw/xen/xen_pt.c | 7 +++
include/hw/pci/pci.h | 3 +++
4 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index def5000e7b..8a87ccc8b0 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -1116,6 +1116,21 @@ static bool pci_bus_devfn_reserved(PCIBus *bus, int
devfn)
return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn));
}
+uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus)
+{
+return bus->slot_reserved_mask;
+}
+
+void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask)
+{
+bus->slot_reserved_mask |= mask;
+}
+
+void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask)
+{
+bus->slot_reserved_mask &= ~mask;
+}
+
/* -1 for devfn means auto assign */
static PCIDevice *do_pci_register_device(PCIDevice *pci_dev,
const char *name, int devfn,
diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index a25e951f9d..eae7589462 100644
--- a/hw/sparc64/sun4u.c
+++ b/hw/sparc64/sun4u.c
@@ -31,7 +31,6 @@
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"
-#include "hw/pci/pci_bus.h"
#include "hw/pci/pci_host.h"
#include "hw/qdev-properties.h"
#include "hw/pci-host/sabre.h"
@@ -608,9 +607,9 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
/* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
reserved (leaving no slots free after on-board devices) however slots
0-3 are free on busB */
-pci_bus->slot_reserved_mask = 0xfffc;
-pci_busA->slot_reserved_mask = 0xfff1;
-pci_busB->slot_reserved_mask = 0xfff0;
+pci_bus_set_slot_reserved_mask(pci_bus, 0xfffc);
+pci_bus_set_slot_reserved_mask(pci_busA, 0xfff1);
+pci_bus_set_slot_reserved_mask(pci_busB, 0xfff0);
ebus = pci_new_multifunction(PCI_DEVFN(1, 0), true, TYPE_EBUS);
qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c
index 2d33d178ad..a540149639 100644
--- a/hw/xen/xen_pt.c
+++ b/hw/xen/xen_pt.c
@@ -57,7 +57,6 @@
#include
#include "hw/pci/pci.h"
-#include "hw/pci/pci_bus.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
#include "xen_pt.h"
@@ -951,7 +950,7 @@ void xen_igd_reserve_slot(PCIBus *pci_bus)
}
XEN_PT_LOG(0, "Reserving PCI slot 2 for IGD\n");
-pci_bus->slot_reserved_mask |= XEN_PCI_IGD_SLOT_MASK;
+pci_bus_set_slot_reserved_mask(pci_bus, XEN_PCI_IGD_SLOT_MASK);
}
static void xen_igd_clear_slot(DeviceState *qdev, Error **errp)
@@ -971,7 +970,7 @@ static void xen_igd_clear_slot(DeviceState *qdev, Error
**errp)
return;
}
-if (!(pci_bus->slot_reserved_mask & XEN_PCI_IGD_SLOT_MASK)) {
+if (!(pci_bus_get_slot_reserved_mask(pci_bus) & XEN_PCI_IGD_SLOT_MASK)) {
xpdc->pci_qdev_realize(qdev, errp);
return;
}
@@ -982,7 +981,7 @@ static void xen_igd_clear_slot(DeviceState *qdev, Error
**errp)
s->real_device.dev == XEN_PCI_IGD_DEV &&
s->real_device.func == XEN_PCI_IGD_FN &&
s->real_device.vendor_id == PCI_VENDOR_ID_INTEL) {
-pci_bus->slot_reserved_mask &= ~XEN_PCI_IGD_SLOT_MASK;
+pci_bus_clear_slot_reserved_mask(pci_bus, XEN_PCI_IGD_SLOT_MASK);
XEN_PT_LOG(pci_dev, "Intel IGD found, using slot 2\n");
}
xpdc->pci_qdev_realize(qdev, errp);
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index d5a40cd058..935b4b91b4 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -287,6 +287,9 @@ void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq,
void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq);
void pci_bus_irqs_cleanup(PCIBus *bus);
int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
+uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus);
+void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask);
+void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask);
/* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
static inline int pci_swizzle(int slot, int pin)
{
--
2.39.2
[PATCH v2 2/2] pci: allow slot_reserved_mask to be ignored with manual slot assignment
Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot 2 for Intel igd-passthru")
uses slot_reserved_mask to reserve slot 2 for the Intel IGD for the
xenfv machine when the guest is configured for igd-passthru.
A desired extension to that commit is to allow use of the reserved slot
if the administrator manually configures a device to use the reserved
slot. Currently, slot_reserved_mask is enforced unconditionally. With
this patch, the pci bus can be configured so the slot is only reserved
if the pci device to be added to the bus is configured for automatic
slot assignment.
To enable the desired behavior of slot_reserved_mask machine, add a
boolean member enforce_slot_reserved_mask_manual to struct PCIBus and
add a function pci_bus_ignore_slot_reserved_mask_manual which can be
called to change the default behavior of always enforcing
slot_reserved_mask so, in that case, slot_reserved_mask is only enforced
when the pci device being added is configured for automatic slot
assignment.
Call the new pci_bus_ignore_slot_reserved_mask_manual function after
creating the pci bus for the pc/i440fx/xenfv machine type to implement
the desired behavior of causing slot_reserved_mask to only apply when
the pci device to be added to a pc/i440fx/xenfv machine is configured
for automatic slot assignment.
Link:
https://lore.kernel.org/qemu-devel/20230106064838-mutt-send-email-...@kernel.org/
Signed-off-by: Chuck Zmudzinski
---
Changelog
v2: Change Subject of patch from
"pci: add enforce_slot_reserved_mask_manual property" To
"pci: allow slot_reserved_mask to be ignored with manual slot assignment"
Add pci_bus_ignore_slot_reserved_mask_manual function
Call pci_bus_ignore_slot_reserved_mask_manual at appropriate place
in hw/pci-host/i440fx.c
hw/pci-host/i440fx.c | 1 +
hw/pci/pci.c | 14 +-
include/hw/pci/pci.h | 1 +
include/hw/pci/pci_bus.h | 1 +
4 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c
index 262f82c303..8e00b88926 100644
--- a/hw/pci-host/i440fx.c
+++ b/hw/pci-host/i440fx.c
@@ -257,6 +257,7 @@ PCIBus *i440fx_init(const char *pci_type,
s = PCI_HOST_BRIDGE(dev);
b = pci_root_bus_new(dev, NULL, pci_address_space,
address_space_io, 0, TYPE_PCI_BUS);
+pci_bus_ignore_slot_reserved_mask_manual(b);
s->bus = b;
object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev));
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), _fatal);
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 8a87ccc8b0..670ecc6986 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -501,6 +501,7 @@ static void pci_root_bus_internal_init(PCIBus *bus,
DeviceState *parent,
assert(PCI_FUNC(devfn_min) == 0);
bus->devfn_min = devfn_min;
bus->slot_reserved_mask = 0x0;
+bus->enforce_slot_reserved_mask_manual = true;
bus->address_space_mem = address_space_mem;
bus->address_space_io = address_space_io;
bus->flags |= PCI_BUS_IS_ROOT;
@@ -1116,6 +1117,17 @@ static bool pci_bus_devfn_reserved(PCIBus *bus, int
devfn)
return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn));
}
+static bool pci_bus_devfn_reserved_manual(PCIBus *bus, int devfn)
+{
+return bus->enforce_slot_reserved_mask_manual &&
+(bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)));
+}
+
+void pci_bus_ignore_slot_reserved_mask_manual(PCIBus *bus)
+{
+bus->enforce_slot_reserved_mask_manual = false;
+}
+
uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus)
{
return bus->slot_reserved_mask;
@@ -1164,7 +1176,7 @@ static PCIDevice *do_pci_register_device(PCIDevice
*pci_dev,
"or reserved", name);
return NULL;
found: ;
-} else if (pci_bus_devfn_reserved(bus, devfn)) {
+} else if (pci_bus_devfn_reserved_manual(bus, devfn)) {
error_setg(errp, "PCI: slot %d function %d not available for %s,"
" reserved",
PCI_SLOT(devfn), PCI_FUNC(devfn), name);
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 935b4b91b4..48d29ec234 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -287,6 +287,7 @@ void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq,
void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq);
void pci_bus_irqs_cleanup(PCIBus *bus);
int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
+void pci_bus_ignore_slot_reserved_mask_manual(PCIBus *bus);
uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus);
void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask);
void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask);
diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
index 5653175957..e0f15ee9be 100644
--- a/include/hw/pci/pci_bus.h
+++ b/include/hw/pci/pci_bus.h
@@ -37,6 +37,7 @@ struct PCIBus {
void *iommu_opaque;
uint8_t devfn_min;
uint32_t slot_reserved_mask;
+bool enforce_slot_reserved_mask_manual;
Re: [PATCH v6 1/4] file-posix: add tracking of the zone write pointers
On 3/14/23 11:23, Dmitry Fomichev wrote:
>> @@ -3339,10 +3473,27 @@ static int coroutine_fn
>> raw_co_zone_mgmt(BlockDriverState *bs, BlockZoneOp op,
>> len >> BDRV_SECTOR_BITS);
>> ret = raw_thread_pool_submit(bs, handle_aiocb_zone_mgmt, );
>> if (ret != 0) {
>> + update_zones_wp(s->fd, wps, offset, index);
>> ret = -errno;
>> error_report("ioctl %s failed %d", op_name, ret);
>> + goto out;
>> }
>>
>> + if (zo == BLKRESETZONE && len == capacity) {
>> + for (int i = 0; i < bs->bl.nr_zones; ++i) {
>> + if (!BDRV_ZT_IS_CONV(wps->wp[i])) {
>> + wps->wp[i] = i * bs->bl.zone_size;
>
> This will reset write pointers of all read-only zones that may exist on the
> device and make the data stored in those zones unreadable. R/O zones need to
> be
> skipped in this loop.
And offline zones need to be skipped as well.
--
Damien Le Moal
Western Digital Research
Re: [PATCH v6 2/4] block: introduce zone append write for zoned devices
On Fri, 2023-03-10 at 18:31 +0800, Sam Li wrote:
> A zone append command is a write operation that specifies the first
> logical block of a zone as the write position. When writing to a zoned
> block device using zone append, the byte offset of writes is pointing
> to the write pointer of that zone.
s/writes is pointing to the write pointer of that zone/the call may point at any
position within the zone to which the data is being appended/
> Upon completion the device will
> respond with the position the data
s/position the data/position where the data/
> has been written in the zone.
>
> Signed-off-by: Sam Li
With nits above,
Reviewed-by: Dmitry Fomichev
> ---
> block/block-backend.c | 60 +++
> block/file-posix.c | 54 +---
> block/io.c | 21 +++
> block/io_uring.c | 4 +++
> block/linux-aio.c | 3 ++
> block/raw-format.c | 8 +
> include/block/block-io.h | 4 +++
> include/block/block_int-common.h | 5 +++
> include/block/raw-aio.h | 4 ++-
> include/sysemu/block-backend-io.h | 9 +
> 10 files changed, 166 insertions(+), 6 deletions(-)
>
> diff --git a/block/block-backend.c b/block/block-backend.c
> index f70b08e3f6..28e8f5d778 100644
> --- a/block/block-backend.c
> +++ b/block/block-backend.c
> @@ -1888,6 +1888,45 @@ BlockAIOCB *blk_aio_zone_mgmt(BlockBackend *blk,
> BlockZoneOp op,
> return >common;
> }
>
> +static void coroutine_fn blk_aio_zone_append_entry(void *opaque)
> +{
> + BlkAioEmAIOCB *acb = opaque;
> + BlkRwCo *rwco = >rwco;
> +
> + rwco->ret = blk_co_zone_append(rwco->blk, >bytes,
> + rwco->iobuf, rwco->flags);
> + blk_aio_complete(acb);
> +}
> +
> +BlockAIOCB *blk_aio_zone_append(BlockBackend *blk, int64_t *offset,
> + QEMUIOVector *qiov, BdrvRequestFlags flags,
> + BlockCompletionFunc *cb, void *opaque) {
> + BlkAioEmAIOCB *acb;
> + Coroutine *co;
> + IO_CODE();
> +
> + blk_inc_in_flight(blk);
> + acb = blk_aio_get(_aio_em_aiocb_info, blk, cb, opaque);
> + acb->rwco = (BlkRwCo) {
> + .blk = blk,
> + .ret = NOT_DONE,
> + .flags = flags,
> + .iobuf = qiov,
> + };
> + acb->bytes = *offset;
> + acb->has_returned = false;
> +
> + co = qemu_coroutine_create(blk_aio_zone_append_entry, acb);
> + aio_co_enter(blk_get_aio_context(blk), co);
> + acb->has_returned = true;
> + if (acb->rwco.ret != NOT_DONE) {
> + replay_bh_schedule_oneshot_event(blk_get_aio_context(blk),
> + blk_aio_complete_bh, acb);
> + }
> +
> + return >common;
> +}
> +
> /*
> * Send a zone_report command.
> * offset is a byte offset from the start of the device. No alignment
> @@ -1939,6 +1978,27 @@ int coroutine_fn blk_co_zone_mgmt(BlockBackend *blk,
> BlockZoneOp op,
> return ret;
> }
>
> +/*
> + * Send a zone_append command.
> + */
> +int coroutine_fn blk_co_zone_append(BlockBackend *blk, int64_t *offset,
> + QEMUIOVector *qiov, BdrvRequestFlags flags)
> +{
> + int ret;
> + IO_CODE();
> +
> + blk_inc_in_flight(blk);
> + blk_wait_while_drained(blk);
> + if (!blk_is_available(blk)) {
> + blk_dec_in_flight(blk);
> + return -ENOMEDIUM;
> + }
> +
> + ret = bdrv_co_zone_append(blk_bs(blk), offset, qiov, flags);
> + blk_dec_in_flight(blk);
> + return ret;
> +}
> +
> void blk_drain(BlockBackend *blk)
> {
> BlockDriverState *bs = blk_bs(blk);
> diff --git a/block/file-posix.c b/block/file-posix.c
> index 61ed769ac8..2ba9174778 100644
> --- a/block/file-posix.c
> +++ b/block/file-posix.c
> @@ -160,6 +160,7 @@ typedef struct BDRVRawState {
> bool has_write_zeroes:1;
> bool use_linux_aio:1;
> bool use_linux_io_uring:1;
> + int64_t *offset; /* offset of zone append operation */
> int page_cache_inconsistent; /* errno from fdatasync failure */
> bool has_fallocate;
> bool needs_alignment;
> @@ -1672,7 +1673,7 @@ static ssize_t handle_aiocb_rw_vector(RawPosixAIOData
> *aiocb)
> ssize_t len;
>
> len = RETRY_ON_EINTR(
> - (aiocb->aio_type & QEMU_AIO_WRITE) ?
> + (aiocb->aio_type & (QEMU_AIO_WRITE | QEMU_AIO_ZONE_APPEND)) ?
> qemu_pwritev(aiocb->aio_fildes,
> aiocb->io.iov,
> aiocb->io.niov,
> @@ -1701,7 +1702,7 @@ static ssize_t handle_aiocb_rw_linear(RawPosixAIOData
> *aiocb, char *buf)
> ssize_t len;
>
> while (offset < aiocb->aio_nbytes) {
> - if (aiocb->aio_type & QEMU_AIO_WRITE) {
> + if (aiocb->aio_type & (QEMU_AIO_WRITE | QEMU_AIO_ZONE_APPEND)) {
> len = pwrite(aiocb->aio_fildes,
> (const char *)buf + offset,
>
Re: [PATCH v6 4/4] block: add some trace events for zone append
On Fri, 2023-03-10 at 18:31 +0800, Sam Li wrote:
> Signed-off-by: Sam Li
Looks good,
Reviewed-by: Dmitry Fomichev
> block/file-posix.c | 3 +++
> block/trace-events | 2 ++
> 2 files changed, 5 insertions(+)
>
> diff --git a/block/file-posix.c b/block/file-posix.c
> index 2ba9174778..5187f810e5 100644
> --- a/block/file-posix.c
> +++ b/block/file-posix.c
> @@ -2489,6 +2489,8 @@ out:
> if (!BDRV_ZT_IS_CONV(wps->wp[index])) {
> if (type & QEMU_AIO_ZONE_APPEND) {
> *s->offset = wps->wp[index];
> + trace_zbd_zone_append_complete(bs, *s->offset
> + >> BDRV_SECTOR_BITS);
> }
> /* Advance the wp if needed */
> if (offset + bytes > wps->wp[index]) {
> @@ -3537,6 +3539,7 @@ static int coroutine_fn
> raw_co_zone_append(BlockDriverState *bs,
> len += iov_len;
> }
>
> + trace_zbd_zone_append(bs, *offset >> BDRV_SECTOR_BITS);
> return raw_co_prw(bs, *offset, len, qiov, QEMU_AIO_ZONE_APPEND);
> }
> #endif
> diff --git a/block/trace-events b/block/trace-events
> index 3f4e1d088a..32665158d6 100644
> --- a/block/trace-events
> +++ b/block/trace-events
> @@ -211,6 +211,8 @@ file_hdev_is_sg(int type, int version) "SG device found:
> type=%d, version=%d"
> file_flush_fdatasync_failed(int err) "errno %d"
> zbd_zone_report(void *bs, unsigned int nr_zones, int64_t sector) "bs %p
> report
> %d zones starting at sector offset 0x%" PRIx64 ""
> zbd_zone_mgmt(void *bs, const char *op_name, int64_t sector, int64_t len) "bs
> %p %s starts at sector offset 0x%" PRIx64 " over a range of 0x%" PRIx64 "
> sectors"
> +zbd_zone_append(void *bs, int64_t sector) "bs %p append at sector offset 0x%"
> PRIx64 ""
> +zbd_zone_append_complete(void *bs, int64_t sector) "bs %p returns append
> sector 0x%" PRIx64 ""
>
> # ssh.c
> sftp_error(const char *op, const char *ssh_err, int ssh_err_code, int
> sftp_err_code) "%s failed: %s (libssh error code: %d, sftp error code: %d)"
Re: [PATCH v6 1/4] file-posix: add tracking of the zone write pointers
On Fri, 2023-03-10 at 18:31 +0800, Sam Li wrote:
> Since Linux doesn't have a user API to issue zone append operations to
> zoned devices from user space, the file-posix driver is modified to add
> zone append emulation using regular writes. To do this, the file-posix
> driver tracks the wp location of all zones of the device. It uses an
> array of uint64_t. The most significant bit of each wp location indicates
> if the zone type is conventional zones.
>
> The zones wp can be changed due to the following operations issued:
> - zone reset: change the wp to the start offset of that zone
> - zone finish: change to the end location of that zone
> - write to a zone
> - zone append
>
> Signed-off-by: Sam Li
> ---
> block/file-posix.c | 159 ++-
> include/block/block-common.h | 14 +++
> include/block/block_int-common.h | 3 +
> 3 files changed, 172 insertions(+), 4 deletions(-)
>
> diff --git a/block/file-posix.c b/block/file-posix.c
> index 563acc76ae..61ed769ac8 100644
> --- a/block/file-posix.c
> +++ b/block/file-posix.c
> @@ -1324,6 +1324,77 @@ static int hdev_get_max_segments(int fd, struct stat
> *st)
> #endif
> }
>
> +#if defined(CONFIG_BLKZONED)
> +static int get_zones_wp(int fd, BlockZoneWps *wps, int64_t offset,
> + unsigned int nrz) {
> + struct blk_zone *blkz;
> + size_t rep_size;
> + uint64_t sector = offset >> BDRV_SECTOR_BITS;
> + int ret, n = 0, i = 0;
> + rep_size = sizeof(struct blk_zone_report) + nrz * sizeof(struct
> blk_zone);
> + g_autofree struct blk_zone_report *rep = NULL;
> +
> + rep = g_malloc(rep_size);
> + blkz = (struct blk_zone *)(rep + 1);
> + while (n < nrz) {
> + memset(rep, 0, rep_size);
> + rep->sector = sector;
> + rep->nr_zones = nrz - n;
> +
> + do {
> + ret = ioctl(fd, BLKREPORTZONE, rep);
> + } while (ret != 0 && errno == EINTR);
> + if (ret != 0) {
> + error_report("%d: ioctl BLKREPORTZONE at %" PRId64 " failed %d",
> + fd, offset, errno);
> + return -errno;
> + }
> +
> + if (!rep->nr_zones) {
> + break;
> + }
> +
> + for (i = 0; i < rep->nr_zones; i++, n++) {
> + /*
> + * The wp tracking cares only about sequential writes required
> and
> + * sequential write preferred zones so that the wp can advance to
> + * the right location.
> + * Use the most significant bit of the wp location to indicate
> the
> + * zone type: 0 for SWR/SWP zones and 1 for conventional zones.
> + */
> + if (blkz[i].type == BLK_ZONE_TYPE_CONVENTIONAL) {
> + wps->wp[i] = 1ULL << 63;
> + } else {
> + switch(blkz[i].cond) {
> + case BLK_ZONE_COND_FULL:
> + case BLK_ZONE_COND_READONLY:
> + /* Zone not writable */
> + wps->wp[i] = (blkz[i].start + blkz[i].len) <<
> BDRV_SECTOR_BITS;
> + break;
> + case BLK_ZONE_COND_OFFLINE:
> + /* Zone not writable nor readable */
> + wps->wp[i] = (blkz[i].start) << BDRV_SECTOR_BITS;
> + break;
> + default:
> + wps->wp[i] = blkz[i].wp << BDRV_SECTOR_BITS;
> + break;
> + }
> + }
> + }
> + sector = blkz[i - 1].start + blkz[i - 1].len;
> + }
> +
> + return 0;
> +}
> +
> +static void update_zones_wp(int fd, BlockZoneWps *wps, int64_t offset,
> + unsigned int nrz) {
> + if (get_zones_wp(fd, wps, offset, nrz) < 0) {
> + error_report("update zone wp failed");
> + }
> +}
> +#endif
> +
> static void raw_refresh_limits(BlockDriverState *bs, Error **errp)
> {
> BDRVRawState *s = bs->opaque;
> @@ -1413,6 +1484,21 @@ static void raw_refresh_limits(BlockDriverState *bs,
> Error **errp)
> if (ret >= 0) {
> bs->bl.max_active_zones = ret;
> }
> +
> + ret = get_sysfs_long_val(, "physical_block_size");
> + if (ret >= 0) {
> + bs->bl.write_granularity = ret;
> + }
> +
> + bs->bl.wps = g_malloc(sizeof(BlockZoneWps) +
> + sizeof(int64_t) * bs->bl.nr_zones);
> + ret = get_zones_wp(s->fd, bs->bl.wps, 0, bs->bl.nr_zones);
> + if (ret < 0) {
> + error_setg_errno(errp, -ret, "report wps failed");
> + g_free(bs->bl.wps);
> + return;
> + }
> + qemu_co_mutex_init(>bl.wps->colock);
> return;
> }
> out:
> @@ -2338,9 +2424,15 @@ static int coroutine_fn raw_co_prw(BlockDriverState
> *bs,
> uint64_t offset,
> {
> BDRVRawState *s = bs->opaque;
> RawPosixAIOData acb;
> + int ret;
>
> if (fd_open(bs) < 0)
> return -EIO;
> +#if
[PATCH] add option for a multislot usb ccid device
Signed-off-by: Klaus Ripke
hw/usb/dev-smartcard-reader.c:
add multi option for a multislot smartcard reader, similar to audio
multi
---
hw/usb/dev-smartcard-reader.c | 106 +-
1 file changed, 103 insertions(+), 3 deletions(-)
diff --git a/hw/usb/dev-smartcard-reader.c b/hw/usb/dev-smartcard-
reader.c
index be0a4fc3bc..b0063b669e 100644
--- a/hw/usb/dev-smartcard-reader.c
+++ b/hw/usb/dev-smartcard-reader.c
@@ -90,10 +90,13 @@ OBJECT_DECLARE_SIMPLE_TYPE(USBCCIDState,
USB_CCID_DEV)
* usbccid.sys (winxp, others untested) is a class driver so it
doesn't care.
* linux has a number of class drivers, but openct filters based on
* vendor/product (/etc/openct.conf under fedora), hence Gemplus.
+ * Use a Omnikey/HID 3121 with multislot for distinction.
*/
#define CCID_VENDOR_ID 0x08e6
#define CCID_PRODUCT_ID 0x4433
#define CCID_DEVICE_VERSION 0x
+#define CCID_VENDOR_ID_MULTI0x076b
+#define CCID_PRODUCT_ID_MULTI 0x3021
/*
* BULK_OUT messages from PC to Reader
@@ -312,7 +315,9 @@ struct USBCCIDState {
uint8_t bmSlotICCState;
uint8_t powered;
uint8_t notify_slot_change;
+/* properties */
uint8_t debug;
+bool multi;
};
/*
@@ -411,6 +416,34 @@ static const uint8_t qemu_ccid_descriptor[] = {
0x01, /* u8 bMaxCCIDBusySlots; */
};
+static const uint8_t qemu_ccid_descriptor_multi[] = {
+/* Smart Card Device Class Descriptor */
+0x36, /* u8 bLength; */
+0x21, /* u8 bDescriptorType; Functional */
+0x10, 0x01, /* u16 bcdCCID; CCID Specification Release Number.
*/
+0x0e, /* u8 bMaxSlotIndex; 14, as 16 slots can cause
trouble. */
+0x07, /* u8 bVoltageSupport; 01h - 5.0v, 02h - 3.0, 03
- 1.8 */
+
+0x01, 0x00, /* u32 dwProtocols; . = h.*/
+0x00, 0x00, /* : see above */
+0xa0, 0x0f, 0x00, 0x00, /* u32 dwMaximumClock; */
+0x00, 0x00, 0x01, 0x00,
+0x00, /* u8 bNumClockSupported; see above */
+0x80, 0x25, 0x00, 0x00, /* u32 dwMaxDataRate ; see above */
+0x00, 0xC2, 0x01, 0x00,
+0x00, /* u8 bNumDataRatesSupported; see above */
+0xfe, 0x00, 0x00, 0x00, /* u32 dwMaxIFSD; see above */
+0x00, 0x00, 0x00, 0x00, /* u32 dwSyncProtocols; see above */
+0x00, 0x00, 0x00, 0x00, /* u32 dwMechanical; see above */
+0xfe, 0x04, 0x04, 0x00, /* u32 dwFeatures; 400 for better
compat. */
+0x12, 0x00, 0x01, 0x00, /* u32 dwMaxCCIDMessageLength; see
above */
+0xFF, /* u8 bClassGetResponse; see above */
+0xFF, /* u8 bClassEnvelope; see above */
+0x00, 0x00, /* u16 wLcdLayout; see above */
+0x01, /* u8 bPINSupport; see above */
+0x0f, /* u8 bMaxCCIDBusySlots; modified from 1 */
+};
+
enum {
STR_MANUFACTURER = 1,
STR_PRODUCT,
@@ -457,6 +490,38 @@ static const USBDescIface desc_iface0 = {
}
};
+static const USBDescIface desc_iface0_multi = {
+.bInterfaceNumber = 0,
+.bNumEndpoints = 3,
+.bInterfaceClass = USB_CLASS_CSCID,
+.bInterfaceSubClass= USB_SUBCLASS_UNDEFINED,
+.bInterfaceProtocol= 0x00,
+.iInterface= STR_INTERFACE,
+.ndesc = 1,
+.descs = (USBDescOther[]) {
+{
+/* smartcard descriptor */
+.data = qemu_ccid_descriptor_multi,
+},
+},
+.eps = (USBDescEndpoint[]) {
+{
+.bEndpointAddress = USB_DIR_IN | CCID_INT_IN_EP,
+.bmAttributes = USB_ENDPOINT_XFER_INT,
+.bInterval = 255,
+.wMaxPacketSize= 64,
+},{
+.bEndpointAddress = USB_DIR_IN | CCID_BULK_IN_EP,
+.bmAttributes = USB_ENDPOINT_XFER_BULK,
+.wMaxPacketSize= 64,
+},{
+.bEndpointAddress = USB_DIR_OUT | CCID_BULK_OUT_EP,
+.bmAttributes = USB_ENDPOINT_XFER_BULK,
+.wMaxPacketSize= 64,
+},
+}
+};
+
static const USBDescDevice desc_device = {
.bcdUSB= 0x0110,
.bMaxPacketSize0 = 64,
@@ -474,6 +539,23 @@ static const USBDescDevice desc_device = {
},
};
+static const USBDescDevice desc_device_multi = {
+.bcdUSB= 0x0110,
+.bMaxPacketSize0 = 64,
+.bNumConfigurations= 1,
+.confs = (USBDescConfig[]) {
+{
+.bNumInterfaces= 1,
+.bConfigurationValue = 1,
+.bmAttributes = USB_CFG_ATT_ONE |
USB_CFG_ATT_SELFPOWER |
+ USB_CFG_ATT_WAKEUP,
+.bMaxPower = 50,
+.nif = 1,
+.ifs =
Re: [PATCH qemu v2] linux-user: Emulate /proc/cpuinfo output for riscv
On Tue, Mar 14, 2023 at 4:29 AM ~abordado wrote:
>
> From: Afonso Bordado
>
> RISC-V does not expose all extensions via hwcaps, thus some userspace
> applications may want to query these via /proc/cpuinfo.
>
> Currently when querying this file the host's file is shown instead
> which is slightly confusing. Emulate a basic /proc/cpuinfo file
> with mmu info and an ISA string.
>
> Changes from V1:
The changelog should go below ---
>
> - Call `g_free` on ISA string.
> - Use `riscv_cpu_cfg` API.
> - Query `cpu_env->xl` to check for RV32.
>
> Signed-off-by: Afonso Bordado
> Reviewed-by: Palmer Dabbelt
> Acked-by: Palmer Dabbelt
> Reviewed-by: Laurent Vivier
> ---
> linux-user/syscall.c | 34 +--
> tests/tcg/riscv64/Makefile.target | 1 +
> tests/tcg/riscv64/cpuinfo.c | 30 +++
> 3 files changed, 63 insertions(+), 2 deletions(-)
> create mode 100644 tests/tcg/riscv64/cpuinfo.c
>
> diff --git a/linux-user/syscall.c b/linux-user/syscall.c
> index 24cea6fb6a..0388f8b0b0 100644
> --- a/linux-user/syscall.c
> +++ b/linux-user/syscall.c
> @@ -8230,7 +8230,8 @@ void target_exception_dump(CPUArchState *env, const
> char *fmt, int code)
> }
>
> #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN || \
> -defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA)
> +defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA) ||
> \
> +defined(TARGET_RISCV)
> static int is_proc(const char *filename, const char *entry)
> {
> return strcmp(filename, entry) == 0;
> @@ -8308,6 +8309,35 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd)
> }
> #endif
>
> +#if defined(TARGET_RISCV)
> +static int open_cpuinfo(CPUArchState *cpu_env, int fd)
> +{
> +int i;
> +int num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
> +RISCVCPU *cpu = env_archcpu(cpu_env);
> +const RISCVCPUConfig *cfg = riscv_cpu_cfg((CPURISCVState *) cpu_env);
> +char *isa_string = riscv_isa_string(cpu);
> +const char *mmu;
> +
> +if (cfg->mmu) {
> +mmu = (cpu_env->xl == MXL_RV32) ? "sv32" : "sv48";
> +} else {
> +mmu = "none";
> +}
> +
> +for (i = 0; i < num_cpus; i++) {
> +dprintf(fd, "processor\t: %d\n", i);
> +dprintf(fd, "hart\t\t: %d\n", i);
> +dprintf(fd, "isa\t\t: %s\n", isa_string);
> +dprintf(fd, "mmu\t\t: %s\n", mmu);
> +dprintf(fd, "uarch\t\t: qemu\n\n");
> +}
> +
> +g_free(isa_string);
> +return 0;
> +}
> +#endif
> +
> #if defined(TARGET_M68K)
> static int open_hardware(CPUArchState *cpu_env, int fd)
> {
> @@ -8332,7 +8362,7 @@ static int do_openat(CPUArchState *cpu_env, int dirfd,
> const char *pathname, int
> #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
> { "/proc/net/route", open_net_route, is_proc },
> #endif
> -#if defined(TARGET_SPARC) || defined(TARGET_HPPA)
> +#if defined(TARGET_SPARC) || defined(TARGET_HPPA) || defined(TARGET_RISCV)
> { "/proc/cpuinfo", open_cpuinfo, is_proc },
> #endif
> #if defined(TARGET_M68K)
> diff --git a/tests/tcg/riscv64/Makefile.target
> b/tests/tcg/riscv64/Makefile.target
> index cc3ed65ffd..df93a2ce1f 100644
> --- a/tests/tcg/riscv64/Makefile.target
> +++ b/tests/tcg/riscv64/Makefile.target
> @@ -4,6 +4,7 @@
> VPATH += $(SRC_PATH)/tests/tcg/riscv64
> TESTS += test-div
> TESTS += noexec
> +TESTS += cpuinfo
>
> # Disable compressed instructions for test-noc
> TESTS += test-noc
> diff --git a/tests/tcg/riscv64/cpuinfo.c b/tests/tcg/riscv64/cpuinfo.c
> new file mode 100644
> index 00..296abd0a8c
> --- /dev/null
> +++ b/tests/tcg/riscv64/cpuinfo.c
> @@ -0,0 +1,30 @@
> +#include
> +#include
> +#include
> +#include
> +
> +#define BUFFER_SIZE 1024
> +
> +int main(void)
> +{
> +char buffer[BUFFER_SIZE];
> +FILE *fp = fopen("/proc/cpuinfo", "r");
> +assert(fp != NULL);
> +
> +while (fgets(buffer, BUFFER_SIZE, fp) != NULL) {
> +if (strstr(buffer, "processor") != NULL) {
> +assert(strstr(buffer, "processor\t: ") == buffer);
> +} else if (strstr(buffer, "hart") != NULL) {
> +assert(strstr(buffer, "hart\t\t: ") == buffer);
> +} else if (strstr(buffer, "isa") != NULL) {
> +assert(strcmp(buffer, "isa\t\t: rv64imafdc_zicsr_zifencei\n") ==
> 0);
> +} else if (strstr(buffer, "mmu") != NULL) {
> +assert(strcmp(buffer, "mmu\t\t: sv48\n") == 0);
> +} else if (strstr(buffer, "uarch") != NULL) {
> +assert(strcmp(buffer, "uarch\t\t: qemu\n") == 0);
> +}
> +}
> +
> +fclose(fp);
> +return 0;
> +}
Regards,
Bin
Re: [PATCH v2 07/10] contrib/gitdm: add Alibaba to the domain-map
Acked-by: Guo Ren On Sat, Mar 11, 2023 at 2:03 AM Alex Bennée wrote: > > This replaces the previous attempt to add c-sky.com so I've dropped > the review/ack tags. Group everything under Alibaba now. > > Added as requested by LIU Zhiwei. > > Signed-off-by: Alex Bennée > Cc: LIU Zhiwei > Cc: Xuan Zhuo > Cc: Guo Ren > --- > contrib/gitdm/domain-map| 1 + > contrib/gitdm/group-map-alibaba | 7 +++ > gitdm.config| 1 + > 3 files changed, 9 insertions(+) > create mode 100644 contrib/gitdm/group-map-alibaba > > diff --git a/contrib/gitdm/domain-map b/contrib/gitdm/domain-map > index 0261533990..e678c23a9c 100644 > --- a/contrib/gitdm/domain-map > +++ b/contrib/gitdm/domain-map > @@ -4,6 +4,7 @@ > # This maps email domains to nice easy to read company names > # > > +linux.alibaba.com Alibaba > amazon.com Amazon > amazon.co.ukAmazon > amd.com AMD > diff --git a/contrib/gitdm/group-map-alibaba b/contrib/gitdm/group-map-alibaba > new file mode 100644 > index 00..0ebbe6b06e > --- /dev/null > +++ b/contrib/gitdm/group-map-alibaba > @@ -0,0 +1,7 @@ > +# > +# Alibaba contributors including its subsidiaries > +# > + > +# c-sky.com, now part of T-Head, wholly-owned entity of Alibaba Group > +ren_...@c-sky.com > +zhiwei_...@c-sky.com > diff --git a/gitdm.config b/gitdm.config > index 4b52ee47be..6908ddbd19 100644 > --- a/gitdm.config > +++ b/gitdm.config > @@ -31,6 +31,7 @@ EmailMap contrib/gitdm/domain-map > # identifiable corporate emails. Please keep this list sorted. > # > > +GroupMap contrib/gitdm/group-map-alibaba Alibaba > GroupMap contrib/gitdm/group-map-cadence Cadence Design Systems > GroupMap contrib/gitdm/group-map-codeweavers CodeWeavers > GroupMap contrib/gitdm/group-map-facebook Facebook > -- > 2.39.2 > -- Best Regards Guo Ren
Re: [PATCH v16 7/8] block: add some trace events for new block layer APIs
On Fri, 2023-03-10 at 18:24 +0800, Sam Li wrote:
> Signed-off-by: Sam Li
> Reviewed-by: Stefan Hajnoczi
With one small nit below,
Reviewed-by: Dmitry Fomichev
> ---
> block/file-posix.c | 3 +++
> block/trace-events | 2 ++
> 2 files changed, 5 insertions(+)
>
> diff --git a/block/file-posix.c b/block/file-posix.c
> index 2eceb250f1..563acc76ae 100644
> --- a/block/file-posix.c
> +++ b/block/file-posix.c
> @@ -3256,6 +3256,7 @@ static int coroutine_fn
> raw_co_zone_report(BlockDriverState *bs, int64_t offset,
> BlockZoneDescriptor *zones) {
> BDRVRawState *s = bs->opaque;
> RawPosixAIOData acb;
> + trace_zbd_zone_report(bs, *nr_zones, offset >> BDRV_SECTOR_BITS);
The code in this function could be made a bit simpler -
BDRVRawState *s = bs->opaque;
RawPosixAIOData acb = (RawPosixAIOData) {
.bs = bs,
.aio_fildes = s->fd,
.aio_type = QEMU_AIO_ZONE_REPORT,
.aio_offset = offset,
.zone_report= {
.nr_zones = nr_zones,
.zones = zones,
},
};
trace_zbd_zone_report(bs, *nr_zones, offset >> BDRV_SECTOR_BITS);
return raw_thread_pool_submit(bs, handle_aiocb_zone_report, );
>
> acb = (RawPosixAIOData) {
> .bs = bs,
> @@ -3334,6 +3335,8 @@ static int coroutine_fn
> raw_co_zone_mgmt(BlockDriverState
> *bs, BlockZoneOp op,
> },
> };
>
> + trace_zbd_zone_mgmt(bs, op_name, offset >> BDRV_SECTOR_BITS,
> + len >> BDRV_SECTOR_BITS);
> ret = raw_thread_pool_submit(bs, handle_aiocb_zone_mgmt, );
> if (ret != 0) {
> ret = -errno;
> diff --git a/block/trace-events b/block/trace-events
> index 48dbf10c66..3f4e1d088a 100644
> --- a/block/trace-events
> +++ b/block/trace-events
> @@ -209,6 +209,8 @@ file_FindEjectableOpticalMedia(const char *media)
> "Matching
> using %s"
> file_setup_cdrom(const char *partition) "Using %s as optical disc"
> file_hdev_is_sg(int type, int version) "SG device found: type=%d, version=%d"
> file_flush_fdatasync_failed(int err) "errno %d"
> +zbd_zone_report(void *bs, unsigned int nr_zones, int64_t sector) "bs %p
> report
> %d zones starting at sector offset 0x%" PRIx64 ""
> +zbd_zone_mgmt(void *bs, const char *op_name, int64_t sector, int64_t len) "bs
> %p %s starts at sector offset 0x%" PRIx64 " over a range of 0x%" PRIx64 "
> sectors"
>
> # ssh.c
> sftp_error(const char *op, const char *ssh_err, int ssh_err_code, int
> sftp_err_code) "%s failed: %s (libssh error code: %d, sftp error code: %d)"
Re: [PATCH v16 3/8] block: add block layer APIs resembling Linux ZonedBlockDevice ioctls
On Fri, 2023-03-10 at 18:23 +0800, Sam Li wrote:
> Add zoned device option to host_device BlockDriver. It will be presented only
> for zoned host block devices. By adding zone management operations to the
> host_block_device BlockDriver, users can use the new block layer APIs
> including Report Zone and four zone management operations
> (open, close, finish, reset, reset_all).
>
> Qemu-io uses the new APIs to perform zoned storage commands of the device:
> zone_report(zrp), zone_open(zo), zone_close(zc), zone_reset(zrs),
> zone_finish(zf).
>
> For example, to test zone_report, use following command:
> $ ./build/qemu-io --image-opts -n driver=host_device, filename=/dev/nullb0
> -c "zrp offset nr_zones"
>
> Signed-off-by: Sam Li
> Reviewed-by: Hannes Reinecke
> Reviewed-by: Stefan Hajnoczi
LGTM,
Reviewed-by: Dmitry Fomichev
> Acked-by: Kevin Wolf
> ---
> block/block-backend.c | 133 +
> block/file-posix.c | 309 +-
> block/io.c | 41
> include/block/block-io.h | 9 +
> include/block/block_int-common.h | 21 ++
> include/block/raw-aio.h | 6 +-
> include/sysemu/block-backend-io.h | 18 ++
> meson.build | 4 +
> qemu-io-cmds.c | 149 ++
> 9 files changed, 687 insertions(+), 3 deletions(-)
>
> diff --git a/block/block-backend.c b/block/block-backend.c
> index 278b04ce69..f70b08e3f6 100644
> --- a/block/block-backend.c
> +++ b/block/block-backend.c
> @@ -1806,6 +1806,139 @@ int coroutine_fn blk_co_flush(BlockBackend *blk)
> return ret;
> }
>
> +static void coroutine_fn blk_aio_zone_report_entry(void *opaque)
> +{
> + BlkAioEmAIOCB *acb = opaque;
> + BlkRwCo *rwco = >rwco;
> +
> + rwco->ret = blk_co_zone_report(rwco->blk, rwco->offset,
> + (unsigned int*)acb->bytes,rwco->iobuf);
> + blk_aio_complete(acb);
> +}
> +
> +BlockAIOCB *blk_aio_zone_report(BlockBackend *blk, int64_t offset,
> + unsigned int *nr_zones,
> + BlockZoneDescriptor *zones,
> + BlockCompletionFunc *cb, void *opaque)
> +{
> + BlkAioEmAIOCB *acb;
> + Coroutine *co;
> + IO_CODE();
> +
> + blk_inc_in_flight(blk);
> + acb = blk_aio_get(_aio_em_aiocb_info, blk, cb, opaque);
> + acb->rwco = (BlkRwCo) {
> + .blk = blk,
> + .offset = offset,
> + .iobuf = zones,
> + .ret = NOT_DONE,
> + };
> + acb->bytes = (int64_t)nr_zones,
> + acb->has_returned = false;
> +
> + co = qemu_coroutine_create(blk_aio_zone_report_entry, acb);
> + aio_co_enter(blk_get_aio_context(blk), co);
> +
> + acb->has_returned = true;
> + if (acb->rwco.ret != NOT_DONE) {
> + replay_bh_schedule_oneshot_event(blk_get_aio_context(blk),
> + blk_aio_complete_bh, acb);
> + }
> +
> + return >common;
> +}
> +
> +static void coroutine_fn blk_aio_zone_mgmt_entry(void *opaque)
> +{
> + BlkAioEmAIOCB *acb = opaque;
> + BlkRwCo *rwco = >rwco;
> +
> + rwco->ret = blk_co_zone_mgmt(rwco->blk, (BlockZoneOp)rwco->iobuf,
> + rwco->offset, acb->bytes);
> + blk_aio_complete(acb);
> +}
> +
> +BlockAIOCB *blk_aio_zone_mgmt(BlockBackend *blk, BlockZoneOp op,
> + int64_t offset, int64_t len,
> + BlockCompletionFunc *cb, void *opaque) {
> + BlkAioEmAIOCB *acb;
> + Coroutine *co;
> + IO_CODE();
> +
> + blk_inc_in_flight(blk);
> + acb = blk_aio_get(_aio_em_aiocb_info, blk, cb, opaque);
> + acb->rwco = (BlkRwCo) {
> + .blk = blk,
> + .offset = offset,
> + .iobuf = (void *)op,
> + .ret = NOT_DONE,
> + };
> + acb->bytes = len;
> + acb->has_returned = false;
> +
> + co = qemu_coroutine_create(blk_aio_zone_mgmt_entry, acb);
> + aio_co_enter(blk_get_aio_context(blk), co);
> +
> + acb->has_returned = true;
> + if (acb->rwco.ret != NOT_DONE) {
> + replay_bh_schedule_oneshot_event(blk_get_aio_context(blk),
> + blk_aio_complete_bh, acb);
> + }
> +
> + return >common;
> +}
> +
> +/*
> + * Send a zone_report command.
> + * offset is a byte offset from the start of the device. No alignment
> + * required for offset.
> + * nr_zones represents IN maximum and OUT actual.
> + */
> +int coroutine_fn blk_co_zone_report(BlockBackend *blk, int64_t offset,
> + unsigned int *nr_zones,
> + BlockZoneDescriptor *zones)
> +{
> + int ret;
> + IO_CODE();
> +
> + blk_inc_in_flight(blk); /* increase before waiting */
> + blk_wait_while_drained(blk);
> + if (!blk_is_available(blk)) {
> + blk_dec_in_flight(blk);
> + return -ENOMEDIUM;
> + }
> + ret =
Re: [PATCH v16 1/8] include: add zoned device structs
On Fri, 2023-03-10 at 18:23 +0800, Sam Li wrote:
> Signed-off-by: Sam Li
> Reviewed-by: Stefan Hajnoczi
> Reviewed-by: Damien Le Moal
> Reviewed-by: Hannes Reinecke
Looks good to me.
Reviewed-by: Dmitry Fomichev
> ---
> include/block/block-common.h | 43
> 1 file changed, 43 insertions(+)
>
> diff --git a/include/block/block-common.h b/include/block/block-common.h
> index b5122ef8ab..1576fcf2ed 100644
> --- a/include/block/block-common.h
> +++ b/include/block/block-common.h
> @@ -75,6 +75,49 @@ typedef struct BlockDriver BlockDriver;
> typedef struct BdrvChild BdrvChild;
> typedef struct BdrvChildClass BdrvChildClass;
>
> +typedef enum BlockZoneOp {
> + BLK_ZO_OPEN,
> + BLK_ZO_CLOSE,
> + BLK_ZO_FINISH,
> + BLK_ZO_RESET,
> +} BlockZoneOp;
> +
> +typedef enum BlockZoneModel {
> + BLK_Z_NONE = 0x0, /* Regular block device */
> + BLK_Z_HM = 0x1, /* Host-managed zoned block device */
> + BLK_Z_HA = 0x2, /* Host-aware zoned block device */
> +} BlockZoneModel;
> +
> +typedef enum BlockZoneState {
> + BLK_ZS_NOT_WP = 0x0,
> + BLK_ZS_EMPTY = 0x1,
> + BLK_ZS_IOPEN = 0x2,
> + BLK_ZS_EOPEN = 0x3,
> + BLK_ZS_CLOSED = 0x4,
> + BLK_ZS_RDONLY = 0xD,
> + BLK_ZS_FULL = 0xE,
> + BLK_ZS_OFFLINE = 0xF,
> +} BlockZoneState;
> +
> +typedef enum BlockZoneType {
> + BLK_ZT_CONV = 0x1, /* Conventional random writes supported */
> + BLK_ZT_SWR = 0x2, /* Sequential writes required */
> + BLK_ZT_SWP = 0x3, /* Sequential writes preferred */
> +} BlockZoneType;
> +
> +/*
> + * Zone descriptor data structure.
> + * Provides information on a zone with all position and size values in bytes.
> + */
> +typedef struct BlockZoneDescriptor {
> + uint64_t start;
> + uint64_t length;
> + uint64_t cap;
> + uint64_t wp;
> + BlockZoneType type;
> + BlockZoneState state;
> +} BlockZoneDescriptor;
> +
> typedef struct BlockDriverInfo {
> /* in bytes, 0 if irrelevant */
> int cluster_size;
[PATCH 1/2] target/s390x: Fix EXECUTE of relative long instructions
The code uses the wrong base for relative addressing: it should use the
target instruction address and not the EXECUTE's address.
Fix by storing the target instruction address in the new CPUS390XState
member and loading it from the code generated by in2_ri2().
Reported-by: Nina Schoetterl-Glausch
Signed-off-by: Ilya Leoshkevich
---
target/s390x/cpu.h| 1 +
target/s390x/tcg/mem_helper.c | 1 +
target/s390x/tcg/translate.c | 10 +-
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 7d6d01325b2..8aaf8dd5a3b 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -87,6 +87,7 @@ struct CPUArchState {
uint64_t cc_vr;
uint64_t ex_value;
+uint64_t ex_target;
uint64_t __excp_addr;
uint64_t psa;
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index 6835c26dda4..00afae2b640 100644
--- a/target/s390x/tcg/mem_helper.c
+++ b/target/s390x/tcg/mem_helper.c
@@ -2530,6 +2530,7 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen,
uint64_t r1, uint64_t addr)
that ex_value is non-zero, which flags that we are in a state
that requires such execution. */
env->ex_value = insn | ilen;
+env->ex_target = addr;
}
uint32_t HELPER(mvcos)(CPUS390XState *env, uint64_t dest, uint64_t src,
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 811049ea281..fefff95b91c 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -5888,7 +5888,15 @@ static void in2_a2(DisasContext *s, DisasOps *o)
static void in2_ri2(DisasContext *s, DisasOps *o)
{
-o->in2 = tcg_const_i64(s->base.pc_next + (int64_t)get_field(s, i2) * 2);
+int64_t delta = (int64_t)get_field(s, i2) * 2;
+
+if (unlikely(s->ex_value)) {
+o->in2 = tcg_temp_new_i64();
+tcg_gen_ld_i64(o->in2, cpu_env, offsetof(CPUS390XState, ex_target));
+tcg_gen_addi_i64(o->in2, o->in2, delta);
+} else {
+o->in2 = tcg_const_i64(s->base.pc_next + delta);
+}
}
#define SPEC_in2_ri2 0
--
2.39.2
[PATCH 2/2] tests/tcg/s390x: Add ex-relative-long.c
Test EXECUTE and EXECUTE RELATIVE LONG with relative long instructions
as targets.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target| 1 +
tests/tcg/s390x/ex-relative-long.c | 149 +
2 files changed, 150 insertions(+)
create mode 100644 tests/tcg/s390x/ex-relative-long.c
diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.target
index 72ad309b273..ed2709ee2c3 100644
--- a/tests/tcg/s390x/Makefile.target
+++ b/tests/tcg/s390x/Makefile.target
@@ -28,6 +28,7 @@ TESTS+=div
TESTS+=clst
TESTS+=long-double
TESTS+=cdsg
+TESTS+=ex-relative-long
cdsg: CFLAGS+=-pthread
cdsg: LDFLAGS+=-pthread
diff --git a/tests/tcg/s390x/ex-relative-long.c
b/tests/tcg/s390x/ex-relative-long.c
new file mode 100644
index 000..e47dac7e2c3
--- /dev/null
+++ b/tests/tcg/s390x/ex-relative-long.c
@@ -0,0 +1,149 @@
+/* Check EXECUTE with relative long instructions as targets. */
+#include
+#include
+
+struct test {
+const char *name;
+long (*func)(long reg, long *cc);
+long exp_reg;
+long exp_mem;
+long exp_cc;
+};
+
+/* Variable targeted by relative long instructions. */
+long mem;
+
+/* Initial %r2 value. */
+#define REG 0x1234567887654321
+
+/* Initial "mem" value. */
+#define MEM 0xfedcba9889abcdef
+
+/* Initial cc value. */
+#define CC 0
+
+/* Relative long instructions. */
+#define FOR_EACH_TEST(F)
\
+F(cgfrl, REG,MEM,2)
\
+F(cghrl, REG,MEM,2)
\
+F(cgrl, REG,MEM,2)
\
+F(chrl, REG,MEM,1)
\
+F(clgfrl, REG,MEM,2)
\
+F(clghrl, REG,MEM,2)
\
+F(clgrl, REG,MEM,1)
\
+F(clhrl, REG,MEM,2)
\
+F(clrl, REG,MEM,1)
\
+F(crl,REG,MEM,1)
\
+F(larl, (long), MEM,CC)
\
+F(lgfrl, 0xfedcba98, MEM,CC)
\
+F(lghrl, 0xfedc, MEM,CC)
\
+F(lgrl, MEM,MEM,CC)
\
+F(lhrl, 0x12345678fedc, MEM,CC)
\
+F(llghrl, 0xfedc, MEM,CC)
\
+F(llhrl, 0x12345678fedc, MEM,CC)
\
+F(lrl,0x12345678fedcba98, MEM,CC)
\
+F(stgrl, REG,REG,CC)
\
+F(sthrl, REG,0x4321ba9889abcdef, CC)
\
+F(strl, REG,0x8765432189abcdef, CC)
+
+/* Test functions. */
+#define DEFINE_EX_TEST(insn, exp_reg, exp_mem, exp_cc)
\
+static long test_ex_ ## insn(long reg, long *cc)
\
+{
\
+register long reg_val asm("r2");
\
+long cc_val, mask, target;
\
+
\
+reg_val = reg;
\
+asm("xgr %[cc_val],%[cc_val]\n" /* initial cc */
\
+"lghi %[mask],0x20\n"/* make target use %r2 */
\
+"larl %[target],0f\n"
\
+"ex %[mask],0(%[target])\n"
\
+"jg 1f\n"
\
+"0: " #insn " %%r0,mem\n"
\
+"1: ipm %[cc_val]\n"
\
+: [cc_val] "=" (cc_val)
\
+, [mask] "=" (mask)
\
+, [target] "=" (target)
\
+, [reg_val] "+" (reg_val)
\
+: : "cc", "memory");
\
+reg = reg_val;
\
+*cc = (cc_val >> 28) & 3;
\
+
[PATCH 0/2] Fix EXECUTE of relative long instructions
Hi, This series fixes EXECUTE of instructions like LARL, LGLR, etc. Currently the address calculation uses EXECUTE's address as a base, while it should be using that of the target instruction. Patch 1 fixes the issue, patch 2 adds a test. Best regards, Ilya Ilya Leoshkevich (2): target/s390x: Fix EXECUTE of relative long instructions tests/tcg/s390x: Add ex-relative-long.c target/s390x/cpu.h | 1 + target/s390x/tcg/mem_helper.c | 1 + target/s390x/tcg/translate.c | 10 +- tests/tcg/s390x/Makefile.target| 1 + tests/tcg/s390x/ex-relative-long.c | 149 + 5 files changed, 161 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/s390x/ex-relative-long.c -- 2.39.2
Re: [PULL 13/27] hw/xen: Add xenstore operations to allow redirection to internal emulation
Hi, David,
On Mon, Mar 13, 2023 at 4:45 AM David Woodhouse wrote:
>
> On Sun, 2023-03-12 at 15:19 -0400, Jason Andryuk wrote:
> >
> > This breaks dm_restrict=1 since the xs_open is not allowed by the
> > time
> > this is called. There are other evtchn errors before this as well:
> > # cat /var/log/xen/qemu-dm-debian.log
> > char device redirected to /dev/pts/8 (label serial0)
> > xen be core: can't open evtchn device
> > xen be core: can't open evtchn device
> > xen be core: can't open evtchn device
> > xen be core: can't open evtchn device
> > xen be core: can't open evtchn device
> > xen be core: can't open evtchn device
> > xen be core: can't open evtchn device
> > xen be core: can't open evtchn device
> > Could not contact XenStore
> >
> > Ok, those "xen be core: can't open evtchn device" were there before
> > the recent changes and seem to be non-fatal.
>
> Hm, I *think* we can just revert that part and use the global
> 'xenstore' like we did before, except via the new ops.
>
> --- a/accel/xen/xen-all.c
> +++ b/accel/xen/xen-all.c
> @@ -32,28 +32,18 @@ xendevicemodel_handle *xen_dmod;
>
> static void xenstore_record_dm_state(const char *state)
> {
> -struct xs_handle *xs;
> char path[50];
>
> -/* We now have everything we need to set the xenstore entry. */
> -xs = xs_open(0);
> -if (xs == NULL) {
> -fprintf(stderr, "Could not contact XenStore\n");
> -exit(1);
> -}
> -
> snprintf(path, sizeof (path), "device-model/%u/state", xen_domid);
> /*
> * This call may fail when running restricted so don't make it fatal in
> * that case. Toolstacks should instead use QMP to listen for state
> changes.
> */
> -if (!xs_write(xs, XBT_NULL, path, state, strlen(state)) &&
> +if (!qemu_xen_xs_write(xenstore, XBT_NULL, path, state, strlen(state)) &&
> !xen_domid_restrict) {
> error_report("error recording dm state");
> exit(1);
> }
> -
> -xs_close(xs);
> }
This looks good, better than what I posted, and seems to work for both
dm_restrict set and unset.
>
> Alternatively, that xs_write is destined to fail anyway in the
> xen_domid_restrict case, isn't it? So the xs_open() should be allowed
> to fail similarly. Or perhaps we shouldn't even *try*?
For dm_restricted, xs_write() does fail. I verified that with a print
statement. I think "shouldn't even try" makes sense. I'm thinking
that xen_domid_restricted shouldn't even add the callback. Something
like:
--- a/accel/xen/xen-all.c
+++ b/accel/xen/xen-all.c
@@ -39,8 +39,7 @@ static void xenstore_record_dm_state(const char *state)
* This call may fail when running restricted so don't make it fatal in
* that case. Toolstacks should instead use QMP to listen for
state changes.
*/
-if (!qemu_xen_xs_write(xenstore, XBT_NULL, path, state, strlen(state)) &&
-!xen_domid_restrict) {
+if (!qemu_xen_xs_write(xenstore, XBT_NULL, path, state, strlen(state))) {
error_report("error recording dm state");
exit(1);
}
@@ -101,7 +100,10 @@ static int xen_init(MachineState *ms)
xc_interface_close(xen_xc);
return -1;
}
-qemu_add_vm_change_state_handler(xen_change_state_handler, NULL);
+
+if(!xen_domid_restrict)
+qemu_add_vm_change_state_handler(xen_change_state_handler, NULL);
+
/*
* opt out of system RAM being allocated by generic code
*/
That works for both dm_restrict 0 & 1.
I think you should submit your change and I can follow up with the
above if it seems desirable.
Thanks,
Jason
Re: [PATCH] include/blcok: fixup typos
On Mon, 2023-03-13 at 10:01 +, Peter Maydell wrote: > On Mon, 13 Mar 2023 at 00:26, Wilfred Mallawa > wrote: > > > > From: Wilfred Mallawa > > > > Fixup a few minor typos > > Typo in patch subject line: should be 'block' :-) Ha! already sent a V2 for this :) > > > Signed-off-by: Wilfred Mallawa > > --- > > Otherwise > Reviewed-by: Peter Maydell > > thanks > -- PMM
need help with ACPI generic port implementation for QEMU
I'm attempting to implement the support of ACPI "generic port" detailed in the ACPI r6.5 spec in QEMU. The spec section 5.2.16.7 details the Generi Port Affinity Structure where it ties a Device Handle to a Proximity Domain. And with section 6.2.28.4 for the HMAT table, the latency and bandwidth information are provided by the System Locality Latency and Bandwidth Information Structure (SLLBIS) sub-table. In the CXL world, a hotplugged type-3 device would not have the approriate end to end latency and bandwidth data provided by the HMAT. The QoS data needs to be computed from the CXL host bridge (HB) and the endpoint device. Some parts of the data are supplemented by the CDAT from the endpoint device and the CXL switch(es) if they exist in the path. The component missing is the path between the CPU and the CXL HB (generic port). The data provided by HMAT for generic port will fill that gap. In QEMU, the SRAT is generated by code and the table entry addition is a somewhat straight forward implementation. The HMAT information is fed through user parameter inputs and will require a new object to allow the representation of generic port. The intention is to be able to do something like: "-object genport,id=genport0" "-numa node,genport=genport0,nodeid=5,initiator=0" "-numa dist,src=0,dst=5,val=$dist" "-numa hmat-lb,initiator=0,target=5,hierachy=memory,data-type=access-latency,latency=$lat" "-numa hmat-lb,initiator=0,target=5,hierarchy=memory,data-type=access-bandwidth,bandwidth=$bw" I put together a skeletal generic port device that seems to pass the numa parsing code parts. However I'm hitting an error after that that I can't figure out how to deal with: qemu-system-x86_64: ../hw/core/qdev.c:316: qdev_assert_realized_properly_cb: Assertion `dev->realized' failed. At what point is qdev_realize() being called for a device object? It seems that this never happens for this generic port device. What am I missing in terms of initialization or setup? Any assistance is appreciated. Thanks in advance. Here's my latest code that I'm playing with as reference: https://github.com/davejiang/qemu/tree/genport
Re: [PATCH 09/11] tests/tcg: disable pauth for aarch64 gdb tests
On Mon, 13 Mar 2023 at 19:21, Richard Henderson wrote: > > On 3/13/23 04:44, Luis Machado wrote: > >> Luis: I think that rather than doing (2) with a QEMU namespace, > >> we should define a gdb namespace for this. That makes it clear > >> that this is still a gdb-upstream-sanctioned way of exposing > >> the pauth registers. > > > > That should be fine as well, and would work to side-step the gdb 12 bug so > > it doesn't crash. > > > > We could name the feature "org.gnu.gdb.aarch64.pauth_v2" or somesuch, and > > slowly stop > > using the original > > "org.gnu.gdb.aarch64.pauth" feature. I can document the requirements for a > > compliant > > pauth_v2. > > What if we leave the original two registers, pauth_[cd]mask, in > org.gnu.gdb.aarch64.pauth > and move the new *_high registers into a different feature? That would > maximize the set > of gdb version for which the original user-only support is functional. If that avoids the gdb crash, sure. But I had the impression from Luis' description of it that that would not help (i.e. that it was the not-used-by-gdb registers in other XML sections like sysregs that resulted in it getting confused about the register number for its internal pauth-related register). thanks -- PMM
Re: [PATCH v3 1/1] hw/riscv: Fix max size limit when put initrd to RAM
On 3/13/23 12:49, Anup Patel wrote:
On Mon, Mar 13, 2023 at 7:49 AM Hang Xu wrote:
Because the starting address of ram is not necessarily 0,
the remaining free space in ram is
ram_size - (start - ram_base) instead of ram_size-start.
Signed-off-by: Hang Xu
What happens in-case a platform has multiple RAM banks ?
In this case the board must specify a contiguous RAM region to be used. It's
not restricted to a single RAM bank - as long as it is contiguous RAM it can
spam multiple RAM banks.
This was done to accomodate boards that has RAM gaps (at this moment the
microchip board) and where we can't use the whole RAM to determine where
to put the initrd/fdt.
Thanks,
Daniel
Regards,
Anup
---
hw/riscv/boot.c| 19 +--
hw/riscv/microchip_pfsoc.c | 5 -
hw/riscv/opentitan.c | 2 +-
hw/riscv/sifive_e.c| 2 +-
hw/riscv/sifive_u.c| 5 -
hw/riscv/spike.c | 5 -
hw/riscv/virt.c| 5 -
include/hw/riscv/boot.h| 2 ++
8 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 52bf8e67de..cfbc376a82 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -173,13 +173,14 @@ target_ulong riscv_load_firmware(const char
*firmware_filename,
exit(1);
}
-static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
+static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry,
+ uint64_t ram_base, uint64_t ram_size)
{
const char *filename = machine->initrd_filename;
-uint64_t mem_size = machine->ram_size;
void *fdt = machine->fdt;
hwaddr start, end;
ssize_t size;
+uint64_t max_initrd;
g_assert(filename != NULL);
@@ -193,12 +194,16 @@ static void riscv_load_initrd(MachineState *machine,
uint64_t kernel_entry)
* So for boards with less than 256MB of RAM we put the initrd
* halfway into RAM, and for boards with 256MB of RAM or more we put
* the initrd at 128MB.
+ * A ram_size == 0, usually from a MemMapEntry[].size element,
+ * means that the RAM block goes all the way to ms->ram_size.
*/
-start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
+ram_size = ram_size ? MIN(machine->ram_size, ram_size) : machine->ram_size;
+start = kernel_entry + MIN(ram_size / 2, 128 * MiB);
+max_initrd = ram_size - (start - ram_base);
-size = load_ramdisk(filename, start, mem_size - start);
+size = load_ramdisk(filename, start, max_initrd);
if (size == -1) {
-size = load_image_targphys(filename, start, mem_size - start);
+size = load_image_targphys(filename, start, max_initrd);
if (size == -1) {
error_report("could not load ramdisk '%s'", filename);
exit(1);
@@ -217,6 +222,8 @@ target_ulong riscv_load_kernel(MachineState *machine,
RISCVHartArrayState *harts,
target_ulong kernel_start_addr,
bool load_initrd,
+ uint64_t ram_base,
+ uint64_t ram_size,
symbol_fn_t sym_cb)
{
const char *kernel_filename = machine->kernel_filename;
@@ -263,7 +270,7 @@ out:
}
if (load_initrd && machine->initrd_filename) {
-riscv_load_initrd(machine, kernel_entry);
+riscv_load_initrd(machine, kernel_entry, ram_base, ram_size);
}
if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) {
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index e81bbd12df..b42d90b89e 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -630,7 +630,10 @@ static void microchip_icicle_kit_machine_init(MachineState
*machine)
firmware_end_addr);
kernel_entry = riscv_load_kernel(machine, >soc.u_cpus,
- kernel_start_addr, true, NULL);
+ kernel_start_addr, true,
+ memmap[MICROCHIP_PFSOC_DRAM_LO].base,
+ memmap[MICROCHIP_PFSOC_DRAM_LO].size,
+ NULL);
/* Compute the fdt load address in dram */
fdt_load_addr =
riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index b06944d382..bb663523d5 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -103,7 +103,7 @@ static void opentitan_board_init(MachineState *machine)
if (machine->kernel_filename) {
riscv_load_kernel(machine, >soc.cpus,
memmap[IBEX_DEV_RAM].base,
- false, NULL);
+ false, 0, 0, NULL);
}
}
diff --git
[PATCH] s390x/gdb: Split s390-virt.xml
TCG emulates ckc, cputm, last_break and prefix, and it's quite useful
to have them during debugging.
So move them into the new s390-virt-tcg.xml file.
pp, pfault_token, pfault_select and pfault_compare are not emulated,
so keep them in s390-virt.xml.
Signed-off-by: Ilya Leoshkevich
---
configs/targets/s390x-linux-user.mak | 2 +-
configs/targets/s390x-softmmu.mak| 2 +-
gdb-xml/s390-virt-tcg.xml| 14 +
gdb-xml/s390-virt.xml| 4 --
target/s390x/gdbstub.c | 82 ++--
5 files changed, 69 insertions(+), 35 deletions(-)
create mode 100644 gdb-xml/s390-virt-tcg.xml
diff --git a/configs/targets/s390x-linux-user.mak
b/configs/targets/s390x-linux-user.mak
index e2978248ede..fb3e2b73be7 100644
--- a/configs/targets/s390x-linux-user.mak
+++ b/configs/targets/s390x-linux-user.mak
@@ -2,4 +2,4 @@ TARGET_ARCH=s390x
TARGET_SYSTBL_ABI=common,64
TARGET_SYSTBL=syscall.tbl
TARGET_BIG_ENDIAN=y
-TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml
gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml
gdb-xml/s390-virt.xml gdb-xml/s390-gs.xml
+TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml
gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml
gdb-xml/s390-virt.xml gdb-xml/s390-virt-tcg.xml gdb-xml/s390-gs.xml
diff --git a/configs/targets/s390x-softmmu.mak
b/configs/targets/s390x-softmmu.mak
index 258b4cf3582..554330d7c85 100644
--- a/configs/targets/s390x-softmmu.mak
+++ b/configs/targets/s390x-softmmu.mak
@@ -1,4 +1,4 @@
TARGET_ARCH=s390x
TARGET_BIG_ENDIAN=y
TARGET_SUPPORTS_MTTCG=y
-TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml
gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml
gdb-xml/s390-virt.xml gdb-xml/s390-gs.xml
+TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml
gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml
gdb-xml/s390-virt.xml gdb-xml/s390-virt-tcg.xml gdb-xml/s390-gs.xml
diff --git a/gdb-xml/s390-virt-tcg.xml b/gdb-xml/s390-virt-tcg.xml
new file mode 100644
index 000..0f77c9b48c6
--- /dev/null
+++ b/gdb-xml/s390-virt-tcg.xml
@@ -0,0 +1,14 @@
+
+
+
+
+
+
+
+
+
+
diff --git a/gdb-xml/s390-virt.xml b/gdb-xml/s390-virt.xml
index e2e9a7ad3cc..a79c0307682 100644
--- a/gdb-xml/s390-virt.xml
+++ b/gdb-xml/s390-virt.xml
@@ -7,10 +7,6 @@
-
-
-
-
diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c
index a5d69d0e0bc..111b695dc85 100644
--- a/target/s390x/gdbstub.c
+++ b/target/s390x/gdbstub.c
@@ -200,61 +200,81 @@ static int cpu_write_c_reg(CPUS390XState *env, uint8_t
*mem_buf, int n)
}
}
-/* the values represent the positions in s390-virt.xml */
-#define S390_VIRT_CKC_REGNUM0
-#define S390_VIRT_CPUTM_REGNUM 1
-#define S390_VIRT_BEA_REGNUM2
-#define S390_VIRT_PREFIX_REGNUM 3
-#define S390_VIRT_PP_REGNUM 4
-#define S390_VIRT_PFT_REGNUM5
-#define S390_VIRT_PFS_REGNUM6
-#define S390_VIRT_PFC_REGNUM7
-/* total number of registers in s390-virt.xml */
-#define S390_NUM_VIRT_REGS 8
+/* the values represent the positions in s390-virt-tcg.xml */
+#define S390_VIRT_TCG_CKC_REGNUM0
+#define S390_VIRT_TCG_CPUTM_REGNUM 1
+#define S390_VIRT_TCG_BEA_REGNUM2
+#define S390_VIRT_TCG_PREFIX_REGNUM 3
+/* total number of registers in s390-virt-tcg.xml */
+#define S390_NUM_VIRT_TCG_REGS 4
-static int cpu_read_virt_reg(CPUS390XState *env, GByteArray *mem_buf, int n)
+static int cpu_read_virt_tcg_reg(CPUS390XState *env, GByteArray *mem_buf, int
n)
{
switch (n) {
-case S390_VIRT_CKC_REGNUM:
+case S390_VIRT_TCG_CKC_REGNUM:
return gdb_get_regl(mem_buf, env->ckc);
-case S390_VIRT_CPUTM_REGNUM:
+case S390_VIRT_TCG_CPUTM_REGNUM:
return gdb_get_regl(mem_buf, env->cputm);
-case S390_VIRT_BEA_REGNUM:
+case S390_VIRT_TCG_BEA_REGNUM:
return gdb_get_regl(mem_buf, env->gbea);
-case S390_VIRT_PREFIX_REGNUM:
+case S390_VIRT_TCG_PREFIX_REGNUM:
return gdb_get_regl(mem_buf, env->psa);
-case S390_VIRT_PP_REGNUM:
-return gdb_get_regl(mem_buf, env->pp);
-case S390_VIRT_PFT_REGNUM:
-return gdb_get_regl(mem_buf, env->pfault_token);
-case S390_VIRT_PFS_REGNUM:
-return gdb_get_regl(mem_buf, env->pfault_select);
-case S390_VIRT_PFC_REGNUM:
-return gdb_get_regl(mem_buf, env->pfault_compare);
default:
return 0;
}
}
-static int cpu_write_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
+static int cpu_write_virt_tcg_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
{
switch (n) {
-case S390_VIRT_CKC_REGNUM:
+case S390_VIRT_TCG_CKC_REGNUM:
env->ckc = ldtul_p(mem_buf);
cpu_synchronize_post_init(env_cpu(env));
return 8;
-case S390_VIRT_CPUTM_REGNUM:
+case S390_VIRT_TCG_CPUTM_REGNUM:
env->cputm = ldtul_p(mem_buf);
cpu_synchronize_post_init(env_cpu(env));
return 8;
-case
Re: [PATCH v2 10/10] contrib/gitdm: add group map for AMD
On 2023-03-10 19:03, Alex Bennée wrote: AMD recently acquired Xilinx and contributors have been transitioning their emails across. > Signed-off-by: Alex Bennée Reviewed-by: Francisco Iglesias Cc: Vikram Garhwal Cc: Francisco Iglesias Cc: Stefano Stabellini Cc: Sai Pavan Boddu Cc: Tong Ho --- contrib/gitdm/domain-map| 1 - contrib/gitdm/group-map-amd | 8 gitdm.config| 1 + 3 files changed, 9 insertions(+), 1 deletion(-) create mode 100644 contrib/gitdm/group-map-amd diff --git a/contrib/gitdm/domain-map b/contrib/gitdm/domain-map index ee0804b6ed..79fd65b077 100644 --- a/contrib/gitdm/domain-map +++ b/contrib/gitdm/domain-map @@ -50,6 +50,5 @@ virtuozzo.com Virtuozzo vrull.euVRULL wdc.com Western Digital windriver.com Wind River -xilinx.com Xilinx yadro.com YADRO yandex-team.ru Yandex diff --git a/contrib/gitdm/group-map-amd b/contrib/gitdm/group-map-amd new file mode 100644 index 00..bda4239a8a --- /dev/null +++ b/contrib/gitdm/group-map-amd @@ -0,0 +1,8 @@ +# AMD acquired Xilinx and contributors have been slowly updating emails + +edgar.igles...@xilinx.com +fnu.vik...@xilinx.com +francisco.igles...@xilinx.com +sai.pavan.bo...@xilinx.com +stefano.stabell...@xilinx.com +tong...@xilinx.com diff --git a/gitdm.config b/gitdm.config index 6908ddbd19..c9d961dd23 100644 --- a/gitdm.config +++ b/gitdm.config @@ -32,6 +32,7 @@ EmailMap contrib/gitdm/domain-map # GroupMap contrib/gitdm/group-map-alibaba Alibaba +GroupMap contrib/gitdm/group-map-amd AMD GroupMap contrib/gitdm/group-map-cadence Cadence Design Systems GroupMap contrib/gitdm/group-map-codeweavers CodeWeavers GroupMap contrib/gitdm/group-map-facebook Facebook
Re: [PATCH] MAINTAINERS: Mark the Nios II CPU as orphan
+CodeSourcery folks On 13/3/23 19:33, Thomas Huth wrote: Marek and Chris haven't been active for Nios II since years (the last time seems to have been in 2017), and we've got unhandled severe Nios II bug tickets in the bug tracker since a long time, so to avoid wrong expectations of people who are looking at the MAINTAINERS file, it's maybe best to mark the Nios II entry as orphan nowadays. Suggested-by: Richard Henderson Signed-off-by: Thomas Huth --- Suggested by Richard here: https://lore.kernel.org/qemu-devel/cb2e92b7-40bb-4975-290d-6321c5574...@linaro.org/ And bugs like this sound like the linux-user target is in a bad shape, too: https://gitlab.com/qemu-project/qemu/-/issues/261 See also: https://bugs.launchpad.net/qemu/+bug/1791796 (comment 3) ... nobody tried to fix nios2 linux-user in years, maybe we should deprecate it? MAINTAINERS | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 95c957d587..9780430626 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -257,9 +257,9 @@ F: docs/system/cpu-models-mips.rst.inc F: tests/tcg/mips/ NiosII TCG CPUs -M: Chris Wulff -M: Marek Vasut -S: Maintained +R: Chris Wulff +R: Marek Vasut +S: Orphan F: target/nios2/ F: hw/nios2/ F: disas/nios2.c Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH v7 0/6] memory: prevent dma-reentracy issues
On 13/3/23 17:18, Thomas Huth wrote: https://gitlab.com/thuth/qemu/-/jobs/3920337136#L307 ... but I think that was pre-existing and was caused by one of Philippe's reworks, hopefully to be fixed soon ... Phillipe? Jiaxun fixed this on little-endian hosts, but this is still failing on big-endian ones so I was a bit reluctant until figuring out the full fix but since this helps CI...
[PATCH qemu v2] linux-user: Emulate /proc/cpuinfo output for riscv
From: Afonso Bordado
RISC-V does not expose all extensions via hwcaps, thus some userspace
applications may want to query these via /proc/cpuinfo.
Currently when querying this file the host's file is shown instead
which is slightly confusing. Emulate a basic /proc/cpuinfo file
with mmu info and an ISA string.
Changes from V1:
- Call `g_free` on ISA string.
- Use `riscv_cpu_cfg` API.
- Query `cpu_env->xl` to check for RV32.
Signed-off-by: Afonso Bordado
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
Reviewed-by: Laurent Vivier
---
linux-user/syscall.c | 34 +--
tests/tcg/riscv64/Makefile.target | 1 +
tests/tcg/riscv64/cpuinfo.c | 30 +++
3 files changed, 63 insertions(+), 2 deletions(-)
create mode 100644 tests/tcg/riscv64/cpuinfo.c
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 24cea6fb6a..0388f8b0b0 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -8230,7 +8230,8 @@ void target_exception_dump(CPUArchState *env, const char
*fmt, int code)
}
#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN || \
-defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA)
+defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA) || \
+defined(TARGET_RISCV)
static int is_proc(const char *filename, const char *entry)
{
return strcmp(filename, entry) == 0;
@@ -8308,6 +8309,35 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd)
}
#endif
+#if defined(TARGET_RISCV)
+static int open_cpuinfo(CPUArchState *cpu_env, int fd)
+{
+int i;
+int num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
+RISCVCPU *cpu = env_archcpu(cpu_env);
+const RISCVCPUConfig *cfg = riscv_cpu_cfg((CPURISCVState *) cpu_env);
+char *isa_string = riscv_isa_string(cpu);
+const char *mmu;
+
+if (cfg->mmu) {
+mmu = (cpu_env->xl == MXL_RV32) ? "sv32" : "sv48";
+} else {
+mmu = "none";
+}
+
+for (i = 0; i < num_cpus; i++) {
+dprintf(fd, "processor\t: %d\n", i);
+dprintf(fd, "hart\t\t: %d\n", i);
+dprintf(fd, "isa\t\t: %s\n", isa_string);
+dprintf(fd, "mmu\t\t: %s\n", mmu);
+dprintf(fd, "uarch\t\t: qemu\n\n");
+}
+
+g_free(isa_string);
+return 0;
+}
+#endif
+
#if defined(TARGET_M68K)
static int open_hardware(CPUArchState *cpu_env, int fd)
{
@@ -8332,7 +8362,7 @@ static int do_openat(CPUArchState *cpu_env, int dirfd,
const char *pathname, int
#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
{ "/proc/net/route", open_net_route, is_proc },
#endif
-#if defined(TARGET_SPARC) || defined(TARGET_HPPA)
+#if defined(TARGET_SPARC) || defined(TARGET_HPPA) || defined(TARGET_RISCV)
{ "/proc/cpuinfo", open_cpuinfo, is_proc },
#endif
#if defined(TARGET_M68K)
diff --git a/tests/tcg/riscv64/Makefile.target
b/tests/tcg/riscv64/Makefile.target
index cc3ed65ffd..df93a2ce1f 100644
--- a/tests/tcg/riscv64/Makefile.target
+++ b/tests/tcg/riscv64/Makefile.target
@@ -4,6 +4,7 @@
VPATH += $(SRC_PATH)/tests/tcg/riscv64
TESTS += test-div
TESTS += noexec
+TESTS += cpuinfo
# Disable compressed instructions for test-noc
TESTS += test-noc
diff --git a/tests/tcg/riscv64/cpuinfo.c b/tests/tcg/riscv64/cpuinfo.c
new file mode 100644
index 00..296abd0a8c
--- /dev/null
+++ b/tests/tcg/riscv64/cpuinfo.c
@@ -0,0 +1,30 @@
+#include
+#include
+#include
+#include
+
+#define BUFFER_SIZE 1024
+
+int main(void)
+{
+char buffer[BUFFER_SIZE];
+FILE *fp = fopen("/proc/cpuinfo", "r");
+assert(fp != NULL);
+
+while (fgets(buffer, BUFFER_SIZE, fp) != NULL) {
+if (strstr(buffer, "processor") != NULL) {
+assert(strstr(buffer, "processor\t: ") == buffer);
+} else if (strstr(buffer, "hart") != NULL) {
+assert(strstr(buffer, "hart\t\t: ") == buffer);
+} else if (strstr(buffer, "isa") != NULL) {
+assert(strcmp(buffer, "isa\t\t: rv64imafdc_zicsr_zifencei\n") ==
0);
+} else if (strstr(buffer, "mmu") != NULL) {
+assert(strcmp(buffer, "mmu\t\t: sv48\n") == 0);
+} else if (strstr(buffer, "uarch") != NULL) {
+assert(strcmp(buffer, "uarch\t\t: qemu\n") == 0);
+}
+}
+
+fclose(fp);
+return 0;
+}
--
2.34.7
Re: [PATCH v9 05/10] target/arm: gdbstub: Guard pauth code with CONFIG_TCG
On 3/13/23 08:10, Fabiano Rosas wrote: We currently don't have the reading of pauth regs implemented for KVM so wrap the pauth registration with CONFIG_TCG. This avoids the build error when using --disable-tcg: libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub64.c.o: in function `aarch64_gdb_get_pauth_reg': ../target/arm/gdbstub64.c:233: undefined reference to `pauth_ptr_mask' Signed-off-by: Fabiano Rosas --- target/arm/gdbstub.c | 4 +++- target/arm/gdbstub64.c | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~
Re: [PATCH] DO-NOT-MERGE: pipewire sample code
Am 13.03.23 um 13:28 schrieb Dorinda Bassey:
Hi Volker,
Thanks for the patch, I've tested the patch and it works. I don't hear
the choppy audio with this option "qemu-system-x86_64 -device
ich9-intel-hda -device hda-duplex,audiodev=audio0 -audiodev
pipewire,id=audio0,out.frequency=96000,in.frequency=96000 "
I don't understand how the req == 0 case can work at all.
how this works is that b->requested could be zero when no suggestion
is provided. For playback streams, this field contains the suggested
amount of data to provide. hence the reason for this check.
Hi Dorinda,
there has to be a control mechanism that ensures that our write rate on
average is exactly the frame rate that the down stream audio device
writes to the DAC. My question was how can this work if we always write
4096 frames.
The answer is, that after a 4096 frames write, the callback is delayed
by 4096 frames / 44100 frames/s = 93ms. This ensures that our write rate
is exactly 44100 frames/s.
This means a fixed 4096 frames write is wrong for the req == 0 case. We
have to write 75% of timer-period frames.
If you want to test this yourself, just ignore req and assume it's 0.
With best regards,
Volker
I suggest to use the same option names as the pulseaudio backend.
out.latency is the effective Pipewire buffer size.
Ack.
Thanks,
Dorinda.
On Sat, Mar 11, 2023 at 5:19 PM Volker Rümelin
wrote:
> Based-on:<20230306171020.381116-1-dbas...@redhat.com>
> ([PATCH v7] audio/pwaudio.c: Add Pipewire audio backend for QEMU)
>
> This is sample code for the review of the pipewire backed. The
> code actually works.
>
> An email with explanations for the changes will follow.
>
> Signed-off-by: Volker Rümelin
> ---
> audio/pwaudio.c | 67
+
> qapi/audio.json | 10 +++-
> 2 files changed, 49 insertions(+), 28 deletions(-)
>
> diff --git a/audio/pwaudio.c b/audio/pwaudio.c
> index d357761152..8e2a38938f 100644
> --- a/audio/pwaudio.c
> +++ b/audio/pwaudio.c
> @@ -23,7 +23,6 @@
> #define AUDIO_CAP "pipewire"
> #define RINGBUFFER_SIZE (1u << 22)
> #define RINGBUFFER_MASK (RINGBUFFER_SIZE - 1)
> -#define BUFFER_SAMPLES 512
>
> #include "audio_int.h"
>
> @@ -48,6 +47,7 @@ typedef struct PWVoice {
> struct pw_stream *stream;
> struct spa_hook stream_listener;
> struct spa_audio_info_raw info;
> + uint32_t highwater_mark;
> uint32_t frame_size;
> struct spa_ringbuffer ring;
> uint8_t buffer[RINGBUFFER_SIZE];
> @@ -82,7 +82,7 @@ playback_on_process(void *data)
> void *p;
> struct pw_buffer *b;
> struct spa_buffer *buf;
> - uint32_t n_frames, req, index, n_bytes;
> + uint32_t req, index, n_bytes;
> int32_t avail;
>
> if (!v->stream) {
> @@ -105,8 +105,7 @@ playback_on_process(void *data)
> if (req == 0) {
> req = 4096 * v->frame_size;
> }
I don't understand how the req == 0 case can work at all. The
downstream
audio device is the thinnest point in the playback stream. We can't
write more audio frames than the audio device will consume.
[PULL v2 12/18] ui/shader: fix #version directive must occur on first line
From: Marc-André Lureau ANGLE fails to compile shaders otherwise. Signed-off-by: Marc-André Lureau Reviewed-by: Daniel P. Berrangé --- ui/shader/texture-blit-flip.vert | 1 - ui/shader/texture-blit.frag | 1 - ui/shader/texture-blit.vert | 1 - 3 files changed, 3 deletions(-) diff --git a/ui/shader/texture-blit-flip.vert b/ui/shader/texture-blit-flip.vert index ba081fa5a6..f7a448d229 100644 --- a/ui/shader/texture-blit-flip.vert +++ b/ui/shader/texture-blit-flip.vert @@ -1,4 +1,3 @@ - #version 300 es in vec2 in_position; diff --git a/ui/shader/texture-blit.frag b/ui/shader/texture-blit.frag index bfa202c22b..8ed95a46b6 100644 --- a/ui/shader/texture-blit.frag +++ b/ui/shader/texture-blit.frag @@ -1,4 +1,3 @@ - #version 300 es uniform sampler2D image; diff --git a/ui/shader/texture-blit.vert b/ui/shader/texture-blit.vert index 6fe2744d68..fb48d70665 100644 --- a/ui/shader/texture-blit.vert +++ b/ui/shader/texture-blit.vert @@ -1,4 +1,3 @@ - #version 300 es in vec2 in_position; -- 2.39.2
[PULL v2 13/18] ui/egl: print EGL error, helping debugging
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
---
ui/egl-helpers.c | 54 ++--
1 file changed, 48 insertions(+), 6 deletions(-)
diff --git a/ui/egl-helpers.c b/ui/egl-helpers.c
index 3a88245b67..b11837415b 100644
--- a/ui/egl-helpers.c
+++ b/ui/egl-helpers.c
@@ -26,6 +26,48 @@ DisplayGLMode qemu_egl_mode;
/* -- */
+#if defined(CONFIG_X11) || defined(CONFIG_GBM)
+static const char *egl_get_error_string(void)
+{
+EGLint error = eglGetError();
+
+switch (error) {
+case EGL_SUCCESS:
+return "EGL_SUCCESS";
+case EGL_NOT_INITIALIZED:
+return "EGL_NOT_INITIALIZED";
+case EGL_BAD_ACCESS:
+return "EGL_BAD_ACCESS";
+case EGL_BAD_ALLOC:
+return "EGL_BAD_ALLOC";
+case EGL_BAD_ATTRIBUTE:
+return "EGL_BAD_ATTRIBUTE";
+case EGL_BAD_CONTEXT:
+return "EGL_BAD_CONTEXT";
+case EGL_BAD_CONFIG:
+return "EGL_BAD_CONFIG";
+case EGL_BAD_CURRENT_SURFACE:
+return "EGL_BAD_CURRENT_SURFACE";
+case EGL_BAD_DISPLAY:
+return "EGL_BAD_DISPLAY";
+case EGL_BAD_SURFACE:
+return "EGL_BAD_SURFACE";
+case EGL_BAD_MATCH:
+return "EGL_BAD_MATCH";
+case EGL_BAD_PARAMETER:
+return "EGL_BAD_PARAMETER";
+case EGL_BAD_NATIVE_PIXMAP:
+return "EGL_BAD_NATIVE_PIXMAP";
+case EGL_BAD_NATIVE_WINDOW:
+return "EGL_BAD_NATIVE_WINDOW";
+case EGL_CONTEXT_LOST:
+return "EGL_CONTEXT_LOST";
+default:
+return "Unknown EGL error";
+}
+}
+#endif
+
static void egl_fb_delete_texture(egl_fb *fb)
{
if (!fb->delete_texture) {
@@ -438,20 +480,20 @@ static int qemu_egl_init_dpy(EGLNativeDisplayType dpy,
qemu_egl_display = qemu_egl_get_display(dpy, platform);
if (qemu_egl_display == EGL_NO_DISPLAY) {
-error_report("egl: eglGetDisplay failed");
+error_report("egl: eglGetDisplay failed: %s", egl_get_error_string());
return -1;
}
b = eglInitialize(qemu_egl_display, , );
if (b == EGL_FALSE) {
-error_report("egl: eglInitialize failed");
+error_report("egl: eglInitialize failed: %s", egl_get_error_string());
return -1;
}
b = eglBindAPI(gles ? EGL_OPENGL_ES_API : EGL_OPENGL_API);
if (b == EGL_FALSE) {
-error_report("egl: eglBindAPI failed (%s mode)",
- gles ? "gles" : "core");
+error_report("egl: eglBindAPI failed (%s mode): %s",
+ gles ? "gles" : "core", egl_get_error_string());
return -1;
}
@@ -459,8 +501,8 @@ static int qemu_egl_init_dpy(EGLNativeDisplayType dpy,
gles ? conf_att_gles : conf_att_core,
_egl_config, 1, );
if (b == EGL_FALSE || n != 1) {
-error_report("egl: eglChooseConfig failed (%s mode)",
- gles ? "gles" : "core");
+error_report("egl: eglChooseConfig failed (%s mode): %s",
+ gles ? "gles" : "core", egl_get_error_string());
return -1;
}
--
2.39.2
[PULL v2 03/18] audio/dbus: there are no sender for p2p mode
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
audio/audio_int.h | 2 +-
audio/dbusaudio.c | 7 +--
ui/dbus.c | 2 +-
3 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/audio/audio_int.h b/audio/audio_int.h
index d51d63f08d..e57ff50155 100644
--- a/audio/audio_int.h
+++ b/audio/audio_int.h
@@ -143,7 +143,7 @@ struct audio_driver {
void *(*init) (Audiodev *);
void (*fini) (void *);
#ifdef CONFIG_GIO
-void (*set_dbus_server) (AudioState *s, GDBusObjectManagerServer *manager);
+void (*set_dbus_server) (AudioState *s, GDBusObjectManagerServer *manager,
bool p2p);
#endif
struct audio_pcm_ops *pcm_ops;
int can_be_default;
diff --git a/audio/dbusaudio.c b/audio/dbusaudio.c
index 722df0355e..fece74f78c 100644
--- a/audio/dbusaudio.c
+++ b/audio/dbusaudio.c
@@ -43,6 +43,7 @@
typedef struct DBusAudio {
GDBusObjectManagerServer *server;
+bool p2p;
GDBusObjectSkeleton *audio;
QemuDBusDisplay1Audio *iface;
GHashTable *out_listeners;
@@ -448,7 +449,8 @@ dbus_audio_register_listener(AudioState *s,
bool out)
{
DBusAudio *da = s->drv_opaque;
-const char *sender = g_dbus_method_invocation_get_sender(invocation);
+const char *sender =
+da->p2p ? "p2p" : g_dbus_method_invocation_get_sender(invocation);
g_autoptr(GDBusConnection) listener_conn = NULL;
g_autoptr(GError) err = NULL;
g_autoptr(GSocket) socket = NULL;
@@ -591,7 +593,7 @@ dbus_audio_register_in_listener(AudioState *s,
}
static void
-dbus_audio_set_server(AudioState *s, GDBusObjectManagerServer *server)
+dbus_audio_set_server(AudioState *s, GDBusObjectManagerServer *server, bool
p2p)
{
DBusAudio *da = s->drv_opaque;
@@ -599,6 +601,7 @@ dbus_audio_set_server(AudioState *s,
GDBusObjectManagerServer *server)
g_assert(!da->server);
da->server = g_object_ref(server);
+da->p2p = p2p;
da->audio = g_dbus_object_skeleton_new(DBUS_DISPLAY1_AUDIO_PATH);
da->iface = qemu_dbus_display1_audio_skeleton_new();
diff --git a/ui/dbus.c b/ui/dbus.c
index f2dcba03d0..f529928f0b 100644
--- a/ui/dbus.c
+++ b/ui/dbus.c
@@ -220,7 +220,7 @@ dbus_display_complete(UserCreatable *uc, Error **errp)
dd->audiodev);
return;
}
-audio_state->drv->set_dbus_server(audio_state, dd->server);
+audio_state->drv->set_dbus_server(audio_state, dd->server, dd->p2p);
}
consoles = g_array_new(FALSE, FALSE, sizeof(guint32));
--
2.39.2
[PULL v2 14/18] ui/sdl: add QEMU_ENABLE_SDL_LOGGING setting/environment
From: Marc-André Lureau
Enable SDL logging when QEMU_ENABLE_SDL_LOGGING variable is set, as
suggested by Sam Lantinga, upstream SDL maintainer.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
ui/sdl2.c | 4
1 file changed, 4 insertions(+)
diff --git a/ui/sdl2.c b/ui/sdl2.c
index 137f7ab57f..221cdced60 100644
--- a/ui/sdl2.c
+++ b/ui/sdl2.c
@@ -843,6 +843,10 @@ static void sdl2_display_init(DisplayState *ds,
DisplayOptions *o)
}
#endif
+if (SDL_GetHintBoolean("QEMU_ENABLE_SDL_LOGGING", SDL_FALSE)) {
+SDL_LogSetAllPriority(SDL_LOG_PRIORITY_VERBOSE);
+}
+
if (SDL_Init(SDL_INIT_VIDEO)) {
fprintf(stderr, "Could not initialize SDL(%s) - exiting\n",
SDL_GetError());
--
2.39.2
[PULL v2 17/18] ui/dbus: do not require opengl & gbm
From: Marc-André Lureau
Allow to build & use the DBus display without 3d/GPU acceleration support.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
meson.build | 4 ++--
ui/dbus-listener.c | 15 +--
ui/dbus.c | 8
tests/qtest/meson.build | 2 +-
ui/meson.build | 4 ++--
5 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/meson.build b/meson.build
index 6bcab8bf0d..29f8644d6d 100644
--- a/meson.build
+++ b/meson.build
@@ -1746,8 +1746,8 @@ dbus_display = get_option('dbus_display') \
error_message: '-display dbus requires glib>=2.64') \
.require(gdbus_codegen.found(),
error_message: gdbus_codegen_error.format('-display dbus')) \
- .require(opengl.found() and gbm.found(),
- error_message: '-display dbus requires epoxy/egl and gbm') \
+ .require(targetos != 'windows',
+ error_message: '-display dbus is not available on Windows') \
.allowed()
have_virtfs = get_option('virtfs') \
diff --git a/ui/dbus-listener.c b/ui/dbus-listener.c
index 2e87ed7e9a..85692f1b27 100644
--- a/ui/dbus-listener.c
+++ b/ui/dbus-listener.c
@@ -27,9 +27,11 @@
#include "dbus.h"
#include
+#ifdef CONFIG_OPENGL
#include "ui/shader.h"
#include "ui/egl-helpers.h"
#include "ui/egl-context.h"
+#endif
#include "trace.h"
struct _DBusDisplayListener {
@@ -48,6 +50,7 @@ struct _DBusDisplayListener {
G_DEFINE_TYPE(DBusDisplayListener, dbus_display_listener, G_TYPE_OBJECT)
+#ifdef CONFIG_OPENGL
static void dbus_update_gl_cb(GObject *source_object,
GAsyncResult *res,
gpointer user_data)
@@ -229,12 +232,14 @@ static void dbus_gl_refresh(DisplayChangeListener *dcl)
ddl->gl_updates = 0;
}
}
+#endif
static void dbus_refresh(DisplayChangeListener *dcl)
{
graphic_hw_update(dcl->con);
}
+#ifdef CONFIG_OPENGL
static void dbus_gl_gfx_update(DisplayChangeListener *dcl,
int x, int y, int w, int h)
{
@@ -242,6 +247,7 @@ static void dbus_gl_gfx_update(DisplayChangeListener *dcl,
ddl->gl_updates++;
}
+#endif
static void dbus_gfx_update(DisplayChangeListener *dcl,
int x, int y, int w, int h)
@@ -296,6 +302,7 @@ static void dbus_gfx_update(DisplayChangeListener *dcl,
DBUS_DEFAULT_TIMEOUT, NULL, NULL, NULL);
}
+#ifdef CONFIG_OPENGL
static void dbus_gl_gfx_switch(DisplayChangeListener *dcl,
struct DisplaySurface *new_surface)
{
@@ -311,6 +318,7 @@ static void dbus_gl_gfx_switch(DisplayChangeListener *dcl,
width, height, 0, 0, width, height);
}
}
+#endif
static void dbus_gfx_switch(DisplayChangeListener *dcl,
struct DisplaySurface *new_surface)
@@ -361,6 +369,7 @@ static void dbus_cursor_define(DisplayChangeListener *dcl,
NULL);
}
+#ifdef CONFIG_OPENGL
const DisplayChangeListenerOps dbus_gl_dcl_ops = {
.dpy_name= "dbus-gl",
.dpy_gfx_update = dbus_gl_gfx_update,
@@ -378,6 +387,7 @@ const DisplayChangeListenerOps dbus_gl_dcl_ops = {
.dpy_gl_release_dmabuf = dbus_release_dmabuf,
.dpy_gl_update = dbus_scanout_update,
};
+#endif
const DisplayChangeListenerOps dbus_dcl_ops = {
.dpy_name= "dbus",
@@ -406,11 +416,12 @@ dbus_display_listener_constructed(GObject *object)
{
DBusDisplayListener *ddl = DBUS_DISPLAY_LISTENER(object);
+ddl->dcl.ops = _dcl_ops;
+#ifdef CONFIG_OPENGL
if (display_opengl) {
ddl->dcl.ops = _gl_dcl_ops;
-} else {
-ddl->dcl.ops = _dcl_ops;
}
+#endif
G_OBJECT_CLASS(dbus_display_listener_parent_class)->constructed(object);
}
diff --git a/ui/dbus.c b/ui/dbus.c
index ebf03bd84d..904f5a0a6d 100644
--- a/ui/dbus.c
+++ b/ui/dbus.c
@@ -30,8 +30,10 @@
#include "qom/object_interfaces.h"
#include "sysemu/sysemu.h"
#include "ui/dbus-module.h"
+#ifdef CONFIG_OPENGL
#include "ui/egl-helpers.h"
#include "ui/egl-context.h"
+#endif
#include "audio/audio.h"
#include "audio/audio_int.h"
#include "qapi/error.h"
@@ -41,6 +43,7 @@
static DBusDisplay *dbus_display;
+#ifdef CONFIG_OPENGL
static QEMUGLContext dbus_create_context(DisplayGLCtx *dgc,
QEMUGLParams *params)
{
@@ -84,6 +87,7 @@ static const DisplayGLCtxOps dbus_gl_ops = {
.dpy_gl_ctx_destroy_texture = dbus_destroy_texture,
.dpy_gl_ctx_update_texture = dbus_update_texture,
};
+#endif
static NotifierList dbus_display_notifiers =
NOTIFIER_LIST_INITIALIZER(dbus_display_notifiers);
@@ -112,10 +116,12 @@ dbus_display_init(Object *o)
DBusDisplay *dd = DBUS_DISPLAY(o);
g_autoptr(GDBusObjectSkeleton) vm = NULL;
+#ifdef CONFIG_OPENGL
dd->glctx.ops = _gl_ops;
if (display_opengl) {
dd->glctx.gls = qemu_gl_init_shader();
}
+#endif
[PULL v2 10/18] ui: set cursor position upon listener registration
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
ui/console.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/ui/console.c b/ui/console.c
index 35f8274aab..f3783021e5 100644
--- a/ui/console.c
+++ b/ui/console.c
@@ -95,6 +95,7 @@ struct QemuConsole {
QemuUIInfo ui_info;
QEMUTimer *ui_timer;
QEMUCursor *cursor;
+int cursor_x, cursor_y, cursor_on;
const GraphicHwOps *hw_ops;
void *hw;
@@ -1665,6 +1666,9 @@ void register_displaychangelistener(DisplayChangeListener
*dcl)
if (con && con->cursor && dcl->ops->dpy_cursor_define) {
dcl->ops->dpy_cursor_define(dcl, con->cursor);
}
+if (con && dcl->ops->dpy_mouse_set) {
+dcl->ops->dpy_mouse_set(dcl, con->cursor_x, con->cursor_y,
con->cursor_on);
+}
text_console_update_cursor(NULL);
}
@@ -1909,6 +1913,9 @@ void dpy_mouse_set(QemuConsole *con, int x, int y, int on)
DisplayState *s = con->ds;
DisplayChangeListener *dcl;
+con->cursor_x = x;
+con->cursor_y = y;
+con->cursor_on = on;
if (!qemu_console_is_visible(con)) {
return;
}
--
2.39.2
[PULL v2 11/18] ui/sdl: get the GL context from the window
From: Marc-André Lureau
There is no guarantee to have a current GL context here. The current
code seems to rely on the renderer using a GL backend, and to set a
current GL context. But this is not always the case, for example if the
renderer backend is DirectX.
This change is enough to fix using virgl with sdl2 on win32, on my setup.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
ui/sdl2.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/ui/sdl2.c b/ui/sdl2.c
index 8cb77416af..137f7ab57f 100644
--- a/ui/sdl2.c
+++ b/ui/sdl2.c
@@ -101,7 +101,7 @@ void sdl2_window_create(struct sdl2_console *scon)
flags);
scon->real_renderer = SDL_CreateRenderer(scon->real_window, -1, 0);
if (scon->opengl) {
-scon->winctx = SDL_GL_GetCurrentContext();
+scon->winctx = SDL_GL_CreateContext(scon->real_window);
}
sdl_update_caption(scon);
}
@@ -112,6 +112,8 @@ void sdl2_window_destroy(struct sdl2_console *scon)
return;
}
+SDL_GL_DeleteContext(scon->winctx);
+scon->winctx = NULL;
SDL_DestroyRenderer(scon->real_renderer);
scon->real_renderer = NULL;
SDL_DestroyWindow(scon->real_window);
--
2.39.2
[PULL v2 00/18] Display patches
From: Marc-André Lureau
The following changes since commit 284c52eec2d0a1b9c47f06c3eee46762c5fc0915:
Merge tag 'win-socket-pull-request' of
https://gitlab.com/marcandre.lureau/qemu into staging (2023-03-13 13:44:17
+)
are available in the Git repository at:
https://gitlab.com/marcandre.lureau/qemu.git tags/display-pull-request
for you to fetch changes up to 4814d3cbf9f921b6f60a384b4aa3fc3151fdd3a7:
ui/dbus: restrict opengl to gbm-enabled config (2023-03-13 23:48:45 +0400)
ui: dbus & misc fixes
v2:
- fix crash spotted by avocado VNC test
Marc-André Lureau (18):
ui/dbus: initialize cursor_fb
ui/dbus: unregister clipboard on connection close
audio/dbus: there are no sender for p2p mode
ui/dbus: set mouse is-absolute during console creation
meson: ensure dbus-display generated code is built before other units
ui: rename cursor_{put->unref}
ui: rename cursor_{get->ref}, return it
ui: keep current cursor with QemuConsole
ui: set cursor upon listener registration
ui: set cursor position upon listener registration
ui/sdl: get the GL context from the window
ui/shader: fix #version directive must occur on first line
ui/egl: print EGL error, helping debugging
ui/sdl: add QEMU_ENABLE_SDL_LOGGING setting/environment
ui/sdl: try to instantiate the matching opengl renderer
ui: introduce egl_init()
ui/dbus: do not require opengl & gbm
ui/dbus: restrict opengl to gbm-enabled config
meson.build | 4 +-
audio/audio_int.h| 2 +-
include/ui/console.h | 5 +-
include/ui/egl-helpers.h | 4 ++
ui/vnc.h | 1 -
audio/dbusaudio.c| 7 ++-
hw/display/qxl-render.c | 4 +-
hw/display/qxl.c | 2 +-
hw/display/vmware_vga.c | 4 +-
ui/console.c | 18
ui/cursor.c | 5 +-
ui/dbus-clipboard.c | 18 +++-
ui/dbus-console.c| 13 --
ui/dbus-listener.c | 22 ++---
ui/dbus.c| 29
ui/egl-headless.c| 16 +++
ui/egl-helpers.c | 78 +---
ui/sdl2.c| 24 +-
ui/spice-core.c | 7 +--
ui/spice-display.c | 8 ++--
ui/vnc.c | 8 +---
tests/qtest/meson.build | 2 +-
ui/meson.build | 6 ++-
ui/shader/texture-blit-flip.vert | 1 -
ui/shader/texture-blit.frag | 1 -
ui/shader/texture-blit.vert | 1 -
26 files changed, 210 insertions(+), 80 deletions(-)
--
2.39.2
[PULL v2 16/18] ui: introduce egl_init()
From: Marc-André Lureau
Future patches will introduce EGL support on win32 (too late for 8.0
though). Having a common place for EGL initialization and error handling
will make it simpler.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
include/ui/egl-helpers.h | 2 ++
ui/dbus.c| 7 +--
ui/egl-headless.c| 16
ui/egl-helpers.c | 24
ui/spice-core.c | 7 +--
5 files changed, 36 insertions(+), 20 deletions(-)
diff --git a/include/ui/egl-helpers.h b/include/ui/egl-helpers.h
index c92dd90e33..53d953ddf4 100644
--- a/include/ui/egl-helpers.h
+++ b/include/ui/egl-helpers.h
@@ -65,4 +65,6 @@ int qemu_egl_init_dpy_mesa(EGLNativeDisplayType dpy,
DisplayGLMode mode);
EGLContext qemu_egl_init_ctx(void);
bool qemu_egl_has_dmabuf(void);
+bool egl_init(const char *rendernode, DisplayGLMode mode, Error **errp);
+
#endif /* EGL_HELPERS_H */
diff --git a/ui/dbus.c b/ui/dbus.c
index f529928f0b..ebf03bd84d 100644
--- a/ui/dbus.c
+++ b/ui/dbus.c
@@ -451,12 +451,7 @@ early_dbus_init(DisplayOptions *opts)
DisplayGLMode mode = opts->has_gl ? opts->gl : DISPLAYGL_MODE_OFF;
if (mode != DISPLAYGL_MODE_OFF) {
-if (egl_rendernode_init(opts->u.dbus.rendernode, mode) < 0) {
-error_report("dbus: render node init failed");
-exit(1);
-}
-
-display_opengl = 1;
+egl_init(opts->u.dbus.rendernode, mode, _fatal);
}
type_register(_vc_type_info);
diff --git a/ui/egl-headless.c b/ui/egl-headless.c
index ae07e91302..ef70e6a18e 100644
--- a/ui/egl-headless.c
+++ b/ui/egl-headless.c
@@ -1,7 +1,7 @@
#include "qemu/osdep.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
-#include "sysemu/sysemu.h"
+#include "qapi/error.h"
#include "ui/console.h"
#include "ui/egl-helpers.h"
#include "ui/egl-context.h"
@@ -191,21 +191,21 @@ static const DisplayGLCtxOps eglctx_ops = {
static void early_egl_headless_init(DisplayOptions *opts)
{
-display_opengl = 1;
+DisplayGLMode mode = DISPLAYGL_MODE_ON;
+
+if (opts->has_gl) {
+mode = opts->gl;
+}
+
+egl_init(opts->u.egl_headless.rendernode, mode, _fatal);
}
static void egl_headless_init(DisplayState *ds, DisplayOptions *opts)
{
-DisplayGLMode mode = opts->has_gl ? opts->gl : DISPLAYGL_MODE_ON;
QemuConsole *con;
egl_dpy *edpy;
int idx;
-if (egl_rendernode_init(opts->u.egl_headless.rendernode, mode) < 0) {
-error_report("egl: render node init failed");
-exit(1);
-}
-
for (idx = 0;; idx++) {
DisplayGLCtx *ctx;
diff --git a/ui/egl-helpers.c b/ui/egl-helpers.c
index b11837415b..4203163ace 100644
--- a/ui/egl-helpers.c
+++ b/ui/egl-helpers.c
@@ -19,6 +19,8 @@
#include "qemu/error-report.h"
#include "ui/console.h"
#include "ui/egl-helpers.h"
+#include "sysemu/sysemu.h"
+#include "qapi/error.h"
EGLDisplay *qemu_egl_display;
EGLConfig qemu_egl_config;
@@ -569,3 +571,25 @@ EGLContext qemu_egl_init_ctx(void)
return ectx;
}
+
+bool egl_init(const char *rendernode, DisplayGLMode mode, Error **errp)
+{
+ERRP_GUARD();
+
+if (mode == DISPLAYGL_MODE_OFF) {
+error_setg(errp, "egl: turning off GL doesn't make sense");
+return false;
+}
+
+#ifdef CONFIG_GBM
+if (egl_rendernode_init(rendernode, mode) < 0) {
+error_setg(errp, "egl: render node init failed");
+return false;
+}
+display_opengl = 1;
+return true;
+#else
+error_setg(errp, "egl: not available on this platform");
+return false;
+#endif
+}
diff --git a/ui/spice-core.c b/ui/spice-core.c
index 76f7c2bc3d..b05c830086 100644
--- a/ui/spice-core.c
+++ b/ui/spice-core.c
@@ -820,12 +820,7 @@ static void qemu_spice_init(void)
"incompatible with -spice port/tls-port");
exit(1);
}
-if (egl_rendernode_init(qemu_opt_get(opts, "rendernode"),
-DISPLAYGL_MODE_ON) != 0) {
-error_report("Failed to initialize EGL render node for SPICE GL");
-exit(1);
-}
-display_opengl = 1;
+egl_init(qemu_opt_get(opts, "rendernode"), DISPLAYGL_MODE_ON,
_fatal);
spice_opengl = 1;
}
#endif
--
2.39.2
[PULL v2 15/18] ui/sdl: try to instantiate the matching opengl renderer
From: Marc-André Lureau
-display sdl,gl=es didn't actually use OpenGL ES.
Using OpenGL ES allows to use ANGLE, which works generally better than
Windows/OEM OpenGL driver.
(note: users can still bypass the QEMU choice with SDL_RENDER_DRIVER
environment variable)
(note: for some reason, specifying a driver disables batching and
breaks rendering, so enable it explicitly)
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
ui/sdl2.c | 16
1 file changed, 16 insertions(+)
diff --git a/ui/sdl2.c b/ui/sdl2.c
index 221cdced60..35c58c1104 100644
--- a/ui/sdl2.c
+++ b/ui/sdl2.c
@@ -58,6 +58,11 @@ static Notifier mouse_mode_notifier;
#define SDL2_MAX_IDLE_COUNT (2 * GUI_REFRESH_INTERVAL_DEFAULT \
/ SDL2_REFRESH_INTERVAL_BUSY + 1)
+/* introduced in SDL 2.0.10 */
+#ifndef SDL_HINT_RENDER_BATCHING
+#define SDL_HINT_RENDER_BATCHING "SDL_RENDER_BATCHING"
+#endif
+
static void sdl_update_caption(struct sdl2_console *scon);
static struct sdl2_console *get_scon_from_window(uint32_t window_id)
@@ -99,7 +104,18 @@ void sdl2_window_create(struct sdl2_console *scon)
surface_width(scon->surface),
surface_height(scon->surface),
flags);
+if (scon->opengl) {
+const char *driver = "opengl";
+
+if (scon->opts->gl == DISPLAYGL_MODE_ES) {
+driver = "opengles2";
+}
+
+SDL_SetHint(SDL_HINT_RENDER_DRIVER, driver);
+SDL_SetHint(SDL_HINT_RENDER_BATCHING, "1");
+}
scon->real_renderer = SDL_CreateRenderer(scon->real_window, -1, 0);
+
if (scon->opengl) {
scon->winctx = SDL_GL_CreateContext(scon->real_window);
}
--
2.39.2
[PULL v2 06/18] ui: rename cursor_{put->unref}
From: Marc-André Lureau
The naming is more conventional in QEMU.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
include/ui/console.h| 2 +-
hw/display/qxl-render.c | 4 ++--
hw/display/qxl.c| 2 +-
hw/display/vmware_vga.c | 4 ++--
ui/cursor.c | 2 +-
ui/dbus-listener.c | 2 +-
ui/spice-display.c | 4 ++--
ui/vnc.c| 2 +-
8 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/include/ui/console.h b/include/ui/console.h
index 1cb53acc33..3efd1f6b82 100644
--- a/include/ui/console.h
+++ b/include/ui/console.h
@@ -152,7 +152,7 @@ typedef struct QEMUCursor {
QEMUCursor *cursor_alloc(int width, int height);
void cursor_get(QEMUCursor *c);
-void cursor_put(QEMUCursor *c);
+void cursor_unref(QEMUCursor *c);
QEMUCursor *cursor_builtin_hidden(void);
QEMUCursor *cursor_builtin_left_ptr(void);
void cursor_print_ascii_art(QEMUCursor *c, const char *prefix);
diff --git a/hw/display/qxl-render.c b/hw/display/qxl-render.c
index fcfd40c3ac..ec99ec887a 100644
--- a/hw/display/qxl-render.c
+++ b/hw/display/qxl-render.c
@@ -290,7 +290,7 @@ static QEMUCursor *qxl_cursor(PCIQXLDevice *qxl, QXLCursor
*cursor,
return c;
fail:
-cursor_put(c);
+cursor_unref(c);
return NULL;
}
@@ -336,7 +336,7 @@ int qxl_render_cursor(PCIQXLDevice *qxl, QXLCommandExt *ext)
}
qemu_mutex_lock(>ssd.lock);
if (qxl->ssd.cursor) {
-cursor_put(qxl->ssd.cursor);
+cursor_unref(qxl->ssd.cursor);
}
qxl->ssd.cursor = c;
qxl->ssd.mouse_x = cmd->u.set.position.x;
diff --git a/hw/display/qxl.c b/hw/display/qxl.c
index ec712d3ca2..80ce1e9a93 100644
--- a/hw/display/qxl.c
+++ b/hw/display/qxl.c
@@ -299,7 +299,7 @@ void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
qxl->guest_cursor = 0;
qemu_mutex_unlock(>track_lock);
if (qxl->ssd.cursor) {
-cursor_put(qxl->ssd.cursor);
+cursor_unref(qxl->ssd.cursor);
}
qxl->ssd.cursor = cursor_builtin_hidden();
}
diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c
index 59ae7f74b8..09591fbd39 100644
--- a/hw/display/vmware_vga.c
+++ b/hw/display/vmware_vga.c
@@ -550,12 +550,12 @@ static inline void vmsvga_cursor_define(struct
vmsvga_state_s *s,
default:
fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
__func__, c->bpp);
-cursor_put(qc);
+cursor_unref(qc);
qc = cursor_builtin_left_ptr();
}
dpy_cursor_define(s->vga.con, qc);
-cursor_put(qc);
+cursor_unref(qc);
}
#endif
diff --git a/ui/cursor.c b/ui/cursor.c
index 835f0802f9..31b09bf058 100644
--- a/ui/cursor.c
+++ b/ui/cursor.c
@@ -111,7 +111,7 @@ void cursor_get(QEMUCursor *c)
c->refcount++;
}
-void cursor_put(QEMUCursor *c)
+void cursor_unref(QEMUCursor *c)
{
if (c == NULL)
return;
diff --git a/ui/dbus-listener.c b/ui/dbus-listener.c
index 2dafd6569c..906ab296ca 100644
--- a/ui/dbus-listener.c
+++ b/ui/dbus-listener.c
@@ -345,7 +345,7 @@ static void dbus_cursor_define(DisplayChangeListener *dcl,
c->data,
c->width * c->height * 4,
TRUE,
-(GDestroyNotify)cursor_put,
+(GDestroyNotify)cursor_unref,
c);
qemu_dbus_display1_listener_call_cursor_define(
diff --git a/ui/spice-display.c b/ui/spice-display.c
index 16802f99cb..243a794638 100644
--- a/ui/spice-display.c
+++ b/ui/spice-display.c
@@ -464,7 +464,7 @@ void qemu_spice_cursor_refresh_bh(void *opaque)
qemu_mutex_unlock(>lock);
dpy_cursor_define(ssd->dcl.con, c);
qemu_mutex_lock(>lock);
-cursor_put(c);
+cursor_unref(c);
}
if (ssd->mouse_x != -1 && ssd->mouse_y != -1) {
@@ -766,7 +766,7 @@ static void display_mouse_define(DisplayChangeListener *dcl,
qemu_mutex_lock(>lock);
cursor_get(c);
-cursor_put(ssd->cursor);
+cursor_unref(ssd->cursor);
ssd->cursor = c;
ssd->hot_x = c->hot_x;
ssd->hot_y = c->hot_y;
diff --git a/ui/vnc.c b/ui/vnc.c
index d9eacad759..0bdcc3dfce 100644
--- a/ui/vnc.c
+++ b/ui/vnc.c
@@ -1029,7 +1029,7 @@ static void vnc_dpy_cursor_define(DisplayChangeListener
*dcl,
VncDisplay *vd = container_of(dcl, VncDisplay, dcl);
VncState *vs;
-cursor_put(vd->cursor);
+cursor_unref(vd->cursor);
g_free(vd->cursor_mask);
vd->cursor = c;
--
2.39.2
[PULL v2 18/18] ui/dbus: restrict opengl to gbm-enabled config
From: Marc-André Lureau
We can enable EGL later for non-GBM hosts.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
ui/dbus-listener.c | 10 +-
ui/dbus.c | 12 +++-
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/ui/dbus-listener.c b/ui/dbus-listener.c
index 85692f1b27..911acdc529 100644
--- a/ui/dbus-listener.c
+++ b/ui/dbus-listener.c
@@ -50,7 +50,7 @@ struct _DBusDisplayListener {
G_DEFINE_TYPE(DBusDisplayListener, dbus_display_listener, G_TYPE_OBJECT)
-#ifdef CONFIG_OPENGL
+#ifdef CONFIG_GBM
static void dbus_update_gl_cb(GObject *source_object,
GAsyncResult *res,
gpointer user_data)
@@ -239,7 +239,7 @@ static void dbus_refresh(DisplayChangeListener *dcl)
graphic_hw_update(dcl->con);
}
-#ifdef CONFIG_OPENGL
+#ifdef CONFIG_GBM
static void dbus_gl_gfx_update(DisplayChangeListener *dcl,
int x, int y, int w, int h)
{
@@ -302,7 +302,7 @@ static void dbus_gfx_update(DisplayChangeListener *dcl,
DBUS_DEFAULT_TIMEOUT, NULL, NULL, NULL);
}
-#ifdef CONFIG_OPENGL
+#ifdef CONFIG_GBM
static void dbus_gl_gfx_switch(DisplayChangeListener *dcl,
struct DisplaySurface *new_surface)
{
@@ -369,7 +369,7 @@ static void dbus_cursor_define(DisplayChangeListener *dcl,
NULL);
}
-#ifdef CONFIG_OPENGL
+#ifdef CONFIG_GBM
const DisplayChangeListenerOps dbus_gl_dcl_ops = {
.dpy_name= "dbus-gl",
.dpy_gfx_update = dbus_gl_gfx_update,
@@ -417,7 +417,7 @@ dbus_display_listener_constructed(GObject *object)
DBusDisplayListener *ddl = DBUS_DISPLAY_LISTENER(object);
ddl->dcl.ops = _dcl_ops;
-#ifdef CONFIG_OPENGL
+#ifdef CONFIG_GBM
if (display_opengl) {
ddl->dcl.ops = _gl_dcl_ops;
}
diff --git a/ui/dbus.c b/ui/dbus.c
index 904f5a0a6d..0513de9918 100644
--- a/ui/dbus.c
+++ b/ui/dbus.c
@@ -47,8 +47,10 @@ static DBusDisplay *dbus_display;
static QEMUGLContext dbus_create_context(DisplayGLCtx *dgc,
QEMUGLParams *params)
{
+#ifdef CONFIG_GBM
eglMakeCurrent(qemu_egl_display, EGL_NO_SURFACE, EGL_NO_SURFACE,
qemu_egl_rn_ctx);
+#endif
return qemu_egl_create_context(dgc, params);
}
@@ -56,7 +58,11 @@ static bool
dbus_is_compatible_dcl(DisplayGLCtx *dgc,
DisplayChangeListener *dcl)
{
-return dcl->ops == _gl_dcl_ops || dcl->ops == _console_dcl_ops;
+return
+#ifdef CONFIG_GBM
+dcl->ops == _gl_dcl_ops ||
+#endif
+dcl->ops == _console_dcl_ops;
}
static void
@@ -459,7 +465,11 @@ early_dbus_init(DisplayOptions *opts)
DisplayGLMode mode = opts->has_gl ? opts->gl : DISPLAYGL_MODE_OFF;
if (mode != DISPLAYGL_MODE_OFF) {
+#ifdef CONFIG_OPENGL
egl_init(opts->u.dbus.rendernode, mode, _fatal);
+#else
+error_report("dbus: GL rendering is not supported");
+#endif
}
type_register(_vc_type_info);
--
2.39.2
[PULL v2 09/18] ui: set cursor upon listener registration
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
ui/console.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/ui/console.c b/ui/console.c
index 0dccbdd4be..35f8274aab 100644
--- a/ui/console.c
+++ b/ui/console.c
@@ -1662,6 +1662,9 @@ void register_displaychangelistener(DisplayChangeListener
*dcl)
con = active_console;
}
displaychangelistener_display_console(dcl, con, dcl->con ? _fatal :
NULL);
+if (con && con->cursor && dcl->ops->dpy_cursor_define) {
+dcl->ops->dpy_cursor_define(dcl, con->cursor);
+}
text_console_update_cursor(NULL);
}
--
2.39.2
[PULL v2 02/18] ui/dbus: unregister clipboard on connection close
From: Marc-André Lureau
Fixes unregistration with p2p connections, since they don't have an
associated name owner.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
ui/dbus-clipboard.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/ui/dbus-clipboard.c b/ui/dbus-clipboard.c
index df9a754a8d..fe7fcdecb6 100644
--- a/ui/dbus-clipboard.c
+++ b/ui/dbus-clipboard.c
@@ -204,15 +204,6 @@ dbus_clipboard_unregister_proxy(DBusDisplay *dpy)
g_clear_object(>clipboard_proxy);
}
-static void
-dbus_on_clipboard_proxy_name_owner_changed(
-DBusDisplay *dpy,
-GObject *object,
-GParamSpec *pspec)
-{
-dbus_clipboard_unregister_proxy(dpy);
-}
-
static gboolean
dbus_clipboard_register(
DBusDisplay *dpy,
@@ -220,6 +211,7 @@ dbus_clipboard_register(
{
g_autoptr(GError) err = NULL;
const char *name = NULL;
+GDBusConnection *connection =
g_dbus_method_invocation_get_connection(invocation);
if (dpy->clipboard_proxy) {
g_dbus_method_invocation_return_error(
@@ -232,7 +224,7 @@ dbus_clipboard_register(
dpy->clipboard_proxy =
qemu_dbus_display1_clipboard_proxy_new_sync(
-g_dbus_method_invocation_get_connection(invocation),
+connection,
G_DBUS_PROXY_FLAGS_DO_NOT_AUTO_START,
g_dbus_method_invocation_get_sender(invocation),
"/org/qemu/Display1/Clipboard",
@@ -252,7 +244,11 @@ dbus_clipboard_register(
g_object_connect(dpy->clipboard_proxy,
"swapped-signal::notify::g-name-owner",
- dbus_on_clipboard_proxy_name_owner_changed, dpy,
+ dbus_clipboard_unregister_proxy, dpy,
+ NULL);
+g_object_connect(connection,
+ "swapped-signal::closed",
+ dbus_clipboard_unregister_proxy, dpy,
NULL);
qemu_clipboard_reset_serial();
--
2.39.2
[PULL v2 05/18] meson: ensure dbus-display generated code is built before other units
From: Marc-André Lureau
It's simply by luck that dbus-display header is built first before the
other units using it.
With sourceset, I can't find an easier way out than declaring an extra
dependency for dbus-display1 generate code.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
ui/meson.build | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/ui/meson.build b/ui/meson.build
index 612ea2325b..0b2d0d21d1 100644
--- a/ui/meson.build
+++ b/ui/meson.build
@@ -83,7 +83,9 @@ if dbus_display
'--interface-prefix', 'org.qemu.',
'--c-namespace', 'QemuDBus',
'--generate-c-code', '@BASENAME@'])
- dbus_ss.add(when: [gio, pixman, opengl, gbm],
+ dbus_display1_lib = static_library('dbus-display1', dbus_display1,
dependencies: gio)
+ dbus_display1_dep = declare_dependency(link_with: dbus_display1_lib,
include_directories: include_directories('.'))
+ dbus_ss.add(when: [gio, pixman, opengl, gbm, dbus_display1_dep],
if_true: [files(
'dbus-chardev.c',
'dbus-clipboard.c',
@@ -91,7 +93,7 @@ if dbus_display
'dbus-error.c',
'dbus-listener.c',
'dbus.c',
- ), dbus_display1])
+ )])
ui_modules += {'dbus' : dbus_ss}
endif
--
2.39.2
[PULL v2 07/18] ui: rename cursor_{get->ref}, return it
From: Marc-André Lureau
The naming is more conventional in QEMU code, and allows to simplify
some code by changing the API design, so it returns the input parameter,
instead of void.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
include/ui/console.h | 2 +-
ui/cursor.c | 3 ++-
ui/dbus-listener.c | 3 +--
ui/spice-display.c | 4 ++--
ui/vnc.c | 3 +--
5 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/include/ui/console.h b/include/ui/console.h
index 3efd1f6b82..0b01df947e 100644
--- a/include/ui/console.h
+++ b/include/ui/console.h
@@ -151,7 +151,7 @@ typedef struct QEMUCursor {
} QEMUCursor;
QEMUCursor *cursor_alloc(int width, int height);
-void cursor_get(QEMUCursor *c);
+QEMUCursor *cursor_ref(QEMUCursor *c);
void cursor_unref(QEMUCursor *c);
QEMUCursor *cursor_builtin_hidden(void);
QEMUCursor *cursor_builtin_left_ptr(void);
diff --git a/ui/cursor.c b/ui/cursor.c
index 31b09bf058..6fe67990e2 100644
--- a/ui/cursor.c
+++ b/ui/cursor.c
@@ -106,9 +106,10 @@ QEMUCursor *cursor_alloc(int width, int height)
return c;
}
-void cursor_get(QEMUCursor *c)
+QEMUCursor *cursor_ref(QEMUCursor *c)
{
c->refcount++;
+return c;
}
void cursor_unref(QEMUCursor *c)
diff --git a/ui/dbus-listener.c b/ui/dbus-listener.c
index 906ab296ca..2e87ed7e9a 100644
--- a/ui/dbus-listener.c
+++ b/ui/dbus-listener.c
@@ -339,14 +339,13 @@ static void dbus_cursor_define(DisplayChangeListener *dcl,
DBusDisplayListener *ddl = container_of(dcl, DBusDisplayListener, dcl);
GVariant *v_data = NULL;
-cursor_get(c);
v_data = g_variant_new_from_data(
G_VARIANT_TYPE("ay"),
c->data,
c->width * c->height * 4,
TRUE,
(GDestroyNotify)cursor_unref,
-c);
+cursor_ref(c));
qemu_dbus_display1_listener_call_cursor_define(
ddl->proxy,
diff --git a/ui/spice-display.c b/ui/spice-display.c
index 243a794638..5bee19a7f9 100644
--- a/ui/spice-display.c
+++ b/ui/spice-display.c
@@ -460,7 +460,7 @@ void qemu_spice_cursor_refresh_bh(void *opaque)
if (ssd->cursor) {
QEMUCursor *c = ssd->cursor;
assert(ssd->dcl.con);
-cursor_get(c);
+cursor_ref(c);
qemu_mutex_unlock(>lock);
dpy_cursor_define(ssd->dcl.con, c);
qemu_mutex_lock(>lock);
@@ -765,7 +765,7 @@ static void display_mouse_define(DisplayChangeListener *dcl,
SimpleSpiceDisplay *ssd = container_of(dcl, SimpleSpiceDisplay, dcl);
qemu_mutex_lock(>lock);
-cursor_get(c);
+cursor_ref(c);
cursor_unref(ssd->cursor);
ssd->cursor = c;
ssd->hot_x = c->hot_x;
diff --git a/ui/vnc.c b/ui/vnc.c
index 0bdcc3dfce..8aec5d751e 100644
--- a/ui/vnc.c
+++ b/ui/vnc.c
@@ -1032,8 +1032,7 @@ static void vnc_dpy_cursor_define(DisplayChangeListener
*dcl,
cursor_unref(vd->cursor);
g_free(vd->cursor_mask);
-vd->cursor = c;
-cursor_get(vd->cursor);
+vd->cursor = cursor_ref(vd->cursor);
vd->cursor_msize = cursor_get_mono_bpl(c) * c->height;
vd->cursor_mask = g_malloc0(vd->cursor_msize);
cursor_get_mono_mask(c, 0, vd->cursor_mask);
--
2.39.2
[PULL v2 04/18] ui/dbus: set mouse is-absolute during console creation
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
---
ui/dbus-console.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/ui/dbus-console.c b/ui/dbus-console.c
index 0bfaa2298d..f77bc49d2e 100644
--- a/ui/dbus-console.c
+++ b/ui/dbus-console.c
@@ -411,15 +411,21 @@ dbus_mouse_release(DBusDisplayConsole *ddc,
return DBUS_METHOD_INVOCATION_HANDLED;
}
+static void
+dbus_mouse_update_is_absolute(DBusDisplayConsole *ddc)
+{
+g_object_set(ddc->iface_mouse,
+ "is-absolute", qemu_input_is_absolute(),
+ NULL);
+}
+
static void
dbus_mouse_mode_change(Notifier *notify, void *data)
{
DBusDisplayConsole *ddc =
container_of(notify, DBusDisplayConsole, mouse_mode_notifier);
-g_object_set(ddc->iface_mouse,
- "is-absolute", qemu_input_is_absolute(),
- NULL);
+dbus_mouse_update_is_absolute(ddc);
}
int dbus_display_console_get_index(DBusDisplayConsole *ddc)
@@ -492,6 +498,7 @@ dbus_display_console_new(DBusDisplay *display, QemuConsole
*con)
register_displaychangelistener(>dcl);
ddc->mouse_mode_notifier.notify = dbus_mouse_mode_change;
qemu_add_mouse_mode_change_notifier(>mouse_mode_notifier);
+dbus_mouse_update_is_absolute(ddc);
return ddc;
}
--
2.39.2
[PULL v2 08/18] ui: keep current cursor with QemuConsole
From: Marc-André Lureau
Keeping the current cursor around is useful, not only for VNC, but for
other displays. Let's move it down, see the following patches for other
usages.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
include/ui/console.h | 1 +
ui/vnc.h | 1 -
ui/console.c | 8
ui/vnc.c | 7 ++-
4 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/include/ui/console.h b/include/ui/console.h
index 0b01df947e..2a8fab091f 100644
--- a/include/ui/console.h
+++ b/include/ui/console.h
@@ -459,6 +459,7 @@ QemuConsole *qemu_console_lookup_by_device(DeviceState
*dev, uint32_t head);
QemuConsole *qemu_console_lookup_by_device_name(const char *device_id,
uint32_t head, Error **errp);
QemuConsole *qemu_console_lookup_unused(void);
+QEMUCursor *qemu_console_get_cursor(QemuConsole *con);
bool qemu_console_is_visible(QemuConsole *con);
bool qemu_console_is_graphic(QemuConsole *con);
bool qemu_console_is_fixedsize(QemuConsole *con);
diff --git a/ui/vnc.h b/ui/vnc.h
index a60fb13115..757fa83044 100644
--- a/ui/vnc.h
+++ b/ui/vnc.h
@@ -159,7 +159,6 @@ struct VncDisplay
QKbdState *kbd;
QemuMutex mutex;
-QEMUCursor *cursor;
int cursor_msize;
uint8_t *cursor_mask;
diff --git a/ui/console.c b/ui/console.c
index 98b701f5a3..0dccbdd4be 100644
--- a/ui/console.c
+++ b/ui/console.c
@@ -94,6 +94,7 @@ struct QemuConsole {
uint32_t head;
QemuUIInfo ui_info;
QEMUTimer *ui_timer;
+QEMUCursor *cursor;
const GraphicHwOps *hw_ops;
void *hw;
@@ -1923,6 +1924,8 @@ void dpy_cursor_define(QemuConsole *con, QEMUCursor
*cursor)
DisplayState *s = con->ds;
DisplayChangeListener *dcl;
+cursor_unref(con->cursor);
+con->cursor = cursor_ref(cursor);
if (!qemu_console_is_visible(con)) {
return;
}
@@ -2288,6 +2291,11 @@ QemuConsole *qemu_console_lookup_unused(void)
return NULL;
}
+QEMUCursor *qemu_console_get_cursor(QemuConsole *con)
+{
+return con->cursor;
+}
+
bool qemu_console_is_visible(QemuConsole *con)
{
return (con == active_console) || (con->dcls > 0);
diff --git a/ui/vnc.c b/ui/vnc.c
index 8aec5d751e..bbd8b6baae 100644
--- a/ui/vnc.c
+++ b/ui/vnc.c
@@ -988,10 +988,10 @@ static void vnc_mouse_set(DisplayChangeListener *dcl,
static int vnc_cursor_define(VncState *vs)
{
-QEMUCursor *c = vs->vd->cursor;
+QEMUCursor *c = qemu_console_get_cursor(vs->vd->dcl.con);
int isize;
-if (!vs->vd->cursor) {
+if (!c) {
return -1;
}
@@ -1029,10 +1029,7 @@ static void vnc_dpy_cursor_define(DisplayChangeListener
*dcl,
VncDisplay *vd = container_of(dcl, VncDisplay, dcl);
VncState *vs;
-cursor_unref(vd->cursor);
g_free(vd->cursor_mask);
-
-vd->cursor = cursor_ref(vd->cursor);
vd->cursor_msize = cursor_get_mono_bpl(c) * c->height;
vd->cursor_mask = g_malloc0(vd->cursor_msize);
cursor_get_mono_mask(c, 0, vd->cursor_mask);
--
2.39.2
[PULL v2 01/18] ui/dbus: initialize cursor_fb
From: Marc-André Lureau
Or else, we may randomly destroy some textures..
Signed-off-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
---
include/ui/egl-helpers.h | 2 ++
ui/dbus-listener.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/ui/egl-helpers.h b/include/ui/egl-helpers.h
index 2fb6e0dd6b..c92dd90e33 100644
--- a/include/ui/egl-helpers.h
+++ b/include/ui/egl-helpers.h
@@ -22,6 +22,8 @@ typedef struct egl_fb {
QemuDmaBuf *dmabuf;
} egl_fb;
+#define EGL_FB_INIT { 0, }
+
void egl_fb_destroy(egl_fb *fb);
void egl_fb_setup_default(egl_fb *fb, int width, int height);
void egl_fb_setup_for_tex(egl_fb *fb, int width, int height,
diff --git a/ui/dbus-listener.c b/ui/dbus-listener.c
index 57d4e401db..2dafd6569c 100644
--- a/ui/dbus-listener.c
+++ b/ui/dbus-listener.c
@@ -149,7 +149,7 @@ static void dbus_cursor_dmabuf(DisplayChangeListener *dcl,
DBusDisplayListener *ddl = container_of(dcl, DBusDisplayListener, dcl);
DisplaySurface *ds;
GVariant *v_data = NULL;
-egl_fb cursor_fb;
+egl_fb cursor_fb = EGL_FB_INIT;
if (!dmabuf) {
qemu_dbus_display1_listener_call_mouse_set(
--
2.39.2
Re: [PATCH v2 01/12] target/s390x: Handle branching to odd addresses
On 3/13/23 08:38, Ilya Leoshkevich wrote: Let branching happen and try to generate a new translation block with an odd address. Generate a specification exception in cpu_get_tb_cpu_state(). Reported-by: Harold Grovesteen Reported-by: Nina Schoetterl-Glausch Signed-off-by: Ilya Leoshkevich --- target/s390x/cpu.h | 9 + 1 file changed, 9 insertions(+) Reviewed-by: Richard Henderson r~
Re: [PATCH] MAINTAINERS: Mark the Nios II CPU as orphan
On 3/13/23 11:33, Thomas Huth wrote: Marek and Chris haven't been active for Nios II since years (the last time seems to have been in 2017), and we've got unhandled severe Nios II bug tickets in the bug tracker since a long time, so to avoid wrong expectations of people who are looking at the MAINTAINERS file, it's maybe best to mark the Nios II entry as orphan nowadays. Suggested-by: Richard Henderson Signed-off-by: Thomas Huth Reviewed-by: Richard Henderson r~ --- Suggested by Richard here: https://lore.kernel.org/qemu-devel/cb2e92b7-40bb-4975-290d-6321c5574...@linaro.org/ And bugs like this sound like the linux-user target is in a bad shape, too: https://gitlab.com/qemu-project/qemu/-/issues/261 See also: https://bugs.launchpad.net/qemu/+bug/1791796 (comment 3) ... nobody tried to fix nios2 linux-user in years, maybe we should deprecate it? MAINTAINERS | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 95c957d587..9780430626 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -257,9 +257,9 @@ F: docs/system/cpu-models-mips.rst.inc F: tests/tcg/mips/ NiosII TCG CPUs -M: Chris Wulff -M: Marek Vasut -S: Maintained +R: Chris Wulff +R: Marek Vasut +S: Orphan F: target/nios2/ F: hw/nios2/ F: disas/nios2.c
Re: [PATCH v7] audio/pwaudio.c: Add Pipewire audio backend for QEMU
Am 13.03.23 um 14:11 schrieb Dorinda Bassey:
Hi Volker,
To hear this,
start QEMU with qemu-system-x86_64 -machine pcspk-audiodev=audio0
-device ich9-intel-hda -device hda-duplex,audiodev=audio0 -audiodev
pipewire,id=audio0,out.mixing-engine=off ...
I hear the clipped audio stream with these options. IMO, I don't think
memset is responsible for that behaviour, I still hear the harsh sound
with "-audiodev pa". I also tried using an alternative like:
Hi Dorinda,
when you test -audiodev pa with a pulseaudio server, audio playback is
fine. Audio playback with -audiodev pa with the pipewire-pulse server is
clipped. This is a pipewire bug.
With best regards,
Volker
@@ -117,7 +118,7 @@ playback_on_process(void *data)
}
if (avail == 0) {
- memset(p, 0, n_bytes);
+ p = g_malloc0(sizeof(n_bytes));
} else {
The clipped audio issue is still persistent.
Thanks,
Dorinda.
On Sun, Mar 12, 2023 at 9:01 AM Volker Rümelin
wrote:
> +/* output data processing function to read stuffs from the
buffer */
> +static void
> +playback_on_process(void *data)
> +{
> + PWVoice *v = (PWVoice *) data;
> + void *p;
> + struct pw_buffer *b;
> + struct spa_buffer *buf;
> + uint32_t n_frames, req, index, n_bytes;
> + int32_t avail;
> +
> + if (!v->stream) {
> + return;
> + }
> +
> + /* obtain a buffer to read from */
> + b = pw_stream_dequeue_buffer(v->stream);
> + if (b == NULL) {
> + error_report("out of buffers: %s", strerror(errno));
> + return;
> + }
> +
> + buf = b->buffer;
> + p = buf->datas[0].data;
> + if (p == NULL) {
> + return;
> + }
> + req = b->requested * v->frame_size;
> + if (req == 0) {
> + req = 4096 * v->frame_size;
> + }
> + n_frames = SPA_MIN(req, buf->datas[0].maxsize);
> + n_bytes = n_frames * v->frame_size;
> +
> + /* get no of available bytes to read data from buffer */
> +
> + avail = spa_ringbuffer_get_read_index(>ring, );
> +
> + if (!v->enabled) {
> + avail = 0;
> + }
> +
> + if (avail == 0) {
> + memset(p, 0, n_bytes);
memset() doesn't work for unsigned samples. For unsigned samples, a
stream of zeros is silence with a DC offset. When Pipewire mixes this
stream with another, the result is a clipped audio stream. To hear
this,
start QEMU with qemu-system-x86_64 -machine pcspk-audiodev=audio0
-device ich9-intel-hda -device hda-duplex,audiodev=audio0 -audiodev
pipewire,id=audio0,out.mixing-engine=off ... and start playback
with the
hda device.
With best regards,
Volker
> + } else {
> + if (avail < (int32_t) n_bytes) {
> + n_bytes = avail;
> + }
> +
> + spa_ringbuffer_read_data(>ring,
> + v->buffer, RINGBUFFER_SIZE,
> + index & RINGBUFFER_MASK, p,
n_bytes);
> +
> + index += n_bytes;
> + spa_ringbuffer_read_update(>ring, index);
> + }
> +
> + buf->datas[0].chunk->offset = 0;
> + buf->datas[0].chunk->stride = v->frame_size;
> + buf->datas[0].chunk->size = n_bytes;
> +
> + /* queue the buffer for playback */
> + pw_stream_queue_buffer(v->stream, b);
> +}
> +
>
Re: [PATCH 09/11] tests/tcg: disable pauth for aarch64 gdb tests
On 3/13/23 04:44, Luis Machado wrote: Luis: I think that rather than doing (2) with a QEMU namespace, we should define a gdb namespace for this. That makes it clear that this is still a gdb-upstream-sanctioned way of exposing the pauth registers. That should be fine as well, and would work to side-step the gdb 12 bug so it doesn't crash. We could name the feature "org.gnu.gdb.aarch64.pauth_v2" or somesuch, and slowly stop using the original "org.gnu.gdb.aarch64.pauth" feature. I can document the requirements for a compliant pauth_v2. What if we leave the original two registers, pauth_[cd]mask, in org.gnu.gdb.aarch64.pauth and move the new *_high registers into a different feature? That would maximize the set of gdb version for which the original user-only support is functional. r~
Re: [PATCH v7] audio/pwaudio.c: Add Pipewire audio backend for QEMU
>
> Are you sure about sizeof(n_bytes) here? That's 4. ;-)
>
my bad!
>
> Volker's point was that "silence" is the center of the wave range. With
> signed
> range that's zero, yes, but with unsigned range that's 2^(bitdepth) / 2.
>
> So you need to memset() the correct value to generate "silence".
>
I understand now, Thanks. I guess it should work for signed range, so I
would do:
@@ -117,7 +117,9 @@ playback_on_process(void *data)
}
if (avail == 0) {
-memset(p, 0, n_bytes);
+memset(p, 0, (int32_t) n_bytes);
CMIIW
Thanks,
Dorinda.
On Mon, Mar 13, 2023 at 2:37 PM Christian Schoenebeck <
qemu_...@crudebyte.com> wrote:
> On Monday, March 13, 2023 2:11:11 PM CET Dorinda Bassey wrote:
> > Hi Volker,
> >
> >
> > > To hear this,
> > > start QEMU with qemu-system-x86_64 -machine pcspk-audiodev=audio0
> > > -device ich9-intel-hda -device hda-duplex,audiodev=audio0 -audiodev
> > > pipewire,id=audio0,out.mixing-engine=off ...
> > >
> > I hear the clipped audio stream with these options. IMO, I don't think
> > memset is responsible for that behaviour, I still hear the harsh sound
> with
> > "-audiodev pa". I also tried using an alternative like:
> >
> > @@ -117,7 +118,7 @@ playback_on_process(void *data)
> > }
> >
> > if (avail == 0) {
> > -memset(p, 0, n_bytes);
> > +p = g_malloc0(sizeof(n_bytes));
> > } else {
> >
> > The clipped audio issue is still persistent.
>
> Are you sure about sizeof(n_bytes) here? That's 4. ;-)
>
> Volker's point was that "silence" is the center of the wave range. With
> signed
> range that's zero, yes, but with unsigned range that's 2^(bitdepth) / 2.
>
> So you need to memset() the correct value to generate "silence".
>
> Best regards,
> Christian Schoenebeck
>
>
>
[PATCH RESEND v2 2/2] migration/xbzrle: fix out-of-bounds write with axv512
xbzrle_encode_buffer_avx512() checks for overflows too scarcely in its
outer loop, causing out-of-bounds writes:
$ ../configure --target-list=aarch64-softmmu --enable-sanitizers
--enable-avx512bw
$ make tests/unit/test-xbzrle && ./tests/unit/test-xbzrle
==5518==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x6210b100
at pc 0x561109a7714d bp 0x7ffed712a440 sp 0x7ffed712a430
WRITE of size 1 at 0x6210b100 thread T0
#0 0x561109a7714c in uleb128_encode_small ../util/cutils.c:831
#1 0x561109b67f6a in xbzrle_encode_buffer_avx512 ../migration/xbzrle.c:275
#2 0x5611099a7428 in test_encode_decode_overflow
../tests/unit/test-xbzrle.c:153
#3 0x7fb2fb65a58d (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x7a58d)
#4 0x7fb2fb65a333 (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x7a333)
#5 0x7fb2fb65aa79 in g_test_run_suite
(/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x7aa79)
#6 0x7fb2fb65aa94 in g_test_run
(/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x7aa94)
#7 0x5611099a3a23 in main ../tests/unit/test-xbzrle.c:218
#8 0x7fb2fa78c082 in __libc_start_main
(/lib/x86_64-linux-gnu/libc.so.6+0x24082)
#9 0x5611099a608d in _start (/qemu/build/tests/unit/test-xbzrle+0x28408d)
0x6210b100 is located 0 bytes to the right of 4096-byte region
[0x6210a100,0x6210b100)
allocated by thread T0 here:
#0 0x7fb2fb823a06 in __interceptor_calloc
../../../../src/libsanitizer/asan/asan_malloc_linux.cc:153
#1 0x7fb2fb637ef0 in g_malloc0
(/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x57ef0)
Fix that by performing the overflow check in the inner loop, instead.
Signed-off-by: Matheus Tavares Bernardino
---
migration/xbzrle.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/migration/xbzrle.c b/migration/xbzrle.c
index 21b92d4eae..c6f8b20917 100644
--- a/migration/xbzrle.c
+++ b/migration/xbzrle.c
@@ -197,10 +197,6 @@ int xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t
*new_buf, int slen,
__m512i r = _mm512_set1_epi32(0);
while (count512s) {
-if (d + 2 > dlen) {
-return -1;
-}
-
int bytes_to_check = 64;
uint64_t mask = 0x;
if (count512s == 1) {
@@ -216,6 +212,9 @@ int xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t
*new_buf, int slen,
bool is_same = (comp & 0x1);
while (bytes_to_check) {
+if (d + 2 > dlen) {
+return -1;
+}
if (is_same) {
if (nzrun_len) {
d += uleb128_encode_small(dst + d, nzrun_len);
--
2.39.1
[PATCH RESEND v2 1/2] migration/xbzrle: use ctz64 to avoid undefined result
__builtin_ctzll() produces undefined results when the argument is 0. This can be seen through test-xbzrle, which produces the following warning: ../migration/xbzrle.c:265: runtime error: passing zero to ctz(), which is not a valid argument Replace __builtin_ctzll() with our ctz64() wrapper which properly handles 0. Signed-off-by: Matheus Tavares Bernardino --- migration/xbzrle.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/migration/xbzrle.c b/migration/xbzrle.c index 05366e86c0..21b92d4eae 100644 --- a/migration/xbzrle.c +++ b/migration/xbzrle.c @@ -12,6 +12,7 @@ */ #include "qemu/osdep.h" #include "qemu/cutils.h" +#include "qemu/host-utils.h" #include "xbzrle.h" /* @@ -233,7 +234,7 @@ int xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t *new_buf, int slen, break; } never_same = false; -num = __builtin_ctzll(~comp); +num = ctz64(~comp); num = (num < bytes_to_check) ? num : bytes_to_check; zrun_len += num; bytes_to_check -= num; @@ -262,7 +263,7 @@ int xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t *new_buf, int slen, nzrun_len += 64; break; } -num = __builtin_ctzll(comp); +num = ctz64(comp); num = (num < bytes_to_check) ? num : bytes_to_check; nzrun_len += num; bytes_to_check -= num; -- 2.39.1
[PULL v3 00/91] tcg patch queue
Version 3 fixes a rebase error from v2 affecting ARM BFC insn.
r~
The following changes since commit 29c8a9e31a982874ce4e2c15f2bf82d5f8dc3517:
Merge tag 'linux-user-for-8.0-pull-request' of
https://gitlab.com/laurent_vivier/qemu into staging (2023-03-12 10:57:00 +)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230313
for you to fetch changes up to 0c8b6b9a6383e2e37ff3d1d12b40c58b7ed36c1c:
tcg: Drop tcg_const_* (2023-03-13 07:03:39 -0700)
accel/tcg: Fix NB_MMU_MODES to 16
Balance of the target/ patchset which eliminates tcg_temp_free
Balance of the target/ patchset which eliminates tcg_const
Anton Johansson (23):
include/exec: Set default `NB_MMU_MODES` to 16
target/alpha: Remove `NB_MMU_MODES` define
target/arm: Remove `NB_MMU_MODES` define
target/avr: Remove `NB_MMU_MODES` define
target/cris: Remove `NB_MMU_MODES` define
target/hexagon: Remove `NB_MMU_MODES` define
target/hppa: Remove `NB_MMU_MODES` define
target/i386: Remove `NB_MMU_MODES` define
target/loongarch: Remove `NB_MMU_MODES` define
target/m68k: Remove `NB_MMU_MODES` define
target/microblaze: Remove `NB_MMU_MODES` define
target/mips: Remove `NB_MMU_MODES` define
target/nios2: Remove `NB_MMU_MODES` define
target/openrisc: Remove `NB_MMU_MODES` define
target/ppc: Remove `NB_MMU_MODES` define
target/riscv: Remove `NB_MMU_MODES` define
target/rx: Remove `NB_MMU_MODES` define
target/s390x: Remove `NB_MMU_MODES` define
target/sh4: Remove `NB_MMU_MODES` define
target/sparc: Remove `NB_MMU_MODES` define
target/tricore: Remove `NB_MMU_MODES` define
target/xtensa: Remove `NB_MMU_MODES` define
include/exec: Remove guards around `NB_MMU_MODES`
Richard Henderson (68):
target/mips: Drop tcg_temp_free from micromips_translate.c.inc
target/mips: Drop tcg_temp_free from msa_translate.c
target/mips: Drop tcg_temp_free from mxu_translate.c
target/mips: Drop tcg_temp_free from nanomips_translate.c.inc
target/mips: Drop tcg_temp_free from octeon_translate.c
target/mips: Drop tcg_temp_free from translate_addr_const.c
target/mips: Drop tcg_temp_free from tx79_translate.c
target/mips: Drop tcg_temp_free from vr54xx_translate.c
target/mips: Drop tcg_temp_free from translate.c
target/s390x: Drop free_compare
target/s390x: Drop tcg_temp_free from translate_vx.c.inc
target/s390x: Drop tcg_temp_free from translate.c
target/s390x: Remove assert vs g_in2
target/s390x: Remove g_out, g_out2, g_in1, g_in2 from DisasContext
tcg: Create tcg/tcg-temp-internal.h
target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS
target/avr: Avoid use of tcg_const_i32 throughout
target/cris: Avoid use of tcg_const_i32 throughout
target/hppa: Avoid tcg_const_i64 in trans_fid_f
target/hppa: Avoid use of tcg_const_i32 throughout
target/i386: Avoid use of tcg_const_* throughout
target/m68k: Avoid tcg_const_i32 when modified
target/m68k: Avoid tcg_const_i32 in bfop_reg
target/m68k: Avoid tcg_const_* throughout
target/mips: Split out gen_lxl
target/mips: Split out gen_lxr
target/mips: Avoid tcg_const_tl in gen_r6_ld
target/mips: Avoid tcg_const_* throughout
target/ppc: Split out gen_vx_vmul10
target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad
target/rx: Use tcg_gen_abs_i32
target/rx: Use cpu_psw_z as temp in flags computation
target/rx: Avoid tcg_const_i32 when new temp needed
target/rx: Avoid tcg_const_i32
target/s390x: Avoid tcg_const_i64
target/sh4: Avoid tcg_const_i32 for TAS.B
target/sh4: Avoid tcg_const_i32
tcg/sparc: Avoid tcg_const_tl in gen_edge
target/tricore: Split t_n as constant from temp as variable
target/tricore: Rename t_off10 and use tcg_constant_i32
target/tricore: Use setcondi instead of explicit allocation
target/tricore: Drop some temp initialization
target/tricore: Avoid tcg_const_i32
tcg: Replace tcg_const_i64 in tcg-op.c
target/arm: Use rmode >= 0 for need_rmode
target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf
target/arm: Improve arm_rmode_to_sf
target/arm: Consistently use ARMFPRounding during translation
target/arm: Create gen_set_rmode, gen_restore_rmode
target/arm: Improve trans_BFCI
target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}
target/arm: Avoid tcg_const_* in translate-mve.c
target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
target/arm: Avoid tcg_const_ptr in handle_rev
target/m68k: Use tcg_constant_i32 in gen_ea_mode
target/
[PULL v3 73/91] target/arm: Improve trans_BFCI
Reorg temporary usage so that we can use tcg_constant_i32.
tcg_gen_deposit_i32 already has a width == 32 special case,
so remove the check here.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index b70b628000..2cb9368b1b 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -7261,8 +7261,8 @@ static bool trans_UBFX(DisasContext *s, arg_UBFX *a)
static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
{
-TCGv_i32 tmp;
int msb = a->msb, lsb = a->lsb;
+TCGv_i32 t_in, t_rd;
int width;
if (!ENABLE_ARCH_6T2) {
@@ -7277,16 +7277,14 @@ static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
width = msb + 1 - lsb;
if (a->rn == 15) {
/* BFC */
-tmp = tcg_const_i32(0);
+t_in = tcg_constant_i32(0);
} else {
/* BFI */
-tmp = load_reg(s, a->rn);
+t_in = load_reg(s, a->rn);
}
-if (width != 32) {
-TCGv_i32 tmp2 = load_reg(s, a->rd);
-tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width);
-}
-store_reg(s, a->rd, tmp);
+t_rd = load_reg(s, a->rd);
+tcg_gen_deposit_i32(t_rd, t_rd, t_in, lsb, width);
+store_reg(s, a->rd, t_rd);
return true;
}
--
2.34.1
[PATCH RESEND v2 0/2] migration/xbzrle: fix two avx512 runtime issues
This patchset strives to fix two bugs at xvzrle when --enable-avx512 is used: an out-of-bounds write and an invalid argument to __builtin_ctz(). Those two errors can be seen in the test suite running: $ ../configure --target-list=aarch64-softmmu --enable-sanitizers --enable-avx512bw $ make tests/unit/test-xbzrle && ./tests/unit/test-xbzrle ==5518==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x6210b100 at pc 0x561109a7714d bp 0x7ffed712a440 sp 0x7ffed712a430 WRITE of size 1 at 0x6210b100 thread T0 #0 0x561109a7714c in uleb128_encode_small ../util/cutils.c:831 #1 0x561109b67f6a in xbzrle_encode_buffer_avx512 ../migration/xbzrle.c:275 #2 0x5611099a7428 in test_encode_decode_overflow ../tests/unit/test-xbzrle.c:153 #3 0x7fb2fb65a58d (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x7a58d) #4 0x7fb2fb65a333 (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x7a333) #5 0x7fb2fb65aa79 in g_test_run_suite (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x7aa79) #6 0x7fb2fb65aa94 in g_test_run (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x7aa94) #7 0x5611099a3a23 in main ../tests/unit/test-xbzrle.c:218 #8 0x7fb2fa78c082 in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x24082) #9 0x5611099a608d in _start (/qemu/build/tests/unit/test-xbzrle+0x28408d) 0x6210b100 is located 0 bytes to the right of 4096-byte region [0x6210a100,0x6210b100) allocated by thread T0 here: #0 0x7fb2fb823a06 in __interceptor_calloc ../../../../src/libsanitizer/asan/asan_malloc_linux.cc:153 #1 0x7fb2fb637ef0 in g_malloc0 (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x57ef0) ../migration/xbzrle.c:265: runtime error: passing zero to ctz(), which is not a valid argument v1: https://lore.kernel.org/qemu-devel/cover.1678199971.git.quic_mathb...@quicinc.com/ (No changes since v1, only rebased on current master) Matheus Tavares Bernardino (2): migration/xbzrle: use ctz64 to avoid undefined result migration/xbzrle: fix out-of-bounds write with axv512 migration/xbzrle.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.39.1
Re: [PATCH v3 0/9] virtio-gpu: Support Venus Vulkan driver
On Mon, Mar 13, 2023 at 5:58 AM Marc-André Lureau wrote: > > Hi Gurchetan > > On Tue, Mar 7, 2023 at 2:41 AM Gurchetan Singh > wrote: > > > > On Tue, Jan 31, 2023 at 3:15 PM Dmitry Osipenko > > wrote: > > > > > > Hello, > > > > > > On 1/30/23 20:00, Alex Bennée wrote: > > > > > > > > Antonio Caggiano writes: > > > > > > > >> This series of patches enables support for the Venus VirtIO-GPU Vulkan > > > >> driver by adding some features required by the driver: > > > >> > > > >> - CONTEXT_INIT > > > >> - HOSTMEM > > > >> - RESOURCE_UUID > > > >> - BLOB_RESOURCES > > > >> > > > >> In addition to these features, Venus capset support was required > > > >> together with the implementation for Virgl blob resource commands. > > > > > > > > I managed to apply to current master but I needed a bunch of patches to > > > > get it to compile with my old virgl: > > > > > > Thank you for reviewing and testing the patches! Antonio isn't working > > > on Venus anymore, I'm going to continue this effort. Last year we > > > stabilized some of the virglrenderer Venus APIs, this year Venus may > > > transition to supporting per-context fences only and require to init a > > > renderserver, which will result in a more changes to Qemu. I'm going to > > > wait a bit for Venus to settle down and then make a v4. > > > > > > In the end we will either need to add more #ifdefs if we will want to > > > keep supporting older virglrenderer versions in Qemu, or bump the min > > > required virglrenderer version. > > > > Hi Dmitry, > > > > Thanks for working on this, it's great to see QEMU graphics moving > > forward. I noticed a few things from your patchset: > > > > 1) Older versions of virglrenderer -- supported or not? > > > > As you alluded to, there have been significant changes to > > virglrenderer since the last QEMU graphics update. For example, the > > asynchronous callback introduces an entirely different and > > incompatible way to signal fence completion. > > > > Notionally, QEMU must support older versions of virglrenderer, though > > in practice I'm not sure how much that is true. If we want to keep up > > the notion that older versions must be supported, you'll need: > > > > a) virtio-gpu-virgl.c > > b) virtio-gpu-virgl2.c (or an equivalent) > > > > Similarly for the vhost-user paths (if you want to support that). If > > older versions of virglrenderer don't need to be supported, then that > > would simplify the amount of additional paths/#ifdefs. > > We should support old versions of virgl (as described in > https://www.qemu.org/docs/master/about/build-platforms.html#linux-os-macos-freebsd-netbsd-openbsd). > > Whether a new virtio-gpu-virgl2. (or equivalent) is necessary, we > can't really tell without seeing the changes involved. Ack. Something to keep in mind as Dmitry refactors. > > > > > 2) Additional context type: gfxstream [i]? > > > > One of the major motivations for adding context types in the > > virtio-gpu spec was supporting gfxstream. gfxstream is used in the > > Android Studio emulator (a variant of QEMU) [ii], among other places. > > That would move the Android emulator closer to the goal of using > > upstream QEMU for everything. > > What is the advantage of using gfxstream over virgl? or zink+venus? History/backstory: gfxstream development has its roots in the development of the Android Emulator (circa 2010). In those days, both DRM and Android were relatively new and the communities didn't know much about each other. A method was devised to auto-generate GLES calls (that's all Android needed) and stream it over an interface very similar to pipe(..). Host generated IDs were used to track shareable buffers. That same method used to auto-generate GLES was expanded to Vulkan and support for coherent memory was added. In 2018 the Android Emulator was the first to ship CTS-compliant virtualized Vulkan via downstream kernel interfaces, before work on venus began. As virtio-gpu continued to mature, gfxstream was actually the first to ship both blob resources [1] and context types [2] in production via crosvm to form a completely upstreamable solution (I consider AOSP to be an "upstream" as well). [1] https://patchwork.kernel.org/project/dri-devel/cover/20200814024000.2485-1-gurchetansi...@chromium.org/ [2] https://lists.oasis-open.org/archives/virtio-dev/202108/msg00141.html With this history out of the way, here are some advantages of gfxstream GLES over virgl: - gfxstream GLES actually has much less rendering artifacts than virgl since it's autogenerated and not hand-written. Using an Gallium command stream is lossy (partly since the GLES spec is ambiguous and drivers are buggy), and we always had better dEQP runs on gfxstream GLES than on virgl (especially on closed source drivers). - Better memory management: virgl makes heavy use of RESOURCE_CREATE_3D, which creates shadow buffers for every GL texture/buffer. gfxstream just uses a single guest memory buffer per DRM instance for
Re: [PATCH] MAINTAINERS: Remove CXL maintainer Ben Widawsky
Le 20/02/2023 à 22:24, Markus Armbruster a écrit : Ben is no longer with intel. He told me he expected to get back to CXL, but it's not happening as quickly as he'd like, and that it's best to remove him as maintainer. So let's do that. Thank you for serving as maintainer, Ben! Signed-off-by: Markus Armbruster --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index fd54c1f140..c3e83a1a47 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2630,7 +2630,6 @@ T: git https://gitlab.com/jsnow/qemu.git jobs T: git https://gitlab.com/vsementsov/qemu.git block Compute Express Link -M: Ben Widawsky M: Jonathan Cameron S: Supported F: hw/cxl/ Applied to my trivial-patches branch. Thanks, Laurent
[PATCH] MAINTAINERS: Mark the Nios II CPU as orphan
Marek and Chris haven't been active for Nios II since years (the last time seems to have been in 2017), and we've got unhandled severe Nios II bug tickets in the bug tracker since a long time, so to avoid wrong expectations of people who are looking at the MAINTAINERS file, it's maybe best to mark the Nios II entry as orphan nowadays. Suggested-by: Richard Henderson Signed-off-by: Thomas Huth --- Suggested by Richard here: https://lore.kernel.org/qemu-devel/cb2e92b7-40bb-4975-290d-6321c5574...@linaro.org/ And bugs like this sound like the linux-user target is in a bad shape, too: https://gitlab.com/qemu-project/qemu/-/issues/261 See also: https://bugs.launchpad.net/qemu/+bug/1791796 (comment 3) ... nobody tried to fix nios2 linux-user in years, maybe we should deprecate it? MAINTAINERS | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 95c957d587..9780430626 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -257,9 +257,9 @@ F: docs/system/cpu-models-mips.rst.inc F: tests/tcg/mips/ NiosII TCG CPUs -M: Chris Wulff -M: Marek Vasut -S: Maintained +R: Chris Wulff +R: Marek Vasut +S: Orphan F: target/nios2/ F: hw/nios2/ F: disas/nios2.c -- 2.31.1
Re: [PATCH v4] target/arm: Add Neoverse-N1 registers
W dniu 13.03.2023 o 04:39, Chen Baozi pisze: Add implementation defined registers for neoverse-n1 which would be accessed by TF-A. Since there is no DSU in Qemu, CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition. Signed-off-by: Chen Baozi Tested-by: Marcin Juszkiewicz ~ # cat /proc/cpuinfo processor : 0 BogoMIPS: 125.00 Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x4 CPU part: 0xd0c CPU revision: 1
Re: [PATCH] MAINTAINERS: update my email address for the clock framework
Le 13/02/2023 à 11:53, Damien Hedde a écrit : Also update mailmap Signed-off-by: Damien Hedde --- MAINTAINERS | 2 +- .mailmap| 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 96e25f62ac..ceeda49d49 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3321,7 +3321,7 @@ F: .gitlab-ci.d/opensbi/ Clock framework M: Luc Michel -R: Damien Hedde +R: Damien Hedde S: Maintained F: include/hw/clock.h F: include/hw/qdev-clock.h diff --git a/.mailmap b/.mailmap index fad2aff5aa..7677047950 100644 --- a/.mailmap +++ b/.mailmap @@ -56,6 +56,7 @@ Aleksandar Rikalo Alexander Graf Anthony Liguori Anthony Liguori Christian Borntraeger +Damien Hedde Filip Bozuta Frederic Konrad Frederic Konrad -- 2.37.0 Applied to my trivial-patches branch. Thanks, Laurent
Re: [PATCH 10/11] include/exec: fix kerneldoc definition
On Mon, 13 Mar 2023 at 17:30, Peter Maydell wrote: > So I think the problem here is not with Sphinx, but with the > kernel-doc script. That script has an option "-Werror" which > turns its warnings into errors, but our Sphinx extension > docs/sphinx/kerneldoc.py does not set it. I think we need to > have the extension say "if Sphinx was run with -W then > pass this flag along" (hopefully Sphinx lets us find out...) This works: --- a/docs/sphinx/kerneldoc.py +++ b/docs/sphinx/kerneldoc.py @@ -74,6 +74,10 @@ def run(self): # Sphinx versions cmd += ['-sphinx-version', sphinx.__version__] +# Pass through the warnings-as-errors flag if appropriate +if env.app.warningiserror: +cmd += ['-Werror'] + filename = env.config.kerneldoc_srctree + '/' + self.arguments[0] export_file_patterns = [] but I think it's prodding undocumented Sphinx internals, so I'm going to check whether there's a better way to do this. It might be more robust to have meson create a commandline with a -Dkerneldoc_werror option that we then pick up in the extension code, rather than trying to find out whether -W was passed. -- PMM
[RFC 1/2] vhost-user: Add interface for virtio-fs migration
Add a virtio-fs-specific vhost-user interface to facilitate migrating
back-end-internal state. We plan to migrate the internal state simply
as a binary blob after the streaming phase, so all we need is a way to
transfer such a blob from and to the back-end. We do so by using a
dedicated area of shared memory through which the blob is transferred in
chunks.
This patch adds the following vhost operations (and implements them for
vhost-user):
- FS_SET_STATE_FD: The front-end passes a dedicated shared memory area
to the back-end. This area will be used to transfer state via the
other two operations.
(After the transfer FS_SET_STATE_FD detaches the shared memory area
again.)
- FS_GET_STATE: The front-end asks the back-end to place a chunk of
internal state into the shared memory area.
- FS_SET_STATE: The front-end puts a chunk of internal state into the
shared memory area, and asks the back-end to fetch it.
On the source side, the back-end is expected to serialize its internal
state either when FS_SET_STATE_FD is invoked, or when FS_GET_STATE is
invoked the first time. On subsequent FS_GET_STATE calls, it memcpy()s
parts of that serialized state into the shared memory area.
On the destination side, the back-end is expected to collect the state
blob over all FS_SET_STATE calls, and then deserialize and apply it once
FS_SET_STATE_FD detaches the shared memory area.
Signed-off-by: Hanna Czenczek
---
include/hw/virtio/vhost-backend.h | 9 ++
include/hw/virtio/vhost.h | 68 +++
hw/virtio/vhost-user.c| 138 ++
hw/virtio/vhost.c | 29 +++
4 files changed, 244 insertions(+)
diff --git a/include/hw/virtio/vhost-backend.h
b/include/hw/virtio/vhost-backend.h
index ec3fbae58d..fa3bd19386 100644
--- a/include/hw/virtio/vhost-backend.h
+++ b/include/hw/virtio/vhost-backend.h
@@ -42,6 +42,12 @@ typedef int (*vhost_backend_init)(struct vhost_dev *dev,
void *opaque,
typedef int (*vhost_backend_cleanup)(struct vhost_dev *dev);
typedef int (*vhost_backend_memslots_limit)(struct vhost_dev *dev);
+typedef ssize_t (*vhost_fs_get_state_op)(struct vhost_dev *dev,
+ uint64_t state_offset, size_t size);
+typedef int (*vhost_fs_set_state_op)(struct vhost_dev *dev,
+ uint64_t state_offset, size_t size);
+typedef int (*vhost_fs_set_state_fd_op)(struct vhost_dev *dev, int memfd,
+size_t size);
typedef int (*vhost_net_set_backend_op)(struct vhost_dev *dev,
struct vhost_vring_file *file);
typedef int (*vhost_net_set_mtu_op)(struct vhost_dev *dev, uint16_t mtu);
@@ -138,6 +144,9 @@ typedef struct VhostOps {
vhost_backend_init vhost_backend_init;
vhost_backend_cleanup vhost_backend_cleanup;
vhost_backend_memslots_limit vhost_backend_memslots_limit;
+vhost_fs_get_state_op vhost_fs_get_state;
+vhost_fs_set_state_op vhost_fs_set_state;
+vhost_fs_set_state_fd_op vhost_fs_set_state_fd;
vhost_net_set_backend_op vhost_net_set_backend;
vhost_net_set_mtu_op vhost_net_set_mtu;
vhost_scsi_set_endpoint_op vhost_scsi_set_endpoint;
diff --git a/include/hw/virtio/vhost.h b/include/hw/virtio/vhost.h
index a52f273347..b1ad9785dd 100644
--- a/include/hw/virtio/vhost.h
+++ b/include/hw/virtio/vhost.h
@@ -336,4 +336,72 @@ int vhost_dev_set_inflight(struct vhost_dev *dev,
struct vhost_inflight *inflight);
int vhost_dev_get_inflight(struct vhost_dev *dev, uint16_t queue_size,
struct vhost_inflight *inflight);
+
+/**
+ * vhost_fs_set_state_fd(): Share memory with a virtio-fs vhost
+ * back-end for transferring internal state for the purpose of
+ * migration. Calling this function again will have the back-end
+ * unregister (free) the previously shared memory area.
+ *
+ * @dev: The vhost device
+ * @memfd: File descriptor associated with the shared memory to share.
+ * If negative, no memory area is shared, only releasing the
+ * previously shared area, and announcing the end of transfer
+ * (which, on the destination side, should lead to the
+ * back-end deserializing and applying the received state).
+ * @size: Size of the shared memory area
+ *
+ * Returns 0 on success, and -errno on failure.
+ */
+int vhost_fs_set_state_fd(struct vhost_dev *dev, int memfd, size_t size);
+
+/**
+ * vhost_fs_get_state(): Request the virtio-fs vhost back-end to place
+ * a chunk of migration state into the shared memory area negotiated
+ * through vhost_fs_set_state_fd(). May only be used for migration,
+ * and only by the source side.
+ *
+ * The back-end-internal migration state is treated as a binary blob,
+ * which is transferred in chunks to fit into the shared memory area.
+ *
+ * @dev: The vhost device
+ * @state_offset: Offset into the state blob of the first byte to be
+ *
[RFC 2/2] vhost-user-fs: Implement stateful migration
A virtio-fs device's VM state consists of:
- the virtio device (vring) state (VMSTATE_VIRTIO_DEVICE)
- the back-end's (virtiofsd's) internal state
We get/set the latter via the new vhost-user operations FS_SET_STATE_FD,
FS_GET_STATE, and FS_SET_STATE.
Signed-off-by: Hanna Czenczek
---
hw/virtio/vhost-user-fs.c | 171 +-
1 file changed, 170 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vhost-user-fs.c b/hw/virtio/vhost-user-fs.c
index 83fc20e49e..df1fb02acc 100644
--- a/hw/virtio/vhost-user-fs.c
+++ b/hw/virtio/vhost-user-fs.c
@@ -20,8 +20,10 @@
#include "hw/virtio/virtio-bus.h"
#include "hw/virtio/virtio-access.h"
#include "qemu/error-report.h"
+#include "qemu/memfd.h"
#include "hw/virtio/vhost.h"
#include "hw/virtio/vhost-user-fs.h"
+#include "migration/qemu-file-types.h"
#include "monitor/monitor.h"
#include "sysemu/sysemu.h"
@@ -298,9 +300,176 @@ static struct vhost_dev *vuf_get_vhost(VirtIODevice *vdev)
return >vhost_dev;
}
+/**
+ * Fetch the internal state from the back-end (virtiofsd) and save it
+ * to `f`.
+ */
+static int vuf_save_state(QEMUFile *f, void *pv, size_t size,
+ const VMStateField *field, JSONWriter *vmdesc)
+{
+VirtIODevice *vdev = pv;
+VHostUserFS *fs = VHOST_USER_FS(vdev);
+int memfd = -1;
+/* Size of the shared memory through which to transfer the state */
+const size_t chunk_size = 4 * 1024 * 1024;
+size_t state_offset;
+ssize_t remaining;
+void *shm_buf;
+Error *local_err = NULL;
+int ret, ret2;
+
+/* Set up shared memory through which to receive the state from virtiofsd
*/
+shm_buf = qemu_memfd_alloc("vhost-fs-state", chunk_size,
+ F_SEAL_SEAL | F_SEAL_SHRINK | F_SEAL_GROW,
+ , _err);
+if (!shm_buf) {
+error_report_err(local_err);
+ret = -ENOMEM;
+goto early_fail;
+}
+
+/* Share the SHM area with virtiofsd */
+ret = vhost_fs_set_state_fd(>vhost_dev, memfd, chunk_size);
+if (ret < 0) {
+goto early_fail;
+}
+
+/* Receive the virtiofsd state in chunks, and write them to `f` */
+state_offset = 0;
+do {
+size_t this_chunk_size;
+
+remaining = vhost_fs_get_state(>vhost_dev, state_offset,
+ chunk_size);
+if (remaining < 0) {
+ret = remaining;
+goto fail;
+}
+
+/* Prefix the whole state by its total length */
+if (state_offset == 0) {
+qemu_put_be64(f, remaining);
+}
+
+this_chunk_size = MIN(remaining, chunk_size);
+qemu_put_buffer(f, shm_buf, this_chunk_size);
+state_offset += this_chunk_size;
+} while (remaining >= chunk_size);
+
+ret = 0;
+fail:
+/* Have virtiofsd close the shared memory */
+ret2 = vhost_fs_set_state_fd(>vhost_dev, -1, 0);
+if (ret2 < 0) {
+error_report("Failed to remove state FD from the vhost-user-fs back "
+ "end: %s", strerror(-ret));
+if (ret == 0) {
+ret = ret2;
+}
+}
+
+early_fail:
+if (shm_buf) {
+qemu_memfd_free(shm_buf, chunk_size, memfd);
+}
+
+return ret;
+}
+
+/**
+ * Load the back-end's (virtiofsd's) internal state from `f` and send
+ * it over to that back-end.
+ */
+static int vuf_load_state(QEMUFile *f, void *pv, size_t size,
+ const VMStateField *field)
+{
+VirtIODevice *vdev = pv;
+VHostUserFS *fs = VHOST_USER_FS(vdev);
+int memfd = -1;
+/* Size of the shared memory through which to transfer the state */
+const size_t chunk_size = 4 * 1024 * 1024;
+size_t state_offset;
+uint64_t remaining;
+void *shm_buf;
+Error *local_err = NULL;
+int ret, ret2;
+
+/* The state is prefixed by its total length, read that first */
+remaining = qemu_get_be64(f);
+
+/* Set up shared memory through which to send the state to virtiofsd */
+shm_buf = qemu_memfd_alloc("vhost-fs-state", chunk_size,
+ F_SEAL_SEAL | F_SEAL_SHRINK | F_SEAL_GROW,
+ , _err);
+if (!shm_buf) {
+error_report_err(local_err);
+ret = -ENOMEM;
+goto early_fail;
+}
+
+/* Share the SHM area with virtiofsd */
+ret = vhost_fs_set_state_fd(>vhost_dev, memfd, chunk_size);
+if (ret < 0) {
+goto early_fail;
+}
+
+/*
+ * Read the virtiofsd state in chunks from `f`, and send them over
+ * to virtiofsd
+ */
+state_offset = 0;
+do {
+size_t this_chunk_size = MIN(remaining, chunk_size);
+
+if (qemu_get_buffer(f, shm_buf, this_chunk_size) < this_chunk_size) {
+ret = -EINVAL;
+goto fail;
+}
+
+ret = vhost_fs_set_state(>vhost_dev, state_offset,
this_chunk_size);
+if (ret < 0) {
+goto fail;
+}
+
+
[RFC 0/2] vhost-user-fs: Stateful migration
Hi, Patch 1 of this RFC series adds virtio-fs-specific operations to vhost for transferring a binary blob of back-end-internal state, and implements those for vhost-user. Patch 2 uses those operations to implement stateful migration for vhost-user-fs devices, assuming the back-end (virtiofsd) supports it. This is an RFC for multiple reasons, most notably: - Patch 1 proposes yet undiscussed changes to the vhost protocol, which makes it RFC by default. - Without much experience in the fields of migration or vhost (on the qemu side), I hope marking this as an RFC leads to extra scrutiny on the reviewerâs side. O:) Hanna Czenczek (2): vhost-user: Add interface for virtio-fs migration vhost-user-fs: Implement stateful migration include/hw/virtio/vhost-backend.h | 9 ++ include/hw/virtio/vhost.h | 68 hw/virtio/vhost-user-fs.c | 171 +- hw/virtio/vhost-user.c| 138 hw/virtio/vhost.c | 29 + 5 files changed, 414 insertions(+), 1 deletion(-) -- 2.39.1
Re: [PATCH v2] qemu-options.hx: remove stray quote
Le 02/02/2023 à 23:31, John Snow a écrit : Signed-off-by: John Snow --- qemu-options.hx | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu-options.hx b/qemu-options.hx index d59d19704bc..52d477547f5 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -1606,7 +1606,7 @@ SRST .. parsed-literal:: -|qemu_system_x86| -drive file=a -drive file=b" +|qemu_system_x86| -drive file=a -drive file=b is interpreted like: Applied to my trivial-patches branch. Thanks, Laurent
Re: [PATCH 10/11] include/exec: fix kerneldoc definition
On Mon, 13 Mar 2023 at 17:14, Thomas Huth wrote:
>
> On 13/03/2023 18.03, Peter Maydell wrote:
> > On Mon, 13 Mar 2023 at 17:00, Thomas Huth wrote:
> >> I also keep running into this problem ... I wonder whether we should run
> >> sphinx with "-W" to turn warnings into errors when configure has been run
> >> with --enable-werror ...?
> >
> > We certainly try to do that: docs/meson.build says:
> >
> ># If we're making warnings fatal, apply this to Sphinx runs as well
> >if get_option('werror')
> > SPHINX_ARGS += [ '-W' ]
> >endif
> >
> > Has that broken ?
>
> It apparently does not work in our CI, see e.g.:
>
> https://gitlab.com/qemu-project/qemu/-/jobs/3922732898#L1420
>
> ... there is a warning here, but the job succeeded happily.
Specifically:
/builds/qemu-project/qemu/docs/../include/exec/memory.h:1741: warning:
Function parameter or member 'n' not described in
'memory_region_unmap_iommu_notifier_range'
/builds/qemu-project/qemu/docs/../include/exec/memory.h:1741: warning:
Excess function parameter 'notifier' description in
'memory_region_unmap_iommu_notifier_range'
ninja: bad depfile: multiple outputs:
/builds/qemu-project/qemu/docs/devel/secure-coding-practices.rst !=
docs/docs.stamp
Also, what's that 'bad depfile' warning from ninja about ??
I looked at the build.ninja file (which you can fish out of
the artifacts for this build), and it shows that we are
passing -W to sphinx-build:
build docs/docs.stamp: CUSTOM_COMMAND_DEP ../docs/conf.py |
/usr/bin/env /usr/bin/sphinx-build
DEPFILE = docs/docs.d
DEPFILE_UNQUOTED = docs/docs.d
COMMAND = /usr/bin/env CONFDIR=etc/qemu /usr/bin/sphinx-build -q -W
-Dversion=7.2.50 -Drelease= -Ddepfile=docs/docs.d
-Ddepfile_stamp=docs/docs.stamp -b html -d
/builds/qemu-project/qemu/build/docs/manual.p
/builds/qemu-project/qemu/docs
/builds/qemu-project/qemu/build/docs/manual
description = Generating$ docs/QEMU$ manual$ with$ a$ custom$ command
So I think the problem here is not with Sphinx, but with the
kernel-doc script. That script has an option "-Werror" which
turns its warnings into errors, but our Sphinx extension
docs/sphinx/kerneldoc.py does not set it. I think we need to
have the extension say "if Sphinx was run with -W then
pass this flag along" (hopefully Sphinx lets us find out...)
thanks
-- PMM
[PATCH] Use f-strings in python scripts
Replace python 2 format string with f-strings
Signed-off-by: Marco Liebel
---
target/hexagon/gen_helper_funcs.py | 54 ++--
target/hexagon/gen_helper_protos.py | 10 +-
target/hexagon/gen_idef_parser_funcs.py | 8 +-
target/hexagon/gen_op_attribs.py| 4 +-
target/hexagon/gen_op_regs.py | 10 +-
target/hexagon/gen_opcodes_def.py | 2 +-
target/hexagon/gen_printinsn.py | 14 +-
target/hexagon/gen_shortcode.py | 2 +-
target/hexagon/gen_tcg_func_table.py| 2 +-
target/hexagon/gen_tcg_funcs.py | 317 +++-
target/hexagon/hex_common.py| 4 +-
11 files changed, 198 insertions(+), 229 deletions(-)
diff --git a/target/hexagon/gen_helper_funcs.py
b/target/hexagon/gen_helper_funcs.py
index 7a224b66e6..dc67eaf716 100755
--- a/target/hexagon/gen_helper_funcs.py
+++ b/target/hexagon/gen_helper_funcs.py
@@ -38,23 +38,23 @@ def gen_helper_return_type_pair(f,regtype,regid,regno):
def gen_helper_arg(f,regtype,regid,regno):
if regno > 0 : f.write(", " )
-f.write("int32_t %s%sV" % (regtype,regid))
+f.write(f"int32_t {regtype}{regid}V")
def gen_helper_arg_new(f,regtype,regid,regno):
if regno >= 0 : f.write(", " )
-f.write("int32_t %s%sN" % (regtype,regid))
+f.write(f"int32_t {regtype}{regid}N")
def gen_helper_arg_pair(f,regtype,regid,regno):
if regno >= 0 : f.write(", ")
-f.write("int64_t %s%sV" % (regtype,regid))
+f.write(f"int64_t {regtype}{regid}V")
def gen_helper_arg_ext(f,regtype,regid,regno):
if regno > 0 : f.write(", ")
-f.write("void *%s%sV_void" % (regtype,regid))
+f.write(f"void *{regtype}{regid}V_void")
def gen_helper_arg_ext_pair(f,regtype,regid,regno):
if regno > 0 : f.write(", ")
-f.write("void *%s%sV_void" % (regtype,regid))
+f.write(f"void *{regtype}{regid}V_void")
def gen_helper_arg_opn(f,regtype,regid,i,tag):
if (hex_common.is_pair(regid)):
@@ -76,27 +76,25 @@ def gen_helper_arg_opn(f,regtype,regid,i,tag):
print("Bad register parse: ",regtype,regid,toss,numregs)
def gen_helper_arg_imm(f,immlett):
-f.write(", int32_t %s" % (hex_common.imm_name(immlett)))
+f.write(f", int32_t {hex_common.imm_name(immlett)}")
def gen_helper_dest_decl(f,regtype,regid,regno,subfield=""):
-f.write("int32_t %s%sV%s = 0;\n" % \
-(regtype,regid,subfield))
+f.write(f"int32_t {regtype}{regid}V{subfield} = 0;\n")
def gen_helper_dest_decl_pair(f,regtype,regid,regno,subfield=""):
-f.write("int64_t %s%sV%s = 0;\n" % \
-(regtype,regid,subfield))
+f.write(f"int64_t {regtype}{regid}V{subfield} = 0;\n")
def gen_helper_dest_decl_ext(f,regtype,regid):
if (regtype == "Q"):
-f.write("/* %s%sV is *(MMQReg *)(%s%sV_void) */\n" % \
-(regtype,regid,regtype,regid))
+f.write(f"/* {regtype}{regid}V is *(MMQReg *)"
+f"({regtype}{regid}V_void) */\n")
else:
-f.write("/* %s%sV is *(MMVector *)(%s%sV_void) */\n" % \
-(regtype,regid,regtype,regid))
+f.write(f"/* {regtype}{regid}V is *(MMVector *)"
+f"({regtype}{regid}V_void) */\n")
def gen_helper_dest_decl_ext_pair(f,regtype,regid,regno):
-f.write("/* %s%sV is *(MMVectorPair *))%s%sV_void) */\n" % \
-(regtype,regid,regtype, regid))
+f.write(f"/* {regtype}{regid}V is *(MMVectorPair *))"
+f"{regtype}{regid}V_void) */\n")
def gen_helper_dest_decl_opn(f,regtype,regid,i):
if (hex_common.is_pair(regid)):
@@ -114,21 +112,21 @@ def gen_helper_dest_decl_opn(f,regtype,regid,i):
def gen_helper_src_var_ext(f,regtype,regid):
if (regtype == "Q"):
- f.write("/* %s%sV is *(MMQReg *)(%s%sV_void) */\n" % \
- (regtype,regid,regtype,regid))
+ f.write(f"/* {regtype}{regid}V is *(MMQReg *)"
+ f"({regtype}{regid}V_void) */\n")
else:
- f.write("/* %s%sV is *(MMVector *)(%s%sV_void) */\n" % \
- (regtype,regid,regtype,regid))
+ f.write(f"/* {regtype}{regid}V is *(MMVector *)"
+ f"({regtype}{regid}V_void) */\n")
def gen_helper_src_var_ext_pair(f,regtype,regid,regno):
-f.write("/* %s%sV%s is *(MMVectorPair *)(%s%sV%s_void) */\n" % \
-(regtype,regid,regno,regtype,regid,regno))
+f.write(f"/* {regtype}{regid}V{regno} is *(MMVectorPair *)"
+f"({regtype}{regid}V{regno}_void) */\n")
def gen_helper_return(f,regtype,regid,regno):
-f.write("return %s%sV;\n" % (regtype,regid))
+f.write(f"return {regtype}{regid}V;\n")
def gen_helper_return_pair(f,regtype,regid,regno):
-f.write("return %s%sV;\n" % (regtype,regid))
+f.write(f"return {regtype}{regid}V;\n")
def gen_helper_dst_write_ext(f,regtype,regid):
return
@@ -181,8 +179,8 @@ def gen_helper_function(f, tag, tagregs, tagimms):
if (numscalarresults > 1):
## The helper is
Re: [PATCH v7 0/6] memory: prevent dma-reentracy issues
On 230313 1608, Peter Maydell wrote: > On Mon, 13 Mar 2023 at 15:41, Philippe Mathieu-Daudé > wrote: > > Now I wonder again if this is a good time to merge this change set. > > No, I don't think it is at this point in the release > cycle. I would vote for merging it when we reopen for 8.1, > so that we'll have a full cycle to find all the weird corner > cases that it breaks. Ok. I'll fix the rasbpi issue and look into adding some compile-time option to make the re-entrancy check fatal. That way we might catch additional edge-cases with fuzzing (though non-x86 coverage is poor) and unit-tests. -Alex
Re: [PATCH 10/11] include/exec: fix kerneldoc definition
On 13/03/2023 18.03, Peter Maydell wrote:
On Mon, 13 Mar 2023 at 17:00, Thomas Huth wrote:
On 10/03/2023 11.31, Alex Bennée wrote:
The kerneldoc processor complains about the mismatched variable name.
Fix it.
Signed-off-by: Alex Bennée
---
include/exec/memory.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 6fa0b071f0..15ade918ba 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -1738,7 +1738,7 @@ void memory_region_notify_iommu_one(IOMMUNotifier
*notifier,
*
* @notifier: the notifier to be notified
*/
-void memory_region_unmap_iommu_notifier_range(IOMMUNotifier *n);
+void memory_region_unmap_iommu_notifier_range(IOMMUNotifier *notifier);
I also keep running into this problem ... I wonder whether we should run
sphinx with "-W" to turn warnings into errors when configure has been run
with --enable-werror ...?
We certainly try to do that: docs/meson.build says:
# If we're making warnings fatal, apply this to Sphinx runs as well
if get_option('werror')
SPHINX_ARGS += [ '-W' ]
endif
Has that broken ?
It apparently does not work in our CI, see e.g.:
https://gitlab.com/qemu-project/qemu/-/jobs/3922732898#L1420
... there is a warning here, but the job succeeded happily.
Thomas
Re: [PULL v2 00/25] Win socket patches
On Mon, 13 Mar 2023 at 11:46, wrote: > > From: Marc-André Lureau > > The following changes since commit 29c8a9e31a982874ce4e2c15f2bf82d5f8dc3517: > > Merge tag 'linux-user-for-8.0-pull-request' of > https://gitlab.com/laurent_vivier/qemu into staging (2023-03-12 10:57:00 > +) > > are available in the Git repository at: > > https://gitlab.com/marcandre.lureau/qemu.git tags/win-socket-pull-request > > for you to fetch changes up to 4bf21c7f748bee42b6f4692f8c37a11d1033b2d1: > > monitor: restrict command getfd to POSIX hosts (2023-03-13 15:46:09 +0400) > > > QMP command to import win32 sockets > > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0 for any user-visible changes. -- PMM
Re: [PATCH 09/10] Python: Drop support for Python 3.6
On Wed, Feb 22, 2023 at 03:37:51PM +0100, Paolo Bonzini wrote:
> Python 3.6 was EOL 2021-12-31. Newer versions of upstream libraries have
> begun dropping support for this version and it is becoming more
> cumbersome to support. Avocado-framework and qemu.qmp each have their
> own reasons for wanting to drop Python 3.6, but won't until QEMU does.
>
> Versions of Python available in our supported build platforms as of today,
> with optional versions available in parentheses:
>
> openSUSE Leap 15.4: 3.6.15 (3.9.10, 3.10.2)
> CentOS Stream 8:3.6.8 (3.8.13, 3.9.16)
> CentOS Stream 9:3.9.13
> Fedora 36: 3.10
> Fedora 37: 3.11
> Debian 11: 3.9.2
> Alpine 3.14, 3.15: 3.9.16
> Alpine 3.16, 3.17: 3.10.10
> Ubuntu 20.04 LTS: 3.8.10
> Ubuntu 22.04 LTS: 3.10.4
> NetBSD 9.3: 3.9.13*
> FreeBSD 12.4: 3.9.16
> FreeBSD 13.1: 3.9.16
> OpenBSD 7.2:3.9.16
>
> Note: Our VM tests install 3.7 specifically for freebsd and netbsd; the
> default for "python" or "python3" in FreeBSD is 3.9.16. NetBSD does not
> appear to have a default meta-package, but offers several options, the
> lowest of which is 3.7.15. "python39" appears to be a pre-requisite to
> one of the other packages we request in tests/vm/netbsd.
>
> Since it is safe to under our supported platform policy, bump our
> minimum supported version of Python to 3.7.
In the above list of versions, there's no platform which actually
has 3.7 as a limiting factor. THe only mention of 3.7 comes from
our own VM scripts, which for freebsd is outdated compared to
their default, and for netbsd the 3.7 choice appears arbitrary
on our side given their lack of default.
Ubuntu 20.04 on 3.8 would be the hard constraint out of the above
list of distros.
Our normal practice wrt the support policy would be to go to the
baseline from the above distro list. IOW, if we're dropping 3.6,
then going to 3.8 would be the normal course of action, rather
than stopping at 3.7 which doesn't appear needed by our targetted
distros.
>
> Signed-off-by: John Snow
> Signed-off-by: Paolo Bonzini
> ---
> configure| 8
> python/Makefile | 10 +-
> python/setup.cfg | 7 +++
> python/tests/minreqs.txt | 2 +-
> scripts/qapi/mypy.ini| 2 +-
> 5 files changed, 14 insertions(+), 15 deletions(-)
>
> diff --git a/configure b/configure
> index 762b8397a7b7..476d8a38b900 100755
> --- a/configure
> +++ b/configure
> @@ -594,9 +594,9 @@ esac
>
>
> check_py_version() {
> -# We require python >= 3.6.
> +# We require python >= 3.7.
> # NB: a True python conditional creates a non-zero return code (Failure)
> -"$1" -c 'import sys; sys.exit(sys.version_info < (3,6))'
> +"$1" -c 'import sys; sys.exit(sys.version_info < (3,7))'
> }
>
> python=
> @@ -605,7 +605,7 @@ if test -z "${PYTHON}"; then
> explicit_python=no
> # A bare 'python' is traditionally python 2.x, but some distros
> # have it as python 3.x, so check in both places.
> -for binary in python3 python python3.11 python3.10 python3.9 python3.8
> python3.7 python3.6; do
> +for binary in python3 python python3.11 python3.10 python3.9 python3.8
> python3.7; do
> if has "$binary"; then
> python=$(command -v "$binary")
> if check_py_version "$python"; then
> @@ -1069,7 +1069,7 @@ then
> fi
>
> if ! check_py_version "$python"; then
> - error_exit "Cannot use '$python', Python >= 3.6 is required." \
> + error_exit "Cannot use '$python', Python >= 3.7 is required." \
>"Use --python=/path/to/python to specify a supported Python."
> fi
>
> diff --git a/python/Makefile b/python/Makefile
> index c5bd6ff83ac9..f660d9991437 100644
> --- a/python/Makefile
> +++ b/python/Makefile
> @@ -9,14 +9,14 @@ help:
> @echo "make check-minreqs:"
> @echo "Run tests in the minreqs virtual environment."
> @echo "These tests use the oldest dependencies."
> - @echo "Requires: Python 3.6"
> - @echo "Hint (Fedora): 'sudo dnf install python3.6'"
> + @echo "Requires: Python 3.7"
> + @echo "Hint (Fedora): 'sudo dnf install python3.7'"
> @echo ""
> @echo "make check-tox:"
> @echo "Run tests against multiple python versions."
> @echo "These tests use the newest dependencies."
> - @echo "Requires: Python 3.6 - 3.10, and tox."
> - @echo "Hint (Fedora): 'sudo dnf install python3-tox python3.10'"
> + @echo "Requires: Python 3.7 - 3.11, and tox."
> + @echo "Hint (Fedora): 'sudo dnf install python3-tox python3.11'"
> @echo "The variable QEMU_TOX_EXTRA_ARGS can be use to pass extra"
> @echo "arguments to tox".
> @echo ""
> @@ -58,7 +58,7 @@ pipenv check-pipenv:
> min-venv: $(QEMU_MINVENV_DIR) $(QEMU_MINVENV_DIR)/bin/activate
> $(QEMU_MINVENV_DIR) $(QEMU_MINVENV_DIR)/bin/activate: setup.cfg
> tests/minreqs.txt
>
Re: [PATCH 10/11] include/exec: fix kerneldoc definition
On Mon, 13 Mar 2023 at 17:00, Thomas Huth wrote:
>
> On 10/03/2023 11.31, Alex Bennée wrote:
> > The kerneldoc processor complains about the mismatched variable name.
> > Fix it.
> >
> > Signed-off-by: Alex Bennée
> > ---
> > include/exec/memory.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/include/exec/memory.h b/include/exec/memory.h
> > index 6fa0b071f0..15ade918ba 100644
> > --- a/include/exec/memory.h
> > +++ b/include/exec/memory.h
> > @@ -1738,7 +1738,7 @@ void memory_region_notify_iommu_one(IOMMUNotifier
> > *notifier,
> >*
> >* @notifier: the notifier to be notified
> >*/
> > -void memory_region_unmap_iommu_notifier_range(IOMMUNotifier *n);
> > +void memory_region_unmap_iommu_notifier_range(IOMMUNotifier *notifier);
>
> I also keep running into this problem ... I wonder whether we should run
> sphinx with "-W" to turn warnings into errors when configure has been run
> with --enable-werror ...?
We certainly try to do that: docs/meson.build says:
# If we're making warnings fatal, apply this to Sphinx runs as well
if get_option('werror')
SPHINX_ARGS += [ '-W' ]
endif
Has that broken ?
-- PMM
Re: [PATCH 10/11] include/exec: fix kerneldoc definition
On 10/03/2023 11.31, Alex Bennée wrote: The kerneldoc processor complains about the mismatched variable name. Fix it. Signed-off-by: Alex Bennée --- include/exec/memory.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/memory.h b/include/exec/memory.h index 6fa0b071f0..15ade918ba 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1738,7 +1738,7 @@ void memory_region_notify_iommu_one(IOMMUNotifier *notifier, * * @notifier: the notifier to be notified */ -void memory_region_unmap_iommu_notifier_range(IOMMUNotifier *n); +void memory_region_unmap_iommu_notifier_range(IOMMUNotifier *notifier); I also keep running into this problem ... I wonder whether we should run sphinx with "-W" to turn warnings into errors when configure has been run with --enable-werror ...? Anyway, for this patch here: Reviewed-by: Thomas Huth
Re: [PATCH v1] hw/pvrdma: Protect against buggy or malicious guest driver
Hello! INC2534320 ([PATCH v1] hw/pvrdma: Protect against buggy or malicious guest driver) has been updated. Opened for: yuval.shaia...@gmail.com Followers: qemu-devel@nongnu.org, soulchen8...@gmail.com, Mauro Matteo Cascella, qemu-secur...@nongnu.org, yuval.shaia...@gmail.com, marcel.apfelb...@gmail.com A Guest updated your request with the following comments: Reply from: p...@fedoraproject.org [mailto:p...@fedoraproject.org] Hello Yuval, How can I track and update my request? To respond, reply to this email. You may also create a new email and include the request number (INC2534320) in the subject. Thank you, Product Security Ref:MSG71528958
Re: [PATCH for-8.0] ide: Fix manual in-flight count for TRIM BH
Am 10.03.2023 um 16:13 hat Paolo Bonzini geschrieben: > On Fri, Mar 10, 2023 at 3:25 PM Kevin Wolf wrote: > > > 1. The TRIM operation should be completed on the IDE level before > > > draining ends. > > > 2. Block layer requests issued after draining has begun are queued. > > > > > > To me, the conclusion seems to be: > > > Issue all block layer requests belonging to the IDE TRIM operation up > > > front. > > > > > > The other alternative I see is to break assumption 2, introduce a way > > > to not queue certain requests while drained, and use it for the > > > recursive requests issued by ide_issue_trim_cb. But not the initial > > > one, if that would defeat the purpose of request queuing. Of course > > > this can't be done if QEMU relies on the assumption in other places > > > already. > > > > I feel like this should be allowed because if anyone has exclusive > > access in this scenario, it's IDE, so it should be able to bypass the > > queuing. Of course, the queuing is still needed if someone else drained > > the backend, so we can't just make TRIM bypass it in general. And if you > > make it conditional on IDE being in blk_drain(), it already starts to > > become ugly again... > > > > So maybe the while loop is unavoidable. > > > > Hmm... But could ide_cancel_dma_sync() just directly use > > AIO_WAIT_WHILE(s->bus->dma->aiocb) instead of using blk_drain()? > > While that should work, it would not fix other uses of > bdrv_drain_all(), for example in softmmu/cpus.c. Stopping the device > model relies on those to run *until the device model has finished > submitting requests*. If so, do_vm_stop() really expects drain to do something it isn't designed to do. It's only for quiescing backends, not for any other activity a qdev device might still be doing. I think it's really the vm_state_notify() that should take care of stopping device activity. But maybe we can make it work with drain anyway. > So I still think that this bug is a symptom of a problem in the design > of request queuing. > > In fact, shouldn't request queuing was enabled at the _end_ of > bdrv_drained_begin (once the BlockBackend has reached a quiescent > state on its own terms), rather than at the beginning (which leads to > deadlocks like this one)? No, I don't think that is ever right. As I said earlier in this thread (and you said yourself previously), there are two different users of drain: 1. I want to have exclusive access to the node. This one wants request queuing from the start to avoid losing time unnecessarily until the guest stops sending new requests. 2. I want to wait for my requests to complete. This one never wants request queuing. Enabling it at the end of bdrv_drained_begin() wouldn't hurt it (because it has already achieved its goal then), but it's also not necessary for the same reason. IDE reset and do_vm_stop() are case 2, implemented with blk_drain*(). The request queuing was implemented for case 1, something else in the block graph draining the BlockBackend's root node with bdrv_drain*(). So maybe what we could take from this is that request queuing should be temporarily disabled while we're in blk_drain*() because these interfaces are only meant for case 2. In all other cases, it should continue to work as it does now. Kevin
Re: [PATCH v7 0/6] memory: prevent dma-reentracy issues
On 13/03/2023 15.52, Alexander Bulekov wrote: On 230313 1502, Thomas Huth wrote: On 13/03/2023 09.24, Alexander Bulekov wrote: v6 -> v7: - Fix bad qemu_bh_new_guarded calls found by Thomas (Patch 4) - Add an MR-specific flag to disable reentrancy (Patch 5) - Disable reentrancy checks for lsi53c895a's RAM-like MR (Patch 6) Patches 5 and 6 need review. I left the review-tags for Patch 4, however a few of the qemu_bh_new_guarded calls have changed. Hi Alexander, there seems to be another issue with one of the avocado tests: make -j8 qemu-system-aarch64 make check-venv ./tests/venv/bin/avocado run \ tests/avocado/boot_linux_console.py:BootLinuxConsole.test_aarch64_raspi3_atf ... works fine for me with the master branch, but it fails for me after applying your patch series. ... Do the avocado tests exit on failure, or do you know if there are any other test failures? I noticed it in the gitlab-CI, the test was hanging and got marked as "INTERRUPTED": https://gitlab.com/thuth/qemu/-/jobs/3922243532#L214 As far as I could see, this was the only new failure there. There is another one in the avocado-system-fedora job here: https://gitlab.com/thuth/qemu/-/jobs/3920337136#L307 ... but I think that was pre-existing and was caused by one of Philippe's reworks, hopefully to be fixed soon ... Phillipe? Thomas
Re: [PATCH v4 6/6] hw/cxl: Add clear poison mailbox command support.
On Fri, 3 Mar 2023 15:09:08 +
Jonathan Cameron wrote:
> Current implementation is very simple so many of the corner
> cases do not exist (e.g. fragmenting larger poison list entries)
>
> Signed-off-by: Jonathan Cameron
Another case in here of directly accessing MemoryRegion->size.
I'll fix that up for v5.
...
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index 21e3a84785..0d9de0ee03 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -919,6 +919,41 @@ static void set_lsa(CXLType3Dev *ct3d, const void *buf,
> uint64_t size,
> */
> }
>
> +static bool set_cacheline(CXLType3Dev *ct3d, uint64_t dpa_offset, uint8_t
> *data)
> +{
> +MemoryRegion *vmr = NULL, *pmr = NULL;
> +AddressSpace *as;
> +
> +if (ct3d->hostvmem) {
> +vmr = host_memory_backend_get_memory(ct3d->hostvmem);
> +}
> +if (ct3d->hostpmem) {
> +pmr = host_memory_backend_get_memory(ct3d->hostpmem);
> +}
> +
> +if (!vmr && !pmr) {
> +return false;
> +}
> +
> +if (dpa_offset + 64 > int128_get64(ct3d->cxl_dstate.mem_size)) {
> +return false;
> +}
> +
> +if (vmr) {
> +if (dpa_offset < int128_get64(vmr->size)) {
> +as = >hostvmem_as;
> +} else {
> +as = >hostpmem_as;
> +dpa_offset -= vmr->size;
Michael pointed out we shouldn't do this in the Volatile series.
Fixed the same way here with memory_region_size() here and instead
of the int128_get64 above.
> +}
> +} else {
> +as = >hostpmem_as;
> +}
> +
> +address_space_write(as, dpa_offset, MEMTXATTRS_UNSPECIFIED, , 64);
> +return true;
> +}
> +
Re: [PATCH v7 0/6] memory: prevent dma-reentracy issues
On Mon, 13 Mar 2023 at 15:41, Philippe Mathieu-Daudé wrote: > Now I wonder again if this is a good time to merge this change set. No, I don't think it is at this point in the release cycle. I would vote for merging it when we reopen for 8.1, so that we'll have a full cycle to find all the weird corner cases that it breaks. thanks -- PMM
Re: [PATCH v4 2/2] hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent)
...
> > +if (vmr) {
> > +if (*dpa_offset < int128_get64(vmr->size)) {
> > +*as = >hostvmem_as;
> > +} else {
> > +*as = >hostpmem_as;
> > +*dpa_offset -= vmr->size;
>
> You can't do math on vmr->size, it's Int128.
> And generally please do not poke at mr->size use APIs.
>
> Which one will depend ...
Good spot. In this case they are all sub 64 bit so
simple memory_region_size() is appropriate I think.
I'll add a precursor patch converting existing
int128_get64(mr->size) users in this file over to that.
Thanks,
Jonathan
Re: [RFC QEMU PATCH 08/18] virtio-gpu: Initialize Venus
On Mon, Mar 13, 2023 at 01:51:03AM +0800, Dmitry Osipenko wrote:
> On 3/12/23 12:22, Huang Rui wrote:
> > From: Antonio Caggiano
> >
> > Request Venus when initializing VirGL.
> >
> > Signed-off-by: Antonio Caggiano
> > ---
> > hw/display/virtio-gpu-virgl.c | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c
> > index fe03dc916f..f5ce206b93 100644
> > --- a/hw/display/virtio-gpu-virgl.c
> > +++ b/hw/display/virtio-gpu-virgl.c
> > @@ -803,7 +803,11 @@ int virtio_gpu_virgl_init(VirtIOGPU *g)
> > {
> > int ret;
> >
> > +#ifdef VIRGL_RENDERER_VENUS
> > +ret = virgl_renderer_init(g, VIRGL_RENDERER_VENUS, _gpu_3d_cbs);
> > +#else
> > ret = virgl_renderer_init(g, 0, _gpu_3d_cbs);
> > +#endif
>
> Note that Venus now requires VIRGL_RENDERER_RENDER_SERVER flag to be
> set. Please test the patches with the latest virglrenderer and etc.
>
> The #ifdef also doesn't allow adding new flags, it should look like:
>
> #ifdef VIRGL_RENDERER_VENUS
> flags |= VIRGL_RENDERER_RENDER_SERVER;
> #endif
>
> ret = virgl_renderer_init(g, flags, _gpu_3d_cbs);
In fact, we have rebased to the latest virglrenderer:
We check both VIRGL_RENDERER_RENDER_SERVER or VIRGL_RENDERER_VENUS in
virglrenderer, alternative of them works.
https://gitlab.freedesktop.org/rui/virglrenderer/-/commit/c1322a8a84379b1ef7939f56c6761b0114716f45
Thanks,
Ray
Re: [RFC QEMU PATCH 08/18] virtio-gpu: Initialize Venus
On Mon, Mar 13, 2023 at 10:22:24AM +0800, Dmitry Osipenko wrote:
> On 3/12/23 20:51, Dmitry Osipenko wrote:
> > On 3/12/23 12:22, Huang Rui wrote:
> >> From: Antonio Caggiano
> >>
> >> Request Venus when initializing VirGL.
> >>
> >> Signed-off-by: Antonio Caggiano
> >> ---
> >> hw/display/virtio-gpu-virgl.c | 4
> >> 1 file changed, 4 insertions(+)
> >>
> >> diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c
> >> index fe03dc916f..f5ce206b93 100644
> >> --- a/hw/display/virtio-gpu-virgl.c
> >> +++ b/hw/display/virtio-gpu-virgl.c
> >> @@ -803,7 +803,11 @@ int virtio_gpu_virgl_init(VirtIOGPU *g)
> >> {
> >> int ret;
> >>
> >> +#ifdef VIRGL_RENDERER_VENUS
> >> +ret = virgl_renderer_init(g, VIRGL_RENDERER_VENUS,
> >> _gpu_3d_cbs);
> >> +#else
> >> ret = virgl_renderer_init(g, 0, _gpu_3d_cbs);
> >> +#endif
> >
> > Note that Venus now requires VIRGL_RENDERER_RENDER_SERVER flag to be
> > set. Please test the patches with the latest virglrenderer and etc.
> >
> > The #ifdef also doesn't allow adding new flags, it should look like:
> >
> > #ifdef VIRGL_RENDERER_VENUS
> > flags |= VIRGL_RENDERER_RENDER_SERVER;
> > #endif
> >
> > ret = virgl_renderer_init(g, flags, _gpu_3d_cbs);
> >
>
> BTW, Alex reviewed the Venus v3 patches a month ago [1] and the review
> comments need to be addressed. AFAICS, you're actually using the very
> old Venus patches here that stopped working about a year ago, so again
> you're using a very outdated virglrenderer version.
>
> Please take it all into account if you'll beat me to posting the next
> version of Venus patches ;)
>
> [1]
> https://lore.kernel.org/qemu-devel/20220926142422.22325-1-antonio.caggi...@collabora.com/
>
Thanks Dmitry point it out, I will use the latest v3 patches, and try to
address the comments in next version. :-)
Thanks,
Ray
Re: [PATCH v3 1/1] hw/riscv: Fix max size limit when put initrd to RAM
On Mon, Mar 13, 2023 at 7:49 AM Hang Xu wrote:
>
> Because the starting address of ram is not necessarily 0,
> the remaining free space in ram is
> ram_size - (start - ram_base) instead of ram_size-start.
>
> Signed-off-by: Hang Xu
What happens in-case a platform has multiple RAM banks ?
Regards,
Anup
> ---
> hw/riscv/boot.c| 19 +--
> hw/riscv/microchip_pfsoc.c | 5 -
> hw/riscv/opentitan.c | 2 +-
> hw/riscv/sifive_e.c| 2 +-
> hw/riscv/sifive_u.c| 5 -
> hw/riscv/spike.c | 5 -
> hw/riscv/virt.c| 5 -
> include/hw/riscv/boot.h| 2 ++
> 8 files changed, 33 insertions(+), 12 deletions(-)
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index 52bf8e67de..cfbc376a82 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -173,13 +173,14 @@ target_ulong riscv_load_firmware(const char
> *firmware_filename,
> exit(1);
> }
>
> -static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
> +static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry,
> + uint64_t ram_base, uint64_t ram_size)
> {
> const char *filename = machine->initrd_filename;
> -uint64_t mem_size = machine->ram_size;
> void *fdt = machine->fdt;
> hwaddr start, end;
> ssize_t size;
> +uint64_t max_initrd;
>
> g_assert(filename != NULL);
>
> @@ -193,12 +194,16 @@ static void riscv_load_initrd(MachineState *machine,
> uint64_t kernel_entry)
> * So for boards with less than 256MB of RAM we put the initrd
> * halfway into RAM, and for boards with 256MB of RAM or more we put
> * the initrd at 128MB.
> + * A ram_size == 0, usually from a MemMapEntry[].size element,
> + * means that the RAM block goes all the way to ms->ram_size.
> */
> -start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
> +ram_size = ram_size ? MIN(machine->ram_size, ram_size) :
> machine->ram_size;
> +start = kernel_entry + MIN(ram_size / 2, 128 * MiB);
> +max_initrd = ram_size - (start - ram_base);
>
> -size = load_ramdisk(filename, start, mem_size - start);
> +size = load_ramdisk(filename, start, max_initrd);
> if (size == -1) {
> -size = load_image_targphys(filename, start, mem_size - start);
> +size = load_image_targphys(filename, start, max_initrd);
> if (size == -1) {
> error_report("could not load ramdisk '%s'", filename);
> exit(1);
> @@ -217,6 +222,8 @@ target_ulong riscv_load_kernel(MachineState *machine,
> RISCVHartArrayState *harts,
> target_ulong kernel_start_addr,
> bool load_initrd,
> + uint64_t ram_base,
> + uint64_t ram_size,
> symbol_fn_t sym_cb)
> {
> const char *kernel_filename = machine->kernel_filename;
> @@ -263,7 +270,7 @@ out:
> }
>
> if (load_initrd && machine->initrd_filename) {
> -riscv_load_initrd(machine, kernel_entry);
> +riscv_load_initrd(machine, kernel_entry, ram_base, ram_size);
> }
>
> if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) {
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index e81bbd12df..b42d90b89e 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -630,7 +630,10 @@ static void
> microchip_icicle_kit_machine_init(MachineState *machine)
> firmware_end_addr);
>
> kernel_entry = riscv_load_kernel(machine, >soc.u_cpus,
> - kernel_start_addr, true, NULL);
> + kernel_start_addr, true,
> +
> memmap[MICROCHIP_PFSOC_DRAM_LO].base,
> +
> memmap[MICROCHIP_PFSOC_DRAM_LO].size,
> + NULL);
>
> /* Compute the fdt load address in dram */
> fdt_load_addr =
> riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index b06944d382..bb663523d5 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -103,7 +103,7 @@ static void opentitan_board_init(MachineState *machine)
> if (machine->kernel_filename) {
> riscv_load_kernel(machine, >soc.cpus,
>memmap[IBEX_DEV_RAM].base,
> - false, NULL);
> + false, 0, 0, NULL);
> }
> }
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 04939b60c3..5b47d539a6 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -116,7 +116,7 @@ static void sifive_e_machine_init(MachineState *machine)
> if
Re: [PATCH v7 0/6] memory: prevent dma-reentracy issues
On 13/3/23 15:52, Alexander Bulekov wrote: On 230313 1502, Thomas Huth wrote: On 13/03/2023 09.24, Alexander Bulekov wrote: v6 -> v7: - Fix bad qemu_bh_new_guarded calls found by Thomas (Patch 4) - Add an MR-specific flag to disable reentrancy (Patch 5) - Disable reentrancy checks for lsi53c895a's RAM-like MR (Patch 6) Patches 5 and 6 need review. I left the review-tags for Patch 4, however a few of the qemu_bh_new_guarded calls have changed. Hi Alexander, there seems to be another issue with one of the avocado tests: make -j8 qemu-system-aarch64 make check-venv ./tests/venv/bin/avocado run \ tests/avocado/boot_linux_console.py:BootLinuxConsole.test_aarch64_raspi3_atf ... works fine for me with the master branch, but it fails for me after applying your patch series. Can you reproduce that failure? #0 __GI_exit (status=0x1) at ./stdlib/exit.c:143 #1 0x55f05819 in access_with_adjusted_size (addr=0x0, addr@entry=0x73b609d0, value=0x73b609d0, size=size@entry=0x4, access_size_min=0x1, access_size_max=0x4, access_fn=0x55f0b4b0 , mr=0x7 #2 0x55f05380 in memory_region_dispatch_read1 (mr=0x73e34990, addr=0x1, pval=, size=0x4, attrs=...) at ../softmmu/memory.c:1442 #3 memory_region_dispatch_read (mr=, mr@entry=0x73e34990, addr=0x1, pval=, pval@entry=0x73b609d0, op=, attrs=..., attrs@entry=...) at ../softmmu/memory.c:1476 #4 0x55f1278f in address_space_ldl_internal (as=, addr=, attrs=..., result=0x0, endian=DEVICE_LITTLE_ENDIAN) at ../memory_ldst.c.inc:41 #5 0x559ebb5d in ldl_le_phys (as=0x73e35258, addr=0x80) at /home/alxndr/Development/qemu-demo/qemu/include/exec/memory_ldst_phys.h.inc:79 #6 bcm2835_mbox_update (s=0x73e34f20) at ../hw/misc/bcm2835_mbox.c:109 #7 0x559ecd5d in bcm2835_property_write (opaque=0x73e34600, offset=, value=, size=) at ../hw/misc/bcm2835_property.c:349 #8 0x55f05903 in memory_region_write_accessor (mr=0x73e34990, addr=0x0, value=, size=0x4, shift=, mask=, attrs=...) at ../softmmu/memory.c:493 #9 0x55f0576b in access_with_adjusted_size (addr=addr@entry=0x0, value=0x73b60c38, value@entry=0x73b60c28, size=size@entry=0x4, access_size_min=, access_size_max=, access_fn=0x55f05820 < attrs=...) at ../softmmu/memory.c:570 #10 0x55f055c6 in memory_region_dispatch_write (mr=, mr@entry=0x73e34990, addr=0x0, data=, data@entry=0x2f2228, op=, attrs=..., attrs@entry=...) at ../softmmu/memory.c:1532 #11 0x55f132ec in address_space_stl_internal (as=, addr=, val=0x2f2228, attrs=..., result=0x0, endian=DEVICE_LITTLE_ENDIAN) at ../memory_ldst.c.inc:319 #12 0x559eb9a4 in stl_le_phys (as=, addr=0x80, val=0x2f2228) at /home/alxndr/Development/qemu-demo/qemu/include/exec/memory_ldst_phys.h.inc:121 #13 bcm2835_mbox_write (opaque=0x73e34f20, offset=, value=0x2f2228, size=) at ../hw/misc/bcm2835_mbox.c:227 #14 0x55f05903 in memory_region_write_accessor (mr=0x73e352b0, addr=0xa0, value=, size=0x4, shift=, mask=, attrs=...) at ../softmmu/memory.c:493 #15 0x55f0576b in access_with_adjusted_size (addr=addr@entry=0xa0, value=0x73b60e48, value@entry=0x73b60e38, size=size@entry=0x4, access_size_min=, access_size_max=, access_fn=0x55f05820 attrs=...) at ../softmmu/memory.c:570 #16 0x55f055c6 in memory_region_dispatch_write (mr=, mr@entry=0x2, addr=addr@entry=0xa0, data=, data@entry=0x2f2228, op=, op@entry=MO_32, attrs=...) at ../softmmu/memory.c:1532 #17 0x55f9b3ae in io_writex (env=0x73dd60e0, full=0x5790c710, mmu_idx=0x7, val=0x4, val@entry=0x2f2228, addr=0x3f00b8a0, retaddr=retaddr@entry=0x7fffac01f9dd, op=MO_32) at ../accel/tcg/cputlb.c:1430 #18 0x55f90062 in store_helper (env=, addr=, val=0x2f2228, oi=, retaddr=0x73b609d0, op=MO_32) at ../accel/tcg/cputlb.c:2454 #19 full_le_stl_mmu (env=, addr=, val=0x2f2228, oi=, retaddr=0x73b609d0) at ../accel/tcg/cputlb.c:2542 #20 0x7fffac01f9dd in code_gen_buffer () #21 0x55f7367e in cpu_tb_exec (cpu=cpu@entry=0x73dd4210, itb=itb@entry=0x7fffac01f8c0 , tb_exit=tb_exit@entry=0x73b6148c) at ../accel/tcg/cpu-exec.c:460 #22 0x55f744f9 in cpu_loop_exec_tb (cpu=0x73dd4210, tb=, pc=, tb_exit=0x73b6148c, last_tb=) at ../accel/tcg/cpu-exec.c:894 #23 cpu_exec_loop (cpu=cpu@entry=0x73dd4210, sc=sc@entry=0x73b61510) at ../accel/tcg/cpu-exec.c:1005 #24 0x55f73c27 in cpu_exec_setjmp (cpu=cpu@entry=0x73dd4210, sc=sc@entry=0x73b61510) at ../accel/tcg/cpu-exec.c:1037 #25 0x55f73aee in cpu_exec (cpu=cpu@entry=0x73dd4210) at ../accel/tcg/cpu-exec.c:1063 #26 0x55f9da4f in tcg_cpus_exec (cpu=cpu@entry=0x73dd4210) at ../accel/tcg/tcg-accel-ops.c:81 #27 0x55f9e019 in mttcg_cpu_thread_fn (arg=arg@entry=0x73dd4210) at ../accel/tcg/tcg-accel-ops-mttcg.c:95 #28 0x5611d0c5 in qemu_thread_start
[PATCH v2 03/12] target/s390x: Handle LGRL from non-aligned addresses
Use MO_ALIGN and let do_unaligned_access() generate a specification
exception.
Reported-by: Nina Schoetterl-Glausch
Suggested-by: Nina Schoetterl-Glausch
Reviewed-by: Richard Henderson
Signed-off-by: Ilya Leoshkevich
---
target/s390x/tcg/insn-data.h.inc | 6 +++---
target/s390x/tcg/translate.c | 3 ++-
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc
index 6fe8ca51437..d439d803509 100644
--- a/target/s390x/tcg/insn-data.h.inc
+++ b/target/s390x/tcg/insn-data.h.inc
@@ -414,7 +414,7 @@
C(0xe358, LY, RXY_a, LD, 0, a2, new, r1_32, ld32s, 0)
C(0xb904, LGR, RRE, Z, 0, r2_o, 0, r1, mov2, 0)
C(0xb914, LGFR,RRE, Z, 0, r2_32s, 0, r1, mov2, 0)
-C(0xe304, LG, RXY_a, Z, 0, a2, r1, 0, ld64, 0)
+D(0xe304, LG, RXY_a, Z, 0, a2, r1, 0, ld64, 0, 0)
C(0xe314, LGF, RXY_a, Z, 0, a2, r1, 0, ld32s, 0)
F(0x2800, LDR, RR_a, Z, 0, f2, 0, f1, mov2, 0, IF_AFP1 | IF_AFP2)
F(0x6800, LD, RX_a, Z, 0, m2_64, 0, f1, mov2, 0, IF_AFP1)
@@ -427,7 +427,7 @@
C(0xc001, LGFI,RIL_a, EI, 0, i2, 0, r1, mov2, 0)
/* LOAD RELATIVE LONG */
C(0xc40d, LRL, RIL_b, GIE, 0, ri2, new, r1_32, ld32s, 0)
-C(0xc408, LGRL,RIL_b, GIE, 0, ri2, r1, 0, ld64, 0)
+D(0xc408, LGRL,RIL_b, GIE, 0, ri2, r1, 0, ld64, 0, MO_ALIGN)
C(0xc40c, LGFRL, RIL_b, GIE, 0, ri2, r1, 0, ld32s, 0)
/* LOAD ADDRESS */
C(0x4100, LA, RX_a, Z, 0, a2, 0, r1, mov2, 0)
@@ -457,7 +457,7 @@
C(0xb902, LTGR,RRE, Z, 0, r2_o, 0, r1, mov2, s64)
C(0xb912, LTGFR, RRE, Z, 0, r2_32s, 0, r1, mov2, s64)
C(0xe312, LT, RXY_a, EI, 0, a2, new, r1_32, ld32s, s64)
-C(0xe302, LTG, RXY_a, EI, 0, a2, r1, 0, ld64, s64)
+D(0xe302, LTG, RXY_a, EI, 0, a2, r1, 0, ld64, s64, 0)
C(0xe332, LTGF,RXY_a, GIE, 0, a2, r1, 0, ld32s, s64)
F(0xb302, LTEBR, RRE, Z, 0, e2, 0, cond_e1e2, mov2, f32, IF_BFP)
F(0xb312, LTDBR, RRE, Z, 0, f2, 0, f1, mov2, f64, IF_BFP)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index d324c0b6f2a..924efdad7a4 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -2851,7 +2851,8 @@ static DisasJumpType op_ld32u(DisasContext *s, DisasOps
*o)
static DisasJumpType op_ld64(DisasContext *s, DisasOps *o)
{
-tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
+tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s),
+MO_TEUQ | s->insn->data);
return DISAS_NEXT;
}
--
2.39.2
[PATCH v2 04/12] target/s390x: Handle LRL and LGFRL from non-aligned addresses
Use MO_ALIGN and let do_unaligned_access() generate a specification
exception.
Reported-by: Nina Schoetterl-Glausch
Suggested-by: Nina Schoetterl-Glausch
Reviewed-by: Richard Henderson
Signed-off-by: Ilya Leoshkevich
---
target/s390x/tcg/insn-data.h.inc | 14 +++---
target/s390x/tcg/translate.c | 3 ++-
2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc
index d439d803509..5aff4c0873a 100644
--- a/target/s390x/tcg/insn-data.h.inc
+++ b/target/s390x/tcg/insn-data.h.inc
@@ -410,12 +410,12 @@
/* LOAD */
C(0x1800, LR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, 0)
-C(0x5800, L, RX_a, Z, 0, a2, new, r1_32, ld32s, 0)
-C(0xe358, LY, RXY_a, LD, 0, a2, new, r1_32, ld32s, 0)
+D(0x5800, L, RX_a, Z, 0, a2, new, r1_32, ld32s, 0, 0)
+D(0xe358, LY, RXY_a, LD, 0, a2, new, r1_32, ld32s, 0, 0)
C(0xb904, LGR, RRE, Z, 0, r2_o, 0, r1, mov2, 0)
C(0xb914, LGFR,RRE, Z, 0, r2_32s, 0, r1, mov2, 0)
D(0xe304, LG, RXY_a, Z, 0, a2, r1, 0, ld64, 0, 0)
-C(0xe314, LGF, RXY_a, Z, 0, a2, r1, 0, ld32s, 0)
+D(0xe314, LGF, RXY_a, Z, 0, a2, r1, 0, ld32s, 0, 0)
F(0x2800, LDR, RR_a, Z, 0, f2, 0, f1, mov2, 0, IF_AFP1 | IF_AFP2)
F(0x6800, LD, RX_a, Z, 0, m2_64, 0, f1, mov2, 0, IF_AFP1)
F(0xed65, LDY, RXY_a, LD, 0, m2_64, 0, f1, mov2, 0, IF_AFP1)
@@ -426,9 +426,9 @@
/* LOAD IMMEDIATE */
C(0xc001, LGFI,RIL_a, EI, 0, i2, 0, r1, mov2, 0)
/* LOAD RELATIVE LONG */
-C(0xc40d, LRL, RIL_b, GIE, 0, ri2, new, r1_32, ld32s, 0)
+D(0xc40d, LRL, RIL_b, GIE, 0, ri2, new, r1_32, ld32s, 0, MO_ALIGN)
D(0xc408, LGRL,RIL_b, GIE, 0, ri2, r1, 0, ld64, 0, MO_ALIGN)
-C(0xc40c, LGFRL, RIL_b, GIE, 0, ri2, r1, 0, ld32s, 0)
+D(0xc40c, LGFRL, RIL_b, GIE, 0, ri2, r1, 0, ld32s, 0, MO_ALIGN)
/* LOAD ADDRESS */
C(0x4100, LA, RX_a, Z, 0, a2, 0, r1, mov2, 0)
C(0xe371, LAY, RXY_a, LD, 0, a2, 0, r1, mov2, 0)
@@ -456,9 +456,9 @@
C(0x1200, LTR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, s32)
C(0xb902, LTGR,RRE, Z, 0, r2_o, 0, r1, mov2, s64)
C(0xb912, LTGFR, RRE, Z, 0, r2_32s, 0, r1, mov2, s64)
-C(0xe312, LT, RXY_a, EI, 0, a2, new, r1_32, ld32s, s64)
+D(0xe312, LT, RXY_a, EI, 0, a2, new, r1_32, ld32s, s64, 0)
D(0xe302, LTG, RXY_a, EI, 0, a2, r1, 0, ld64, s64, 0)
-C(0xe332, LTGF,RXY_a, GIE, 0, a2, r1, 0, ld32s, s64)
+D(0xe332, LTGF,RXY_a, GIE, 0, a2, r1, 0, ld32s, s64, 0)
F(0xb302, LTEBR, RRE, Z, 0, e2, 0, cond_e1e2, mov2, f32, IF_BFP)
F(0xb312, LTDBR, RRE, Z, 0, f2, 0, f1, mov2, f64, IF_BFP)
F(0xb342, LTXBR, RRE, Z, x2h, x2l, 0, x1_P, movx, f128, IF_BFP)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 924efdad7a4..5033767cef4 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -2839,7 +2839,8 @@ static DisasJumpType op_ld16u(DisasContext *s, DisasOps
*o)
static DisasJumpType op_ld32s(DisasContext *s, DisasOps *o)
{
-tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
+tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s),
+ MO_TESL | s->insn->data);
return DISAS_NEXT;
}
--
2.39.2
[PATCH v2 05/12] target/s390x: Handle LLGFRL from non-aligned addresses
Use MO_ALIGN and let do_unaligned_access() generate a specification
exception.
Reported-by: Nina Schoetterl-Glausch
Suggested-by: Nina Schoetterl-Glausch
Reviewed-by: Richard Henderson
Signed-off-by: Ilya Leoshkevich
---
target/s390x/tcg/insn-data.h.inc | 6 +++---
target/s390x/tcg/translate.c | 3 ++-
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc
index 5aff4c0873a..3abd2dbedd5 100644
--- a/target/s390x/tcg/insn-data.h.inc
+++ b/target/s390x/tcg/insn-data.h.inc
@@ -502,16 +502,16 @@
C(0xc405, LHRL,RIL_b, GIE, 0, ri2, new, r1_32, ld16s, 0)
C(0xc404, LGHRL, RIL_b, GIE, 0, ri2, r1, 0, ld16s, 0)
/* LOAD HIGH */
-C(0xe3ca, LFH, RXY_a, HW, 0, a2, new, r1_32h, ld32u, 0)
+D(0xe3ca, LFH, RXY_a, HW, 0, a2, new, r1_32h, ld32u, 0, 0)
/* LOAG HIGH AND TRAP */
C(0xe3c8, LFHAT, RXY_a, LAT, 0, m2_32u, r1, 0, lfhat, 0)
/* LOAD LOGICAL */
C(0xb916, LLGFR, RRE, Z, 0, r2_32u, 0, r1, mov2, 0)
-C(0xe316, LLGF,RXY_a, Z, 0, a2, r1, 0, ld32u, 0)
+D(0xe316, LLGF,RXY_a, Z, 0, a2, r1, 0, ld32u, 0, 0)
/* LOAD LOGICAL AND TRAP */
C(0xe39d, LLGFAT, RXY_a, LAT, 0, a2, r1, 0, llgfat, 0)
/* LOAD LOGICAL RELATIVE LONG */
-C(0xc40e, LLGFRL, RIL_b, GIE, 0, ri2, r1, 0, ld32u, 0)
+D(0xc40e, LLGFRL, RIL_b, GIE, 0, ri2, r1, 0, ld32u, 0, MO_ALIGN)
/* LOAD LOGICAL CHARACTER */
C(0xb994, LLCR,RRE, EI, 0, r2_8u, 0, r1_32, mov2, 0)
C(0xb984, LLGCR, RRE, EI, 0, r2_8u, 0, r1, mov2, 0)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 5033767cef4..6ceb14de92f 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -2846,7 +2846,8 @@ static DisasJumpType op_ld32s(DisasContext *s, DisasOps
*o)
static DisasJumpType op_ld32u(DisasContext *s, DisasOps *o)
{
-tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
+tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s),
+ MO_TEUL | s->insn->data);
return DISAS_NEXT;
}
--
2.39.2
[PATCH v2 10/12] target/s390x: Handle STGRL to non-aligned addresses
Use MO_ALIGN and let do_unaligned_access() generate a specification
exception.
Reported-by: Nina Schoetterl-Glausch
Suggested-by: Nina Schoetterl-Glausch
Reviewed-by: Richard Henderson
Signed-off-by: Ilya Leoshkevich
---
target/s390x/tcg/insn-data.h.inc | 8
target/s390x/tcg/translate.c | 3 ++-
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc
index 30c02b3fcd6..597d968b0e8 100644
--- a/target/s390x/tcg/insn-data.h.inc
+++ b/target/s390x/tcg/insn-data.h.inc
@@ -842,14 +842,14 @@
/* STORE */
D(0x5000, ST, RX_a, Z, r1_o, a2, 0, 0, st32, 0, 0)
D(0xe350, STY, RXY_a, LD, r1_o, a2, 0, 0, st32, 0, 0)
-C(0xe324, STG, RXY_a, Z, r1_o, a2, 0, 0, st64, 0)
-F(0x6000, STD, RX_a, Z, f1, a2, 0, 0, st64, 0, IF_AFP1)
-F(0xed67, STDY,RXY_a, LD, f1, a2, 0, 0, st64, 0, IF_AFP1)
+D(0xe324, STG, RXY_a, Z, r1_o, a2, 0, 0, st64, 0, 0)
+E(0x6000, STD, RX_a, Z, f1, a2, 0, 0, st64, 0, 0, IF_AFP1)
+E(0xed67, STDY,RXY_a, LD, f1, a2, 0, 0, st64, 0, 0, IF_AFP1)
E(0x7000, STE, RX_a, Z, e1, a2, 0, 0, st32, 0, 0, IF_AFP1)
E(0xed66, STEY,RXY_a, LD, e1, a2, 0, 0, st32, 0, 0, IF_AFP1)
/* STORE RELATIVE LONG */
D(0xc40f, STRL,RIL_b, GIE, r1_o, ri2, 0, 0, st32, 0, MO_ALIGN)
-C(0xc40b, STGRL, RIL_b, GIE, r1_o, ri2, 0, 0, st64, 0)
+D(0xc40b, STGRL, RIL_b, GIE, r1_o, ri2, 0, 0, st64, 0, MO_ALIGN)
/* STORE CHARACTER */
C(0x4200, STC, RX_a, Z, r1_o, a2, 0, 0, st8, 0)
C(0xe372, STCY,RXY_a, LD, r1_o, a2, 0, 0, st8, 0)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 29efbfab4e9..be95df73e9d 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -4504,7 +4504,8 @@ static DisasJumpType op_st32(DisasContext *s, DisasOps *o)
static DisasJumpType op_st64(DisasContext *s, DisasOps *o)
{
-tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
+tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s),
+MO_TEUQ | s->insn->data);
return DISAS_NEXT;
}
--
2.39.2
[PATCH v2 00/12] target/s390x: Handle unaligned accesses
v1: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg03821.html v1 -> v2: Use MO_ALIGN (Richard). Patches that need review: - [PATCH 01/12] target/s390x: Handle branching to odd addresses - [PATCH 12/12] tests/tcg/s390x: Test unaligned accesses Hi, This series makes accessing unaligned addresses with branching, LPSWE, EXECUTE and relative long instructions fail with a specification exception instead of succeeding. Patches 1-10 are fixes, patch 11 adjusts a comment to reflect a change done by fixes, patch 12 adds a number of softmmu and user tests. Best regards, Ilya Ilya Leoshkevich (12): target/s390x: Handle branching to odd addresses target/s390x: Handle EXECUTE of odd addresses target/s390x: Handle LGRL from non-aligned addresses target/s390x: Handle LRL and LGFRL from non-aligned addresses target/s390x: Handle LLGFRL from non-aligned addresses target/s390x: Handle CRL and CGFRL with non-aligned addresses target/s390x: Handle CGRL and CLGRL with non-aligned addresses target/s390x: Handle CLRL and CLGFRL with non-aligned addresses target/s390x: Handle STRL to non-aligned addresses target/s390x: Handle STGRL to non-aligned addresses target/s390x: Update do_unaligned_access() comment tests/tcg/s390x: Test unaligned accesses target/s390x/cpu.h | 9 +++ target/s390x/tcg/excp_helper.c | 4 +- target/s390x/tcg/insn-data.h.inc| 46 ++--- target/s390x/tcg/mem_helper.c | 12 +++- target/s390x/tcg/translate.c| 24 --- tests/tcg/s390x/Makefile.softmmu-target | 4 +- tests/tcg/s390x/Makefile.target | 3 + tests/tcg/s390x/asm-const.h | 13 tests/tcg/s390x/br-odd.S| 18 + tests/tcg/s390x/cgrl-unaligned.S| 17 + tests/tcg/s390x/clrl-unaligned.S| 15 + tests/tcg/s390x/crl-unaligned.S | 17 + tests/tcg/s390x/ex-odd.S| 17 + tests/tcg/s390x/lgrl-unaligned.S| 17 + tests/tcg/s390x/llgfrl-unaligned.S | 17 + tests/tcg/s390x/lpswe-unaligned.S | 17 + tests/tcg/s390x/lrl-unaligned.S | 17 + tests/tcg/s390x/pgm-specification.inc | 90 + tests/tcg/s390x/pgm-specification.mak | 15 + tests/tcg/s390x/stgrl-unaligned.S | 17 + tests/tcg/s390x/strl-unaligned.S| 17 + 21 files changed, 370 insertions(+), 36 deletions(-) create mode 100644 tests/tcg/s390x/asm-const.h create mode 100644 tests/tcg/s390x/br-odd.S create mode 100644 tests/tcg/s390x/cgrl-unaligned.S create mode 100644 tests/tcg/s390x/clrl-unaligned.S create mode 100644 tests/tcg/s390x/crl-unaligned.S create mode 100644 tests/tcg/s390x/ex-odd.S create mode 100644 tests/tcg/s390x/lgrl-unaligned.S create mode 100644 tests/tcg/s390x/llgfrl-unaligned.S create mode 100644 tests/tcg/s390x/lpswe-unaligned.S create mode 100644 tests/tcg/s390x/lrl-unaligned.S create mode 100644 tests/tcg/s390x/pgm-specification.inc create mode 100644 tests/tcg/s390x/pgm-specification.mak create mode 100644 tests/tcg/s390x/stgrl-unaligned.S create mode 100644 tests/tcg/s390x/strl-unaligned.S -- 2.39.2
[PATCH v2 09/12] target/s390x: Handle STRL to non-aligned addresses
Use MO_ALIGN and let do_unaligned_access() generate a specification
exception.
Reported-by: Nina Schoetterl-Glausch
Suggested-by: Nina Schoetterl-Glausch
Reviewed-by: Richard Henderson
Signed-off-by: Ilya Leoshkevich
---
target/s390x/tcg/insn-data.h.inc | 12 ++--
target/s390x/tcg/translate.c | 3 ++-
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc
index 3abd2dbedd5..30c02b3fcd6 100644
--- a/target/s390x/tcg/insn-data.h.inc
+++ b/target/s390x/tcg/insn-data.h.inc
@@ -840,15 +840,15 @@
F(0xed15, SQDB,RXE, Z, 0, m2_64, new, f1, sqdb, 0, IF_BFP)
/* STORE */
-C(0x5000, ST, RX_a, Z, r1_o, a2, 0, 0, st32, 0)
-C(0xe350, STY, RXY_a, LD, r1_o, a2, 0, 0, st32, 0)
+D(0x5000, ST, RX_a, Z, r1_o, a2, 0, 0, st32, 0, 0)
+D(0xe350, STY, RXY_a, LD, r1_o, a2, 0, 0, st32, 0, 0)
C(0xe324, STG, RXY_a, Z, r1_o, a2, 0, 0, st64, 0)
F(0x6000, STD, RX_a, Z, f1, a2, 0, 0, st64, 0, IF_AFP1)
F(0xed67, STDY,RXY_a, LD, f1, a2, 0, 0, st64, 0, IF_AFP1)
-F(0x7000, STE, RX_a, Z, e1, a2, 0, 0, st32, 0, IF_AFP1)
-F(0xed66, STEY,RXY_a, LD, e1, a2, 0, 0, st32, 0, IF_AFP1)
+E(0x7000, STE, RX_a, Z, e1, a2, 0, 0, st32, 0, 0, IF_AFP1)
+E(0xed66, STEY,RXY_a, LD, e1, a2, 0, 0, st32, 0, 0, IF_AFP1)
/* STORE RELATIVE LONG */
-C(0xc40f, STRL,RIL_b, GIE, r1_o, ri2, 0, 0, st32, 0)
+D(0xc40f, STRL,RIL_b, GIE, r1_o, ri2, 0, 0, st32, 0, MO_ALIGN)
C(0xc40b, STGRL, RIL_b, GIE, r1_o, ri2, 0, 0, st64, 0)
/* STORE CHARACTER */
C(0x4200, STC, RX_a, Z, r1_o, a2, 0, 0, st8, 0)
@@ -867,7 +867,7 @@
/* STORE HALFWORD RELATIVE LONG */
C(0xc407, STHRL, RIL_b, GIE, r1_o, ri2, 0, 0, st16, 0)
/* STORE HIGH */
-C(0xe3cb, STFH,RXY_a, HW, r1_sr32, a2, 0, 0, st32, 0)
+D(0xe3cb, STFH,RXY_a, HW, r1_sr32, a2, 0, 0, st32, 0, 0)
/* STORE ON CONDITION */
D(0xebf3, STOC,RSY_b, LOC, 0, 0, 0, 0, soc, 0, 0)
D(0xebe3, STOCG, RSY_b, LOC, 0, 0, 0, 0, soc, 0, 1)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index a6ac7b7e136..29efbfab4e9 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -4497,7 +4497,8 @@ static DisasJumpType op_st16(DisasContext *s, DisasOps *o)
static DisasJumpType op_st32(DisasContext *s, DisasOps *o)
{
-tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
+tcg_gen_qemu_st_tl(o->in1, o->in2, get_mem_index(s),
+ MO_TEUL | s->insn->data);
return DISAS_NEXT;
}
--
2.39.2
