Please help me with with one information

[Antonio Apostoliu]

Hello 

 

You are so kind to tell me how can I use qmp to send colon character . I
speak about this character   :

 

I tried:

{"execute":"send-key","arguments":{"keys":[{"type":"qcode","data":"shift-sem
icolon"}]}}

{"execute":"send-key","arguments":{"keys":[{"type":"qcode","data":"shift","d
ata":"semicolon"}]}}

 

Both don't sent the character in my case

All others character worked

 

Best regards

 

 



-- 
This email has been checked for viruses by Avast antivirus software.
www.avast.com

Re: [RESEND PATCH v2] target/i386: Switch back XFRM value

[Yang Zhong]

On Mon, Mar 27, 2023 at 04:03:54PM +0800, Yang, Weijiang wrote:
> 
> On 3/27/2023 3:33 PM, Christian Ehrhardt wrote:
> > On Thu, Oct 27, 2022 at 2:36 AM Yang, Weijiang  
> > wrote:
> > > 
> > > On 10/26/2022 7:57 PM, Zhong, Yang wrote:
> > > > The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
> > > > FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
> > > > SGX enclave only supported SSE and x87 feature(xfrm=0x3).
> > > > 
> > > > Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based 
> > > > features")
> > > > 
> > > > Signed-off-by: Yang Zhong 
> > > > ---
> > > >target/i386/cpu.c | 4 ++--
> > > >1 file changed, 2 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > > > index ad623d91e4..19aaed877b 100644
> > > > --- a/target/i386/cpu.c
> > > > +++ b/target/i386/cpu.c
> > > > @@ -5584,8 +5584,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t 
> > > > index, uint32_t count,
> > > >} else {
> > > >*eax &= env->features[FEAT_SGX_12_1_EAX];
> > > >*ebx &= 0; /* ebx reserve */
> > > > -*ecx &= env->features[FEAT_XSAVE_XSS_LO];
> > > > -*edx &= env->features[FEAT_XSAVE_XSS_HI];
> > > > +*ecx &= env->features[FEAT_XSAVE_XCR0_LO];
> > > > +*edx &= env->features[FEAT_XSAVE_XCR0_HI];
> > > Oops, that's my fault to replace with wrong definitions, thanks for the 
> > > fix!
> > > 
> > > Reviewed-by:  Yang Weijiang 
> > Hi,
> > I do not have any background on this but stumbled over this and wondered,
> > is there any particular reason why this wasn't applied yet?
> > 
> > It seemed to fix a former mistake, was acked and then ... silence
> 
> Chris, thanks for the catch!
> 
> I double checked this patch isn't in the latest 8.0.0-rc1 tree.
> 
> 
> Hi, Paolo,
> 
> Could you help merge this fixup patch? Thanks!


  Hello all,

  Let me rebase this patch and resend it, thanks!

  Yang


> 
> > 
> > > >/* FP and SSE are always allowed regardless of 
> > > > XSAVE/XCR0. */
> > > >*ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK;
> > 

Re: [PATCH 1/2] target/riscv: Fix the mstatus.MPP value after executing MRET

[Alistair Francis]

On Thu, Apr 6, 2023 at 1:02 PM liweiwei  wrote:
>
>
> On 2023/4/6 10:24, Alistair Francis wrote:
> > On Thu, Apr 6, 2023 at 12:14 PM liweiwei  wrote:
> >>
> >> On 2023/4/6 09:46, Alistair Francis wrote:
> >>> On Thu, Apr 6, 2023 at 10:56 AM liweiwei  wrote:
>  On 2023/4/6 08:43, Alistair Francis wrote:
> 
>  On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li  wrote:
> 
>  The MPP will be set to the least-privileged supported mode (U if
>  U-mode is implemented, else M).
> 
>  I don't think this is right, the spec in section 8.6.4 says this:
> 
>  Sorry, I didn't find this section in latest release of both privilege 
>  and un-privilege spec
> >>> I updated my spec, using commit
> >>> f6b8d5c7d2dcd935b48689a337c8f5bc2be4b5e5 it's now section 9.6.4 Trap
> >>> Return
> >> Yeah. I see it. However, this is a little different from the description
> >> in section 3.1.6.1.
> > They seem to be in conflict. It's probably worth opening an issue
> > against the spec to get some clarification here.
>
> I have sent an issue for
> it(https://github.com/riscv/riscv-isa-manual/issues/1006).
>
> However, I just find it may be not a conflict. Section 9.6.4 is the spec
> for hypervisor. And when hypervisor is supported,
>
> S-mode, then U-mode should be supported too.

Ah, I didn't think to check the actual section!

Good call. I think you are right then. In which case this patch is the
correct way to go :)

Feel free to close the issue if you want to.

Reviewed-by: Alistair Francis 

Alistair

>
> Regards,
>
> Weiwei Li
>
> >
> >> And MPP is WARL field.  PRV_U will be an illegal value for MPP if U-mode
> >> is not implemented.
> > Yeah, I think you are right. It just directly goes against the mret
> > section. I suspect the mret section is wrong and needs to be updated
> >
> >> So I think description in section 3.1.6.1 seems more reasonable.
> >>
>  (draft-20230131-c0b298a: Clarify WFI trapping behavior (#972)).
> >>> Also, you replied with a HTML email which loses the conversation
> >>> history (just see above). Can you fixup your client to reply with
> >>> plain text please
> >> Sorry. I don't get your problem. I replied by Thunderbird. Above is the
> > Have a look at your previous email, it's a HTML email. If I view the
> > source of the email I see this:
> >
> >  Content-Type: text/html; charset=UTF-8
> >
> > and the formatting is a little off.
> >
> > This email that I'm replying to is a plain text email. I'm not sure
> > what happened, but try to check that your responses are plain text. I
> > think there is a setting in Thunderbird to just open and reply to all
> > emails as plain text, which is probably worth turning on
> >
> > Alistair
> >
> >> title for the latest release version of the spec in riscv-isa-manual
> >> github
> >> (https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20230131-c0b298a).
> >>
> >> Regards,
> >>
> >> Weiwei Li
> >>
> >>> Alistair
> >>>
>  "MRET then in mstatus/mstatush sets MPV=0, MPP=0,
>  MIE=MPIE, and MPIE=1"
> 
>  In section 3.1.6.1, the privilege spec says this:
> 
>  "An MRET or SRET instruction is used to return from a trap in M-mode or 
>  S-mode respectively.
>  When executing an xRET instruction, supposing xPP holds the value y, xIE 
>  is set to xPIE; the
>  privilege mode is changed to y; xPIE is set to 1; and xPP is set to the 
>  least-privileged supported
>  mode (U if U-mode is implemented, else M). If y̸=M, xRET also sets 
>  MPRV=0"
> 
>  And I think PRV_U is an illegal value for MPP if U-mode is not 
>  implemented.
> 
>  Regards,
> 
>  Weiwei Li
> 
>  So it should just always be 0 (PRV_U is 0)
> 
>  Alistair
> 
>  Signed-off-by: Weiwei Li 
>  Signed-off-by: Junqiang Wang 
>  ---
> target/riscv/op_helper.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
> 
>  diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
>  index 84ee018f7d..991f06d98d 100644
>  --- a/target/riscv/op_helper.c
>  +++ b/target/riscv/op_helper.c
>  @@ -339,7 +339,8 @@ target_ulong helper_mret(CPURISCVState *env)
> mstatus = set_field(mstatus, MSTATUS_MIE,
> get_field(mstatus, MSTATUS_MPIE));
> mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
>  -mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
>  +mstatus = set_field(mstatus, MSTATUS_MPP,
>  +riscv_has_ext(env, RVU) ? PRV_U : PRV_M);
> mstatus = set_field(mstatus, MSTATUS_MPV, 0);
> if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != 
>  PRV_M)) {
> mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
>  --
>  2.25.1
> 
> 
>

RE: [PULL 36/53] memory: Optimize replay of guest mapping

[Duan, Zhenzhong]

>-Original Message-
>From: Michael S. Tsirkin 
>Sent: Wednesday, April 5, 2023 3:13 AM
>To: Peter Maydell 
>Cc: qemu-devel@nongnu.org; Duan, Zhenzhong
>; Peter Xu ; Jason Wang
>; Marcel Apfelbaum
>; Paolo Bonzini ;
>Richard Henderson ; Eduardo Habkost
>; David Hildenbrand ; Philippe
>Mathieu-Daudé 
>Subject: Re: [PULL 36/53] memory: Optimize replay of guest mapping
>
>On Tue, Apr 04, 2023 at 07:00:04PM +0100, Peter Maydell wrote:
>> On Thu, 2 Mar 2023 at 08:26, Michael S. Tsirkin  wrote:
>> >
>> > From: Zhenzhong Duan 
>> >
>> > On x86, there are two notifiers registered due to vtd-ir memory
>> > region splitting the whole address space. During replay of the
>> > address space for each notifier, the whole address space is scanned
>> > which is unnecessory.
>> >
>> > We only need to scan the space belong to notifier montiored space.
>> >
>> > Assert when notifier is used to monitor beyond iommu memory region's
>> > address space.
>>
>> Hi. This patch seems to have regressed the mps3-an547 board, which now
>> asserts on startup:
>>
>> $ ./build/x86/qemu-system-arm --machine mps3-an547 -serial stdio
>> -kernel /tmp/an547-mwe/build/test.elf
>> qemu-system-arm: ../../softmmu/memory.c:1903:
>> memory_region_register_iommu_notifier: Assertion `n->end <=
>> memory_region_size(mr)' failed.
>> Aborted (core dumped)
>>
>> (reported under https://gitlab.com/qemu-project/qemu/-/issues/1488)
>>
>> Since this commit says it's just an optimization, for the 8.0 release
>> can we simply revert it without breaking anything?
>>
>> > diff --git a/softmmu/memory.c b/softmmu/memory.c index
>> > 9d64efca26..da7d846619 100644
>> > --- a/softmmu/memory.c
>> > +++ b/softmmu/memory.c
>> > @@ -1900,6 +1900,7 @@ int
>memory_region_register_iommu_notifier(MemoryRegion *mr,
>> >  iommu_mr = IOMMU_MEMORY_REGION(mr);
>> >  assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
>> >  assert(n->start <= n->end);
>> > +assert(n->end <= memory_region_size(mr));
>>
>> In the mps3-an547 case we assert here because n->end is -1.
>> This is because tcg_register_iommu_notifier() registers an iommu
>> notifier that covers the entire address space:
>>
>> iommu_notifier_init(>n,
>> tcg_iommu_unmap_notify,
>> IOMMU_NOTIFIER_UNMAP,
>> 0,
>> HWADDR_MAX,
>> iommu_idx);
>> memory_region_register_iommu_notifier(notifier->mr, >n,
>>   _fatal);
>>
>> thanks
>> -- PMM
>
>
>Fine to revert by me.  Zhenzhong Duan  can you pls fix up this regression and
>repost? Maybe fix typos in commit log when reposting. Thanks!

Sorry for the trouble, I'll fix and repost a new version later with wider test.
Initial thought is to pick the intersection of iommu_mr and iommu notifier
in memory_region_iommu_replay(), then the assert() could be dropped.

Regards
Zhenzhong

Re: [PATCH 1/2] target/riscv: Fix the mstatus.MPP value after executing MRET

[liweiwei]

On 2023/4/6 10:24, Alistair Francis wrote:

On Thu, Apr 6, 2023 at 12:14 PM liweiwei  wrote:


On 2023/4/6 09:46, Alistair Francis wrote:

On Thu, Apr 6, 2023 at 10:56 AM liweiwei  wrote:

On 2023/4/6 08:43, Alistair Francis wrote:

On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li  wrote:

The MPP will be set to the least-privileged supported mode (U if
U-mode is implemented, else M).

I don't think this is right, the spec in section 8.6.4 says this:

Sorry, I didn't find this section in latest release of both privilege and 
un-privilege spec

I updated my spec, using commit
f6b8d5c7d2dcd935b48689a337c8f5bc2be4b5e5 it's now section 9.6.4 Trap
Return

Yeah. I see it. However, this is a little different from the description
in section 3.1.6.1.

They seem to be in conflict. It's probably worth opening an issue
against the spec to get some clarification here.


I have sent an issue for 
it(https://github.com/riscv/riscv-isa-manual/issues/1006).


However, I just find it may be not a conflict. Section 9.6.4 is the spec 
for hypervisor. And when hypervisor is supported,


S-mode, then U-mode should be supported too.

Regards,

Weiwei Li




And MPP is WARL field.  PRV_U will be an illegal value for MPP if U-mode
is not implemented.

Yeah, I think you are right. It just directly goes against the mret
section. I suspect the mret section is wrong and needs to be updated


So I think description in section 3.1.6.1 seems more reasonable.


(draft-20230131-c0b298a: Clarify WFI trapping behavior (#972)).

Also, you replied with a HTML email which loses the conversation
history (just see above). Can you fixup your client to reply with
plain text please

Sorry. I don't get your problem. I replied by Thunderbird. Above is the

Have a look at your previous email, it's a HTML email. If I view the
source of the email I see this:

 Content-Type: text/html; charset=UTF-8

and the formatting is a little off.

This email that I'm replying to is a plain text email. I'm not sure
what happened, but try to check that your responses are plain text. I
think there is a setting in Thunderbird to just open and reply to all
emails as plain text, which is probably worth turning on

Alistair


title for the latest release version of the spec in riscv-isa-manual
github
(https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20230131-c0b298a).

Regards,

Weiwei Li


Alistair


"MRET then in mstatus/mstatush sets MPV=0, MPP=0,
MIE=MPIE, and MPIE=1"

In section 3.1.6.1, the privilege spec says this:

"An MRET or SRET instruction is used to return from a trap in M-mode or S-mode 
respectively.
When executing an xRET instruction, supposing xPP holds the value y, xIE is set 
to xPIE; the
privilege mode is changed to y; xPIE is set to 1; and xPP is set to the 
least-privileged supported
mode (U if U-mode is implemented, else M). If y̸=M, xRET also sets MPRV=0"

And I think PRV_U is an illegal value for MPP if U-mode is not implemented.

Regards,

Weiwei Li

So it should just always be 0 (PRV_U is 0)

Alistair

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
---
   target/riscv/op_helper.c | 3 ++-
   1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 84ee018f7d..991f06d98d 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -339,7 +339,8 @@ target_ulong helper_mret(CPURISCVState *env)
   mstatus = set_field(mstatus, MSTATUS_MIE,
   get_field(mstatus, MSTATUS_MPIE));
   mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
-mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
+mstatus = set_field(mstatus, MSTATUS_MPP,
+riscv_has_ext(env, RVU) ? PRV_U : PRV_M);
   mstatus = set_field(mstatus, MSTATUS_MPV, 0);
   if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
   mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
--
2.25.1

Re: [PATCH 1/2] target/riscv: Fix the mstatus.MPP value after executing MRET

[liweiwei]

On 2023/4/6 10:24, Alistair Francis wrote:

On Thu, Apr 6, 2023 at 12:14 PM liweiwei  wrote:


On 2023/4/6 09:46, Alistair Francis wrote:

On Thu, Apr 6, 2023 at 10:56 AM liweiwei  wrote:

On 2023/4/6 08:43, Alistair Francis wrote:

On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li  wrote:

The MPP will be set to the least-privileged supported mode (U if
U-mode is implemented, else M).

I don't think this is right, the spec in section 8.6.4 says this:

Sorry, I didn't find this section in latest release of both privilege and 
un-privilege spec

I updated my spec, using commit
f6b8d5c7d2dcd935b48689a337c8f5bc2be4b5e5 it's now section 9.6.4 Trap
Return

Yeah. I see it. However, this is a little different from the description
in section 3.1.6.1.

They seem to be in conflict. It's probably worth opening an issue
against the spec to get some clarification here.

OK. I'll send an issue for it.



And MPP is WARL field.  PRV_U will be an illegal value for MPP if U-mode
is not implemented.

Yeah, I think you are right. It just directly goes against the mret
section. I suspect the mret section is wrong and needs to be updated


So I think description in section 3.1.6.1 seems more reasonable.


(draft-20230131-c0b298a: Clarify WFI trapping behavior (#972)).

Also, you replied with a HTML email which loses the conversation
history (just see above). Can you fixup your client to reply with
plain text please

Sorry. I don't get your problem. I replied by Thunderbird. Above is the

Have a look at your previous email, it's a HTML email. If I view the
source of the email I see this:

 Content-Type: text/html; charset=UTF-8

and the formatting is a little off.

This email that I'm replying to is a plain text email. I'm not sure
what happened, but try to check that your responses are plain text. I
think there is a setting in Thunderbird to just open and reply to all
emails as plain text, which is probably worth turning on


OK . Thanks! I'll try to set it later.

Regards,

Weiwei Li



Alistair


title for the latest release version of the spec in riscv-isa-manual
github
(https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20230131-c0b298a).

Regards,

Weiwei Li


Alistair


"MRET then in mstatus/mstatush sets MPV=0, MPP=0,
MIE=MPIE, and MPIE=1"

In section 3.1.6.1, the privilege spec says this:

"An MRET or SRET instruction is used to return from a trap in M-mode or S-mode 
respectively.
When executing an xRET instruction, supposing xPP holds the value y, xIE is set 
to xPIE; the
privilege mode is changed to y; xPIE is set to 1; and xPP is set to the 
least-privileged supported
mode (U if U-mode is implemented, else M). If y̸=M, xRET also sets MPRV=0"

And I think PRV_U is an illegal value for MPP if U-mode is not implemented.

Regards,

Weiwei Li

So it should just always be 0 (PRV_U is 0)

Alistair

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
---
   target/riscv/op_helper.c | 3 ++-
   1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 84ee018f7d..991f06d98d 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -339,7 +339,8 @@ target_ulong helper_mret(CPURISCVState *env)
   mstatus = set_field(mstatus, MSTATUS_MIE,
   get_field(mstatus, MSTATUS_MPIE));
   mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
-mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
+mstatus = set_field(mstatus, MSTATUS_MPP,
+riscv_has_ext(env, RVU) ? PRV_U : PRV_M);
   mstatus = set_field(mstatus, MSTATUS_MPV, 0);
   if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
   mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
--
2.25.1

Re: [PATCH v6 01/25] target/riscv: Extract virt enabled state from tb flags

[Alistair Francis]

On Sat, Mar 25, 2023 at 9:58 PM Richard Henderson
 wrote:
>
> From: LIU Zhiwei 
>
> Virt enabled state is not a constant. So we should put it into tb flags.
> Thus we can use it like a constant condition at translation phase.
>
> Reported-by: Richard Henderson 
> Reviewed-by: Richard Henderson 
> Signed-off-by: LIU Zhiwei 
> Reviewed-by: Weiwei Li 
> Message-Id: <20230324143031.1093-2-zhiwei_...@linux.alibaba.com>

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.h|  2 ++
>  target/riscv/cpu_helper.c |  2 ++
>  target/riscv/translate.c  | 10 +-
>  3 files changed, 5 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 638e47c75a..12fe8d8546 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -650,6 +650,8 @@ FIELD(TB_FLAGS, VTA, 24, 1)
>  FIELD(TB_FLAGS, VMA, 25, 1)
>  /* Native debug itrigger */
>  FIELD(TB_FLAGS, ITRIGGER, 26, 1)
> +/* Virtual mode enabled */
> +FIELD(TB_FLAGS, VIRT_ENABLED, 27, 1)
>
>  #ifdef TARGET_RISCV32
>  #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index f88c503cf4..9d50e7bbb6 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -104,6 +104,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, 
> target_ulong *pc,
>
>  flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
> get_field(env->mstatus_hs, MSTATUS_VS));
> +flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED,
> +   get_field(env->virt, VIRT_ONOFF));
>  }
>  if (cpu->cfg.debug && !icount_enabled()) {
>  flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 0ee8ee147d..880f6318aa 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1156,15 +1156,7 @@ static void 
> riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>  ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
>  ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
>  ctx->priv_ver = env->priv_ver;
> -#if !defined(CONFIG_USER_ONLY)
> -if (riscv_has_ext(env, RVH)) {
> -ctx->virt_enabled = riscv_cpu_virt_enabled(env);
> -} else {
> -ctx->virt_enabled = false;
> -}
> -#else
> -ctx->virt_enabled = false;
> -#endif
> +ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED);
>  ctx->misa_ext = env->misa_ext;
>  ctx->frm = -1;  /* unknown rounding mode */
>  ctx->cfg_ptr = &(cpu->cfg);
> --
> 2.34.1
>
>

[PATCH 1/2] accel/tcg/plugin: export host insn size

[Fei Wu]

The translation ratio of host to guest instruction count is one of the
key performance factor of binary translation. TCG doesn't collect host
instruction count at present, it does collect host instruction size
instead, although they are not the same thing as instruction size might
not be fixed, instruction size is still a valid estimation.

Signed-off-by: Fei Wu 
---
 accel/tcg/plugin-gen.c   | 1 +
 include/qemu/plugin.h| 2 ++
 include/qemu/qemu-plugin.h   | 8 
 plugins/api.c| 5 +
 plugins/qemu-plugins.symbols | 1 +
 5 files changed, 17 insertions(+)

diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index 5efb8db258..4a3ca8fa2f 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -881,6 +881,7 @@ bool plugin_gen_tb_start(CPUState *cpu, const 
DisasContextBase *db,
 ptb->haddr2 = NULL;
 ptb->mem_only = mem_only;
 ptb->mem_helper = false;
+ptb->host_insn_size = >tb->tc.size;
 
 plugin_gen_empty_callback(PLUGIN_GEN_FROM_TB);
 }
diff --git a/include/qemu/plugin.h b/include/qemu/plugin.h
index bc0781cab8..b38fd139e1 100644
--- a/include/qemu/plugin.h
+++ b/include/qemu/plugin.h
@@ -151,6 +151,8 @@ struct qemu_plugin_tb {
 /* if set, the TB calls helpers that might access guest memory */
 bool mem_helper;
 
+uint64_t *host_insn_size;
+
 GArray *cbs[PLUGIN_N_CB_SUBTYPES];
 };
 
diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h
index 50a9957279..2397574a21 100644
--- a/include/qemu/qemu-plugin.h
+++ b/include/qemu/qemu-plugin.h
@@ -336,6 +336,14 @@ void qemu_plugin_register_vcpu_insn_exec_inline(struct 
qemu_plugin_insn *insn,
  */
 size_t qemu_plugin_tb_n_insns(const struct qemu_plugin_tb *tb);
 
+/**
+ * qemu_plugin_tb_n_insns() - query helper for host insns size in TB
+ * @tb: opaque handle to TB passed to callback
+ *
+ * Returns: address of host insns size of this block
+ */
+void *qemu_plugin_tb_host_insn_size(const struct qemu_plugin_tb *tb);
+
 /**
  * qemu_plugin_tb_vaddr() - query helper for vaddr of TB start
  * @tb: opaque handle to TB passed to callback
diff --git a/plugins/api.c b/plugins/api.c
index 2078b16edb..0d70cb1f0f 100644
--- a/plugins/api.c
+++ b/plugins/api.c
@@ -188,6 +188,11 @@ size_t qemu_plugin_tb_n_insns(const struct qemu_plugin_tb 
*tb)
 return tb->n;
 }
 
+void *qemu_plugin_tb_host_insn_size(const struct qemu_plugin_tb *tb)
+{
+return tb->host_insn_size;
+}
+
 uint64_t qemu_plugin_tb_vaddr(const struct qemu_plugin_tb *tb)
 {
 return tb->vaddr;
diff --git a/plugins/qemu-plugins.symbols b/plugins/qemu-plugins.symbols
index 71f6c90549..3e92c3b8ba 100644
--- a/plugins/qemu-plugins.symbols
+++ b/plugins/qemu-plugins.symbols
@@ -39,6 +39,7 @@
   qemu_plugin_start_code;
   qemu_plugin_tb_get_insn;
   qemu_plugin_tb_n_insns;
+  qemu_plugin_tb_host_insn_size;
   qemu_plugin_tb_vaddr;
   qemu_plugin_uninstall;
   qemu_plugin_vcpu_for_each;
-- 
2.25.1

[PATCH 2/2] plugins/hotblocks: add host insn size

[Fei Wu]

It's only valid when inline=false, otherwise it's default to 0.

Signed-off-by: Fei Wu 
---
 contrib/plugins/hotblocks.c | 24 +++-
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/contrib/plugins/hotblocks.c b/contrib/plugins/hotblocks.c
index 062200a7a4..c9716da7fe 100644
--- a/contrib/plugins/hotblocks.c
+++ b/contrib/plugins/hotblocks.c
@@ -37,6 +37,8 @@ typedef struct {
 uint64_t exec_count;
 int  trans_count;
 unsigned long insns;
+void*p_host_insn_size;
+uint64_t host_insn_size;
 } ExecCount;
 
 static gint cmp_exec_count(gconstpointer a, gconstpointer b)
@@ -59,13 +61,17 @@ static void plugin_exit(qemu_plugin_id_t id, void *p)
 it = g_list_sort(counts, cmp_exec_count);
 
 if (it) {
-g_string_append_printf(report, "pc, tcount, icount, ecount\n");
+g_string_append_printf(report,
+   "host isize is only valid when inline=false\n"
+   "pc, tcount, icount, ecount, host isize\n");
 
 for (i = 0; i < limit && it->next; i++, it = it->next) {
 ExecCount *rec = (ExecCount *) it->data;
-g_string_append_printf(report, "0x%016"PRIx64", %d, %ld, 
%"PRId64"\n",
+g_string_append_printf(report, "0x%016"PRIx64", %d, %ld, %"PRId64
+   ", %"PRIu64"\n",
rec->start_addr, rec->trans_count,
-   rec->insns, rec->exec_count);
+   rec->insns, rec->exec_count,
+   rec->host_insn_size);
 }
 
 g_list_free(it);
@@ -82,14 +88,13 @@ static void plugin_init(void)
 
 static void vcpu_tb_exec(unsigned int cpu_index, void *udata)
 {
-ExecCount *cnt;
-uint64_t hash = (uint64_t) udata;
+ExecCount *cnt = (ExecCount *) udata;
 
 g_mutex_lock();
-cnt = (ExecCount *) g_hash_table_lookup(hotblocks, (gconstpointer) hash);
-/* should always succeed */
-g_assert(cnt);
 cnt->exec_count++;
+if (cnt->host_insn_size == 0) {
+cnt->host_insn_size = *((uint64_t *)cnt->p_host_insn_size);
+}
 g_mutex_unlock();
 }
 
@@ -114,6 +119,7 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct 
qemu_plugin_tb *tb)
 cnt->start_addr = pc;
 cnt->trans_count = 1;
 cnt->insns = insns;
+cnt->p_host_insn_size = qemu_plugin_tb_host_insn_size(tb);
 g_hash_table_insert(hotblocks, (gpointer) hash, (gpointer) cnt);
 }
 
@@ -125,7 +131,7 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct 
qemu_plugin_tb *tb)
 } else {
 qemu_plugin_register_vcpu_tb_exec_cb(tb, vcpu_tb_exec,
  QEMU_PLUGIN_CB_NO_REGS,
- (void *)hash);
+ (void *)cnt);
 }
 }
 
-- 
2.25.1

[PATCH 0/2] accel/tcg/plugin: host insn size for plugin

[Fei Wu]

The translation ratio of host to guest instruction count is one of the
key performance factor of binary translation. It's better to have this
kind of information exported to plugin for analysis. As the host insn
size is not determined at guest->IR time, its address is recorded for
later dereference, and plugin inline mode is not supported.

Here is an example of the output with modified plugin hotblocks:

pc, tcount, icount, ecount, host isize
0x8041ad6c, 1, 9, 130450345, 456
0x800084f0, 1, 9, 88273714, 264
0x800084e4, 1, 3, 88264146, 135
0x8041abd0, 1, 1, 46032689, 123
0x8041ab3c, 1, 1, 46021650, 123
0x8045ffe8, 1, 5, 40927215, 328

Fei Wu (2):
  accel/tcg/plugin: export host insn size
  plugins/hotblocks: add host insn size

 accel/tcg/plugin-gen.c   |  1 +
 contrib/plugins/hotblocks.c  | 24 +++-
 include/qemu/plugin.h|  2 ++
 include/qemu/qemu-plugin.h   |  8 
 plugins/api.c|  5 +
 plugins/qemu-plugins.symbols |  1 +
 6 files changed, 32 insertions(+), 9 deletions(-)

-- 
2.25.1

Re: [PATCH 1/2] target/riscv: Fix the mstatus.MPP value after executing MRET

[Alistair Francis]

On Thu, Apr 6, 2023 at 12:14 PM liweiwei  wrote:
>
>
> On 2023/4/6 09:46, Alistair Francis wrote:
> > On Thu, Apr 6, 2023 at 10:56 AM liweiwei  wrote:
> >>
> >> On 2023/4/6 08:43, Alistair Francis wrote:
> >>
> >> On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li  wrote:
> >>
> >> The MPP will be set to the least-privileged supported mode (U if
> >> U-mode is implemented, else M).
> >>
> >> I don't think this is right, the spec in section 8.6.4 says this:
> >>
> >> Sorry, I didn't find this section in latest release of both privilege and 
> >> un-privilege spec
> > I updated my spec, using commit
> > f6b8d5c7d2dcd935b48689a337c8f5bc2be4b5e5 it's now section 9.6.4 Trap
> > Return
>
> Yeah. I see it. However, this is a little different from the description
> in section 3.1.6.1.

They seem to be in conflict. It's probably worth opening an issue
against the spec to get some clarification here.

>
> And MPP is WARL field.  PRV_U will be an illegal value for MPP if U-mode
> is not implemented.

Yeah, I think you are right. It just directly goes against the mret
section. I suspect the mret section is wrong and needs to be updated

>
> So I think description in section 3.1.6.1 seems more reasonable.
>
> >
> >> (draft-20230131-c0b298a: Clarify WFI trapping behavior (#972)).
> > Also, you replied with a HTML email which loses the conversation
> > history (just see above). Can you fixup your client to reply with
> > plain text please
>
> Sorry. I don't get your problem. I replied by Thunderbird. Above is the

Have a look at your previous email, it's a HTML email. If I view the
source of the email I see this:

Content-Type: text/html; charset=UTF-8

and the formatting is a little off.

This email that I'm replying to is a plain text email. I'm not sure
what happened, but try to check that your responses are plain text. I
think there is a setting in Thunderbird to just open and reply to all
emails as plain text, which is probably worth turning on

Alistair

> title for the latest release version of the spec in riscv-isa-manual
> github
> (https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20230131-c0b298a).
>
> Regards,
>
> Weiwei Li
>
> >
> > Alistair
> >
> >> "MRET then in mstatus/mstatush sets MPV=0, MPP=0,
> >> MIE=MPIE, and MPIE=1"
> >>
> >> In section 3.1.6.1, the privilege spec says this:
> >>
> >> "An MRET or SRET instruction is used to return from a trap in M-mode or 
> >> S-mode respectively.
> >> When executing an xRET instruction, supposing xPP holds the value y, xIE 
> >> is set to xPIE; the
> >> privilege mode is changed to y; xPIE is set to 1; and xPP is set to the 
> >> least-privileged supported
> >> mode (U if U-mode is implemented, else M). If y̸=M, xRET also sets MPRV=0"
> >>
> >> And I think PRV_U is an illegal value for MPP if U-mode is not implemented.
> >>
> >> Regards,
> >>
> >> Weiwei Li
> >>
> >> So it should just always be 0 (PRV_U is 0)
> >>
> >> Alistair
> >>
> >> Signed-off-by: Weiwei Li 
> >> Signed-off-by: Junqiang Wang 
> >> ---
> >>   target/riscv/op_helper.c | 3 ++-
> >>   1 file changed, 2 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> >> index 84ee018f7d..991f06d98d 100644
> >> --- a/target/riscv/op_helper.c
> >> +++ b/target/riscv/op_helper.c
> >> @@ -339,7 +339,8 @@ target_ulong helper_mret(CPURISCVState *env)
> >>   mstatus = set_field(mstatus, MSTATUS_MIE,
> >>   get_field(mstatus, MSTATUS_MPIE));
> >>   mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
> >> -mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
> >> +mstatus = set_field(mstatus, MSTATUS_MPP,
> >> +riscv_has_ext(env, RVU) ? PRV_U : PRV_M);
> >>   mstatus = set_field(mstatus, MSTATUS_MPV, 0);
> >>   if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
> >>   mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
> >> --
> >> 2.25.1
> >>
> >>
>

Re: [PATCH 1/2] target/riscv: Fix the mstatus.MPP value after executing MRET

[liweiwei]

On 2023/4/6 09:46, Alistair Francis wrote:

On Thu, Apr 6, 2023 at 10:56 AM liweiwei  wrote:


On 2023/4/6 08:43, Alistair Francis wrote:

On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li  wrote:

The MPP will be set to the least-privileged supported mode (U if
U-mode is implemented, else M).

I don't think this is right, the spec in section 8.6.4 says this:

Sorry, I didn't find this section in latest release of both privilege and 
un-privilege spec

I updated my spec, using commit
f6b8d5c7d2dcd935b48689a337c8f5bc2be4b5e5 it's now section 9.6.4 Trap
Return


Yeah. I see it. However, this is a little different from the description 
in section 3.1.6.1.


And MPP is WARL field.  PRV_U will be an illegal value for MPP if U-mode 
is not implemented.


So I think description in section 3.1.6.1 seems more reasonable.




(draft-20230131-c0b298a: Clarify WFI trapping behavior (#972)).

Also, you replied with a HTML email which loses the conversation
history (just see above). Can you fixup your client to reply with
plain text please


Sorry. I don't get your problem. I replied by Thunderbird. Above is the 
title for the latest release version of the spec in riscv-isa-manual 
github 
(https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20230131-c0b298a).


Regards,

Weiwei Li



Alistair


"MRET then in mstatus/mstatush sets MPV=0, MPP=0,
MIE=MPIE, and MPIE=1"

In section 3.1.6.1, the privilege spec says this:

"An MRET or SRET instruction is used to return from a trap in M-mode or S-mode 
respectively.
When executing an xRET instruction, supposing xPP holds the value y, xIE is set 
to xPIE; the
privilege mode is changed to y; xPIE is set to 1; and xPP is set to the 
least-privileged supported
mode (U if U-mode is implemented, else M). If y̸=M, xRET also sets MPRV=0"

And I think PRV_U is an illegal value for MPP if U-mode is not implemented.

Regards,

Weiwei Li

So it should just always be 0 (PRV_U is 0)

Alistair

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
---
  target/riscv/op_helper.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 84ee018f7d..991f06d98d 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -339,7 +339,8 @@ target_ulong helper_mret(CPURISCVState *env)
  mstatus = set_field(mstatus, MSTATUS_MIE,
  get_field(mstatus, MSTATUS_MPIE));
  mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
-mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
+mstatus = set_field(mstatus, MSTATUS_MPP,
+riscv_has_ext(env, RVU) ? PRV_U : PRV_M);
  mstatus = set_field(mstatus, MSTATUS_MPV, 0);
  if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
  mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
--
2.25.1

Re: [PATCH v6 8/9] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()

[Alistair Francis]

On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
 wrote:
>
> We have 4 config settings being done in riscv_cpu_init(): ext_ifencei,
> ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu"
> device, which happens to be the parent device of every RISC-V cpu.
>
> The result is that these 4 configs are being set every time, and every
> other CPU should always account for them. CPUs such as sifive_e need to
> disable settings that aren't enabled simply because the parent class
> happens to be enabling it.
>
> Moving all configurations from the parent class to each CPU will
> centralize the config of each CPU into its own init(), which is clearer
> than having to account to whatever happens to be set in the parent
> device. These settings are also being set in register_cpu_props() when
> no 'misa_ext' is set, so for these CPUs we don't need changes. Named
> CPUs will receive all cfgs that the parent were setting into their
> init().
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: LIU Zhiwei 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 59 --
>  1 file changed, 47 insertions(+), 12 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 331272c8a0..4aa119b9bc 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -325,7 +325,8 @@ static void set_satp_mode_default_map(RISCVCPU *cpu)
>
>  static void riscv_any_cpu_init(Object *obj)
>  {
> -CPURISCVState *env = _CPU(obj)->env;
> +RISCVCPU *cpu = RISCV_CPU(obj);
> +CPURISCVState *env = >env;
>  #if defined(TARGET_RISCV32)
>  set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
>  #elif defined(TARGET_RISCV64)
> @@ -339,6 +340,12 @@ static void riscv_any_cpu_init(Object *obj)
>  #endif
>
>  env->priv_ver = PRIV_VERSION_LATEST;
> +
> +/* inherited from parent obj via riscv_cpu_init() */
> +cpu->cfg.ext_ifencei = true;
> +cpu->cfg.ext_icsr = true;
> +cpu->cfg.mmu = true;
> +cpu->cfg.pmp = true;
>  }
>
>  #if defined(TARGET_RISCV64)
> @@ -357,12 +364,19 @@ static void rv64_base_cpu_init(Object *obj)
>
>  static void rv64_sifive_u_cpu_init(Object *obj)
>  {
> -CPURISCVState *env = _CPU(obj)->env;
> +RISCVCPU *cpu = RISCV_CPU(obj);
> +CPURISCVState *env = >env;
>  set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
>  env->priv_ver = PRIV_VERSION_1_10_0;
>  #ifndef CONFIG_USER_ONLY
>  set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
>  #endif
> +
> +/* inherited from parent obj via riscv_cpu_init() */
> +cpu->cfg.ext_ifencei = true;
> +cpu->cfg.ext_icsr = true;
> +cpu->cfg.mmu = true;
> +cpu->cfg.pmp = true;
>  }
>
>  static void rv64_sifive_e_cpu_init(Object *obj)
> @@ -372,10 +386,14 @@ static void rv64_sifive_e_cpu_init(Object *obj)
>
>  set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
>  env->priv_ver = PRIV_VERSION_1_10_0;
> -cpu->cfg.mmu = false;
>  #ifndef CONFIG_USER_ONLY
>  set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
>  #endif
> +
> +/* inherited from parent obj via riscv_cpu_init() */
> +cpu->cfg.ext_ifencei = true;
> +cpu->cfg.ext_icsr = true;
> +cpu->cfg.pmp = true;
>  }
>
>  static void rv64_thead_c906_cpu_init(Object *obj)
> @@ -403,6 +421,9 @@ static void rv64_thead_c906_cpu_init(Object *obj)
>  #ifndef CONFIG_USER_ONLY
>  set_satp_mode_max_supported(cpu, VM_1_10_SV39);
>  #endif
> +
> +/* inherited from parent obj via riscv_cpu_init() */
> +cpu->cfg.pmp = true;
>  }
>
>  static void rv128_base_cpu_init(Object *obj)
> @@ -439,12 +460,19 @@ static void rv32_base_cpu_init(Object *obj)
>
>  static void rv32_sifive_u_cpu_init(Object *obj)
>  {
> -CPURISCVState *env = _CPU(obj)->env;
> +RISCVCPU *cpu = RISCV_CPU(obj);
> +CPURISCVState *env = >env;
>  set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
>  env->priv_ver = PRIV_VERSION_1_10_0;
>  #ifndef CONFIG_USER_ONLY
>  set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
>  #endif
> +
> +/* inherited from parent obj via riscv_cpu_init() */
> +cpu->cfg.ext_ifencei = true;
> +cpu->cfg.ext_icsr = true;
> +cpu->cfg.mmu = true;
> +cpu->cfg.pmp = true;
>  }
>
>  static void rv32_sifive_e_cpu_init(Object *obj)
> @@ -454,10 +482,14 @@ static void rv32_sifive_e_cpu_init(Object *obj)
>
>  set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
>  env->priv_ver = PRIV_VERSION_1_10_0;
> -cpu->cfg.mmu = false;
>  #ifndef CONFIG_USER_ONLY
>  set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
>  #endif
> +
> +/* inherited from parent obj via riscv_cpu_init() */
> +cpu->cfg.ext_ifencei = true;
> +cpu->cfg.ext_icsr = true;
> +cpu->cfg.pmp = true;
>  }
>
>  static void rv32_ibex_cpu_init(Object *obj)
> @@ -467,11 +499,15 @@ static void rv32_ibex_cpu_init(Object *obj)
>
>  set_misa(env, 

Re: [PATCH v6 7/9] target/riscv/cpu.c: validate extensions before riscv_timer_init()

[Alistair Francis]

On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
 wrote:
>
> There is no need to init timers if we're not even sure that our
> extensions are valid. Execute riscv_cpu_validate_set_extensions() before
> riscv_timer_init().
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: LIU Zhiwei 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 11 ---
>  1 file changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index e8045840bd..331272c8a0 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1196,13 +1196,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>  return;
>  }
>
> -
> -#ifndef CONFIG_USER_ONLY
> -if (cpu->cfg.ext_sstc) {
> -riscv_timer_init(cpu);
> -}
> -#endif /* CONFIG_USER_ONLY */
> -
>  riscv_cpu_validate_set_extensions(cpu, _err);
>  if (local_err != NULL) {
>  error_propagate(errp, local_err);
> @@ -1210,6 +1203,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>  }
>
>  #ifndef CONFIG_USER_ONLY
> +if (cpu->cfg.ext_sstc) {
> +riscv_timer_init(cpu);
> +}
> +
>  if (cpu->cfg.pmu_num) {
>  if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) 
> {
>  cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
> --
> 2.39.2
>
>

Re: [PATCH v6 6/9] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()

[Alistair Francis]

On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
 wrote:
>
> Let's remove more code that is open coded in riscv_cpu_realize() and put
> it into a helper. Let's also add an error message instead of just
> asserting out if env->misa_mxl_max != env->misa_mlx.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: LIU Zhiwei 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 50 ++
>  1 file changed, 33 insertions(+), 17 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 8f0620376c..e8045840bd 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -866,6 +866,33 @@ static void 
> riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
>  }
>  }
>
> +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
> +{
> +RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
> +CPUClass *cc = CPU_CLASS(mcc);
> +CPURISCVState *env = >env;
> +
> +/* Validate that MISA_MXL is set properly. */
> +switch (env->misa_mxl_max) {
> +#ifdef TARGET_RISCV64
> +case MXL_RV64:
> +case MXL_RV128:
> +cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
> +break;
> +#endif
> +case MXL_RV32:
> +cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
> +break;
> +default:
> +g_assert_not_reached();
> +}
> +
> +if (env->misa_mxl_max != env->misa_mxl) {
> +error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
> +return;
> +}
> +}
> +
>  /*
>   * Check consistency between chosen extensions while setting
>   * cpu->cfg accordingly.
> @@ -1134,7 +1161,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>  RISCVCPU *cpu = RISCV_CPU(dev);
>  CPURISCVState *env = >env;
>  RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> -CPUClass *cc = CPU_CLASS(mcc);
>  Error *local_err = NULL;
>
>  cpu_exec_realizefn(cs, _err);
> @@ -1143,6 +1169,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>  return;
>  }
>
> +riscv_cpu_validate_misa_mxl(cpu, _err);
> +if (local_err != NULL) {
> +error_propagate(errp, local_err);
> +return;
> +}
> +
>  riscv_cpu_validate_priv_spec(cpu, _err);
>  if (local_err != NULL) {
>  error_propagate(errp, local_err);
> @@ -1171,22 +1203,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>  }
>  #endif /* CONFIG_USER_ONLY */
>
> -/* Validate that MISA_MXL is set properly. */
> -switch (env->misa_mxl_max) {
> -#ifdef TARGET_RISCV64
> -case MXL_RV64:
> -case MXL_RV128:
> -cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
> -break;
> -#endif
> -case MXL_RV32:
> -cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
> -break;
> -default:
> -g_assert_not_reached();
> -}
> -assert(env->misa_mxl_max == env->misa_mxl);
> -
>  riscv_cpu_validate_set_extensions(cpu, _err);
>  if (local_err != NULL) {
>  error_propagate(errp, local_err);
> --
> 2.39.2
>
>

Re: [PATCH v6 5/9] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers

[Alistair Francis]

On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
 wrote:
>
> We're doing env->priv_spec validation and assignment at the start of
> riscv_cpu_realize(), which is fine, but then we're doing a force disable
> on extensions that aren't compatible with the priv version.
>
> This second step is being done too early. The disabled extensions might be
> re-enabled again in riscv_cpu_validate_set_extensions() by accident. A
> better place to put this code is at the end of
> riscv_cpu_validate_set_extensions() after all the validations are
> completed.
>
> Add a new helper, riscv_cpu_disable_priv_spec_isa_exts(), to disable the
> extesions after the validation is done. While we're at it, create a
> riscv_cpu_validate_priv_spec() helper to host all env->priv_spec related
> validation to unclog riscv_cpu_realize a bit.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: LIU Zhiwei 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 91 --
>  1 file changed, 56 insertions(+), 35 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1743e9ede3..8f0620376c 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -820,6 +820,52 @@ static void riscv_cpu_validate_v(CPURISCVState *env, 
> RISCVCPUConfig *cfg,
>  env->vext_ver = vext_version;
>  }
>
> +static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
> +{
> +CPURISCVState *env = >env;
> +int priv_version = -1;
> +
> +if (cpu->cfg.priv_spec) {
> +if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
> +priv_version = PRIV_VERSION_1_12_0;
> +} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
> +priv_version = PRIV_VERSION_1_11_0;
> +} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
> +priv_version = PRIV_VERSION_1_10_0;
> +} else {
> +error_setg(errp,
> +   "Unsupported privilege spec version '%s'",
> +   cpu->cfg.priv_spec);
> +return;
> +}
> +
> +env->priv_ver = priv_version;
> +}
> +}
> +
> +static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> +{
> +CPURISCVState *env = >env;
> +int i;
> +
> +/* Force disable extensions if priv spec version does not match */
> +for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> +if (isa_ext_is_enabled(cpu, _edata_arr[i]) &&
> +(env->priv_ver < isa_edata_arr[i].min_version)) {
> +isa_ext_update_enabled(cpu, _edata_arr[i], false);
> +#ifndef CONFIG_USER_ONLY
> +warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
> +" because privilege spec version does not match",
> +isa_edata_arr[i].name, env->mhartid);
> +#else
> +warn_report("disabling %s extension because "
> +"privilege spec version does not match",
> +isa_edata_arr[i].name);
> +#endif
> +}
> +}
> +}
> +
>  /*
>   * Check consistency between chosen extensions while setting
>   * cpu->cfg accordingly.
> @@ -984,6 +1030,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  cpu->cfg.ext_zksed = true;
>  cpu->cfg.ext_zksh = true;
>  }
> +
> +/*
> + * Disable isa extensions based on priv spec after we
> + * validated and set everything we need.
> + */
> +riscv_cpu_disable_priv_spec_isa_exts(cpu);
>  }
>
>  #ifndef CONFIG_USER_ONLY
> @@ -1083,7 +1135,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>  CPURISCVState *env = >env;
>  RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
>  CPUClass *cc = CPU_CLASS(mcc);
> -int i, priv_version = -1;
>  Error *local_err = NULL;
>
>  cpu_exec_realizefn(cs, _err);
> @@ -1092,23 +1143,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>  return;
>  }
>
> -if (cpu->cfg.priv_spec) {
> -if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
> -priv_version = PRIV_VERSION_1_12_0;
> -} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
> -priv_version = PRIV_VERSION_1_11_0;
> -} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
> -priv_version = PRIV_VERSION_1_10_0;
> -} else {
> -error_setg(errp,
> -   "Unsupported privilege spec version '%s'",
> -   cpu->cfg.priv_spec);
> -return;
> -}
> -}
> -
> -if (priv_version >= PRIV_VERSION_1_10_0) {
> -env->priv_ver = priv_version;
> +riscv_cpu_validate_priv_spec(cpu, _err);
> +if (local_err != NULL) {
> +error_propagate(errp, local_err);
> +return;
>  }
>
>  riscv_cpu_validate_misa_priv(env, _err);
> @@ -1117,23 +1155,6 @@ static void 

Re: [PATCH v6 4/9] target/riscv: add PRIV_VERSION_LATEST

[Alistair Francis]

On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
 wrote:
>
> All these generic CPUs are using the latest priv available, at this
> moment PRIV_VERSION_1_12_0:
>
> - riscv_any_cpu_init()
> - rv32_base_cpu_init()
> - rv64_base_cpu_init()
> - rv128_base_cpu_init()
>
> Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll
> make it easier to update everything at once when a new priv version is
> available.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Richard Henderson 
> Reviewed-by: LIU Zhiwei 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 8 
>  target/riscv/cpu.h | 2 ++
>  2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 75c3d4ed22..1743e9ede3 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -338,7 +338,7 @@ static void riscv_any_cpu_init(Object *obj)
>  VM_1_10_SV32 : VM_1_10_SV57);
>  #endif
>
> -env->priv_ver = PRIV_VERSION_1_12_0;
> +env->priv_ver = PRIV_VERSION_LATEST;
>  }
>
>  #if defined(TARGET_RISCV64)
> @@ -349,7 +349,7 @@ static void rv64_base_cpu_init(Object *obj)
>  set_misa(env, MXL_RV64, 0);
>  riscv_cpu_add_user_properties(obj);
>  /* Set latest version of privileged specification */
> -env->priv_ver = PRIV_VERSION_1_12_0;
> +env->priv_ver = PRIV_VERSION_LATEST;
>  #ifndef CONFIG_USER_ONLY
>  set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
>  #endif
> @@ -418,7 +418,7 @@ static void rv128_base_cpu_init(Object *obj)
>  set_misa(env, MXL_RV128, 0);
>  riscv_cpu_add_user_properties(obj);
>  /* Set latest version of privileged specification */
> -env->priv_ver = PRIV_VERSION_1_12_0;
> +env->priv_ver = PRIV_VERSION_LATEST;
>  #ifndef CONFIG_USER_ONLY
>  set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
>  #endif
> @@ -431,7 +431,7 @@ static void rv32_base_cpu_init(Object *obj)
>  set_misa(env, MXL_RV32, 0);
>  riscv_cpu_add_user_properties(obj);
>  /* Set latest version of privileged specification */
> -env->priv_ver = PRIV_VERSION_1_12_0;
> +env->priv_ver = PRIV_VERSION_LATEST;
>  #ifndef CONFIG_USER_ONLY
>  set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
>  #endif
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 02f26130d5..03b5cc2cf4 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -86,6 +86,8 @@ enum {
>  PRIV_VERSION_1_10_0 = 0,
>  PRIV_VERSION_1_11_0,
>  PRIV_VERSION_1_12_0,
> +
> +PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0,
>  };
>
>  #define VEXT_VERSION_1_00_0 0x0001
> --
> 2.39.2
>
>

Re: [PATCH v6 3/9] target/riscv/cpu.c: remove set_priv_version()

[Alistair Francis]

On Thu, Mar 30, 2023 at 6:09 AM Daniel Henrique Barboza
 wrote:
>
> The setter is doing nothing special. Just set env->priv_ver directly.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: LIU Zhiwei 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 29 -
>  1 file changed, 12 insertions(+), 17 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 19e0a6a902..75c3d4ed22 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -240,11 +240,6 @@ static void set_misa(CPURISCVState *env, RISCVMXL mxl, 
> uint32_t ext)
>  env->misa_ext_mask = env->misa_ext = ext;
>  }
>
> -static void set_priv_version(CPURISCVState *env, int priv_ver)
> -{
> -env->priv_ver = priv_ver;
> -}
> -
>  #ifndef CONFIG_USER_ONLY
>  static uint8_t satp_mode_from_str(const char *satp_mode_str)
>  {
> @@ -343,7 +338,7 @@ static void riscv_any_cpu_init(Object *obj)
>  VM_1_10_SV32 : VM_1_10_SV57);
>  #endif
>
> -set_priv_version(env, PRIV_VERSION_1_12_0);
> +env->priv_ver = PRIV_VERSION_1_12_0;
>  }
>
>  #if defined(TARGET_RISCV64)
> @@ -354,7 +349,7 @@ static void rv64_base_cpu_init(Object *obj)
>  set_misa(env, MXL_RV64, 0);
>  riscv_cpu_add_user_properties(obj);
>  /* Set latest version of privileged specification */
> -set_priv_version(env, PRIV_VERSION_1_12_0);
> +env->priv_ver = PRIV_VERSION_1_12_0;
>  #ifndef CONFIG_USER_ONLY
>  set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
>  #endif
> @@ -364,7 +359,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)
>  {
>  CPURISCVState *env = _CPU(obj)->env;
>  set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> -set_priv_version(env, PRIV_VERSION_1_10_0);
> +env->priv_ver = PRIV_VERSION_1_10_0;
>  #ifndef CONFIG_USER_ONLY
>  set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
>  #endif
> @@ -376,7 +371,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
>  RISCVCPU *cpu = RISCV_CPU(obj);
>
>  set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
> -set_priv_version(env, PRIV_VERSION_1_10_0);
> +env->priv_ver = PRIV_VERSION_1_10_0;
>  cpu->cfg.mmu = false;
>  #ifndef CONFIG_USER_ONLY
>  set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -389,7 +384,7 @@ static void rv64_thead_c906_cpu_init(Object *obj)
>  RISCVCPU *cpu = RISCV_CPU(obj);
>
>  set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
> -set_priv_version(env, PRIV_VERSION_1_11_0);
> +env->priv_ver = PRIV_VERSION_1_11_0;
>
>  cpu->cfg.ext_zfh = true;
>  cpu->cfg.mmu = true;
> @@ -423,7 +418,7 @@ static void rv128_base_cpu_init(Object *obj)
>  set_misa(env, MXL_RV128, 0);
>  riscv_cpu_add_user_properties(obj);
>  /* Set latest version of privileged specification */
> -set_priv_version(env, PRIV_VERSION_1_12_0);
> +env->priv_ver = PRIV_VERSION_1_12_0;
>  #ifndef CONFIG_USER_ONLY
>  set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
>  #endif
> @@ -436,7 +431,7 @@ static void rv32_base_cpu_init(Object *obj)
>  set_misa(env, MXL_RV32, 0);
>  riscv_cpu_add_user_properties(obj);
>  /* Set latest version of privileged specification */
> -set_priv_version(env, PRIV_VERSION_1_12_0);
> +env->priv_ver = PRIV_VERSION_1_12_0;
>  #ifndef CONFIG_USER_ONLY
>  set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
>  #endif
> @@ -446,7 +441,7 @@ static void rv32_sifive_u_cpu_init(Object *obj)
>  {
>  CPURISCVState *env = _CPU(obj)->env;
>  set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> -set_priv_version(env, PRIV_VERSION_1_10_0);
> +env->priv_ver = PRIV_VERSION_1_10_0;
>  #ifndef CONFIG_USER_ONLY
>  set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
>  #endif
> @@ -458,7 +453,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
>  RISCVCPU *cpu = RISCV_CPU(obj);
>
>  set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
> -set_priv_version(env, PRIV_VERSION_1_10_0);
> +env->priv_ver = PRIV_VERSION_1_10_0;
>  cpu->cfg.mmu = false;
>  #ifndef CONFIG_USER_ONLY
>  set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -471,7 +466,7 @@ static void rv32_ibex_cpu_init(Object *obj)
>  RISCVCPU *cpu = RISCV_CPU(obj);
>
>  set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
> -set_priv_version(env, PRIV_VERSION_1_11_0);
> +env->priv_ver = PRIV_VERSION_1_11_0;
>  cpu->cfg.mmu = false;
>  #ifndef CONFIG_USER_ONLY
>  set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -485,7 +480,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
>  RISCVCPU *cpu = RISCV_CPU(obj);
>
>  set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
> -set_priv_version(env, PRIV_VERSION_1_10_0);
> +env->priv_ver = PRIV_VERSION_1_10_0;
>  cpu->cfg.mmu = false;
>  #ifndef CONFIG_USER_ONLY
>  

Re: [PATCH v6 2/9] target/riscv/cpu.c: remove set_vext_version()

[Alistair Francis]

On Thu, Mar 30, 2023 at 6:09 AM Daniel Henrique Barboza
 wrote:
>
> This setter is doing nothing else but setting env->vext_ver. Assign the
> value directly.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: LIU Zhiwei 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 7 +--
>  1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 610e55cb04..19e0a6a902 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -245,11 +245,6 @@ static void set_priv_version(CPURISCVState *env, int 
> priv_ver)
>  env->priv_ver = priv_ver;
>  }
>
> -static void set_vext_version(CPURISCVState *env, int vext_ver)
> -{
> -env->vext_ver = vext_ver;
> -}
> -
>  #ifndef CONFIG_USER_ONLY
>  static uint8_t satp_mode_from_str(const char *satp_mode_str)
>  {
> @@ -827,7 +822,7 @@ static void riscv_cpu_validate_v(CPURISCVState *env, 
> RISCVCPUConfig *cfg,
>  qemu_log("vector version is not specified, "
>   "use the default value v1.0\n");
>  }
> -set_vext_version(env, vext_version);
> +env->vext_ver = vext_version;
>  }
>
>  /*
> --
> 2.39.2
>
>

Re: [PATCH v6 1/9] target/riscv/cpu.c: add riscv_cpu_validate_v()

[Alistair Francis]

On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
 wrote:
>
> The RVV verification will error out if fails and it's being done at the
> end of riscv_cpu_validate_set_extensions(), after we've already set some
> extensions that are dependent on RVV.  Let's put it in its own function
> and do it earlier.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: LIU Zhiwei 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 89 +-
>  1 file changed, 48 insertions(+), 41 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d8568a024c..610e55cb04 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -790,6 +790,46 @@ static void riscv_cpu_disas_set_info(CPUState *s, 
> disassemble_info *info)
>  }
>  }
>
> +static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
> + Error **errp)
> +{
> +int vext_version = VEXT_VERSION_1_00_0;
> +
> +if (!is_power_of_2(cfg->vlen)) {
> +error_setg(errp, "Vector extension VLEN must be power of 2");
> +return;
> +}
> +if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
> +error_setg(errp,
> +   "Vector extension implementation only supports VLEN "
> +   "in the range [128, %d]", RV_VLEN_MAX);
> +return;
> +}
> +if (!is_power_of_2(cfg->elen)) {
> +error_setg(errp, "Vector extension ELEN must be power of 2");
> +return;
> +}
> +if (cfg->elen > 64 || cfg->elen < 8) {
> +error_setg(errp,
> +   "Vector extension implementation only supports ELEN "
> +   "in the range [8, 64]");
> +return;
> +}
> +if (cfg->vext_spec) {
> +if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
> +vext_version = VEXT_VERSION_1_00_0;
> +} else {
> +error_setg(errp, "Unsupported vector spec version '%s'",
> +   cfg->vext_spec);
> +return;
> +}
> +} else {
> +qemu_log("vector version is not specified, "
> + "use the default value v1.0\n");
> +}
> +set_vext_version(env, vext_version);
> +}
> +
>  /*
>   * Check consistency between chosen extensions while setting
>   * cpu->cfg accordingly.
> @@ -797,6 +837,7 @@ static void riscv_cpu_disas_set_info(CPUState *s, 
> disassemble_info *info)
>  static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>  {
>  CPURISCVState *env = >env;
> +Error *local_err = NULL;
>
>  /* Do some ISA extension error checking */
>  if (riscv_has_ext(env, RVG) &&
> @@ -865,8 +906,14 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  return;
>  }
>
> -/* The V vector extension depends on the Zve64d extension */
>  if (riscv_has_ext(env, RVV)) {
> +riscv_cpu_validate_v(env, >cfg, _err);
> +if (local_err != NULL) {
> +error_propagate(errp, local_err);
> +return;
> +}
> +
> +/* The V vector extension depends on the Zve64d extension */
>  cpu->cfg.ext_zve64d = true;
>  }
>
> @@ -947,46 +994,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  cpu->cfg.ext_zksed = true;
>  cpu->cfg.ext_zksh = true;
>  }
> -
> -if (riscv_has_ext(env, RVV)) {
> -int vext_version = VEXT_VERSION_1_00_0;
> -if (!is_power_of_2(cpu->cfg.vlen)) {
> -error_setg(errp,
> -   "Vector extension VLEN must be power of 2");
> -return;
> -}
> -if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
> -error_setg(errp,
> -   "Vector extension implementation only supports VLEN "
> -   "in the range [128, %d]", RV_VLEN_MAX);
> -return;
> -}
> -if (!is_power_of_2(cpu->cfg.elen)) {
> -error_setg(errp,
> -   "Vector extension ELEN must be power of 2");
> -return;
> -}
> -if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
> -error_setg(errp,
> -   "Vector extension implementation only supports ELEN "
> -   "in the range [8, 64]");
> -return;
> -}
> -if (cpu->cfg.vext_spec) {
> -if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
> -vext_version = VEXT_VERSION_1_00_0;
> -} else {
> -error_setg(errp,
> -   "Unsupported vector spec version '%s'",
> -   cpu->cfg.vext_spec);
> -return;
> -}
> -} else {
> -qemu_log("vector version is not specified, "
> - "use the default value v1.0\n");
> -}
> -

Re: [PATCH v4] target/riscv: fix H extension TVM trap

[Alistair Francis]

On Sun, Mar 12, 2023 at 10:07 PM Yi Chen  wrote:
>
> - Trap satp/hgatp accesses from HS-mode when MSTATUS.TVM is enabled.
> - Trap satp accesses from VS-mode when HSTATUS.VTVM is enabled.
> - Raise RISCV_EXCP_ILLEGAL_INST when U-mode executes SFENCE.VMA/SINVAL.VMA.
> - Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes
>   SFENCE.VMA/SINVAL.VMA or VS-mode executes SFENCE.VMA/SINVAL.VMA with
>   HSTATUS.VTVM enabled.
> - Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes
>   HFENCE.GVMA/HFENCE.VVMA/HINVAL.GVMA/HINVAL.VVMA.

Thanks for the patch!

It looks like this patch needs to be rebased. Do you mind rebasing it
on https://github.com/alistair23/qemu/tree/riscv-to-apply.next and
then re-sending?

Also, when you are fixing a range of issues it's best to split the
fixes into patches that fix each individual issue (where that is
possible). This makes it easier to review but also makes it easier to
track changes and regressions if any problems arise.

In this case you don't need to split them up for a v5, but in future
it's something to keep in mind

The changes look good otherwise though :)

Alistair

>
> Signed-off-by: Yi Chen 
> Reviewed-by: Weiwei Li 
> ---
> Add reviewed-by
> Replace "env->priv <= PRV_S && riscv_cpu_virt_enabled(env)" with 
> "riscv_cpu_virt_enabled(env)"
>  target/riscv/csr.c   | 56 +---
>  target/riscv/op_helper.c | 12 -
>  2 files changed, 41 insertions(+), 27 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d522efc0b6..26a02e57bd 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -443,6 +443,30 @@ static RISCVException sstc_32(CPURISCVState *env, int 
> csrno)
>  return sstc(env, csrno);
>  }
>
> +static RISCVException satp(CPURISCVState *env, int csrno)
> +{
> +if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) &&
> +get_field(env->mstatus, MSTATUS_TVM)) {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +if (env->priv == PRV_S && riscv_cpu_virt_enabled(env) &&
> +get_field(env->hstatus, HSTATUS_VTVM)) {
> +return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> +}
> +
> +return smode(env, csrno);
> +}
> +
> +static RISCVException hgatp(CPURISCVState *env, int csrno)
> +{
> +if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) &&
> +get_field(env->mstatus, MSTATUS_TVM)) {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +
> +return hmode(env, csrno);
> +}
> +
>  /* Checks if PointerMasking registers could be accessed */
>  static RISCVException pointer_masking(CPURISCVState *env, int csrno)
>  {
> @@ -2655,13 +2679,7 @@ static RISCVException read_satp(CPURISCVState *env, 
> int csrno,
>  *val = 0;
>  return RISCV_EXCP_NONE;
>  }
> -
> -if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
> -return RISCV_EXCP_ILLEGAL_INST;
> -} else {
> -*val = env->satp;
> -}
> -
> +*val = env->satp;
>  return RISCV_EXCP_NONE;
>  }
>
> @@ -2684,18 +2702,14 @@ static RISCVException write_satp(CPURISCVState *env, 
> int csrno,
>  }
>
>  if (vm && mask) {
> -if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
> -return RISCV_EXCP_ILLEGAL_INST;
> -} else {
> -/*
> - * The ISA defines SATP.MODE=Bare as "no translation", but we 
> still
> - * pass these through QEMU's TLB emulation as it improves
> - * performance.  Flushing the TLB on SATP writes with paging
> - * enabled avoids leaking those invalid cached mappings.
> - */
> -tlb_flush(env_cpu(env));
> -env->satp = val;
> -}
> +/*
> + * The ISA defines SATP.MODE=Bare as "no translation", but we still
> + * pass these through QEMU's TLB emulation as it improves
> + * performance.  Flushing the TLB on SATP writes with paging
> + * enabled avoids leaking those invalid cached mappings.
> + */
> +tlb_flush(env_cpu(env));
> +env->satp = val;
>  }
>  return RISCV_EXCP_NONE;
>  }
> @@ -4180,7 +4194,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>   .min_priv_ver = PRIV_VERSION_1_12_0 },
>
>  /* Supervisor Protection and Translation */
> -[CSR_SATP] = { "satp", smode, read_satp, write_satp },
> +[CSR_SATP] = { "satp", satp, read_satp, write_satp },
>
>  /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
>  [CSR_SISELECT]   = { "siselect",   aia_smode, NULL, NULL, rmw_xiselect },
> @@ -4217,7 +4231,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>.min_priv_ver = PRIV_VERSION_1_12_0
> },
>  [CSR_HGEIP]   = { "hgeip",   hmode,   read_hgeip,
>.min_priv_ver = PRIV_VERSION_1_12_0
> },
> -

Re: [PATCH 1/2] target/riscv: Fix the mstatus.MPP value after executing MRET

[Alistair Francis]

On Thu, Apr 6, 2023 at 10:56 AM liweiwei  wrote:
>
>
> On 2023/4/6 08:43, Alistair Francis wrote:
>
> On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li  wrote:
>
> The MPP will be set to the least-privileged supported mode (U if
> U-mode is implemented, else M).
>
> I don't think this is right, the spec in section 8.6.4 says this:
>
> Sorry, I didn't find this section in latest release of both privilege and 
> un-privilege spec

I updated my spec, using commit
f6b8d5c7d2dcd935b48689a337c8f5bc2be4b5e5 it's now section 9.6.4 Trap
Return

>
> (draft-20230131-c0b298a: Clarify WFI trapping behavior (#972)).

Also, you replied with a HTML email which loses the conversation
history (just see above). Can you fixup your client to reply with
plain text please

Alistair

>
> "MRET then in mstatus/mstatush sets MPV=0, MPP=0,
> MIE=MPIE, and MPIE=1"
>
> In section 3.1.6.1, the privilege spec says this:
>
> "An MRET or SRET instruction is used to return from a trap in M-mode or 
> S-mode respectively.
> When executing an xRET instruction, supposing xPP holds the value y, xIE is 
> set to xPIE; the
> privilege mode is changed to y; xPIE is set to 1; and xPP is set to the 
> least-privileged supported
> mode (U if U-mode is implemented, else M). If y̸=M, xRET also sets MPRV=0"
>
> And I think PRV_U is an illegal value for MPP if U-mode is not implemented.
>
> Regards,
>
> Weiwei Li
>
> So it should just always be 0 (PRV_U is 0)
>
> Alistair
>
> Signed-off-by: Weiwei Li 
> Signed-off-by: Junqiang Wang 
> ---
>  target/riscv/op_helper.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 84ee018f7d..991f06d98d 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -339,7 +339,8 @@ target_ulong helper_mret(CPURISCVState *env)
>  mstatus = set_field(mstatus, MSTATUS_MIE,
>  get_field(mstatus, MSTATUS_MPIE));
>  mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
> -mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
> +mstatus = set_field(mstatus, MSTATUS_MPP,
> +riscv_has_ext(env, RVU) ? PRV_U : PRV_M);
>  mstatus = set_field(mstatus, MSTATUS_MPV, 0);
>  if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
>  mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
> --
> 2.25.1
>
>

Re: [PATCH 2/2] target/riscv: Legalize MPP value in write_mstatus

[liweiwei]

On 2023/4/6 09:26, Alistair Francis wrote:

On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li  wrote:

mstatus.MPP field is a WARL field, so we remain it unchanged if an

Only since version 1.11 of the priv spec and we do still support priv 1.10.

I think it's ok to make this change for all priv versions, as it won't
break any software running 1.10, but it's worth adding a comment or at
least a mention in the commit message.


OK. I'll add it in next version.

Regards,

Weiwei Li



Alistair


invalid value is written into it. And after this, RVH shouldn't be
passed to riscv_cpu_set_mode().

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
---
  target/riscv/cpu_helper.c |  5 +
  target/riscv/csr.c| 14 ++
  2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f88c503cf4..46baf3ab7c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -659,12 +659,9 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, 
uint32_t priv,

  void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
  {
-if (newpriv > PRV_M) {
+if (newpriv > PRV_M || newpriv == PRV_H) {
  g_assert_not_reached();
  }
-if (newpriv == PRV_H) {
-newpriv = PRV_U;
-}
  if (icount_enabled() && newpriv != env->priv) {
  riscv_itrigger_update_priv(env);
  }
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d522efc0b6..a99026c3e8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1238,6 +1238,18 @@ static bool validate_vm(CPURISCVState *env, target_ulong 
vm)
  return (vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map);
  }

+static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp,
+ target_ulong val)
+{
+target_ulong new_mpp = get_field(val, MSTATUS_MPP);
+bool mpp_invalid = (new_mpp == PRV_S && !riscv_has_ext(env, RVS)) ||
+   (new_mpp == PRV_U && !riscv_has_ext(env, RVU)) ||
+   (new_mpp == PRV_H);
+
+/* Remain field unchanged if new_mpp value is invalid */
+return mpp_invalid ? set_field(val, MSTATUS_MPP, old_mpp) : val;
+}
+
  static RISCVException write_mstatus(CPURISCVState *env, int csrno,
  target_ulong val)
  {
@@ -1245,6 +1257,8 @@ static RISCVException write_mstatus(CPURISCVState *env, 
int csrno,
  uint64_t mask = 0;
  RISCVMXL xl = riscv_cpu_mxl(env);

+val = legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val);
+
  /* flush tlb on mstatus fields that affect VM */
  if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
  MSTATUS_MPRV | MSTATUS_SUM)) {
--
2.25.1

Re: [PATCH v4 0/1] hw/riscv: Add ACT related support

[Alistair Francis]

On Wed, Apr 5, 2023 at 7:58 PM Weiwei Li  wrote:
>
> ACT tests play an important role in riscv tests. This patch tries to
> add related support to run ACT tests.
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-act-upstream-v2
>
> The ACT tests can be run on qemu-system-riscv32/64 with machine argument
> "-M spike,signature=,signature-granularity=".
>
> v4:
> * update error message for opening signature file failed
> * add check for existence of begin/end_signature symbols when trying to 
> update signature file.
>
> v3:
> * move definition of signature related parameters from spike.c to riscv_htif.c
>
> v2：
> * move "extern ..." declaration from riscv_htif.c to riscv_htif.h
>
> Weiwei Li (1):
>   hw/riscv: Add signature dump function for spike to run ACT tests

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  hw/char/riscv_htif.c | 44 +++-
>  hw/riscv/spike.c | 13 +++
>  include/hw/char/riscv_htif.h |  3 +++
>  3 files changed, 59 insertions(+), 1 deletion(-)
>
> --
> 2.25.1
>
>

Re: [PATCH v4 1/1] hw/riscv: Add signature dump function for spike to run ACT tests

[Alistair Francis]

On Thu, Apr 6, 2023 at 11:02 AM liweiwei  wrote:
>
>
> On 2023/4/6 08:36, Alistair Francis wrote:
> > On Wed, Apr 5, 2023 at 7:58 PM Weiwei Li  wrote:
> >> Add signature and signature-granularity properties in spike to specify the 
> >> target
> >> signatrue file and the line size for signature data.
> >>
> >> Recgonize the signature section between begin_signature and end_signature 
> >> symbols
> >> when loading elf of ACT tests. Then dump signature data in signature 
> >> section just
> >> before the ACT tests exit.
> >>
> >> Signed-off-by: Weiwei Li 
> >> Signed-off-by: Junqiang Wang 
> >> Reviewed-by: LIU Zhiwei 
> >> ---
> >>   hw/char/riscv_htif.c | 44 +++-
> >>   hw/riscv/spike.c | 13 +++
> >>   include/hw/char/riscv_htif.h |  3 +++
> >>   3 files changed, 59 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
> >> index 098de50e35..37d3ccc76b 100644
> >> --- a/hw/char/riscv_htif.c
> >> +++ b/hw/char/riscv_htif.c
> >> @@ -29,6 +29,8 @@
> >>   #include "chardev/char-fe.h"
> >>   #include "qemu/timer.h"
> >>   #include "qemu/error-report.h"
> >> +#include "exec/address-spaces.h"
> >> +#include "sysemu/dma.h"
> >>
> >>   #define RISCV_DEBUG_HTIF 0
> >>   #define HTIF_DEBUG(fmt, ...) 
> >>   \
> >> @@ -51,7 +53,10 @@
> >>   /* PK system call number */
> >>   #define PK_SYS_WRITE64
> >>
> >> -static uint64_t fromhost_addr, tohost_addr;
> >> +const char *sig_file;
> >> +uint8_t line_size = 16;
> >> +
> >> +static uint64_t fromhost_addr, tohost_addr, begin_sig_addr, end_sig_addr;
> >>
> >>   void htif_symbol_callback(const char *st_name, int st_info, uint64_t 
> >> st_value,
> >> uint64_t st_size)
> >> @@ -68,6 +73,10 @@ void htif_symbol_callback(const char *st_name, int 
> >> st_info, uint64_t st_value,
> >>   error_report("HTIF tohost must be 8 bytes");
> >>   exit(1);
> >>   }
> >> +} else if (strcmp("begin_signature", st_name) == 0) {
> >> +begin_sig_addr = st_value;
> >> +} else if (strcmp("end_signature", st_name) == 0) {
> >> +end_sig_addr = st_value;
> >>   }
> >>   }
> >>
> >> @@ -163,6 +172,39 @@ static void htif_handle_tohost_write(HTIFState *s, 
> >> uint64_t val_written)
> >>   if (payload & 0x1) {
> >>   /* exit code */
> >>   int exit_code = payload >> 1;
> >> +
> >> +/*
> >> + * Dump signature data if sig_file is specified and
> >> + * begin/end_signature symbols exist.
> >> + */
> >> +if (sig_file && begin_sig_addr && end_sig_addr) {
> > There is no guarantee that these are initalised to zero, so this isn't
> > really checking anything is it?
>
> I think the static global variable will be  initialized to zero by default.

Ah, yes you are right. static variables are initalised to zero as per
the C99 standard.

In which case:

Reviewed-by: Alistair Francis 

Alistair

>
> If not,  fromhost_addr and tohost_addr may have the same problem.
>
> Regards,
>
> Weiwei Li
>
> >

Re: [PATCH 2/2] target/riscv: Legalize MPP value in write_mstatus

[Alistair Francis]

On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li  wrote:
>
> mstatus.MPP field is a WARL field, so we remain it unchanged if an

Only since version 1.11 of the priv spec and we do still support priv 1.10.

I think it's ok to make this change for all priv versions, as it won't
break any software running 1.10, but it's worth adding a comment or at
least a mention in the commit message.

Alistair

> invalid value is written into it. And after this, RVH shouldn't be
> passed to riscv_cpu_set_mode().
>
> Signed-off-by: Weiwei Li 
> Signed-off-by: Junqiang Wang 
> ---
>  target/riscv/cpu_helper.c |  5 +
>  target/riscv/csr.c| 14 ++
>  2 files changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index f88c503cf4..46baf3ab7c 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -659,12 +659,9 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, 
> uint32_t priv,
>
>  void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
>  {
> -if (newpriv > PRV_M) {
> +if (newpriv > PRV_M || newpriv == PRV_H) {
>  g_assert_not_reached();
>  }
> -if (newpriv == PRV_H) {
> -newpriv = PRV_U;
> -}
>  if (icount_enabled() && newpriv != env->priv) {
>  riscv_itrigger_update_priv(env);
>  }
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d522efc0b6..a99026c3e8 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1238,6 +1238,18 @@ static bool validate_vm(CPURISCVState *env, 
> target_ulong vm)
>  return (vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map);
>  }
>
> +static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp,
> + target_ulong val)
> +{
> +target_ulong new_mpp = get_field(val, MSTATUS_MPP);
> +bool mpp_invalid = (new_mpp == PRV_S && !riscv_has_ext(env, RVS)) ||
> +   (new_mpp == PRV_U && !riscv_has_ext(env, RVU)) ||
> +   (new_mpp == PRV_H);
> +
> +/* Remain field unchanged if new_mpp value is invalid */
> +return mpp_invalid ? set_field(val, MSTATUS_MPP, old_mpp) : val;
> +}
> +
>  static RISCVException write_mstatus(CPURISCVState *env, int csrno,
>  target_ulong val)
>  {
> @@ -1245,6 +1257,8 @@ static RISCVException write_mstatus(CPURISCVState *env, 
> int csrno,
>  uint64_t mask = 0;
>  RISCVMXL xl = riscv_cpu_mxl(env);
>
> +val = legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val);
> +
>  /* flush tlb on mstatus fields that affect VM */
>  if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
>  MSTATUS_MPRV | MSTATUS_SUM)) {
> --
> 2.25.1
>
>

Re: [PATCH v4 1/1] hw/riscv: Add signature dump function for spike to run ACT tests

[liweiwei]

On 2023/4/6 08:36, Alistair Francis wrote:

On Wed, Apr 5, 2023 at 7:58 PM Weiwei Li  wrote:

Add signature and signature-granularity properties in spike to specify the 
target
signatrue file and the line size for signature data.

Recgonize the signature section between begin_signature and end_signature 
symbols
when loading elf of ACT tests. Then dump signature data in signature section 
just
before the ACT tests exit.

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
Reviewed-by: LIU Zhiwei 
---
  hw/char/riscv_htif.c | 44 +++-
  hw/riscv/spike.c | 13 +++
  include/hw/char/riscv_htif.h |  3 +++
  3 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index 098de50e35..37d3ccc76b 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -29,6 +29,8 @@
  #include "chardev/char-fe.h"
  #include "qemu/timer.h"
  #include "qemu/error-report.h"
+#include "exec/address-spaces.h"
+#include "sysemu/dma.h"

  #define RISCV_DEBUG_HTIF 0
  #define HTIF_DEBUG(fmt, ...)  
 \
@@ -51,7 +53,10 @@
  /* PK system call number */
  #define PK_SYS_WRITE64

-static uint64_t fromhost_addr, tohost_addr;
+const char *sig_file;
+uint8_t line_size = 16;
+
+static uint64_t fromhost_addr, tohost_addr, begin_sig_addr, end_sig_addr;

  void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
uint64_t st_size)
@@ -68,6 +73,10 @@ void htif_symbol_callback(const char *st_name, int st_info, 
uint64_t st_value,
  error_report("HTIF tohost must be 8 bytes");
  exit(1);
  }
+} else if (strcmp("begin_signature", st_name) == 0) {
+begin_sig_addr = st_value;
+} else if (strcmp("end_signature", st_name) == 0) {
+end_sig_addr = st_value;
  }
  }

@@ -163,6 +172,39 @@ static void htif_handle_tohost_write(HTIFState *s, 
uint64_t val_written)
  if (payload & 0x1) {
  /* exit code */
  int exit_code = payload >> 1;
+
+/*
+ * Dump signature data if sig_file is specified and
+ * begin/end_signature symbols exist.
+ */
+if (sig_file && begin_sig_addr && end_sig_addr) {

There is no guarantee that these are initalised to zero, so this isn't
really checking anything is it?


I think the static global variable will be  initialized to zero by default.

If not,  fromhost_addr and tohost_addr may have the same problem.

Regards,

Weiwei Li



Alistair


+uint64_t sig_len = end_sig_addr - begin_sig_addr;
+char *sig_data = g_malloc(sig_len);
+dma_memory_read(_space_memory, begin_sig_addr,
+sig_data, sig_len, MEMTXATTRS_UNSPECIFIED);
+FILE *signature = fopen(sig_file, "w");
+if (signature == NULL) {
+error_report("Unable to open %s with error %s",
+ sig_file, strerror(errno));
+exit(1);
+}
+
+for (int i = 0; i < sig_len; i += line_size) {
+for (int j = line_size; j > 0; j--) {
+if (i + j <= sig_len) {
+fprintf(signature, "%02x",
+sig_data[i + j - 1] & 0xff);
+} else {
+fprintf(signature, "%02x", 0);
+}
+}
+fprintf(signature, "\n");
+}
+
+fclose(signature);
+g_free(sig_data);
+}
+
  exit(exit_code);
  } else {
  uint64_t syscall[8];
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index a584d5b3a2..2c5546560a 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -332,6 +332,11 @@ static void spike_board_init(MachineState *machine)
   htif_custom_base);
  }

+static void spike_set_signature(Object *obj, const char *val, Error **errp)
+{
+sig_file = g_strdup(val);
+}
+
  static void spike_machine_instance_init(Object *obj)
  {
  }
@@ -350,6 +355,14 @@ static void spike_machine_class_init(ObjectClass *oc, void 
*data)
  mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
  mc->numa_mem_supported = true;
  mc->default_ram_id = "riscv.spike.ram";
+object_class_property_add_str(oc, "signature", NULL, spike_set_signature);
+object_class_property_set_description(oc, "signature",
+  "File to write ACT test signature");
+object_class_property_add_uint8_ptr(oc, "signature-granularity",
+_size, 

Re: [PATCH 1/2] target/riscv: Fix the mstatus.MPP value after executing MRET

[liweiwei]

On 2023/4/6 08:43, Alistair Francis wrote:

On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li  wrote:

The MPP will be set to the least-privileged supported mode (U if
U-mode is implemented, else M).

I don't think this is right, the spec in section 8.6.4 says this:


Sorry, I didn't find this section in latest release of both privilege 
and un-privilege spec


(draft-20230131-c0b298a: Clarify WFI trapping behavior (#972)).



"MRET then in mstatus/mstatush sets MPV=0, MPP=0,
MIE=MPIE, and MPIE=1"


In section 3.1.6.1, the privilege spec says this:

"An MRET or SRET instruction is used to return from a trap in M-mode or 
S-mode respectively.
When executing anxRET instruction, supposingxPP holds the valuey,xIE is 
set toxPIE; the
privilege mode is changed toy;xPIE is set to 1; andxPP is set to the 
least-privileged supported

mode (U if U-mode is implemented, else M). Ify̸=M,xRET also sets MPRV=0"

And I think PRV_U is an illegal value for MPP if U-mode is not implemented.

Regards,

Weiwei Li


So it should just always be 0 (PRV_U is 0)

Alistair


Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
  target/riscv/op_helper.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 84ee018f7d..991f06d98d 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -339,7 +339,8 @@ target_ulong helper_mret(CPURISCVState *env)
  mstatus = set_field(mstatus, MSTATUS_MIE,
  get_field(mstatus, MSTATUS_MPIE));
  mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
-mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
+mstatus = set_field(mstatus, MSTATUS_MPP,
+riscv_has_ext(env, RVU) ? PRV_U : PRV_M);
  mstatus = set_field(mstatus, MSTATUS_MPV, 0);
  if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
  mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
--
2.25.1

Re: [PATCH 1/2] target/riscv: Fix the mstatus.MPP value after executing MRET

[Alistair Francis]

On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li  wrote:
>
> The MPP will be set to the least-privileged supported mode (U if
> U-mode is implemented, else M).

I don't think this is right, the spec in section 8.6.4 says this:

"MRET then in mstatus/mstatush sets MPV=0, MPP=0,
MIE=MPIE, and MPIE=1"

So it should just always be 0 (PRV_U is 0)

Alistair

>
> Signed-off-by: Weiwei Li 
> Signed-off-by: Junqiang Wang 
> ---
>  target/riscv/op_helper.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 84ee018f7d..991f06d98d 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -339,7 +339,8 @@ target_ulong helper_mret(CPURISCVState *env)
>  mstatus = set_field(mstatus, MSTATUS_MIE,
>  get_field(mstatus, MSTATUS_MPIE));
>  mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
> -mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
> +mstatus = set_field(mstatus, MSTATUS_MPP,
> +riscv_has_ext(env, RVU) ? PRV_U : PRV_M);
>  mstatus = set_field(mstatus, MSTATUS_MPV, 0);
>  if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
>  mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
> --
> 2.25.1
>
>

Re: [PATCH v4 1/1] hw/riscv: Add signature dump function for spike to run ACT tests

[Alistair Francis]

On Wed, Apr 5, 2023 at 7:58 PM Weiwei Li  wrote:
>
> Add signature and signature-granularity properties in spike to specify the 
> target
> signatrue file and the line size for signature data.
>
> Recgonize the signature section between begin_signature and end_signature 
> symbols
> when loading elf of ACT tests. Then dump signature data in signature section 
> just
> before the ACT tests exit.
>
> Signed-off-by: Weiwei Li 
> Signed-off-by: Junqiang Wang 
> Reviewed-by: LIU Zhiwei 
> ---
>  hw/char/riscv_htif.c | 44 +++-
>  hw/riscv/spike.c | 13 +++
>  include/hw/char/riscv_htif.h |  3 +++
>  3 files changed, 59 insertions(+), 1 deletion(-)
>
> diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
> index 098de50e35..37d3ccc76b 100644
> --- a/hw/char/riscv_htif.c
> +++ b/hw/char/riscv_htif.c
> @@ -29,6 +29,8 @@
>  #include "chardev/char-fe.h"
>  #include "qemu/timer.h"
>  #include "qemu/error-report.h"
> +#include "exec/address-spaces.h"
> +#include "sysemu/dma.h"
>
>  #define RISCV_DEBUG_HTIF 0
>  #define HTIF_DEBUG(fmt, ...) 
>   \
> @@ -51,7 +53,10 @@
>  /* PK system call number */
>  #define PK_SYS_WRITE64
>
> -static uint64_t fromhost_addr, tohost_addr;
> +const char *sig_file;
> +uint8_t line_size = 16;
> +
> +static uint64_t fromhost_addr, tohost_addr, begin_sig_addr, end_sig_addr;
>
>  void htif_symbol_callback(const char *st_name, int st_info, uint64_t 
> st_value,
>uint64_t st_size)
> @@ -68,6 +73,10 @@ void htif_symbol_callback(const char *st_name, int 
> st_info, uint64_t st_value,
>  error_report("HTIF tohost must be 8 bytes");
>  exit(1);
>  }
> +} else if (strcmp("begin_signature", st_name) == 0) {
> +begin_sig_addr = st_value;
> +} else if (strcmp("end_signature", st_name) == 0) {
> +end_sig_addr = st_value;
>  }
>  }
>
> @@ -163,6 +172,39 @@ static void htif_handle_tohost_write(HTIFState *s, 
> uint64_t val_written)
>  if (payload & 0x1) {
>  /* exit code */
>  int exit_code = payload >> 1;
> +
> +/*
> + * Dump signature data if sig_file is specified and
> + * begin/end_signature symbols exist.
> + */
> +if (sig_file && begin_sig_addr && end_sig_addr) {

There is no guarantee that these are initalised to zero, so this isn't
really checking anything is it?

Alistair

> +uint64_t sig_len = end_sig_addr - begin_sig_addr;
> +char *sig_data = g_malloc(sig_len);
> +dma_memory_read(_space_memory, begin_sig_addr,
> +sig_data, sig_len, 
> MEMTXATTRS_UNSPECIFIED);
> +FILE *signature = fopen(sig_file, "w");
> +if (signature == NULL) {
> +error_report("Unable to open %s with error %s",
> + sig_file, strerror(errno));
> +exit(1);
> +}
> +
> +for (int i = 0; i < sig_len; i += line_size) {
> +for (int j = line_size; j > 0; j--) {
> +if (i + j <= sig_len) {
> +fprintf(signature, "%02x",
> +sig_data[i + j - 1] & 0xff);
> +} else {
> +fprintf(signature, "%02x", 0);
> +}
> +}
> +fprintf(signature, "\n");
> +}
> +
> +fclose(signature);
> +g_free(sig_data);
> +}
> +
>  exit(exit_code);
>  } else {
>  uint64_t syscall[8];
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index a584d5b3a2..2c5546560a 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -332,6 +332,11 @@ static void spike_board_init(MachineState *machine)
>   htif_custom_base);
>  }
>
> +static void spike_set_signature(Object *obj, const char *val, Error **errp)
> +{
> +sig_file = g_strdup(val);
> +}
> +
>  static void spike_machine_instance_init(Object *obj)
>  {
>  }
> @@ -350,6 +355,14 @@ static void spike_machine_class_init(ObjectClass *oc, 
> void *data)
>  mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
>  mc->numa_mem_supported = true;
>  mc->default_ram_id = "riscv.spike.ram";
> +object_class_property_add_str(oc, "signature", NULL, 
> spike_set_signature);
> +object_class_property_set_description(oc, "signature",
> +  "File to write ACT test 
> signature");
> +object_class_property_add_uint8_ptr(oc, "signature-granularity",
> +

Re: [PATCH v3 00/20] remove MISA ext_N flags from cpu->cfg,

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
 wrote:
>
> Hi,
>
> This new version has a new patch (3) that removes the 'multi_letter'
> attribute from isa_ext_data that became redundant after the changes made
> in patch 2. The change was proposed by Weiwei Li in the v2.
>
> All patches but patch 3 are acked.
>
> Changes from v2:
> - patch 3 (new)
>   - remove 'multi_letter' from isa_ext_data
> - v2 link: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg06493.html
>
> Daniel Henrique Barboza (20):
>   target/riscv: sync env->misa_ext* with cpu->cfg in realize()
>   target/riscv: remove MISA properties from isa_edata_arr[]
>   target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data
>   target/riscv: introduce riscv_cpu_add_misa_properties()
>   target/riscv: remove cpu->cfg.ext_a
>   target/riscv: remove cpu->cfg.ext_c
>   target/riscv: remove cpu->cfg.ext_d
>   target/riscv: remove cpu->cfg.ext_f
>   target/riscv: remove cpu->cfg.ext_i
>   target/riscv: remove cpu->cfg.ext_e
>   target/riscv: remove cpu->cfg.ext_m
>   target/riscv: remove cpu->cfg.ext_s
>   target/riscv: remove cpu->cfg.ext_u
>   target/riscv: remove cpu->cfg.ext_h
>   target/riscv: remove cpu->cfg.ext_j
>   target/riscv: remove cpu->cfg.ext_v
>   target/riscv: remove riscv_cpu_sync_misa_cfg()
>   target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
>   target/riscv: add RVG and remove cpu->cfg.ext_g
>   target/riscv/cpu.c: redesign register_cpu_props()

Thanks for the cleanup. Do you mind rebasing it on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next then I
will apply it

Alistair

>
>  target/riscv/cpu.c | 386 +++--
>  target/riscv/cpu.h |  19 +--
>  2 files changed, 202 insertions(+), 203 deletions(-)
>
> --
> 2.39.2
>
>

Re: [PATCH v3 20/20] target/riscv/cpu.c: redesign register_cpu_props()

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:32 AM Daniel Henrique Barboza
 wrote:
>
> The function is now a no-op for all cpu_init() callers that are setting
> a non-zero misa value in set_misa(), since it's no longer used to sync
> cpu->cfg props with env->misa_ext bits. Remove it in those cases.
>
> While we're at it, rename the function to match what it's actually
> doing: create user properties to set/remove CPU extensions. Make a note
> that it will overwrite env->misa_ext with the defaults set by each user
> property.
>
> Update the MISA bits comment in cpu.h as well.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 41 ++---
>  target/riscv/cpu.h |  5 +
>  2 files changed, 11 insertions(+), 35 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6988ff443a..d8568a024c 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -221,7 +221,7 @@ static const char * const riscv_intr_names[] = {
>  "reserved"
>  };
>
> -static void register_cpu_props(Object *obj);
> +static void riscv_cpu_add_user_properties(Object *obj);
>
>  const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
>  {
> @@ -349,7 +349,6 @@ static void riscv_any_cpu_init(Object *obj)
>  #endif
>
>  set_priv_version(env, PRIV_VERSION_1_12_0);
> -register_cpu_props(obj);
>  }
>
>  #if defined(TARGET_RISCV64)
> @@ -358,7 +357,7 @@ static void rv64_base_cpu_init(Object *obj)
>  CPURISCVState *env = _CPU(obj)->env;
>  /* We set this in the realise function */
>  set_misa(env, MXL_RV64, 0);
> -register_cpu_props(obj);
> +riscv_cpu_add_user_properties(obj);
>  /* Set latest version of privileged specification */
>  set_priv_version(env, PRIV_VERSION_1_12_0);
>  #ifndef CONFIG_USER_ONLY
> @@ -370,7 +369,6 @@ static void rv64_sifive_u_cpu_init(Object *obj)
>  {
>  CPURISCVState *env = _CPU(obj)->env;
>  set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> -register_cpu_props(obj);
>  set_priv_version(env, PRIV_VERSION_1_10_0);
>  #ifndef CONFIG_USER_ONLY
>  set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
> @@ -383,7 +381,6 @@ static void rv64_sifive_e_cpu_init(Object *obj)
>  RISCVCPU *cpu = RISCV_CPU(obj);
>
>  set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
> -register_cpu_props(obj);
>  set_priv_version(env, PRIV_VERSION_1_10_0);
>  cpu->cfg.mmu = false;
>  #ifndef CONFIG_USER_ONLY
> @@ -429,7 +426,7 @@ static void rv128_base_cpu_init(Object *obj)
>  CPURISCVState *env = _CPU(obj)->env;
>  /* We set this in the realise function */
>  set_misa(env, MXL_RV128, 0);
> -register_cpu_props(obj);
> +riscv_cpu_add_user_properties(obj);
>  /* Set latest version of privileged specification */
>  set_priv_version(env, PRIV_VERSION_1_12_0);
>  #ifndef CONFIG_USER_ONLY
> @@ -442,7 +439,7 @@ static void rv32_base_cpu_init(Object *obj)
>  CPURISCVState *env = _CPU(obj)->env;
>  /* We set this in the realise function */
>  set_misa(env, MXL_RV32, 0);
> -register_cpu_props(obj);
> +riscv_cpu_add_user_properties(obj);
>  /* Set latest version of privileged specification */
>  set_priv_version(env, PRIV_VERSION_1_12_0);
>  #ifndef CONFIG_USER_ONLY
> @@ -454,7 +451,6 @@ static void rv32_sifive_u_cpu_init(Object *obj)
>  {
>  CPURISCVState *env = _CPU(obj)->env;
>  set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> -register_cpu_props(obj);
>  set_priv_version(env, PRIV_VERSION_1_10_0);
>  #ifndef CONFIG_USER_ONLY
>  set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
> @@ -467,7 +463,6 @@ static void rv32_sifive_e_cpu_init(Object *obj)
>  RISCVCPU *cpu = RISCV_CPU(obj);
>
>  set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
> -register_cpu_props(obj);
>  set_priv_version(env, PRIV_VERSION_1_10_0);
>  cpu->cfg.mmu = false;
>  #ifndef CONFIG_USER_ONLY
> @@ -481,7 +476,6 @@ static void rv32_ibex_cpu_init(Object *obj)
>  RISCVCPU *cpu = RISCV_CPU(obj);
>
>  set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
> -register_cpu_props(obj);
>  set_priv_version(env, PRIV_VERSION_1_11_0);
>  cpu->cfg.mmu = false;
>  #ifndef CONFIG_USER_ONLY
> @@ -496,7 +490,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
>  RISCVCPU *cpu = RISCV_CPU(obj);
>
>  set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
> -register_cpu_props(obj);
>  set_priv_version(env, PRIV_VERSION_1_10_0);
>  cpu->cfg.mmu = false;
>  #ifndef CONFIG_USER_ONLY
> @@ -514,7 +507,7 @@ static void riscv_host_cpu_init(Object *obj)
>  #elif defined(TARGET_RISCV64)
>  set_misa(env, MXL_RV64, 0);
>  #endif
> -register_cpu_props(obj);
> +riscv_cpu_add_user_properties(obj);
>  }
>  #endif
>
> @@ -1508,30 +1501,16 @@ static Property riscv_cpu_extensions[] = {

[PATCH 0/2] hw/arm/npcm7xx_gpio: Add some pin state QOM

[Joe Komlodi]

Hi all,

This series adds a couple QOM properties for retrieving and setting pin
state via qom-get and qom-get.

We ran into a situation in multi-SoC simulation where the BMC would need
to update its input pin state based on behavior from the other SoC. It
made the most sense to expose this over QMP, so this adds properties to
allow people to do so.

Since the NPCM7xx is typically used to help manage other SoCs, hopefully
other people will find this useful as well.

Thanks!
Joe

Joe Komlodi (2):
  hw/gpio/npcm7xx: Add GPIO DIN object property
  hw/gpio/npcm7xx: Support qom-get on GPIO pin level

 hw/gpio/npcm7xx_gpio.c | 31 +++
 1 file changed, 31 insertions(+)

-- 
2.40.0.348.gf938b09366-goog

[PATCH 1/2] hw/gpio/npcm7xx: Add GPIO DIN object property

[Joe Komlodi]

In cases where the input pin is driven by an entity outside of the
machine, such as a machine the BMC is managing, we need a way to
update the pin state when the external machine drives it.

This allows us to do it via QMP.
For example, to set pin 20 on GPIO controller 0:
{"execute":"qom-set","arguments": {
   "path":"/machine/soc/gpio[0]",
   "property":"gpio-pins-in",
   "value":1048576
}}

1048576 == 0x10, JSON does not support hex.

Signed-off-by: Joe Komlodi 
---
 hw/gpio/npcm7xx_gpio.c | 28 
 1 file changed, 28 insertions(+)

diff --git a/hw/gpio/npcm7xx_gpio.c b/hw/gpio/npcm7xx_gpio.c
index 3376901ab1..2a7be60d8d 100644
--- a/hw/gpio/npcm7xx_gpio.c
+++ b/hw/gpio/npcm7xx_gpio.c
@@ -20,6 +20,7 @@
 #include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
 #include "qapi/error.h"
+#include "qapi/visitor.h"
 #include "qemu/log.h"
 #include "qemu/module.h"
 #include "qemu/units.h"
@@ -340,6 +341,29 @@ static void npcm7xx_gpio_set_input(void *opaque, int line, 
int level)
 npcm7xx_gpio_update_pins(s, BIT(line));
 }
 
+static void npcm7xx_gpio_get_pins_in(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+uint32_t *pins_in = (uint32_t *)opaque;
+
+visit_type_uint32(v, name, pins_in, errp);
+}
+
+static void npcm7xx_gpio_set_pins_in(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
+uint32_t new_pins_in;
+
+if (!visit_type_uint32(v, name, _pins_in, errp)) {
+return;
+}
+
+s->ext_driven = new_pins_in;
+s->ext_level = new_pins_in;
+npcm7xx_gpio_update_pins(s, new_pins_in);
+}
+
 static void npcm7xx_gpio_enter_reset(Object *obj, ResetType type)
 {
 NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
@@ -371,6 +395,10 @@ static void npcm7xx_gpio_init(Object *obj)
 
 qdev_init_gpio_in(dev, npcm7xx_gpio_set_input, NPCM7XX_GPIO_NR_PINS);
 qdev_init_gpio_out(dev, s->output, NPCM7XX_GPIO_NR_PINS);
+
+object_property_add(obj, "gpio-pins-in", "uint32",
+npcm7xx_gpio_get_pins_in,  npcm7xx_gpio_set_pins_in,
+NULL, >regs[NPCM7XX_GPIO_DIN]);
 }
 
 static const VMStateDescription vmstate_npcm7xx_gpio = {
-- 
2.40.0.348.gf938b09366-goog

[PATCH 2/2] hw/gpio/npcm7xx: Support qom-get on GPIO pin level

[Joe Komlodi]

This goes along with input pin modification. In some cases it's easier
to know the state of all pins on the GPIO controller before modifying
input pins, rather than knowing only the state of input pins.

For example over QMP:
{"execute":"qom-get","arguments":{
"path":"/machine/soc/gpio[0]",
"property":"gpio-pin-level"
}}

Signed-off-by: Joe Komlodi 
---
 hw/gpio/npcm7xx_gpio.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/gpio/npcm7xx_gpio.c b/hw/gpio/npcm7xx_gpio.c
index 2a7be60d8d..58db3a8d64 100644
--- a/hw/gpio/npcm7xx_gpio.c
+++ b/hw/gpio/npcm7xx_gpio.c
@@ -399,6 +399,9 @@ static void npcm7xx_gpio_init(Object *obj)
 object_property_add(obj, "gpio-pins-in", "uint32",
 npcm7xx_gpio_get_pins_in,  npcm7xx_gpio_set_pins_in,
 NULL, >regs[NPCM7XX_GPIO_DIN]);
+
+object_property_add_uint32_ptr(obj, "gpio-pin-level", >pin_level,
+   OBJ_PROP_FLAG_READ);
 }
 
 static const VMStateDescription vmstate_npcm7xx_gpio = {
-- 
2.40.0.348.gf938b09366-goog

Re: [PATCH v3 19/20] target/riscv: add RVG and remove cpu->cfg.ext_g

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:33 AM Daniel Henrique Barboza
 wrote:
>
> We're still have one RISCVCPUConfig MISA flag, 'ext_g'. We'll remove it
> the same way we did with the others: create a "g" RISCVCPUMisaExtConfig
> property, remove the old "g" property, remove all instances of 'cfg.ext_g'
> and use riscv_has_ext(env, RVG).
>
> The caveat is that we don't have RVG, so add it. RVG will be used right
> off the bat in set_misa() of rv64_thead_c906_cpu_init() because the CPU is
> enabling G via the now removed 'ext_g' flag.
>
> After this patch, there are no more MISA extensions represented by flags
> in RISCVCPUConfig.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 17 -
>  target/riscv/cpu.h |  2 +-
>  2 files changed, 9 insertions(+), 10 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 036d6191ca..6988ff443a 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -396,10 +396,9 @@ static void rv64_thead_c906_cpu_init(Object *obj)
>  CPURISCVState *env = _CPU(obj)->env;
>  RISCVCPU *cpu = RISCV_CPU(obj);
>
> -set_misa(env, MXL_RV64, RVC | RVS | RVU);
> +set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
>  set_priv_version(env, PRIV_VERSION_1_11_0);
>
> -cpu->cfg.ext_g = true;
>  cpu->cfg.ext_zfh = true;
>  cpu->cfg.mmu = true;
>  cpu->cfg.ext_xtheadba = true;
> @@ -807,12 +806,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  CPURISCVState *env = >env;
>
>  /* Do some ISA extension error checking */
> -if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) &&
> -riscv_has_ext(env, RVM) &&
> -riscv_has_ext(env, RVA) &&
> -riscv_has_ext(env, RVF) &&
> -riscv_has_ext(env, RVD) &&
> -cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
> +if (riscv_has_ext(env, RVG) &&
> +!(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
> +  riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
> +  riscv_has_ext(env, RVD) &&
> +  cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
>  warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
>  cpu->cfg.ext_icsr = true;
>  cpu->cfg.ext_ifencei = true;
> @@ -1402,6 +1400,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>   .misa_bit = RVJ, .enabled = false},
>  {.name = "v", .description = "Vector operations",
>   .misa_bit = RVV, .enabled = false},
> +{.name = "g", .description = "General purpose (IMAFD_Zicsr_Zifencei)",
> + .misa_bit = RVG, .enabled = false},
>  };
>
>  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> @@ -1424,7 +1424,6 @@ static void riscv_cpu_add_misa_properties(Object 
> *cpu_obj)
>
>  static Property riscv_cpu_extensions[] = {
>  /* Defaults for standard extensions */
> -DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
>  DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
>  DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
>  DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index c0280ace2a..ce92e8393d 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -81,6 +81,7 @@
>  #define RVU RV('U')
>  #define RVH RV('H')
>  #define RVJ RV('J')
> +#define RVG RV('G')
>
>
>  /* Privileged specification version */
> @@ -418,7 +419,6 @@ typedef struct {
>  } RISCVSATPMap;
>
>  struct RISCVCPUConfig {
> -bool ext_g;
>  bool ext_zba;
>  bool ext_zbb;
>  bool ext_zbc;
> --
> 2.39.2
>
>

Re: [PATCH v3 18/20] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
 wrote:
>
> This CPU is enabling G via cfg.ext_g and, at the same time, setting
> IMAFD in set_misa() and cfg.ext_icsr.
>
> riscv_cpu_validate_set_extensions() is already doing that, so there's no
> need for cpu_init() setups to worry about setting G and its extensions.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 3eb3b7dc59..036d6191ca 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -396,11 +396,10 @@ static void rv64_thead_c906_cpu_init(Object *obj)
>  CPURISCVState *env = _CPU(obj)->env;
>  RISCVCPU *cpu = RISCV_CPU(obj);
>
> -set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> +set_misa(env, MXL_RV64, RVC | RVS | RVU);
>  set_priv_version(env, PRIV_VERSION_1_11_0);
>
>  cpu->cfg.ext_g = true;
> -cpu->cfg.ext_icsr = true;
>  cpu->cfg.ext_zfh = true;
>  cpu->cfg.mmu = true;
>  cpu->cfg.ext_xtheadba = true;
> --
> 2.39.2
>
>

Re: [PATCH v3 17/20] target/riscv: remove riscv_cpu_sync_misa_cfg()

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
 wrote:
>
> This function was created to move the sync between cpu->cfg.ext_N bit
> changes to env->misa_ext* from the validation step to an ealier step,
> giving us a guarantee that we could use either cpu->cfg.ext_N or
> riscv_has_ext(env,N) in the validation.
>
> We don't have any cpu->cfg.ext_N left that has an existing MISA bit
> (cfg.ext_g will be handled shortly). The function is now a no-op, simply
> copying the existing values of misa_ext* back to misa_ext*.
>
> Remove it.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 52 --
>  1 file changed, 52 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b40a55bc8d..3eb3b7dc59 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1081,50 +1081,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, 
> Error **errp)
>  #endif
>  }
>
> -static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
> -{
> -uint32_t ext = 0;
> -
> -if (riscv_has_ext(env, RVI)) {
> -ext |= RVI;
> -}
> -if (riscv_has_ext(env, RVE)) {
> -ext |= RVE;
> -}
> -if (riscv_has_ext(env, RVM)) {
> -ext |= RVM;
> -}
> -if (riscv_has_ext(env, RVA)) {
> -ext |= RVA;
> -}
> -if (riscv_has_ext(env, RVF)) {
> -ext |= RVF;
> -}
> -if (riscv_has_ext(env, RVD)) {
> -ext |= RVD;
> -}
> -if (riscv_has_ext(env, RVC)) {
> -ext |= RVC;
> -}
> -if (riscv_has_ext(env, RVS)) {
> -ext |= RVS;
> -}
> -if (riscv_has_ext(env, RVU)) {
> -ext |= RVU;
> -}
> -if (riscv_has_ext(env, RVH)) {
> -ext |= RVH;
> -}
> -if (riscv_has_ext(env, RVV)) {
> -ext |= RVV;
> -}
> -if (riscv_has_ext(env, RVJ)) {
> -ext |= RVJ;
> -}
> -
> -env->misa_ext = env->misa_ext_mask = ext;
> -}
> -
>  static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
>  {
>  if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
> @@ -1168,14 +1124,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>  set_priv_version(env, priv_version);
>  }
>
> -/*
> - * We can't be sure of whether we set defaults during cpu_init()
> - * or whether the user enabled/disabled some bits via cpu->cfg
> - * flags. Sync env->misa_ext with cpu->cfg now to allow us to
> - * use just env->misa_ext later.
> - */
> -riscv_cpu_sync_misa_cfg(env);
> -
>  riscv_cpu_validate_misa_priv(env, _err);
>  if (local_err != NULL) {
>  error_propagate(errp, local_err);
> --
> 2.39.2
>
>

Re: [PATCH v3 16/20] target/riscv: remove cpu->cfg.ext_v

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:33 AM Daniel Henrique Barboza
 wrote:
>
> Create a new "v" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are
> replaced with riscv_has_ext(env, RVV).
>
> Remove the old "v" property and 'ext_v' from RISCVCPUConfig.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 12 +---
>  target/riscv/cpu.h |  1 -
>  2 files changed, 5 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 86edc08545..b40a55bc8d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -876,7 +876,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  }
>
>  /* The V vector extension depends on the Zve64d extension */
> -if (cpu->cfg.ext_v) {
> +if (riscv_has_ext(env, RVV)) {
>  cpu->cfg.ext_zve64d = true;
>  }
>
> @@ -958,7 +958,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  cpu->cfg.ext_zksh = true;
>  }
>
> -if (cpu->cfg.ext_v) {
> +if (riscv_has_ext(env, RVV)) {
>  int vext_version = VEXT_VERSION_1_00_0;
>  if (!is_power_of_2(cpu->cfg.vlen)) {
>  error_setg(errp,
> @@ -1115,7 +1115,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
>  if (riscv_has_ext(env, RVH)) {
>  ext |= RVH;
>  }
> -if (riscv_cpu_cfg(env)->ext_v) {
> +if (riscv_has_ext(env, RVV)) {
>  ext |= RVV;
>  }
>  if (riscv_has_ext(env, RVJ)) {
> @@ -1453,6 +1453,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>   .misa_bit = RVH, .enabled = true},
>  {.name = "x-j", .description = "Dynamic translated languages",
>   .misa_bit = RVJ, .enabled = false},
> +{.name = "v", .description = "Vector operations",
> + .misa_bit = RVV, .enabled = false},
>  };
>
>  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> @@ -1476,7 +1478,6 @@ static void riscv_cpu_add_misa_properties(Object 
> *cpu_obj)
>  static Property riscv_cpu_extensions[] = {
>  /* Defaults for standard extensions */
>  DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
> -DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
>  DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
>  DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
>  DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> @@ -1569,7 +1570,6 @@ static Property riscv_cpu_extensions[] = {
>  static void register_cpu_props(Object *obj)
>  {
>  RISCVCPU *cpu = RISCV_CPU(obj);
> -uint32_t misa_ext = cpu->env.misa_ext;
>  Property *prop;
>  DeviceState *dev = DEVICE(obj);
>
> @@ -1579,8 +1579,6 @@ static void register_cpu_props(Object *obj)
>   * later on.
>   */
>  if (cpu->env.misa_ext != 0) {
> -cpu->cfg.ext_v = misa_ext & RVV;
> -
>  /*
>   * We don't want to set the default riscv_cpu_extensions
>   * in this case.
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 43a40ba950..c0280ace2a 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -419,7 +419,6 @@ typedef struct {
>
>  struct RISCVCPUConfig {
>  bool ext_g;
> -bool ext_v;
>  bool ext_zba;
>  bool ext_zbb;
>  bool ext_zbc;
> --
> 2.39.2
>
>

Re: [PATCH v3 15/20] target/riscv: remove cpu->cfg.ext_j

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
 wrote:
>
> Create a new "j" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are
> replaced with riscv_has_ext(env, RVJ).
>
> Remove the old "j" property and 'ext_j' from RISCVCPUConfig.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 6 +++---
>  target/riscv/cpu.h | 1 -
>  2 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 76dcf26f6c..86edc08545 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1118,7 +1118,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
>  if (riscv_cpu_cfg(env)->ext_v) {
>  ext |= RVV;
>  }
> -if (riscv_cpu_cfg(env)->ext_j) {
> +if (riscv_has_ext(env, RVJ)) {
>  ext |= RVJ;
>  }
>
> @@ -1451,6 +1451,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>   .misa_bit = RVU, .enabled = true},
>  {.name = "h", .description = "Hypervisor",
>   .misa_bit = RVH, .enabled = true},
> +{.name = "x-j", .description = "Dynamic translated languages",
> + .misa_bit = RVJ, .enabled = false},
>  };
>
>  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> @@ -1547,7 +1549,6 @@ static Property riscv_cpu_extensions[] = {
>
>  /* These are experimental so mark with 'x-' */
>  DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
> -DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
>  /* ePMP 0.9.3 */
>  DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
>  DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
> @@ -1579,7 +1580,6 @@ static void register_cpu_props(Object *obj)
>   */
>  if (cpu->env.misa_ext != 0) {
>  cpu->cfg.ext_v = misa_ext & RVV;
> -cpu->cfg.ext_j = misa_ext & RVJ;
>
>  /*
>   * We don't want to set the default riscv_cpu_extensions
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index f3cb28443c..43a40ba950 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -419,7 +419,6 @@ typedef struct {
>
>  struct RISCVCPUConfig {
>  bool ext_g;
> -bool ext_j;
>  bool ext_v;
>  bool ext_zba;
>  bool ext_zbb;
> --
> 2.39.2
>
>

Re: [PATCH v3 14/20] target/riscv: remove cpu->cfg.ext_h

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
 wrote:
>
> Create a new "h" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVH. Instances of cpu->cfg.ext_h and similar are
> replaced with riscv_has_ext(env, RVH).
>
> Remove the old "h" property and 'ext_h' from RISCVCPUConfig.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 10 +-
>  target/riscv/cpu.h |  1 -
>  2 files changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a72bc651cf..76dcf26f6c 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -840,13 +840,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  return;
>  }
>
> -if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) {
> +if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
>  error_setg(errp,
> "H depends on an I base integer ISA with 32 x registers");
>  return;
>  }
>
> -if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) {
> +if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
>  error_setg(errp, "H extension implicitly requires S-mode");
>  return;
>  }
> @@ -1112,7 +1112,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
>  if (riscv_has_ext(env, RVU)) {
>  ext |= RVU;
>  }
> -if (riscv_cpu_cfg(env)->ext_h) {
> +if (riscv_has_ext(env, RVH)) {
>  ext |= RVH;
>  }
>  if (riscv_cpu_cfg(env)->ext_v) {
> @@ -1449,6 +1449,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>   .misa_bit = RVS, .enabled = true},
>  {.name = "u", .description = "User-level instructions",
>   .misa_bit = RVU, .enabled = true},
> +{.name = "h", .description = "Hypervisor",
> + .misa_bit = RVH, .enabled = true},
>  };
>
>  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> @@ -1473,7 +1475,6 @@ static Property riscv_cpu_extensions[] = {
>  /* Defaults for standard extensions */
>  DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
>  DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
> -DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
>  DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
>  DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
>  DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> @@ -1578,7 +1579,6 @@ static void register_cpu_props(Object *obj)
>   */
>  if (cpu->env.misa_ext != 0) {
>  cpu->cfg.ext_v = misa_ext & RVV;
> -cpu->cfg.ext_h = misa_ext & RVH;
>  cpu->cfg.ext_j = misa_ext & RVJ;
>
>  /*
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7b98cf4dd7..f3cb28443c 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -419,7 +419,6 @@ typedef struct {
>
>  struct RISCVCPUConfig {
>  bool ext_g;
> -bool ext_h;
>  bool ext_j;
>  bool ext_v;
>  bool ext_zba;
> --
> 2.39.2
>
>

Re: [PATCH v3 13/20] target/riscv: remove cpu->cfg.ext_u

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:32 AM Daniel Henrique Barboza
 wrote:
>
> Create a new "u" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVU. Instances of cpu->cfg.ext_u and similar are
> replaced with riscv_has_ext(env, RVU).
>
> Remove the old "u" property and 'ext_u' from RISCVCPUConfig.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 9 -
>  target/riscv/cpu.h | 1 -
>  2 files changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 59f6711f94..a72bc651cf 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -400,7 +400,6 @@ static void rv64_thead_c906_cpu_init(Object *obj)
>  set_priv_version(env, PRIV_VERSION_1_11_0);
>
>  cpu->cfg.ext_g = true;
> -cpu->cfg.ext_u = true;
>  cpu->cfg.ext_icsr = true;
>  cpu->cfg.ext_zfh = true;
>  cpu->cfg.mmu = true;
> @@ -835,7 +834,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  return;
>  }
>
> -if (riscv_has_ext(env, RVS) && !cpu->cfg.ext_u) {
> +if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
>  error_setg(errp,
> "Setting S extension without U extension is illegal");
>  return;
> @@ -1110,7 +1109,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
>  if (riscv_has_ext(env, RVS)) {
>  ext |= RVS;
>  }
> -if (riscv_cpu_cfg(env)->ext_u) {
> +if (riscv_has_ext(env, RVU)) {
>  ext |= RVU;
>  }
>  if (riscv_cpu_cfg(env)->ext_h) {
> @@ -1448,6 +1447,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>   .misa_bit = RVM, .enabled = true},
>  {.name = "s", .description = "Supervisor-level instructions",
>   .misa_bit = RVS, .enabled = true},
> +{.name = "u", .description = "User-level instructions",
> + .misa_bit = RVU, .enabled = true},
>  };
>
>  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> @@ -1471,7 +1472,6 @@ static void riscv_cpu_add_misa_properties(Object 
> *cpu_obj)
>  static Property riscv_cpu_extensions[] = {
>  /* Defaults for standard extensions */
>  DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
> -DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>  DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
>  DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
>  DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
> @@ -1578,7 +1578,6 @@ static void register_cpu_props(Object *obj)
>   */
>  if (cpu->env.misa_ext != 0) {
>  cpu->cfg.ext_v = misa_ext & RVV;
> -cpu->cfg.ext_u = misa_ext & RVU;
>  cpu->cfg.ext_h = misa_ext & RVH;
>  cpu->cfg.ext_j = misa_ext & RVJ;
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index fc35aa7509..7b98cf4dd7 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -419,7 +419,6 @@ typedef struct {
>
>  struct RISCVCPUConfig {
>  bool ext_g;
> -bool ext_u;
>  bool ext_h;
>  bool ext_j;
>  bool ext_v;
> --
> 2.39.2
>
>

Re: [PATCH v3 12/20] target/riscv: remove cpu->cfg.ext_s

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:32 AM Daniel Henrique Barboza
 wrote:
>
> Create a new "s" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVS. Instances of cpu->cfg.ext_s and similar are
> replaced with riscv_has_ext(env, RVS).
>
> Remove the old "s" property and 'ext_s' from RISCVCPUConfig.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 11 +--
>  target/riscv/cpu.h |  1 -
>  2 files changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6861446489..59f6711f94 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -401,7 +401,6 @@ static void rv64_thead_c906_cpu_init(Object *obj)
>
>  cpu->cfg.ext_g = true;
>  cpu->cfg.ext_u = true;
> -cpu->cfg.ext_s = true;
>  cpu->cfg.ext_icsr = true;
>  cpu->cfg.ext_zfh = true;
>  cpu->cfg.mmu = true;
> @@ -836,7 +835,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  return;
>  }
>
> -if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
> +if (riscv_has_ext(env, RVS) && !cpu->cfg.ext_u) {
>  error_setg(errp,
> "Setting S extension without U extension is illegal");
>  return;
> @@ -848,7 +847,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  return;
>  }
>
> -if (cpu->cfg.ext_h && !cpu->cfg.ext_s) {
> +if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) {
>  error_setg(errp, "H extension implicitly requires S-mode");
>  return;
>  }
> @@ -1108,7 +1107,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
>  if (riscv_has_ext(env, RVC)) {
>  ext |= RVC;
>  }
> -if (riscv_cpu_cfg(env)->ext_s) {
> +if (riscv_has_ext(env, RVS)) {
>  ext |= RVS;
>  }
>  if (riscv_cpu_cfg(env)->ext_u) {
> @@ -1447,6 +1446,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>   .misa_bit = RVE, .enabled = false},
>  {.name = "m", .description = "Integer multiplication and division",
>   .misa_bit = RVM, .enabled = true},
> +{.name = "s", .description = "Supervisor-level instructions",
> + .misa_bit = RVS, .enabled = true},
>  };
>
>  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> @@ -1470,7 +1471,6 @@ static void riscv_cpu_add_misa_properties(Object 
> *cpu_obj)
>  static Property riscv_cpu_extensions[] = {
>  /* Defaults for standard extensions */
>  DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
> -DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
>  DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>  DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
>  DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
> @@ -1578,7 +1578,6 @@ static void register_cpu_props(Object *obj)
>   */
>  if (cpu->env.misa_ext != 0) {
>  cpu->cfg.ext_v = misa_ext & RVV;
> -cpu->cfg.ext_s = misa_ext & RVS;
>  cpu->cfg.ext_u = misa_ext & RVU;
>  cpu->cfg.ext_h = misa_ext & RVH;
>  cpu->cfg.ext_j = misa_ext & RVJ;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7a42c80b7d..fc35aa7509 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -419,7 +419,6 @@ typedef struct {
>
>  struct RISCVCPUConfig {
>  bool ext_g;
> -bool ext_s;
>  bool ext_u;
>  bool ext_h;
>  bool ext_j;
> --
> 2.39.2
>
>

Re: [PATCH v3 11/20] target/riscv: remove cpu->cfg.ext_m

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:33 AM Daniel Henrique Barboza
 wrote:
>
> Create a new "m" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are
> replaced with riscv_has_ext(env, RVM).
>
> Remove the old "m" property and 'ext_m' from RISCVCPUConfig.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 10 +-
>  target/riscv/cpu.h |  1 -
>  2 files changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9cf3ab3988..6861446489 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -810,13 +810,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  CPURISCVState *env = >env;
>
>  /* Do some ISA extension error checking */
> -if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m &&
> +if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) &&
> +riscv_has_ext(env, RVM) &&
>  riscv_has_ext(env, RVA) &&
>  riscv_has_ext(env, RVF) &&
>  riscv_has_ext(env, RVD) &&
>  cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
>  warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
> -cpu->cfg.ext_m = true;
>  cpu->cfg.ext_icsr = true;
>  cpu->cfg.ext_ifencei = true;
>
> @@ -1093,7 +1093,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
>  if (riscv_has_ext(env, RVE)) {
>  ext |= RVE;
>  }
> -if (riscv_cpu_cfg(env)->ext_m) {
> +if (riscv_has_ext(env, RVM)) {
>  ext |= RVM;
>  }
>  if (riscv_has_ext(env, RVA)) {
> @@ -1445,6 +1445,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>   .misa_bit = RVI, .enabled = true},
>  {.name = "e", .description = "Base integer instruction set (embedded)",
>   .misa_bit = RVE, .enabled = false},
> +{.name = "m", .description = "Integer multiplication and division",
> + .misa_bit = RVM, .enabled = true},
>  };
>
>  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> @@ -1468,7 +1470,6 @@ static void riscv_cpu_add_misa_properties(Object 
> *cpu_obj)
>  static Property riscv_cpu_extensions[] = {
>  /* Defaults for standard extensions */
>  DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
> -DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
>  DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
>  DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>  DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
> @@ -1576,7 +1577,6 @@ static void register_cpu_props(Object *obj)
>   * later on.
>   */
>  if (cpu->env.misa_ext != 0) {
> -cpu->cfg.ext_m = misa_ext & RVM;
>  cpu->cfg.ext_v = misa_ext & RVV;
>  cpu->cfg.ext_s = misa_ext & RVS;
>  cpu->cfg.ext_u = misa_ext & RVU;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index cc0b9e73ac..7a42c80b7d 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -419,7 +419,6 @@ typedef struct {
>
>  struct RISCVCPUConfig {
>  bool ext_g;
> -bool ext_m;
>  bool ext_s;
>  bool ext_u;
>  bool ext_h;
> --
> 2.39.2
>
>

Re: [PATCH v3 10/20] target/riscv: remove cpu->cfg.ext_e

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:33 AM Daniel Henrique Barboza
 wrote:
>
> Create a new "e" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVE. Instances of cpu->cfg.ext_e and similar are
> replaced with riscv_has_ext(env, RVE).
>
> Remove the old "e" property and 'ext_e' from RISCVCPUConfig.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 10 +-
>  target/riscv/cpu.h |  1 -
>  2 files changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 2156cb380e..9cf3ab3988 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -824,13 +824,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  env->misa_ext_mask = env->misa_ext;
>  }
>
> -if (riscv_has_ext(env, RVI) && cpu->cfg.ext_e) {
> +if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
>  error_setg(errp,
> "I and E extensions are incompatible");
>  return;
>  }
>
> -if (!riscv_has_ext(env, RVI) && !cpu->cfg.ext_e) {
> +if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
>  error_setg(errp,
> "Either I or E extension must be set");
>  return;
> @@ -1090,7 +1090,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
>  if (riscv_has_ext(env, RVI)) {
>  ext |= RVI;
>  }
> -if (riscv_cpu_cfg(env)->ext_e) {
> +if (riscv_has_ext(env, RVE)) {
>  ext |= RVE;
>  }
>  if (riscv_cpu_cfg(env)->ext_m) {
> @@ -1443,6 +1443,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>   .misa_bit = RVF, .enabled = true},
>  {.name = "i", .description = "Base integer instruction set",
>   .misa_bit = RVI, .enabled = true},
> +{.name = "e", .description = "Base integer instruction set (embedded)",
> + .misa_bit = RVE, .enabled = false},
>  };
>
>  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> @@ -1465,7 +1467,6 @@ static void riscv_cpu_add_misa_properties(Object 
> *cpu_obj)
>
>  static Property riscv_cpu_extensions[] = {
>  /* Defaults for standard extensions */
> -DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
>  DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
>  DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
>  DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
> @@ -1575,7 +1576,6 @@ static void register_cpu_props(Object *obj)
>   * later on.
>   */
>  if (cpu->env.misa_ext != 0) {
> -cpu->cfg.ext_e = misa_ext & RVE;
>  cpu->cfg.ext_m = misa_ext & RVM;
>  cpu->cfg.ext_v = misa_ext & RVV;
>  cpu->cfg.ext_s = misa_ext & RVS;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 573bf85ff1..cc0b9e73ac 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -418,7 +418,6 @@ typedef struct {
>  } RISCVSATPMap;
>
>  struct RISCVCPUConfig {
> -bool ext_e;
>  bool ext_g;
>  bool ext_m;
>  bool ext_s;
> --
> 2.39.2
>
>

Re: [PATCH v3 09/20] target/riscv: remove cpu->cfg.ext_i

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
 wrote:
>
> Create a new "i" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVI. Instances of cpu->cfg.ext_i and similar are
> replaced with riscv_has_ext(env, RVI).
>
> Remove the old "i" property and 'ext_i' from RISCVCPUConfig.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 15 +++
>  target/riscv/cpu.h |  1 -
>  2 files changed, 7 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index f53400d40f..2156cb380e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -810,13 +810,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  CPURISCVState *env = >env;
>
>  /* Do some ISA extension error checking */
> -if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
> +if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m &&
>  riscv_has_ext(env, RVA) &&
>  riscv_has_ext(env, RVF) &&
>  riscv_has_ext(env, RVD) &&
>  cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
>  warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
> -cpu->cfg.ext_i = true;
>  cpu->cfg.ext_m = true;
>  cpu->cfg.ext_icsr = true;
>  cpu->cfg.ext_ifencei = true;
> @@ -825,13 +824,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  env->misa_ext_mask = env->misa_ext;
>  }
>
> -if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
> +if (riscv_has_ext(env, RVI) && cpu->cfg.ext_e) {
>  error_setg(errp,
> "I and E extensions are incompatible");
>  return;
>  }
>
> -if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
> +if (!riscv_has_ext(env, RVI) && !cpu->cfg.ext_e) {
>  error_setg(errp,
> "Either I or E extension must be set");
>  return;
> @@ -843,7 +842,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  return;
>  }
>
> -if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
> +if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) {
>  error_setg(errp,
> "H depends on an I base integer ISA with 32 x registers");
>  return;
> @@ -1088,7 +1087,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
>  {
>  uint32_t ext = 0;
>
> -if (riscv_cpu_cfg(env)->ext_i) {
> +if (riscv_has_ext(env, RVI)) {
>  ext |= RVI;
>  }
>  if (riscv_cpu_cfg(env)->ext_e) {
> @@ -1442,6 +1441,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>   .misa_bit = RVD, .enabled = true},
>  {.name = "f", .description = "Single-precision float point",
>   .misa_bit = RVF, .enabled = true},
> +{.name = "i", .description = "Base integer instruction set",
> + .misa_bit = RVI, .enabled = true},
>  };
>
>  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> @@ -1464,7 +1465,6 @@ static void riscv_cpu_add_misa_properties(Object 
> *cpu_obj)
>
>  static Property riscv_cpu_extensions[] = {
>  /* Defaults for standard extensions */
> -DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
>  DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
>  DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
>  DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
> @@ -1575,7 +1575,6 @@ static void register_cpu_props(Object *obj)
>   * later on.
>   */
>  if (cpu->env.misa_ext != 0) {
> -cpu->cfg.ext_i = misa_ext & RVI;
>  cpu->cfg.ext_e = misa_ext & RVE;
>  cpu->cfg.ext_m = misa_ext & RVM;
>  cpu->cfg.ext_v = misa_ext & RVV;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index ce23b1c431..573bf85ff1 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -418,7 +418,6 @@ typedef struct {
>  } RISCVSATPMap;
>
>  struct RISCVCPUConfig {
> -bool ext_i;
>  bool ext_e;
>  bool ext_g;
>  bool ext_m;
> --
> 2.39.2
>
>

Re: [PATCH v3 08/20] target/riscv: remove cpu->cfg.ext_f

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:30 AM Daniel Henrique Barboza
 wrote:
>
> Create a new "f" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVF. Instances of cpu->cfg.ext_f and similar are
> replaced with riscv_has_ext(env, RVF).
>
> Remove the old "f" property and 'ext_f' from RISCVCPUConfig.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 20 ++--
>  target/riscv/cpu.h |  1 -
>  2 files changed, 10 insertions(+), 11 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9bb714d0d8..f53400d40f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -812,12 +812,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  /* Do some ISA extension error checking */
>  if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
>  riscv_has_ext(env, RVA) &&
> -cpu->cfg.ext_f && riscv_has_ext(env, RVD) &&
> +riscv_has_ext(env, RVF) &&
> +riscv_has_ext(env, RVD) &&
>  cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
>  warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
>  cpu->cfg.ext_i = true;
>  cpu->cfg.ext_m = true;
> -cpu->cfg.ext_f = true;
>  cpu->cfg.ext_icsr = true;
>  cpu->cfg.ext_ifencei = true;
>
> @@ -854,7 +854,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  return;
>  }
>
> -if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
> +if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
>  error_setg(errp, "F extension requires Zicsr");
>  return;
>  }
> @@ -868,12 +868,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  cpu->cfg.ext_zfhmin = true;
>  }
>
> -if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) {
> +if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
>  error_setg(errp, "Zfh/Zfhmin extensions require F extension");
>  return;
>  }
>
> -if (riscv_has_ext(env, RVD) && !cpu->cfg.ext_f) {
> +if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
>  error_setg(errp, "D extension requires F extension");
>  return;
>  }
> @@ -898,7 +898,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  return;
>  }
>
> -if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) {
> +if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
>  error_setg(errp, "Zve32f/Zve64f extensions require F extension");
>  return;
>  }
> @@ -931,7 +931,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  error_setg(errp, "Zfinx extension requires Zicsr");
>  return;
>  }
> -if (cpu->cfg.ext_f) {
> +if (riscv_has_ext(env, RVF)) {
>  error_setg(errp,
> "Zfinx cannot be supported together with F 
> extension");
>  return;
> @@ -1100,7 +1100,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
>  if (riscv_has_ext(env, RVA)) {
>  ext |= RVA;
>  }
> -if (riscv_cpu_cfg(env)->ext_f) {
> +if (riscv_has_ext(env, RVF)) {
>  ext |= RVF;
>  }
>  if (riscv_has_ext(env, RVD)) {
> @@ -1440,6 +1440,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>   .misa_bit = RVC, .enabled = true},
>  {.name = "d", .description = "Double-precision float point",
>   .misa_bit = RVD, .enabled = true},
> +{.name = "f", .description = "Single-precision float point",
> + .misa_bit = RVF, .enabled = true},
>  };
>
>  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> @@ -1466,7 +1468,6 @@ static Property riscv_cpu_extensions[] = {
>  DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
>  DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
>  DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
> -DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
>  DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
>  DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>  DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
> @@ -1577,7 +1578,6 @@ static void register_cpu_props(Object *obj)
>  cpu->cfg.ext_i = misa_ext & RVI;
>  cpu->cfg.ext_e = misa_ext & RVE;
>  cpu->cfg.ext_m = misa_ext & RVM;
> -cpu->cfg.ext_f = misa_ext & RVF;
>  cpu->cfg.ext_v = misa_ext & RVV;
>  cpu->cfg.ext_s = misa_ext & RVS;
>  cpu->cfg.ext_u = misa_ext & RVU;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index e4cf79e36f..ce23b1c431 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -422,7 +422,6 @@ struct RISCVCPUConfig {
>  bool ext_e;
>  bool ext_g;
>  bool ext_m;

Re: [PATCH v3 07/20] target/riscv: remove cpu->cfg.ext_d

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
 wrote:
>
> Create a new "d" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVD. Instances of cpu->cfg.ext_d and similar are
> replaced with riscv_has_ext(env, RVD).
>
> Remove the old "d" property and 'ext_d' from RISCVCPUConfig.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 13 ++---
>  target/riscv/cpu.h |  1 -
>  2 files changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 693ff10cab..9bb714d0d8 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -812,13 +812,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  /* Do some ISA extension error checking */
>  if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
>  riscv_has_ext(env, RVA) &&
> -cpu->cfg.ext_f && cpu->cfg.ext_d &&
> +cpu->cfg.ext_f && riscv_has_ext(env, RVD) &&
>  cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
>  warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
>  cpu->cfg.ext_i = true;
>  cpu->cfg.ext_m = true;
>  cpu->cfg.ext_f = true;
> -cpu->cfg.ext_d = true;
>  cpu->cfg.ext_icsr = true;
>  cpu->cfg.ext_ifencei = true;
>
> @@ -874,7 +873,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  return;
>  }
>
> -if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
> +if (riscv_has_ext(env, RVD) && !cpu->cfg.ext_f) {
>  error_setg(errp, "D extension requires F extension");
>  return;
>  }
> @@ -894,7 +893,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  cpu->cfg.ext_zve32f = true;
>  }
>
> -if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) {
> +if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
>  error_setg(errp, "Zve64d/V extensions require D extension");
>  return;
>  }
> @@ -1104,7 +1103,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
>  if (riscv_cpu_cfg(env)->ext_f) {
>  ext |= RVF;
>  }
> -if (riscv_cpu_cfg(env)->ext_d) {
> +if (riscv_has_ext(env, RVD)) {
>  ext |= RVD;
>  }
>  if (riscv_has_ext(env, RVC)) {
> @@ -1439,6 +1438,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>   .misa_bit = RVA, .enabled = true},
>  {.name = "c", .description = "Compressed instructions",
>   .misa_bit = RVC, .enabled = true},
> +{.name = "d", .description = "Double-precision float point",
> + .misa_bit = RVD, .enabled = true},
>  };
>
>  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> @@ -1466,7 +1467,6 @@ static Property riscv_cpu_extensions[] = {
>  DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
>  DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
>  DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
> -DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
>  DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
>  DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>  DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
> @@ -1578,7 +1578,6 @@ static void register_cpu_props(Object *obj)
>  cpu->cfg.ext_e = misa_ext & RVE;
>  cpu->cfg.ext_m = misa_ext & RVM;
>  cpu->cfg.ext_f = misa_ext & RVF;
> -cpu->cfg.ext_d = misa_ext & RVD;
>  cpu->cfg.ext_v = misa_ext & RVV;
>  cpu->cfg.ext_s = misa_ext & RVS;
>  cpu->cfg.ext_u = misa_ext & RVU;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index c6dc24d236..e4cf79e36f 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -423,7 +423,6 @@ struct RISCVCPUConfig {
>  bool ext_g;
>  bool ext_m;
>  bool ext_f;
> -bool ext_d;
>  bool ext_s;
>  bool ext_u;
>  bool ext_h;
> --
> 2.39.2
>
>

Re: [PATCH v3 06/20] target/riscv: remove cpu->cfg.ext_c

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
 wrote:
>
> Create a new "c" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVC. Instances of cpu->cfg.ext_c and similar are
> replaced with riscv_has_ext(env, RVC).
>
> Remove the old "c" property and 'ext_c' from RISCVCPUConfig.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 7 +++
>  target/riscv/cpu.h | 1 -
>  2 files changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 63efd1b313..693ff10cab 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -400,7 +400,6 @@ static void rv64_thead_c906_cpu_init(Object *obj)
>  set_priv_version(env, PRIV_VERSION_1_11_0);
>
>  cpu->cfg.ext_g = true;
> -cpu->cfg.ext_c = true;
>  cpu->cfg.ext_u = true;
>  cpu->cfg.ext_s = true;
>  cpu->cfg.ext_icsr = true;
> @@ -1108,7 +1107,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
>  if (riscv_cpu_cfg(env)->ext_d) {
>  ext |= RVD;
>  }
> -if (riscv_cpu_cfg(env)->ext_c) {
> +if (riscv_has_ext(env, RVC)) {
>  ext |= RVC;
>  }
>  if (riscv_cpu_cfg(env)->ext_s) {
> @@ -1438,6 +1437,8 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor 
> *v, const char *name,
>  static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>  {.name = "a", .description = "Atomic instructions",
>   .misa_bit = RVA, .enabled = true},
> +{.name = "c", .description = "Compressed instructions",
> + .misa_bit = RVC, .enabled = true},
>  };
>
>  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> @@ -1466,7 +1467,6 @@ static Property riscv_cpu_extensions[] = {
>  DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
>  DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
>  DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
> -DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
>  DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
>  DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>  DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
> @@ -1580,7 +1580,6 @@ static void register_cpu_props(Object *obj)
>  cpu->cfg.ext_f = misa_ext & RVF;
>  cpu->cfg.ext_d = misa_ext & RVD;
>  cpu->cfg.ext_v = misa_ext & RVV;
> -cpu->cfg.ext_c = misa_ext & RVC;
>  cpu->cfg.ext_s = misa_ext & RVS;
>  cpu->cfg.ext_u = misa_ext & RVU;
>  cpu->cfg.ext_h = misa_ext & RVH;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index f703888310..c6dc24d236 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -424,7 +424,6 @@ struct RISCVCPUConfig {
>  bool ext_m;
>  bool ext_f;
>  bool ext_d;
> -bool ext_c;
>  bool ext_s;
>  bool ext_u;
>  bool ext_h;
> --
> 2.39.2
>
>

Re: [PATCH v3 05/20] target/riscv: remove cpu->cfg.ext_a

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
 wrote:
>
> Create a new "a" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are
> replaced with riscv_has_ext(env, RVA).
>
> Remove the old "a" property and 'ext_a' from RISCVCPUConfig.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 16 
>  target/riscv/cpu.h |  1 -
>  2 files changed, 8 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d7763ecfa9..63efd1b313 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -812,13 +812,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>
>  /* Do some ISA extension error checking */
>  if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
> -cpu->cfg.ext_a && cpu->cfg.ext_f &&
> -cpu->cfg.ext_d &&
> +riscv_has_ext(env, RVA) &&
> +cpu->cfg.ext_f && cpu->cfg.ext_d &&
>  cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
>  warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
>  cpu->cfg.ext_i = true;
>  cpu->cfg.ext_m = true;
> -cpu->cfg.ext_a = true;
>  cpu->cfg.ext_f = true;
>  cpu->cfg.ext_d = true;
>  cpu->cfg.ext_icsr = true;
> @@ -862,7 +861,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  return;
>  }
>
> -if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) {
> +if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
>  error_setg(errp, "Zawrs extension requires A extension");
>  return;
>  }
> @@ -1100,7 +1099,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
>  if (riscv_cpu_cfg(env)->ext_m) {
>  ext |= RVM;
>  }
> -if (riscv_cpu_cfg(env)->ext_a) {
> +if (riscv_has_ext(env, RVA)) {
>  ext |= RVA;
>  }
>  if (riscv_cpu_cfg(env)->ext_f) {
> @@ -1436,7 +1435,10 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor 
> *v, const char *name,
>  visit_type_bool(v, name, , errp);
>  }
>
> -static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {};
> +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
> +{.name = "a", .description = "Atomic instructions",
> + .misa_bit = RVA, .enabled = true},
> +};
>
>  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
>  {
> @@ -1462,7 +1464,6 @@ static Property riscv_cpu_extensions[] = {
>  DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
>  DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
>  DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
> -DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
>  DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
>  DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
>  DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
> @@ -1576,7 +1577,6 @@ static void register_cpu_props(Object *obj)
>  cpu->cfg.ext_i = misa_ext & RVI;
>  cpu->cfg.ext_e = misa_ext & RVE;
>  cpu->cfg.ext_m = misa_ext & RVM;
> -cpu->cfg.ext_a = misa_ext & RVA;
>  cpu->cfg.ext_f = misa_ext & RVF;
>  cpu->cfg.ext_d = misa_ext & RVD;
>  cpu->cfg.ext_v = misa_ext & RVV;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 638e47c75a..f703888310 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -422,7 +422,6 @@ struct RISCVCPUConfig {
>  bool ext_e;
>  bool ext_g;
>  bool ext_m;
> -bool ext_a;
>  bool ext_f;
>  bool ext_d;
>  bool ext_c;
> --
> 2.39.2
>
>

Re: [PATCH v3 04/20] target/riscv: introduce riscv_cpu_add_misa_properties()

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:29 AM Daniel Henrique Barboza
 wrote:
>
> Ever since RISCVCPUConfig got introduced users are able to set CPU extensions
> in the command line. User settings are reflected in the cpu->cfg object
> for later use. These properties are used in the target/riscv/cpu.c code,
> most notably in riscv_cpu_validate_set_extensions(), where most of our
> realize time validations are made.
>
> And then there's env->misa_ext, the field where the MISA extensions are
> set, that is read everywhere else. We need to keep env->misa_ext updated
> with cpu->cfg settings, since our validations rely on it, forcing us to
> make register_cpu_props() write cpu->cfg.ext_N flags to cover for named
> CPUs that aren't used named properties but also needs to go through the
> same validation steps. Failing to so will make those name CPUs fail
> validation (see c66ffcd5358b for more info). Not only that, but we also
> need to sync env->misa_ext with cpu->cfg again during realize() time to
> catch any change the user might have done, since the rest of the code
> relies on that.
>
> Making cpu->cfg.ext_N and env->misa_ext reflect each other is not
> needed. What we want is a way for users to enable/disable MISA extensions,
> and there's nothing stopping us from letting the user write env->misa_ext
> directly. Here are the artifacts that will enable us to do that:
>
> - RISCVCPUMisaExtConfig will declare each MISA property;
>
> - cpu_set_misa_ext_cfg() is the setter for each property. We'll write
>   env->misa_ext and env->misa_ext_mask with the appropriate misa_bit;
>   cutting off cpu->cfg.ext_N from the logic;
>
> - cpu_get_misa_ext_cfg() is a getter that will retrieve the current val
>   of the property based on env->misa_ext;
>
> - riscv_cpu_add_misa_properties() will be called in register_cpu_props()
>   to init all MISA properties from the misa_ext_cfgs[] array.
>
> With this infrastructure we'll start to get rid of each cpu->cfg.ext_N
> attribute in the next patches.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 65 ++
>  1 file changed, 65 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 5ae9440aee..d7763ecfa9 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1393,6 +1393,69 @@ static void riscv_cpu_init(Object *obj)
>  #endif /* CONFIG_USER_ONLY */
>  }
>
> +typedef struct RISCVCPUMisaExtConfig {
> +const char *name;
> +const char *description;
> +target_ulong misa_bit;
> +bool enabled;
> +} RISCVCPUMisaExtConfig;
> +
> +static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> +const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
> +target_ulong misa_bit = misa_ext_cfg->misa_bit;
> +RISCVCPU *cpu = RISCV_CPU(obj);
> +CPURISCVState *env = >env;
> +bool value;
> +
> +if (!visit_type_bool(v, name, , errp)) {
> +return;
> +}
> +
> +if (value) {
> +env->misa_ext |= misa_bit;
> +env->misa_ext_mask |= misa_bit;
> +} else {
> +env->misa_ext &= ~misa_bit;
> +env->misa_ext_mask &= ~misa_bit;
> +}
> +}
> +
> +static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> +const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
> +target_ulong misa_bit = misa_ext_cfg->misa_bit;
> +RISCVCPU *cpu = RISCV_CPU(obj);
> +CPURISCVState *env = >env;
> +bool value;
> +
> +value = env->misa_ext & misa_bit;
> +
> +visit_type_bool(v, name, , errp);
> +}
> +
> +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {};
> +
> +static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> +{
> +int i;
> +
> +for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
> +const RISCVCPUMisaExtConfig *misa_cfg = _ext_cfgs[i];
> +
> +object_property_add(cpu_obj, misa_cfg->name, "bool",
> +cpu_get_misa_ext_cfg,
> +cpu_set_misa_ext_cfg,
> +NULL, (void *)misa_cfg);
> +object_property_set_description(cpu_obj, misa_cfg->name,
> +misa_cfg->description);
> +object_property_set_bool(cpu_obj, misa_cfg->name,
> + misa_cfg->enabled, NULL);
> +}
> +}
> +
>  static Property riscv_cpu_extensions[] = {
>  /* Defaults for standard extensions */
>  DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
> @@ -1530,6 +1593,8 @@ static void register_cpu_props(Object *obj)
>  return;
>  }
>
> +riscv_cpu_add_misa_properties(obj);
> +
>  for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
>  qdev_property_add_static(dev, prop);
>  }
> --
> 2.39.2
>
>

Re: [PATCH v3 03/20] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:32 AM Daniel Henrique Barboza
 wrote:
>
> We don't have MISA extensions in isa_edata_arr[] anymore. Remove the
> redundant 'multi_letter' field from isa_ext_data.
>
> Suggested-by: Weiwei Li 
> Signed-off-by: Daniel Henrique Barboza 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 118 ++---
>  1 file changed, 58 insertions(+), 60 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 21c0c637e4..5ae9440aee 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -48,13 +48,12 @@ static const char riscv_single_letter_exts[] = 
> "IEMAFDQCPVH";
>
>  struct isa_ext_data {
>  const char *name;
> -bool multi_letter;
>  int min_version;
>  int ext_enable_offset;
>  };
>
> -#define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \
> -{#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
> +#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
> +{#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
>
>  /**
>   * Here are the ordering rules of extension naming defined by RISC-V
> @@ -77,61 +76,61 @@ struct isa_ext_data {
>   * instead.
>   */
>  static const struct isa_ext_data isa_edata_arr[] = {
> -ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom),
> -ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz),
> -ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond),
> -ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
> -ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
> -ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, 
> ext_zihintpause),
> -ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs),
> -ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh),
> -ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
> -ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
> -ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
> -ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba),
> -ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb),
> -ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc),
> -ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb),
> -ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc),
> -ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx),
> -ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs),
> -ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk),
> -ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn),
> -ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd),
> -ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne),
> -ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh),
> -ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr),
> -ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks),
> -ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed),
> -ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh),
> -ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt),
> -ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f),
> -ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
> -ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_12_0, ext_zve64d),
> -ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh),
> -ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin),
> -ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
> -ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
> -ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia),
> -ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia),
> -ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf),
> -ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc),
> -ISA_EXT_DATA_ENTRY(svadu, true, PRIV_VERSION_1_12_0, ext_svadu),
> -ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
> -ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
> -ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
> -ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba),
> -ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb),
> -ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs),
> -ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
> -ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, 
> ext_xtheadcondmov),
> -ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, 
> ext_xtheadfmemidx),
> -ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv),
> -ISA_EXT_DATA_ENTRY(xtheadmac, true, 

Re: [PATCH v3 02/20] target/riscv: remove MISA properties from isa_edata_arr[]

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:33 AM Daniel Henrique Barboza
 wrote:
>
> The code that disables extensions if there's a priv version mismatch
> uses cpu->cfg.ext_N properties to do its job.
>
> We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split
> the MISA related verifications in a new function, removing it from
> isa_edata_arr[].
>
> We're also erroring it out instead of disabling, making the cpu_init()
> function responsible for running an adequate priv spec for the MISA
> extensions it wants to use.
>
> Note that the RVV verification is being ignored since we're always have
> at least PRIV_VERSION_1_10_0.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 19 +--
>  1 file changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 2711d80e16..21c0c637e4 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -72,10 +72,11 @@ struct isa_ext_data {
>   * 4. Non-standard extensions (starts with 'X') must be listed after all
>   *standard extensions. They must be separated from other multi-letter
>   *extensions by an underscore.
> + *
> + * Single letter extensions are checked in riscv_cpu_validate_misa_priv()
> + * instead.
>   */
>  static const struct isa_ext_data isa_edata_arr[] = {
> -ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h),
> -ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v),
>  ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom),
>  ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz),
>  ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond),
> @@ -1131,6 +1132,14 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
>  env->misa_ext = env->misa_ext_mask = ext;
>  }
>
> +static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
> +{
> +if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
> +error_setg(errp, "H extension requires priv spec 1.12.0");
> +return;
> +}
> +}
> +
>  static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>  {
>  CPUState *cs = CPU(dev);
> @@ -1174,6 +1183,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>   */
>  riscv_cpu_sync_misa_cfg(env);
>
> +riscv_cpu_validate_misa_priv(env, _err);
> +if (local_err != NULL) {
> +error_propagate(errp, local_err);
> +return;
> +}
> +
>  /* Force disable extensions if priv spec version does not match */
>  for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
>  if (isa_ext_is_enabled(cpu, _edata_arr[i]) &&
> --
> 2.39.2
>
>

Re: [PATCH v3 01/20] target/riscv: sync env->misa_ext* with cpu->cfg in realize()

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:29 AM Daniel Henrique Barboza
 wrote:
>
> When riscv_cpu_realize() starts we're guaranteed to have cpu->cfg.ext_N
> properties updated. The same can't be said about env->misa_ext*, since
> the user might enable/disable MISA extensions in the command line, and
> env->misa_ext* won't caught these changes. The current solution is to
> sync everything at the end of validate_set_extensions(), checking every
> cpu->cfg.ext_N value to do a set_misa() in the end.
>
> The last change we're making in the MISA cfg flags are in the G
> extension logic, enabling IMAFG if cpu->cfg_ext.g is enabled. Otherwise
> we're not making any changes in MISA bits ever since realize() starts.
>
> There's no reason to postpone misa_ext updates until the end of the
> validation. Let's do it earlier, during realize(), in a new helper
> called riscv_cpu_sync_misa_cfg(). If cpu->cfg.ext_g is enabled, do it
> again by updating env->misa_ext* directly.
>
> This is a pre-requisite to allow riscv_cpu_validate_set_extensions() to
> use riscv_has_ext() instead of cpu->cfg.ext_N to validate the MISA
> extensions, which is our end goal here.
>
> Signed-off-by: Daniel Henrique Barboza 
> Reviewed-by: Weiwei Li 
> ---
>  target/riscv/cpu.c | 94 +++---
>  1 file changed, 56 insertions(+), 38 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1e97473af2..2711d80e16 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -804,12 +804,11 @@ static void riscv_cpu_disas_set_info(CPUState *s, 
> disassemble_info *info)
>
>  /*
>   * Check consistency between chosen extensions while setting
> - * cpu->cfg accordingly, doing a set_misa() in the end.
> + * cpu->cfg accordingly.
>   */
>  static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>  {
>  CPURISCVState *env = >env;
> -uint32_t ext = 0;
>
>  /* Do some ISA extension error checking */
>  if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
> @@ -824,6 +823,9 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  cpu->cfg.ext_d = true;
>  cpu->cfg.ext_icsr = true;
>  cpu->cfg.ext_ifencei = true;
> +
> +env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
> +env->misa_ext_mask = env->misa_ext;
>  }
>
>  if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
> @@ -962,39 +964,8 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  cpu->cfg.ext_zksh = true;
>  }
>
> -if (cpu->cfg.ext_i) {
> -ext |= RVI;
> -}
> -if (cpu->cfg.ext_e) {
> -ext |= RVE;
> -}
> -if (cpu->cfg.ext_m) {
> -ext |= RVM;
> -}
> -if (cpu->cfg.ext_a) {
> -ext |= RVA;
> -}
> -if (cpu->cfg.ext_f) {
> -ext |= RVF;
> -}
> -if (cpu->cfg.ext_d) {
> -ext |= RVD;
> -}
> -if (cpu->cfg.ext_c) {
> -ext |= RVC;
> -}
> -if (cpu->cfg.ext_s) {
> -ext |= RVS;
> -}
> -if (cpu->cfg.ext_u) {
> -ext |= RVU;
> -}
> -if (cpu->cfg.ext_h) {
> -ext |= RVH;
> -}
>  if (cpu->cfg.ext_v) {
>  int vext_version = VEXT_VERSION_1_00_0;
> -ext |= RVV;
>  if (!is_power_of_2(cpu->cfg.vlen)) {
>  error_setg(errp,
> "Vector extension VLEN must be power of 2");
> @@ -1032,11 +1003,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>  }
>  set_vext_version(env, vext_version);
>  }
> -if (cpu->cfg.ext_j) {
> -ext |= RVJ;
> -}
> -
> -set_misa(env, env->misa_mxl, ext);
>  }
>
>  #ifndef CONFIG_USER_ONLY
> @@ -1121,6 +1087,50 @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, 
> Error **errp)
>  #endif
>  }
>
> +static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
> +{
> +uint32_t ext = 0;
> +
> +if (riscv_cpu_cfg(env)->ext_i) {

It's probably worth storing riscv_cpu_cfg(env) in a variable

But either way:

Reviewed-by: Alistair Francis 

Alistair

> +ext |= RVI;
> +}
> +if (riscv_cpu_cfg(env)->ext_e) {
> +ext |= RVE;
> +}
> +if (riscv_cpu_cfg(env)->ext_m) {
> +ext |= RVM;
> +}
> +if (riscv_cpu_cfg(env)->ext_a) {
> +ext |= RVA;
> +}
> +if (riscv_cpu_cfg(env)->ext_f) {
> +ext |= RVF;
> +}
> +if (riscv_cpu_cfg(env)->ext_d) {
> +ext |= RVD;
> +}
> +if (riscv_cpu_cfg(env)->ext_c) {
> +ext |= RVC;
> +}
> +if (riscv_cpu_cfg(env)->ext_s) {
> +ext |= RVS;
> +}
> +if (riscv_cpu_cfg(env)->ext_u) {
> +ext |= RVU;
> +}
> +if (riscv_cpu_cfg(env)->ext_h) {
> +ext |= RVH;
> +}
> +if (riscv_cpu_cfg(env)->ext_v) {
> +ext |= RVV;
> +}
> +if (riscv_cpu_cfg(env)->ext_j) {
> +ext |= RVJ;
> +}
> +
> +env->misa_ext = env->misa_ext_mask = ext;
> +}
> +
>  static 

Re: [PATCH v3 0/4] target/riscv: Simplification for RVH related check and code style fix

[Alistair Francis]

On Wed, Apr 5, 2023 at 6:59 PM Weiwei Li  wrote:
>
> This patchset tries to simplify the RVH related check and fix some code style 
> problems, such as problems for indentation, multi-line comments and lines 
> with over 80 characters.
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-virtfix-upstream
>
> v2:
> * add comment to specify riscv_cpu_set_virt_enabled() can only be called when 
> RVH is enabled in patch 4 (suggested by Richard Henderson)
> * merge patch from LIU Zhiwei(Message-ID: 
> <20230325145348.1208-1-zhiwei_...@linux.alibaba.com>) to patch 5
> * use env->virt_enabled directly instead of riscv_cpu_virt_enabled() in patch 
> 6 (suggested by LIU Zhiwei)
> * remain the orginal identation for macro name in patch 8 (suggested by LIU 
> Zhiwei)
>
> v3:
> * rebase on riscv-to-apply.next (partial patches in v2 have been applied)
> * Fix new found format problem in patch 2,3,4 of v3
>
> Weiwei Li (4):
>   target/riscv: Remove riscv_cpu_virt_enabled()
>   target/riscv: Fix format for indentation
>   target/riscv: Fix format for comments
>   target/riscv: Fix lines with over 80 characters

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/arch_dump.c|   7 +-
>  target/riscv/cpu.c  |  47 ++--
>  target/riscv/cpu.h  |  31 +--
>  target/riscv/cpu_bits.h |   2 +-
>  target/riscv/cpu_helper.c   | 274 ++--
>  target/riscv/csr.c  |  90 +++
>  target/riscv/debug.c|  21 +-
>  target/riscv/fpu_helper.c   |  24 +-
>  target/riscv/gdbstub.c  |   3 +-
>  target/riscv/insn_trans/trans_rvv.c.inc |  36 +--
>  target/riscv/m128_helper.c  |  16 +-
>  target/riscv/machine.c  |  18 +-
>  target/riscv/op_helper.c|  20 +-
>  target/riscv/pmp.c  |  66 ++---
>  target/riscv/pmp.h  |   9 +-
>  target/riscv/pmu.c  |   7 +-
>  target/riscv/sbi_ecall_interface.h  |   8 +-
>  target/riscv/translate.c|  26 +-
>  target/riscv/vector_helper.c| 317 ++--
>  19 files changed, 552 insertions(+), 470 deletions(-)
>
> --
> 2.25.1
>
>

Re: [PATCH for-8.1] target/sparc: Use tcg_gen_lookup_and_goto_ptr

[Richard Henderson]

On 4/5/23 14:09, Mark Cave-Ayland wrote:
I can certainly give this an R-B, however I'm fairly sure I tried this a couple of years 
back and found that it introduced random hangs on qemu-system-sparc64 :/. Have you seen 
any issues in the relevant avocado tests with this patch applied?


No issues.

I suspect the last time this was tried all tcg_gen_exit_tb were replaced, including the 
one after changing psr.  That would mean we wouldn't see exceptions after enabling.



r~

Re: [RFC PATCH v3 1/2] mm: restrictedmem: Allow userspace to specify mount for memfd_restricted

[Ackerley Tng]

Thanks for reviewing these patches!

"Kirill A. Shutemov"  writes:


On Fri, Mar 31, 2023 at 11:50:39PM +, Ackerley Tng wrote:



...



+static int restrictedmem_create_on_user_mount(int mount_fd)
+{
+   int ret;
+   struct fd f;
+   struct vfsmount *mnt;
+
+   f = fdget_raw(mount_fd);
+   if (!f.file)
+   return -EBADF;
+
+   ret = -EINVAL;
+   if (!is_mount_root(f.file))
+   goto out;
+
+   mnt = f.file->f_path.mnt;
+   if (!is_shmem_mount(mnt))
+   goto out;
+
+   ret = file_permission(f.file, MAY_WRITE | MAY_EXEC);



Why MAY_EXEC?



Christian pointed out that this check does not make sense, I'll be
removing the entire check in the next revision.


+   if (ret)
+   goto out;
+
+   ret = mnt_want_write(mnt);
+   if (unlikely(ret))
+   goto out;
+
+   ret = restrictedmem_create(mnt);
+
+   mnt_drop_write(mnt);
+out:
+   fdput(f);
+
+   return ret;
+}



We need review from fs folks. Look mostly sensible, but I have no
experience in fs.



+
+SYSCALL_DEFINE2(memfd_restricted, unsigned int, flags, int, mount_fd)
+{
+   if (flags & ~RMFD_USERMNT)
+   return -EINVAL;
+
+   if (flags == RMFD_USERMNT) {
+   if (mount_fd < 0)
+   return -EINVAL;
+
+   return restrictedmem_create_on_user_mount(mount_fd);
+   } else {
+   return restrictedmem_create(NULL);
+   }



Maybe restructure with single restrictedmem_create() call?



struct vfsmount *mnt = NULL;



if (flags == RMFD_USERMNT) {
...
mnt = ...();
}



return restrictedmem_create(mnt);


Will do so in the next revision.


+}
+
  int restrictedmem_bind(struct file *file, pgoff_t start, pgoff_t end,
   struct restrictedmem_notifier *notifier, bool exclusive)
  {
--
2.40.0.348.gf938b09366-goog

Re: [RFC PATCH v3 1/2] mm: restrictedmem: Allow userspace to specify mount for memfd_restricted

[Ackerley Tng]

Thanks for your review!

David Hildenbrand  writes:


On 01.04.23 01:50, Ackerley Tng wrote:



...


diff --git a/include/uapi/linux/restrictedmem.h  
b/include/uapi/linux/restrictedmem.h

new file mode 100644
index ..22d6f2285f6d
--- /dev/null
+++ b/include/uapi/linux/restrictedmem.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _UAPI_LINUX_RESTRICTEDMEM_H
+#define _UAPI_LINUX_RESTRICTEDMEM_H
+
+/* flags for memfd_restricted */
+#define RMFD_USERMNT   0x0001U



I wonder if we can come up with a more expressive prefix than RMFD.
Sounds more like "rm fd" ;) Maybe it should better match the
"memfd_restricted" syscall name, like "MEMFD_RSTD_USERMNT".



RMFD did actually sound vulgar, I'm good with MEMFD_RSTD_USERMNT!


+
+#endif /* _UAPI_LINUX_RESTRICTEDMEM_H */
diff --git a/mm/restrictedmem.c b/mm/restrictedmem.c
index c5d869d8c2d8..f7b62364a31a 100644
--- a/mm/restrictedmem.c
+++ b/mm/restrictedmem.c
@@ -1,11 +1,12 @@
   // SPDX-License-Identifier: GPL-2.0
-#include "linux/sbitmap.h"



Looks like an unrelated change?



Will remove this in the next revision.


+#include 
   #include 
   #include 
   #include 
   #include 
   #include 
   #include 
+#include 
   #include 



   struct restrictedmem {
@@ -189,19 +190,20 @@ static struct file  
*restrictedmem_file_create(struct file *memfd)

return file;
   }



-SYSCALL_DEFINE1(memfd_restricted, unsigned int, flags)
+static int restrictedmem_create(struct vfsmount *mount)
   {
struct file *file, *restricted_file;
int fd, err;



-   if (flags)
-   return -EINVAL;
-
fd = get_unused_fd_flags(0);
if (fd < 0)
return fd;



-   file = shmem_file_setup("memfd:restrictedmem", 0, VM_NORESERVE);
+   if (mount)
+		file = shmem_file_setup_with_mnt(mount, "memfd:restrictedmem", 0,  
VM_NORESERVE);

+   else
+   file = shmem_file_setup("memfd:restrictedmem", 0, VM_NORESERVE);
+
if (IS_ERR(file)) {
err = PTR_ERR(file);
goto err_fd;
@@ -223,6 +225,66 @@ SYSCALL_DEFINE1(memfd_restricted, unsigned int,  
flags)

return err;
   }



+static bool is_shmem_mount(struct vfsmount *mnt)
+{
+   return mnt && mnt->mnt_sb && mnt->mnt_sb->s_magic == TMPFS_MAGIC;
+}
+
+static bool is_mount_root(struct file *file)
+{
+   return file->f_path.dentry == file->f_path.mnt->mnt_root;
+}



I'd inline at least that function, pretty self-explaining.



Will inline this in the next revision.


+
+static int restrictedmem_create_on_user_mount(int mount_fd)
+{
+   int ret;
+   struct fd f;
+   struct vfsmount *mnt;
+
+   f = fdget_raw(mount_fd);
+   if (!f.file)
+   return -EBADF;
+
+   ret = -EINVAL;
+   if (!is_mount_root(f.file))
+   goto out;
+
+   mnt = f.file->f_path.mnt;
+   if (!is_shmem_mount(mnt))
+   goto out;
+
+   ret = file_permission(f.file, MAY_WRITE | MAY_EXEC);
+   if (ret)
+   goto out;
+
+   ret = mnt_want_write(mnt);
+   if (unlikely(ret))
+   goto out;
+
+   ret = restrictedmem_create(mnt);
+
+   mnt_drop_write(mnt);
+out:
+   fdput(f);
+
+   return ret;
+}
+
+SYSCALL_DEFINE2(memfd_restricted, unsigned int, flags, int, mount_fd)
+{
+   if (flags & ~RMFD_USERMNT)
+   return -EINVAL;
+
+   if (flags == RMFD_USERMNT) {
+   if (mount_fd < 0)
+   return -EINVAL;
+
+   return restrictedmem_create_on_user_mount(mount_fd);
+   } else {
+   return restrictedmem_create(NULL);
+   }




You can drop the else case:



if (flags == RMFD_USERMNT) {
...
return restrictedmem_create_on_user_mount(mount_fd);
}
return restrictedmem_create(NULL);



I'll be refactoring this to adopt Kirill's suggestion of using a single
restrictedmem_create(mnt) call.



I do wonder if you want to properly check for a flag instead of
comparing values. Results in a more natural way to deal with flags:



if (flags & RMFD_USERMNT) {



}



Will use this in the next revision.


+}
+
   int restrictedmem_bind(struct file *file, pgoff_t start, pgoff_t end,
   struct restrictedmem_notifier *notifier, bool exclusive)
   {



The "memfd_restricted" vs. "restrictedmem" terminology is a bit
unfortunate, but not your fault here.




I'm not a FS person, but it does look good to me.

Re: [PATCH] Hexagon (target/hexagon) Remove redundant/unused macros

[Richard Henderson]

On 4/5/23 11:30, Taylor Simpson wrote:

Remove the following macros (remnants of the old generator design)
 READ_REG
 READ_PREG
 WRITE_RREG
 WRITE_PREG
Modify macros that rely on the above

The following are unused
 READ_IREG
 fGET_FIELD
 fSET_FIELD
 fREAD_P3
 fREAD_NPC
 fWRITE_LC0
 fWRITE_LC1

Signed-off-by: Taylor Simpson
---
  target/hexagon/macros.h | 65 ++---
  1 file changed, 22 insertions(+), 43 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH] Hexagon (target/hexagon) Add overrides for count trailing zeros/ones

[Richard Henderson]

On 4/5/23 09:42, Taylor Simpson wrote:

The following instructions are overriden
 S2_ct0Count trailing zeros
 S2_ct1Count trailing ones
 S2_ct0p   Count trailing zeros (register pair)
 S2_ct1p   Count trailing ones (register pair)

These instructions are not handled by idef-parser because the
imported semantics uses bit-reverse.  However, they are
straightforward to implement in TCG with tcg_gen_ctzi_*

Test cases added to tests/tcg/hexagon/misc.c

Signed-off-by: Taylor Simpson
---
  target/hexagon/gen_tcg.h | 24 +
  tests/tcg/hexagon/misc.c | 56 +++-
  2 files changed, 79 insertions(+), 1 deletion(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 0/2] target/arm: KVM Aarch32 spring cleaning

[Richard Henderson]

On 4/5/23 03:08, Philippe Mathieu-Daudé wrote:

Remove unused KVM/Aarch32 definitions.

Philippe Mathieu-Daudé (2):
   target/arm: Remove KVM AArch32 CPU definitions
   hw/arm/virt: Restrict Cortex-A7 check to TCG

  target/arm/kvm-consts.h | 9 +++--
  hw/arm/virt.c   | 2 ++
  target/arm/cpu_tcg.c| 2 --
  3 files changed, 5 insertions(+), 8 deletions(-)



Reviewed-by: Richard Henderson 

r~

Re: [RFC PATCH v3 1/2] mm: restrictedmem: Allow userspace to specify mount for memfd_restricted

[Ackerley Tng]

Thanks again for your review!

Christian Brauner  writes:

On Tue, Apr 04, 2023 at 03:53:13PM +0200, Christian Brauner wrote:

On Fri, Mar 31, 2023 at 11:50:39PM +, Ackerley Tng wrote:
>
> ...
>
> -SYSCALL_DEFINE1(memfd_restricted, unsigned int, flags)
> +static int restrictedmem_create(struct vfsmount *mount)
>  {
>struct file *file, *restricted_file;
>int fd, err;
>
> -  if (flags)
> -  return -EINVAL;
> -
>fd = get_unused_fd_flags(0);



Any reasons the file descriptors aren't O_CLOEXEC by default? I don't
see any reasons why we should introduce new fdtypes that aren't
O_CLOEXEC by default. The "don't mix-and-match" train has already left
the station anyway as we do have seccomp noitifer fds and pidfds both of
which are O_CLOEXEC by default.



Thanks for pointing this out. I agree with using O_CLOEXEC, but didn’t
notice this before. Let us discuss this under the original series at
[1].


>if (fd < 0)
>return fd;
>
> -  file = shmem_file_setup("memfd:restrictedmem", 0, VM_NORESERVE);
> +  if (mount)
> +		file = shmem_file_setup_with_mnt(mount, "memfd:restrictedmem", 0,  
VM_NORESERVE);

> +  else
> +  file = shmem_file_setup("memfd:restrictedmem", 0, VM_NORESERVE);
> +
>if (IS_ERR(file)) {
>err = PTR_ERR(file);
>goto err_fd;
> @@ -223,6 +225,66 @@ SYSCALL_DEFINE1(memfd_restricted, unsigned int,  
flags)

>return err;
>  }
>
> +static bool is_shmem_mount(struct vfsmount *mnt)
> +{
> +  return mnt && mnt->mnt_sb && mnt->mnt_sb->s_magic == TMPFS_MAGIC;



This can just be if (mnt->mnt_sb->s_magic == TMPFS_MAGIC).



Will simplify this in the next revision.


> +}
> +
> +static bool is_mount_root(struct file *file)
> +{
> +  return file->f_path.dentry == file->f_path.mnt->mnt_root;



mount -t tmpfs tmpfs /mnt
touch /mnt/bla
touch /mnt/ble
mount --bind /mnt/bla /mnt/ble
fd = open("/mnt/ble")
fd_restricted = memfd_restricted(fd)



IOW, this doesn't restrict it to the tmpfs root. It only restricts it to
paths that refer to the root of any tmpfs mount. To exclude bind-mounts
that aren't bind-mounts of the whole filesystem you want:



path->dentry == path->mnt->mnt_root &&
path->mnt->mnt_root == path->mnt->mnt_sb->s_root



Will adopt this in the next revision and add a selftest to check
this. Thanks for pointing this out!


> +}
> +
> +static int restrictedmem_create_on_user_mount(int mount_fd)
> +{
> +  int ret;
> +  struct fd f;
> +  struct vfsmount *mnt;
> +
> +  f = fdget_raw(mount_fd);
> +  if (!f.file)
> +  return -EBADF;
> +
> +  ret = -EINVAL;
> +  if (!is_mount_root(f.file))
> +  goto out;
> +
> +  mnt = f.file->f_path.mnt;
> +  if (!is_shmem_mount(mnt))
> +  goto out;
> +
> +  ret = file_permission(f.file, MAY_WRITE | MAY_EXEC);



With the current semantics you're asking whether you have write
permissions on the /mnt/ble file in order to get answer to the question
whether you're allowed to create an unlinked restricted memory file.
That doesn't make much sense afaict.



That's true. Since mnt_want_write() already checks for write permissions
and this syscall creates an unlinked file on the mount, we don't have to
check permissions on the file then. Will remove this in the next
revision!


> +  if (ret)
> +  goto out;
> +
> +  ret = mnt_want_write(mnt);
> +  if (unlikely(ret))
> +  goto out;
> +
> +  ret = restrictedmem_create(mnt);
> +
> +  mnt_drop_write(mnt);
> +out:
> +  fdput(f);
> +
> +  return ret;
> +}
> +
> +SYSCALL_DEFINE2(memfd_restricted, unsigned int, flags, int, mount_fd)
> +{
> +  if (flags & ~RMFD_USERMNT)
> +  return -EINVAL;
> +
> +  if (flags == RMFD_USERMNT) {



Why do you even need this flag? It seems that @mount_fd being < 0 is
sufficient to indicate that a new restricted memory fd is supposed to be
created in the system instance.



I'm hoping to have this patch series merged after Chao's patch series
introduces the memfd_restricted() syscall [1].

This flag is necessary to indicate the validity of the second argument.

With this flag, we can definitively return an error if the fd is
invalid, which I think is a better experience for the userspace
programmer than if we just silently default to the kernel mount when the
fd provided is invalid.


> +  if (mount_fd < 0)
> +  return -EINVAL;
> +
> +  return restrictedmem_create_on_user_mount(mount_fd);
> +  } else {
> +  return restrictedmem_create(NULL);
> +  }
> +}


I have to say that I'm very confused by all of this the more I look at  
it.



Effectively memfd restricted functions as a wrapper filesystem around
the tmpfs filesystem. This is basically a weird overlay filesystem.
You're allocating tmpfs files that you stash in restrictedmem files.
I have to say that this seems very hacky. I didn't get this at all at
first.



So what does the caller get if they call statx() on a restricted memfd?
Do they get the device number of the tmpfs mount and the inode 

[PATCH 11/16] bsd-user: Implement do_sysctl_kern_proc_filedesc

[Warner Losh]

From: Stacey Son 

Implement do_sysctl_kern_proc_filedesc. This pulls kern.proc.filedesc
out of the host kernel and converts it to the guest's format.

Signed-off-by: Stacey Son 
Signed-off-by: Warner Losh 
---
 bsd-user/freebsd/os-sys.c | 193 ++
 bsd-user/qemu.h   |   3 +
 2 files changed, 196 insertions(+)

diff --git a/bsd-user/freebsd/os-sys.c b/bsd-user/freebsd/os-sys.c
index d4a6dcc6c2b..00b2dcc9641 100644
--- a/bsd-user/freebsd/os-sys.c
+++ b/bsd-user/freebsd/os-sys.c
@@ -270,6 +270,199 @@ do_sysctl_kern_getprocs(int op, int arg, size_t olen,
 return ret;
 }
 
+static void
+host_to_target_kinfo_file(struct target_kinfo_file *tkif,
+struct kinfo_file *hkif)
+{
+int type = hkif->kf_type;
+
+__put_user(hkif->kf_structsize, >kf_structsize);
+__put_user(hkif->kf_type, >kf_type);
+__put_user(hkif->kf_fd, >kf_fd);
+__put_user(hkif->kf_ref_count, >kf_ref_count);
+__put_user(hkif->kf_flags, >kf_flags);
+__put_user(hkif->kf_offset, >kf_offset);
+switch (type) {
+case TARGET_KF_TYPE_FIFO:
+case TARGET_KF_TYPE_SHM:
+case TARGET_KF_TYPE_VNODE:
+__put_user(hkif->kf_un.kf_file.kf_file_type,
+>kf_un.kf_file.kf_file_type);
+__put_user(hkif->kf_un.kf_file.kf_file_fsid,
+>kf_un.kf_file.kf_file_fsid);
+__put_user(hkif->kf_un.kf_file.kf_file_rdev,
+>kf_un.kf_file.kf_file_rdev);
+__put_user(hkif->kf_un.kf_file.kf_file_fileid,
+>kf_un.kf_file.kf_file_fileid);
+__put_user(hkif->kf_un.kf_file.kf_file_size,
+>kf_un.kf_file.kf_file_size);
+__put_user(hkif->kf_un.kf_file.kf_file_fsid_freebsd11,
+>kf_un.kf_file.kf_file_fsid_freebsd11);
+__put_user(hkif->kf_un.kf_file.kf_file_rdev_freebsd11,
+>kf_un.kf_file.kf_file_rdev_freebsd11);
+__put_user(hkif->kf_un.kf_file.kf_file_mode,
+>kf_un.kf_file.kf_file_mode);
+break;
+
+case TARGET_KF_TYPE_SOCKET:
+__put_user(hkif->kf_un.kf_sock.kf_sock_domain0,
+>kf_un.kf_sock.kf_sock_domain0);
+__put_user(hkif->kf_un.kf_sock.kf_sock_type0,
+>kf_un.kf_sock.kf_sock_type0);
+__put_user(hkif->kf_un.kf_sock.kf_sock_protocol0,
+>kf_un.kf_sock.kf_sock_protocol0);
+/*  XXX - Implement copy function for sockaddr_storage
+host_to_target_copy_sockaddr_storage(
+>kf_un.kf_file.kf_sa_local,
+>kf_un.kf_file.kf_sa_local);
+host_to_target_copy_sockaddr_storage(
+>kf_un.kf_file.kf_sa_peer,
+>kf_un.kf_file.kf_sa_peer);
+*/
+__put_user(hkif->kf_un.kf_sock.kf_sock_pcb,
+>kf_un.kf_sock.kf_sock_pcb);
+__put_user(hkif->kf_un.kf_sock.kf_sock_inpcb,
+>kf_un.kf_sock.kf_sock_inpcb);
+__put_user(hkif->kf_un.kf_sock.kf_sock_unpconn,
+>kf_un.kf_sock.kf_sock_unpconn);
+__put_user(hkif->kf_un.kf_sock.kf_sock_snd_sb_state,
+>kf_un.kf_sock.kf_sock_snd_sb_state);
+__put_user(hkif->kf_un.kf_sock.kf_sock_rcv_sb_state,
+>kf_un.kf_sock.kf_sock_rcv_sb_state);
+break;
+
+case TARGET_KF_TYPE_PIPE:
+__put_user(hkif->kf_un.kf_pipe.kf_pipe_addr,
+>kf_un.kf_pipe.kf_pipe_addr);
+__put_user(hkif->kf_un.kf_pipe.kf_pipe_peer,
+>kf_un.kf_pipe.kf_pipe_peer);
+__put_user(hkif->kf_un.kf_pipe.kf_pipe_buffer_cnt,
+>kf_un.kf_pipe.kf_pipe_buffer_cnt);
+break;
+
+case TARGET_KF_TYPE_SEM:
+__put_user(hkif->kf_un.kf_sem.kf_sem_value,
+>kf_un.kf_sem.kf_sem_value);
+__put_user(hkif->kf_un.kf_sem.kf_sem_mode,
+>kf_un.kf_sem.kf_sem_mode);
+break;
+
+case TARGET_KF_TYPE_PTS:
+__put_user(hkif->kf_un.kf_pts.kf_pts_dev_freebsd11,
+>kf_un.kf_pts.kf_pts_dev_freebsd11);
+__put_user(hkif->kf_un.kf_pts.kf_pts_dev,
+>kf_un.kf_pts.kf_pts_dev);
+break;
+
+case TARGET_KF_TYPE_PROCDESC:
+__put_user(hkif->kf_un.kf_proc.kf_pid,
+>kf_un.kf_proc.kf_pid);
+break;
+
+
+case TARGET_KF_TYPE_CRYPTO:
+case TARGET_KF_TYPE_KQUEUE:
+case TARGET_KF_TYPE_MQUEUE:
+case TARGET_KF_TYPE_NONE:
+case TARGET_KF_TYPE_UNKNOWN:
+default:
+/* Do nothing. */
+break;
+}
+__put_user(hkif->kf_status, >kf_status);
+for (int i = 0; i < (CAP_RIGHTS_VERSION + 2); i++)
+__put_user(hkif->kf_cap_rights.cr_rights[i],
+>kf_cap_rights.cr_rights[i]);
+strncpy(tkif->kf_path, hkif->kf_path, sizeof(tkif->kf_path));
+}
+
+abi_long
+do_sysctl_kern_proc_filedesc(int pid, size_t olen,
+struct target_kinfo_file *tkif, size_t *tlen)
+{
+abi_long ret;
+int mib[4], sz;
+size_t len;
+char *buf, *bp, *eb, *tp;
+

[PATCH 12/16] bsd-user: Implement do_sysctl_kern_proc_vmmap

[Warner Losh]

From: Stacey Son 

Implement do_sysctl_kern_proc_vmmap. This pulls kern.proc.vmmap out of
the host kernel and converts it to the guest's format.

Signed-off-by: Stacey Son 
Signed-off-by: Warner Losh 
---
 bsd-user/freebsd/os-sys.c | 115 ++
 bsd-user/qemu.h   |   3 +
 2 files changed, 118 insertions(+)

diff --git a/bsd-user/freebsd/os-sys.c b/bsd-user/freebsd/os-sys.c
index 00b2dcc9641..418358adc1e 100644
--- a/bsd-user/freebsd/os-sys.c
+++ b/bsd-user/freebsd/os-sys.c
@@ -463,6 +463,121 @@ do_sysctl_kern_proc_filedesc(int pid, size_t olen,
 return ret;
 }
 
+static void
+host_to_target_kinfo_vmentry(struct target_kinfo_vmentry *tkve,
+struct kinfo_vmentry *hkve)
+{
+
+__put_user(hkve->kve_structsize, >kve_structsize);
+__put_user(hkve->kve_type, >kve_type);
+__put_user(hkve->kve_start, >kve_start);
+__put_user(hkve->kve_end, >kve_end);
+__put_user(hkve->kve_offset, >kve_offset);
+__put_user(hkve->kve_vn_fileid, >kve_vn_fileid);
+__put_user(hkve->kve_vn_fsid_freebsd11, >kve_vn_fsid_freebsd11);
+__put_user(hkve->kve_vn_fsid, >kve_vn_fsid);
+__put_user(hkve->kve_flags, >kve_flags);
+__put_user(hkve->kve_resident, >kve_resident);
+__put_user(hkve->kve_private_resident, >kve_private_resident);
+__put_user(hkve->kve_protection, >kve_protection);
+__put_user(hkve->kve_ref_count, >kve_ref_count);
+__put_user(hkve->kve_shadow_count, >kve_shadow_count);
+__put_user(hkve->kve_vn_type, >kve_vn_type);
+__put_user(hkve->kve_vn_size, >kve_vn_size);
+__put_user(hkve->kve_vn_rdev_freebsd11, >kve_vn_rdev_freebsd11);
+__put_user(hkve->kve_vn_rdev, >kve_vn_rdev);
+__put_user(hkve->kve_vn_mode, >kve_vn_mode);
+__put_user(hkve->kve_status, >kve_status);
+strncpy(tkve->kve_path, hkve->kve_path, sizeof(tkve->kve_path));
+}
+
+abi_long
+do_sysctl_kern_proc_vmmap(int pid, size_t olen,
+struct target_kinfo_vmentry *tkve, size_t *tlen)
+{
+abi_long ret;
+int mib[4], sz;
+size_t len;
+char *buf, *bp, *eb, *tp;
+struct kinfo_vmentry *kve, kvme;
+struct target_kinfo_vmentry target_kvme;
+
+if (tlen == NULL) {
+return -TARGET_EINVAL;
+}
+
+len = 0;
+mib[0] = CTL_KERN;
+mib[1] = KERN_PROC;
+mib[2] = KERN_PROC_VMMAP;
+mib[3] = pid;
+
+ret = get_errno(sysctl(mib, 4, NULL, , NULL, 0));
+if (is_error(ret)) {
+return ret;
+}
+if (tkve == NULL) {
+*tlen = len;
+return ret;
+}
+len = len * 4 / 3;
+buf = g_malloc(len);
+if (buf == NULL) {
+return -TARGET_ENOMEM;
+}
+
+/*
+ * Count the number of records.
+ *
+ * Given that the kinfo_file information returned by
+ * the kernel may be differents sizes per record we have
+ * to read it in and count the variable length records
+ * by walking them.
+ */
+ret = get_errno(sysctl(mib, 4, buf, , NULL, 0));
+if (is_error(ret)) {
+g_free(buf);
+return ret;
+}
+*tlen = len;
+bp = buf;
+eb = buf + len;
+while (bp < eb) {
+kve = (struct kinfo_vmentry *)(uintptr_t)bp;
+bp += kve->kve_structsize;
+}
+if (olen < *tlen) {
+g_free(buf);
+return -TARGET_EINVAL;
+}
+
+/*
+ * Unpack the records from the kernel into full length records
+ * and byte swap, if needed.
+ */
+bp = buf;
+eb = buf + len;
+tp = (char *)tkve;
+while (bp < eb) {
+kve = (struct kinfo_vmentry *)(uintptr_t)bp;
+sz = kve->kve_structsize;
+/* Copy/expand into a zeroed buffer */
+memset(, 0, sizeof(kvme));
+memcpy(, kve, sz);
+/* Byte swap and copy into a target aligned buffer. */
+host_to_target_kinfo_vmentry(_kvme, );
+/* Copy target buffer to user buffer, packed. */
+memcpy(tp, _kvme, sz);
+/* Advance to next packed record. */
+bp += sz;
+/* Advance to next packed, target record. */
+tp += sz;
+}
+
+g_free(buf);
+return ret;
+}
+
 /*
  * This uses the undocumented oidfmt interface to find the kind of a requested
  * sysctl, see /sys/kern/kern_sysctl.c:sysctl_sysctl_oidfmt() (compare to
diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h
index 5926bdcc101..aed0d481cba 100644
--- a/bsd-user/qemu.h
+++ b/bsd-user/qemu.h
@@ -260,10 +260,13 @@ int host_to_target_errno(int err);
 /* os-sys.c */
 struct target_kinfo_proc;
 struct target_kinfo_file;
+struct target_kinfo_vmentry;
 abi_long do_sysctl_kern_getprocs(int op, int arg, size_t olen,
 struct target_kinfo_proc *tki, size_t *tlen);
 abi_long do_sysctl_kern_proc_filedesc(int pid, size_t olen,
 struct target_kinfo_file *tkif, size_t *tlen);
+abi_long do_sysctl_kern_proc_vmmap(int pid, size_t olen,
+struct target_kinfo_vmentry *tkve, size_t *tlen);
 abi_long do_freebsd_sysctl(CPUArchState *env, abi_ulong namep, int32_t namelen,
 abi_ulong 

[PATCH 00/16] bsd-user 2023 Q2 first batch

[Warner Losh]

This series is a number of misc cleanups.

First, this replaces my plans to remove netbsd and openbsd code entirely. I've
been in contact with the NetBSD folks that would like to make things work. The
plan is that I'll not remove it in qemu-project, and restore them in bsd-user
fork. These changes clean up some of the mess that's here: I've moved the bits
that make sense here, and removed the ones that don't (but upstream I've moved
them when it makes sense). My intention is to work with the NetBSD folks (and
OpenBSD too if they want) to cope with the structural issues I'm aware of in
bsd-user fork. Future contributions should go via that route at a rate of
contributions (I have little time to do the work, but will commit to finding
time to do the coordination and review work).

Next I've #ifdef'd some mmap handling based on certain flags being defined or
not. This was something I'd removed before, and were in what Taylor sent me, so
I've restored the relevant ones. The rest of the patch that Taylor sent me
conflicts with bsd-user and needs some work to get it in upstream. I removed a
few unused mmap defines as well. And I cleanup mmap.c to remove gratuitous
differences and pass checkpatch.pl.

Next, I've made unimplmeneted system calls generate SIGSYS. For the moment, this
is the best we should do since so much is unimplemented and as things get
implemented this will allow controlled testing of code to ensure it doesn't
silently succeed, giving the impression things are working when they aren't. I
also add SIGSYS to the uncaught coredump signal list, to match FreeBSD's
behavior. I only do this on arm, though, because the signal implementation on
x86 is incomplete (even upstream) and I didn't want to take chances.

Finally, I've included the core dump code. There's about 600 lines of sysctl
support that I've included as separate commits of ~150 lines each (and
incidentlaly, added the translation to os-sys.c for those bits). The core dump
code itself is largely copied from linux-user/elfload.c by sson (so he gets the
author credit). I moved it to elfcore.c when I was upstremaing in the past and
upstreamed a stub. One of the patches in this series replaces elfcore.c and is
1300 lines long. It's not easily sliced up into smaller bits that compile, but
I'm open to suggestions. It's known to "work" in the sense that it will generate
core files that gdb can read and intelligently parse.

This patch series is for after 8.0 is done, but before any GSoC projects start,
and will be independent of any GSoC contribution tasks.

Stacey Son (6):
  bsd-user: h2g_rusage
  bsd-user: Implmenet do_sysctl_kern_getprocs
  bsd-user: Implement do_sysctl_kern_proc_filedesc
  bsd-user: Implement do_sysctl_kern_proc_vmmap
  bsd-user: Implement sysctl kern.proc, except kern.proc.full_path
  bsd-user: Implment core dumps

Warner Losh (10):
  bsd-user: Make print_* public
  bsd-user: Ifdef a few MAP_ constants for NetBSD
  bsd-user: Cleanup style.
  bsd-user: Move system FreeBSD call table to freebsd/os-syscall.c
  bsd-user: Remove NetBSD specific syscall printing
  bsd-user: Remove OpenBSD specific syscall printing
  bsd-user: Move system call include to os-syscall.h
  bsd-user: Remove useless mmap definitions
  bsd-user: Add SIGSYS to core dump signals.
  bsd-user: Implement SIGSYS on arm

 bsd-user/arm/target_arch_cpu.h |8 +
 bsd-user/bsd-proc.c|   48 ++
 bsd-user/elfcore.c | 1318 +++-
 bsd-user/freebsd/os-sys.c  |  508 +++-
 bsd-user/freebsd/os-syscall.c  |   19 +
 bsd-user/freebsd/os-syscall.h  |   21 +
 bsd-user/meson.build   |1 +
 bsd-user/mmap.c|  101 ++-
 bsd-user/netbsd/os-syscall.h   |   16 +
 bsd-user/openbsd/os-syscall.h  |   16 +
 bsd-user/qemu-bsd.h|   30 +
 bsd-user/qemu.h|   44 +-
 bsd-user/signal.c  |   13 +-
 bsd-user/strace.c  |   88 +--
 bsd-user/syscall_defs.h|   69 +-
 15 files changed, 2106 insertions(+), 194 deletions(-)
 create mode 100644 bsd-user/bsd-proc.c
 create mode 100644 bsd-user/freebsd/os-syscall.h
 create mode 100644 bsd-user/netbsd/os-syscall.h
 create mode 100644 bsd-user/openbsd/os-syscall.h
 create mode 100644 bsd-user/qemu-bsd.h

-- 
2.40.0

[PATCH 07/16] bsd-user: Move system call include to os-syscall.h

[Warner Losh]

Move the include of the system calls to os-syscall.h. Include that from
syscall_defs.h. Use target_time_t and target_suseconds_t instead of the
variant that has _freebsd_ in the name. Define these for OpenBSD and
NetBSD based on comments in the file.

Signed-off-by: Warner Losh 
---
 bsd-user/freebsd/os-syscall.h | 21 +
 bsd-user/netbsd/os-syscall.h  | 16 
 bsd-user/openbsd/os-syscall.h | 16 
 bsd-user/syscall_defs.h   | 33 -
 4 files changed, 57 insertions(+), 29 deletions(-)
 create mode 100644 bsd-user/freebsd/os-syscall.h
 create mode 100644 bsd-user/netbsd/os-syscall.h
 create mode 100644 bsd-user/openbsd/os-syscall.h

diff --git a/bsd-user/freebsd/os-syscall.h b/bsd-user/freebsd/os-syscall.h
new file mode 100644
index 000..1f2c0acb1c5
--- /dev/null
+++ b/bsd-user/freebsd/os-syscall.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2023 Warner Losh 
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * OS-Specific portion of syscall_defs.h
+ */
+
+#include "freebsd/syscall_nr.h"
+
+/*
+ * FreeBSD uses a 64bits time_t except on i386 so we have to add a special case
+ * here.
+ */
+#if (!defined(TARGET_I386))
+typedef int64_t target_time_t;
+#else
+typedef int32_t target_time_t;
+#endif
+
+typedef abi_long target_suseconds_t;
diff --git a/bsd-user/netbsd/os-syscall.h b/bsd-user/netbsd/os-syscall.h
new file mode 100644
index 000..7507350d8d2
--- /dev/null
+++ b/bsd-user/netbsd/os-syscall.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2023 Warner Losh 
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * OS-Specific portion of syscall_defs.h
+ */
+
+#include "netbsd/syscall_nr.h"
+
+/*
+ * time_t seems to be very inconsistly defined for the different *BSD's...
+ *
+ * NetBSD always uses int64_t.
+ */
+typedef int64_t target_time_t;
diff --git a/bsd-user/openbsd/os-syscall.h b/bsd-user/openbsd/os-syscall.h
new file mode 100644
index 000..191a76fa935
--- /dev/null
+++ b/bsd-user/openbsd/os-syscall.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2023 Warner Losh 
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * OS-Specific portion of syscall_defs.h
+ */
+
+#include "openbsd/syscall_nr.h"
+
+/*
+ * time_t seems to be very inconsistly defined for the different *BSD's...
+ *
+ * OpenBSD always uses int.
+ */
+typedef int target_time_t;
diff --git a/bsd-user/syscall_defs.h b/bsd-user/syscall_defs.h
index b6d113d24a7..489d3a2e292 100644
--- a/bsd-user/syscall_defs.h
+++ b/bsd-user/syscall_defs.h
@@ -25,30 +25,7 @@
 
 #include "errno_defs.h"
 
-#include "freebsd/syscall_nr.h"
-#include "netbsd/syscall_nr.h"
-#include "openbsd/syscall_nr.h"
-
-/*
- * machine/_types.h
- * or x86/_types.h
- */
-
-/*
- * time_t seems to be very inconsistly defined for the different *BSD's...
- *
- * FreeBSD uses a 64bits time_t except on i386
- * so we have to add a special case here.
- *
- * On NetBSD time_t is always defined as an int64_t.  On OpenBSD time_t
- * is always defined as an int.
- *
- */
-#if (!defined(TARGET_I386))
-typedef int64_t target_freebsd_time_t;
-#else
-typedef int32_t target_freebsd_time_t;
-#endif
+#include "os-syscall.h"
 
 struct target_iovec {
 abi_long iov_base;   /* Starting address */
@@ -98,11 +75,9 @@ struct target_iovec {
  * sys/timex.h
  */
 
-typedef abi_long target_freebsd_suseconds_t;
-
 /* compare to sys/timespec.h */
 struct target_freebsd_timespec {
-target_freebsd_time_t   tv_sec; /* seconds */
+target_time_t   tv_sec; /* seconds */
 abi_longtv_nsec;/* and nanoseconds */
 #if !defined(TARGET_I386) && TARGET_ABI_BITS == 32
 abi_long _pad;
@@ -120,8 +95,8 @@ struct target_freebsd__umtx_time {
 };
 
 struct target_freebsd_timeval {
-target_freebsd_time_t   tv_sec; /* seconds */
-target_freebsd_suseconds_t  tv_usec;/* and microseconds */
+target_time_t   tv_sec; /* seconds */
+target_suseconds_t  tv_usec;/* and microseconds */
 #if !defined(TARGET_I386) && TARGET_ABI_BITS == 32
 abi_long _pad;
 #endif
-- 
2.40.0

[PATCH 16/16] bsd-user: Implement SIGSYS on arm

[Warner Losh]

When a system call returns ENOSYS, send a SIGSYS to the process (to
generate a core dump).

Signed-off-by: Warner Losh 
---
 bsd-user/arm/target_arch_cpu.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/bsd-user/arm/target_arch_cpu.h b/bsd-user/arm/target_arch_cpu.h
index 517d0087644..c4b21fef713 100644
--- a/bsd-user/arm/target_arch_cpu.h
+++ b/bsd-user/arm/target_arch_cpu.h
@@ -127,6 +127,14 @@ static inline void target_cpu_loop(CPUARMState *env)
 env->regs[15] -= env->thumb ? 2 : 4;
 break;
 }
+/*
+ * Emulate BSD's sigsys behavior on unimplemented system calls.
+ * XXX may need to gate this somehow or arrange for sigsys to 
be
+ * masked in some use cases.
+ */
+if (ret == -TARGET_ENOSYS) {
+force_sig_fault(TARGET_SIGSYS, SI_KERNEL, env->regs[15]);
+}
 if ((unsigned int)ret >= (unsigned int)(-515)) {
 ret = -ret;
 cpsr_write(env, CPSR_C, CPSR_C, CPSRWriteByInstr);
-- 
2.40.0

[PATCH 08/16] bsd-user: Remove useless mmap definitions

[Warner Losh]

On BSD, all architectures have the same mmap flags. Since we don't
translate the flags, we don't need these defines here. We can't
cross-run different BSD binaries.

Signed-off-by: Warner Losh 
---
 bsd-user/syscall_defs.h | 36 
 1 file changed, 36 deletions(-)

diff --git a/bsd-user/syscall_defs.h b/bsd-user/syscall_defs.h
index 489d3a2e292..0604e96973e 100644
--- a/bsd-user/syscall_defs.h
+++ b/bsd-user/syscall_defs.h
@@ -32,42 +32,6 @@ struct target_iovec {
 abi_long iov_len;   /* Number of bytes */
 };
 
-/*
- *  sys/mman.h
- */
-#define TARGET_FREEBSD_MAP_RESERVED0080 0x0080  /* previously misimplemented */
-/* MAP_INHERIT */
-#define TARGET_FREEBSD_MAP_RESERVED0100 0x0100  /* previously unimplemented */
-/* MAP_NOEXTEND */
-#define TARGET_FREEBSD_MAP_STACK0x0400  /* region grows down, like a */
-/* stack */
-#define TARGET_FREEBSD_MAP_NOSYNC   0x0800  /* page to but do not sync */
-/* underlying file */
-
-#define TARGET_FREEBSD_MAP_FLAGMASK 0x1ff7
-
-#define TARGET_NETBSD_MAP_INHERIT   0x0080  /* region is retained after */
-/* exec */
-#define TARGET_NETBSD_MAP_TRYFIXED  0x0400  /* attempt hint address, even 
*/
-/* within break */
-#define TARGET_NETBSD_MAP_WIRED 0x0800  /* mlock() mapping when it is 
*/
-/* established */
-
-#define TARGET_NETBSD_MAP_STACK 0x2000  /* allocated from memory, */
-/* swap space (stack) */
-
-#define TARGET_NETBSD_MAP_FLAGMASK  0x3ff7
-
-#define TARGET_OPENBSD_MAP_INHERIT  0x0080  /* region is retained after */
-/* exec */
-#define TARGET_OPENBSD_MAP_NOEXTEND 0x0100  /* for MAP_FILE, don't change 
*/
-/* file size */
-#define TARGET_OPENBSD_MAP_TRYFIXED 0x0400  /* attempt hint address, */
-/* even within heap */
-
-#define TARGET_OPENBSD_MAP_FLAGMASK 0x17f7
-
-/* XXX */
 #define TARGET_BSD_MAP_FLAGMASK 0x3ff7
 
 /*
-- 
2.40.0

[PATCH 13/16] bsd-user: Implement sysctl kern.proc, except kern.proc.full_path

[Warner Losh]

From: Stacey Son 

Use the recently committed conversion routines to implement all the
kern.proc flavors, except for the full path (the prereqs of which aren't
yet in qemu-project's master branch).

Signed-off-by: Stacey Son 
Signed-off-by: Warner Losh 
---
 bsd-user/freebsd/os-sys.c | 35 +++
 1 file changed, 35 insertions(+)

diff --git a/bsd-user/freebsd/os-sys.c b/bsd-user/freebsd/os-sys.c
index 418358adc1e..3772cf500ba 100644
--- a/bsd-user/freebsd/os-sys.c
+++ b/bsd-user/freebsd/os-sys.c
@@ -753,6 +753,41 @@ static abi_long do_freebsd_sysctl_oid(CPUArchState *env, 
int32_t *snamep,
 ret = 0;
 goto out;
 
+case KERN_PROC:
+switch (snamep[2]) {
+case KERN_PROC_ALL:
+case KERN_PROC_PROC:
+case KERN_PROC_PID:
+case KERN_PROC_PID | KERN_PROC_INC_THREAD:
+case KERN_PROC_PGRP:
+case KERN_PROC_PGRP | KERN_PROC_INC_THREAD:
+case KERN_PROC_SESSION:
+case KERN_PROC_SESSION | KERN_PROC_INC_THREAD:
+case KERN_PROC_TTY:
+case KERN_PROC_TTY | KERN_PROC_INC_THREAD:
+case KERN_PROC_UID:
+case KERN_PROC_UID | KERN_PROC_INC_THREAD:
+case KERN_PROC_RUID:
+case KERN_PROC_RUID | KERN_PROC_INC_THREAD:
+ret = do_sysctl_kern_getprocs(snamep[2], snamep[3], oldlen,
+  holdp, );
+goto out;
+
+case KERN_PROC_FILEDESC:
+ret = do_sysctl_kern_proc_filedesc(snamep[3], oldlen, holdp,
+   );
+goto out;
+
+case KERN_PROC_VMMAP:
+ret = do_sysctl_kern_proc_vmmap(snamep[3], oldlen, holdp,
+);
+goto out;
+
+default:
+break;
+}
+break;
+
 default:
 break;
 }
-- 
2.40.0

[PATCH 06/16] bsd-user: Remove OpenBSD specific syscall printing

[Warner Losh]

Nothing calls these routines now. In the bsd-user fork, though, they've
moved to openbsd/os-syscall.c, but those aren't ready for upstreaming.

Signed-off-by: Warner Losh 
---
 bsd-user/qemu.h   |  5 -
 bsd-user/strace.c | 25 -
 2 files changed, 30 deletions(-)

diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h
index cee02d2a0ea..49468734d44 100644
--- a/bsd-user/qemu.h
+++ b/bsd-user/qemu.h
@@ -196,11 +196,6 @@ struct syscallname {
 void (*result)(const struct syscallname *, abi_long);
 };
 
-void
-print_openbsd_syscall(int num,
-  abi_long arg1, abi_long arg2, abi_long arg3,
-  abi_long arg4, abi_long arg5, abi_long arg6);
-void print_openbsd_syscall_ret(int num, abi_long ret);
 void print_execve(const struct syscallname *name, abi_long arg1,
   abi_long arg2, abi_long arg3, abi_long arg4,
   abi_long arg5, abi_long arg6);
diff --git a/bsd-user/strace.c b/bsd-user/strace.c
index 8e76caa3c3f..b827acb2477 100644
--- a/bsd-user/strace.c
+++ b/bsd-user/strace.c
@@ -142,14 +142,6 @@ void print_syscall_ret_addr(const struct syscallname 
*name, abi_long ret)
 }
 }
 
-/*
- * An array of all of the syscalls we know about
- */
-
-static const struct syscallname openbsd_scnames[] = {
-#include "openbsd/strace.list"
-};
-
 void print_syscall(int num, const struct syscallname *scnames,
unsigned int nscnames, abi_long arg1, abi_long arg2,
abi_long arg3, abi_long arg4, abi_long arg5, abi_long arg6)
@@ -203,23 +195,6 @@ void print_syscall_ret(int num, abi_long ret, const struct 
syscallname *scnames,
 }
 }
 
-/*
- * The public interface to this module.
- */
-void print_openbsd_syscall(int num, abi_long arg1, abi_long arg2, abi_long 
arg3,
-abi_long arg4, abi_long arg5, abi_long arg6)
-{
-
-print_syscall(num, openbsd_scnames, ARRAY_SIZE(openbsd_scnames), arg1, 
arg2,
-arg3, arg4, arg5, arg6);
-}
-
-void print_openbsd_syscall_ret(int num, abi_long ret)
-{
-
-print_syscall_ret(num, ret, openbsd_scnames, ARRAY_SIZE(openbsd_scnames));
-}
-
 static void
 print_signal(abi_ulong arg, int last)
 {
-- 
2.40.0

[PATCH 09/16] bsd-user: h2g_rusage

[Warner Losh]

From: Stacey Son 

Converts host's rusage to the guest's rusage.

Signed-off-by: Stacey Son 
Signed-off-by: Warner Losh 
---
 bsd-user/bsd-proc.c  | 48 
 bsd-user/meson.build |  1 +
 bsd-user/qemu-bsd.h  | 30 +++
 3 files changed, 79 insertions(+)
 create mode 100644 bsd-user/bsd-proc.c
 create mode 100644 bsd-user/qemu-bsd.h

diff --git a/bsd-user/bsd-proc.c b/bsd-user/bsd-proc.c
new file mode 100644
index 000..e64eb958947
--- /dev/null
+++ b/bsd-user/bsd-proc.c
@@ -0,0 +1,48 @@
+/*
+ *  BSD process related system call helpers
+ *
+ *  Copyright (c) 2013-14 Stacey D. Son
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see .
+ */
+#include "qemu/osdep.h"
+
+#include "qemu.h"
+#include "qemu-bsd.h"
+#include "signal-common.h"
+
+void h2g_rusage(const struct rusage *rusage,
+struct target_freebsd_rusage *target_rusage)
+{
+__put_user(rusage->ru_utime.tv_sec, _rusage->ru_utime.tv_sec);
+__put_user(rusage->ru_utime.tv_usec, _rusage->ru_utime.tv_usec);
+
+__put_user(rusage->ru_stime.tv_sec, _rusage->ru_stime.tv_sec);
+__put_user(rusage->ru_stime.tv_usec, _rusage->ru_stime.tv_usec);
+
+__put_user(rusage->ru_maxrss, _rusage->ru_maxrss);
+__put_user(rusage->ru_idrss, _rusage->ru_idrss);
+__put_user(rusage->ru_idrss, _rusage->ru_idrss);
+__put_user(rusage->ru_isrss, _rusage->ru_isrss);
+__put_user(rusage->ru_minflt, _rusage->ru_minflt);
+__put_user(rusage->ru_majflt, _rusage->ru_majflt);
+__put_user(rusage->ru_nswap, _rusage->ru_nswap);
+__put_user(rusage->ru_inblock, _rusage->ru_inblock);
+__put_user(rusage->ru_oublock, _rusage->ru_oublock);
+__put_user(rusage->ru_msgsnd, _rusage->ru_msgsnd);
+__put_user(rusage->ru_msgrcv, _rusage->ru_msgrcv);
+__put_user(rusage->ru_nsignals, _rusage->ru_nsignals);
+__put_user(rusage->ru_nvcsw, _rusage->ru_nvcsw);
+__put_user(rusage->ru_nivcsw, _rusage->ru_nivcsw);
+}
diff --git a/bsd-user/meson.build b/bsd-user/meson.build
index 5243122fc56..7d1b4de78b1 100644
--- a/bsd-user/meson.build
+++ b/bsd-user/meson.build
@@ -8,6 +8,7 @@ common_user_inc += include_directories('include')
 
 bsd_user_ss.add(files(
   'bsdload.c',
+  'bsd-proc.c',
   'elfload.c',
   'main.c',
   'mmap.c',
diff --git a/bsd-user/qemu-bsd.h b/bsd-user/qemu-bsd.h
new file mode 100644
index 000..96e7f34b27c
--- /dev/null
+++ b/bsd-user/qemu-bsd.h
@@ -0,0 +1,30 @@
+/*
+ *  BSD conversion extern declarations
+ *
+ *  Copyright (c) 2013 Stacey D. Son
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see .
+ */
+
+#ifndef QEMU_BSD_H
+#define QEMU_BSD_H
+
+#include 
+#include 
+
+/* bsd-proc.c */
+void h2g_rusage(const struct rusage *rusage,
+struct target_freebsd_rusage *target_rusage);
+
+#endif /* QEMU_BSD_H */
-- 
2.40.0

[PATCH 01/16] bsd-user: Make print_* public

[Warner Losh]

Make these functions public. Due to coming restructuring, we'll need to
call these from *bsd/os-syscall.c. Add declarations to qemu.h.

Signed-off-by: Warner Losh 
---
 bsd-user/qemu.h   | 20 
 bsd-user/strace.c | 29 +
 2 files changed, 33 insertions(+), 16 deletions(-)

diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h
index 41d84e0b81b..22e16816a9e 100644
--- a/bsd-user/qemu.h
+++ b/bsd-user/qemu.h
@@ -211,6 +211,26 @@ print_openbsd_syscall(int num,
   abi_long arg1, abi_long arg2, abi_long arg3,
   abi_long arg4, abi_long arg5, abi_long arg6);
 void print_openbsd_syscall_ret(int num, abi_long ret);
+void print_execve(const struct syscallname *name, abi_long arg1,
+  abi_long arg2, abi_long arg3, abi_long arg4,
+  abi_long arg5, abi_long arg6);
+void print_ioctl(const struct syscallname *name,
+ abi_long arg1, abi_long arg2, abi_long arg3,
+ abi_long arg4, abi_long arg5, abi_long arg6);
+void print_sysarch(const struct syscallname *name, abi_long arg1,
+   abi_long arg2, abi_long arg3, abi_long arg4,
+   abi_long arg5, abi_long arg6);
+void print_sysctl(const struct syscallname *name, abi_long arg1,
+  abi_long arg2, abi_long arg3, abi_long arg4,
+  abi_long arg5, abi_long arg6);
+void print_syscall(int num, const struct syscallname *scnames,
+   unsigned int nscnames, abi_long arg1, abi_long arg2,
+   abi_long arg3, abi_long arg4, abi_long arg5,
+   abi_long arg6);
+void print_syscall_ret(int num, abi_long ret,
+   const struct syscallname *scnames,
+   unsigned int nscnames);
+void print_syscall_ret_addr(const struct syscallname *name, abi_long ret);
 /**
  * print_taken_signal:
  * @target_signum: target signal being taken
diff --git a/bsd-user/strace.c b/bsd-user/strace.c
index 96499751eb0..e45909b8688 100644
--- a/bsd-user/strace.c
+++ b/bsd-user/strace.c
@@ -49,7 +49,7 @@ print_raw_param(const char *fmt, abi_long param, int last)
 gemu_log(format, param);
 }
 
-static void print_sysctl(const struct syscallname *name, abi_long arg1,
+void print_sysctl(const struct syscallname *name, abi_long arg1,
 abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5,
 abi_long arg6)
 {
@@ -71,9 +71,8 @@ static void print_sysctl(const struct syscallname *name, 
abi_long arg1,
 (uint32_t)arg2, arg3, arg4, arg5, arg6);
 }
 
-static void print_execve(const struct syscallname *name, abi_long arg1,
-abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5,
-abi_long arg6)
+void print_execve(const struct syscallname *name, abi_long arg1, abi_long arg2,
+  abi_long arg3, abi_long arg4, abi_long arg5, abi_long arg6)
 {
 abi_ulong arg_ptr_addr;
 char *s;
@@ -105,9 +104,8 @@ static void print_execve(const struct syscallname *name, 
abi_long arg1,
 gemu_log("NULL})");
 }
 
-static void print_ioctl(const struct syscallname *name,
-abi_long arg1, abi_long arg2, abi_long arg3, abi_long arg4,
-abi_long arg5, abi_long arg6)
+void print_ioctl(const struct syscallname *name, abi_long arg1, abi_long arg2,
+ abi_long arg3, abi_long arg4, abi_long arg5, abi_long arg6)
 {
 /* Decode the ioctl request */
 gemu_log("%s(%d, 0x%0lx { IO%s%s GRP:0x%x('%c') CMD:%d LEN:%d }, 0x"
@@ -124,9 +122,8 @@ static void print_ioctl(const struct syscallname *name,
 arg3);
 }
 
-static void print_sysarch(const struct syscallname *name, abi_long arg1,
-abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5,
-abi_long arg6)
+void print_sysarch(const struct syscallname *name, abi_long arg1, abi_long 
arg2,
+   abi_long arg3, abi_long arg4, abi_long arg5, abi_long arg6)
 {
 /* This is os dependent. */
 do_os_print_sysarch(name, arg1, arg2, arg3, arg4, arg5, arg6);
@@ -136,7 +133,7 @@ static void print_sysarch(const struct syscallname *name, 
abi_long arg1,
  * Variants for the return value output function
  */
 
-static void print_syscall_ret_addr(const struct syscallname *name, abi_long 
ret)
+void print_syscall_ret_addr(const struct syscallname *name, abi_long ret)
 {
 if (ret == -1) {
 gemu_log(" = -1 errno=%d (%s)\n", errno, strerror(errno));
@@ -159,9 +156,9 @@ static const struct syscallname openbsd_scnames[] = {
 #include "openbsd/strace.list"
 };
 
-static void print_syscall(int num, const struct syscallname *scnames,
-unsigned int nscnames, abi_long arg1, abi_long arg2, abi_long arg3,
-abi_long arg4, abi_long arg5, abi_long arg6)
+void print_syscall(int num, const struct syscallname *scnames,
+   unsigned int nscnames, abi_long arg1, abi_long arg2,
+   abi_long arg3, abi_long arg4, abi_long arg5, abi_long arg6)
 {
 

[PATCH 03/16] bsd-user: Cleanup style.

[Warner Losh]

The only diffs between bsd-user fork and qemu upstream is style. Make
mmap.c pass checkpatch.pl.

Signed-off-by: Warner Losh 
---
 bsd-user/mmap.c | 91 -
 1 file changed, 60 insertions(+), 31 deletions(-)

diff --git a/bsd-user/mmap.c b/bsd-user/mmap.c
index f732a6f6f2b..5f60efb3c5d 100644
--- a/bsd-user/mmap.c
+++ b/bsd-user/mmap.c
@@ -45,17 +45,19 @@ bool have_mmap_lock(void)
 /* Grab lock to make sure things are in a consistent state after fork().  */
 void mmap_fork_start(void)
 {
-if (mmap_lock_count)
+if (mmap_lock_count) {
 abort();
+}
 pthread_mutex_lock(_mutex);
 }
 
 void mmap_fork_end(int child)
 {
-if (child)
+if (child) {
 pthread_mutex_init(_mutex, NULL);
-else
+} else {
 pthread_mutex_unlock(_mutex);
+}
 }
 
 /* NOTE: all the constants are the HOST ones, but addresses are target. */
@@ -69,15 +71,18 @@ int target_mprotect(abi_ulong start, abi_ulong len, int 
prot)
   prot & PROT_READ ? 'r' : '-',
   prot & PROT_WRITE ? 'w' : '-',
   prot & PROT_EXEC ? 'x' : '-');
-if ((start & ~TARGET_PAGE_MASK) != 0)
+if ((start & ~TARGET_PAGE_MASK) != 0) {
 return -EINVAL;
+}
 len = TARGET_PAGE_ALIGN(len);
 end = start + len;
-if (end < start)
+if (end < start) {
 return -EINVAL;
+}
 prot &= PROT_READ | PROT_WRITE | PROT_EXEC;
-if (len == 0)
+if (len == 0) {
 return 0;
+}
 
 mmap_lock();
 host_start = start & qemu_host_page_mask;
@@ -96,8 +101,9 @@ int target_mprotect(abi_ulong start, abi_ulong len, int prot)
 }
 ret = mprotect(g2h_untagged(host_start),
qemu_host_page_size, prot1 & PAGE_BITS);
-if (ret != 0)
+if (ret != 0) {
 goto error;
+}
 host_start += qemu_host_page_size;
 }
 if (end < host_end) {
@@ -107,16 +113,18 @@ int target_mprotect(abi_ulong start, abi_ulong len, int 
prot)
 }
 ret = mprotect(g2h_untagged(host_end - qemu_host_page_size),
qemu_host_page_size, prot1 & PAGE_BITS);
-if (ret != 0)
+if (ret != 0) {
 goto error;
+}
 host_end -= qemu_host_page_size;
 }
 
 /* handle the pages in the middle */
 if (host_start < host_end) {
 ret = mprotect(g2h_untagged(host_start), host_end - host_start, prot);
-if (ret != 0)
+if (ret != 0) {
 goto error;
+}
 }
 page_set_flags(start, start + len, prot | PAGE_VALID);
 mmap_unlock();
@@ -161,31 +169,37 @@ static int mmap_frag(abi_ulong real_start,
 /* get the protection of the target pages outside the mapping */
 prot1 = 0;
 for (addr = real_start; addr < real_end; addr++) {
-if (addr < start || addr >= end)
+if (addr < start || addr >= end) {
 prot1 |= page_get_flags(addr);
+}
 }
 
 if (prot1 == 0) {
 /* no page was there, so we allocate one. See also above. */
 void *p = mmap(host_start, qemu_host_page_size, prot,
flags | ((fd != -1) ? MAP_ANON : 0), -1, 0);
-if (p == MAP_FAILED)
+if (p == MAP_FAILED) {
 return -1;
+}
 prot1 = prot;
 }
 prot1 &= PAGE_BITS;
 
 prot_new = prot | prot1;
 if (fd != -1) {
-/* msync() won't work here, so we return an error if write is
-   possible while it is a shared mapping */
+/*
+ * msync() won't work here, so we return an error if write is
+ * possible while it is a shared mapping
+ */
 if ((flags & TARGET_BSD_MAP_FLAGMASK) == MAP_SHARED &&
-(prot & PROT_WRITE))
+(prot & PROT_WRITE)) {
 return -1;
+}
 
 /* adjust protection to be able to read */
-if (!(prot1 & PROT_WRITE))
+if (!(prot1 & PROT_WRITE)) {
 mprotect(host_start, qemu_host_page_size, prot1 | PROT_WRITE);
+}
 
 /* read the corresponding file data */
 if (pread(fd, g2h_untagged(start), end - start, offset) == -1) {
@@ -193,8 +207,9 @@ static int mmap_frag(abi_ulong real_start,
 }
 
 /* put final protection */
-if (prot_new != (prot1 | PROT_WRITE))
+if (prot_new != (prot1 | PROT_WRITE)) {
 mprotect(host_start, qemu_host_page_size, prot_new);
+}
 } else {
 if (prot_new != prot1) {
 mprotect(host_start, qemu_host_page_size, prot_new);
@@ -554,8 +569,9 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int 
prot,
  */
 p = mmap(g2h_untagged(start), host_len, prot,
  flags | MAP_FIXED | ((fd != -1) ? MAP_ANON : 0), -1, 0);
-if (p == MAP_FAILED)
+if (p == MAP_FAILED) {
 goto fail;
+}
 /* update start so that it points to the file 

[PATCH 10/16] bsd-user: Implmenet do_sysctl_kern_getprocs

[Warner Losh]

From: Stacey Son 

Implement do_sysctl_kern_getprocs to retrieve proc info from the kernel.

Signed-off-by: Stacey Son 
Signed-off-by: Warner Losh 
---
 bsd-user/freebsd/os-sys.c | 165 +-
 bsd-user/qemu.h   |   3 +
 2 files changed, 167 insertions(+), 1 deletion(-)

diff --git a/bsd-user/freebsd/os-sys.c b/bsd-user/freebsd/os-sys.c
index df317065587..d4a6dcc6c2b 100644
--- a/bsd-user/freebsd/os-sys.c
+++ b/bsd-user/freebsd/os-sys.c
@@ -19,9 +19,14 @@
 
 #include "qemu/osdep.h"
 #include "qemu.h"
+#include "qemu-bsd.h"
 #include "target_arch_sysarch.h"
-
+#include "signal-common.h"
+#include 
 #include 
+#include/* For struct kinfo_* */
+
+#include "target_os_user.h"
 
 /*
  * Length for the fixed length types.
@@ -107,6 +112,164 @@ static abi_ulong h2g_ulong_sat(u_long ul)
  */
 #define bsd_get_ncpu() 1
 
+static void
+host_to_target_kinfo_proc(struct target_kinfo_proc *tki, struct kinfo_proc 
*hki)
+{
+int i;
+
+__put_user(sizeof(struct target_kinfo_proc), >ki_structsize);
+__put_user(hki->ki_layout, >ki_layout);
+
+/* Some of these are used as flags (e.g. ki_fd == NULL in procstat). */
+tki->ki_args = tswapal((abi_ulong)(uintptr_t)hki->ki_args);
+tki->ki_paddr = tswapal((abi_ulong)(uintptr_t)hki->ki_paddr);
+tki->ki_addr = tswapal((abi_ulong)(uintptr_t)hki->ki_addr);
+tki->ki_tracep = tswapal((abi_ulong)(uintptr_t)hki->ki_tracep);
+tki->ki_textvp = tswapal((abi_ulong)(uintptr_t)hki->ki_textvp);
+tki->ki_fd = tswapal((abi_ulong)(uintptr_t)hki->ki_fd);
+tki->ki_vmspace = tswapal((abi_ulong)(uintptr_t)hki->ki_vmspace);
+tki->ki_wchan = tswapal((abi_ulong)(uintptr_t)hki->ki_wchan);
+
+__put_user(hki->ki_pid, >ki_pid);
+__put_user(hki->ki_ppid, >ki_ppid);
+__put_user(hki->ki_pgid, >ki_pgid);
+__put_user(hki->ki_tpgid, >ki_tpgid);
+__put_user(hki->ki_sid, >ki_sid);
+__put_user(hki->ki_tsid, >ki_tsid);
+__put_user(hki->ki_jobc, >ki_jobc);
+__put_user(hki->ki_tdev, >ki_tdev);
+
+host_to_target_sigset(>ki_siglist, >ki_siglist);
+host_to_target_sigset(>ki_sigmask, >ki_sigmask);
+host_to_target_sigset(>ki_sigignore, >ki_sigignore);
+host_to_target_sigset(>ki_sigcatch, >ki_sigcatch);
+
+__put_user(hki->ki_uid, >ki_uid);
+__put_user(hki->ki_ruid, >ki_ruid);
+__put_user(hki->ki_svuid, >ki_svuid);
+__put_user(hki->ki_rgid, >ki_rgid);
+__put_user(hki->ki_svgid, >ki_svgid);
+__put_user(hki->ki_ngroups, >ki_ngroups);
+
+for (i=0; i < TARGET_KI_NGROUPS; i++)
+__put_user(hki->ki_groups[i], >ki_groups[i]);
+
+__put_user(hki->ki_size, >ki_size);
+
+__put_user(hki->ki_rssize, >ki_rssize);
+__put_user(hki->ki_swrss, >ki_swrss);
+__put_user(hki->ki_tsize, >ki_tsize);
+__put_user(hki->ki_dsize, >ki_dsize);
+__put_user(hki->ki_ssize, >ki_ssize);
+
+__put_user(hki->ki_xstat, >ki_xstat);
+__put_user(hki->ki_acflag, >ki_acflag);
+
+__put_user(hki->ki_pctcpu, >ki_pctcpu);
+
+__put_user(hki->ki_estcpu, >ki_estcpu);
+__put_user(hki->ki_slptime, >ki_slptime);
+__put_user(hki->ki_swtime, >ki_swtime);
+__put_user(hki->ki_cow, >ki_cow);
+__put_user(hki->ki_runtime, >ki_runtime);
+
+__put_user(hki->ki_start.tv_sec, >ki_start.tv_sec);
+__put_user(hki->ki_start.tv_usec, >ki_start.tv_usec);
+__put_user(hki->ki_childtime.tv_sec, >ki_childtime.tv_sec);
+__put_user(hki->ki_childtime.tv_usec, >ki_childtime.tv_usec);
+
+__put_user(hki->ki_flag, >ki_flag);
+__put_user(hki->ki_kiflag, >ki_kiflag);
+
+__put_user(hki->ki_traceflag, >ki_traceflag);
+__put_user(hki->ki_stat, >ki_stat);
+__put_user(hki->ki_nice, >ki_nice);
+__put_user(hki->ki_lock, >ki_lock);
+__put_user(hki->ki_rqindex, >ki_rqindex);
+__put_user(hki->ki_oncpu_old, >ki_oncpu_old);
+__put_user(hki->ki_lastcpu_old, >ki_lastcpu_old);
+
+strncpy(tki->ki_tdname, hki->ki_tdname, TARGET_TDNAMLEN+1);
+strncpy(tki->ki_wmesg, hki->ki_wmesg, TARGET_WMESGLEN+1);
+strncpy(tki->ki_login, hki->ki_login, TARGET_LOGNAMELEN+1);
+strncpy(tki->ki_lockname, hki->ki_lockname, TARGET_LOCKNAMELEN+1);
+strncpy(tki->ki_comm, hki->ki_comm, TARGET_COMMLEN+1);
+strncpy(tki->ki_emul, hki->ki_emul, TARGET_KI_EMULNAMELEN+1);
+strncpy(tki->ki_loginclass, hki->ki_loginclass, TARGET_LOGINCLASSLEN+1);
+
+__put_user(hki->ki_oncpu, >ki_oncpu);
+__put_user(hki->ki_lastcpu, >ki_lastcpu);
+__put_user(hki->ki_tracer, >ki_tracer);
+__put_user(hki->ki_flag2, >ki_flag2);
+__put_user(hki->ki_fibnum, >ki_fibnum);
+__put_user(hki->ki_cr_flags, >ki_cr_flags);
+__put_user(hki->ki_jid, >ki_jid);
+__put_user(hki->ki_numthreads, >ki_numthreads);
+__put_user(hki->ki_tid, >ki_tid);
+
+memcpy(>ki_pri, >ki_pri, sizeof(struct target_priority));
+
+h2g_rusage(>ki_rusage, >ki_rusage);
+h2g_rusage(>ki_rusage_ch, >ki_rusage_ch);
+
+__put_user(((uintptr_t)hki->ki_pcb), >ki_pcb);
+

[PATCH 15/16] bsd-user: Add SIGSYS to core dump signals.

[Warner Losh]

SIGSYS creates a core by default if uncaught. Follow that here. Sort
with the same order as is in the kernel.

Signed-off-by: Warner Losh 
---
 bsd-user/signal.c | 13 +
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/bsd-user/signal.c b/bsd-user/signal.c
index f4e078ee1da..4301595cc2f 100644
--- a/bsd-user/signal.c
+++ b/bsd-user/signal.c
@@ -330,17 +330,22 @@ int block_signals(void)
 return qatomic_xchg(>signal_pending, 1);
 }
 
-/* Returns 1 if given signal should dump core if not handled. */
+/*
+ * Returns 1 if given signal should dump core if not handled.
+ * Compare with kern_sig.c sigproptbl[].
+ */
 static int core_dump_signal(int sig)
 {
 switch (sig) {
+case TARGET_SIGQUIT:
+case TARGET_SIGILL:
+case TARGET_SIGTRAP:
 case TARGET_SIGABRT:
+case TARGET_SIGEMT:
 case TARGET_SIGFPE:
-case TARGET_SIGILL:
-case TARGET_SIGQUIT:
 case TARGET_SIGSEGV:
-case TARGET_SIGTRAP:
 case TARGET_SIGBUS:
+case TARGET_SIGSYS:
 return 1;
 default:
 return 0;
-- 
2.40.0

[PATCH 05/16] bsd-user: Remove NetBSD specific syscall printing

[Warner Losh]

Nothing calls these routines now. In the bsd-user fork, though, they've
moved to netbsd/os-syscall.c, but those aren't ready for upstreaming.

Signed-off-by: Warner Losh 
---
 bsd-user/qemu.h   |  5 -
 bsd-user/strace.c | 17 -
 2 files changed, 22 deletions(-)

diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h
index c5240938da7..cee02d2a0ea 100644
--- a/bsd-user/qemu.h
+++ b/bsd-user/qemu.h
@@ -196,11 +196,6 @@ struct syscallname {
 void (*result)(const struct syscallname *, abi_long);
 };
 
-void
-print_netbsd_syscall(int num,
- abi_long arg1, abi_long arg2, abi_long arg3,
- abi_long arg4, abi_long arg5, abi_long arg6);
-void print_netbsd_syscall_ret(int num, abi_long ret);
 void
 print_openbsd_syscall(int num,
   abi_long arg1, abi_long arg2, abi_long arg3,
diff --git a/bsd-user/strace.c b/bsd-user/strace.c
index 7d0117fd3cf..8e76caa3c3f 100644
--- a/bsd-user/strace.c
+++ b/bsd-user/strace.c
@@ -146,9 +146,6 @@ void print_syscall_ret_addr(const struct syscallname *name, 
abi_long ret)
  * An array of all of the syscalls we know about
  */
 
-static const struct syscallname netbsd_scnames[] = {
-#include "netbsd/strace.list"
-};
 static const struct syscallname openbsd_scnames[] = {
 #include "openbsd/strace.list"
 };
@@ -209,20 +206,6 @@ void print_syscall_ret(int num, abi_long ret, const struct 
syscallname *scnames,
 /*
  * The public interface to this module.
  */
-void print_netbsd_syscall(int num, abi_long arg1, abi_long arg2, abi_long arg3,
-abi_long arg4, abi_long arg5, abi_long arg6)
-{
-
-print_syscall(num, netbsd_scnames, ARRAY_SIZE(netbsd_scnames),
-  arg1, arg2, arg3, arg4, arg5, arg6);
-}
-
-void print_netbsd_syscall_ret(int num, abi_long ret)
-{
-
-print_syscall_ret(num, ret, netbsd_scnames, ARRAY_SIZE(netbsd_scnames));
-}
-
 void print_openbsd_syscall(int num, abi_long arg1, abi_long arg2, abi_long 
arg3,
 abi_long arg4, abi_long arg5, abi_long arg6)
 {
-- 
2.40.0

[PATCH 14/16] bsd-user: Implment core dumps

[Warner Losh]

From: Stacey Son 

Bring in the code that was originally copied from linxu-user/elfload.c
and moved to elfcore.c. This code then removed the Linux specific bits,
replacing them with FreeBSD specific bits. The commit history for this
is not at all what we'd like (it was done in one go by sson in
227070562fc in one commit, with very few followup tweaks). Since the
original commit, this code has been moved, and updated by sson and ed
slightly. That makes it hard to split into smaller commits.

Signed-off-by: Stacey Son 
Signed-off-by: Ed Schouten 
Signed-off-by: Warner Losh 
---
 bsd-user/elfcore.c | 1318 +++-
 1 file changed, 1315 insertions(+), 3 deletions(-)

diff --git a/bsd-user/elfcore.c b/bsd-user/elfcore.c
index c49d9280e2d..2905f2b8414 100644
--- a/bsd-user/elfcore.c
+++ b/bsd-user/elfcore.c
@@ -1,10 +1,1322 @@
-/* Stubbed out version of core dump support, explicitly in public domain */
+/*
+ *  ELF loading code
+ *
+ *  Copyright (c) 2015 Stacey D. Son
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see .
+ */
+#include "qemu/osdep.h"
 
-static int elf_core_dump(int signr, CPUArchState *env)
+#ifdef USE_ELF_CORE_DUMP
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ELF_NOTE_ROUNDSIZE  4
+#define ELF_MACHINE ELF_ARCH
+
+#define TARGET_NT_PRSTATUS  1   /* Process status. */
+#define TARGET_NT_FPREGSET  2   /* Floating point registers. */
+#define TARGET_NT_PRPSINFO  3   /* Process state info. */
+#define TARGET_NT_THRMISC   7   /* Thread miscellaneous info. 
*/
+#define TARGET_NT_PROCSTAT_PROC 8   /* Procstat proc data. */
+#define TARGET_NT_PROCSTAT_FILES9   /* Procstat files data. */
+#define TARGET_NT_PROCSTAT_VMMAP   10   /* Procstat vmmap data. */
+#define TARGET_NT_PROCSTAT_GROUPS  11   /* Procstat groups data. */
+#define TARGET_NT_PROCSTAT_UMASK   12   /* Procstat umask data. */
+#define TARGET_NT_PROCSTAT_RLIMIT  13   /* Procstat rlimit data. */
+#define TARGET_NT_PROCSTAT_OSREL   14   /* Procstat osreldate data. */
+#define TARGET_NT_PROCSTAT_PSSTRINGS   15   /* Procstat ps_strings data. */
+#define TARGET_NT_PROCSTAT_AUXV16   /* Procstat auxv data. */
+
+/*
+ * Write out ELF coredump.
+ *
+ * See documentation of ELF object file format in:
+ * http://www.caldera.com/developers/devspecs/gabi41.pdf
+ * and sys/kern_imgact_elf.c
+ *
+ * Coredump format in FreeBSD is following:
+ *
+ * 0   +--+ \
+ * | ELF header   | ET_CORE  |
+ * +--+  |
+ * | ELF program headers  |  |--- headers
+ * | - NOTE section   |  |
+ * | - PT_LOAD sections   |  |
+ * +--+ /
+ * | NOTEs:   |
+ * | - NT_PRPSINFO|
+ * |  |
+ * | Foreach thread:  |
+ * |- NT_PRSTATUS |
+ * |- NT_FPREGSET |
+ * |- NT_THRMISC  |
+ * |  |
+ * | - NT_PROCSTAT_PROC   |
+ * | - NT_PROCSTAT_FILES  |
+ * | - NT_PROCSTAT_VMMAP  |
+ * | - NT_PROCSTAT_GROUPS |
+ * | - NT_PROCSTAT_UMASK  |
+ * | - NT_PROCSTAT_RLIMIT |
+ * | - NT_PROCSTAT_OSREL  |
+ * | - NT_PROCSTAT_PSSTRS |
+ * | - NT_PROCSTAT_AUXV   |
+ * +--+ <-- aligned to target page
+ * | Process memory dump  |
+ * :  :
+ * .  .
+ * :  :
+ * |  |
+ * +--+
+ *
+ * Format follows System V format as close as possible.  Current
+ * version limitations are as follows:
+ * - no floating point registers are dumped
+ *
+ * Function returns 0 in case of success, negative errno otherwise.
+ *
+ * TODO: make this work also during runtime: it should be
+ * possible to force coredump from running process and then
+ * continue processing.  For example qemu could set up SIGUSR2
+ * handler (provided that target process haven't registered
+ * handler for that) that does the dump when signal is received.
+ */
+
+#define TARGET_PRFNAMESZ   16   /* Maximum command length saved */
+#define TARGET_PRARGSZ 80   /* Maximum argument bytes saved */
+

[PATCH 02/16] bsd-user: Ifdef a few MAP_ constants for NetBSD

[Warner Losh]

MAP_GUARD, MAP_EXCL, and MAP_NOCORE are FreeBSD only. Add back the
ifdefs that I removed in 36d5d891559f (but only these ifdefs, the
rest of the commit is not reverted).

Signed-off-by: Warner Losh 
---
 bsd-user/mmap.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/bsd-user/mmap.c b/bsd-user/mmap.c
index d6c5a344c9b..f732a6f6f2b 100644
--- a/bsd-user/mmap.c
+++ b/bsd-user/mmap.c
@@ -416,27 +416,33 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int 
prot,
 qemu_log("MAP_ALIGNED(%u) ",
  (flags & MAP_ALIGNMENT_MASK) >> MAP_ALIGNMENT_SHIFT);
 }
+#ifdef MAP_GUARD
 if (flags & MAP_GUARD) {
 qemu_log("MAP_GUARD ");
 }
+#endif
 if (flags & MAP_FIXED) {
 qemu_log("MAP_FIXED ");
 }
 if (flags & MAP_ANON) {
 qemu_log("MAP_ANON ");
 }
+#ifdef MAP_EXCL
 if (flags & MAP_EXCL) {
 qemu_log("MAP_EXCL ");
 }
+#endif
 if (flags & MAP_PRIVATE) {
 qemu_log("MAP_PRIVATE ");
 }
 if (flags & MAP_SHARED) {
 qemu_log("MAP_SHARED ");
 }
+#ifdef MAP_NOCORE
 if (flags & MAP_NOCORE) {
 qemu_log("MAP_NOCORE ");
 }
+#endif
 if (flags & MAP_STACK) {
 qemu_log("MAP_STACK ");
 }
@@ -454,6 +460,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int 
prot,
 goto fail;
 }
 }
+#ifdef MAP_GUARD
 if ((flags & MAP_GUARD) && (prot != PROT_NONE || fd != -1 ||
 offset != 0 || (flags & (MAP_SHARED | MAP_PRIVATE |
 /* MAP_PREFAULT | */ /* MAP_PREFAULT not in mman.h */
@@ -461,6 +468,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int 
prot,
 errno = EINVAL;
 goto fail;
 }
+#endif
 
 if (offset & ~TARGET_PAGE_MASK) {
 errno = EINVAL;
@@ -608,11 +616,13 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int 
prot,
 goto the_end;
 }
 
+#ifdef MAP_EXCL
 /* Reject the mapping if any page within the range is mapped */
 if ((flags & MAP_EXCL) && page_check_range(start, len, 0) < 0) {
 errno = EINVAL;
 goto fail;
 }
+#endif
 
 /* handle the start of the mapping */
 if (start > real_start) {
-- 
2.40.0

[PATCH 04/16] bsd-user: Move system FreeBSD call table to freebsd/os-syscall.c

[Warner Losh]

Move the system call table, and FreeBSD helper routines out of strace.c.
We do not support multiple BSD-types in one binary, so simplify things
by moving it.

Signed-off-by: Warner Losh 
---
 bsd-user/freebsd/os-syscall.c | 19 +++
 bsd-user/qemu.h   |  5 -
 bsd-user/strace.c | 17 -
 3 files changed, 19 insertions(+), 22 deletions(-)

diff --git a/bsd-user/freebsd/os-syscall.c b/bsd-user/freebsd/os-syscall.c
index c8f998ecec1..354a38943e5 100644
--- a/bsd-user/freebsd/os-syscall.c
+++ b/bsd-user/freebsd/os-syscall.c
@@ -517,6 +517,25 @@ static abi_long freebsd_syscall(void *cpu_env, int num, 
abi_long arg1,
 return ret;
 }
 
+static const struct syscallname freebsd_scnames[] = {
+#include "freebsd/strace.list"
+};
+
+static void print_freebsd_syscall(int num, abi_long arg1, abi_long arg2,
+  abi_long arg3, abi_long arg4, abi_long arg5,
+  abi_long arg6)
+{
+
+print_syscall(num, freebsd_scnames, ARRAY_SIZE(freebsd_scnames), arg1, 
arg2,
+arg3, arg4, arg5, arg6);
+}
+
+static void print_freebsd_syscall_ret(int num, abi_long ret)
+{
+
+print_syscall_ret(num, ret, freebsd_scnames, ARRAY_SIZE(freebsd_scnames));
+}
+
 /*
  * do_freebsd_syscall() should always have a single exit point at the end so
  * that actions, such as logging of syscall results, can be performed. This
diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h
index 22e16816a9e..c5240938da7 100644
--- a/bsd-user/qemu.h
+++ b/bsd-user/qemu.h
@@ -196,11 +196,6 @@ struct syscallname {
 void (*result)(const struct syscallname *, abi_long);
 };
 
-void
-print_freebsd_syscall(int num,
-  abi_long arg1, abi_long arg2, abi_long arg3,
-  abi_long arg4, abi_long arg5, abi_long arg6);
-void print_freebsd_syscall_ret(int num, abi_long ret);
 void
 print_netbsd_syscall(int num,
  abi_long arg1, abi_long arg2, abi_long arg3,
diff --git a/bsd-user/strace.c b/bsd-user/strace.c
index e45909b8688..7d0117fd3cf 100644
--- a/bsd-user/strace.c
+++ b/bsd-user/strace.c
@@ -146,9 +146,6 @@ void print_syscall_ret_addr(const struct syscallname *name, 
abi_long ret)
  * An array of all of the syscalls we know about
  */
 
-static const struct syscallname freebsd_scnames[] = {
-#include "freebsd/strace.list"
-};
 static const struct syscallname netbsd_scnames[] = {
 #include "netbsd/strace.list"
 };
@@ -212,20 +209,6 @@ void print_syscall_ret(int num, abi_long ret, const struct 
syscallname *scnames,
 /*
  * The public interface to this module.
  */
-void print_freebsd_syscall(int num, abi_long arg1, abi_long arg2, abi_long 
arg3,
-abi_long arg4, abi_long arg5, abi_long arg6)
-{
-
-print_syscall(num, freebsd_scnames, ARRAY_SIZE(freebsd_scnames), arg1, 
arg2,
-arg3, arg4, arg5, arg6);
-}
-
-void print_freebsd_syscall_ret(int num, abi_long ret)
-{
-
-print_syscall_ret(num, ret, freebsd_scnames, ARRAY_SIZE(freebsd_scnames));
-}
-
 void print_netbsd_syscall(int num, abi_long arg1, abi_long arg2, abi_long arg3,
 abi_long arg4, abi_long arg5, abi_long arg6)
 {
-- 
2.40.0

Re: [PATCH for-8.1] target/sparc: Use tcg_gen_lookup_and_goto_ptr

[Mark Cave-Ayland]

On 05/04/2023 19:59, Richard Henderson wrote:


Signed-off-by: Richard Henderson 
---
  target/sparc/translate.c | 8 
  1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 137bdc5159..47940fd85e 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -322,7 +322,7 @@ static void gen_goto_tb(DisasContext *s, int tb_num,
  /* jump to another page: currently not optimized */
  tcg_gen_movi_tl(cpu_pc, pc);
  tcg_gen_movi_tl(cpu_npc, npc);
-tcg_gen_exit_tb(NULL, 0);
+tcg_gen_lookup_and_goto_ptr();
  }
  }
  
@@ -4153,7 +4153,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)

  /* End TB to notice changed ASI.  */
  save_state(dc);
  gen_op_next_insn();
-tcg_gen_exit_tb(NULL, 0);
+tcg_gen_lookup_and_goto_ptr();
  dc->base.is_jmp = DISAS_NORETURN;
  break;
  case 0x6: /* V9 wrfprs */
@@ -4162,7 +4162,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned 
int insn)
  dc->fprs_dirty = 0;
  save_state(dc);
  gen_op_next_insn();
-tcg_gen_exit_tb(NULL, 0);
+tcg_gen_lookup_and_goto_ptr();
  dc->base.is_jmp = DISAS_NORETURN;
  break;
  case 0xf: /* V9 sir, nop if user */
@@ -5661,7 +5661,7 @@ static void sparc_tr_tb_stop(DisasContextBase *dcbase, 
CPUState *cs)
  tcg_gen_movi_tl(cpu_pc, dc->pc);
  }
  save_npc(dc);
-tcg_gen_exit_tb(NULL, 0);
+tcg_gen_lookup_and_goto_ptr();
  }
  break;


I can certainly give this an R-B, however I'm fairly sure I tried this a couple of 
years back and found that it introduced random hangs on qemu-system-sparc64 :/. Have 
you seen any issues in the relevant avocado tests with this patch applied?



ATB,

Mark.

Re: QEMU stable 7.2.1

[Michael Roth]

On Wed, Apr 05, 2023 at 01:57:20PM -0500, Michael Roth wrote:
> On Wed, Apr 05, 2023 at 05:16:33PM +0300, Michael Tokarev wrote:
> > 05.04.2023 16:58, Michael Roth wrote:
> > > On Wed, Apr 05, 2023 at 02:54:47PM +0300, Michael Tokarev wrote:
> > > > So let it be, with a delay of about a week.
> > > > 
> > > > Since no one from the qemu team replied to my final-release steps, I'm
> > > > making it available on my site instead:
> > > > 
> > > >http://www.corpit.ru/mjt/qemu/qemu-7.2.1.tar.xz
> > > >http://www.corpit.ru/mjt/qemu/qemu-7.2.1.tar.xz.sig - signed with my 
> > > > GPG key
> > > >http://www.corpit.ru/mjt/qemu/qemu-7.2.1.diff - whole difference 
> > > > from 7.2.0.
> > > > 
> > > > The tag (v7.2.1) is in the main qemu repository.
> > > 
> > 
> > For the tarballs, it's definitely better to follow the established practice,
> > I published the generated tarball on my site just as a last-resort, so that
> > it ends up *somewhere*. It should be prepared the same way as other releases
> > has been made, including the .bz2 version.
> > 
> > If that's okay with you, feel free to re-create the tarball from v7.2.1
> > tag, and compress the tarball with whatever compressors usually used by
> > the qemu team.  It's the way to go.
> 
> Ok, sure, I'll go ahead and re-publish 7.2.1 tarball a bit later today.

Re-packaged tarball based on your 7.2.1 tag is now uploaded:

  https://www.qemu.org/download/

-Mike

> 
> We can stick with this approach until you're all set up for uploading.
> 
> -Mike
> 
> > 
> > Thanks,
> > 
> > /mjt
> > 

Re: [RFC PATCH] docs/about/deprecated: Deprecate 32-bit host systems

[Mark Cave-Ayland]

On 04/04/2023 15:00, Thomas Huth wrote:


On 05/02/2023 23.12, Mark Cave-Ayland wrote:

On 30/01/2023 20:45, Alex Bennée wrote:


Daniel P. Berrangé  writes:


On Mon, Jan 30, 2023 at 11:47:02AM +, Peter Maydell wrote:

On Mon, 30 Jan 2023 at 11:44, Thomas Huth  wrote:


Testing 32-bit host OS support takes a lot of precious time during the QEMU
contiguous integration tests, and considering that many OS vendors stopped
shipping 32-bit variants of their OS distributions and most hardware from
the past >10 years is capable of 64-bit


True for x86, not necessarily true for other architectures.
Are you proposing to deprecate x86 32-bit, or all 32-bit?
I'm not entirely sure about whether we're yet at a point where
I'd want to deprecate-and-drop 32-bit arm host support.


Do we have a feeling on which aspects of 32-bit cause us the support
burden ? The boring stuff like compiler errors from mismatched integer
sizes is mostly quick & easy to detect simply through a cross compile.

I vaguely recall someone mentioned problems with atomic ops in the past,
or was it 128-bit ints, caused implications for the codebase ?


Atomic operations on > TARGET_BIT_SIZE and cputlb when
TCG_OVERSIZED_GUEST is set. Also the core TCG code and a bunch of the
backends have TARGET_LONG_BITS > TCG_TARGET_REG_BITS ifdefs peppered
throughout.


I am one of an admittedly small group of people still interested in using KVM-PR on 
ppc32 to boot MacOS, although there is some interest on using 64-bit KVM-PR to run 
super-fast MacOS on modern Talos hardware.


 From my perspective losing the ability to run 64-bit guests on 32-bit hardware 
with TCG wouldn't be an issue, as long as it were still possible to use 
qemu-system-ppc on 32-bit hardware using both TCG and KVM to help debug the 
remaining issues.


  Hi Mark!

Just out of curiosity (since we briefly talked about 32-bit KVM on ppc in today's 
QEMU/KVM call - in the context of whether qemu-system-ppc64 is a proper superset of 
qemu-system-ppc when it comes to building a unified qemu-system binary): What host 
machine are you using for running KVM-PR? And which QEMU machine are you using for 
running macOS? The mac99 or the g3beige machine?


I'm using a G4 Mac Mini for my KVM experiments running Debian ports which is fairly 
up to date e.g. gcc-12 for building QEMU. Both the mac99 and g3beige machines will 
boot up to the OS X 10.2 installer on my current (custom) 5.1 kernel.


Unrelated to KVM: Do you happen to know whether there are any problems when running 
32-bit guests with TCG with the mac99 or g3beige machine while using qemu-system-ppc64 ?


I'm not sure as I don't run qemu-system-ppc64 on a regular basis, but I have heard 
from people in the past who have happily used it to boot 64-bit Linux.


(goes and turns on the Mac Mini)

A quick test this evening shows that latest git master builds qemu-system-ppc and 
runs fine with -accel=kvm on the Mac Mini, however something now asserts with 
-accel=tcg on startup which didn't happen before:



Thread 1 "qemu-system-ppc" received signal SIGSEGV, Segmentation fault.
tcg_tb_alloc (s=0x1) at ../tcg/tcg.c:1025
1025tb = (void *)ROUND_UP((uintptr_t)s->code_gen_ptr, align);
(gdb) bt
#0  0x00ad4148 in tcg_tb_alloc (s=0x1) at ../tcg/tcg.c:1025
#1  0x00ad34c8 in tcg_context_init (max_cpus=1) at ../tcg/tcg.c:959
#2  0x00ad34c8 in tcg_init (tb_size=0, splitwx=0, max_cpus=max_cpus@entry=1) at 
../tcg/tcg.c:1010

#3  0x00b3b784 in tcg_init_machine (ms=) at 
../accel/tcg/tcg-all.c:127
#4  0x008dc784 in accel_init_machine (accel=accel@entry=0x159f8c0, ms=0x1538000) at 
../accel/accel-softmmu.c:39
#5  0x00869184 in do_configure_accelerator (opaque=opaque@entry=0xb2ac, 
opts=opts@entry=0x159f4f0, errp=errp@entry=0x13694cc ) at 
../softmmu/vl.c:2224
#6  0x00d8e13c in qemu_opts_foreach (list=, func=func@entry=0x869010 
, opaque=opaque@entry=0xb2ac, errp=errp@entry=0x13694cc 
)

at ../util/qemu-option.c:1135
#7  0x0086c3b4 in configure_accelerators (progname=) at 
../softmmu/vl.c:2293
#8  0x0086c3b4 in qemu_init (argc=, argv=) at 
../softmmu/vl.c:3561
#9  0x0060acd4 in main (argc=, argv=) at 
../softmmu/main.c:47



Richard, any thoughts on this at all?


ATB,

Mark.

Re: [RFC PATCH 09/10] target/riscv: Restrict KVM-specific fields from ArchCPU

[Daniel Henrique Barboza]

On 4/5/23 13:04, Philippe Mathieu-Daudé wrote:

These fields shouldn't be accessed when KVM is not available.

Signed-off-by: Philippe Mathieu-Daudé 
---
RFC: The migration part is likely invalid...

kvmtimer_needed() is defined in target/riscv/machine.c as

   static bool kvmtimer_needed(void *opaque)
   {
   return kvm_enabled();
   }

which depends on a host feature.



kvm_enabled() can be false even when CONFIG_KVM is true when a KVM capable host
is running a TCG guest, for example. In that case env->kvm_timer_* states exist
but aren't initialized, and shouldn't be migrated.

Thus it's not just a host feature, but a host feature + accel option. I think
this is fine.


---
  target/riscv/cpu.h | 2 ++
  target/riscv/machine.c | 4 
  2 files changed, 6 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 638e47c75a..82939235ab 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -377,12 +377,14 @@ struct CPUArchState {
  hwaddr kernel_addr;
  hwaddr fdt_addr;
  
+#ifdef CONFIG_KVM

  /* kvm timer */
  bool kvm_timer_dirty;
  uint64_t kvm_timer_time;
  uint64_t kvm_timer_compare;
  uint64_t kvm_timer_state;
  uint64_t kvm_timer_frequency;
+#endif /* CONFIG_KVM */
  };
  
  OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)

diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 9c455931d8..e45d564ec3 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -201,10 +201,12 @@ static bool kvmtimer_needed(void *opaque)
  
  static int cpu_post_load(void *opaque, int version_id)

  {
+#ifdef CONFIG_KVM
  RISCVCPU *cpu = opaque;
  CPURISCVState *env = >env;
  
  env->kvm_timer_dirty = true;

+#endif
  return 0;
  }
  
@@ -215,9 +217,11 @@ static const VMStateDescription vmstate_kvmtimer = {

  .needed = kvmtimer_needed,
  .post_load = cpu_post_load,
  .fields = (VMStateField[]) {
+#ifdef CONFIG_KVM
  VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
  VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
  VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
+#endif


Here you're creating an empty 'cpu/kvmtimer' vmstate that won't be migrated 
anyway
because kvmtimer_needed (== kvm_enabled()) will be always false if CONFIG_KVM=n.

I'd say it's better to just get rid of the whole vmstate in this case, but I 
don't
like the precedence of having vmstates being gated by build flags.


Reviewed-by: Daniel Henrique Barboza 




  VMSTATE_END_OF_LIST()
  }
  };

Re: [PATCH v8 2/4] block: introduce zone append write for zoned devices

[Stefan Hajnoczi]

On Tue, Apr 04, 2023 at 11:32:37PM +0800, Sam Li wrote:
> A zone append command is a write operation that specifies the first
> logical block of a zone as the write position. When writing to a zoned
> block device using zone append, the byte offset of the call may point at
> any position within the zone to which the data is being appended. Upon
> completion the device will respond with the position where the data has
> been written in the zone.
> 
> Signed-off-by: Sam Li 
> Reviewed-by: Dmitry Fomichev 
> ---
>  block/block-backend.c | 60 +++
>  block/file-posix.c| 56 +
>  block/io.c| 27 ++
>  block/io_uring.c  |  4 +++
>  block/linux-aio.c |  3 ++
>  block/raw-format.c|  8 +
>  include/block/block-io.h  |  4 +++
>  include/block/block_int-common.h  |  3 ++
>  include/block/raw-aio.h   |  4 ++-
>  include/sysemu/block-backend-io.h |  9 +
>  10 files changed, 171 insertions(+), 7 deletions(-)

Reviewed-by: Stefan Hajnoczi 


signature.asc
Description: PGP signature

Re: [PATCH v8 1/4] file-posix: add tracking of the zone write pointers

[Stefan Hajnoczi]

On Tue, Apr 04, 2023 at 11:32:36PM +0800, Sam Li wrote:
> Since Linux doesn't have a user API to issue zone append operations to
> zoned devices from user space, the file-posix driver is modified to add
> zone append emulation using regular writes. To do this, the file-posix
> driver tracks the wp location of all zones of the device. It uses an
> array of uint64_t. The most significant bit of each wp location indicates
> if the zone type is conventional zones.
> 
> The zones wp can be changed due to the following operations issued:
> - zone reset: change the wp to the start offset of that zone
> - zone finish: change to the end location of that zone
> - write to a zone
> - zone append
> 
> Signed-off-by: Sam Li 
> ---
>  block/file-posix.c   | 168 ++-
>  include/block/block-common.h |  14 +++
>  include/block/block_int-common.h |   5 +
>  3 files changed, 184 insertions(+), 3 deletions(-)
> 
> diff --git a/block/file-posix.c b/block/file-posix.c
> index 65efe5147e..bc58f7193b 100644
> --- a/block/file-posix.c
> +++ b/block/file-posix.c
> @@ -1324,6 +1324,88 @@ static int hdev_get_max_segments(int fd, struct stat 
> *st)
>  #endif
>  }
>  
> +#if defined(CONFIG_BLKZONED)
> +/*
> + * If the reset_all flag is true, then the wps of zone whose state is
> + * not readonly or offline should be all reset to the start sector.
> + * Else, take the real wp of the device.
> + */
> +static int get_zones_wp(int fd, BlockZoneWps *wps, int64_t offset,
> +unsigned int nrz, bool reset_all)
> +{
> +struct blk_zone *blkz;
> +size_t rep_size;
> +uint64_t sector = offset >> BDRV_SECTOR_BITS;
> +int ret, n = 0, i = 0;
> +rep_size = sizeof(struct blk_zone_report) + nrz * sizeof(struct 
> blk_zone);
> +g_autofree struct blk_zone_report *rep = NULL;
> +
> +rep = g_malloc(rep_size);
> +blkz = (struct blk_zone *)(rep + 1);
> +while (n < nrz) {
> +memset(rep, 0, rep_size);
> +rep->sector = sector;
> +rep->nr_zones = nrz - n;
> +
> +do {
> +ret = ioctl(fd, BLKREPORTZONE, rep);
> +} while (ret != 0 && errno == EINTR);
> +if (ret != 0) {
> +error_report("%d: ioctl BLKREPORTZONE at %" PRId64 " failed %d",
> +fd, offset, errno);
> +return -errno;
> +}
> +
> +if (!rep->nr_zones) {
> +break;
> +}
> +
> +for (i = 0; i < rep->nr_zones; i++, n++) {
> +/*
> + * The wp tracking cares only about sequential writes required 
> and
> + * sequential write preferred zones so that the wp can advance to
> + * the right location.
> + * Use the most significant bit of the wp location to indicate 
> the
> + * zone type: 0 for SWR/SWP zones and 1 for conventional zones.
> + */
> +if (blkz[i].type == BLK_ZONE_TYPE_CONVENTIONAL) {
> +wps->wp[i] &= 1ULL << 63;

Should this be |= instead of &=? I think the intention is to set the
bit.

> +} else {
> +switch(blkz[i].cond) {
> +case BLK_ZONE_COND_FULL:
> +case BLK_ZONE_COND_READONLY:
> +/* Zone not writable */
> +wps->wp[i] = (blkz[i].start + blkz[i].len) << 
> BDRV_SECTOR_BITS;

wps->wp[i] looks wrong in two cases:
1. After the first iteration of the while (n < nrz) loop.
2. When offset > 0.

I think there should be a j variable that tracks the index into wp[]. It
should be initialized outside the while loop based on offset and
incremented inside the for loop.

> +break;
> +case BLK_ZONE_COND_OFFLINE:
> +/* Zone not writable nor readable */
> +wps->wp[i] = (blkz[i].start) << BDRV_SECTOR_BITS;
> +break;
> +default:
> +if (reset_all) {
> +wps->wp[i] = blkz[i].start << BDRV_SECTOR_BITS;
> +} else {
> +wps->wp[i] = blkz[i].wp << BDRV_SECTOR_BITS;
> +}
> +break;
> +}
> +}
> +}
> +sector = blkz[i - 1].start + blkz[i - 1].len;
> +}
> +
> +return 0;
> +}
> +
> +static void update_zones_wp(int fd, BlockZoneWps *wps, int64_t offset,
> +unsigned int nrz)
> +{
> +if (get_zones_wp(fd, wps, offset, nrz, 0) < 0) {
> +error_report("update zone wp failed");
> +}
> +}
> +#endif
> +
>  static void raw_refresh_limits(BlockDriverState *bs, Error **errp)
>  {
>  BDRVRawState *s = bs->opaque;
> @@ -1413,6 +1495,23 @@ static void raw_refresh_limits(BlockDriverState *bs, 
> Error **errp)
>  if (ret >= 0) {
>  bs->bl.max_active_zones = ret;
>  }
> +
> +ret = get_sysfs_long_val(, "physical_block_size");
> +

Re: [PATCH 08/10] target/ppc: Restrict KVM-specific field from ArchCPU

[Daniel Henrique Barboza]

On 4/5/23 13:04, Philippe Mathieu-Daudé wrote:

The 'kvm_sw_tlb' field shouldn't be accessed when KVM is not available.

Signed-off-by: Philippe Mathieu-Daudé 
---


Reviewed-by: Daniel Henrique Barboza 


  target/ppc/cpu.h| 2 ++
  target/ppc/mmu_common.c | 4 
  2 files changed, 6 insertions(+)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 557d736dab..0ec3957397 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1148,7 +1148,9 @@ struct CPUArchState {
  int tlb_type;/* Type of TLB we're dealing with */
  ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed */
  bool tlb_dirty;  /* Set to non-zero when modifying TLB */
+#ifdef CONFIG_KVM
  bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
+#endif /* CONFIG_KVM */
  uint32_t tlb_need_flush; /* Delayed flush needed */
  #define TLB_NEED_LOCAL_FLUSH   0x1
  #define TLB_NEED_GLOBAL_FLUSH  0x2
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 7235a4befe..21843c69f6 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -917,10 +917,12 @@ static void mmubooke_dump_mmu(CPUPPCState *env)
  ppcemb_tlb_t *entry;
  int i;
  
+#ifdef CONFIG_KVM

  if (kvm_enabled() && !env->kvm_sw_tlb) {
  qemu_printf("Cannot access KVM TLB\n");
  return;
  }
+#endif
  
  qemu_printf("\nTLB:\n");

  qemu_printf("Effective  Physical   Size PID   Prot "
@@ -1008,10 +1010,12 @@ static void mmubooke206_dump_mmu(CPUPPCState *env)
  int offset = 0;
  int i;
  
+#ifdef CONFIG_KVM

  if (kvm_enabled() && !env->kvm_sw_tlb) {
  qemu_printf("Cannot access KVM TLB\n");
  return;
  }
+#endif
  
  for (i = 0; i < BOOKE206_MAX_TLBN; i++) {

  int size = booke206_tlb_size(env, i);

Re: [PATCH-for-8.1] block/dmg: Declare a type definition for DMG uncompress function

[Stefan Hajnoczi]

On Mon, Mar 20, 2023 at 04:26:10PM +0100, Philippe Mathieu-Daudé wrote:
> Introduce the BdrvDmgUncompressFunc type defintion. To emphasis
> dmg_uncompress_bz2 and dmg_uncompress_lzfse are pointer to functions,
> declare them using this new typedef.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  block/dmg.h | 8 
>  block/dmg.c | 7 ++-
>  2 files changed, 6 insertions(+), 9 deletions(-)

Sorry for the delay, applied to my block-next tree:
https://gitlab.com/stefanha/qemu/commits/block-next

Stefan


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Description: PGP signature

Re: [PATCH 0/4] block: Split padded I/O vectors exceeding IOV_MAX

[Stefan Hajnoczi]

On Fri, Mar 17, 2023 at 06:50:15PM +0100, Hanna Czenczek wrote:
> RFC:
> https://lists.nongnu.org/archive/html/qemu-block/2023-03/msg00446.html
> 
> Thanks for the feedback on the RFC!  Sounds like we agree that this is
> the right way to fix the bug.
> 
> Here in v1, I’ve followed Vladimir’s suggestion to inline the
> functionality of qemu_iovec_init_extended() in block/io.c, which, I
> think (hope), also addresses much of the feedback of Eric and Stefan.
> 
> The test is unchanged, the rest is pretty much rewritten (though in
> spirit stays the same).
> 
> 
> Hanna Czenczek (4):
>   util/iov: Make qiov_slice() public
>   block: Split padded I/O vectors exceeding IOV_MAX
>   util/iov: Remove qemu_iovec_init_extended()
>   iotests/iov-padding: New test
> 
>  include/qemu/iov.h   |   8 +-
>  block/io.c   | 153 +--
>  util/iov.c   |  89 +++--
>  tests/qemu-iotests/tests/iov-padding |  85 +
>  tests/qemu-iotests/tests/iov-padding.out |  59 +
>  5 files changed, 306 insertions(+), 88 deletions(-)
>  create mode 100755 tests/qemu-iotests/tests/iov-padding
>  create mode 100644 tests/qemu-iotests/tests/iov-padding.out

Acked-by: Stefan Hajnoczi 


signature.asc
Description: PGP signature

[PATCH] Hexagon (tests/tcg/hexagon) Move HVX test infra to header file

[Taylor Simpson]

This will facilitate adding additional tests in separate .c files

Signed-off-by: Taylor Simpson 
---
 tests/tcg/hexagon/hvx_misc.h  | 178 ++
 tests/tcg/hexagon/hvx_misc.c  | 160 +--
 tests/tcg/hexagon/Makefile.target |   1 +
 3 files changed, 181 insertions(+), 158 deletions(-)
 create mode 100644 tests/tcg/hexagon/hvx_misc.h

diff --git a/tests/tcg/hexagon/hvx_misc.h b/tests/tcg/hexagon/hvx_misc.h
new file mode 100644
index 00..ebcdb9f033
--- /dev/null
+++ b/tests/tcg/hexagon/hvx_misc.h
@@ -0,0 +1,178 @@
+/*
+ *  Copyright(c) 2021-2023 Qualcomm Innovation Center, Inc. All Rights 
Reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see .
+ */
+
+#ifndef HVX_MISC_H
+#define HVX_MISC_H
+
+static inline void check(int line, int i, int j,
+ uint64_t result, uint64_t expect)
+{
+if (result != expect) {
+printf("ERROR at line %d: [%d][%d] 0x%016llx != 0x%016llx\n",
+   line, i, j, result, expect);
+err++;
+}
+}
+
+#define MAX_VEC_SIZE_BYTES 128
+
+typedef union {
+uint64_t ud[MAX_VEC_SIZE_BYTES / 8];
+int64_t   d[MAX_VEC_SIZE_BYTES / 8];
+uint32_t uw[MAX_VEC_SIZE_BYTES / 4];
+int32_t   w[MAX_VEC_SIZE_BYTES / 4];
+uint16_t uh[MAX_VEC_SIZE_BYTES / 2];
+int16_t   h[MAX_VEC_SIZE_BYTES / 2];
+uint8_t  ub[MAX_VEC_SIZE_BYTES / 1];
+int8_tb[MAX_VEC_SIZE_BYTES / 1];
+} MMVector;
+
+#define BUFSIZE  16
+#define OUTSIZE  16
+#define MASKMOD  3
+
+MMVector buffer0[BUFSIZE] __attribute__((aligned(MAX_VEC_SIZE_BYTES)));
+MMVector buffer1[BUFSIZE] __attribute__((aligned(MAX_VEC_SIZE_BYTES)));
+MMVector mask[BUFSIZE] __attribute__((aligned(MAX_VEC_SIZE_BYTES)));
+MMVector output[OUTSIZE] __attribute__((aligned(MAX_VEC_SIZE_BYTES)));
+MMVector expect[OUTSIZE] __attribute__((aligned(MAX_VEC_SIZE_BYTES)));
+
+#define CHECK_OUTPUT_FUNC(FIELD, FIELDSZ) \
+static void check_output_##FIELD(int line, size_t num_vectors) \
+{ \
+for (int i = 0; i < num_vectors; i++) { \
+for (int j = 0; j < MAX_VEC_SIZE_BYTES / FIELDSZ; j++) { \
+check(line, i, j, output[i].FIELD[j], expect[i].FIELD[j]); \
+} \
+} \
+}
+
+CHECK_OUTPUT_FUNC(d,  8)
+CHECK_OUTPUT_FUNC(w,  4)
+CHECK_OUTPUT_FUNC(h,  2)
+CHECK_OUTPUT_FUNC(b,  1)
+
+static void init_buffers(void)
+{
+int counter0 = 0;
+int counter1 = 17;
+for (int i = 0; i < BUFSIZE; i++) {
+for (int j = 0; j < MAX_VEC_SIZE_BYTES; j++) {
+buffer0[i].b[j] = counter0++;
+buffer1[i].b[j] = counter1++;
+}
+for (int j = 0; j < MAX_VEC_SIZE_BYTES / 4; j++) {
+mask[i].w[j] = (i + j % MASKMOD == 0) ? 0 : 1;
+}
+}
+}
+
+#define VEC_OP1(ASM, EL, IN, OUT) \
+asm("v2 = vmem(%0 + #0)\n\t" \
+"v2" #EL " = " #ASM "(v2" #EL ")\n\t" \
+"vmem(%1 + #0) = v2\n\t" \
+: : "r"(IN), "r"(OUT) : "v2", "memory")
+
+#define VEC_OP2(ASM, EL, IN0, IN1, OUT) \
+asm("v2 = vmem(%0 + #0)\n\t" \
+"v3 = vmem(%1 + #0)\n\t" \
+"v2" #EL " = " #ASM "(v2" #EL ", v3" #EL ")\n\t" \
+"vmem(%2 + #0) = v2\n\t" \
+: : "r"(IN0), "r"(IN1), "r"(OUT) : "v2", "v3", "memory")
+
+#define TEST_VEC_OP1(NAME, ASM, EL, FIELD, FIELDSZ, OP) \
+static void test_##NAME(void) \
+{ \
+void *pin = buffer0; \
+void *pout = output; \
+for (int i = 0; i < BUFSIZE; i++) { \
+VEC_OP1(ASM, EL, pin, pout); \
+pin += sizeof(MMVector); \
+pout += sizeof(MMVector); \
+} \
+for (int i = 0; i < BUFSIZE; i++) { \
+for (int j = 0; j < MAX_VEC_SIZE_BYTES / FIELDSZ; j++) { \
+expect[i].FIELD[j] = OP buffer0[i].FIELD[j]; \
+} \
+} \
+check_output_##FIELD(__LINE__, BUFSIZE); \
+}
+
+#define TEST_VEC_OP2(NAME, ASM, EL, FIELD, FIELDSZ, OP) \
+static void test_##NAME(void) \
+{ \
+void *p0 = buffer0; \
+void *p1 = buffer1; \
+void *pout = output; \
+for (int i = 0; i < BUFSIZE; i++) { \
+VEC_OP2(ASM, EL, p0, p1, pout); \
+p0 += sizeof(MMVector); \
+p1 += sizeof(MMVector); \
+pout += sizeof(MMVector); \
+} \
+for (int i = 0; i < BUFSIZE; i++) { \
+for (int j = 0; j < MAX_VEC_SIZE_BYTES / FIELDSZ; j++) { \
+expect[i].FIELD[j] = buffer0[i].FIELD[j] OP 

Re: QEMU stable 7.2.1

[Peter Maydell]

On Wed, 5 Apr 2023 at 19:58, Michael Roth  wrote:
> One thing I forgot to mention previously is updating the wiki with the
> release schedule once you have an idea of when you plan to push your tags.

On a slight tangent, do you have the process you use for
releases (main as well as stable-branch ones) written down
somewhere? It might be handy if we ever need to pass that
duty on to somebody else (or if you're bored with it and
want to rotate it between multiple people...)

thanks
-- PMM

Re: [PATCH v3 0/4] target/riscv: Simplification for RVH related check and code style fix

[Daniel Henrique Barboza]

On 4/5/23 05:58, Weiwei Li wrote:

This patchset tries to simplify the RVH related check and fix some code style 
problems, such as problems for indentation, multi-line comments and lines with 
over 80 characters.

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-virtfix-upstream

v2:
* add comment to specify riscv_cpu_set_virt_enabled() can only be called when 
RVH is enabled in patch 4 (suggested by Richard Henderson)
* merge patch from LIU Zhiwei(Message-ID: 
<20230325145348.1208-1-zhiwei_...@linux.alibaba.com>) to patch 5
* use env->virt_enabled directly instead of riscv_cpu_virt_enabled() in patch 6 
(suggested by LIU Zhiwei)
* remain the orginal identation for macro name in patch 8 (suggested by LIU 
Zhiwei)

v3:
* rebase on riscv-to-apply.next (partial patches in v2 have been applied)
* Fix new found format problem in patch 2,3,4 of v3


All patches:

Reviewed-by: Daniel Henrique Barboza 



Weiwei Li (4):
   target/riscv: Remove riscv_cpu_virt_enabled()
   target/riscv: Fix format for indentation
   target/riscv: Fix format for comments
   target/riscv: Fix lines with over 80 characters

  target/riscv/arch_dump.c|   7 +-
  target/riscv/cpu.c  |  47 ++--
  target/riscv/cpu.h  |  31 +--
  target/riscv/cpu_bits.h |   2 +-
  target/riscv/cpu_helper.c   | 274 ++--
  target/riscv/csr.c  |  90 +++
  target/riscv/debug.c|  21 +-
  target/riscv/fpu_helper.c   |  24 +-
  target/riscv/gdbstub.c  |   3 +-
  target/riscv/insn_trans/trans_rvv.c.inc |  36 +--
  target/riscv/m128_helper.c  |  16 +-
  target/riscv/machine.c  |  18 +-
  target/riscv/op_helper.c|  20 +-
  target/riscv/pmp.c  |  66 ++---
  target/riscv/pmp.h  |   9 +-
  target/riscv/pmu.c  |   7 +-
  target/riscv/sbi_ecall_interface.h  |   8 +-
  target/riscv/translate.c|  26 +-
  target/riscv/vector_helper.c| 317 ++--
  19 files changed, 552 insertions(+), 470 deletions(-)

[PATCH for-8.1] target/sparc: Use tcg_gen_lookup_and_goto_ptr

[Richard Henderson]

Signed-off-by: Richard Henderson 
---
 target/sparc/translate.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 137bdc5159..47940fd85e 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -322,7 +322,7 @@ static void gen_goto_tb(DisasContext *s, int tb_num,
 /* jump to another page: currently not optimized */
 tcg_gen_movi_tl(cpu_pc, pc);
 tcg_gen_movi_tl(cpu_npc, npc);
-tcg_gen_exit_tb(NULL, 0);
+tcg_gen_lookup_and_goto_ptr();
 }
 }
 
@@ -4153,7 +4153,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned 
int insn)
 /* End TB to notice changed ASI.  */
 save_state(dc);
 gen_op_next_insn();
-tcg_gen_exit_tb(NULL, 0);
+tcg_gen_lookup_and_goto_ptr();
 dc->base.is_jmp = DISAS_NORETURN;
 break;
 case 0x6: /* V9 wrfprs */
@@ -4162,7 +4162,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned 
int insn)
 dc->fprs_dirty = 0;
 save_state(dc);
 gen_op_next_insn();
-tcg_gen_exit_tb(NULL, 0);
+tcg_gen_lookup_and_goto_ptr();
 dc->base.is_jmp = DISAS_NORETURN;
 break;
 case 0xf: /* V9 sir, nop if user */
@@ -5661,7 +5661,7 @@ static void sparc_tr_tb_stop(DisasContextBase *dcbase, 
CPUState *cs)
 tcg_gen_movi_tl(cpu_pc, dc->pc);
 }
 save_npc(dc);
-tcg_gen_exit_tb(NULL, 0);
+tcg_gen_lookup_and_goto_ptr();
 }
 break;
 
-- 
2.34.1

Re: QEMU stable 7.2.1

[Michael Roth]

On Wed, Apr 05, 2023 at 05:16:33PM +0300, Michael Tokarev wrote:
> 05.04.2023 16:58, Michael Roth wrote:
> > On Wed, Apr 05, 2023 at 02:54:47PM +0300, Michael Tokarev wrote:
> > > So let it be, with a delay of about a week.
> > > 
> > > Since no one from the qemu team replied to my final-release steps, I'm
> > > making it available on my site instead:
> > > 
> > >http://www.corpit.ru/mjt/qemu/qemu-7.2.1.tar.xz
> > >http://www.corpit.ru/mjt/qemu/qemu-7.2.1.tar.xz.sig - signed with my 
> > > GPG key
> > >http://www.corpit.ru/mjt/qemu/qemu-7.2.1.diff - whole difference from 
> > > 7.2.0.
> > > 
> > > The tag (v7.2.1) is in the main qemu repository.
> > 
> > Hi Michael,
> > 
> > Thanks for handling this release!
> > 
> > Somehow I missed your final steps email, but for future releases I would
> > recommend going ahead and tagging your release (also signed with your GPG
> > key) in your local tree once you've got everything ready, and then sending
> > me an email to directly so I can push that to gitlab and then handle
> > creating the tarball and publish it with my GPG key. That's basically what
> > we do for the normal QEMU releases as well.
> > 
> > Then once you get your accounts set up by gitlab/qemu.org admins you can
> > handle the tag-pushing/tarball-uploading on your end. Would be good to
> > have someone else involved with that process so we have some redundancy
> > just in case.
> 
> Thank you for the reply!
> 
> I'm not sure I follow you here. I already pushed v7.2.1 tag and stable-7.2
> branch to gitlab/qemu. The branch has been there for quite some time.

Oh! Nice, didn't realize you were set up there already. Just noticed the
7.2.1 tag when pulling down 8.0.0-rc3.

That also helped me notice that your reply here got quarantined by my email
server, along with a number of your previous emails relating to stable, so
that explains how those slipped by (the ones that hit the mailing list
still show up if I'm looking in the right place).

I'll keep a better eye out for this in the future and try to reach an
understanding with this advanced AI technology that treats straight-forward
direct replies to my emails as spam for inexplicable reasons.

> 
> Should I avoid tagging/pushing for the future or is it okay to do that?

Nope, that's fine. Just ignore my comments regarding git, everything seems
to be good on that end.

One thing I forgot to mention previously is updating the wiki with the
release schedule once you have an idea of when you plan to push your tags.
E.g.:

  https://wiki.qemu.org/Planning/7.2

I usually set the date once I have the initial staging ready and get
ready to send out the "patch round-up" with expected freeze/release
dates. Might be good to email me directly or Cc: me on related
announcements around that time so I can make sure I'm around.

> 
> For the tarballs, it's definitely better to follow the established practice,
> I published the generated tarball on my site just as a last-resort, so that
> it ends up *somewhere*. It should be prepared the same way as other releases
> has been made, including the .bz2 version.
> 
> If that's okay with you, feel free to re-create the tarball from v7.2.1
> tag, and compress the tarball with whatever compressors usually used by
> the qemu team.  It's the way to go.

Ok, sure, I'll go ahead and re-publish 7.2.1 tarball a bit later today.

We can stick with this approach until you're all set up for uploading.

-Mike

> 
> Thanks,
> 
> /mjt
> 

[ANNOUNCE] QEMU 8.0.0-rc3 is now available

[Michael Roth]

Hello,

On behalf of the QEMU Team, I'd like to announce the availability of the
fourth release candidate for the QEMU 8.0 release. This release is meant
for testing purposes and should not be used in a production environment.

  http://download.qemu.org/qemu-8.0.0-rc3.tar.xz
  http://download.qemu.org/qemu-8.0.0-rc3.tar.xz.sig

A note from the maintainer:

  Unless any showstopper bugs appear in the next week, this will be the
  final rc for this release.

You can help improve the quality of the QEMU 8.0 release by testing this
release and reporting bugs using our GitLab issue tracker:

  https://gitlab.com/qemu-project/qemu/-/milestones/8#tab-issues

The release plan, as well a documented known issues for release
candidates, are available at:

  http://wiki.qemu.org/Planning/8.0

Please add entries to the ChangeLog for the 8.0 release below:

  http://wiki.qemu.org/ChangeLog/8.0

Thank you to everyone involved!

Changes since rc2:

c6f3cbca32: Update version for v8.0.0-rc3 release (Peter Maydell)
b1ab8f9cc5: Revert "memory: Optimize replay of guest mapping" (Peter Maydell)
56adee407f: kvm: dirty-ring: Fix race with vcpu creation (Peter Xu)
1ffbe5d681: tcg/sparc64: Disable direct linking for goto_tb (Richard Henderson)
3371802fba: accel/tcg: Fix jump cache set in cpu_exec_loop (Richard Henderson)
c83574392e: accel/tcg: Fix overwrite problems of tcg_cflags (Weiwei Li)
c8cb603293: tests/avocado: Test Xen guest support under KVM (David Woodhouse)
fc9988916a: gitlab: fix typo (Alex Bennée)
bdd53274f2: tests/vm: use the default system python for NetBSD (Daniel P. 
Berrangé)
90834f5de6: tests/qemu-iotests: explicitly invoke 'check' via 'python' (Daniel 
P. Berrangé)
6e3be02291: Use hexagon toolchain version 16.0.0 (Marco Liebel)
452b3eeacc: metadata: add .git-blame-ignore-revs (Alex Bennée)
3be8c03460: MAINTAINERS: add a section for policy documents (Alex Bennée)
0beaebc041: gdbstub: don't report auxv feature unless on Linux (Alex Bennée)
b846ad627e: gdbstub: Only build libgdb_user.fa / libgdb_softmmu.fa if necessary 
(Philippe Mathieu-Daudé)
6cda41daa2: Revert "linux-user/arm: Take more care allocating commpage" 
(Richard Henderson)
899c3fc2dc: scripts/coverage: initial coverage comparison script (Alex Bennée)
f1426881a8: nbd/server: Request TCP_NODELAY (Eric Blake)
b8b6d3c04a: MAINTAINERS: Remove and change David Gilbert maintainer entries 
(Dr. David Alan Gilbert)
ec28dd6c6f: target/loongarch: Enables plugins to get instruction codes 
(tanhongze)
51d54503e8: hw/loongarch/virt: Fix virt_to_phys_addr function (Tianrui Zhao)
a0eaa126af: hw/ssi: Fix Linux driver init issue with xilinx_spi (Chris Rauer)
782781e85d: target/arm: Fix generated code for cpreg reads when HSTR is active 
(Peter Maydell)
12148d442e: hw/arm: do not free machine->fdt in arm_load_dtb() (Markus 
Armbruster)
b15bdc9651: target/arm: Fix non-TCG build failure by inlining pauth_ptr_mask() 
(Philippe Mathieu-Daudé)
aad3eb1ffe: block/dmg: Ignore C99 prototype declaration mismatch from  
(Philippe Mathieu-Daudé)
95bf341865: hw/i2c: pmbus: block uninitialised string reads (Titus Rwantare)
9d403d27bc: tests/avocado: Enable TuxRun/mips64 (big-endian) test (Philippe 
Mathieu-Daudé)
3d85c7c15f: hw/mips/gt64xxx_pci: Don't endian-swap GT_PCI0_CFGADDR (Jiaxun Yang)
450cb7ec2c: linux-user/mips: Use P5600 as default CPU to run NaN2008 ELF 
binaries (Philippe Mathieu-Daudé)
baead64297: linux-user/sparc: Don't use 16-bit UIDs on SPARC V9 (Philippe 
Mathieu-Daudé)
87e303de70: softmmu: Restore use of CPU watchpoint for all accelerators 
(Philippe Mathieu-Daudé)
a085860834: softmmu/watchpoint: Add missing 'qemu/error-report.h' include 
(Philippe Mathieu-Daudé)
6eece7f531: softmmu: Restrict cpu_check_watchpoint / address_matches to TCG 
accel (Philippe Mathieu-Daudé)
4f5c67f8df: linux-user/arm: Take more care allocating commpage (Richard 
Henderson)
95059f9c31: include/exec: Change reserved_va semantics to last byte (Richard 
Henderson)
a3a67f54f0: linux-user: Pass last not end to probe_guest_base (Richard 
Henderson)
e506ad6a05: accel/tcg: Pass last not end to tb_invalidate_phys_range (Richard 
Henderson)
73f96d51ff: accel/tcg: Pass last not end to 
tb_invalidate_phys_page_range__locked (Richard Henderson)
f6555e3f39: accel/tcg: Pass last not end to page_collection_lock (Richard 
Henderson)
f7e2add5fd: accel/tcg: Pass last not end to PAGE_FOR_EACH_TB (Richard Henderson)
10310cbd62: accel/tcg: Pass last not end to page_reset_target_data (Richard 
Henderson)
49840a4a09: accel/tcg: Pass last not end to page_set_flags (Richard Henderson)
2f7828b572: linux-user: Diagnose misaligned -R size (Richard Henderson)
1ff4a81bd3: tcg: use QTree instead of GTree (Emilio Cota)
e3feb2cc22: util: import GTree as QTree (Emilio Cota)

[PATCH] Hexagon (target/hexagon) Remove redundant/unused macros

[Taylor Simpson]

Remove the following macros (remnants of the old generator design)
READ_REG
READ_PREG
WRITE_RREG
WRITE_PREG
Modify macros that rely on the above

The following are unused
READ_IREG
fGET_FIELD
fSET_FIELD
fREAD_P3
fREAD_NPC
fWRITE_LC0
fWRITE_LC1

Signed-off-by: Taylor Simpson 
---
 target/hexagon/macros.h | 65 ++---
 1 file changed, 22 insertions(+), 43 deletions(-)

diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 482a9c787f..f5f31b6930 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -22,16 +22,6 @@
 #include "hex_regs.h"
 #include "reg_fields.h"
 
-#ifdef QEMU_GENERATE
-#define READ_REG(dest, NUM)  gen_read_reg(dest, NUM)
-#else
-#define READ_REG(NUM)(env->gpr[(NUM)])
-#define READ_PREG(NUM)   (env->pred[NUM])
-
-#define WRITE_RREG(NUM, VAL) log_reg_write(env, NUM, VAL, slot)
-#define WRITE_PREG(NUM, VAL) log_pred_write(env, NUM, VAL)
-#endif
-
 #define PCALIGN 4
 #define PCALIGN_MASK (PCALIGN - 1)
 
@@ -361,37 +351,30 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, 
int shift)
 tcg_gen_shli_tl(result, result, shift);
 return result;
 }
-#define fREAD_IREG(VAL, SHIFT) gen_read_ireg(ireg, (VAL), (SHIFT))
-#else
-#define fREAD_IREG(VAL) \
-(fSXTN(11, 64, (((VAL) & 0xf000) >> 21) | ((VAL >> 17) & 0x7f)))
 #endif
 
-#define fREAD_LR() (READ_REG(HEX_REG_LR))
+#define fREAD_LR() (env->gpr[HEX_REG_LR])
 
-#define fWRITE_LR(A) WRITE_RREG(HEX_REG_LR, A)
-#define fWRITE_FP(A) WRITE_RREG(HEX_REG_FP, A)
-#define fWRITE_SP(A) WRITE_RREG(HEX_REG_SP, A)
+#define fWRITE_LR(A) log_reg_write(env, HEX_REG_LR, A, slot)
+#define fWRITE_FP(A) log_reg_write(env, HEX_REG_FP, A, slot)
+#define fWRITE_SP(A) log_reg_write(env, HEX_REG_SP, A, slot)
 
-#define fREAD_SP() (READ_REG(HEX_REG_SP))
-#define fREAD_LC0 (READ_REG(HEX_REG_LC0))
-#define fREAD_LC1 (READ_REG(HEX_REG_LC1))
-#define fREAD_SA0 (READ_REG(HEX_REG_SA0))
-#define fREAD_SA1 (READ_REG(HEX_REG_SA1))
-#define fREAD_FP() (READ_REG(HEX_REG_FP))
+#define fREAD_SP() (env->gpr[HEX_REG_SP])
+#define fREAD_LC0 (env->gpr[HEX_REG_LC0])
+#define fREAD_LC1 (env->gpr[HEX_REG_LC1])
+#define fREAD_SA0 (env->gpr[HEX_REG_SA0])
+#define fREAD_SA1 (env->gpr[HEX_REG_SA1])
+#define fREAD_FP() (env->gpr[HEX_REG_FP])
 #ifdef FIXME
 /* Figure out how to get insn->extension_valid to helper */
 #define fREAD_GP() \
-(insn->extension_valid ? 0 : READ_REG(HEX_REG_GP))
+(insn->extension_valid ? 0 : env->gpr[HEX_REG_GP])
 #else
-#define fREAD_GP() READ_REG(HEX_REG_GP)
+#define fREAD_GP() (env->gpr[HEX_REG_GP])
 #endif
 #define fREAD_PC() (PC)
 
-#define fREAD_NPC() (next_PC & (0xfffe))
-
-#define fREAD_P0() (READ_PREG(0))
-#define fREAD_P3() (READ_PREG(3))
+#define fREAD_P0() (env->pred[0])
 
 #define fCHECK_PCALIGN(A)
 
@@ -402,24 +385,22 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, 
int shift)
 #define fHINTJR(TARGET) { /* Not modelled in qemu */}
 #define fWRITE_LOOP_REGS0(START, COUNT) \
 do { \
-WRITE_RREG(HEX_REG_LC0, COUNT);  \
-WRITE_RREG(HEX_REG_SA0, START); \
+log_reg_write(env, HEX_REG_LC0, COUNT, slot);  \
+log_reg_write(env, HEX_REG_SA0, START, slot); \
 } while (0)
 #define fWRITE_LOOP_REGS1(START, COUNT) \
 do { \
-WRITE_RREG(HEX_REG_LC1, COUNT);  \
-WRITE_RREG(HEX_REG_SA1, START);\
+log_reg_write(env, HEX_REG_LC1, COUNT, slot);  \
+log_reg_write(env, HEX_REG_SA1, START, slot);\
 } while (0)
-#define fWRITE_LC0(VAL) WRITE_RREG(HEX_REG_LC0, VAL)
-#define fWRITE_LC1(VAL) WRITE_RREG(HEX_REG_LC1, VAL)
 
 #define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1)
 #define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL))
 #define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG))
-#define fWRITE_P0(VAL) WRITE_PREG(0, VAL)
-#define fWRITE_P1(VAL) WRITE_PREG(1, VAL)
-#define fWRITE_P2(VAL) WRITE_PREG(2, VAL)
-#define fWRITE_P3(VAL) WRITE_PREG(3, VAL)
+#define fWRITE_P0(VAL) log_pred_write(env, 0, VAL)
+#define fWRITE_P1(VAL) log_pred_write(env, 1, VAL)
+#define fWRITE_P2(VAL) log_pred_write(env, 2, VAL)
+#define fWRITE_P3(VAL) log_pred_write(env, 3, VAL)
 #define fPART1(WORK) if (part1) { WORK; return; }
 #define fCAST4u(A) ((uint32_t)(A))
 #define fCAST4s(A) ((int32_t)(A))
@@ -576,7 +557,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int 
shift)
 
 #define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE)
 
-#define fGET_FRAMEKEY() READ_REG(HEX_REG_FRAMEKEY)
+#define fGET_FRAMEKEY() (env->gpr[HEX_REG_FRAMEKEY])
 #define fFRAME_SCRAMBLE(VAL) ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32))
 #define fFRAME_UNSCRAMBLE(VAL) fFRAME_SCRAMBLE(VAL)
 
@@ -686,8 +667,6 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int 
shift)
 fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \
reg_field_info[FIELD].width, \
reg_field_info[FIELD].offset)
-#define 

Re: [PATCH 05/10] hw/arm/sbsa-ref: Include missing 'sysemu/kvm.h' header

[Leif Lindholm]

On Wed, Apr 05, 2023 at 18:04:49 +0200, Philippe Mathieu-Daudé wrote:
> "sysemu/kvm.h" is indirectly pulled in. Explicit its
> inclusion to avoid when refactoring include/:
> 
>   hw/arm/sbsa-ref.c:693:9: error: implicit declaration of function 
> 'kvm_enabled' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
> if (kvm_enabled()) {
> ^
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  hw/arm/sbsa-ref.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
> index 0b93558dde..7df4d7b712 100644
> --- a/hw/arm/sbsa-ref.c
> +++ b/hw/arm/sbsa-ref.c
> @@ -26,6 +26,7 @@
>  #include "sysemu/numa.h"
>  #include "sysemu/runstate.h"
>  #include "sysemu/sysemu.h"
> +#include "sysemu/kvm.h"

Can I do my traditional nitpick and ask this to be added above
sysemu/numa.h in order to maintain alphabetical ordering within the
sysemu block?

With that:
Reviewed-by: Leif Lindholm 


>  #include "exec/hwaddr.h"
>  #include "kvm_arm.h"
>  #include "hw/arm/boot.h"
> -- 
> 2.38.1
> 

Re: [PATCH 2/2] Add missing Linux kernel headers.

[David Turner]

On Wed, Apr 5, 2023 at 6:41 PM Peter Maydell 
wrote:

> On Wed, 5 Apr 2023 at 16:55, Cornelia Huck  wrote:
> >
> > On Wed, Apr 05 2023, David Turner  wrote:
> >
> > > On Wed, Apr 5, 2023 at 3:06 PM Cornelia Huck 
> wrote:
> > >
> > >> On Wed, Apr 05 2023, "David 'Digit' Turner"  wrote:
> > >> > The script has then been run against the official
> > >> > 6.2.8 kernel source tree (current stable release),
> > >> > which explains why comments in 
> > >> > have been updated too.
> > >>
> > >> I think we usually run the script against a release or release
> > >> candidate, not stable.
> > >>
> > >> I meant that this was run against the headers of the 6.2.8 official
> > > release, which was listed as "stable" on https://kernel.org/ (that
> page now
> > > lists the 6.2.9 release btw)
> > > I'd be happy to re-run it against a different set if you can tell me
> which
> > > one (and where to get it, just in case).
> >
> > I think most people actually run it against a checkout of Linus' git
> > tree, preferrably either the latest -rc version (or the latest release
> > during the kernel merge window) -- people usually run the script because
> > they want to use some new interfaces that were recently introduced to
> > the kernel. (This also ensures linear history, although I don't think
> > that's too much of a problem.)
>
> Yeah, I think the requirement is just "it has to be against some commit
> that is on the mainline of the upstream kernel", it doesn't inherently
> have to be an rc or a full point release. The assumption we're making
> here is that ABI is stable once a change hits Linus' git tree, and
> not stable before that.
>
> The other requirement is "don't go backwards", ie don't sync to a
> commit that pre-dates whatever the last commit we synced to is.
>
> The last sync we did was to ceaa837f96ad ("Linux 6.2-rc8").
>
> Thank you, that makes perfect sense, I have sent another series of patches
(with the headers updade as a separate patch for consistency)

thanks
> -- PMM
>

[PATCH 3/3] Update linux headers to v6.3rc5

[David 'Digit' Turner]

commit 7e364e56293bb98cae1b55fd835f5991c4e96e7d

Signed-off-by: David 'Digit' Turner 
---
 include/standard-headers/drm/drm_fourcc.h|  12 ++
 include/standard-headers/linux/ethtool.h |  48 +++-
 include/standard-headers/linux/fuse.h|  45 +++-
 include/standard-headers/linux/pci_regs.h|   1 +
 include/standard-headers/linux/vhost_types.h |   2 +
 include/standard-headers/linux/virtio_blk.h  | 105 +
 linux-headers/asm-arm64/kvm.h|   1 +
 linux-headers/asm-x86/kvm.h  |  34 +-
 linux-headers/linux/const.h  |  36 ++
 linux-headers/linux/kvm.h|   9 ++
 linux-headers/linux/memfd.h  |  39 +++
 linux-headers/linux/nvme_ioctl.h | 114 +++
 linux-headers/linux/vfio.h   |  15 ++-
 linux-headers/linux/vhost.h  |   8 ++
 14 files changed, 459 insertions(+), 10 deletions(-)
 create mode 100644 linux-headers/linux/const.h
 create mode 100644 linux-headers/linux/memfd.h
 create mode 100644 linux-headers/linux/nvme_ioctl.h

diff --git a/include/standard-headers/drm/drm_fourcc.h 
b/include/standard-headers/drm/drm_fourcc.h
index 69cab17b38..dc3e6112c1 100644
--- a/include/standard-headers/drm/drm_fourcc.h
+++ b/include/standard-headers/drm/drm_fourcc.h
@@ -87,6 +87,18 @@ extern "C" {
  *
  * The authoritative list of format modifier codes is found in
  * `include/uapi/drm/drm_fourcc.h`
+ *
+ * Open Source User Waiver
+ * ---
+ *
+ * Because this is the authoritative source for pixel formats and modifiers
+ * referenced by GL, Vulkan extensions and other standards and hence used both
+ * by open source and closed source driver stacks, the usual requirement for an
+ * upstream in-kernel or open source userspace user does not apply.
+ *
+ * To ensure, as much as feasible, compatibility across stacks and avoid
+ * confusion with incompatible enumerations stakeholders for all relevant 
driver
+ * stacks should approve additions.
  */
 
 #define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \
diff --git a/include/standard-headers/linux/ethtool.h 
b/include/standard-headers/linux/ethtool.h
index 87176ab075..99fcddf04f 100644
--- a/include/standard-headers/linux/ethtool.h
+++ b/include/standard-headers/linux/ethtool.h
@@ -711,6 +711,24 @@ enum ethtool_stringset {
ETH_SS_COUNT
 };
 
+/**
+ * enum ethtool_mac_stats_src - source of ethtool MAC statistics
+ * @ETHTOOL_MAC_STATS_SRC_AGGREGATE:
+ * if device supports a MAC merge layer, this retrieves the aggregate
+ * statistics of the eMAC and pMAC. Otherwise, it retrieves just the
+ * statistics of the single (express) MAC.
+ * @ETHTOOL_MAC_STATS_SRC_EMAC:
+ * if device supports a MM layer, this retrieves the eMAC statistics.
+ * Otherwise, it retrieves the statistics of the single (express) MAC.
+ * @ETHTOOL_MAC_STATS_SRC_PMAC:
+ * if device supports a MM layer, this retrieves the pMAC statistics.
+ */
+enum ethtool_mac_stats_src {
+   ETHTOOL_MAC_STATS_SRC_AGGREGATE,
+   ETHTOOL_MAC_STATS_SRC_EMAC,
+   ETHTOOL_MAC_STATS_SRC_PMAC,
+};
+
 /**
  * enum ethtool_module_power_mode_policy - plug-in module power mode policy
  * @ETHTOOL_MODULE_POWER_MODE_POLICY_HIGH: Module is always in high power mode.
@@ -779,6 +797,31 @@ enum ethtool_podl_pse_pw_d_status {
ETHTOOL_PODL_PSE_PW_D_STATUS_ERROR,
 };
 
+/**
+ * enum ethtool_mm_verify_status - status of MAC Merge Verify function
+ * @ETHTOOL_MM_VERIFY_STATUS_UNKNOWN:
+ * verification status is unknown
+ * @ETHTOOL_MM_VERIFY_STATUS_INITIAL:
+ * the 802.3 Verify State diagram is in the state INIT_VERIFICATION
+ * @ETHTOOL_MM_VERIFY_STATUS_VERIFYING:
+ * the Verify State diagram is in the state VERIFICATION_IDLE,
+ * SEND_VERIFY or WAIT_FOR_RESPONSE
+ * @ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED:
+ * indicates that the Verify State diagram is in the state VERIFIED
+ * @ETHTOOL_MM_VERIFY_STATUS_FAILED:
+ * the Verify State diagram is in the state VERIFY_FAIL
+ * @ETHTOOL_MM_VERIFY_STATUS_DISABLED:
+ * verification of preemption operation is disabled
+ */
+enum ethtool_mm_verify_status {
+   ETHTOOL_MM_VERIFY_STATUS_UNKNOWN,
+   ETHTOOL_MM_VERIFY_STATUS_INITIAL,
+   ETHTOOL_MM_VERIFY_STATUS_VERIFYING,
+   ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED,
+   ETHTOOL_MM_VERIFY_STATUS_FAILED,
+   ETHTOOL_MM_VERIFY_STATUS_DISABLED,
+};
+
 /**
  * struct ethtool_gstrings - string set for data tagging
  * @cmd: Command number = %ETHTOOL_GSTRINGS
@@ -1183,7 +1226,7 @@ struct ethtool_rxnfc {
uint32_trule_cnt;
uint32_trss_context;
};
-   uint32_trule_locs[0];
+   uint32_trule_locs[];
 };
 
 
@@ -1741,6 +1784,9 @@ enum ethtool_link_mode_bit_indices {

[PATCH 1/3] Fix libvhost-user.c compilation.

[David 'Digit' Turner]

The source file uses VIRTIO_F_VERSION_1 which is
not defined by  on Debian 10.

The system-provided  which
does not include the macro definition is included
through , so fix the issue by including
the standard-headers version before that.

Signed-off-by: David 'Digit' Turner 
---
 subprojects/libvhost-user/libvhost-user.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/subprojects/libvhost-user/libvhost-user.c 
b/subprojects/libvhost-user/libvhost-user.c
index 0200b78e8e..0a5768cb55 100644
--- a/subprojects/libvhost-user/libvhost-user.c
+++ b/subprojects/libvhost-user/libvhost-user.c
@@ -32,6 +32,12 @@
 #include 
 #include 
 
+/* Necessary to provide VIRTIO_F_VERSION_1 on system
+ * with older linux headers. Must appear before
+ *  below.
+ */
+#include "standard-headers/linux/virtio_config.h"
+
 #if defined(__linux__)
 #include 
 #include 
-- 
2.40.0.348.gf938b09366-goog

[PATCH 2/3] update-linux-headers.sh: Add missing kernel headers.

[David 'Digit' Turner]

Add , used by hw/display/virtio-gpu-udmabuf.c
Add , used by qga/commands-posix.c
Add  used by kvm-all.c, which requires
the _BITUL() macro definition to be available.

Without these, QEMU will not compile on Debian 10 systems.

Signed-off-by: David 'Digit' Turner 
---
 scripts/update-linux-headers.sh | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
index b1ad99cba8..e21225baf3 100755
--- a/scripts/update-linux-headers.sh
+++ b/scripts/update-linux-headers.sh
@@ -160,8 +160,8 @@ done
 
 rm -rf "$output/linux-headers/linux"
 mkdir -p "$output/linux-headers/linux"
-for header in kvm.h vfio.h vfio_ccw.h vfio_zdev.h vhost.h \
-  psci.h psp-sev.h userfaultfd.h mman.h vduse.h; do
+for header in const.h kvm.h vfio.h vfio_ccw.h vfio_zdev.h vhost.h \
+  psci.h psp-sev.h userfaultfd.h memfd.h mman.h nvme_ioctl.h 
vduse.h; do
 cp "$tmpdir/include/linux/$header" "$output/linux-headers/linux"
 done
 
-- 
2.40.0.348.gf938b09366-goog