Re: [Qemu-devel] [PATCH v2 01/17] RISC-V: add vfp field in CPURISCVState

[liuzhiwei]

On 2019/9/11 下午10:51, Chih-Min Chao wrote:



On Wed, Sep 11, 2019 at 2:35 PM liuzhiwei <mailto:zhiwei_...@c-sky.com>> wrote:


From: LIU Zhiwei mailto:zhiwei_...@c-sky.com>>

Signed-off-by: LIU Zhiwei mailto:zhiwei_...@c-sky.com>>
---
 target/riscv/cpu.h | 28 
 1 file changed, 28 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0adb307..c992b1d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -93,9 +93,37 @@ typedef struct CPURISCVState CPURISCVState;

 #include "pmp.h"

+#define VLEN 128
+#define VUNIT(x) (VLEN / x)
+
 struct CPURISCVState {
     target_ulong gpr[32];
     uint64_t fpr[32]; /* assume both F and D extensions */
+
+    /* vector coprocessor state.  */
+    struct {
+        union VECTOR {
+            float64  f64[VUNIT(64)];
+            float32  f32[VUNIT(32)];
+            float16  f16[VUNIT(16)];
+            uint64_t u64[VUNIT(64)];
+            int64_t  s64[VUNIT(64)];
+            uint32_t u32[VUNIT(32)];
+            int32_t  s32[VUNIT(32)];
+            uint16_t u16[VUNIT(16)];
+            int16_t  s16[VUNIT(16)];
+            uint8_t  u8[VUNIT(8)];
+            int8_t   s8[VUNIT(8)];
+        } vreg[32];
+        target_ulong vxrm;
+        target_ulong vxsat;
+        target_ulong vl;
+        target_ulong vstart;
+        target_ulong vtype;
+        float_status fp_status;
+    } vfp;
+
+    bool         foflag;
     target_ulong pc;
     target_ulong load_res;
     target_ulong load_val;
-- 
2.7.4



Could  the VLEN be configurable in cpu initialization but not fixed in 
compilation phase ?


Yes,  it's important that VLEN is configurable to support different 
types of cpu.


Take the integer element as example  and the difference should be the 
stride of vfp.vreg[x] isn't continuous


    struct {
        union VECTOR {
            uint64_t *u64;
            uint16_t *u16;
            uint8_t  *u8;
        } vreg[32];
    } vfp;

   initialization
    int vlen = 256;  //parameter from cpu command line option
    int elem = vlen / 8;
    int size = elem * 32;

    uint8_t *mem = malloc(size)
    for (int idx = 0; idx < 32; ++idx) {
        vfp.vreg[idx].u64 = (void *)[idx * elem];
        vfp.vreg[idx].u32 = (void *)[idx * elem];
        vfp.vreg[idx].u16 = (void *)[idx * elem];
   }

  chihmin


It's a good idea. I will accept it.

Thanks for review.

Zhiwei

[Qemu-devel] [PATCH v2 12/17] RISC-V: add vector extension fixed point instructions

[liuzhiwei]

From: LIU Zhiwei 

Signed-off-by: LIU Zhiwei 
---
 target/riscv/helper.h   |   37 +
 target/riscv/insn32.decode  |   37 +
 target/riscv/insn_trans/trans_rvv.inc.c |   37 +
 target/riscv/vector_helper.c| 3388 +++
 4 files changed, 3499 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index ab31ef7..ff6002e 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -270,5 +270,42 @@ DEF_HELPER_5(vector_vmerge_vvm, void, env, i32, i32, i32, 
i32)
 DEF_HELPER_5(vector_vmerge_vxm, void, env, i32, i32, i32, i32)
 DEF_HELPER_5(vector_vmerge_vim, void, env, i32, i32, i32, i32)
 
+DEF_HELPER_5(vector_vsaddu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsaddu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsaddu_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsadd_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsadd_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsadd_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vssubu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vssubu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vssub_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vssub_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vaadd_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vaadd_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vaadd_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vasub_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vasub_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsmul_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsmul_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwsmaccu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwsmaccu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwsmacc_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwsmacc_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwsmaccsu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwsmaccsu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwsmaccus_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vssrl_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vssrl_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vssrl_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vssra_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vssra_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vssra_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vnclipu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vnclipu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vnclipu_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vnclip_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vnclip_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vnclip_vi, void, env, i32, i32, i32, i32)
+
 DEF_HELPER_4(vector_vsetvli, void, env, i32, i32, i32)
 DEF_HELPER_4(vector_vsetvl, void, env, i32, i32, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6db18c5..a82e53e 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -410,5 +410,42 @@ vmerge_vvm  010111 . . . 000 . 1010111 
@r_vm
 vmerge_vxm  010111 . . . 100 . 1010111 @r_vm
 vmerge_vim  010111 . . . 011 . 1010111 @r_vm
 
+vsaddu_vv   10 . . . 000 . 1010111 @r_vm
+vsaddu_vx   10 . . . 100 . 1010111 @r_vm
+vsaddu_vi   10 . . . 011 . 1010111 @r_vm
+vsadd_vv11 . . . 000 . 1010111 @r_vm
+vsadd_vx11 . . . 100 . 1010111 @r_vm
+vsadd_vi11 . . . 011 . 1010111 @r_vm
+vssubu_vv   100010 . . . 000 . 1010111 @r_vm
+vssubu_vx   100010 . . . 100 . 1010111 @r_vm
+vssub_vv100011 . . . 000 . 1010111 @r_vm
+vssub_vx100011 . . . 100 . 1010111 @r_vm
+vaadd_vv100100 . . . 000 . 1010111 @r_vm
+vaadd_vx100100 . . . 100 . 1010111 @r_vm
+vaadd_vi100100 . . . 011 . 1010111 @r_vm
+vasub_vv100110 . . . 000 . 1010111 @r_vm
+vasub_vx100110 . . . 100 . 1010111 @r_vm
+vsmul_vv100111 . . . 000 . 1010111 @r_vm
+vsmul_vx100111 . . . 100 . 1010111 @r_vm
+vwsmaccu_vv 00 . . . 000 . 1010111 @r_vm
+vwsmaccu_vx 00 . . . 100 . 1010111 @r_vm
+vwsmacc_vv  01 . . . 000 . 1010111 @r_vm
+vwsmacc_vx  01 . . . 100 . 1010111 @r_vm
+vwsmaccsu_vv10 . . . 000 . 1010111 @r_vm
+vwsmaccsu_vx10 . . . 100 . 1010111 @r_vm
+vwsmaccus_vx11 . . . 100 . 1010111 @r_vm
+vssrl_vv101010 . . . 000 . 1010111 @r_vm
+vssrl_vx   

[Qemu-devel] [PATCH v2 16/17] RISC-V: add vector extension mask instructions

[liuzhiwei]

From: LIU Zhiwei 

Signed-off-by: LIU Zhiwei 
---
 target/riscv/helper.h   |  16 +
 target/riscv/insn32.decode  |  17 +
 target/riscv/insn_trans/trans_rvv.inc.c |  27 ++
 target/riscv/vector_helper.c| 635 
 4 files changed, 695 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index d36bd00..337ac2e 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -401,5 +401,21 @@ DEF_HELPER_5(vector_vwredsum_vs, void, env, i32, i32, i32, 
i32)
 DEF_HELPER_5(vector_vfwredsum_vs, void, env, i32, i32, i32, i32)
 DEF_HELPER_5(vector_vfwredosum_vs, void, env, i32, i32, i32, i32)
 
+DEF_HELPER_4(vector_vmandnot_mm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmand_mm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmor_mm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmxor_mm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmornot_mm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmnand_mm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmnor_mm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmxnor_mm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmsbf_m, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmsof_m, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmsif_m, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_viota_m, void, env, i32, i32, i32)
+DEF_HELPER_3(vector_vid_v, void, env, i32, i32)
+DEF_HELPER_4(vector_vmpopc_m, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmfirst_m, void, env, i32, i32, i32)
+
 DEF_HELPER_4(vector_vsetvli, void, env, i32, i32, i32)
 DEF_HELPER_4(vector_vsetvl, void, env, i32, i32, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3f63bc1..1de776b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -68,6 +68,7 @@
 @r_nfvm  nf:3 ... vm:1 . . ... . ... %rs2 %rs1 %rd
 @r2_nfvm nf:3 ... vm:1 . . ... . ... %rs1 %rd
 @r2_vm   .. vm:1 . . ... . ... %rs2 %rd
+@r1_vm   .. vm:1 . . ... . ... %rd
 @r2_zimm . zimm:11  . ... . ... %rs1 %rd
 
 @sfence_vma ... . .   ... . ... %rs2 %rs1
@@ -541,5 +542,21 @@ vfredmax_vs 000111 . . . 001 . 1010111 
@r_vm
 vfwredsum_vs110001 . . . 001 . 1010111 @r_vm
 vfwredosum_vs   110011 . . . 001 . 1010111 @r_vm
 
+vmand_mm011001 - . . 010 . 1010111 @r
+vmnand_mm   011101 - . . 010 . 1010111 @r
+vmandnot_mm 011000 - . . 010 . 1010111 @r
+vmor_mm 011010 - . . 010 . 1010111 @r
+vmxor_mm011011 - . . 010 . 1010111 @r
+vmnor_mm00 - . . 010 . 1010111 @r
+vmornot_mm  011100 - . . 010 . 1010111 @r
+vmxnor_mm   01 - . . 010 . 1010111 @r
+vmpopc_m010100 . . - 010 . 1010111 @r2_vm
+vmfirst_m   010101 . . - 010 . 1010111 @r2_vm
+vmsbf_m 010110 . . 1 010 . 1010111 @r2_vm
+vmsof_m 010110 . . 00010 010 . 1010111 @r2_vm
+vmsif_m 010110 . . 00011 010 . 1010111 @r2_vm
+viota_m 010110 . . 1 010 . 1010111 @r2_vm
+vid_v   010110 . 0 10001 010 . 1010111 @r1_vm
+
 vsetvli 0 ... . 111 . 1010111  @r2_zimm
 vsetvl  100 . . 111 . 1010111  @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c 
b/target/riscv/insn_trans/trans_rvv.inc.c
index 9a3d31b..85e435a 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -77,6 +77,17 @@ static bool trans_##INSN(DisasContext *ctx, arg_##INSN * a) \
 return true;   \
 }
 
+#define GEN_VECTOR_R1_VM(INSN) \
+static bool trans_##INSN(DisasContext *ctx, arg_##INSN * a) \
+{  \
+TCGv_i32 d  = tcg_const_i32(a->rd);\
+TCGv_i32 vm = tcg_const_i32(a->vm);\
+gen_helper_vector_##INSN(cpu_env, vm, d);\
+tcg_temp_free_i32(d);  \
+tcg_temp_free_i32(vm); \
+return true;   \
+}
+
 #define GEN_VECTOR_R_VM(INSN) \
 static bool trans_##INSN(DisasContext *ctx, arg_##INSN * a) \
 {  \
@@ -444,5 +455,21 @@ GEN_VECTOR_R_VM(vfredmax_vs)
 GEN_VECTOR_R_VM(vfwredsum_vs)
 GEN_VECTOR_R_VM(vfwredosum_vs)
 
+GEN_VECTOR_R(vmandnot_mm)
+GEN_VECTOR_R(vmand_mm)
+GEN_VECTOR_R(vmor_mm)
+GEN_VECTOR_R(vmxor_mm)
+GEN_VECTOR_R(vmornot_mm)
+GEN_VECTOR_R(vmnand_mm)
+GEN_VECTOR_R(vmnor_mm)
+GEN_VECTOR_R(vmxnor_mm)
+GEN_VECTOR_R2_VM(vmpopc_m)
+GEN_VECTOR_R2_VM(vmfirst_m)
+GEN_VECTOR_R2_VM(vmsbf_m)
+GEN_VECTOR_R2_VM(vmsof_m)
+GEN_VECTOR_R2_VM(vmsif_m)
+GEN_VECTOR_R2_VM(viota_m)
+GEN_VECTOR_R1_VM(vid_v)
+
 GEN_VECTOR_R2_ZIMM(vsetvli)
 

[Qemu-devel] [PATCH v2 11/17] RISC-V: add vector extension integer instructions part4, mul/div/merge

[liuzhiwei]

From: LIU Zhiwei 

Signed-off-by: LIU Zhiwei 
---
 target/riscv/helper.h   |   41 +
 target/riscv/insn32.decode  |   41 +
 target/riscv/insn_trans/trans_rvv.inc.c |   41 +
 target/riscv/vector_helper.c| 2838 +++
 4 files changed, 2961 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 7354b12..ab31ef7 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -229,5 +229,46 @@ DEF_HELPER_5(vector_vmsgtu_vi, void, env, i32, i32, i32, 
i32)
 DEF_HELPER_5(vector_vmsgt_vx, void, env, i32, i32, i32, i32)
 DEF_HELPER_5(vector_vmsgt_vi, void, env, i32, i32, i32, i32)
 
+DEF_HELPER_5(vector_vmul_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmul_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmulhsu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmulhsu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmulh_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmulh_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vdivu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vdivu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vdiv_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vdiv_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vremu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vremu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vrem_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vrem_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmulhu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmulhu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmadd_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmadd_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vnmsub_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vnmsub_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmacc_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmacc_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vnmsac_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vnmsac_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwmulu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwmulu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwmulsu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwmulsu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwmul_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwmul_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwmaccu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwmaccu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwmacc_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwmacc_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwmaccsu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwmaccsu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwmaccus_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmerge_vvm, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmerge_vxm, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmerge_vim, void, env, i32, i32, i32, i32)
+
 DEF_HELPER_4(vector_vsetvli, void, env, i32, i32, i32)
 DEF_HELPER_4(vector_vsetvl, void, env, i32, i32, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1ff0b08..6db18c5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -369,5 +369,46 @@ vmaxu_vx000110 . . . 100 . 1010111 
@r_vm
 vmax_vv 000111 . . . 000 . 1010111 @r_vm
 vmax_vx 000111 . . . 100 . 1010111 @r_vm
 
+vmul_vv 100101 . . . 010 . 1010111 @r_vm
+vmul_vx 100101 . . . 110 . 1010111 @r_vm
+vmulhsu_vv  100110 . . . 010 . 1010111 @r_vm
+vmulhsu_vx  100110 . . . 110 . 1010111 @r_vm
+vmulh_vv100111 . . . 010 . 1010111 @r_vm
+vmulh_vx100111 . . . 110 . 1010111 @r_vm
+vmulhu_vv   100100 . . . 010 . 1010111 @r_vm
+vmulhu_vx   100100 . . . 110 . 1010111 @r_vm
+vdivu_vv10 . . . 010 . 1010111 @r_vm
+vdivu_vx10 . . . 110 . 1010111 @r_vm
+vdiv_vv 11 . . . 010 . 1010111 @r_vm
+vdiv_vx 11 . . . 110 . 1010111 @r_vm
+vremu_vv100010 . . . 010 . 1010111 @r_vm
+vremu_vx100010 . . . 110 . 1010111 @r_vm
+vrem_vv 100011 . . . 010 . 1010111 @r_vm
+vrem_vx 100011 . . . 110 . 1010111 @r_vm
+vwmulu_vv   111000 . . . 010 . 1010111 @r_vm
+vwmulu_vx   111000 . . . 110 . 1010111 @r_vm
+vwmulsu_vv  111010 . . . 010 . 1010111 @r_vm
+vwmulsu_vx  111010 . . . 110 . 1010111 @r_vm
+vwmul_vv111011 . . . 010 . 1010111 @r_vm
+vwmul_vx111011 . 

[Qemu-devel] [PATCH v2 15/17] RISC-V: add vector extension reduction instructions

[liuzhiwei]

From: LIU Zhiwei 

Signed-off-by: LIU Zhiwei 
---
 target/riscv/helper.h   |   17 +
 target/riscv/insn32.decode  |   17 +
 target/riscv/insn_trans/trans_rvv.inc.c |   17 +
 target/riscv/vector_helper.c| 1275 +++
 4 files changed, 1326 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e2384eb..d36bd00 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -384,5 +384,22 @@ DEF_HELPER_4(vector_vfncvt_f_xu_v, void, env, i32, i32, 
i32)
 DEF_HELPER_4(vector_vfncvt_f_x_v, void, env, i32, i32, i32)
 DEF_HELPER_4(vector_vfncvt_f_f_v, void, env, i32, i32, i32)
 
+DEF_HELPER_5(vector_vredsum_vs, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vredand_vs, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfredsum_vs, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vredor_vs, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vredxor_vs, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfredosum_vs, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vredminu_vs, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vredmin_vs, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfredmin_vs, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vredmaxu_vs, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vredmax_vs, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfredmax_vs, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwredsumu_vs, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwredsum_vs, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfwredsum_vs, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfwredosum_vs, void, env, i32, i32, i32, i32)
+
 DEF_HELPER_4(vector_vsetvli, void, env, i32, i32, i32)
 DEF_HELPER_4(vector_vsetvl, void, env, i32, i32, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 256d8ea..3f63bc1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -524,5 +524,22 @@ vfncvt_f_xu_v   100010 . . 10010 001 . 1010111 
@r2_vm
 vfncvt_f_x_v100010 . . 10011 001 . 1010111 @r2_vm
 vfncvt_f_f_v100010 . . 10100 001 . 1010111 @r2_vm
 
+vredsum_vs  00 . . . 010 . 1010111 @r_vm
+vredand_vs  01 . . . 010 . 1010111 @r_vm
+vredor_vs   10 . . . 010 . 1010111 @r_vm
+vredxor_vs  11 . . . 010 . 1010111 @r_vm
+vredminu_vs 000100 . . . 010 . 1010111 @r_vm
+vredmin_vs  000101 . . . 010 . 1010111 @r_vm
+vredmaxu_vs 000110 . . . 010 . 1010111 @r_vm
+vredmax_vs  000111 . . . 010 . 1010111 @r_vm
+vwredsumu_vs11 . . . 000 . 1010111 @r_vm
+vwredsum_vs 110001 . . . 000 . 1010111 @r_vm
+vfredsum_vs 01 . . . 001 . 1010111 @r_vm
+vfredosum_vs11 . . . 001 . 1010111 @r_vm
+vfredmin_vs 000101 . . . 001 . 1010111 @r_vm
+vfredmax_vs 000111 . . . 001 . 1010111 @r_vm
+vfwredsum_vs110001 . . . 001 . 1010111 @r_vm
+vfwredosum_vs   110011 . . . 001 . 1010111 @r_vm
+
 vsetvli 0 ... . 111 . 1010111  @r2_zimm
 vsetvl  100 . . 111 . 1010111  @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c 
b/target/riscv/insn_trans/trans_rvv.inc.c
index e4d4576..9a3d31b 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -427,5 +427,22 @@ GEN_VECTOR_R2_VM(vfncvt_f_xu_v)
 GEN_VECTOR_R2_VM(vfncvt_f_x_v)
 GEN_VECTOR_R2_VM(vfncvt_f_f_v)
 
+GEN_VECTOR_R_VM(vredsum_vs)
+GEN_VECTOR_R_VM(vredand_vs)
+GEN_VECTOR_R_VM(vredor_vs)
+GEN_VECTOR_R_VM(vredxor_vs)
+GEN_VECTOR_R_VM(vredminu_vs)
+GEN_VECTOR_R_VM(vredmin_vs)
+GEN_VECTOR_R_VM(vredmaxu_vs)
+GEN_VECTOR_R_VM(vredmax_vs)
+GEN_VECTOR_R_VM(vwredsumu_vs)
+GEN_VECTOR_R_VM(vwredsum_vs)
+GEN_VECTOR_R_VM(vfredsum_vs)
+GEN_VECTOR_R_VM(vfredosum_vs)
+GEN_VECTOR_R_VM(vfredmin_vs)
+GEN_VECTOR_R_VM(vfredmax_vs)
+GEN_VECTOR_R_VM(vfwredsum_vs)
+GEN_VECTOR_R_VM(vfwredosum_vs)
+
 GEN_VECTOR_R2_ZIMM(vsetvli)
 GEN_VECTOR_R(vsetvl)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index fd2ecb7..4a9083b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -22720,4 +22720,1279 @@ void VECTOR_HELPER(vfncvt_f_f_v)(CPURISCVState *env, 
uint32_t vm,
 return;
 }
 
+/* vredsum.vs vd, vs2, vs1, vm # vd[0] = sum(vs1[0] , vs2[*]) */
+void VECTOR_HELPER(vredsum_vs)(CPURISCVState *env, uint32_t vm, uint32_t rs1,
+uint32_t rs2, uint32_t rd)
+{
 
+int width, lmul, vl, vlmax;
+int i, j, src2;
+uint64_t sum = 0;
+
+lmul = vector_get_lmul(env);
+vector_lmul_check_reg(env, lmul, rs2, false);
+
+if (vector_vtype_ill(env) || vector_overlap_vm_common(lmul, vm, rd)) {
+riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+return;
+}
+if 

[Qemu-devel] [PATCH v2 10/17] RISC-V: add vector extension integer instructions part3, cmp/min/max

[liuzhiwei]

From: LIU Zhiwei 

Signed-off-by: LIU Zhiwei 
---
 target/riscv/helper.h   |   29 +
 target/riscv/insn32.decode  |   29 +
 target/riscv/insn_trans/trans_rvv.inc.c |   29 +
 target/riscv/vector_helper.c| 2280 +++
 4 files changed, 2367 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 28863e2..7354b12 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -200,5 +200,34 @@ DEF_HELPER_5(vector_vnsra_vv, void, env, i32, i32, i32, 
i32)
 DEF_HELPER_5(vector_vnsra_vx, void, env, i32, i32, i32, i32)
 DEF_HELPER_5(vector_vnsra_vi, void, env, i32, i32, i32, i32)
 
+DEF_HELPER_5(vector_vminu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vminu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmin_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmin_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmaxu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmaxu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmax_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmax_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmseq_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmseq_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmseq_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmsne_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmsne_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmsne_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmsltu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmsltu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmslt_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmslt_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmsleu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmsleu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmsleu_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmsle_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmsle_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmsle_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmsgtu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmsgtu_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmsgt_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmsgt_vi, void, env, i32, i32, i32, i32)
+
 DEF_HELPER_4(vector_vsetvli, void, env, i32, i32, i32)
 DEF_HELPER_4(vector_vsetvl, void, env, i32, i32, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 19710f5..1ff0b08 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -340,5 +340,34 @@ vnsra_vv101101 . . . 000 . 1010111 
@r_vm
 vnsra_vx101101 . . . 100 . 1010111 @r_vm
 vnsra_vi101101 . . . 011 . 1010111 @r_vm
 
+vmseq_vv011000 . . . 000 . 1010111 @r_vm
+vmseq_vx011000 . . . 100 . 1010111 @r_vm
+vmseq_vi011000 . . . 011 . 1010111 @r_vm
+vmsne_vv011001 . . . 000 . 1010111 @r_vm
+vmsne_vx011001 . . . 100 . 1010111 @r_vm
+vmsne_vi011001 . . . 011 . 1010111 @r_vm
+vmsltu_vv   011010 . . . 000 . 1010111 @r_vm
+vmsltu_vx   011010 . . . 100 . 1010111 @r_vm
+vmslt_vv011011 . . . 000 . 1010111 @r_vm
+vmslt_vx011011 . . . 100 . 1010111 @r_vm
+vmsleu_vv   011100 . . . 000 . 1010111 @r_vm
+vmsleu_vx   011100 . . . 100 . 1010111 @r_vm
+vmsleu_vi   011100 . . . 011 . 1010111 @r_vm
+vmsle_vv011101 . . . 000 . 1010111 @r_vm
+vmsle_vx011101 . . . 100 . 1010111 @r_vm
+vmsle_vi011101 . . . 011 . 1010111 @r_vm
+vmsgtu_vx   00 . . . 100 . 1010111 @r_vm
+vmsgtu_vi   00 . . . 011 . 1010111 @r_vm
+vmsgt_vx01 . . . 100 . 1010111 @r_vm
+vmsgt_vi01 . . . 011 . 1010111 @r_vm
+vminu_vv000100 . . . 000 . 1010111 @r_vm
+vminu_vx000100 . . . 100 . 1010111 @r_vm
+vmin_vv 000101 . . . 000 . 1010111 @r_vm
+vmin_vx 000101 . . . 100 . 1010111 @r_vm
+vmaxu_vv000110 . . . 000 . 1010111 @r_vm
+vmaxu_vx000110 . . . 100 . 1010111 @r_vm
+vmax_vv 000111 . . . 000 . 1010111 @r_vm
+vmax_vx 000111 . . . 100 . 1010111 @r_vm
+
 vsetvli 0 ... . 111 . 1010111  @r2_zimm
 vsetvl  100 . . 111 . 1010111  @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c 
b/target/riscv/insn_trans/trans_rvv.inc.c
index 6af29d0..cd5ab07 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -229,5 +229,34 @@ 

[Qemu-devel] [PATCH v2 13/17] RISC-V: add vector extension float instruction part1, add/sub/mul/div

[liuzhiwei]

From: LIU Zhiwei 

Signed-off-by: LIU Zhiwei 
---
 target/riscv/helper.h   |   37 +
 target/riscv/insn32.decode  |   37 +
 target/riscv/insn_trans/trans_rvv.inc.c |   37 +
 target/riscv/vector_helper.c| 2645 +++
 4 files changed, 2756 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index ff6002e..d2c8684 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -307,5 +307,42 @@ DEF_HELPER_5(vector_vnclip_vv, void, env, i32, i32, i32, 
i32)
 DEF_HELPER_5(vector_vnclip_vx, void, env, i32, i32, i32, i32)
 DEF_HELPER_5(vector_vnclip_vi, void, env, i32, i32, i32, i32)
 
+DEF_HELPER_5(vector_vfadd_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfadd_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfsub_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfsub_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfrsub_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfwadd_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfwadd_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfwadd_wv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfwadd_wf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfwsub_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfwsub_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfwsub_wv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfwsub_wf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfmul_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfmul_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfdiv_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfdiv_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfrdiv_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfwmul_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfwmul_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfmacc_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfmacc_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfnmacc_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfnmacc_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfmsac_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfmsac_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfnmsac_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfnmsac_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfmadd_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfmadd_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfnmadd_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfnmadd_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfmsub_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfmsub_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfnmsub_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfnmsub_vf, void, env, i32, i32, i32, i32)
+
 DEF_HELPER_4(vector_vsetvli, void, env, i32, i32, i32)
 DEF_HELPER_4(vector_vsetvl, void, env, i32, i32, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a82e53e..31868ab 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -447,5 +447,42 @@ vnclip_vv   10 . . . 000 . 1010111 
@r_vm
 vnclip_vx   10 . . . 100 . 1010111 @r_vm
 vnclip_vi   10 . . . 011 . 1010111 @r_vm
 
+vfadd_vv00 . . . 001 . 1010111 @r_vm
+vfadd_vf00 . . . 101 . 1010111 @r_vm
+vfsub_vv10 . . . 001 . 1010111 @r_vm
+vfsub_vf10 . . . 101 . 1010111 @r_vm
+vfrsub_vf   100111 . . . 101 . 1010111 @r_vm
+vfwadd_vv   11 . . . 001 . 1010111 @r_vm
+vfwadd_vf   11 . . . 101 . 1010111 @r_vm
+vfwadd_wv   110100 . . . 001 . 1010111 @r_vm
+vfwadd_wf   110100 . . . 101 . 1010111 @r_vm
+vfwsub_vv   110010 . . . 001 . 1010111 @r_vm
+vfwsub_vf   110010 . . . 101 . 1010111 @r_vm
+vfwsub_wv   110110 . . . 001 . 1010111 @r_vm
+vfwsub_wf   110110 . . . 101 . 1010111 @r_vm
+vfmul_vv100100 . . . 001 . 1010111 @r_vm
+vfmul_vf100100 . . . 101 . 1010111 @r_vm
+vfdiv_vv10 . . . 001 . 1010111 @r_vm
+vfdiv_vf10 . . . 101 . 1010111 @r_vm
+vfrdiv_vf   11 . . . 101 . 1010111 @r_vm
+vfwmul_vv   111000 . . . 001 . 1010111 @r_vm
+vfwmul_vf   111000 . . . 101 . 1010111 @r_vm
+vfmacc_vf   101100 . . . 101 . 1010111 @r_vm
+vfmacc_vv   101100 . . . 001 . 1010111 @r_vm
+vfnmacc_vv  101101 . . . 001 . 1010111 @r_vm
+vfnmacc_vf  101101 . . . 101 . 1010111 @r_vm
+vfmsac_vv   101110 . . . 001 . 1010111 @r_vm
+vfmsac_vf   

[Qemu-devel] [PATCH v2 14/17] RISC-V: add vector extension float instructions part2, sqrt/cmp/cvt/others

[liuzhiwei]

From: LIU Zhiwei 

Signed-off-by: LIU Zhiwei 
---
 target/riscv/helper.h   |   40 +
 target/riscv/insn32.decode  |   40 +
 target/riscv/insn_trans/trans_rvv.inc.c |   54 +
 target/riscv/vector_helper.c| 2962 +++
 4 files changed, 3096 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index d2c8684..e2384eb 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -344,5 +344,45 @@ DEF_HELPER_5(vector_vfmsub_vf, void, env, i32, i32, i32, 
i32)
 DEF_HELPER_5(vector_vfnmsub_vv, void, env, i32, i32, i32, i32)
 DEF_HELPER_5(vector_vfnmsub_vf, void, env, i32, i32, i32, i32)
 
+DEF_HELPER_4(vector_vfsqrt_v, void, env, i32, i32, i32)
+DEF_HELPER_5(vector_vfmin_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfmin_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfmax_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfmax_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfsgnj_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfsgnj_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfsgnjn_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfsgnjn_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfsgnjx_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfsgnjx_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmfeq_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmfeq_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmfne_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmfne_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmfle_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmfle_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmflt_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmflt_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmfgt_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmfge_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmford_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vmford_vf, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vfmerge_vfm, void, env, i32, i32, i32, i32)
+DEF_HELPER_4(vector_vfclass_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vfcvt_xu_f_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vfcvt_x_f_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vfcvt_f_xu_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vfcvt_f_x_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vfwcvt_xu_f_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vfwcvt_x_f_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vfwcvt_f_xu_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vfwcvt_f_x_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vfwcvt_f_f_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vfncvt_xu_f_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vfncvt_x_f_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vfncvt_f_xu_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vfncvt_f_x_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vfncvt_f_f_v, void, env, i32, i32, i32)
+
 DEF_HELPER_4(vector_vsetvli, void, env, i32, i32, i32)
 DEF_HELPER_4(vector_vsetvl, void, env, i32, i32, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 31868ab..256d8ea 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -67,6 +67,7 @@
 @r_wdvm  . wd:1 vm:1 . . ... . ... %rs2 %rs1 %rd
 @r_nfvm  nf:3 ... vm:1 . . ... . ... %rs2 %rs1 %rd
 @r2_nfvm nf:3 ... vm:1 . . ... . ... %rs1 %rd
+@r2_vm   .. vm:1 . . ... . ... %rs2 %rd
 @r2_zimm . zimm:11  . ... . ... %rs1 %rd
 
 @sfence_vma ... . .   ... . ... %rs2 %rs1
@@ -483,6 +484,45 @@ vfmsub_vv   101010 . . . 001 . 1010111 
@r_vm
 vfmsub_vf   101010 . . . 101 . 1010111 @r_vm
 vfnmsub_vv  101011 . . . 001 . 1010111 @r_vm
 vfnmsub_vf  101011 . . . 101 . 1010111 @r_vm
+vfsqrt_v100011 . . 0 001 . 1010111 @r2_vm
+vfmin_vv000100 . . . 001 . 1010111 @r_vm
+vfmin_vf000100 . . . 101 . 1010111 @r_vm
+vfmax_vv000110 . . . 001 . 1010111 @r_vm
+vfmax_vf000110 . . . 101 . 1010111 @r_vm
+vfsgnj_vv   001000 . . . 001 . 1010111 @r_vm
+vfsgnj_vf   001000 . . . 101 . 1010111 @r_vm
+vfsgnjn_vv  001001 . . . 001 . 1010111 @r_vm
+vfsgnjn_vf  001001 . . . 101 . 1010111 @r_vm
+vfsgnjx_vv  001010 . . . 001 . 1010111 @r_vm
+vfsgnjx_vf  001010 . . . 101 . 1010111 @r_vm
+vmfeq_vv011000 . . . 001 . 1010111 @r_vm
+vmfeq_vf011000 . . . 101 . 1010111 @r_vm
+vmfne_vv011100 . . . 001 . 1010111 @r_vm
+vmfne_vf011100 . . . 101 . 1010111 @r_vm
+vmflt_vv011011 . . 

[Qemu-devel] [PATCH v2 08/17] RISC-V: add vector extension integer instructions part1, add/sub/adc/sbc

[liuzhiwei]

From: LIU Zhiwei 

Signed-off-by: LIU Zhiwei 
---
 target/riscv/helper.h   |   36 +
 target/riscv/insn32.decode  |   35 +
 target/riscv/insn_trans/trans_rvv.inc.c |   49 +
 target/riscv/vector_helper.c| 2335 +++
 4 files changed, 2455 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index c107925..31e20dc 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -121,6 +121,7 @@ DEF_HELPER_6(vector_vsuxb_v, void, env, i32, i32, i32, i32, 
i32)
 DEF_HELPER_6(vector_vsuxh_v, void, env, i32, i32, i32, i32, i32)
 DEF_HELPER_6(vector_vsuxw_v, void, env, i32, i32, i32, i32, i32)
 DEF_HELPER_6(vector_vsuxe_v, void, env, i32, i32, i32, i32, i32)
+
 DEF_HELPER_6(vector_vamoswapw_v, void, env, i32, i32, i32, i32, i32)
 DEF_HELPER_6(vector_vamoswapd_v, void, env, i32, i32, i32, i32, i32)
 DEF_HELPER_6(vector_vamoaddw_v, void, env, i32, i32, i32, i32, i32)
@@ -139,5 +140,40 @@ DEF_HELPER_6(vector_vamominuw_v, void, env, i32, i32, i32, 
i32, i32)
 DEF_HELPER_6(vector_vamominud_v, void, env, i32, i32, i32, i32, i32)
 DEF_HELPER_6(vector_vamomaxuw_v, void, env, i32, i32, i32, i32, i32)
 DEF_HELPER_6(vector_vamomaxud_v, void, env, i32, i32, i32, i32, i32)
+
+DEF_HELPER_4(vector_vadc_vvm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vadc_vxm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vadc_vim, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmadc_vvm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmadc_vxm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmadc_vim, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vsbc_vvm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vsbc_vxm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmsbc_vvm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmsbc_vxm, void, env, i32, i32, i32)
+DEF_HELPER_5(vector_vadd_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vadd_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vadd_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsub_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsub_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vrsub_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vrsub_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwaddu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwaddu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwadd_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwadd_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwsubu_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwsubu_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwsub_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwsub_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwaddu_wv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwaddu_wx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwadd_wv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwadd_wx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwsubu_wv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwsubu_wx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwsub_wv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vwsub_wx, void, env, i32, i32, i32, i32)
+
 DEF_HELPER_4(vector_vsetvli, void, env, i32, i32, i32)
 DEF_HELPER_4(vector_vsetvl, void, env, i32, i32, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 48e7661..fc7e498 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -63,6 +63,7 @@
 @r_rm...   . . ... . ... %rs2 %rs1 %rm %rd
 @r2_rm   ...   . . ... . ... %rs1 %rm %rd
 @r2  ...   . . ... . ... %rs1 %rd
+@r_vm.. vm:1 . . ... . ... %rs2 %rs1 %rd
 @r_wdvm  . wd:1 vm:1 . . ... . ... %rs2 %rs1 %rd
 @r_nfvm  nf:3 ... vm:1 . . ... . ... %rs2 %rs1 %rd
 @r2_nfvm nf:3 ... vm:1 . . ... . ... %rs1 %rd
@@ -280,5 +281,39 @@ vamomaxuw_v 11100 . . . . 110 . 010 
@r_wdvm
 vamomaxud_v 11100 . . . . 111 . 010 @r_wdvm
 
 #*** new major opcode OP-V ***
+vadd_vv 00 . . . 000 . 1010111 @r_vm
+vadd_vx 00 . . . 100 . 1010111 @r_vm
+vadd_vi 00 . . . 011 . 1010111 @r_vm
+vsub_vv 10 . . . 000 . 1010111 @r_vm
+vsub_vx 10 . . . 100 . 1010111 @r_vm
+vrsub_vx11 . . . 100 . 1010111 @r_vm
+vrsub_vi11 . . . 011 . 1010111 @r_vm
+vwaddu_vv   11 . . . 010 . 1010111 @r_vm
+vwaddu_vx   11 . . . 110 . 1010111 @r_vm
+vwadd_vv110001 . . . 010 . 1010111 @r_vm
+vwadd_vx110001 . . . 110 . 1010111 @r_vm
+vwsubu_vv   110010 . . . 010 . 1010111 @r_vm
+vwsubu_vx   110010 . . . 110 . 

[Qemu-devel] [PATCH v2 09/17] RISC-V: add vector extension integer instructions part2, bit/shift

[liuzhiwei]

From: LIU Zhiwei 

Signed-off-by: LIU Zhiwei 
---
 target/riscv/helper.h   |   25 +
 target/riscv/insn32.decode  |   25 +
 target/riscv/insn_trans/trans_rvv.inc.c |   25 +
 target/riscv/vector_helper.c| 1477 +++
 4 files changed, 1552 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 31e20dc..28863e2 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -175,5 +175,30 @@ DEF_HELPER_5(vector_vwsubu_wx, void, env, i32, i32, i32, 
i32)
 DEF_HELPER_5(vector_vwsub_wv, void, env, i32, i32, i32, i32)
 DEF_HELPER_5(vector_vwsub_wx, void, env, i32, i32, i32, i32)
 
+DEF_HELPER_5(vector_vand_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vand_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vand_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vor_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vor_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vor_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vxor_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vxor_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vxor_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsll_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsll_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsll_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsrl_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsrl_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsrl_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsra_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsra_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsra_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vnsrl_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vnsrl_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vnsrl_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vnsra_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vnsra_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vnsra_vi, void, env, i32, i32, i32, i32)
+
 DEF_HELPER_4(vector_vsetvli, void, env, i32, i32, i32)
 DEF_HELPER_4(vector_vsetvl, void, env, i32, i32, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index fc7e498..19710f5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -315,5 +315,30 @@ vsbc_vxm010010 1 . . 100 . 1010111 @r
 vmsbc_vvm   010011 1 . . 000 . 1010111 @r
 vmsbc_vxm   010011 1 . . 100 . 1010111 @r
 
+vand_vv 001001 . . . 000 . 1010111 @r_vm
+vand_vx 001001 . . . 100 . 1010111 @r_vm
+vand_vi 001001 . . . 011 . 1010111 @r_vm
+vor_vv  001010 . . . 000 . 1010111 @r_vm
+vor_vx  001010 . . . 100 . 1010111 @r_vm
+vor_vi  001010 . . . 011 . 1010111 @r_vm
+vxor_vv 001011 . . . 000 . 1010111 @r_vm
+vxor_vx 001011 . . . 100 . 1010111 @r_vm
+vxor_vi 001011 . . . 011 . 1010111 @r_vm
+vsll_vv 100101 . . . 000 . 1010111 @r_vm
+vsll_vx 100101 . . . 100 . 1010111 @r_vm
+vsll_vi 100101 . . . 011 . 1010111 @r_vm
+vsrl_vv 101000 . . . 000 . 1010111 @r_vm
+vsrl_vx 101000 . . . 100 . 1010111 @r_vm
+vsrl_vi 101000 . . . 011 . 1010111 @r_vm
+vsra_vv 101001 . . . 000 . 1010111 @r_vm
+vsra_vx 101001 . . . 100 . 1010111 @r_vm
+vsra_vi 101001 . . . 011 . 1010111 @r_vm
+vnsrl_vv101100 . . . 000 . 1010111 @r_vm
+vnsrl_vx101100 . . . 100 . 1010111 @r_vm
+vnsrl_vi101100 . . . 011 . 1010111 @r_vm
+vnsra_vv101101 . . . 000 . 1010111 @r_vm
+vnsra_vx101101 . . . 100 . 1010111 @r_vm
+vnsra_vi101101 . . . 011 . 1010111 @r_vm
+
 vsetvli 0 ... . 111 . 1010111  @r2_zimm
 vsetvl  100 . . 111 . 1010111  @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c 
b/target/riscv/insn_trans/trans_rvv.inc.c
index a1c1960..6af29d0 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -204,5 +204,30 @@ GEN_VECTOR_R_VM(vwsubu_wx)
 GEN_VECTOR_R_VM(vwsub_wv)
 GEN_VECTOR_R_VM(vwsub_wx)
 
+GEN_VECTOR_R_VM(vand_vv)
+GEN_VECTOR_R_VM(vand_vx)
+GEN_VECTOR_R_VM(vand_vi)
+GEN_VECTOR_R_VM(vor_vv)
+GEN_VECTOR_R_VM(vor_vx)
+GEN_VECTOR_R_VM(vor_vi)
+GEN_VECTOR_R_VM(vxor_vv)
+GEN_VECTOR_R_VM(vxor_vx)
+GEN_VECTOR_R_VM(vxor_vi)
+GEN_VECTOR_R_VM(vsll_vv)
+GEN_VECTOR_R_VM(vsll_vx)
+GEN_VECTOR_R_VM(vsll_vi)
+GEN_VECTOR_R_VM(vsrl_vv)
+GEN_VECTOR_R_VM(vsrl_vx)
+GEN_VECTOR_R_VM(vsrl_vi)
+GEN_VECTOR_R_VM(vsra_vv)
+GEN_VECTOR_R_VM(vsra_vx)

[Qemu-devel] [PATCH v2 06/17] RISC-V: add vector extension fault-only-first implementation

[liuzhiwei]

From: LIU Zhiwei 

Signed-off-by: LIU Zhiwei 
---
 linux-user/riscv/cpu_loop.c |   7 +
 target/riscv/cpu_helper.c   |   7 +
 target/riscv/helper.h   |   7 +
 target/riscv/insn32.decode  |   7 +
 target/riscv/insn_trans/trans_rvv.inc.c |   7 +
 target/riscv/vector_helper.c| 567 
 6 files changed, 602 insertions(+)

diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
index 12aa3c0..d673fa5 100644
--- a/linux-user/riscv/cpu_loop.c
+++ b/linux-user/riscv/cpu_loop.c
@@ -41,6 +41,13 @@ void cpu_loop(CPURISCVState *env)
 sigcode = 0;
 sigaddr = 0;
 
+if (env->foflag) {
+if (env->vfp.vl != 0) {
+env->foflag = false;
+env->pc += 4;
+continue;
+}
+}
 switch (trapnr) {
 case EXCP_INTERRUPT:
 /* just indicate that signals should be handled asap */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e32b612..405caf6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -521,6 +521,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
 [PRV_H] = RISCV_EXCP_H_ECALL,
 [PRV_M] = RISCV_EXCP_M_ECALL
 };
+if (env->foflag) {
+if (env->vfp.vl != 0) {
+env->foflag = false;
+env->pc += 4;
+return;
+}
+}
 
 if (!async) {
 /* set tval to badaddr for traps with address information */
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index f77c392..973342f 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -84,6 +84,13 @@ DEF_HELPER_5(vector_vle_v, void, env, i32, i32, i32, i32)
 DEF_HELPER_5(vector_vlbu_v, void, env, i32, i32, i32, i32)
 DEF_HELPER_5(vector_vlhu_v, void, env, i32, i32, i32, i32)
 DEF_HELPER_5(vector_vlwu_v, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vlbff_v, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vlhff_v, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vlwff_v, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vleff_v, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vlbuff_v, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vlhuff_v, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vlwuff_v, void, env, i32, i32, i32, i32)
 DEF_HELPER_5(vector_vsb_v, void, env, i32, i32, i32, i32)
 DEF_HELPER_5(vector_vsh_v, void, env, i32, i32, i32, i32)
 DEF_HELPER_5(vector_vsw_v, void, env, i32, i32, i32, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b8a3d8a..b286997 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -218,6 +218,13 @@ vle_v  ... 000 . 0 . 111 . 111 @r2_nfvm
 vlbu_v ... 000 . 0 . 000 . 111 @r2_nfvm
 vlhu_v ... 000 . 0 . 101 . 111 @r2_nfvm
 vlwu_v ... 000 . 0 . 110 . 111 @r2_nfvm
+vlbff_v... 100 . 1 . 000 . 111 @r2_nfvm
+vlhff_v... 100 . 1 . 101 . 111 @r2_nfvm
+vlwff_v... 100 . 1 . 110 . 111 @r2_nfvm
+vleff_v... 000 . 1 . 111 . 111 @r2_nfvm
+vlbuff_v   ... 000 . 1 . 000 . 111 @r2_nfvm
+vlhuff_v   ... 000 . 1 . 101 . 111 @r2_nfvm
+vlwuff_v   ... 000 . 1 . 110 . 111 @r2_nfvm
 vsb_v  ... 000 . 0 . 000 . 0100111 @r2_nfvm
 vsh_v  ... 000 . 0 . 101 . 0100111 @r2_nfvm
 vsw_v  ... 000 . 0 . 110 . 0100111 @r2_nfvm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c 
b/target/riscv/insn_trans/trans_rvv.inc.c
index 16b1f90..bd83885 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -80,6 +80,13 @@ GEN_VECTOR_R2_NFVM(vle_v)
 GEN_VECTOR_R2_NFVM(vlbu_v)
 GEN_VECTOR_R2_NFVM(vlhu_v)
 GEN_VECTOR_R2_NFVM(vlwu_v)
+GEN_VECTOR_R2_NFVM(vlbff_v)
+GEN_VECTOR_R2_NFVM(vlhff_v)
+GEN_VECTOR_R2_NFVM(vlwff_v)
+GEN_VECTOR_R2_NFVM(vleff_v)
+GEN_VECTOR_R2_NFVM(vlbuff_v)
+GEN_VECTOR_R2_NFVM(vlhuff_v)
+GEN_VECTOR_R2_NFVM(vlwuff_v)
 GEN_VECTOR_R2_NFVM(vsb_v)
 GEN_VECTOR_R2_NFVM(vsh_v)
 GEN_VECTOR_R2_NFVM(vsw_v)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 62e4d2e..0ac8c74 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2762,3 +2762,570 @@ void VECTOR_HELPER(vsuxe_v)(CPURISCVState *env, 
uint32_t nf, uint32_t vm,
 env->vfp.vstart = 0;
 }
 
+void VECTOR_HELPER(vlbuff_v)(CPURISCVState *env, uint32_t nf, uint32_t vm,
+uint32_t rs1, uint32_t rd)
+{
+int i, j, k, vl, vlmax, lmul, width, dest, read;
+
+vl = env->vfp.vl;
+
+lmul   = vector_get_lmul(env);
+width = vector_get_width(env);
+vlmax = vector_get_vlmax(env);
+
+if (vector_vtype_ill(env) || vector_overlap_vm_common(lmul, vm, rd)) {
+riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+

[Qemu-devel] [PATCH v2 17/17] RISC-V: add vector extension premutation instructions

[liuzhiwei]

From: LIU Zhiwei 

Signed-off-by: LIU Zhiwei 
---
 target/riscv/helper.h   |   15 +
 target/riscv/insn32.decode  |   16 +
 target/riscv/insn_trans/trans_rvv.inc.c |   15 +
 target/riscv/vector_helper.c| 1068 +++
 4 files changed, 1114 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 337ac2e..2d153ce 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -417,5 +417,20 @@ DEF_HELPER_3(vector_vid_v, void, env, i32, i32)
 DEF_HELPER_4(vector_vmpopc_m, void, env, i32, i32, i32)
 DEF_HELPER_4(vector_vmfirst_m, void, env, i32, i32, i32)
 
+DEF_HELPER_4(vector_vext_x_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmv_s_x, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vfmv_f_s, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vfmv_s_f, void, env, i32, i32, i32)
+DEF_HELPER_5(vector_vslideup_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vslideup_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vslide1up_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vslidedown_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vslidedown_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vslide1down_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vrgather_vv, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vrgather_vx, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vrgather_vi, void, env, i32, i32, i32, i32)
+DEF_HELPER_4(vector_vcompress_vm, void, env, i32, i32, i32)
+
 DEF_HELPER_4(vector_vsetvli, void, env, i32, i32, i32)
 DEF_HELPER_4(vector_vsetvl, void, env, i32, i32, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1de776b..c98915b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -558,5 +558,21 @@ vmsif_m 010110 . . 00011 010 . 1010111 
@r2_vm
 viota_m 010110 . . 1 010 . 1010111 @r2_vm
 vid_v   010110 . 0 10001 010 . 1010111 @r1_vm
 
+vext_x_v001100 1 . . 010 . 1010111 @r
+vmv_s_x 001101 1 . . 110 . 1010111 @r
+vfmv_f_s001100 1 . . 001 . 1010111 @r
+vfmv_s_f001101 1 . . 101 . 1010111 @r
+vslideup_vx 001110 . . . 100 . 1010111 @r_vm
+vslideup_vi 001110 . . . 011 . 1010111 @r_vm
+vslide1up_vx001110 . . . 110 . 1010111 @r_vm
+vslidedown_vx   00 . . . 100 . 1010111 @r_vm
+vslidedown_vi   00 . . . 011 . 1010111 @r_vm
+vslide1down_vx  00 . . . 110 . 1010111 @r_vm
+vrgather_vv 001100 . . . 000 . 1010111 @r_vm
+vrgather_vx 001100 . . . 100 . 1010111 @r_vm
+vrgather_vi 001100 . . . 011 . 1010111 @r_vm
+vcompress_vm010111 - . . 010 . 1010111 @r
+
+
 vsetvli 0 ... . 111 . 1010111  @r2_zimm
 vsetvl  100 . . 111 . 1010111  @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c 
b/target/riscv/insn_trans/trans_rvv.inc.c
index 85e435a..1774d1f 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -471,5 +471,20 @@ GEN_VECTOR_R2_VM(vmsif_m)
 GEN_VECTOR_R2_VM(viota_m)
 GEN_VECTOR_R1_VM(vid_v)
 
+GEN_VECTOR_R(vmv_s_x)
+GEN_VECTOR_R(vfmv_f_s)
+GEN_VECTOR_R(vfmv_s_f)
+GEN_VECTOR_R(vext_x_v)
+GEN_VECTOR_R_VM(vslideup_vx)
+GEN_VECTOR_R_VM(vslideup_vi)
+GEN_VECTOR_R_VM(vslide1up_vx)
+GEN_VECTOR_R_VM(vslidedown_vx)
+GEN_VECTOR_R_VM(vslidedown_vi)
+GEN_VECTOR_R_VM(vslide1down_vx)
+GEN_VECTOR_R_VM(vrgather_vv)
+GEN_VECTOR_R_VM(vrgather_vx)
+GEN_VECTOR_R_VM(vrgather_vi)
+GEN_VECTOR_R(vcompress_vm)
+
 GEN_VECTOR_R2_ZIMM(vsetvli)
 GEN_VECTOR_R(vsetvl)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 9e15df9..0a25996 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1010,6 +1010,26 @@ static inline bool vector_overlap_dstgp_srcgp(int rd, 
int dlen, int rs,
 return false;
 }
 
+/* fetch unsigned element by width */
+static inline uint64_t vector_get_iu_elem(CPURISCVState *env, uint32_t width,
+uint32_t rs2, uint32_t index)
+{
+uint64_t elem;
+if (width == 8) {
+elem = env->vfp.vreg[rs2].u8[index];
+} else if (width == 16) {
+elem = env->vfp.vreg[rs2].u16[index];
+} else if (width == 32) {
+elem = env->vfp.vreg[rs2].u32[index];
+} else if (width == 64) {
+elem = env->vfp.vreg[rs2].u64[index];
+} else { /* the max of (XLEN, FLEN) is no bigger than 64 */
+helper_raise_exception(env, RISCV_EXCP_ILLEGAL_INST);
+return 0;
+}
+return elem;
+}
+
 static inline void vector_get_layout(CPURISCVState *env, int width, int lmul,
 int index, int *idx, int *pos)
 {
@@ -24631,3 +24651,1051 @@ void VECTOR_HELPER(vid_v)(CPURISCVState *env, 
uint32_t vm, uint32_t rd)
 env->vfp.vstart = 0;
 return;
 }
+
+/* vfmv.f.s 

[Qemu-devel] [PATCH v2 05/17] RISC-V: add vector extension load and store instructions

[liuzhiwei]

From: LIU Zhiwei 

Signed-off-by: LIU Zhiwei 
---
 target/riscv/helper.h   |   37 +
 target/riscv/insn32.decode  |   46 +
 target/riscv/insn_trans/trans_rvv.inc.c |   70 +
 target/riscv/vector_helper.c| 2638 +++
 4 files changed, 2791 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 652f8c3..f77c392 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -77,5 +77,42 @@ DEF_HELPER_1(wfi, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 #endif
 /* Vector functions */
+DEF_HELPER_5(vector_vlb_v, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vlh_v, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vlw_v, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vle_v, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vlbu_v, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vlhu_v, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vlwu_v, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsb_v, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsh_v, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vsw_v, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vector_vse_v, void, env, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vlsb_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vlsh_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vlsw_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vlse_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vlsbu_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vlshu_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vlswu_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vssb_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vssh_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vssw_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vsse_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vlxb_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vlxh_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vlxw_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vlxe_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vlxbu_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vlxhu_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vlxwu_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vsxb_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vsxh_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vsxw_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vsxe_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vsuxb_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vsuxh_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vsuxw_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vsuxe_v, void, env, i32, i32, i32, i32, i32)
 DEF_HELPER_4(vector_vsetvli, void, env, i32, i32, i32)
 DEF_HELPER_4(vector_vsetvl, void, env, i32, i32, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5dc009c..b8a3d8a 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -25,6 +25,7 @@
 %sh1020:10
 %csr20:12
 %rm 12:3
+%nf 29:3
 
 # immediates:
 %imm_i20:s12
@@ -62,6 +63,8 @@
 @r_rm...   . . ... . ... %rs2 %rs1 %rm %rd
 @r2_rm   ...   . . ... . ... %rs1 %rm %rd
 @r2  ...   . . ... . ... %rs1 %rd
+@r_nfvm  nf:3 ... vm:1 . . ... . ... %rs2 %rs1 %rd
+@r2_nfvm nf:3 ... vm:1 . . ... . ... %rs1 %rd
 @r2_zimm . zimm:11  . ... . ... %rs1 %rd
 
 @sfence_vma ... . .   ... . ... %rs2 %rs1
@@ -206,5 +209,48 @@ fcvt_d_w   1101001  0 . ... . 1010011 @r2_rm
 fcvt_d_wu  1101001  1 . ... . 1010011 @r2_rm
 
 # *** RV32V Extension ***
+
+# *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
+vlb_v  ... 100 . 0 . 000 . 111 @r2_nfvm
+vlh_v  ... 100 . 0 . 101 . 111 @r2_nfvm
+vlw_v  ... 100 . 0 . 110 . 111 @r2_nfvm
+vle_v  ... 000 . 0 . 111 . 111 @r2_nfvm
+vlbu_v ... 000 . 0 . 000 . 111 @r2_nfvm
+vlhu_v ... 000 . 0 . 101 . 111 @r2_nfvm
+vlwu_v ... 000 . 0 . 110 . 111 @r2_nfvm
+vsb_v  ... 000 . 0 . 000 . 0100111 @r2_nfvm
+vsh_v  ... 000 . 0 . 101 . 0100111 @r2_nfvm
+vsw_v  ... 000 . 0 . 110 . 0100111 @r2_nfvm
+vse_v  ... 000 . 0 . 111 . 0100111 @r2_nfvm
+
+vlsb_v ... 110 . . . 000 . 111 @r_nfvm
+vlsh_v ... 110 . . . 101 . 111 @r_nfvm
+vlsw_v ... 110 . . . 110 . 111 @r_nfvm
+vlse_v ... 010 . . . 111 . 111 @r_nfvm
+vlsbu_v... 010 . . . 000 . 111 @r_nfvm
+vlshu_v

[Qemu-devel] [PATCH v2 04/17] RISC-V: add vector extension configure instruction

[liuzhiwei]

From: LIU Zhiwei 

Signed-off-by: LIU Zhiwei 
---
 target/riscv/Makefile.objs  |   2 +-
 target/riscv/helper.h   |   3 +
 target/riscv/insn32.decode  |   5 ++
 target/riscv/insn_trans/trans_rvv.inc.c |  46 
 target/riscv/translate.c|   1 +
 target/riscv/vector_helper.c| 126 
 6 files changed, 182 insertions(+), 1 deletion(-)
 create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
 create mode 100644 target/riscv/vector_helper.c

diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index b1c79bc..d577cef 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -1,4 +1,4 @@
-obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o 
gdbstub.o pmp.o
+obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o 
vector_helper.o gdbstub.o pmp.o
 
 DECODETREE = $(SRC_PATH)/scripts/decodetree.py
 
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index debb22a..652f8c3 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -76,3 +76,6 @@ DEF_HELPER_2(mret, tl, env, tl)
 DEF_HELPER_1(wfi, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 #endif
+/* Vector functions */
+DEF_HELPER_4(vector_vsetvli, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vsetvl, void, env, i32, i32, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 77f794e..5dc009c 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -62,6 +62,7 @@
 @r_rm...   . . ... . ... %rs2 %rs1 %rm %rd
 @r2_rm   ...   . . ... . ... %rs1 %rm %rd
 @r2  ...   . . ... . ... %rs1 %rd
+@r2_zimm . zimm:11  . ... . ... %rs1 %rd
 
 @sfence_vma ... . .   ... . ... %rs2 %rs1
 @sfence_vm  ... . .   ... . ... %rs1
@@ -203,3 +204,7 @@ fcvt_w_d   111  0 . ... . 1010011 @r2_rm
 fcvt_wu_d  111  1 . ... . 1010011 @r2_rm
 fcvt_d_w   1101001  0 . ... . 1010011 @r2_rm
 fcvt_d_wu  1101001  1 . ... . 1010011 @r2_rm
+
+# *** RV32V Extension ***
+vsetvli 0 ... . 111 . 1010111  @r2_zimm
+vsetvl  100 . . 111 . 1010111  @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c 
b/target/riscv/insn_trans/trans_rvv.inc.c
new file mode 100644
index 000..82e7ad6
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -0,0 +1,46 @@
+/*
+ * RISC-V translation routines for the RVV Standard Extension.
+ *
+ * Copyright (c) 2019 C-SKY Limited. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#define GEN_VECTOR_R(INSN) \
+static bool trans_##INSN(DisasContext *ctx, arg_##INSN * a) \
+{  \
+TCGv_i32 s1 = tcg_const_i32(a->rs1);   \
+TCGv_i32 s2 = tcg_const_i32(a->rs2);   \
+TCGv_i32 d  = tcg_const_i32(a->rd);\
+gen_helper_vector_##INSN(cpu_env, s1, s2, d);\
+tcg_temp_free_i32(s1); \
+tcg_temp_free_i32(s2); \
+tcg_temp_free_i32(d);  \
+return true;   \
+}
+
+#define GEN_VECTOR_R2_ZIMM(INSN) \
+static bool trans_##INSN(DisasContext *ctx, arg_##INSN * a) \
+{  \
+TCGv_i32 s1 = tcg_const_i32(a->rs1);   \
+TCGv_i32 zimm = tcg_const_i32(a->zimm);\
+TCGv_i32 d  = tcg_const_i32(a->rd);\
+gen_helper_vector_##INSN(cpu_env, s1, zimm, d);  \
+tcg_temp_free_i32(s1); \
+tcg_temp_free_i32(zimm);   \
+tcg_temp_free_i32(d);  \
+return true;   \
+}
+
+GEN_VECTOR_R2_ZIMM(vsetvli)
+GEN_VECTOR_R(vsetvl)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8d6ab73..587c23e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -706,6 +706,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
 #include "insn_trans/trans_rva.inc.c"
 #include "insn_trans/trans_rvf.inc.c"
 #include "insn_trans/trans_rvd.inc.c"
+#include "insn_trans/trans_rvv.inc.c"
 #include 

[Qemu-devel] [PATCH v2 03/17] RISC-V: support vector extension csr

[liuzhiwei]

From: LIU Zhiwei 

Signed-off-by: LIU Zhiwei 
---
 target/riscv/cpu_bits.h | 15 
 target/riscv/csr.c  | 65 ++---
 2 files changed, 76 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 11f971a..9eb43ec 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -29,6 +29,14 @@
 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
 #define FSR_AEXC(FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
 
+/* Vector Fixed-Point round model */
+#define FSR_VXRM_SHIFT  9
+#define FSR_VXRM(0x3 << FSR_VXRM_SHIFT)
+
+/* Vector Fixed-Point saturation flag */
+#define FSR_VXSAT_SHIFT 8
+#define FSR_VXSAT   (0x1 << FSR_VXSAT_SHIFT)
+
 /* Control and Status Registers */
 
 /* User Trap Setup */
@@ -48,6 +56,13 @@
 #define CSR_FRM 0x002
 #define CSR_FCSR0x003
 
+/* User Vector CSRs */
+#define CSR_VSTART  0x008
+#define CSR_VXSAT   0x009
+#define CSR_VXRM0x00a
+#define CSR_VL  0xc20
+#define CSR_VTYPE   0xc21
+
 /* User Timers and Counters */
 #define CSR_CYCLE   0xc00
 #define CSR_TIME0xc01
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e0d4586..a6131ff 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -87,12 +87,12 @@ static int ctr(CPURISCVState *env, int csrno)
 return 0;
 }
 
-#if !defined(CONFIG_USER_ONLY)
 static int any(CPURISCVState *env, int csrno)
 {
 return 0;
 }
 
+#if !defined(CONFIG_USER_ONLY)
 static int smode(CPURISCVState *env, int csrno)
 {
 return -!riscv_has_ext(env, RVS);
@@ -158,8 +158,10 @@ static int read_fcsr(CPURISCVState *env, int csrno, 
target_ulong *val)
 return -1;
 }
 #endif
-*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
-| (env->frm << FSR_RD_SHIFT);
+*val = (env->vfp.vxrm << FSR_VXRM_SHIFT)
+| (env->vfp.vxsat << FSR_VXSAT_SHIFT)
+| (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
+| (env->frm << FSR_RD_SHIFT);
 return 0;
 }
 
@@ -172,10 +174,60 @@ static int write_fcsr(CPURISCVState *env, int csrno, 
target_ulong val)
 env->mstatus |= MSTATUS_FS;
 #endif
 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
+env->vfp.vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT;
+env->vfp.vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
 return 0;
 }
 
+static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val)
+{
+*val = env->vfp.vtype;
+return 0;
+}
+
+static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
+{
+*val = env->vfp.vl;
+return 0;
+}
+
+static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val)
+{
+*val = env->vfp.vxrm;
+return 0;
+}
+
+static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val)
+{
+*val = env->vfp.vxsat;
+return 0;
+}
+
+static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val)
+{
+*val = env->vfp.vstart;
+return 0;
+}
+
+static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
+{
+env->vfp.vxrm = val;
+return 0;
+}
+
+static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
+{
+env->vfp.vxsat = val;
+return 0;
+}
+
+static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
+{
+env->vfp.vstart = val;
+return 0;
+}
+
 /* User Timers and Counters */
 static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
 {
@@ -873,7 +925,12 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
 [CSR_FFLAGS] =  { fs,   read_fflags,  write_fflags  },
 [CSR_FRM] = { fs,   read_frm, write_frm },
 [CSR_FCSR] ={ fs,   read_fcsr,write_fcsr},
-
+/* Vector CSRs */
+[CSR_VSTART] =  { any,   read_vstart, write_vstart  },
+[CSR_VXSAT] =   { any,   read_vxsat,  write_vxsat   },
+[CSR_VXRM] ={ any,   read_vxrm,   write_vxrm},
+[CSR_VL] =  { any,   read_vl},
+[CSR_VTYPE] =   { any,   read_vtype },
 /* User Timers and Counters */
 [CSR_CYCLE] =   { ctr,  read_instret},
 [CSR_INSTRET] = { ctr,  read_instret},
-- 
2.7.4

[Qemu-devel] [PATCH v2 07/17] RISC-V: add vector extension atomic instructions

[liuzhiwei]

From: LIU Zhiwei 

Signed-off-by: LIU Zhiwei 
---
 target/riscv/helper.h   |   18 +
 target/riscv/insn32.decode  |   21 +
 target/riscv/insn_trans/trans_rvv.inc.c |   36 +
 target/riscv/vector_helper.c| 1467 +++
 4 files changed, 1542 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 973342f..c107925 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -121,5 +121,23 @@ DEF_HELPER_6(vector_vsuxb_v, void, env, i32, i32, i32, 
i32, i32)
 DEF_HELPER_6(vector_vsuxh_v, void, env, i32, i32, i32, i32, i32)
 DEF_HELPER_6(vector_vsuxw_v, void, env, i32, i32, i32, i32, i32)
 DEF_HELPER_6(vector_vsuxe_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vamoswapw_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vamoswapd_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vamoaddw_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vamoaddd_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vamoxorw_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vamoxord_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vamoandw_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vamoandd_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vamoorw_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vamoord_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vamominw_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vamomind_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vamomaxw_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vamomaxd_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vamominuw_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vamominud_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vamomaxuw_v, void, env, i32, i32, i32, i32, i32)
+DEF_HELPER_6(vector_vamomaxud_v, void, env, i32, i32, i32, i32, i32)
 DEF_HELPER_4(vector_vsetvli, void, env, i32, i32, i32)
 DEF_HELPER_4(vector_vsetvl, void, env, i32, i32, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b286997..48e7661 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -63,6 +63,7 @@
 @r_rm...   . . ... . ... %rs2 %rs1 %rm %rd
 @r2_rm   ...   . . ... . ... %rs1 %rm %rd
 @r2  ...   . . ... . ... %rs1 %rd
+@r_wdvm  . wd:1 vm:1 . . ... . ... %rs2 %rs1 %rd
 @r_nfvm  nf:3 ... vm:1 . . ... . ... %rs2 %rs1 %rd
 @r2_nfvm nf:3 ... vm:1 . . ... . ... %rs1 %rd
 @r2_zimm . zimm:11  . ... . ... %rs1 %rd
@@ -258,6 +259,26 @@ vsuxh_v... 111 . . . 101 . 0100111 @r_nfvm
 vsuxw_v... 111 . . . 110 . 0100111 @r_nfvm
 vsuxe_v... 111 . . . 111 . 0100111 @r_nfvm
 
+#*** Vector AMO operations are encoded under the standard AMO major opcode.***
+vamoswapw_v 1 . . . . 110 . 010 @r_wdvm
+vamoswapd_v 1 . . . . 111 . 010 @r_wdvm
+vamoaddw_v  0 . . . . 110 . 010 @r_wdvm
+vamoaddd_v  0 . . . . 111 . 010 @r_wdvm
+vamoxorw_v  00100 . . . . 110 . 010 @r_wdvm
+vamoxord_v  00100 . . . . 111 . 010 @r_wdvm
+vamoandw_v  01100 . . . . 110 . 010 @r_wdvm
+vamoandd_v  01100 . . . . 111 . 010 @r_wdvm
+vamoorw_v   01000 . . . . 110 . 010 @r_wdvm
+vamoord_v   01000 . . . . 111 . 010 @r_wdvm
+vamominw_v  1 . . . . 110 . 010 @r_wdvm
+vamomind_v  1 . . . . 111 . 010 @r_wdvm
+vamomaxw_v  10100 . . . . 110 . 010 @r_wdvm
+vamomaxd_v  10100 . . . . 111 . 010 @r_wdvm
+vamominuw_v 11000 . . . . 110 . 010 @r_wdvm
+vamominud_v 11000 . . . . 111 . 010 @r_wdvm
+vamomaxuw_v 11100 . . . . 110 . 010 @r_wdvm
+vamomaxud_v 11100 . . . . 111 . 010 @r_wdvm
+
 #*** new major opcode OP-V ***
 vsetvli 0 ... . 111 . 1010111  @r2_zimm
 vsetvl  100 . . 111 . 1010111  @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c 
b/target/riscv/insn_trans/trans_rvv.inc.c
index bd83885..7bda378 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -47,6 +47,23 @@ static bool trans_##INSN(DisasContext *ctx, arg_##INSN * a) \
 return true;   \
 }
 
+#define GEN_VECTOR_R_WDVM(INSN) \
+static bool trans_##INSN(DisasContext *ctx, arg_##INSN * a) \
+{  \
+TCGv_i32 s1 = tcg_const_i32(a->rs1);   \
+TCGv_i32 s2 = tcg_const_i32(a->rs2);   \
+TCGv_i32 d  = 

[Qemu-devel] [PATCH v2 02/17] RISC-V: turn on vector extension from command line by cfg.ext_v Property

[liuzhiwei]

From: LIU Zhiwei 

Signed-off-by: LIU Zhiwei 
---
 target/riscv/cpu.c | 6 +-
 target/riscv/cpu.h | 2 ++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f8d07bd..9f93ce7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -109,7 +109,7 @@ static void set_resetvec(CPURISCVState *env, int resetvec)
 static void riscv_any_cpu_init(Object *obj)
 {
 CPURISCVState *env = _CPU(obj)->env;
-set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU | RVV);
 set_priv_version(env, PRIV_VERSION_1_11_0);
 set_resetvec(env, DEFAULT_RSTVEC);
 }
@@ -406,6 +406,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
**errp)
 if (cpu->cfg.ext_u) {
 target_misa |= RVU;
 }
+if (cpu->cfg.ext_v) {
+target_misa |= RVV;
+}
 
 set_misa(env, RVXLEN | target_misa);
 }
@@ -441,6 +444,7 @@ static Property riscv_cpu_properties[] = {
 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
+DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, true),
 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c992b1d..2c7072a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -67,6 +67,7 @@
 #define RVC RV('C')
 #define RVS RV('S')
 #define RVU RV('U')
+#define RVV RV('V')
 
 /* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
@@ -250,6 +251,7 @@ typedef struct RISCVCPU {
 bool ext_c;
 bool ext_s;
 bool ext_u;
+bool ext_v;
 bool ext_counters;
 bool ext_ifencei;
 bool ext_icsr;
-- 
2.7.4

[Qemu-devel] [PATCH v2 01/17] RISC-V: add vfp field in CPURISCVState

[liuzhiwei]

From: LIU Zhiwei 

Signed-off-by: LIU Zhiwei 
---
 target/riscv/cpu.h | 28 
 1 file changed, 28 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0adb307..c992b1d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -93,9 +93,37 @@ typedef struct CPURISCVState CPURISCVState;
 
 #include "pmp.h"
 
+#define VLEN 128
+#define VUNIT(x) (VLEN / x)
+
 struct CPURISCVState {
 target_ulong gpr[32];
 uint64_t fpr[32]; /* assume both F and D extensions */
+
+/* vector coprocessor state.  */
+struct {
+union VECTOR {
+float64  f64[VUNIT(64)];
+float32  f32[VUNIT(32)];
+float16  f16[VUNIT(16)];
+uint64_t u64[VUNIT(64)];
+int64_t  s64[VUNIT(64)];
+uint32_t u32[VUNIT(32)];
+int32_t  s32[VUNIT(32)];
+uint16_t u16[VUNIT(16)];
+int16_t  s16[VUNIT(16)];
+uint8_t  u8[VUNIT(8)];
+int8_t   s8[VUNIT(8)];
+} vreg[32];
+target_ulong vxrm;
+target_ulong vxsat;
+target_ulong vl;
+target_ulong vstart;
+target_ulong vtype;
+float_status fp_status;
+} vfp;
+
+bool foflag;
 target_ulong pc;
 target_ulong load_res;
 target_ulong load_val;
-- 
2.7.4

[Qemu-devel] [PATCH v2 00/17] RISC-V: support vector extension

[liuzhiwei]

Features:
  * support specification 
riscv-v-spec-0.7.1(https://content.riscv.org/wp-content/uploads/2019/06/17.40-Vector_RISCV-20190611-Vectors.pdf).
  * support basic vector extension. 
   
  * support Zvlsseg.
   
  * support Zvamo.  
   
  * not support Zvediv as it is changing.
  * fixed VLEN 128bit.
  * fixed SLEN 128bit.
  * ELEN support 8bit, 16bit, 32bit, 64bit.

Todo:
  * support VLEN configure from qemu command line.
  * move check code from execution-time to translation-time

Changelog:
V2
  * use float16_compare{_quiet}
  * only use GETPC() in outer most helper
  * add ctx.ext_v Property


LIU Zhiwei (17):
  RISC-V: add vfp field in CPURISCVState
  RISC-V: turn on vector extension from command line by cfg.ext_v
Property
  RISC-V: support vector extension csr
  RISC-V: add vector extension configure instruction
  RISC-V: add vector extension load and store instructions
  RISC-V: add vector extension fault-only-first implementation
  RISC-V: add vector extension atomic instructions
  RISC-V: add vector extension integer instructions part1,
add/sub/adc/sbc
  RISC-V: add vector extension integer instructions part2, bit/shift
  RISC-V: add vector extension integer instructions part3, cmp/min/max
  RISC-V: add vector extension integer instructions part4, mul/div/merge
  RISC-V: add vector extension fixed point instructions
  RISC-V: add vector extension float instruction part1, add/sub/mul/div
  RISC-V: add vector extension float instructions part2,
sqrt/cmp/cvt/others
  RISC-V: add vector extension reduction instructions
  RISC-V: add vector extension mask instructions
  RISC-V: add vector extension premutation instructions

 linux-user/riscv/cpu_loop.c | 7 +
 target/riscv/Makefile.objs  | 2 +-
 target/riscv/cpu.c  | 6 +-
 target/riscv/cpu.h  |30 +
 target/riscv/cpu_bits.h |15 +
 target/riscv/cpu_helper.c   | 7 +
 target/riscv/csr.c  |65 +-
 target/riscv/helper.h   |   358 +
 target/riscv/insn32.decode  |   373 +
 target/riscv/insn_trans/trans_rvv.inc.c |   490 +
 target/riscv/translate.c| 1 +
 target/riscv/vector_helper.c| 25701 ++
 12 files changed, 27049 insertions(+), 6 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
 create mode 100644 target/riscv/vector_helper.c

-- 
2.7.4

Re: [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1

[liuzhiwei]

On 2019/8/29 上午2:54, Richard Henderson wrote:

On 8/27/19 7:36 PM, liuzhiwei wrote:

Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
Signed-off-by: liuzhiwei 
---
  fpu/softfloat.c |   119 +
  include/fpu/softfloat.h | 4 +
  linux-user/riscv/cpu_loop.c | 8 +-
  target/riscv/Makefile.objs  | 2 +-
  target/riscv/cpu.h  |30 +
  target/riscv/cpu_bits.h |15 +
  target/riscv/cpu_helper.c   | 7 +
  target/riscv/csr.c  |65 +-
  target/riscv/helper.h   |   354 +
  target/riscv/insn32.decode  |   374 +-
  target/riscv/insn_trans/trans_rvv.inc.c |   484 +
  target/riscv/translate.c| 1 +
  target/riscv/vector_helper.c| 26563 ++
  13 files changed, 28017 insertions(+), 9 deletions(-)

As Alex mentioned, this is *far* too big to be presented as a single patch.

OK, split it into patch set in V2



diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 3ff3fa5..3b0754c 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -293,6 +293,10 @@ float16 float16_maxnummag(float16, float16, float_status 
*status);
  float16 float16_sqrt(float16, float_status *status);
  int float16_compare(float16, float16, float_status *status);
  int float16_compare_quiet(float16, float16, float_status *status);
+int float16_unordered_quiet(float16, float16, float_status *status);
+int float16_le(float16, float16, float_status *status);
+int float16_lt(float16, float16, float_status *status);
+int float16_eq_quiet(float16, float16, float_status *status);

As Alex mentioned, none of these changes are required, as all
functionality is provided by float16_compare{,_quiet}.

Yes, use float16_compare instead.

diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
index 12aa3c0..b01548a 100644
--- a/linux-user/riscv/cpu_loop.c
+++ b/linux-user/riscv/cpu_loop.c
@@ -40,7 +40,13 @@ void cpu_loop(CPURISCVState *env)
  signum = 0;
  sigcode = 0;
  sigaddr = 0;
-
+if (env->foflag) {
+if (env->vfp.vl != 0) {
+env->foflag = false;
+env->pc += 4;
+continue;
+}

This is most definitely not the correct way to implement first-fault.

You need to have a look at target/arm/sve_helper.c, e.g. sve_ldff1_r,
where we test pages for validity with tlb_vaddr_to_host.
Why should  test pages for validity? If there is a page fault in running 
time, it just the case why it must use the fault-only-first instruction.

+/* vector coprocessor state.  */
+struct {
+union VECTOR {
+float64  f64[VUNIT(64)];
+float32  f32[VUNIT(32)];
+float16  f16[VUNIT(16)];
+target_ulong ul[VUNIT(sizeof(target_ulong))];
+uint64_t u64[VUNIT(64)];
+int64_t  s64[VUNIT(64)];
+uint32_t u32[VUNIT(32)];
+int32_t  s32[VUNIT(32)];
+uint16_t u16[VUNIT(16)];
+int16_t  s16[VUNIT(16)];
+uint8_t  u8[VUNIT(8)];
+int8_t   s8[VUNIT(8)];
+} vreg[32];
+target_ulong vxrm;
+target_ulong vxsat;
+target_ulong vl;
+target_ulong vstart;
+target_ulong vtype;
+float_status fp_status;
+} vfp;

You've obviously copied "vfp" from target/arm.  Drop that.  It makes no sense
in the context of risc-v.
I'm not sure that vreg[].element[] really makes the most sense in the context
of how risc-v rearranges its elements.  It will almost certainly fail clang
validators, if enabled, since you'll be indexing beyond the end of vreg[n] into
vreg[n+1].

It might be best to have a single array:

 union {
 uint64_t u64[32 * VLEN / 64];
 ...
 uint8_t u8[32 * VLEN / 8];
 } velt;

This is clearer to the compiler that this is a single block of memory that we
can index as we please.


A single array is a good idea. But vreg[] will be better for understanding as 
it preserve the register concepts.


Note that float64/float32/float16 are legacy.  They will always be equivalent
to the unsigned integer types of the same size.

Is there really any vector operation at all that is dependent on XLEN?  If not,
then there is no reason to confuse things by including target_ulong.


OK.

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e32b612..405caf6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -521,6 +521,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
  [PRV_H] = RISCV_EXCP_H_ECALL,
  [PRV_M] = RISCV_EXCP_M_ECALL
  };
+if (env->foflag) {
+if (env->vfp.vl != 0) {
+env->foflag = false;
+env->pc += 4;
+return;
+}
+}

Again, not the way to implemen

Re: [Qemu-devel] [Qemu-riscv] [PATCH] RISCV: support riscv vector extension 0.7.1

[liuzhiwei]

On 2019/8/29 下午10:06, Chih-Min Chao wrote:

Hi Liuzhiwei,

Some comments:
     1. vector extension allows flexible implementation. It is better 
to describe the limitation of current implementation (such as 
vlen/elen/slen) , supported sections and unsupported features.

Thanks!  All mentioned will be in patch V2.
     2. there should be cfg.ext_v  to turn on  vector extension from 
command line

I will add the vector extension to cpu "any".  Is it all right?

     3. from license
           It should be   "Copyright  (c) 2019 C-SKY Limited, All 
rights reserved."  but not  "2011 ~ 2019"


It is huge work wait and thanks for your contribution.

chihmin

On Wed, Aug 28, 2019 at 3:06 PM liuzhiwei <mailto:zhiwei_...@c-sky.com>> wrote:


Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
Signed-off-by: liuzhiwei mailto:zhiwei_...@c-sky.com>>
---
 fpu/softfloat.c                         |   119 +
 include/fpu/softfloat.h                 |     4 +
 linux-user/riscv/cpu_loop.c             |     8 +-
 target/riscv/Makefile.objs              |     2 +-
 target/riscv/cpu.h                      |    30 +
 target/riscv/cpu_bits.h                 |    15 +
 target/riscv/cpu_helper.c               |     7 +
 target/riscv/csr.c                      |    65 +-
 target/riscv/helper.h                   |   354 +
 target/riscv/insn32.decode              |   374 +-
 target/riscv/insn_trans/trans_rvv.inc.c |   484 +
 target/riscv/translate.c                |     1 +
 target/riscv/vector_helper.c            | 26563
++
 13 files changed, 28017 insertions(+), 9 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
 create mode 100644 target/riscv/vector_helper.c

Re: [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1

[liuzhiwei]

On 2019/8/29 下午11:09, Richard Henderson wrote:

On 8/29/19 5:45 AM, liuzhiwei wrote:

Even in qemu,  it may be some situations that VSTART != 0. For example, a load
instruction leads to a page fault exception in a middle position. If VSTART ==
0,  some elements that had been loaded before the exception will be loaded once
again.

Alternately, you can validate all of the pages before performing any memory
operations.  At which point there will never be an exception in the middle.


As a vector instruction may access memory  across many pages,  is there 
any way to validate the pages? Page table walk ?Or some TLB APIs?



As it turns out, you *must* do this in order to allow watchpoints to work
correctly.  David Hildebrand and I are at this moment fixing this aspect of
watchpoints for s390x.

See https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg05979.html


I am interested in wathpoint implementation and  once implemented the 
user mode watchpoints in the wild.


A backtrace of watchpoint is like

#0  cpu_watchpoint_address_matches (wp=0x56228110, addr=536871072, 
len=1) at qemu/exec.c:1094
#1  0x5567204f in check_watchpoint (offset=160, len=1, 
attrs=..., flags=2) at qemu/exec.c:2803
#2  0x55672379 in watch_mem_write (opaque=0x0, addr=536871072, 
val=165, size=1, attrs=...) at qemu/exec.c:2878
#3  0x556d44bb in memory_region_write_with_attrs_accessor 
(mr=0x561292e0 , addr=536871072, value=0x7fffedffe2c8, 
size=1, shift=0, mask=255, attrs=...)

    at qemu/memory.c:553
#4  0x556d45de in access_with_adjusted_size (addr=536871072, 
value=0x7fffedffe2c8, size=1, access_size_min=1, access_size_max=8, 
access_fn=0x556d43cd ,

    mr=0x561292e0 , attrs=...) at qemu/memory.c:594
#5  0x556d7247 in memory_region_dispatch_write 
(mr=0x561292e0 , addr=536871072, data=165, size=1, 
attrs=...) at qemu/memory.c:1480
#6  0x556f0d13 in io_writex (env=0x561efb58, 
iotlbentry=0x561f5398, mmu_idx=1, val=165, addr=536871072, 
retaddr=0, recheck=false, size=1) at qemu/accel/tcg/cputlb.c:909
#7  0x556f19a6 in io_writeb (env=0x561efb58, mmu_idx=1, 
index=0, val=165 '\245', addr=536871072, retaddr=0, recheck=false) at 
qemu/accel/tcg/softmmu_template.h:268
#8  0x556f1b54 in helper_ret_stb_mmu (env=0x561efb58, 
addr=536871072, val=165 '\245', oi=1, retaddr=0) at 
qemu/accel/tcg/softmmu_template.h:304
#9  0x55769f06 in cpu_stb_data_ra (env=0x561efb58, 
ptr=536871072, v=165, retaddr=0) at 
qemu/include/exec/cpu_ldst_template.h:182
#10 0x55769f80 in cpu_stb_data (env=0x561efb58, 
ptr=536871072, v=165) at /qemu/include/exec/cpu_ldst_template.h:194
#11 0x5576a913 in csky_cpu_stb_data (env=0x561efb58, 
vaddr=536871072, data=165 '\245') at qemu/target/csky/csky_ldst.c:48
#12 0x5580ba7d in helper_vdsp2_vstru_n (env=0x561efb58, 
insn=4167183360) at qemu/target/csky/op_vdsp2.c:1317


The path is not related to probe_write in the patch().

Could you give more details or a test case where watchpoint doesn't work 
correctly?




r~

Re: [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1

[liuzhiwei]

On 2019/8/29 下午11:14, Richard Henderson wrote:

On 8/29/19 5:00 AM, liuzhiwei wrote:

Maybe there is some better test method or some forced test cases in QEMU. Could
you give me some advice for testing?

If you have hardware, or another simulator, RISU is very good
for testing these sorts of things.

See https://git.linaro.org/people/pmaydell/risu.git

You'll need to write new support for RISC-V, but it's not hard
and we can help out with that.


r~


Hi, Richard

Thank you for your advice.  I will run test cases in Spike for cross 
validation at first.


Best Regards,
Zhiwei

Re: [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1

[liuzhiwei]

On 2019/8/30 上午5:50, Alistair Francis wrote:

On Thu, Aug 29, 2019 at 5:05 AM liuzhiwei  wrote:

On 2019/8/29 上午5:34, Alistair Francis wrote:

On Wed, Aug 28, 2019 at 12:04 AM liuzhiwei  wrote:

Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
Signed-off-by: liuzhiwei 
---
   fpu/softfloat.c |   119 +
   include/fpu/softfloat.h | 4 +
   linux-user/riscv/cpu_loop.c | 8 +-
   target/riscv/Makefile.objs  | 2 +-
   target/riscv/cpu.h  |30 +
   target/riscv/cpu_bits.h |15 +
   target/riscv/cpu_helper.c   | 7 +
   target/riscv/csr.c  |65 +-
   target/riscv/helper.h   |   354 +
   target/riscv/insn32.decode  |   374 +-
   target/riscv/insn_trans/trans_rvv.inc.c |   484 +
   target/riscv/translate.c| 1 +
   target/riscv/vector_helper.c| 26563 
++
   13 files changed, 28017 insertions(+), 9 deletions(-)
   create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
   create mode 100644 target/riscv/vector_helper.c


Hello,

Thanks for the patch!

As others have pointed out you will need to split the patch up into
multiple smaller patches, otherwise it is too hard to review almost
30,000 lines of code.

Hi, Alistair

I'm so sorry for the inconvenience. It will be a patch set with a cover
letter in V2.

No worries.


Can you also include a cover letter with your patch series describing
how you are testing this? AFAIK vector extension support isn't in any
compiler so I'm assuming you are handwriting the assembly or have
toolchain patches. Either way it will help if you can share that so
others can test your implementation.

Yes, it's handwriting assembly. The assembler in Binutils has support
Vector extension.  First define an function test_vadd_vv_8 in assembly
and then it can be called from a C program.

The function is something like

/* vadd.vv */
TEST_FUNC(test_vadd_vv_8)
  vsetvlit1, x0, e8, m2
  vlb.v   v6, (a4)
  vsb.v   v6, (a3)
  vsetvlit1, a0, e8, m2
  vlb.v   v0, (a1)
  vlb.v   v2, (a2)
  vadd.vv v4, v0, v2
  vsb.v  v4, (a3)
ret
  .size   test_vadd_vv_8, .-test_vadd_vv_8

If possible it might be worth releasing the code that you are using for testing.

Yes,  but I didn't find a good place to release these test codes currently.



It takes more time to test than to implement the instructions. Maybe
there is some better test method or some forced test cases in QEMU.
Could you give me some advice for testing?

Richard's idea of risu seems like a good option.
All the test cases will be validated in Spike,  which has supported the 
same vector specification. But this  cross validation work may delay 
until V3.
I will split the patch, and address comments as soon as possible, to 
ensure the patch V2 can be sent next week.

Would it be all right?


Thinking about it a bit more we are going to have other extensions in
the future that will need assembly testing so setting up a test
framework seems like a good idea. I am happy to help try and get this
going as well.

Alistair
There is usually a big difference between new a ISA extension and the 
others. I doubt there is an general framework. A very light framework  
includes
building, input aiding  generation, result validation, and report maybe 
OK .


Best Regards,
Zhiwei

Best Regards,

Zhiwei


Alex and Richard have kindly started the review. Once you have
addressed their comments and split this patch up into smaller patches
you can send a v2 and we can go from there.

Once again thanks for doing this implementation for QEMU!

Alistair

Re: [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1

[liuzhiwei]

Hi,  Alex

On 2019/8/28 下午5:08, Alex Bennée wrote:

liuzhiwei  writes:


Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
Signed-off-by: liuzhiwei 
---
  fpu/softfloat.c |   119 +
  include/fpu/softfloat.h | 4 +

Changes to softfloat should be in a separate patch, but see bellow.


  linux-user/riscv/cpu_loop.c | 8 +-
  target/riscv/Makefile.objs  | 2 +-
  target/riscv/cpu.h  |30 +
  target/riscv/cpu_bits.h |15 +
  target/riscv/cpu_helper.c   | 7 +
  target/riscv/csr.c  |65 +-
  target/riscv/helper.h   |   354 +
  target/riscv/insn32.decode  |   374 +-
  target/riscv/insn_trans/trans_rvv.inc.c |   484 +
  target/riscv/translate.c| 1 +
  target/riscv/vector_helper.c| 26563 ++

This is likely too big to be reviewed. Is it possible to split the patch
up into more discrete chunks, for example support pieces and then maybe
a class at a time?


Yes,  a patch set with cover letter will be sent later.




  13 files changed, 28017 insertions(+), 9 deletions(-)
  create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
  create mode 100644 target/riscv/vector_helper.c

diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 2ba36ec..da155ea 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -433,6 +433,16 @@ static inline int extractFloat16Exp(float16 a)
  }

  /*
+| Returns the sign bit of the half-precision floating-point value `a'.
+**/
+
+static inline flag extractFloat16Sign(float16 a)
+{
+return float16_val(a) >> 0xf;
+}
+

We are trying to avoid this sort of bit fiddling for new code when we
already have generic decompose functions that can extract all the parts
into a common format.


+
+/*
  | Returns the fraction bits of the single-precision floating-point value `a'.
  
**/

@@ -4790,6 +4800,35 @@ int float32_eq(float32 a, float32 b, float_status 
*status)
  }

  /*
+| Returns 1 if the half-precision floating-point value `a' is less than
+| or equal to the corresponding value `b', and 0 otherwise.  The invalid
+| exception is raised if either operand is a NaN.  The comparison is performed
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+**/
+
+int float16_le(float16 a, float16 b, float_status *status)
+{
+flag aSign, bSign;
+uint16_t av, bv;
+a = float16_squash_input_denormal(a, status);
+b = float16_squash_input_denormal(b, status);
+
+if (( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+   ) {
+float_raise(float_flag_invalid, status);
+return 0;
+}
+aSign = extractFloat16Sign( a );
+bSign = extractFloat16Sign( b );
+av = float16_val(a);
+bv = float16_val(b);
+if ( aSign != bSign ) return aSign || ( (uint16_t) ( ( av | bv )<<1 ) == 0 
);
+return ( av == bv ) || ( aSign ^ ( av < bv ) );
+
+}

What does this provide that:

   float16_compare(a, b, status) == float_relation_less;

doesn't?


+
+/*
  | Returns 1 if the single-precision floating-point value `a' is less than
  | or equal to the corresponding value `b', and 0 otherwise.  The invalid
  | exception is raised if either operand is a NaN.  The comparison is performed
@@ -4825,6 +4864,35 @@ int float32_le(float32 a, float32 b, float_status 
*status)
  | to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
  
**/

+int float16_lt(float16 a, float16 b, float_status *status)
+{
+flag aSign, bSign;
+uint16_t av, bv;
+a = float16_squash_input_denormal(a, status);
+b = float16_squash_input_denormal(b, status);
+
+if (( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+   ) {
+float_raise(float_flag_invalid, status);
+return 0;
+}
+aSign = extractFloat16Sign( a );
+bSign = extractFloat16Sign( b );
+av = float16_val(a);
+bv = float16_val(b);
+if ( aSign != bSign ) return aSign && ( (uint16_t) ( ( av | bv )<<

Re: [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1

[liuzhiwei]

On 2019/8/29 上午4:43, Richard Henderson wrote:

On 8/28/19 11:54 AM, Richard Henderson wrote:

But it might be reasonable to include (VSTART == 0 && VL == VLMAX) as a
single bit.

BTW, it is reasonable to check VSTART == 0 always.  Quoting the spec:

# Implementations are permitted to raise illegal instruction exceptions
# when attempting to execute a vector instruction with a value of vstart
# that the implementation can never produce when executing that same
# instruction with the same vtype setting.

Since qemu will never interrupt a single instruction, each vector instruction
will always run to completion, which clears VSTART.  Since QEMU will never
produce a non-zero value of VSTART, it is allowed to trap on any non-zero
setting of VSTART.

I.e. it can be handled at translation time alongside VILL.


Hi, Richard

I am so sorry for the inconvenience. It is very kind of you to review 
the horrible long code and give so many comments.


Even in qemu,  it may be some situations that VSTART != 0. For example, 
a load instruction leads to a page fault exception in a middle position. 
If VSTART == 0,  some elements that had been loaded before the exception 
will be loaded once again.


Specially,  it may be a mistake if  the instruction restores execution 
with VSTART==  0.  When lmul == 1,


   "vlb v0 ,(a0), v0.t"

As v0 is the mask register,  if it is modified,  some part of it can't 
be used again.


It will take some time to address the other comments. After that I will 
split the patch into patch set with a cover letter in V2.


Thank you again for your review!

Best Regards,

Zhiwei




r~

Re: [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1

[liuzhiwei]

On 2019/8/29 上午5:34, Alistair Francis wrote:

On Wed, Aug 28, 2019 at 12:04 AM liuzhiwei  wrote:

Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
Signed-off-by: liuzhiwei 
---
  fpu/softfloat.c |   119 +
  include/fpu/softfloat.h | 4 +
  linux-user/riscv/cpu_loop.c | 8 +-
  target/riscv/Makefile.objs  | 2 +-
  target/riscv/cpu.h  |30 +
  target/riscv/cpu_bits.h |15 +
  target/riscv/cpu_helper.c   | 7 +
  target/riscv/csr.c  |65 +-
  target/riscv/helper.h   |   354 +
  target/riscv/insn32.decode  |   374 +-
  target/riscv/insn_trans/trans_rvv.inc.c |   484 +
  target/riscv/translate.c| 1 +
  target/riscv/vector_helper.c| 26563 ++
  13 files changed, 28017 insertions(+), 9 deletions(-)
  create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
  create mode 100644 target/riscv/vector_helper.c


Hello,

Thanks for the patch!

As others have pointed out you will need to split the patch up into
multiple smaller patches, otherwise it is too hard to review almost
30,000 lines of code.


Hi, Alistair

I'm so sorry for the inconvenience. It will be a patch set with a cover 
letter in V2.



Can you also include a cover letter with your patch series describing
how you are testing this? AFAIK vector extension support isn't in any
compiler so I'm assuming you are handwriting the assembly or have
toolchain patches. Either way it will help if you can share that so
others can test your implementation.


Yes, it's handwriting assembly. The assembler in Binutils has support 
Vector extension.  First define an function test_vadd_vv_8 in assembly 
and then it can be called from a C program.


The function is something like

/* vadd.vv */
TEST_FUNC(test_vadd_vv_8)
    vsetvli    t1, x0, e8, m2
    vlb.v   v6, (a4)
    vsb.v   v6, (a3)
    vsetvli    t1, a0, e8, m2
    vlb.v   v0, (a1)
    vlb.v   v2, (a2)
    vadd.vv v4, v0, v2
    vsb.v  v4, (a3)
ret
    .size   test_vadd_vv_8, .-test_vadd_vv_8

It takes more time to test than to implement the instructions. Maybe 
there is some better test method or some forced test cases in QEMU. 
Could you give me some advice for testing?


Best Regards,

Zhiwei


Alex and Richard have kindly started the review. Once you have
addressed their comments and split this patch up into smaller patches
you can send a v2 and we can go from there.

Once again thanks for doing this implementation for QEMU!

Alistair

Re: [Qemu-devel] RISC-V: Vector && DSP Extension

[liuzhiwei]

On 2019/8/22 上午3:31, Palmer Dabbelt wrote:

On Thu, 15 Aug 2019 14:37:52 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Aug 15, 2019 at 2:07 AM Peter Maydell 
 wrote:


On Thu, 15 Aug 2019 at 09:53, Aleksandar Markovic
 wrote:
>
> > We can accept draft
> > extensions in QEMU as long as they are disabled by default.

> Hi, Alistair, Palmer,
>
> Is this an official stance of QEMU community, or perhaps Alistair's
> personal judgement, or maybe a rule within risv subcomunity?

Alistair asked on a previous thread; my view was:
https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg03364.html
and nobody else spoke up disagreeing (summary: should at least be
disabled-by-default and only enabled by setting an explicit
property whose name should start with the 'x-' prefix).


Agreed!



In general QEMU does sometimes introduce experimental extensions
(we've had them in the block layer, for example) and so the 'x-'
property to enable them is a reasonably established convention.
I think it's a reasonable compromise to allow this sort of work
to start and not have to live out-of-tree for a long time, without
confusing users or getting into a situation where some QEMU
versions behave differently or to obsolete drafts of a spec
without it being clear from the command line that experimental
extensions are being enabled.

There is also an element of "submaintainer judgement" to be applied
here -- upstream is probably not the place for a draft extension
to be implemented if it is:
 * still fast moving or subject to major changes of design direction
 * major changes to the codebase (especially if it requires
   changes to core code) that might later need to be redone
   entirely differently
 * still experimental


Yep, agreed. For RISC-V I think this would extend to only allowing
extensions that have backing from the foundation and are under active
discussion.


My general philosophy here is that we'll take anything written down in 
an official RISC-V ISA manual (ie, the ones actually released by the 
foundation).  This provides a single source of truth for what an 
extension name / version means, which is important to avoid 
confusion.  If it's a ratified extension then I see no reason not to 
support it on my end.  For frozen extensions we should probably just 
wait the 45 days until they go up for a ratification vote, but I'd be 
happy to start reviewing patches then (or earlier :)).


If the spec is a draft in the ISA manual then we need to worry about 
the support burden, which I don't have a fixed criteria for -- 
generally there shouldn't be issues here, but early drafts can be in a 
state where they're going to change extensively and are unlikely to be 
used by anyone.  There's also the question of "what is an official 
release of a draft specification?".
That's a bit awkward right now: the current ratified ISA manual 
contains version 0.3 of the hypervisor extension, but I just talked to 
Andrew and the plan is to remove the draft extensions from the 
ratified manuals because these drafts are old and the official manuals 
update slowly.  For now I guess we'll need an an-hoc way of 
determining if a draft extension has been officially versioned or not, 
which is a bit of a headache.


We already have examples of supporting draft extensions, including 
priv-1.9.1.  This does cause some pain for us on the QEMU side (CSR 
bits have different semantics between the specs), but there's 1.9.1 
hardware out there and the port continues to be useful so I'd be in 
favor of keeping it around for now.  I suppose there is an implicit 
risk that draft extensions will be deprecated, but the "x-" prefix, 
draft status, and long deprecation period should be sufficient to 
inform users of the risk.  I wouldn't be opposed to adding a "this is 
a draft ISA" warning, but I feel like it might be a bit overkill.



Hi, Palmer

Maybe it is the headache of open source hardware. Everyone cooperates to 
build a better architecture.


In my opinion, we should focus on the future. The code in QEMU mainline 
should evolve to the  ratified extension step by step, and only support 
the best extension at last.


At that time,  even many hardwares just support  the deprecated draft 
extension,  the draft codes should be in the wild and maintained by the 
hardware manufactures.


But before that,  it is better to  have a draft implementation. So that 
We can work step by step to accelerate the coming of the ratified 
extension.


Even at last draft extension implementation are deprecated, they are not 
meaningless. The manufactures may use  the  history commit to support 
their hardwares that


only support drafted extension.

Best Regards,

Zhiwei



Alistair



thanks
-- PMM

Re: [Qemu-devel] [Qemu-riscv] RISCV: when will the CLIC be ready?

[liuzhiwei]

On 2019/8/20 上午12:38, Chih-Min Chao wrote:



On Mon, Aug 19, 2019 at 9:47 PM liuzhiwei <mailto:zhiwei_...@c-sky.com>> wrote:



On 2019/8/17 上午1:29, Alistair Francis wrote:
> On Thu, Aug 15, 2019 at 8:39 PM liuzhiweimailto:zhiwei_...@c-sky.com>> wrote:
>> Hi, Palmer
>>
>> When Michael Clark still was the maintainer of RISCV QEMU, he
wrote in the mail list, "the CLIC interrupt controller is under
testing,
>> and will be included in QEMU 3.1 or 3.2". It is pity that the
CLIC is not in
>> included even in QEMU 4.1.0.
> I see that there is a CLIC branch available here:
> https://github.com/riscv/riscv-qemu/pull/157
>
> It looks like all of the work is in a single commit
>

(https://github.com/riscv/riscv-qemu/pull/157/commits/206d9ac339feb9ef2c325402a00f0f45f453d019)
> and that most of the other commits in the PR have already made
it into
> master.
>
> Although the CLIC commit is very large it doesn't seem impossible to
> manually pull out the CLIC bits and apply it onto master.
>
> Do you know the state of the CLIC model? If it's working it
shouldn't
> be too hard to rebase the work and get the code into mainline.
>
> Alistair
>
Hi,  Alistair

In my opinion, the CLIC code almost works.

Last year when my workmate ported an RTOS, I once read the CLIC
specification and used the CLIC model code. It worked through  all
the tests after fixed two bugs. I also had sent the patch to
Michael, but without response(maybe a wrong email address).

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 7bf6cbc..95d80ab 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -505,6 +505,9 @@ static target_ulong
riscv_intr_pc(CPURISCVState *env,
      if (!(async || clic)) {
          return tvec & ~0b11;
      }
+    if (clic) {
+        cause &= 0x3ff;
+    }

      /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >=
reserved */
      switch (mode1) {
@@ -645,6 +648,9 @@ void riscv_cpu_do_interrupt(CPUState *cs)
          riscv_cpu_set_mode(env, PRV_M);
      }

+    if (clic) {
+        env->exccode = 0;
+    }
      /* NOTE: it is not necessary to yield load reservations
here. It is only
         necessary for an SC from "another hart" to cause a load
reservation
         to be yielded. Refer to the memory consistency model
section of the

After that, the specification has updated and the code may
changed. I didn't pull new code again.

If the CLIC model may merged into the mainline, and no body
maintain the code, I'd like to work on it, fixing the bugs and
updating the code according to latest specification.

Best Regards,
Zhiwei

>> As we have cpus using CLIC, I have to use the out of tree qemu
code in SIFIVE
>> a long time. Could you tell me when it will be upstreamed?
>>
>> Best Regards
>> Zhiwei
>>


Hi Zhiwei,

I think what Alistair point out is the latest clic version (or 
https://github.com/riscv/riscv-qemu/tree/riscv-qemu-3.1). The two 
versions, on pull request and 3.1 branch, should be similar.

As far as I know, there is no concrete plan on CLIC patch in short term.
It is good to know that the clic patch has been run with real RTOS.
It is also great if you could update the implementation to latest spec 
and send the patch again.


chihmin


Hi chihmin,

Thanks for your reminding and approval. I will pull the latest clic 
version code and send the patch about two or three weeks later.


The RTOS is Rhino,  which is the kernel of 
AliOS-Things(https://github.com/alibaba/AliOS-Things).


It is also the kernel of YOC(https://cop.c-sky.com).

Best Regards
Zhiwei

Re: [Qemu-devel] RISCV: when will the CLIC be ready?

[liuzhiwei]

On 2019/8/20 上午2:56, Alistair Francis wrote:

On Mon, Aug 19, 2019 at 6:44 AM liuzhiwei  wrote:


On 2019/8/17 上午1:29, Alistair Francis wrote:

On Thu, Aug 15, 2019 at 8:39 PM liuzhiwei  wrote:

Hi, Palmer

When Michael Clark still was the maintainer of RISCV QEMU, he wrote in the mail 
list, "the CLIC interrupt controller is under testing,
and will be included in QEMU 3.1 or 3.2". It is pity that the CLIC is not in
included even in QEMU 4.1.0.

I see that there is a CLIC branch available here:
https://github.com/riscv/riscv-qemu/pull/157

It looks like all of the work is in a single commit
(https://github.com/riscv/riscv-qemu/pull/157/commits/206d9ac339feb9ef2c325402a00f0f45f453d019)
and that most of the other commits in the PR have already made it into
master.

Although the CLIC commit is very large it doesn't seem impossible to
manually pull out the CLIC bits and apply it onto master.

Do you know the state of the CLIC model? If it's working it shouldn't
be too hard to rebase the work and get the code into mainline.

Alistair


Hi,  Alistair

In my opinion, the CLIC code almost works.

Last year when my workmate ported an RTOS, I once read the CLIC specification 
and used the CLIC model code. It worked through  all the tests after fixed two 
bugs. I also had sent the patch to Michael, but without response(maybe a wrong 
email address).

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 7bf6cbc..95d80ab 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -505,6 +505,9 @@ static target_ulong riscv_intr_pc(CPURISCVState *env,
   if (!(async || clic)) {
   return tvec & ~0b11;
   }
+if (clic) {
+cause &= 0x3ff;
+}

   /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
   switch (mode1) {
@@ -645,6 +648,9 @@ void riscv_cpu_do_interrupt(CPUState *cs)
   riscv_cpu_set_mode(env, PRV_M);
   }

+if (clic) {
+env->exccode = 0;
+}
   /* NOTE: it is not necessary to yield load reservations here. It is only
  necessary for an SC from "another hart" to cause a load reservation
  to be yielded. Refer to the memory consistency model section of the

After that, the specification has updated and the code may changed. I didn't 
pull new code again.

If the CLIC model may merged into the mainline, and no body maintain the code, 
I'd like to work on it, fixing the bugs and updating the code according to 
latest specification.

Yes please! We will be happy to merge it!

If you would like to it would be great if you could update the code,
fix the bugs and then send patches to this list.

Alistair

OK,  I'd like to. As the vector extension patch has already been under 
data  disclosure  review,


I will forward move on to this work and send the patch about two or 
three weeks later.


Best Regards,
Zhiwei


Best Regards,
Zhiwei


As we have cpus using CLIC, I have to use the out of tree qemu code in SIFIVE
a long time. Could you tell me when it will be upstreamed?

Best Regards
Zhiwei

Re: [Qemu-devel] RISCV: when will the CLIC be ready?

[liuzhiwei]

On 2019/8/17 上午1:29, Alistair Francis wrote:

On Thu, Aug 15, 2019 at 8:39 PM liuzhiwei  wrote:

Hi, Palmer

When Michael Clark still was the maintainer of RISCV QEMU, he wrote in the mail 
list, "the CLIC interrupt controller is under testing,
and will be included in QEMU 3.1 or 3.2". It is pity that the CLIC is not in
included even in QEMU 4.1.0.

I see that there is a CLIC branch available here:
https://github.com/riscv/riscv-qemu/pull/157

It looks like all of the work is in a single commit
(https://github.com/riscv/riscv-qemu/pull/157/commits/206d9ac339feb9ef2c325402a00f0f45f453d019)
and that most of the other commits in the PR have already made it into
master.

Although the CLIC commit is very large it doesn't seem impossible to
manually pull out the CLIC bits and apply it onto master.

Do you know the state of the CLIC model? If it's working it shouldn't
be too hard to rebase the work and get the code into mainline.

Alistair


Hi,  Alistair

In my opinion, the CLIC code almost works.
 
Last year when my workmate ported an RTOS, I once read the CLIC specification and used the CLIC model code. It worked through  all the tests after fixed two bugs. I also had sent the patch to Michael, but without response(maybe a wrong email address).


diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 7bf6cbc..95d80ab 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -505,6 +505,9 @@ static target_ulong riscv_intr_pc(CPURISCVState *env,
 if (!(async || clic)) {
 return tvec & ~0b11;
 }
+if (clic) {
+cause &= 0x3ff;
+}
 
 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */

 switch (mode1) {
@@ -645,6 +648,9 @@ void riscv_cpu_do_interrupt(CPUState *cs)
 riscv_cpu_set_mode(env, PRV_M);
 }
 
+if (clic) {

+env->exccode = 0;
+}
 /* NOTE: it is not necessary to yield load reservations here. It is only
necessary for an SC from "another hart" to cause a load reservation
to be yielded. Refer to the memory consistency model section of the

After that, the specification has updated and the code may changed. I didn't 
pull new code again.

If the CLIC model may merged into the mainline, and no body maintain the code, 
I'd like to work on it, fixing the bugs and updating the code according to 
latest specification.

Best Regards,
Zhiwei


As we have cpus using CLIC, I have to use the out of tree qemu code in SIFIVE
a long time. Could you tell me when it will be upstreamed?

Best Regards
Zhiwei

[Qemu-devel] RISCV: when will the CLIC be ready?

[liuzhiwei]

Hi, Palmer

When Michael Clark still was the maintainer of RISCV QEMU, he wrote in the mail 
list, "the CLIC interrupt controller is under testing,
and will be included in QEMU 3.1 or 3.2". It is pity that the CLIC is not in
included even in QEMU 4.1.0.

As we have cpus using CLIC, I have to use the out of tree qemu code in SIFIVE
a long time. Could you tell me when it will be upstreamed?

Best Regards
Zhiwei

[Qemu-devel] RISC-V: Vector && DSP Extension

[liuzhiwei]

Hi all,

   My workmate  and I have been working on Vector & Dsp extension, and 
I'd like to share develop status  with folks.


   The spec references for  Vector extension is riscv-v-spec-0.7.1, and 
riscv-p-spec-0.5 for DSP extension. The code of vector extension is 
ready and under testing,  the first patch will be sent about two weeks 
later. After that we will forward working on DSP extension, and send the 
first patch in middle  October.


    Could the maintainers  tell me whether the specs referenced are 
appropriate? Is anyone working on these extensions?  I'd like to get 
your status, and maybe discuss questions and work togather.


Best Regards

LIU Zhiwei