RE: [PATCH v1 03/12] target/riscv: Implement function kvm_arch_init_vcpu

[Jiangyifei via]

> -Original Message-
> From: Richard Henderson [mailto:richard.hender...@linaro.org]
> Sent: Sunday, November 21, 2021 6:19 AM
> To: Jiangyifei ; qemu-devel@nongnu.org;
> qemu-ri...@nongnu.org
> Cc: bin.m...@windriver.com; limingwang (A) ;
> k...@vger.kernel.org; libvir-l...@redhat.com; anup.pa...@wdc.com; wanbo (G)
> ; Alistair Francis ;
> kvm-ri...@lists.infradead.org; Wanghaibin (D)
> ; pal...@dabbelt.com; Fanliang (EulerOS)
> ; Wubin (H) 
> Subject: Re: [PATCH v1 03/12] target/riscv: Implement function
> kvm_arch_init_vcpu
> 
> On 11/20/21 8:46 AM, Yifei Jiang wrote:
> > +id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
> KVM_REG_RISCV_CONFIG_REG(isa));
> > +ret = kvm_get_one_reg(cs, id, );
> > +if (ret) {
> > +return ret;
> > +}
> > +env->misa_mxl |= isa;
> 
> This doesn't look right.
> I'm sure you meant
> 
>  env->misa_ext = isa;
> 
> 
> r~

Thanks, it will be modified in the next series.

Yifei

Re: [PATCH v1 03/12] target/riscv: Implement function kvm_arch_init_vcpu

[Richard Henderson]

On 11/20/21 8:46 AM, Yifei Jiang wrote:

+id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 
KVM_REG_RISCV_CONFIG_REG(isa));
+ret = kvm_get_one_reg(cs, id, );
+if (ret) {
+return ret;
+}
+env->misa_mxl |= isa;


This doesn't look right.
I'm sure you meant

env->misa_ext = isa;


r~

[PATCH v1 03/12] target/riscv: Implement function kvm_arch_init_vcpu

[Yifei Jiang]

Get isa info from kvm while kvm init.

Signed-off-by: Yifei Jiang 
Signed-off-by: Mingwang Li 
Reviewed-by: Alistair Francis 
---
 target/riscv/kvm.c | 32 +++-
 1 file changed, 31 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 687dd4b621..9f9692fb9e 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -38,6 +38,23 @@
 #include "qemu/log.h"
 #include "hw/loader.h"
 
+static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, uint64_t 
idx)
+{
+uint64_t id = KVM_REG_RISCV | type | idx;
+
+switch (riscv_cpu_mxl(env)) {
+case MXL_RV32:
+id |= KVM_REG_SIZE_U32;
+break;
+case MXL_RV64:
+id |= KVM_REG_SIZE_U64;
+break;
+default:
+g_assert_not_reached();
+}
+return id;
+}
+
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
 KVM_CAP_LAST_INFO
 };
@@ -79,7 +96,20 @@ void kvm_arch_init_irq_routing(KVMState *s)
 
 int kvm_arch_init_vcpu(CPUState *cs)
 {
-return 0;
+int ret = 0;
+target_ulong isa;
+RISCVCPU *cpu = RISCV_CPU(cs);
+CPURISCVState *env = >env;
+uint64_t id;
+
+id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 
KVM_REG_RISCV_CONFIG_REG(isa));
+ret = kvm_get_one_reg(cs, id, );
+if (ret) {
+return ret;
+}
+env->misa_mxl |= isa;
+
+return ret;
 }
 
 int kvm_arch_msi_data_to_gsi(uint32_t data)
-- 
2.19.1