Re: [Qemu-devel] [PATCH] target-lm32: fix LOG_DIS operand order

[Michael Tokarev]

12.10.2016 20:15, Michael Walle wrote:

The order of most opcodes with immediates was wrong (according to the
reference manual) in the (debug) logging. Additionally, one operand for the
andhi instruction was completly wrong. Fix these.


Applied to -trivial, thank you!

/mjt

Re: [Qemu-devel] [PATCH] target-lm32: fix LOG_DIS operand order

[Peter Maydell]

On 12 October 2016 at 18:15, Michael Walle  wrote:
> The order of most opcodes with immediates was wrong (according to the
> reference manual) in the (debug) logging. Additionally, one operand for the
> andhi instruction was completly wrong. Fix these.
>
> Signed-off-by: Michael Walle 

Reviewed-by: Peter Maydell 

PS: the wcsr disassembly also looks to be wrong:
LOG_DIS("wcsr r%d, %d\n", dc->r1, dc->csr);
where the manual says this is "wcsr csr, rX"
(separate bug though really).

thanks
-- PMM

[Qemu-devel] [PATCH] target-lm32: fix LOG_DIS operand order

[Michael Walle]

The order of most opcodes with immediates was wrong (according to the
reference manual) in the (debug) logging. Additionally, one operand for the
andhi instruction was completly wrong. Fix these.

Signed-off-by: Michael Walle 
---
 target-lm32/translate.c | 34 +-
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 534c17c..dc64cc6 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -211,7 +211,7 @@ static void dec_and(DisasContext *dc)
 
 static void dec_andhi(DisasContext *dc)
 {
-LOG_DIS("andhi r%d, r%d, %d\n", dc->r2, dc->r0, dc->imm16);
+LOG_DIS("andhi r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm16);
 
 tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
 }
@@ -274,7 +274,7 @@ static inline void gen_cond_branch(DisasContext *dc, int 
cond)
 
 static void dec_be(DisasContext *dc)
 {
-LOG_DIS("be r%d, r%d, %d\n", dc->r0, dc->r1,
+LOG_DIS("be r%d, r%d, %d\n", dc->r1, dc->r0,
 sign_extend(dc->imm16, 16) * 4);
 
 gen_cond_branch(dc, TCG_COND_EQ);
@@ -282,7 +282,7 @@ static void dec_be(DisasContext *dc)
 
 static void dec_bg(DisasContext *dc)
 {
-LOG_DIS("bg r%d, r%d, %d\n", dc->r0, dc->r1,
+LOG_DIS("bg r%d, r%d, %d\n", dc->r1, dc->r0,
 sign_extend(dc->imm16, 16 * 4));
 
 gen_cond_branch(dc, TCG_COND_GT);
@@ -290,7 +290,7 @@ static void dec_bg(DisasContext *dc)
 
 static void dec_bge(DisasContext *dc)
 {
-LOG_DIS("bge r%d, r%d, %d\n", dc->r0, dc->r1,
+LOG_DIS("bge r%d, r%d, %d\n", dc->r1, dc->r0,
 sign_extend(dc->imm16, 16) * 4);
 
 gen_cond_branch(dc, TCG_COND_GE);
@@ -298,7 +298,7 @@ static void dec_bge(DisasContext *dc)
 
 static void dec_bgeu(DisasContext *dc)
 {
-LOG_DIS("bgeu r%d, r%d, %d\n", dc->r0, dc->r1,
+LOG_DIS("bgeu r%d, r%d, %d\n", dc->r1, dc->r0,
 sign_extend(dc->imm16, 16) * 4);
 
 gen_cond_branch(dc, TCG_COND_GEU);
@@ -306,7 +306,7 @@ static void dec_bgeu(DisasContext *dc)
 
 static void dec_bgu(DisasContext *dc)
 {
-LOG_DIS("bgu r%d, r%d, %d\n", dc->r0, dc->r1,
+LOG_DIS("bgu r%d, r%d, %d\n", dc->r1, dc->r0,
 sign_extend(dc->imm16, 16) * 4);
 
 gen_cond_branch(dc, TCG_COND_GTU);
@@ -314,7 +314,7 @@ static void dec_bgu(DisasContext *dc)
 
 static void dec_bne(DisasContext *dc)
 {
-LOG_DIS("bne r%d, r%d, %d\n", dc->r0, dc->r1,
+LOG_DIS("bne r%d, r%d, %d\n", dc->r1, dc->r0,
 sign_extend(dc->imm16, 16) * 4);
 
 gen_cond_branch(dc, TCG_COND_NE);
@@ -367,7 +367,7 @@ static inline void gen_compare(DisasContext *dc, int cond)
 static void dec_cmpe(DisasContext *dc)
 {
 if (dc->format == OP_FMT_RI) {
-LOG_DIS("cmpei r%d, r%d, %d\n", dc->r0, dc->r1,
+LOG_DIS("cmpei r%d, r%d, %d\n", dc->r1, dc->r0,
 sign_extend(dc->imm16, 16));
 } else {
 LOG_DIS("cmpe r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
@@ -379,7 +379,7 @@ static void dec_cmpe(DisasContext *dc)
 static void dec_cmpg(DisasContext *dc)
 {
 if (dc->format == OP_FMT_RI) {
-LOG_DIS("cmpgi r%d, r%d, %d\n", dc->r0, dc->r1,
+LOG_DIS("cmpgi r%d, r%d, %d\n", dc->r1, dc->r0,
 sign_extend(dc->imm16, 16));
 } else {
 LOG_DIS("cmpg r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
@@ -391,7 +391,7 @@ static void dec_cmpg(DisasContext *dc)
 static void dec_cmpge(DisasContext *dc)
 {
 if (dc->format == OP_FMT_RI) {
-LOG_DIS("cmpgei r%d, r%d, %d\n", dc->r0, dc->r1,
+LOG_DIS("cmpgei r%d, r%d, %d\n", dc->r1, dc->r0,
 sign_extend(dc->imm16, 16));
 } else {
 LOG_DIS("cmpge r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
@@ -403,7 +403,7 @@ static void dec_cmpge(DisasContext *dc)
 static void dec_cmpgeu(DisasContext *dc)
 {
 if (dc->format == OP_FMT_RI) {
-LOG_DIS("cmpgeui r%d, r%d, %d\n", dc->r0, dc->r1,
+LOG_DIS("cmpgeui r%d, r%d, %d\n", dc->r1, dc->r0,
 zero_extend(dc->imm16, 16));
 } else {
 LOG_DIS("cmpgeu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
@@ -415,7 +415,7 @@ static void dec_cmpgeu(DisasContext *dc)
 static void dec_cmpgu(DisasContext *dc)
 {
 if (dc->format == OP_FMT_RI) {
-LOG_DIS("cmpgui r%d, r%d, %d\n", dc->r0, dc->r1,
+LOG_DIS("cmpgui r%d, r%d, %d\n", dc->r1, dc->r0,
 zero_extend(dc->imm16, 16));
 } else {
 LOG_DIS("cmpgu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
@@ -427,7 +427,7 @@ static void dec_cmpgu(DisasContext *dc)
 static void dec_cmpne(DisasContext *dc)
 {
 if (dc->format == OP_FMT_RI) {
-LOG_DIS("cmpnei r%d, r%d, %d\n", dc->r0, dc->r1,
+LOG_DIS("cmpnei r%d, r%d, %d\n", dc->r1, dc->r0,
 sign_extend(dc->imm16, 16));
 } else {
 LOG_DIS("cmpne r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
@@ -539,7 +539,7 @@ static void dec_modu(DisasContext *dc)
 static void