Re: [Qemu-devel] [PATCH v8 00/23] RISC-V QEMU Port Submission

[Richard W.M. Jones]

On Fri, Mar 09, 2018 at 04:43:34PM +, Peter Maydell wrote:
> On 5 March 2018 at 08:41, Richard W.M. Jones  wrote:
> >
> > The attached patch is also needed to avoid crashes during various
> > math-heavy test suites.
> 
> Applied to master, thanks.
> 
> FYI, sending patches as attachments in the middle of a long
> thread on something else is a good way to cause them to get
> lost. Luckily Michael ran into the same bug again and that
> reminded me to fish this one out.

Yup sorry I thought that the patch had been separately submitted,
but apparently it never was.

Rich.

-- 
Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones
Read my programming and virtualization blog: http://rwmj.wordpress.com
virt-builder quickly builds VMs from scratch
http://libguestfs.org/virt-builder.1.html

Re: [Qemu-devel] [PATCH v8 00/23] RISC-V QEMU Port Submission

[Peter Maydell]

On 5 March 2018 at 08:41, Richard W.M. Jones  wrote:
>
> The attached patch is also needed to avoid crashes during various
> math-heavy test suites.

Applied to master, thanks.

FYI, sending patches as attachments in the middle of a long
thread on something else is a good way to cause them to get
lost. Luckily Michael ran into the same bug again and that
reminded me to fish this one out.

thanks
-- PMM

Re: [Qemu-devel] [PATCH v8 00/23] RISC-V QEMU Port Submission

[Michael Clark]

On Mon, Mar 5, 2018 at 9:41 PM, Richard W.M. Jones 
wrote:

>
> The attached patch is also needed to avoid crashes during various
> math-heavy test suites.
>

Thanks. I missed your email.

I've integrated this and the other outstanding patches into the `riscv-all`
branch in the riscv repo here.

- https://github.com/riscv/riscv-qemu/commits/riscv-all

This also triggered aborts on riscv-tests, which is all the more reason to
get riscv-tests running in the CI so we spot these things early.

Thanks,
Michael.

Rich.
>
> From: Stef O'Rear 
>
> Date: Sat, 3 Mar 2018 03:46:00 -0800
>
> Subject: [PATCH] softfloat: fix crash on int conversion of SNaN
>
>
>> Signed-off-by: Stef O'Rear 
>
>
Signed-off-by: Michael Clark 


> ---
>
>  fpu/softfloat.c | 4 
>
>  1 file changed, 4 insertions(+)
>
>
>> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
>
> index e7fb0d357a..1da1db377e 100644
>
> --- a/fpu/softfloat.c
>
> +++ b/fpu/softfloat.c
>
> @@ -1342,6 +1342,8 @@ static int64_t round_to_int_and_pack(FloatParts in,
>> int rmode,
>
>  switch (p.cls) {
>
>  case float_class_snan:
>
>  case float_class_qnan:
>
> +case float_class_dnan:
>
> +case float_class_msnan:
>
>  return max;
>
>  case float_class_inf:
>
>  return p.sign ? min : max;
>
> @@ -1430,6 +1432,8 @@ static uint64_t round_to_uint_and_pack(FloatParts
>> in, int rmode, uint64_t max,
>
>  switch (p.cls) {
>
>  case float_class_snan:
>
>  case float_class_qnan:
>
> +case float_class_dnan:
>
> +case float_class_msnan:
>
>  s->float_exception_flags = orig_flags | float_flag_invalid;
>
>  return max;
>
>  case float_class_inf:
>
> --
>
> 2.15.1
>
>
>

Re: [Qemu-devel] [PATCH v8 00/23] RISC-V QEMU Port Submission

[Alex Bennée]

Richard W.M. Jones  writes:

> The attached patch is also needed to avoid crashes during various
> math-heavy test suites.
>
> Rich.
>
> --

> From: Stef O'Rear 
> Date: Sat, 3 Mar 2018 03:46:00 -0800
> Subject: [PATCH] softfloat: fix crash on int conversion of SNaN
>
> Signed-off-by: Stef O'Rear 
> ---
>  fpu/softfloat.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> index e7fb0d357a..1da1db377e 100644
> --- a/fpu/softfloat.c
> +++ b/fpu/softfloat.c
> @@ -1342,6 +1342,8 @@ static int64_t round_to_int_and_pack(FloatParts in, int 
> rmode,
>  switch (p.cls) {
>  case float_class_snan:
>  case float_class_qnan:
> +case float_class_dnan:
> +case float_class_msnan:
>  return max;
>  case float_class_inf:
>  return p.sign ? min : max;
> @@ -1430,6 +1432,8 @@ static uint64_t round_to_uint_and_pack(FloatParts in, 
> int rmode, uint64_t max,
>  switch (p.cls) {
>  case float_class_snan:
>  case float_class_qnan:
> +case float_class_dnan:
> +case float_class_msnan:
>  s->float_exception_flags = orig_flags | float_flag_invalid;
>  return max;
>  case float_class_inf:

Obviously I wasn't exercising the NaN exit paths enough and we added the
return_nan() common code fairly late in the series.

Reviewed-by: Alex Bennée 

--
Alex Bennée

Re: [Qemu-devel] [PATCH v8 00/23] RISC-V QEMU Port Submission

[Richard W.M. Jones]

The attached patch is also needed to avoid crashes during various
math-heavy test suites.

Rich.

-- 
Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones
Read my programming and virtualization blog: http://rwmj.wordpress.com
virt-p2v converts physical machines to virtual machines.  Boot with a
live CD or over the network (PXE) and turn machines into KVM guests.
http://libguestfs.org/virt-v2v
>From 8465cbda688cdc65dfe4037608c14cac087eae03 Mon Sep 17 00:00:00 2001
From: Stef O'Rear 
Date: Sat, 3 Mar 2018 03:46:00 -0800
Subject: [PATCH] softfloat: fix crash on int conversion of SNaN

Signed-off-by: Stef O'Rear 
---
 fpu/softfloat.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index e7fb0d357a..1da1db377e 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -1342,6 +1342,8 @@ static int64_t round_to_int_and_pack(FloatParts in, int 
rmode,
 switch (p.cls) {
 case float_class_snan:
 case float_class_qnan:
+case float_class_dnan:
+case float_class_msnan:
 return max;
 case float_class_inf:
 return p.sign ? min : max;
@@ -1430,6 +1432,8 @@ static uint64_t round_to_uint_and_pack(FloatParts in, int 
rmode, uint64_t max,
 switch (p.cls) {
 case float_class_snan:
 case float_class_qnan:
+case float_class_dnan:
+case float_class_msnan:
 s->float_exception_flags = orig_flags | float_flag_invalid;
 return max;
 case float_class_inf:
-- 
2.15.1

Re: [Qemu-devel] [PATCH v8 00/23] RISC-V QEMU Port Submission

[no-reply]

Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 1519998711-73430-1-git-send-email-...@sifive.com
Subject: [Qemu-devel] [PATCH v8 00/23] RISC-V QEMU Port Submission

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
   427cbc7e41..2e7b766594  master -> master
 * [new tag]   
patchew/1519998711-73430-1-git-send-email-...@sifive.com -> 
patchew/1519998711-73430-1-git-send-email-...@sifive.com
 t [tag update]patchew/20171228180814.9749-1-luke...@lukeshu.com -> 
patchew/20171228180814.9749-1-luke...@lukeshu.com
Switched to a new branch 'test'
21ffb8bdc0 RISC-V Build Infrastructure
ca5d7c8a1c SiFive Freedom U Series RISC-V Machine
da56267fc5 SiFive Freedom E Series RISC-V Machine
b78021cbc8 SiFive RISC-V PRCI Block
29220fc177 SiFive RISC-V UART Device
1b4ad0c360 RISC-V VirtIO Machine
7cbaa5fca0 SiFive RISC-V Test Finisher
1bd4951f4f RISC-V Spike Machines
21b1a969f4 SiFive RISC-V PLIC Block
20e07d9c45 SiFive RISC-V CLINT Block
6c6815bfc3 RISC-V HART Array
811ef36cf0 RISC-V HTIF Console
b802b6c3ce Add symbol table callback interface to load_elf
5c62396737 RISC-V Linux User Emulation
1989f74d4a RISC-V Physical Memory Protection
0ed6709cf3 RISC-V TCG Code Generation
e72021bda7 RISC-V GDB Stub
edc96cf22a RISC-V FPU Support
ea3e025b4c RISC-V CPU Helpers
3a84b79cb8 RISC-V Disassembler
c64a4f09ac RISC-V CPU Core Definition
1c8b9826bd RISC-V ELF Machine Definition
279429e751 RISC-V Maintainers

=== OUTPUT BEGIN ===
Checking PATCH 1/23: RISC-V Maintainers...
Checking PATCH 2/23: RISC-V ELF Machine Definition...
Checking PATCH 3/23: RISC-V CPU Core Definition...
Checking PATCH 4/23: RISC-V Disassembler...
WARNING: line over 80 characters
#649: FILE: disas/riscv.c:597:
+static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, 
rvc_end };

ERROR: line over 90 characters
#650: FILE: disas/riscv.c:598:
+static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, 
rvc_imm_eq_zero, rvc_end };

WARNING: line over 80 characters
#680: FILE: disas/riscv.c:628:
+static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, 
rvc_end };

WARNING: line over 80 characters
#681: FILE: disas/riscv.c:629:
+static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, 
rvc_end };

WARNING: line over 80 characters
#682: FILE: disas/riscv.c:630:
+static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, 
rvc_csr_eq_0xc00, rvc_end };

WARNING: line over 80 characters
#683: FILE: disas/riscv.c:631:
+static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, 
rvc_end };

ERROR: line over 90 characters
#684: FILE: disas/riscv.c:632:
+static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, 
rvc_csr_eq_0xc02, rvc_end };

ERROR: line over 90 characters
#685: FILE: disas/riscv.c:633:
+static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, 
rvc_csr_eq_0xc80, rvc_end };

WARNING: line over 80 characters
#686: FILE: disas/riscv.c:634:
+static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, 
rvc_csr_eq_0xc81, rvc_end };

ERROR: line over 90 characters
#687: FILE: disas/riscv.c:635:
+static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, 
rvc_csr_eq_0xc80, rvc_end };

WARNING: line over 80 characters
#688: FILE: disas/riscv.c:636:
+static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, 
rvc_end };

WARNING: line over 80 characters
#689: FILE: disas/riscv.c:637:
+static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, 
rvc_end };

WARNING: line over 80 characters
#690: FILE: disas/riscv.c:638:
+static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, 
rvc_csr_eq_0x001, rvc_end };

ERROR: line over 90 characters
#1089: FILE: disas/riscv.c:1037:
+{ "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, 
rv_op_addi, rv_op_addi },

WARNING: line over 80 characters
#1090: FILE: disas/riscv.c:1038:
+{ "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, 
rv_op_fld, 0 },

WARNING: line over 80 characters
#1091: FILE: disas/riscv.c:1039:
+{ "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, 
rv_op_lw },

WARNING: line over 80 characters
#1093: FILE: disas/riscv.c:1041:
+{ "c.fsd", rv_codec_cs_s

[Qemu-devel] [PATCH v8 00/23] RISC-V QEMU Port Submission

[Michael Clark]

QEMU RISC-V Emulation Support (RV64GC, RV32GC)

This release renames the SiFive machines to sifive_e and sifive_u
to represent the SiFive Everywhere and SiFive Unleashed platforms.
SiFive has configurable soft-core IP, so it is intended that these
machines will be extended to enable a variety of SiFive IP blocks.
The CPU definition infrastructure has been improved and there are
now vendor CPU modules including the SiFiVe E31, E51, U34 and U54
cores. The emulation accuracy for the E series has been improved
by disabling the MMU for the E series. S mode has been disabled on
cores that only support M mode and U mode. The two Spike machines
that support two privileged ISA versions have been coalesced into
one file. This series has Signed-off-by from the core contributors.

The git tree for the v8 patch series tree (squashed and rebased):

- https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v8

The git tree for the v1-v7 patch series with review commit history:

- https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v7
- https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v6
- https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v5
- https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v4
- https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v3
- https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v2
- https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v1

*** Known Issues ***

- Disassembler has some checkpatch warnings for the sake of code brevity
- scripts/qemu-binfmt-conf.sh has checkpatch warnings due to line length
- PMP (Physical Memory Protection) is as-of-yet unused and needs testing

*** Changelog ***

v8

- Added linux-user/riscv/target_elf.h during rebase
- Make resetvec configurable and clear mpp and mie on reset
- Use SiFive E31, E51, U34 and U54 cores in SiFive machines
- Define SiFive E31, E51, U34 and U54 cores
- Refactor CPU core definition in preparation for vendor cores
- Prevent S or U mode unless S or U extensions are present
- SiFive E Series cores have no MMU
- SiFive E Series cores have U mode
- Make privileged ISA v1.10 implicit in CPU types
- Remove DRAM_BASE and EXT_IO_BASE as they vary by machine
- Correctly handle mtvec and stvec alignment with respect to RVC
- Print more machine mode state in riscv_cpu_dump_state
- Make riscv_isa_string use compact extension order method
- Fix bug introduced in v6 RISCV_CPU_TYPE_NAME macro change
- Parameterize spike v1.9.1 config string
- Coalesce spike_v1.9.1 and spike_v1.10 machines
- Rename sifive_e300 to sifive_e, and sifive_u500 to sifive_u

v7

- Make spike_v1.10 the default machine
- Rename spike_v1.9 to spike_v1.9.1 to match privileged spec version
- Remove empty target/riscv/trace-events file
- Monitor ROM 32-bit reset code needs to be target endian
- Add TARGET_TIOCGPTPEER to linux-user/riscv/termbits.h
- Add -initrd support to the virt board
- Fix naming in spike machine interface header
- Update copyright notice on RISC-V Spike machines
- Update copyright notice on RISC-V HTIF Console device
- Change CPU Core and translator to GPLv2+
- Change RISC-V Disassembler to GPLv2+
- Change SiFive Test Finisher to GPLv2+
- Change SiFive CLINT to GPLv2+
- Change SiFive PRCI to GPLv2+
- Change SiFive PLIC to GPLv2+
- Change RISC-V spike machines to GPLv2+
- Change RISC-V virt machine to GPLv2+
- Change SiFive E300 machine to GPLv2+
- Change SiFive U500 machine to GPLv2+
- Change RISC-V Hart Array to GPLv2+
- Change RISC-V HTIF device to GPLv2+
- Change SiFiveUART device to GPLv2+

v6

- Drop IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax
- Remove some unnecessary commented debug statements
- Change RISCV_CPU_TYPE_NAME to use riscv-cpu suffix
- Define all CPU variants for linux-user
- qemu_log calls require trailing \n
- Replace PLIC printfs with qemu_log
- Tear out unused HTIF code and eliminate shouting debug messages
- Fix illegal instruction when sfence.vma is passed (rs2) arguments
- Make updates to PTE accessed and dirty bits atomic
- Only require atomic PTE updates on MTTCG enabled guests
- Page fault if accessed or dirty bits can't be updated
- Fix get_physical_address PTE reads and writes on riscv32
- Remove erroneous comments from the PLIC
- Default enable MTTCG
- Make WFI less conservative
- Unify local interrupt handling
- Expunge HTIF interrupts
- Always access mstatus.mip under a lock
- Don't implement rdtime/rdtimeh in system mode (bbl emulates them)
- Implement insreth/cycleh for rv32 and always enable user-mode counters
- Add GDB stub support for reading and writing CSRs
- Rename ENABLE_CHARDEV #ifdef from HTIF code
- Replace bad HTIF ELF code with load_elf symbol callback
- Convert chained if else fault handlers to switch statements
- Use RISCV exception codes for linux-user page faults

v5

- Implement NaN-boxing for flw, set high order bits to 1
- Use float_muladd_negate_* flags to floatXX_muladd
- Use IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax
- Fix TARGET_NR_syscalls
- Update