[Qemu-devel] [PATCH v8 2/9] softfloat: Clean code format in fpu/softfloat-specialize.h

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

fpu/softfloat-specialize.h is the most critical file in SoftFloat
library, since it handles numerous differences between platforms in
relation to floating point arithmetics. This patch makes the code
in this file more consistent format-wise, and hopefully easier to
debug and maintain.

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 fpu/softfloat-specialize.h | 99 +++---
 1 file changed, 50 insertions(+), 49 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 4411d3c..e03a529 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -273,7 +273,7 @@ static commonNaNT float16ToCommonNaN(float16 a, 
float_status *status)
 }
 z.sign = float16_val(a) >> 15;
 z.low = 0;
-z.high = ((uint64_t) float16_val(a))<<54;
+z.high = ((uint64_t) float16_val(a)) << 54;
 return z;
 }
 
@@ -284,7 +284,7 @@ static commonNaNT float16ToCommonNaN(float16 a, 
float_status *status)
 
 static float16 commonNaNToFloat16(commonNaNT a, float_status *status)
 {
-uint16_t mantissa = a.high>>54;
+uint16_t mantissa = a.high >> 54;
 
 if (status->default_nan_mode) {
 return float16_default_nan(status);
@@ -372,9 +372,9 @@ static commonNaNT float32ToCommonNaN(float32 a, 
float_status *status)
 if (float32_is_signaling_nan(a, status)) {
 float_raise(float_flag_invalid, status);
 }
-z.sign = float32_val(a)>>31;
+z.sign = float32_val(a) >> 31;
 z.low = 0;
-z.high = ( (uint64_t) float32_val(a) )<<41;
+z.high = ((uint64_t)float32_val(a)) << 41;
 return z;
 }
 
@@ -385,17 +385,18 @@ static commonNaNT float32ToCommonNaN(float32 a, 
float_status *status)
 
 static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
 {
-uint32_t mantissa = a.high>>41;
+uint32_t mantissa = a.high >> 41;
 
 if (status->default_nan_mode) {
 return float32_default_nan(status);
 }
 
-if ( mantissa )
+if (mantissa) {
 return make_float32(
-( ( (uint32_t) a.sign )<<31 ) | 0x7F80 | ( a.high>>41 ) );
-else
-return float32_default_nan;
+(((uint32_t)a.sign) << 31) | 0x7F80 | (a.high >> 41));
+} else {
+return float32_default_nan(status);
+}
 }
 
 /*
@@ -497,11 +498,10 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag 
bIsQNaN, flag bIsSNaN,
 return aIsLargerSignificand ? 0 : 1;
 }
 return bIsQNaN ? 1 : 0;
-}
-else if (aIsQNaN) {
-if (bIsSNaN || !bIsQNaN)
+} else if (aIsQNaN) {
+if (bIsSNaN || !bIsQNaN) {
 return 0;
-else {
+} else {
 return aIsLargerSignificand ? 0 : 1;
 }
 } else {
@@ -644,9 +644,9 @@ static float32 propagateFloat32NaN(float32 a, float32 b, 
float_status *status)
 return float32_default_nan(status);
 }
 
-if ((uint32_t)(av<<1) < (uint32_t)(bv<<1)) {
+if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) {
 aIsLargerSignificand = 0;
-} else if ((uint32_t)(bv<<1) < (uint32_t)(av<<1)) {
+} else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) {
 aIsLargerSignificand = 1;
 } else {
 aIsLargerSignificand = (av < bv) ? 1 : 0;
@@ -789,9 +789,9 @@ static commonNaNT float64ToCommonNaN(float64 a, 
float_status *status)
 if (float64_is_signaling_nan(a, status)) {
 float_raise(float_flag_invalid, status);
 }
-z.sign = float64_val(a)>>63;
+z.sign = float64_val(a) >> 63;
 z.low = 0;
-z.high = float64_val(a)<<12;
+z.high = float64_val(a) << 12;
 return z;
 }
 
@@ -808,13 +808,14 @@ static float64 commonNaNToFloat64(commonNaNT a, 
float_status *status)
 return float64_default_nan(status);
 }
 
-if ( mantissa )
+if (mantissa) {
 return make_float64(
-  ( ( (uint64_t) a.sign )<<63 )
-| LIT64( 0x7FF0 )
-| ( a.high>>12 ));
-else
-return float64_default_nan;
+  (((uint64_t) a.sign) << 63)
+| LIT64(0x7FF0)
+| (a.high >> 12));
+} else {
+return float64_default_nan(status);
+}
 }
 
 /*
@@ -844,9 +845,9 @@ static float64 propagateFloat64NaN(float64 a, float64 b, 
float_status *status)
 return float64_default_nan(status);
 }
 
-if ((uint64_t)(av<<1) < (uint64_t)(bv<<1)) {
+if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) {
 aIsLargerSignificand

[Qemu-devel] [PATCH v8 8/9] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

New set of helpers for handling nan2008-syle versions of instructions
<CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>, for Mips R6.

All involved instructions have float operand and integer result. Their
core functionality is implemented via invocations of appropriate SoftFloat
functions. The problematic cases are when the operand is a NaN, and also
when the operand (float) is out of the range of the result.

Here one can distinguish three cases:

CASE MIPS-A: (FCR31.NAN2008 == 1)

   1. Operand is a NaN, result should be 0;
   2. Operand is larger than INT_MAX, result should be INT_MAX;
   2. Operand is smaller than INT_MIN, result should be INT_MIN.

CASE MIPS-B: (FCR31.NAN2008 == 0)

   1. Operand is a NaN, result should be INT_MAX;
   2. Operand is larger than INT_MAX, result should be INT_MAX;
   2. Operand is smaller than INT_MIN, result should be INT_MAX.

CASE SOFTFLOAT:

   1. Operand is a NaN, result is INT_MAX;
   2. Operand is larger than INT_MAX, result is INT_MAX;
   2. Operand is smaller than INT_MIN, result is INT_MIN.

It is interesting that neither MIPS-A nor MIPS-B desired behaviors
are in this sense identical to correspondent SoftFloat behavior.

Current implementation of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
implements case MIPS-B. This patch relates to case MIPS-A. For case
MIPS-A, only return value for NaN-operands should be corrected after
appropriate SoftFloat library function is called.

Related MSA instructions FTRUNC_S and FTINT_S already handle well
all cases, in the fashion similar to the code from this patch.

Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/helper.h|  18 +--
 target-mips/op_helper.c | 369 +---
 target-mips/translate.c | 122 +---
 3 files changed, 461 insertions(+), 48 deletions(-)

diff --git a/target-mips/helper.h b/target-mips/helper.h
index 8546177..666936c 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -207,8 +207,6 @@ DEF_HELPER_4(ctc1, void, env, tl, i32, i32)
 DEF_HELPER_2(float_cvtd_s, i64, env, i32)
 DEF_HELPER_2(float_cvtd_w, i64, env, i32)
 DEF_HELPER_2(float_cvtd_l, i64, env, i64)
-DEF_HELPER_2(float_cvtl_d, i64, env, i64)
-DEF_HELPER_2(float_cvtl_s, i64, env, i32)
 DEF_HELPER_2(float_cvtps_pw, i64, env, i64)
 DEF_HELPER_2(float_cvtpw_ps, i64, env, i64)
 DEF_HELPER_2(float_cvts_d, i32, env, i64)
@@ -216,8 +214,6 @@ DEF_HELPER_2(float_cvts_w, i32, env, i32)
 DEF_HELPER_2(float_cvts_l, i32, env, i64)
 DEF_HELPER_2(float_cvts_pl, i32, env, i32)
 DEF_HELPER_2(float_cvts_pu, i32, env, i32)
-DEF_HELPER_2(float_cvtw_s, i32, env, i32)
-DEF_HELPER_2(float_cvtw_d, i32, env, i64)
 
 DEF_HELPER_3(float_addr_ps, i64, env, i64, i64)
 DEF_HELPER_3(float_mulr_ps, i64, env, i64, i64)
@@ -242,14 +238,20 @@ FOP_PROTO(mina)
 #undef FOP_PROTO
 
 #define FOP_PROTO(op)\
-DEF_HELPER_2(float_ ## op ## l_s, i64, env, i32) \
-DEF_HELPER_2(float_ ## op ## l_d, i64, env, i64) \
-DEF_HELPER_2(float_ ## op ## w_s, i32, env, i32) \
-DEF_HELPER_2(float_ ## op ## w_d, i32, env, i64)
+DEF_HELPER_2(float_ ## op ## _l_s, i64, env, i32) \
+DEF_HELPER_2(float_ ## op ## _l_d, i64, env, i64) \
+DEF_HELPER_2(float_ ## op ## _w_s, i32, env, i32) \
+DEF_HELPER_2(float_ ## op ## _w_d, i32, env, i64)
+FOP_PROTO(cvt)
 FOP_PROTO(round)
 FOP_PROTO(trunc)
 FOP_PROTO(ceil)
 FOP_PROTO(floor)
+FOP_PROTO(cvt_2008)
+FOP_PROTO(round_2008)
+FOP_PROTO(trunc_2008)
+FOP_PROTO(ceil_2008)
+FOP_PROTO(floor_2008)
 #undef FOP_PROTO
 
 #define FOP_PROTO(op)\
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 9e7e2e0..0d1e959 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2448,6 +2448,7 @@ void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
 
 #define FLOAT_TWO32 make_float32(1 << 30)
 #define FLOAT_TWO64 make_float64(1ULL << 62)
+
 #define FP_TO_INT32_OVERFLOW 0x7fff
 #define FP_TO_INT64_OVERFLOW 0x7fffULL
 
@@ -2683,7 +2684,7 @@ uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t 
dt0)
 return fdt2;
 }
 
-uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
+uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
 {
 uint64_t dt2;
 
@@ -2696,7 +2697,7 @@ uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t 
fdt0)
 return dt2;
 }
 
-uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
+uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
 {
 uint64_t dt2;
 
@@ -2791,7 +2792,7 @@ uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t 
wth0)
 return wt2;
 }
 
-uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
+uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
 {
 uint32_t wt2;
 
@@ -2804,7 +2805,7 @@ uint32_t help

[Qemu-devel] [PATCH v8 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch modifies SoftFloat library so that it can be configured in
run-time in relation to the meaning of signaling NaN bit, while, at the
same time, strictly preserving its behavior on all existing platforms.

Background:

In floating-point calculations, there is a need for denoting undefined or
unrepresentable values. This is achieved by defining certain floating-point
numerical values to be NaNs (which stands for "not a number"). For additional
reasons, virtually all modern floating-point unit implementations use two
kinds of NaNs: quiet and signaling. The binary representations of these two
kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally,
the first bit of mantissa).

Up to 2008, standards for floating-point did not specify all details about
binary representation of NaNs. More specifically, the meaning of the bit
that is used for distinguishing between signaling and quiet NaNs was not
strictly prescribed. (IEEE 754-2008 was the first floating-point standard
that defined that meaning clearly, see [1], p. 35) As a result, different
platforms took different approaches, and that presented considerable
challenge for multi-platform emulators like QEMU.

Mips platform represents the most complex case among QEMU-supported
platforms regarding signaling NaN bit. Up to the Release 6 of Mips
architecture, "1" in signaling NaN bit denoted signaling NaN, which is
opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
that, Mips architecture for SIMD (also known as MSA, or vector instructions)
also specifies signaling bit in accordance to IEEE standard. MSA unit can be
implemented with both pre-Release 6 and Release 6 main processor units.

QEMU uses SoftFloat library to implement various floating-point-related
instructions on all platforms. The current QEMU implementation allows for
defining meaning of signaling NaN bit during build time, and is implemented
via preprocessor macro called SNAN_BIT_IS_ONE.

On the other hand, the change in this patch enables SoftFloat library to be
configured in run-time. This configuration is meant to occur during CPU
initialization, at the moment when it is definitely known what desired
behavior for particular CPU (or any additional FPUs) is.

The change is implemented so that it is consistent with existing
implementation of similar cases. This means that structure float_status is
used for passing the information about desired signaling NaN bit on each
invocation of SoftFloat functions. The additional field in float_status is
called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.

IMPORTANT:

This change is not meant to create any change in emulator behavior or
functionality on any platform. It just provides the means for SoftFloat
library to be used in a more flexible way - in other words, it will just
prepare SoftFloat library for usage related to Mips platform and its
specifics regarding signaling bit meaning, which is done in some of
subsequent patches from this series.

Further break down of changes:

  1) Added field snan_bit_is_one to the structure float_status, and
 correspondent setter function set_snan_bit_is_one().

  2) Constants <float16|float32|float64|floatx80|float128>_default_nan
 (used both internally and externally) converted to functions
 <float16|float32|float64|floatx80|float128>_default_nan(float_status*).
 This is necessary since they are dependent on signaling bit meaning.
 At the same time, for the sake of code cleanup and simplicity, constants
 <floatx80|float128>_default_nan_<low|high> (used only internally within
 SoftFloat library) are removed, as not needed.

  3) Added a float_status* argument to SoftFloat library functions
 XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
 XXX_maybe_silence_nan(XXX a_). This argument must be present in
 order to enable correct invocation of new version of functions
 XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128>
 here)

  4) Updated code for all platforms to reflect changes in SoftFloat library.
 This change is twofolds: it includes modifications of SoftFloat library
 functions invocations, and an addition of invocation of function
 set_snan_bit_is_one() during CPU initialization, with arguments that
 are appropriate for each particular platform. It was established that
 all platforms zero their main CPU data structures, so snan_bit_is_one(0)
 in appropriate places is not added, as it is not needed.

[1] "IEEE Standard for Floating-Point Arithmetic",
IEEE Computer Society, August 29, 2008.

Tested-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> (TriCore part)
Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Sign

[Qemu-devel] [PATCH v8 4/9] softfloat: For Mips only, correct order in pickNaNMulAdd()

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Only for Mips platform, and only for cases when snan_bit_is_one is 0,
correct the order of argument comparisons in pickNaNMulAdd().

For more info, see [1], page 53, section "3.5.3 NaN Propagation".

[1] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32 SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016

Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 fpu/softfloat-specialize.h | 41 +
 1 file changed, 29 insertions(+), 12 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 093218f..11fc66b 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -571,19 +571,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag 
bIsQNaN, flag bIsSNaN,
 return 3;
 }
 
-/* Prefer sNaN over qNaN, in the a, b, c order. */
-if (aIsSNaN) {
-return 0;
-} else if (bIsSNaN) {
-return 1;
-} else if (cIsSNaN) {
-return 2;
-} else if (aIsQNaN) {
-return 0;
-} else if (bIsQNaN) {
-return 1;
+if (status->snan_bit_is_one) {
+/* Prefer sNaN over qNaN, in the c, a, b order. */
+if (cIsSNaN) {
+return 2;
+} else if (aIsSNaN) {
+return 0;
+} else if (bIsSNaN) {
+return 1;
+} else if (cIsQNaN) {
+return 2;
+} else if (aIsQNaN) {
+return 0;
+} else {
+return 1;
+}
 } else {
-return 2;
+/* Prefer sNaN over qNaN, in the a, b, c order. */
+if (aIsSNaN) {
+return 0;
+} else if (bIsSNaN) {
+return 1;
+} else if (cIsSNaN) {
+return 2;
+} else if (aIsQNaN) {
+return 0;
+} else if (bIsQNaN) {
+return 1;
+} else {
+return 2;
+}
 }
 }
 #elif defined(TARGET_PPC)
-- 
1.9.1

[Qemu-devel] [PATCH v7 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch modifies SoftFloat library so that it can be configured in
run-time in relation to the meaning of signaling NaN bit, while, at the
same time, strictly preserving its behavior on all existing platforms.

Background:

In floating-point calculations, there is a need for denoting undefined or
unrepresentable values. This is achieved by defining certain floating-point
numerical values to be NaNs (which stands for "not a number"). For additional
reasons, virtually all modern floating-point unit implementations use two
kinds of NaNs: quiet and signaling. The binary representations of these two
kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally,
the first bit of mantissa).

Up to 2008, standards for floating-point did not specify all details about
binary representation of NaNs. More specifically, the meaning of the bit
that is used for distinguishing between signaling and quiet NaNs was not
strictly prescribed. (IEEE 754-2008 was the first floating-point standard
that defined that meaning clearly, see [1], p. 35) As a result, different
platforms took different approaches, and that presented considerable
challenge for multi-platform emulators like QEMU.

Mips platform represents the most complex case among QEMU-supported
platforms regarding signaling NaN bit. Up to the Release 6 of Mips
architecture, "1" in signaling NaN bit denoted signaling NaN, which is
opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
that, Mips architecture for SIMD (also known as MSA, or vector instructions)
also specifies signaling bit in accordance to IEEE standard. MSA unit can be
implemented with both pre-Release 6 and Release 6 main processor units.

QEMU uses SoftFloat library to implement various floating-point-related
instructions on all platforms. The current QEMU implementation allows for
defining meaning of signaling NaN bit during build time, and is implemented
via preprocessor macro called SNAN_BIT_IS_ONE.

On the other hand, the change in this patch enables SoftFloat library to be
configured in run-time. This configuration is meant to occur during CPU
initialization, at the moment when it is definitely known what desired
behavior for particular CPU (or any additional FPUs) is.

The change is implemented so that it is consistent with existing
implementation of similar cases. This means that structure float_status is
used for passing the information about desired signaling NaN bit on each
invocation of SoftFloat functions. The additional field in float_status is
called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.

IMPORTANT:

This change is not meant to create any change in emulator behavior or
functionality on any platform. It just provides the means for SoftFloat
library to be used in a more flexible way - in other words, it will just
prepare SoftFloat library for usage related to Mips platform and its
specifics regarding signaling bit meaning, which is done in some of
subsequent patches from this series.

Further break down of changes:

  1) Added field snan_bit_is_one to the structure float_status, and
 correspondent setter function set_snan_bit_is_one().

  2) Constants <float16|float32|float64|floatx80|float128>_default_nan
 (used both internally and externally) converted to functions
 <float16|float32|float64|floatx80|float128>_default_nan(float_status*).
 This is necessary since they are dependent on signaling bit meaning.
 At the same time, for the sake of code cleanup and simplicity, constants
 <floatx80|float128>_default_nan_<low|high> (used only internally within
 SoftFloat library) are removed, as not needed.

  3) Added a float_status* argument to SoftFloat library functions
 XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
 XXX_maybe_silence_nan(XXX a_). This argument must be present in
 order to enable correct invocation of new version of functions
 XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128>
 here)

  4) Updated code for all platforms to reflect changes in SoftFloat library.
 This change is twofolds: it includes modifications of SoftFloat library
 functions invocations, and an addition of invocation of function
 set_snan_bit_is_one() during CPU initialization, with arguments that
 are appropriate for each particular platform. It was established that
 all platforms zero their main CPU data structures, so snan_bit_is_one(0)
 in appropriate places is not added, as it is not needed.

[1] "IEEE Standard for Floating-Point Arithmetic",
IEEE Computer Society, August 29, 2008.

Tested-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> (TriCore part)
Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Sign

[Qemu-devel] [PATCH v7 0/9] IEEE 754-2008 support for Mips

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

v7 - preprocesor constants for FCR31 bits removed
   - cleanup items in CFC1 and CTC1 handling removed
   - initialization of snan_bit_is_one for main FP unit moved
 from patch 6 to patch 9
   - an instance of "!" corrected to "~" (logical vs. bitwise negation)

v6 - code for hanlding MSA FCLASS instructions slightly simplified
   - handling of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> corrected for
 nan2008 case
   - R/W bitmask for FCR31 introduced, and related functionalities
 implemented
   - cleanup items for SoftFloat library are now in a separate patch
   - minor errors corrected
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-05/msg02513.html)

v5 - platform initialization code revisited one more time;
   - handling of CLASS.<S|D> and their MSA counterparts revisited;
   - better orgranization of patches (squashing, splitting);
   - corrected handling of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>;
   - code cleanup item in genfarith() - order of cases;
   - scripts/checkpatch.pl executed and errors addressed.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg02774.html)

v4 - Added code cleanup items:
   a. Capitalization of hex constants in softfloat-specialize.h;
   b. White spaces in softfloat-specialize.h;
   c. Order of Mips helpers for CVT.<L|W>.<S|D>.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01962.html)

v3 - Patch series reorganized into 6 patches instead of 2.
   - Commit messages improved.
   - Except commit messages, net result of applying v3 and v2 is the same.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01870.html)

v2 - Relevant CPU initialization code changes revisited for all platforms.
   - In connection with <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> and
 <ABS|NEG>.<S|D> Mips instructions handling, decision on whether
 pre-nan2008/pre-abs2008 or nan2008/abs2008 handling will apply
 moved from run-time to translate-time.
   - For Mips only, in nan2008 cases only, default NaN values fixed.
   - For Mips only, in nan2008 cases only, order in pickNaNMulAdd() fixed.
   - Code cleanup issues:
   a. Constants <floatx80|float128>_default_nan_<low|high> removed;
   b. Suffix <l|w>_<s|d> replaced with _<l|w>_<s|d> for some Mips helpers;
   c. In vicinity of changes, fixed not-beautiful code formatting.
   - Commit messages improved.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01232.html)

v1 - Initial version
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg06082.html)

Mips platform represents the most complex case among QEMU-supported
platforms in reference to certain aspects of floating-point arithmetics.
This is mostly a consequence of the fact that Mips platform, for many
reasons, evolved considerably over time related to floating-point
arithmetics standards (significantly more than other platforms).
It has been difficult for emulators like QEMU to support such variety
of configurations.

This patch series provides number of IEEE 754-2008-related features to
Mips platform. It addresses the most sensitive changes that require
modification of SoftFloat library, also used by most other platforms.

In order to make develpoment, testing, and integration easier, the patch
is split into two distinct parts:

   1. Part 1 (patches 1/9, 2/9, 3/9, 4/9, 5/9) that does not change any
  calculation or behavior on any platform (and, for that matter, even on
  Mips platform). Its sole purpose is to address platform independant
  issues in a non-invasive manner, and to make Part 2 possible.

   2. Part 2 (patches 6/9, 7/9, 8/9, 9/9) that sets some Mips processors to
  use provisions from Part 1, and additionally implements number of
  IEEE 754-2008-relates features for Mips, while, at the same time,
  dealing with files located in directory target-mips only.

This patch series is based on the original set of patches proposed by Maciej W.
Rozycki: http://lists.nongnu.org/archive/html/qemu-devel/2014-12/msg00968.html

Aleksandar Markovic (9):
  softfloat: Implement run-time-configurable meaning of signaling NaN bit
  softfloat: Clean code format in fpu/softfloat-specialize.h
  softfloat: For Mips only, correct default NaN values
  softfloat: For Mips only, correct order in pickNaNMulAdd()
  linux-user: Update preprocessor constants for Mips-specific e_flags bits
  target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSA
  target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>
  target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
  target-mips: Implement FCR31's R/W bitmask and related functionalities

 fpu/softfloat-specialize.h| 664 +++

[Qemu-devel] [PATCH v8 0/9] IEEE 754-2008 support for Mips

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

v8 - fixed mail recipients

v7 - preprocesor constants for FCR31 bits removed
   - cleanup items in CFC1 and CTC1 handling removed
   - initialization of snan_bit_is_one for main FP unit moved
 from patch 6 to patch 9
   - an instance of "!" corrected to "~" (logical vs. bitwise negation)
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-06/msg00886.html)

v6 - code for hanlding MSA FCLASS instructions slightly simplified
   - handling of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> corrected for
 nan2008 case
   - R/W bitmask for FCR31 introduced, and related functionalities
 implemented
   - cleanup items for SoftFloat library are now in a separate patch
   - minor errors corrected
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-05/msg02513.html)

v5 - platform initialization code revisited one more time;
   - handling of CLASS.<S|D> and their MSA counterparts revisited;
   - better orgranization of patches (squashing, splitting);
   - corrected handling of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>;
   - code cleanup item in genfarith() - order of cases;
   - scripts/checkpatch.pl executed and errors addressed.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg02774.html)

v4 - Added code cleanup items:
   a. Capitalization of hex constants in softfloat-specialize.h;
   b. White spaces in softfloat-specialize.h;
   c. Order of Mips helpers for CVT.<L|W>.<S|D>.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01962.html)

v3 - Patch series reorganized into 6 patches instead of 2.
   - Commit messages improved.
   - Except commit messages, net result of applying v3 and v2 is the same.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01870.html)

v2 - Relevant CPU initialization code changes revisited for all platforms.
   - In connection with <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> and
 <ABS|NEG>.<S|D> Mips instructions handling, decision on whether
 pre-nan2008/pre-abs2008 or nan2008/abs2008 handling will apply
 moved from run-time to translate-time.
   - For Mips only, in nan2008 cases only, default NaN values fixed.
   - For Mips only, in nan2008 cases only, order in pickNaNMulAdd() fixed.
   - Code cleanup issues:
   a. Constants <floatx80|float128>_default_nan_<low|high> removed;
   b. Suffix <l|w>_<s|d> replaced with _<l|w>_<s|d> for some Mips helpers;
   c. In vicinity of changes, fixed not-beautiful code formatting.
   - Commit messages improved.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01232.html)

v1 - Initial version
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg06082.html)

Mips platform represents the most complex case among QEMU-supported
platforms in reference to certain aspects of floating-point arithmetics.
This is mostly a consequence of the fact that Mips platform, for many
reasons, evolved considerably over time related to floating-point
arithmetics standards (significantly more than other platforms).
It has been difficult for emulators like QEMU to support such variety
of configurations.

This patch series provides number of IEEE 754-2008-related features to
Mips platform. It addresses the most sensitive changes that require
modification of SoftFloat library, also used by most other platforms.

In order to make develpoment, testing, and integration easier, the patch
is split into two distinct parts:

   1. Part 1 (patches 1/9, 2/9, 3/9, 4/9, 5/9) that does not change any
  calculation or behavior on any platform (and, for that matter, even on
  Mips platform). Its sole purpose is to address platform independant
  issues in a non-invasive manner, and to make Part 2 possible.

   2. Part 2 (patches 6/9, 7/9, 8/9, 9/9) that sets some Mips processors to
  use provisions from Part 1, and additionally implements number of
  IEEE 754-2008-relates features for Mips, while, at the same time,
  dealing with files located in directory target-mips only.

This patch series is based on the original set of patches proposed by Maciej W.
Rozycki: http://lists.nongnu.org/archive/html/qemu-devel/2014-12/msg00968.html

Aleksandar Markovic (9):
  softfloat: Implement run-time-configurable meaning of signaling NaN bit
  softfloat: Clean code format in fpu/softfloat-specialize.h
  softfloat: For Mips only, correct default NaN values
  softfloat: For Mips only, correct order in pickNaNMulAdd()
  linux-user: Update preprocessor constants for Mips-specific e_flags bits
  target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSA
  target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>
  target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
  target-mips:

[Qemu-devel] [PATCH v8 5/9] linux-user: Update preprocessor constants for Mips-specific e_flags bits

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Missing values EF_MIPS_FP64 and EF_MIPS_NAN2008 added, and the format
of the surrounding code segment adjusted.

Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 include/elf.h | 18 ++
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/include/elf.h b/include/elf.h
index 28d448b..b7f59e4 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -46,14 +46,16 @@ typedef int64_t  Elf64_Sxword;
 #define EF_MIPS_ABI_O320x1000  /* O32 ABI.  */
 #define EF_MIPS_ABI_O640x2000  /* O32 extended for 64 
bit.  */
 
-#define EF_MIPS_NOREORDER 0x0001
-#define EF_MIPS_PIC   0x0002
-#define EF_MIPS_CPIC  0x0004
-#define EF_MIPS_ABI2   0x0020
-#define EF_MIPS_OPTIONS_FIRST  0x0080
-#define EF_MIPS_32BITMODE  0x0100
-#define EF_MIPS_ABI0xf000
-#define EF_MIPS_ARCH  0xf000
+#define EF_MIPS_NOREORDER   0x0001
+#define EF_MIPS_PIC 0x0002
+#define EF_MIPS_CPIC0x0004
+#define EF_MIPS_ABI20x0020
+#define EF_MIPS_OPTIONS_FIRST   0x0080
+#define EF_MIPS_32BITMODE   0x0100
+#define EF_MIPS_FP640x0200
+#define EF_MIPS_NAN2008 0x0400
+#define EF_MIPS_ABI 0xf000
+#define EF_MIPS_ARCH0xf000
 
 /* These constants define the different elf file types */
 #define ET_NONE   0
-- 
1.9.1

[Qemu-devel] [PATCH v8 3/9] softfloat: For Mips only, correct default NaN values

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Only for Mips platform, and only for cases when snan_bit_is_one is 0,
correct default NaN values (in their 16-, 32-, and 64-bit flavors).

For more info, see [1], page 84, Table 6.3 "Value Supplied When a New
Quiet NaN Is Created", and [2], page 52, Table 3.7 "Default NaN
Encodings".

[1] "MIPS Architecture For Programmers Volume II-A:
The MIPS64 Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

[2] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32 SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016

Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 fpu/softfloat-specialize.h | 12 
 1 file changed, 12 insertions(+)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index e03a529..093218f 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -97,7 +97,11 @@ float16 float16_default_nan(float_status *status)
 if (status->snan_bit_is_one) {
 return const_float16(0x7DFF);
 } else {
+#if defined(TARGET_MIPS)
+return const_float16(0x7E00);
+#else
 return const_float16(0xFE00);
+#endif
 }
 #endif
 }
@@ -116,7 +120,11 @@ float32 float32_default_nan(float_status *status)
 if (status->snan_bit_is_one) {
 return const_float32(0x7FBF);
 } else {
+#if defined(TARGET_MIPS)
+return const_float32(0x7FC0);
+#else
 return const_float32(0xFFC0);
+#endif
 }
 #endif
 }
@@ -135,7 +143,11 @@ float64 float64_default_nan(float_status *status)
 if (status->snan_bit_is_one) {
 return const_float64(LIT64(0x7FF7));
 } else {
+#if defined(TARGET_MIPS)
+return const_float64(LIT64(0x7FF8));
+#else
 return const_float64(LIT64(0xFFF8));
+#endif
 }
 #endif
 }
-- 
1.9.1

[Qemu-devel] [PATCH v8 9/9] target-mips: Implement FCR31's R/W bitmask and related functionalities

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch implements read and write access rules for Mips floating
point control and status register (FCR31). The change can be divided
into following parts:

- Add fields that will keep FCR31's R/W bitmask in procesor
  definitions and processor float_status structure.

- Add appropriate value for FCR31's R/W bitmask for each supported
  processor.

- Add preprocessor definition of FCR31's FS bit, and update
  related code for setting this bit.

- Add function for setting snan_bit_is_one, and integrate it in
  appropriate places.

- Modify handling of CTC1 (case 31) instruction to use FCR31's R/W
  bitmask.

- Modify handling user mode executables for Mips, in relation to the
  bit EF_MIPS_NAN2008 from ELF header, that is in turn related to
  reading and writing to FCR31.

- Modify gdb behavior in relation to FCR31.

Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 linux-user/main.c| 14 ++
 target-mips/cpu.h| 15 ---
 target-mips/gdbstub.c|  8 +++-
 target-mips/op_helper.c  | 18 ++
 target-mips/translate.c  |  5 ++---
 target-mips/translate_init.c | 26 ++
 6 files changed, 63 insertions(+), 23 deletions(-)

diff --git a/linux-user/main.c b/linux-user/main.c
index 5f3ec97..cc21057 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -4608,6 +4608,20 @@ int main(int argc, char **argv, char **envp)
 if (regs->cp0_epc & 1) {
 env->hflags |= MIPS_HFLAG_M16;
 }
+if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
+((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
+if ((env->active_fpu.fcr31_rw_bitmask &
+  (1 << FCR31_NAN2008)) == 0) {
+fprintf(stderr, "ELF binary's NaN mode not supported by 
CPU\n");
+exit(1);
+}
+if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
+env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
+} else {
+env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
+}
+restore_snan_bit_mode(env);
+}
 }
 #elif defined(TARGET_OPENRISC)
 {
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 6478420..f71bb94 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -110,9 +110,11 @@ struct CPUMIPSFPUContext {
 #define FCR0_PRID 8
 #define FCR0_REV 0
 /* fcsr */
+uint32_t fcr31_rw_bitmask;
 uint32_t fcr31;
-#define FCR31_ABS2008 19
-#define FCR31_NAN2008 18
+#define FCR31_NAN2008 18
+#define FCR31_ABS2008 19
+#define FCR31_FS  24
 #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 
24)) : (1 << 23)); } while(0)
 #define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) 
+ 24)) : (1 << 23)); } while(0)
 #define GET_FP_COND(env) env).fcr31 >> 24) & 0xfe) | (((env).fcr31 
>> 23) & 0x1))
@@ -813,14 +815,21 @@ static inline void restore_rounding_mode(CPUMIPSState 
*env)
 
 static inline void restore_flush_mode(CPUMIPSState *env)
 {
-set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
+set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
   >active_fpu.fp_status);
 }
 
+static inline void restore_snan_bit_mode(CPUMIPSState *env)
+{
+set_snan_bit_is_one(((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0),
+>active_fpu.fp_status);
+}
+
 static inline void restore_fp_status(CPUMIPSState *env)
 {
 restore_rounding_mode(env);
 restore_flush_mode(env);
+restore_snan_bit_mode(env);
 }
 
 static inline void restore_msa_fp_status(CPUMIPSState *env)
diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c
index b0b4a32..aacc721 100644
--- a/target-mips/gdbstub.c
+++ b/target-mips/gdbstub.c
@@ -89,11 +89,9 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t 
*mem_buf, int n)
 if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) {
 switch (n) {
 case 70:
-env->active_fpu.fcr31 = tmp & 0xFF83;
-/* set rounding mode */
-restore_rounding_mode(env);
-/* set flush-to-zero mode */
-restore_flush_mode(env);
+env->active_fpu.fcr31 = (tmp & env->active_fpu.fcr31_rw_bitmask) |
+  (env->active_fpu.fcr31 & 
~(env->active_fpu.fcr31_rw_bitmask));
+restore_fp_status(env);
 break;
 case 71:
 /* FIR is read-only.  Ig

[Qemu-devel] [PATCH v9 02/10] softfloat: Clean code format in fpu/softfloat-specialize.h

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

fpu/softfloat-specialize.h is the most critical file in SoftFloat
library, since it handles numerous differences between platforms in
relation to floating point arithmetics. This patch makes the code
in this file more consistent format-wise, and hopefully easier to
debug and maintain.

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 fpu/softfloat-specialize.h | 71 +++---
 1 file changed, 36 insertions(+), 35 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 8f9e4cc..981d665 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -273,7 +273,7 @@ static commonNaNT float16ToCommonNaN(float16 a, 
float_status *status)
 }
 z.sign = float16_val(a) >> 15;
 z.low = 0;
-z.high = ((uint64_t) float16_val(a))<<54;
+z.high = ((uint64_t) float16_val(a)) << 54;
 return z;
 }
 
@@ -284,7 +284,7 @@ static commonNaNT float16ToCommonNaN(float16 a, 
float_status *status)
 
 static float16 commonNaNToFloat16(commonNaNT a, float_status *status)
 {
-uint16_t mantissa = a.high>>54;
+uint16_t mantissa = a.high >> 54;
 
 if (status->default_nan_mode) {
 return float16_default_nan(status);
@@ -372,9 +372,9 @@ static commonNaNT float32ToCommonNaN(float32 a, 
float_status *status)
 if (float32_is_signaling_nan(a, status)) {
 float_raise(float_flag_invalid, status);
 }
-z.sign = float32_val(a)>>31;
+z.sign = float32_val(a) >> 31;
 z.low = 0;
-z.high = ( (uint64_t) float32_val(a) )<<41;
+z.high = ((uint64_t)float32_val(a)) << 41;
 return z;
 }
 
@@ -385,17 +385,18 @@ static commonNaNT float32ToCommonNaN(float32 a, 
float_status *status)
 
 static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
 {
-uint32_t mantissa = a.high>>41;
+uint32_t mantissa = a.high >> 41;
 
 if (status->default_nan_mode) {
 return float32_default_nan(status);
 }
 
-if ( mantissa )
+if (mantissa) {
 return make_float32(
-( ( (uint32_t) a.sign )<<31 ) | 0x7F80 | ( a.high>>41 ) );
-else
-return float32_default_nan;
+(((uint32_t)a.sign) << 31) | 0x7F80 | (a.high >> 41));
+} else {
+return float32_default_nan(status);
+}
 }
 
 /*
@@ -497,11 +498,10 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag 
bIsQNaN, flag bIsSNaN,
 return aIsLargerSignificand ? 0 : 1;
 }
 return bIsQNaN ? 1 : 0;
-}
-else if (aIsQNaN) {
-if (bIsSNaN || !bIsQNaN)
+} else if (aIsQNaN) {
+if (bIsSNaN || !bIsQNaN) {
 return 0;
-else {
+} else {
 return aIsLargerSignificand ? 0 : 1;
 }
 } else {
@@ -644,9 +644,9 @@ static float32 propagateFloat32NaN(float32 a, float32 b, 
float_status *status)
 return float32_default_nan(status);
 }
 
-if ((uint32_t)(av<<1) < (uint32_t)(bv<<1)) {
+if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) {
 aIsLargerSignificand = 0;
-} else if ((uint32_t)(bv<<1) < (uint32_t)(av<<1)) {
+} else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) {
 aIsLargerSignificand = 1;
 } else {
 aIsLargerSignificand = (av < bv) ? 1 : 0;
@@ -788,9 +788,9 @@ static commonNaNT float64ToCommonNaN(float64 a, 
float_status *status)
 if (float64_is_signaling_nan(a, status)) {
 float_raise(float_flag_invalid, status);
 }
-z.sign = float64_val(a)>>63;
+z.sign = float64_val(a) >> 63;
 z.low = 0;
-z.high = float64_val(a)<<12;
+z.high = float64_val(a) << 12;
 return z;
 }
 
@@ -801,19 +801,20 @@ static commonNaNT float64ToCommonNaN(float64 a, 
float_status *status)
 
 static float64 commonNaNToFloat64(commonNaNT a, float_status *status)
 {
-uint64_t mantissa = a.high>>12;
+uint64_t mantissa = a.high >> 12;
 
 if (status->default_nan_mode) {
 return float64_default_nan(status);
 }
 
-if ( mantissa )
+if (mantissa) {
 return make_float64(
-  ( ( (uint64_t) a.sign )<<63 )
-| LIT64( 0x7FF0 )
-| ( a.high>>12 ));
-else
-return float64_default_nan;
+  (((uint64_t) a.sign) << 63)
+| LIT64(0x7FF0)
+| (a.high >> 12));
+} else {
+return float64_default_nan(status);
+}
 }
 
 /*
@@ -843,9 +844,9 @@ static float64 propagateFloat64NaN(float64 a, float64 b, 
float_status *status)
 re

[Qemu-devel] [PATCH v9 06/10] target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSA

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Function msa_reset() is updated so that flag snan_bit_is_one is
properly set to 0.

By applying this patch, a number of incorrect MSA behaviors that
require IEEE 754-2008 compliance will be fixed. Those are behaviors
that (up to the moment of applying this patch) did not get the desired
functionality from SoftFloat library with respect to distinguishing
between quiet and signaling NaN, getting default NaN values (both
quiet and signaling), establishing if a floating point number is NaN
or not, etc.

Two examples:

* FMAX, FMIN will now correctly detect and propagate NaNs.
* FCLASS.D ans FCLASS.S will now correcty detect NaN flavors.

Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/translate_init.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index e81a831..a37d8bb 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -893,5 +893,6 @@ static void msa_reset(CPUMIPSState *env)
 /* clear float_status nan mode */
 set_default_nan_mode(0, >active_tc.msa_fp_status);
 
-set_snan_bit_is_one(1, >active_tc.msa_fp_status);
+/* set proper signanling bit meaning ("1" means "quiet") */
+set_snan_bit_is_one(0, >active_tc.msa_fp_status);
 }
-- 
1.9.1

[Qemu-devel] [PATCH v9 10/10] target-mips: Add FCR31's FS bit definition

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Add preprocessor definition of FCR31's FS bit, and update related
code for setting this bit.

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/cpu.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 7c81c41..4d2bbdf 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -112,6 +112,7 @@ struct CPUMIPSFPUContext {
 /* fcsr */
 uint32_t fcr31_rw_bitmask;
 uint32_t fcr31;
+#define FCR31_FS 24
 #define FCR31_ABS2008 19
 #define FCR31_NAN2008 18
 #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 
24)) : (1 << 23)); } while(0)
@@ -814,7 +815,7 @@ static inline void restore_rounding_mode(CPUMIPSState *env)
 
 static inline void restore_flush_mode(CPUMIPSState *env)
 {
-set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
+set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
   >active_fpu.fp_status);
 }
 
-- 
1.9.1

Re: [Qemu-devel] [PATCH v6 8/9] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

[Aleksandar Markovic]

I referred to SoftFloat library in QEMU code, and the case "Operand is smaller 
than INT_MIN" is different between SoftFloat and Mips-B, while the case 
"Operand is a NaN" is different between SoftFloat and Mips-A.

Aleksandar

From: Maciej Rozycki
Sent: Tuesday, June 07, 2016 4:39 AM
To: Aleksandar Markovic
Cc: qemu-devel@nongnu.org; peter.mayd...@linaro.org; pro...@gmail.com; 
kbast...@mail.uni-paderborn.de; mark.cave-ayl...@ilande.co.uk; ag...@suse.de; 
blauwir...@gmail.com; jcmvb...@gmail.com; Aleksandar Markovic; 
qemu-...@nongnu.org; qemu-...@nongnu.org; Petar Jovanovic; pbonz...@redhat.com; 
Miodrag Dinic; edgar.igles...@gmail.com; g...@mprc.pku.edu.cn; Leon Alrae; 
afaer...@suse.de; Aurelien Jarno; r...@twiddle.net
Subject: Re: [PATCH v6 8/9] target-mips: Add nan2008 flavor of 
<CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

On Mon, 16 May 2016, Aleksandar Markovic wrote:

> Here one can distinguish three cases:
>
> CASE MIPS-A: (FCR31.NAN2008 == 1)
>
>1. Operand is a NaN, result should be 0;
>2. Operand is larger than INT_MAX, result should be INT_MAX;
>2. Operand is smaller than INT_MIN, result should be INT_MIN.
>
> CASE MIPS-B: (FCR31.NAN2008 == 0)
>
>1. Operand is a NaN, result should be INT_MAX;
>2. Operand is larger than INT_MAX, result should be INT_MAX;
>2. Operand is smaller than INT_MIN, result should be INT_MAX.
>
> CASE SOFTFLOAT:
>
>1. Operand is a NaN, result is INT_MAX;
>2. Operand is larger than INT_MAX, result is INT_MAX;
>2. Operand is smaller than INT_MIN, result is INT_MIN.
>
> It is interesting that neither MIPS-A nor MIPS-B desired behaviors
> are in this sense identical to correspondent SoftFloat behavior.

 A bug in SoftFloat probably -- it has only been fixed quite recently to
handle all MIPS architecture's peculiarites correctly and this case must
have been missed then, making data produced not necessarily identical
between the legacy-NaN hard-float and the soft-float ABIs, even though
intent has been for it to be.

 FAOD, you refer to SoftFloat in the most recent version of GCC, do you?

  Maciej

[Qemu-devel] [PATCH v9 07/10] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Updated handling of instructions <ABS|NEG>.<S|D>. Note that legacy
(pre-abs2008) ABS and NEG instructions are arithmetic (and, therefore,
any NaN operand causes signaling invalid operation), while abs2008
ones are non-arithmetic, always and only changing the sign bit, even
for NaN-like operands. Details on these instructions are documented
in [1] p. 35 and 359.

Implementation-wise, abs2008 versions are implemented without helpers,
for simplicity and performance sake.

[1] "MIPS Architecture For Programmers Volume II-A:
The MIPS64 Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/translate.c | 26 ++
 1 file changed, 22 insertions(+), 4 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index e934884..6771254 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1434,6 +1434,7 @@ typedef struct DisasContext {
 bool vp;
 bool cmgcr;
 bool mrp;
+bool abs2008;
 } DisasContext;
 
 enum {
@@ -8879,7 +8880,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i32 fp0 = tcg_temp_new_i32();
 
 gen_load_fpr32(ctx, fp0, fs);
-gen_helper_float_abs_s(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_andi_i32(fp0, fp0, 0x7fffUL);
+} else {
+gen_helper_float_abs_s(fp0, fp0);
+}
 gen_store_fpr32(ctx, fp0, fd);
 tcg_temp_free_i32(fp0);
 }
@@ -8898,7 +8903,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i32 fp0 = tcg_temp_new_i32();
 
 gen_load_fpr32(ctx, fp0, fs);
-gen_helper_float_chs_s(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_xori_i32(fp0, fp0, 1UL << 31);
+} else {
+gen_helper_float_chs_s(fp0, fp0);
+}
 gen_store_fpr32(ctx, fp0, fd);
 tcg_temp_free_i32(fp0);
 }
@@ -9369,7 +9378,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i64 fp0 = tcg_temp_new_i64();
 
 gen_load_fpr64(ctx, fp0, fs);
-gen_helper_float_abs_d(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_andi_i64(fp0, fp0, 0x7fffULL);
+} else {
+gen_helper_float_abs_d(fp0, fp0);
+}
 gen_store_fpr64(ctx, fp0, fd);
 tcg_temp_free_i64(fp0);
 }
@@ -9390,7 +9403,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i64 fp0 = tcg_temp_new_i64();
 
 gen_load_fpr64(ctx, fp0, fs);
-gen_helper_float_chs_d(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_xori_i64(fp0, fp0, 1ULL << 63);
+} else {
+gen_helper_float_chs_d(fp0, fp0);
+}
 gen_store_fpr64(ctx, fp0, fd);
 tcg_temp_free_i64(fp0);
 }
@@ -19775,6 +19792,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct 
TranslationBlock *tb)
  (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
 ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
 ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
+ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
 restore_cpu_state(env, );
 #ifdef CONFIG_USER_ONLY
 ctx.mem_idx = MIPS_HFLAG_UM;
-- 
1.9.1

[Qemu-devel] [PATCH v9 09/10] target-mips: Implement FCR31's R/W bitmask and related functionalities

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch implements read and write access rules for Mips floating
point control and status register (FCR31). The change can be divided
into following parts:

- Add fields that will keep FCR31's R/W bitmask in procesor
  definitions and processor float_status structure.

- Add appropriate value for FCR31's R/W bitmask for each supported
  processor.

- Add function for setting snan_bit_is_one, and integrate it in
  appropriate places.

- Modify handling of CTC1 (case 31) instruction to use FCR31's R/W
  bitmask.

- Modify handling user mode executables for Mips, in relation to the
  bit EF_MIPS_NAN2008 from ELF header, that is in turn related to
  reading and writing to FCR31.

- Modify gdb behavior in relation to FCR31.

Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 linux-user/main.c| 14 ++
 target-mips/cpu.h|  8 
 target-mips/gdbstub.c|  8 +++-
 target-mips/op_helper.c  | 14 +++---
 target-mips/translate.c  |  5 ++---
 target-mips/translate_init.c | 26 ++
 6 files changed, 56 insertions(+), 19 deletions(-)

diff --git a/linux-user/main.c b/linux-user/main.c
index 5f3ec97..cc21057 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -4608,6 +4608,20 @@ int main(int argc, char **argv, char **envp)
 if (regs->cp0_epc & 1) {
 env->hflags |= MIPS_HFLAG_M16;
 }
+if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
+((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
+if ((env->active_fpu.fcr31_rw_bitmask &
+  (1 << FCR31_NAN2008)) == 0) {
+fprintf(stderr, "ELF binary's NaN mode not supported by 
CPU\n");
+exit(1);
+}
+if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
+env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
+} else {
+env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
+}
+restore_snan_bit_mode(env);
+}
 }
 #elif defined(TARGET_OPENRISC)
 {
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 6478420..7c81c41 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -110,6 +110,7 @@ struct CPUMIPSFPUContext {
 #define FCR0_PRID 8
 #define FCR0_REV 0
 /* fcsr */
+uint32_t fcr31_rw_bitmask;
 uint32_t fcr31;
 #define FCR31_ABS2008 19
 #define FCR31_NAN2008 18
@@ -817,10 +818,17 @@ static inline void restore_flush_mode(CPUMIPSState *env)
   >active_fpu.fp_status);
 }
 
+static inline void restore_snan_bit_mode(CPUMIPSState *env)
+{
+set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
+>active_fpu.fp_status);
+}
+
 static inline void restore_fp_status(CPUMIPSState *env)
 {
 restore_rounding_mode(env);
 restore_flush_mode(env);
+restore_snan_bit_mode(env);
 }
 
 static inline void restore_msa_fp_status(CPUMIPSState *env)
diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c
index b0b4a32..aacc721 100644
--- a/target-mips/gdbstub.c
+++ b/target-mips/gdbstub.c
@@ -89,11 +89,9 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t 
*mem_buf, int n)
 if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) {
 switch (n) {
 case 70:
-env->active_fpu.fcr31 = tmp & 0xFF83;
-/* set rounding mode */
-restore_rounding_mode(env);
-/* set flush-to-zero mode */
-restore_flush_mode(env);
+env->active_fpu.fcr31 = (tmp & env->active_fpu.fcr31_rw_bitmask) |
+  (env->active_fpu.fcr31 & 
~(env->active_fpu.fcr31_rw_bitmask));
+restore_fp_status(env);
 break;
 case 71:
 /* FIR is read-only.  Ignore writes.  */
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 753916d..62776a3 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2576,21 +2576,13 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, 
uint32_t fs, uint32_t rt)
  ((arg1 & 0x4) << 22);
 break;
 case 31:
-if (env->insn_flags & ISA_MIPS32R6) {
-uint32_t mask = 0xfefc;
-env->active_fpu.fcr31 = (arg1 & ~mask) |
-(env->active_fpu.fcr31 & mask);
-} else if (!(arg1 & 0x007c)) {
-env->active_fpu.fcr31 = arg1;
-}
+env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
+   (env-

[Qemu-devel] [PATCH v9 05/10] linux-user: Update preprocessor constants for Mips-specific e_flags bits

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Missing values EF_MIPS_FP64 and EF_MIPS_NAN2008 added.

Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 include/elf.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/elf.h b/include/elf.h
index 28d448b..1dc4643 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -53,6 +53,8 @@ typedef int64_t  Elf64_Sxword;
 #define EF_MIPS_OPTIONS_FIRST  0x0080
 #define EF_MIPS_32BITMODE  0x0100
 #define EF_MIPS_ABI0xf000
+#define EF_MIPS_FP64  0x0200
+#define EF_MIPS_NAN2008   0x0400
 #define EF_MIPS_ARCH  0xf000
 
 /* These constants define the different elf file types */
-- 
1.9.1

[Qemu-devel] [PATCH v9 00/10] IEEE 754-2008 support for Mips

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

v8 -> v9:
   - patches 1 and 2 slightly reorganized to separate real changes from
 cleanup changes more clearly
   - unnecessary changes removed from patches 5 and 9
   - changes related to FS bit moved to a separate patch (patch 10)
   - mail recipients for individual patches slightly adjusted

v7 -> v8:
   - fixed mail recipients
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-06/msg00896.html)

v6 -> v7:
   - preprocesor constants for FCR31 bits removed
   - cleanup items in CFC1 and CTC1 handling removed
   - initialization of snan_bit_is_one for main FP unit moved
 from patch 6 to patch 9
   - an instance of "!" corrected to "~" (logical vs. bitwise negation)
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-06/msg00886.html)

v5 -> v6:
   - code for hanlding MSA FCLASS instructions slightly simplified
   - handling of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> corrected for
 nan2008 case
   - R/W bitmask for FCR31 introduced, and related functionalities
 implemented
   - cleanup items for SoftFloat library are now in a separate patch
   - minor errors corrected
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-05/msg02513.html)

v4 -> v5:
   - platform initialization code revisited one more time;
   - handling of CLASS.<S|D> and their MSA counterparts revisited;
   - better orgranization of patches (squashing, splitting);
   - corrected handling of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>;
   - code cleanup item in genfarith() - order of cases;
   - scripts/checkpatch.pl executed and errors addressed.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg02774.html)

v3 -> v4:
   - Added code cleanup items:
   a. Capitalization of hex constants in softfloat-specialize.h;
   b. White spaces in softfloat-specialize.h;
   c. Order of Mips helpers for CVT.<L|W>.<S|D>.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01962.html)

v2 -> v3:
   - Patch series reorganized into 6 patches instead of 2.
   - Commit messages improved.
   - Except commit messages, net result of applying v3 and v2 is the same.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01870.html)

v1 -> v2:
   - Relevant CPU initialization code changes revisited for all platforms.
   - In connection with <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> and
 <ABS|NEG>.<S|D> Mips instructions handling, decision on whether
 pre-nan2008/pre-abs2008 or nan2008/abs2008 handling will apply
 moved from run-time to translate-time.
   - For Mips only, in nan2008 cases only, default NaN values fixed.
   - For Mips only, in nan2008 cases only, order in pickNaNMulAdd() fixed.
   - Code cleanup issues:
   a. Constants <floatx80|float128>_default_nan_<low|high> removed;
   b. Suffix <l|w>_<s|d> replaced with _<l|w>_<s|d> for some Mips helpers;
   c. In vicinity of changes, fixed not-beautiful code formatting.
   - Commit messages improved.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01232.html)

v1 - Initial version
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg06082.html)

Mips platform represents the most complex case among QEMU-supported
platforms in reference to certain aspects of floating-point arithmetics.
This is mostly a consequence of the fact that Mips platform, for many
reasons, evolved considerably over time related to floating-point
arithmetics standards (significantly more than other platforms).
It has been difficult for emulators like QEMU to support such variety
of configurations.

This patch series provides number of IEEE 754-2008-related features to
Mips platform. It addresses the most sensitive changes that require
modification of SoftFloat library, also used by most other platforms.

In order to make develpoment, testing, and integration easier, the patch
is split into two distinct parts:

   1. Part 1 (patches 1/10, 2/10, 3/10, 4/10, 5/10) that does not change any
  calculation or behavior on any platform (and, for that matter, even on
  Mips platform). Its sole purpose is to address platform independant
  issues in a non-invasive manner, and to make Part 2 possible.

   2. Part 2 (patches 6/10, 7/10, 8/10, 9/10, 10/10) that sets some Mips
  processors to use provisions from Part 1, and additionally implements
  number of IEEE 754-2008-related features for Mips, while, at the same
  time, mainly dealing with files located in directory target-mips only.

This patch series is based on the original set of patches proposed by Maciej W.
Rozycki: http://lists.nongnu.org/archive/html/qemu-devel/2014-12/msg00968.html

Aleksandar Markovic (10):
  softfloat: Implement run-time-configurable meaning of signaling NaN bit
  so

Re: [Qemu-devel] [PATCH v6 8/9] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

[Aleksandar Markovic]

The changes that make QEMU behavior the same as hardware behavior (in relation 
to CEIL, CVT, FLOOR, ROUND, TRUNC Mips instructions) are already contained in 
this patch.

I just mentioned Mips-A / Mips-B / SoftFloat differences as an 
explanation/observation related to the change in this patch.

Aleksandar

From: Maciej Rozycki
Sent: Friday, June 10, 2016 3:35 AM
To: Aleksandar Markovic
Cc: Aleksandar Markovic; qemu-devel@nongnu.org; peter.mayd...@linaro.org; 
pro...@gmail.com; kbast...@mail.uni-paderborn.de; 
mark.cave-ayl...@ilande.co.uk; ag...@suse.de; blauwir...@gmail.com; 
jcmvb...@gmail.com; qemu-...@nongnu.org; qemu-...@nongnu.org; Petar Jovanovic; 
pbonz...@redhat.com; Miodrag Dinic; edgar.igles...@gmail.com; 
g...@mprc.pku.edu.cn; Leon Alrae; afaer...@suse.de; Aurelien Jarno; 
r...@twiddle.net
Subject: RE: [PATCH v6 8/9] target-mips: Add nan2008 flavor of 
<CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

On Fri, 10 Jun 2016, Aleksandar Markovic wrote:

> I referred to SoftFloat library in QEMU code, and the case "Operand is
> smaller than INT_MIN" is different between SoftFloat and Mips-B, while
> the case "Operand is a NaN" is different between SoftFloat and Mips-A.

 Ah, but then you just can and indeed need to fix it to match hardware.
I had it done properly with the original patches I believe.

  Maciej

[Qemu-devel] [PATCH v8 7/9] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Updated handling of instructions <ABS|NEG>.<S|D>. Note that legacy
(pre-abs2008) ABS and NEG instructions are arithmetic (and, therefore,
any NaN operand causes signaling invalid operation), while abs2008
ones are non-arithmetic, always and only changing the sign bit, even
for NaN-like operands. Details on these instructions are documented
in [1] p. 35 and 359.

Implementation-wise, abs2008 versions are implemented without helpers,
for simplicity and performance sake.

[1] "MIPS Architecture For Programmers Volume II-A:
The MIPS64 Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/translate.c | 26 ++
 1 file changed, 22 insertions(+), 4 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index e934884..6771254 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1434,6 +1434,7 @@ typedef struct DisasContext {
 bool vp;
 bool cmgcr;
 bool mrp;
+bool abs2008;
 } DisasContext;
 
 enum {
@@ -8879,7 +8880,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i32 fp0 = tcg_temp_new_i32();
 
 gen_load_fpr32(ctx, fp0, fs);
-gen_helper_float_abs_s(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_andi_i32(fp0, fp0, 0x7fffUL);
+} else {
+gen_helper_float_abs_s(fp0, fp0);
+}
 gen_store_fpr32(ctx, fp0, fd);
 tcg_temp_free_i32(fp0);
 }
@@ -8898,7 +8903,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i32 fp0 = tcg_temp_new_i32();
 
 gen_load_fpr32(ctx, fp0, fs);
-gen_helper_float_chs_s(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_xori_i32(fp0, fp0, 1UL << 31);
+} else {
+gen_helper_float_chs_s(fp0, fp0);
+}
 gen_store_fpr32(ctx, fp0, fd);
 tcg_temp_free_i32(fp0);
 }
@@ -9369,7 +9378,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i64 fp0 = tcg_temp_new_i64();
 
 gen_load_fpr64(ctx, fp0, fs);
-gen_helper_float_abs_d(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_andi_i64(fp0, fp0, 0x7fffULL);
+} else {
+gen_helper_float_abs_d(fp0, fp0);
+}
 gen_store_fpr64(ctx, fp0, fd);
 tcg_temp_free_i64(fp0);
 }
@@ -9390,7 +9403,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i64 fp0 = tcg_temp_new_i64();
 
 gen_load_fpr64(ctx, fp0, fs);
-gen_helper_float_chs_d(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_xori_i64(fp0, fp0, 1ULL << 63);
+} else {
+gen_helper_float_chs_d(fp0, fp0);
+}
 gen_store_fpr64(ctx, fp0, fd);
 tcg_temp_free_i64(fp0);
 }
@@ -19775,6 +19792,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct 
TranslationBlock *tb)
  (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
 ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
 ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
+ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
 restore_cpu_state(env, );
 #ifdef CONFIG_USER_ONLY
 ctx.mem_idx = MIPS_HFLAG_UM;
-- 
1.9.1

[Qemu-devel] [PATCH v8 6/9] target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSA

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Function msa_reset() is updated so that flag snan_bit_is_one is
properly set to 0.

By applying this patch, a number of incorrect MSA behaviors that
require IEEE 754-2008 compliance will be fixed. Those are behaviors
that (up to the moment of applying this patch) did not get the desired
functionality from SoftFloat library with respect to distinguishing
between quiet and signaling NaN, getting default NaN values (both
quiet and signaling), establishing if a floating point number is NaN
or not, etc.

Two examples:

* FMAX, FMIN will now correctly detect and propagate NaNs.
* FCLASS.D ans FCLASS.S will now correcty detect NaN flavors.

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/translate_init.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index e81a831..a37d8bb 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -893,5 +893,6 @@ static void msa_reset(CPUMIPSState *env)
 /* clear float_status nan mode */
 set_default_nan_mode(0, >active_tc.msa_fp_status);
 
-set_snan_bit_is_one(1, >active_tc.msa_fp_status);
+/* set proper signanling bit meaning ("1" means "quiet") */
+set_snan_bit_is_one(0, >active_tc.msa_fp_status);
 }
-- 
1.9.1

[Qemu-devel] [PATCH v9 08/10] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

New set of helpers for handling nan2008-syle versions of instructions
<CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>, for Mips R6.

All involved instructions have float operand and integer result. Their
core functionality is implemented via invocations of appropriate SoftFloat
functions. The problematic cases are when the operand is a NaN, and also
when the operand (float) is out of the range of the result.

Here one can distinguish three cases:

CASE MIPS-A: (FCR31.NAN2008 == 1)

   1. Operand is a NaN, result should be 0;
   2. Operand is larger than INT_MAX, result should be INT_MAX;
   3. Operand is smaller than INT_MIN, result should be INT_MIN.

CASE MIPS-B: (FCR31.NAN2008 == 0)

   1. Operand is a NaN, result should be INT_MAX;
   2. Operand is larger than INT_MAX, result should be INT_MAX;
   3. Operand is smaller than INT_MIN, result should be INT_MAX.

CASE SOFTFLOAT:

   1. Operand is a NaN, result is INT_MAX;
   2. Operand is larger than INT_MAX, result is INT_MAX;
   3. Operand is smaller than INT_MIN, result is INT_MIN.

It is interesting that neither MIPS-A nor MIPS-B desired behaviors
are in this sense identical to correspondent SoftFloat behavior.

Current implementation of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
implements case MIPS-B. This patch relates to case MIPS-A. For case
MIPS-A, only return value for NaN-operands should be corrected after
appropriate SoftFloat library function is called.

Related MSA instructions FTRUNC_S and FTINT_S already handle well
all cases, in the fashion similar to the code from this patch.

Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/helper.h|  18 +--
 target-mips/op_helper.c | 369 +---
 target-mips/translate.c | 122 +---
 3 files changed, 461 insertions(+), 48 deletions(-)

diff --git a/target-mips/helper.h b/target-mips/helper.h
index 8546177..666936c 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -207,8 +207,6 @@ DEF_HELPER_4(ctc1, void, env, tl, i32, i32)
 DEF_HELPER_2(float_cvtd_s, i64, env, i32)
 DEF_HELPER_2(float_cvtd_w, i64, env, i32)
 DEF_HELPER_2(float_cvtd_l, i64, env, i64)
-DEF_HELPER_2(float_cvtl_d, i64, env, i64)
-DEF_HELPER_2(float_cvtl_s, i64, env, i32)
 DEF_HELPER_2(float_cvtps_pw, i64, env, i64)
 DEF_HELPER_2(float_cvtpw_ps, i64, env, i64)
 DEF_HELPER_2(float_cvts_d, i32, env, i64)
@@ -216,8 +214,6 @@ DEF_HELPER_2(float_cvts_w, i32, env, i32)
 DEF_HELPER_2(float_cvts_l, i32, env, i64)
 DEF_HELPER_2(float_cvts_pl, i32, env, i32)
 DEF_HELPER_2(float_cvts_pu, i32, env, i32)
-DEF_HELPER_2(float_cvtw_s, i32, env, i32)
-DEF_HELPER_2(float_cvtw_d, i32, env, i64)
 
 DEF_HELPER_3(float_addr_ps, i64, env, i64, i64)
 DEF_HELPER_3(float_mulr_ps, i64, env, i64, i64)
@@ -242,14 +238,20 @@ FOP_PROTO(mina)
 #undef FOP_PROTO
 
 #define FOP_PROTO(op)\
-DEF_HELPER_2(float_ ## op ## l_s, i64, env, i32) \
-DEF_HELPER_2(float_ ## op ## l_d, i64, env, i64) \
-DEF_HELPER_2(float_ ## op ## w_s, i32, env, i32) \
-DEF_HELPER_2(float_ ## op ## w_d, i32, env, i64)
+DEF_HELPER_2(float_ ## op ## _l_s, i64, env, i32) \
+DEF_HELPER_2(float_ ## op ## _l_d, i64, env, i64) \
+DEF_HELPER_2(float_ ## op ## _w_s, i32, env, i32) \
+DEF_HELPER_2(float_ ## op ## _w_d, i32, env, i64)
+FOP_PROTO(cvt)
 FOP_PROTO(round)
 FOP_PROTO(trunc)
 FOP_PROTO(ceil)
 FOP_PROTO(floor)
+FOP_PROTO(cvt_2008)
+FOP_PROTO(round_2008)
+FOP_PROTO(trunc_2008)
+FOP_PROTO(ceil_2008)
+FOP_PROTO(floor_2008)
 #undef FOP_PROTO
 
 #define FOP_PROTO(op)\
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 5b83b61..753916d 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2448,6 +2448,7 @@ void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
 
 #define FLOAT_TWO32 make_float32(1 << 30)
 #define FLOAT_TWO64 make_float64(1ULL << 62)
+
 #define FP_TO_INT32_OVERFLOW 0x7fff
 #define FP_TO_INT64_OVERFLOW 0x7fffULL
 
@@ -2683,7 +2684,7 @@ uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t 
dt0)
 return fdt2;
 }
 
-uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
+uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
 {
 uint64_t dt2;
 
@@ -2696,7 +2697,7 @@ uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t 
fdt0)
 return dt2;
 }
 
-uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
+uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
 {
 uint64_t dt2;
 
@@ -2791,7 +2792,7 @@ uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t 
wth0)
 return wt2;
 }
 
-uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
+uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
 {
 uint32_t wt2;
 
@@ -2804,7 +2805,7 @@ uint32_t help

[Qemu-devel] [PATCH v9 01/10] softfloat: Implement run-time-configurable meaning of signaling NaN bit

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch modifies SoftFloat library so that it can be configured in
run-time in relation to the meaning of signaling NaN bit, while, at the
same time, strictly preserving its behavior on all existing platforms.

Background:

In floating-point calculations, there is a need for denoting undefined or
unrepresentable values. This is achieved by defining certain floating-point
numerical values to be NaNs (which stands for "not a number"). For additional
reasons, virtually all modern floating-point unit implementations use two
kinds of NaNs: quiet and signaling. The binary representations of these two
kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally,
the first bit of mantissa).

Up to 2008, standards for floating-point did not specify all details about
binary representation of NaNs. More specifically, the meaning of the bit
that is used for distinguishing between signaling and quiet NaNs was not
strictly prescribed. (IEEE 754-2008 was the first floating-point standard
that defined that meaning clearly, see [1], p. 35) As a result, different
platforms took different approaches, and that presented considerable
challenge for multi-platform emulators like QEMU.

Mips platform represents the most complex case among QEMU-supported
platforms regarding signaling NaN bit. Up to the Release 6 of Mips
architecture, "1" in signaling NaN bit denoted signaling NaN, which is
opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
that, Mips architecture for SIMD (also known as MSA, or vector instructions)
also specifies signaling bit in accordance to IEEE standard. MSA unit can be
implemented with both pre-Release 6 and Release 6 main processor units.

QEMU uses SoftFloat library to implement various floating-point-related
instructions on all platforms. The current QEMU implementation allows for
defining meaning of signaling NaN bit during build time, and is implemented
via preprocessor macro called SNAN_BIT_IS_ONE.

On the other hand, the change in this patch enables SoftFloat library to be
configured in run-time. This configuration is meant to occur during CPU
initialization, at the moment when it is definitely known what desired
behavior for particular CPU (or any additional FPUs) is.

The change is implemented so that it is consistent with existing
implementation of similar cases. This means that structure float_status is
used for passing the information about desired signaling NaN bit on each
invocation of SoftFloat functions. The additional field in float_status is
called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.

IMPORTANT:

This change is not meant to create any change in emulator behavior or
functionality on any platform. It just provides the means for SoftFloat
library to be used in a more flexible way - in other words, it will just
prepare SoftFloat library for usage related to Mips platform and its
specifics regarding signaling bit meaning, which is done in some of
subsequent patches from this series.

Further break down of changes:

  1) Added field snan_bit_is_one to the structure float_status, and
 correspondent setter function set_snan_bit_is_one().

  2) Constants <float16|float32|float64|floatx80|float128>_default_nan
 (used both internally and externally) converted to functions
 <float16|float32|float64|floatx80|float128>_default_nan(float_status*).
 This is necessary since they are dependent on signaling bit meaning.
 At the same time, for the sake of code cleanup and simplicity, constants
 <floatx80|float128>_default_nan_<low|high> (used only internally within
 SoftFloat library) are removed, as not needed.

  3) Added a float_status* argument to SoftFloat library functions
 XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
 XXX_maybe_silence_nan(XXX a_). This argument must be present in
 order to enable correct invocation of new version of functions
 XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128>
 here)

  4) Updated code for all platforms to reflect changes in SoftFloat library.
 This change is twofolds: it includes modifications of SoftFloat library
 functions invocations, and an addition of invocation of function
 set_snan_bit_is_one() during CPU initialization, with arguments that
 are appropriate for each particular platform. It was established that
 all platforms zero their main CPU data structures, so snan_bit_is_one(0)
 in appropriate places is not added, as it is not needed.

[1] "IEEE Standard for Floating-Point Arithmetic",
IEEE Computer Society, August 29, 2008.

Tested-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> (TriCore part)
Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Sign

[Qemu-devel] [PATCH v9 03/10] softfloat: For Mips only, correct default NaN values

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Only for Mips platform, and only for cases when snan_bit_is_one is 0,
correct default NaN values (in their 16-, 32-, and 64-bit flavors).

For more info, see [1], page 84, Table 6.3 "Value Supplied When a New
Quiet NaN Is Created", and [2], page 52, Table 3.7 "Default NaN
Encodings".

[1] "MIPS Architecture For Programmers Volume II-A:
The MIPS64 Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

[2] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32 SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016

Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 fpu/softfloat-specialize.h | 12 
 1 file changed, 12 insertions(+)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 981d665..a1bcb46 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -97,7 +97,11 @@ float16 float16_default_nan(float_status *status)
 if (status->snan_bit_is_one) {
 return const_float16(0x7DFF);
 } else {
+#if defined(TARGET_MIPS)
+return const_float16(0x7E00);
+#else
 return const_float16(0xFE00);
+#endif
 }
 #endif
 }
@@ -116,7 +120,11 @@ float32 float32_default_nan(float_status *status)
 if (status->snan_bit_is_one) {
 return const_float32(0x7FBF);
 } else {
+#if defined(TARGET_MIPS)
+return const_float32(0x7FC0);
+#else
 return const_float32(0xFFC0);
+#endif
 }
 #endif
 }
@@ -135,7 +143,11 @@ float64 float64_default_nan(float_status *status)
 if (status->snan_bit_is_one) {
 return const_float64(LIT64(0x7FF7));
 } else {
+#if defined(TARGET_MIPS)
+return const_float64(LIT64(0x7FF8));
+#else
 return const_float64(LIT64(0xFFF8));
+#endif
 }
 #endif
 }
-- 
1.9.1

[Qemu-devel] [PATCH v9 04/10] softfloat: For Mips only, correct order in pickNaNMulAdd()

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Only for Mips platform, and only for cases when snan_bit_is_one is 0,
correct the order of argument comparisons in pickNaNMulAdd().

For more info, see [1], page 53, section "3.5.3 NaN Propagation".

[1] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32 SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016

Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 fpu/softfloat-specialize.h | 41 +
 1 file changed, 29 insertions(+), 12 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index a1bcb46..4063561 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -571,19 +571,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag 
bIsQNaN, flag bIsSNaN,
 return 3;
 }
 
-/* Prefer sNaN over qNaN, in the a, b, c order. */
-if (aIsSNaN) {
-return 0;
-} else if (bIsSNaN) {
-return 1;
-} else if (cIsSNaN) {
-return 2;
-} else if (aIsQNaN) {
-return 0;
-} else if (bIsQNaN) {
-return 1;
+if (status->snan_bit_is_one) {
+/* Prefer sNaN over qNaN, in the c, a, b order. */
+if (cIsSNaN) {
+return 2;
+} else if (aIsSNaN) {
+return 0;
+} else if (bIsSNaN) {
+return 1;
+} else if (cIsQNaN) {
+return 2;
+} else if (aIsQNaN) {
+return 0;
+} else {
+return 1;
+}
 } else {
-return 2;
+/* Prefer sNaN over qNaN, in the a, b, c order. */
+if (aIsSNaN) {
+return 0;
+} else if (bIsSNaN) {
+return 1;
+} else if (cIsSNaN) {
+return 2;
+} else if (aIsQNaN) {
+return 0;
+} else if (bIsQNaN) {
+return 1;
+} else {
+return 2;
+}
 }
 }
 #elif defined(TARGET_PPC)
-- 
1.9.1

Re: [Qemu-devel] [PATCH v9 00/10] IEEE 754-2008 support for Mips

[Aleksandar Markovic]

ping


From: Aleksandar Markovic [aleksandar.marko...@rt-rk.com]
Sent: Friday, June 10, 2016 2:57 AM
To: qemu-devel@nongnu.org; qemu-...@nongnu.org; qemu-...@nongnu.org; Maciej 
Rozycki; pro...@gmail.com; kbast...@mail.uni-paderborn.de; 
mark.cave-ayl...@ilande.co.uk; ag...@suse.de; blauwir...@gmail.com; 
jcmvb...@gmail.com; pbonz...@redhat.com; edgar.igles...@gmail.com; 
g...@mprc.pku.edu.cn; r...@twiddle.net; peter.mayd...@linaro.org; 
aurel...@aurel32.net; Leon Alrae; Petar Jovanovic; Miodrag Dinic; Aleksandar 
Markovic
Subject: [PATCH v9 00/10] IEEE 754-2008 support for Mips

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

v8 -> v9:
   - patches 1 and 2 slightly reorganized to separate real changes from
 cleanup changes more clearly
   - unnecessary changes removed from patches 5 and 9
   - changes related to FS bit moved to a separate patch (patch 10)
   - mail recipients for individual patches slightly adjusted

v7 -> v8:
   - fixed mail recipients
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-06/msg00896.html)

v6 -> v7:
   - preprocesor constants for FCR31 bits removed
   - cleanup items in CFC1 and CTC1 handling removed
   - initialization of snan_bit_is_one for main FP unit moved
 from patch 6 to patch 9
   - an instance of "!" corrected to "~" (logical vs. bitwise negation)
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-06/msg00886.html)

v5 -> v6:
   - code for hanlding MSA FCLASS instructions slightly simplified
   - handling of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> corrected for
 nan2008 case
   - R/W bitmask for FCR31 introduced, and related functionalities
 implemented
   - cleanup items for SoftFloat library are now in a separate patch
   - minor errors corrected
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-05/msg02513.html)

v4 -> v5:
   - platform initialization code revisited one more time;
   - handling of CLASS.<S|D> and their MSA counterparts revisited;
   - better orgranization of patches (squashing, splitting);
   - corrected handling of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>;
   - code cleanup item in genfarith() - order of cases;
   - scripts/checkpatch.pl executed and errors addressed.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg02774.html)

v3 -> v4:
   - Added code cleanup items:
   a. Capitalization of hex constants in softfloat-specialize.h;
   b. White spaces in softfloat-specialize.h;
   c. Order of Mips helpers for CVT.<L|W>.<S|D>.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01962.html)

v2 -> v3:
   - Patch series reorganized into 6 patches instead of 2.
   - Commit messages improved.
   - Except commit messages, net result of applying v3 and v2 is the same.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01870.html)

v1 -> v2:
   - Relevant CPU initialization code changes revisited for all platforms.
   - In connection with <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> and
 <ABS|NEG>.<S|D> Mips instructions handling, decision on whether
 pre-nan2008/pre-abs2008 or nan2008/abs2008 handling will apply
 moved from run-time to translate-time.
   - For Mips only, in nan2008 cases only, default NaN values fixed.
   - For Mips only, in nan2008 cases only, order in pickNaNMulAdd() fixed.
   - Code cleanup issues:
   a. Constants <floatx80|float128>_default_nan_<low|high> removed;
   b. Suffix <l|w>_<s|d> replaced with _<l|w>_<s|d> for some Mips helpers;
   c. In vicinity of changes, fixed not-beautiful code formatting.
   - Commit messages improved.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01232.html)

v1 - Initial version
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg06082.html)

Mips platform represents the most complex case among QEMU-supported
platforms in reference to certain aspects of floating-point arithmetics.
This is mostly a consequence of the fact that Mips platform, for many
reasons, evolved considerably over time related to floating-point
arithmetics standards (significantly more than other platforms).
It has been difficult for emulators like QEMU to support such variety
of configurations.

This patch series provides number of IEEE 754-2008-related features to
Mips platform. It addresses the most sensitive changes that require
modification of SoftFloat library, also used by most other platforms.

In order to make develpoment, testing, and integration easier, the patch
is split into two distinct parts:

   1. Part 1 (patches 1/10, 2/10, 3/10, 4/10, 5/10) that does not change any
  calculation or behavior on any platform (and, for that matter, even on
  Mips platform). Its sole purpose is to address platform independant
  issue

Re: [Qemu-devel] [PATCH v6 8/9] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

[Aleksandar Markovic]

This patch is about NaN-2008 flavor of Mips instructions CEIL, CVT, FLOOR, 
ROUND, TRUNC only (its title is "Add nan2008 flavor...").

Legacy-NaN flavors of the same Mips instructions already operate correctly, and 
there is nothing to be fixed.

The commit message is not description of another bug, it explains the context 
of the change, and the content of added code segments.


From: Maciej Rozycki
Sent: Tuesday, June 14, 2016 8:30 AM
To: Leon Alrae
Cc: Aleksandar Markovic; Aleksandar Markovic; qemu-devel@nongnu.org; 
peter.mayd...@linaro.org; pro...@gmail.com; kbast...@mail.uni-paderborn.de; 
mark.cave-ayl...@ilande.co.uk; ag...@suse.de; blauwir...@gmail.com; 
jcmvb...@gmail.com; qemu-...@nongnu.org; qemu-...@nongnu.org; Petar Jovanovic; 
pbonz...@redhat.com; Miodrag Dinic; edgar.igles...@gmail.com; 
g...@mprc.pku.edu.cn; afaer...@suse.de; Aurelien Jarno; r...@twiddle.net
Subject: Re: [PATCH v6 8/9] target-mips: Add nan2008 flavor of 
<CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

On Tue, 14 Jun 2016, Leon Alrae wrote:

> > 1. A bug fix for SoftFloat legacy-NaN (original) MIPS support, which has
> >been there probably since forever (i.e. since the MIPS target was added
> >to QEMU).
>
> I've just done another round of review and as far as I can tell these
> patches don't modify the legacy-NaN MIPS behaviour. I believe Aleksandar
> was referring to new functionality (i.e. 2008 NaN) only.

 Well, if there's a bug, then it needs to be fixed rather than documented.

  Maciej

Re: [Qemu-devel] [PATCH 2/2] target-mips: Implement IEEE 754-2008 functionality for R6 and MSA instructions

[Aleksandar Markovic]

I really appreciate your guidance and help. I will respond shortly with a 
proposal that will address all issues that you brought up. Thanks again for 
your support and time.

Aleksandar

From: qemu-devel-bounces+aleksandar.markovic=imgtec@nongnu.org 
[qemu-devel-bounces+aleksandar.markovic=imgtec@nongnu.org] on behalf of 
Richard Henderson [r...@twiddle.net]
Sent: Monday, March 28, 2016 2:49 PM
To: Aleksandar Markovic; qemu-devel@nongnu.org
Cc: peter.mayd...@linaro.org; ehabk...@redhat.com; 
kbast...@mail.uni-paderborn.de; mark.cave-ayl...@ilande.co.uk; ag...@suse.de; 
Petar Jovanovic; blauwir...@gmail.com; jcmvb...@gmail.com; Miodrag Dinic; 
qemu-...@nongnu.org; qemu-...@nongnu.org; edgar.igles...@gmail.com; 
pbonz...@redhat.com; g...@mprc.pku.edu.cn; Leon Alrae; afaer...@suse.de; 
aurel...@aurel32.net; pro...@gmail.com
Subject: Re: [Qemu-devel] [PATCH 2/2] target-mips: Implement IEEE 754-2008 
functionality for R6 and MSA instructions

On 03/25/2016 05:50 AM, Aleksandar Markovic wrote:
> @@ -2621,9 +2621,23 @@ uint64_t helper_float_cvtl_d(CPUMIPSState *env, 
> uint64_t fdt0)
>   uint64_t dt2;
>
>   dt2 = float64_to_int64(fdt0, >active_fpu.fp_status);
> -if (get_float_exception_flags(>active_fpu.fp_status)
> -& (float_flag_invalid | float_flag_overflow)) {
> -dt2 = FP_TO_INT64_OVERFLOW;
> +if (env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) {
> +if (get_float_exception_flags(>active_fpu.fp_status)
> +& (float_flag_invalid | float_flag_overflow)) {
> +if (float64_is_any_nan(fdt0)) {
> +dt2 = 0;
> +} else {
> +if (float64_is_neg(fdt0))
> +dt2 = INT64_MIN;
> +else
> +dt2 = INT64_MAX;
> +}
> +}
> +} else {
> +if (get_float_exception_flags(>active_fpu.fp_status)
> +& (float_flag_invalid | float_flag_overflow)) {
> +dt2 = FP_TO_INT64_OVERFLOW;
> +}

Better to swap the tests here, so that you test the exception flags first (and
once).  That is the exceptional condition, the one that will be true least
often.  After that, FCR31_NAN2008 will be tested only when needed.

But also, this pattern is replicated so many times you'd do well to pull this
sequence out to helper functions (one for s, one for d).

> +uint64_t helper_float_abs_d(CPUMIPSState *env, uint64_t fdt0)
> +{
> +uint64_t fdt1;
> +
> +if (env->active_fpu.fcr31 & (1 << FCR31_ABS2008)) {
> +fdt1 = float64_abs(fdt0);
> +} else {
> +if (float64_is_neg(fdt0)) {
> +fdt1 = float64_sub(0, fdt0, >active_fpu.fp_status);
> +} else {
> +fdt1 = float64_add(0, fdt0, >active_fpu.fp_status);
> +}
> +update_fcr31(env, GETPC());

Here you're better off using two separate helper functions, and chose the
correct one during translation.  Indeed, since the 2008 version is a simple
bit-flip, you needn't actually have a helper; just expand the sequence inline.


r~

Re: [Qemu-devel] [PATCH 1/2] softfloat: Enable run-time-configurable meaning of signaling NaN bit

[Aleksandar Markovic]

Thank you very much. I will let you know if any change regarding tricore 
appears in later versions of this patch.

From: qemu-devel-bounces+aleksandar.markovic=imgtec@nongnu.org 
[qemu-devel-bounces+aleksandar.markovic=imgtec@nongnu.org] on behalf of 
Bastian Koppelmann [kbast...@mail.uni-paderborn.de]
Sent: Tuesday, March 29, 2016 5:50 AM
To: Aleksandar Markovic; qemu-devel@nongnu.org
Cc: peter.mayd...@linaro.org; ehabk...@redhat.com; pro...@gmail.com; 
mark.cave-ayl...@ilande.co.uk; ag...@suse.de; Petar Jovanovic; 
blauwir...@gmail.com; jcmvb...@gmail.com; Miodrag Dinic; qemu-...@nongnu.org; 
qemu-...@nongnu.org; edgar.igles...@gmail.com; pbonz...@redhat.com; 
g...@mprc.pku.edu.cn; Leon Alrae; afaer...@suse.de; aurel...@aurel32.net; 
r...@twiddle.net
Subject: Re: [Qemu-devel] [PATCH 1/2] softfloat: Enable run-time-configurable 
meaning of signaling NaN bit

On 03/25/2016 01:50 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
>
> This patch enables SoftFloat library to be configured at run-time in
> relation to the meaning of signaling NaN bit.
>
> Background:
>
> In floating-point calculations, there is a need for denoting undefined or
> unrepresentable values. This is achieved by defining certain floating-point
> numerical values to be NaNs (which stands for "not a number"). For additional
> reasons, virtually all modern floating-point unit implementations use two
> kinds of NaNs: quiet and signaling. The binary representations of these two
> kinds of NaNs, as a rule, differ only in one bit (it is traditionally,
> the first bit of mantissa).
>
> Up to 2008, standards for floating-point did not specify all details about
> binary representation of NaNs. More specifically, the meaning of the bit
> that is used for distinguishing between signaling and quiet NaNs was not
> strictly prescribed. (IEEE 754-2008 was the first floating-point standard
> that defined that meaning clearly, see [1], p. 35) As a result, different
> platforms took different approaches, and this presented certain challenge
> in emulators like QEMU.
>
> Mips architecture represent the most complex case among QEMU-supported
> architectures regarding signaling NaN bit. Up to Release 6 of Mips
> architecture, "1" in signaling NaN bit denoted signaling NaN, which is
> opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
> adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
> that, Mips architecture for SIMD (also known as MSA, or vector instructions)
> also specifies signaling bit in accordance to IEEE standard. MSA unit can be
> implemented with both pre-Release 6 and Release 6 main processor units.
>
> QEMU uses SoftFloat library to implement various floating-point-related
> instructions on all platforms. The current implementation allows for defining
> meaning of signaling NaN bit during build time, and is implemented via
> preprocessor macro called SNAN_BIT_IS_ONE.
>
> The change in this patch enables SoftFloat library to be configured in
> run-time. This configuration is meant to occur during CPU initialization,
> when it is definitely known what desired behavior for particular CPU
> (or any additional FPUs) is.
>
> The change is implemented so that it is consistent with existing
> implementation of similar cases. This means that structure float_status is
> used for passing the information about desired signaling NaN bit during each
> invocation of SoftFloat functions. The additional field in float_status is
> called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.
>
> Further break down of changes:
>
>   (for the sake of brevity, a placeholder XXX is used below and it might
>   mean float16, float32, float64, floatx80, or float128)
>
>   1) Added field snan_bit_is_one to the structure float_status,
>  and the correspondent setter function set_snan_bit_is_one().
>
>   2) SoftFloat library constants XXX_default_nan converted to functions
>  XXX_default_nan(float_status*). This is necessary since they are
>  dependant on signaling bit meaning.
>
>   3) Added a float_status* argument to SoftFloat library functions
>  XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
>  XXX_maybe_silence_nan(XXX a_).
>
>   4) Updated code in all architectures to reflect changes in SoftFloat
>  library. This change is twofolds: it includes modification of SoftFloat
>  library functions invocations, and addition of invocations of function
>  set_snan_bit_is_one() during CPU initialization, with arguments that
>  are appropriate for each architecture.
>
> IMPORTANT:
>
> This change is not meant to create any change in emulato

Re: [Qemu-devel] [PATCH 2/2] target-mips: Implement IEEE 754-2008 functionality for R6 and MSA instructions

[Aleksandar Markovic]

Hi, Richard, what would you think about this approach:

Functionality of <ABS|NEG>.<S|D> and <CVT|FLOOR|CEIL|TRUNC|ROUND>.<L|W>.<S|D>
instructions is dependent on flags ABS2008 and NAN2008 in FCR31. There are
MIPS architectures (for example mips32r5) that allow implementations
with different values of these flags. So, in order to detect the desired
behavior in translate-time, insn_flags field can't be used - and, therefore,
it makes sense to add two new members to the MIPS's DisasContext:

typedef struct DisasContext {
. . .
bool nan2008;
bool abs2008;
} DisasContext;

Their initialization could be in gen_intermediate_code_internal():

ctx.nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;

Now, ABS.D (and all <ABS|NEG>.<S|D>) handling might look like this:

case OPC_ABS_D:
check_cp1_registers(ctx, fs | fd);
{
TCGv_i64 fp0 = tcg_temp_new_i64();

gen_load_fpr64(ctx, fp0, fs);
if (ctx->abs2008) {
tcg_gen_andi_i64(fp0, fp0, 0x7fffULL);
} else {
gen_helper_float_abs_d(fp0, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
opn = "abs.d";
break;

Here, 2008-style ABS.D is implemented inline, without a helper, and
gen_helper_float_abs_d() is an old pre-2008 helper that would be intact
(the same as it is currently) with this change.

On the other hand, CVT.L.D (and all <CVT|FLOOR|CEIL|TRUNC|ROUND>.<L|W>.<S|D>)
handling would take this form:

case OPC_CVT_L_D:
check_cp1_64bitmode(ctx);
{
TCGv_i64 fp0 = tcg_temp_new_i64();

gen_load_fpr64(ctx, fp0, fs);
if (ctx->nan2008) {
gen_helper_float_cvt_2008_l_d(fp0, cpu_env, fp0);
} else {
gen_helper_float_cvt_l_d(fp0, cpu_env, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
opn = "cvt.l.d";
break;

Function helper_float_cvt_2008_l_d() is a new, only-2008-style helper for
CVT.L.D and would look like this:

uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t dt2;

dt2 = float64_to_int64(fdt0, >active_fpu.fp_status);
if (get_float_exception_flags(>active_fpu.fp_status)
& (float_flag_invalid | float_flag_overflow)) {
dt2 = DBL_TO_INT64_OVERFLOW(fdt0)
}
update_fcr31(env, GETPC());
return dt2;
}

(macro DBL_TO_INT64_OVERFLOW(x) would be defined this way:

#define DBL_TO_INT64_OVERFLOW(x) \
float64_is_any_nan(x) ? 0 : (float64_is_neg(x) ? INT64_MIN : INT64_MAX);

to avoid awkward repeating "if" statements in multiple headers)

gen_helper_float_cvt_l_d() and all old style helpers for instructions
<CVT|FLOOR|CEIL|TRUNC|ROUND>.<L|W>.<S|D> would remain the same.

Please let me know about your opinion. I greatly appreciate your kind
consideration of this matter. I am looking forward to hearing from you.

Yours,
Aleksandar

From: qemu-devel-bounces+aleksandar.markovic=imgtec@nongnu.org 
[qemu-devel-bounces+aleksandar.markovic=imgtec@nongnu.org] on behalf of 
Richard Henderson [r...@twiddle.net]
Sent: Monday, March 28, 2016 2:49 PM
To: Aleksandar Markovic; qemu-devel@nongnu.org
Cc: peter.mayd...@linaro.org; ehabk...@redhat.com; 
kbast...@mail.uni-paderborn.de; mark.cave-ayl...@ilande.co.uk; ag...@suse.de; 
Petar Jovanovic; blauwir...@gmail.com; jcmvb...@gmail.com; Miodrag Dinic; 
qemu-...@nongnu.org; qemu-...@nongnu.org; edgar.igles...@gmail.com; 
pbonz...@redhat.com; g...@mprc.pku.edu.cn; Leon Alrae; afaer...@suse.de; 
aurel...@aurel32.net; pro...@gmail.com
Subject: Re: [Qemu-devel] [PATCH 2/2] target-mips: Implement IEEE 754-2008 
functionality for R6 and MSA instructions

On 03/25/2016 05:50 AM, Aleksandar Markovic wrote:
> @@ -2621,9 +2621,23 @@ uint64_t helper_float_cvtl_d(CPUMIPSState *env, 
> uint64_t fdt0)
>   uint64_t dt2;
>
>   dt2 = float64_to_int64(fdt0, >active_fpu.fp_status);
> -if (get_float_exception_flags(>active_fpu.fp_status)
> -& (float_flag_invalid | float_flag_overflow)) {
> -dt2 = FP_TO_INT64_OVERFLOW;
> +if (env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) {
> +if (get_float_exception_flags(>active_fpu.fp_status)
> +& (float_flag_invalid | float_flag_overflow)) {
> +if (float64_is_any_nan(fdt0)) {
> +dt2 = 0;
> +} else {
> +if (float64_is_neg(fdt0))
> +dt2 = INT64_MIN;
> +else
>

[Qemu-devel] [PATCH 0/2] target-mips: Initiate IEEE 754-2008 support for Mips

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

V2 - Relevant CPU initialization code changes revisited for all platforms.

   - In connection with <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> and
 <ABS|NEG>.<S|D> Mips instructions handling, decision on whether
 pre-nan2008 or nan2008 handling will apply moved from run-time to
 translate-time.

   - For Mips only, in nan2008 cases only, default NaN values fixed.

   - For Mips only, in nan2008 cases only, order in pickNaNMulAdd() fixed.

   - Code cleanup issues:
   a. Constants <floatx80|float128>_default_nan_<low|high> removed;
   b. Suffix <l|w>_<s|d> replaced with _<l|w>_<s|d> for some Mips helpers;
   c. In vicinity of changes, fixed not-beautiful code formatting.

   - Commit messages improved.

V1 - Initial version
 (https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg06082.html)

Mips platform represents the most complex case among QEMU-supported
platforms in reference to certain aspects of floating-point arithmetics.
This is mostly a consequence of the fact that Mips platform, for many
reasons, evolved considerably over time related to floating-point
arithmetics standards (significantly more than other platforms).
It has been difficult for emulators like QEMU to support such variety
of configurations.

This patch series provides number of IEEE 754-2008-related features to
Mips platform. It addresses the most sensitive changes that require
modification of SoftFloat library, that is used by most other platforms.

In order to make develpoment, testing, and integration easier, the patch
is split into two distinct parts:

1. Patch 1 that does not change any calculation or behavior for any
   platform (and, for that matter, even for Mips platform). Its sole
   purpose is to address platform independant issues in a non-invasive
   manner, and to make Patch 2 possible.

2. Patch 2 that sets approprite Mips architecures to use provisions from
   Patch 1, and additionally implements some of IEEE 754-2008-related
   features for Mips, but, at the same time, dealing with files located
   in directory target-mips only.

A limitation of this patch series is that it does not cover all IEEE 754-2008
Mips issues (for example, handling FCR31's FS bit). However, hopefully all
remaining such issues will touch only Mips-specific source code files, and thus
will be much easier to integrate in QEMU, in overall.

This patch series is based on the original set of patches proposed by Maciej
Rozycki: http://lists.nongnu.org/archive/html/qemu-devel/2014-12/msg00968.html
Aleksandar Markovic (2):
  softfloat: Implement run-time-configurable meaning of signaling NaN bit
  target-mips: Activate IEEE 754-2008 support for Mips

 fpu/softfloat-specialize.h|  587 +
 fpu/softfloat.c   |  180 ++---
 include/fpu/softfloat.h   |   49 ++--
 target-alpha/cpu.c|2 +
 target-arm/helper-a64.c   |   14 +-
 target-arm/helper.c   |   40 +--
 target-m68k/helper.c  |6 +-
 target-microblaze/cpu.c   |2 +
 target-microblaze/op_helper.c |6 +-
 target-mips/helper.h  |   22 +-
 target-mips/msa_helper.c  |   96 ---
 target-mips/op_helper.c   |  350 ++--
 target-mips/translate.c   |  157 +--
 target-mips/translate_init.c  |   20 +-
 target-ppc/fpu_helper.c   |  120 -
 target-ppc/translate_init.c   |2 +
 target-s390x/cpu.c|1 +
 target-s390x/fpu_helper.c |   28 +-
 target-s390x/helper.h |6 +-
 target-s390x/translate.c  |6 +-
 target-sh4/cpu.c  |1 +
 target-sparc/cpu.c|1 +
 target-tricore/helper.c   |1 +
 target-unicore32/cpu.c|2 +
 target-xtensa/cpu.c   |3 +
 25 files changed, 1078 insertions(+), 624 deletions(-)

-- 
1.7.9.5

[Qemu-devel] [PATCH 1/2] softfloat: Implement run-time-configurable meaning of signaling NaN bit

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch modifies SoftFloat library so that it can be configured at
run-time in relation to the meaning of signaling NaN bit, while, at the
same time, strictly preserving its behavior on all existing platforms.

Background:

In floating-point calculations, there is a need for denoting undefined or
unrepresentable values. This is achieved by defining certain floating-point
numerical values to be NaNs (which stands for "not a number"). For additional
reasons, virtually all modern floating-point unit implementations use two
kinds of NaNs: quiet and signaling. The binary representations of these two
kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally,
the first bit of mantissa).

Up to 2008, standards for floating-point did not specify all details about
binary representation of NaNs. More specifically, the meaning of the bit
that is used for distinguishing between signaling and quiet NaNs was not
strictly prescribed. (IEEE 754-2008 was the first floating-point standard
that defined that meaning clearly, see [1], p. 35) As a result, different
platforms took different approaches, and that presented considerable
challenge for multi-platform emulators like QEMU.

Mips platform represents the most complex case among QEMU-supported
platforms regarding signaling NaN bit. Up to the Release 6 of Mips
architecture, "1" in signaling NaN bit denoted signaling NaN, which is
opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
that, Mips architecture for SIMD (also known as MSA, or vector instructions)
also specifies signaling bit in accordance to IEEE standard. MSA unit can be
implemented with both pre-Release 6 and Release 6 main processor units.

QEMU uses SoftFloat library to implement various floating-point-related
instructions on all platforms. The current QEMU implementation allows for
defining meaning of signaling NaN bit during build time, and is implemented
via preprocessor macro called SNAN_BIT_IS_ONE.

On the other hand, the change in this patch enables SoftFloat library to be
configured in run-time. This configuration is meant to occur during CPU
initialization, at the moment when it is definitely known what desired
behavior for particular CPU (or any additional FPUs) is.

The change is implemented so that it is consistent with existing
implementation of similar cases. This means that structure float_status is
used for passing the information about desired signaling NaN bit on each
invocation of SoftFloat functions. The additional field in float_status is
called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.

IMPORTANT:

This change is not meant to create any change in emulator behavior or
functionality on any platform. It just provides the means for SoftFloat
library to be used in a more flexible way - in other words, it will just
prepare SoftFloat library for usage related to Mips platform and its
specifics regarding signaling bit meaning, which is done in the next patch.

Further break down of changes:

  1) Added field snan_bit_is_one to the structure float_status, and
 correspondent setter function set_snan_bit_is_one().

  2) Constants <float16|float32|float64|floatx80|float128>_default_nan
 (used both internally and externally) converted to functions
 <float16|float32|float64|floatx80|float128>_default_nan(float_status*).
 This is necessary since they are dependent on signaling bit meaning.
 At the same time, for the sake of code cleanup and simplicity, constants
 <floatx80|float128>_default_nan_<low|high> (used only internally within
 SoftFloat library) are removed, as not needed.

  3) Added a float_status* argument to SoftFloat library functions
 XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
 XXX_maybe_silence_nan(XXX a_). This argument must be present in
 order to enable correct invocation of new version of functions
 XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128>
 here)

  4) Only for mips platform, and only for cases when snan_bit_is_one is 0,
 desired values for default NaNs (in their 16-, 32-, and 64-bit flavors)
 are different than the default ones currently provided by SoftFloat
 library (which are actually correct values for pre-nan2008 mips cases).
 This is all sorted out by this patch. The newly added values will
 never be used, if only this patch from the patch series is applied.
 However, they will kick in once appropriate mips architectures are
 configured to use them, which happens in the next patch of the series.

  5) Only for mips platform, and only for cases when snan_bit_is_one is 0,
 current pickNaNMulAdd() would not provide the right order for argument
 comparisons. This patch fixes this behavior too. Simila

[Qemu-devel] [PATCH 2/2] target-mips: Activate IEEE 754-2008 support for Mips

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch utilizes provisions from the previous patch, and configures
Mips R6 CPUs and Mips MSA units appropriately with reference to the meaning
of the signaling NaN bit (this is mentioned in point 2 in the list below).
The majority of involved MIPS instructions will be fixed just with that
change. Certain number of other IEEE 754-2008-related MIPS issues are
addressed with this patch as well.

The changes can be summarized this way:

1) Definitions of Mips processors are updated to reflect supported
   IEEE-754-2008-related features. (file target-mips/translate_init.c)

2) Functions mips_cpu_reset() and msa_reset() are updated so that flag
   snan_bit_is_one is properly set for any Mips configuration.
   (file target-mips/translate_init.c)

3) Updated handling of instuctions <ABS|NEG>.<S|D>. Note that legacy
   (pre-nan2008) ABS and NEG instructions are arithmetic (any NaN operand
   signals invalid operation), while R6 ones are non-arithmetic, always
   changing the sign bit, even for NaN-like operands. Details on these
   instructions are documented in [1] p. 35 and 359. Affected file is
   target-mips/translate.c.

4) New set of helpers for handling nan2008-syle versions of instructions
   <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>. Details on these instructions
   are presented in [1] p. 129, 130, 149, 155, 222, 223, 393, 394, 504,
   505. Affected files are target-mips/helper.h, target-mips/translate.c,
   and target-mips/op-helper.c.

[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

[2] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32® SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016

Signed-off-by: Maciej Rozycki <maciej.rozy...@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/helper.h |   18 ++-
 target-mips/op_helper.c  |  334 +++---
 target-mips/translate.c  |  154 +++
 target-mips/translate_init.c |   17 ++-
 4 files changed, 467 insertions(+), 56 deletions(-)

diff --git a/target-mips/helper.h b/target-mips/helper.h
index 133dcfb..61bbda7 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -207,8 +207,6 @@ DEF_HELPER_4(ctc1, void, env, tl, i32, i32)
 DEF_HELPER_2(float_cvtd_s, i64, env, i32)
 DEF_HELPER_2(float_cvtd_w, i64, env, i32)
 DEF_HELPER_2(float_cvtd_l, i64, env, i64)
-DEF_HELPER_2(float_cvtl_d, i64, env, i64)
-DEF_HELPER_2(float_cvtl_s, i64, env, i32)
 DEF_HELPER_2(float_cvtps_pw, i64, env, i64)
 DEF_HELPER_2(float_cvtpw_ps, i64, env, i64)
 DEF_HELPER_2(float_cvts_d, i32, env, i64)
@@ -216,8 +214,6 @@ DEF_HELPER_2(float_cvts_w, i32, env, i32)
 DEF_HELPER_2(float_cvts_l, i32, env, i64)
 DEF_HELPER_2(float_cvts_pl, i32, env, i32)
 DEF_HELPER_2(float_cvts_pu, i32, env, i32)
-DEF_HELPER_2(float_cvtw_s, i32, env, i32)
-DEF_HELPER_2(float_cvtw_d, i32, env, i64)
 
 DEF_HELPER_3(float_addr_ps, i64, env, i64, i64)
 DEF_HELPER_3(float_mulr_ps, i64, env, i64, i64)
@@ -242,14 +238,20 @@ FOP_PROTO(mina)
 #undef FOP_PROTO
 
 #define FOP_PROTO(op)\
-DEF_HELPER_2(float_ ## op ## l_s, i64, env, i32) \
-DEF_HELPER_2(float_ ## op ## l_d, i64, env, i64) \
-DEF_HELPER_2(float_ ## op ## w_s, i32, env, i32) \
-DEF_HELPER_2(float_ ## op ## w_d, i32, env, i64)
+DEF_HELPER_2(float_ ## op ## _l_s, i64, env, i32) \
+DEF_HELPER_2(float_ ## op ## _l_d, i64, env, i64) \
+DEF_HELPER_2(float_ ## op ## _w_s, i32, env, i32) \
+DEF_HELPER_2(float_ ## op ## _w_d, i32, env, i64)
+FOP_PROTO(cvt)
 FOP_PROTO(round)
 FOP_PROTO(trunc)
 FOP_PROTO(ceil)
 FOP_PROTO(floor)
+FOP_PROTO(cvt_2008)
+FOP_PROTO(round_2008)
+FOP_PROTO(trunc_2008)
+FOP_PROTO(ceil_2008)
+FOP_PROTO(floor_2008)
 #undef FOP_PROTO
 
 #define FOP_PROTO(op)\
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index ce7ec9c..841f066 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2448,9 +2448,19 @@ void mips_cpu_unassigned_access(CPUState *cs, hwaddr 
addr,
 
 #define FLOAT_TWO32 make_float32(1 << 30)
 #define FLOAT_TWO64 make_float64(1ULL << 62)
+
 #define FP_TO_INT32_OVERFLOW 0x7fff
 #define FP_TO_INT64_OVERFLOW 0x7fffULL
 
+#define FLT_TO_INT32_OVERFLOW(x) \
+float32_is_any_nan(x) ? 0 : (float32_is_neg(x) ? INT32_MIN : INT32_MAX)
+#define FLT_TO_INT64_OVERFLOW(x) \
+float32_is_any_nan(x) ? 0 : (float32_is_neg(x) ? INT64_MIN : INT64_MAX)
+#define DBL_TO_INT32_OVERFLOW(x) \
+float64_is_any_nan(x) ? 0 : (float64_is_neg(x) ? INT32_MIN : INT32_MAX)
+#define DBL_TO_INT64_OVERFLOW

[Qemu-devel] [PATCH v4 6/9] target-mips: Activate IEEE 274-2008 support

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

1) Definitions of Mips processors are updated to reflect supported
   IEEE-754-2008-related features. (file target-mips/translate_init.c)

2) Functions mips_cpu_reset() and msa_reset() are updated so that flag
   snan_bit_is_one is properly set for any Mips configuration.
   (file target-mips/translate_init.c)

Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/translate.c  |6 +-
 target-mips/translate_init.c |   18 +++---
 2 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 496216d..de0b224 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -20129,7 +20129,11 @@ void cpu_state_reset(CPUMIPSState *env)
 env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
 env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
 env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
-set_snan_bit_is_one(1, >active_fpu.fp_status);
+if ((env->active_fpu.fcr31 >> FCR31_NAN2008) & 1) {
+set_snan_bit_is_one(0, >active_fpu.fp_status);
+} else {
+set_snan_bit_is_one(1, >active_fpu.fp_status);
+}
 env->msair = env->cpu_model->MSAIR;
 env->insn_flags = env->cpu_model->insn_flags;
 
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index e81a831..878fef6 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -273,6 +273,7 @@ static const mips_def_t mips_defs[] =
 .CP0_Status_rw_bitmask = 0x3678FF1F,
 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+.CP1_fcr31 = 0,
 .SEGBITS = 32,
 .PABITS = 32,
 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
@@ -303,6 +304,7 @@ static const mips_def_t mips_defs[] =
 (0xff << CP0TCSt_TASID),
 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
+.CP1_fcr31 = 0,
 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
 .CP0_SRSConf0_rw_bitmask = 0x3fff,
 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
@@ -343,6 +345,7 @@ static const mips_def_t mips_defs[] =
 .CP0_Status_rw_bitmask = 0x3778FF1F,
 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+.CP1_fcr31 = 0,
 .SEGBITS = 32,
 .PABITS = 32,
 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
@@ -434,7 +437,7 @@ static const mips_def_t mips_defs[] =
 },
 {
 /* A generic CPU supporting MIPS32 Release 6 ISA.
-   FIXME: Support IEEE 754-2008 FP.
+   FIXME: Complete support for IEEE 754-2008 FP.
   Eventually this should be replaced by a real CPU model. */
 .name = "mips32r6-generic",
 .CP0_PRid = 0x0001,
@@ -485,6 +488,7 @@ static const mips_def_t mips_defs[] =
 .CP0_Status_rw_bitmask = 0x3678,
 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
+.CP1_fcr31 = 0,
 .SEGBITS = 40,
 .PABITS = 36,
 .insn_flags = CPU_MIPS3,
@@ -503,6 +507,7 @@ static const mips_def_t mips_defs[] =
 .CP0_Status_rw_bitmask = 0x3678,
 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
+.CP1_fcr31 = 0,
 .SEGBITS = 40,
 .PABITS = 32,
 .insn_flags = CPU_VR54XX,
@@ -548,6 +553,7 @@ static const mips_def_t mips_defs[] =
 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
+.CP1_fcr31 = 0,
 .SEGBITS = 42,
 .PABITS = 36,
 .insn_flags = CPU_MIPS64,
@@ -575,6 +581,7 @@ static const mips_def_t mips_defs[] =
 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
 (1 << FCR0_D) | (1 << FCR0_S) |
 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
+.CP1_fcr31 = 0,
 .SEGBITS = 40,
 .PABITS = 36,
 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
@@ -601,6 +608,7 @@ static const mips_def_t mips_defs[] =
 .CP1_fcr0 = (1

[Qemu-devel] [PATCH v4 3/9] softfloat: For Mips only, correct order in pickNaNMulAdd()

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Only for Mips platform, and only for cases when snan_bit_is_one is 0,
correct the order of argument comparisons in pickNaNMulAdd().

For more info, see [2], page 53, section "3.5.3 NaN Propagation".

[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

[2] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32® SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 fpu/softfloat-specialize.h |   41 +
 1 file changed, 29 insertions(+), 12 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 169246e..807ecc0 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -569,19 +569,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag 
bIsQNaN, flag bIsSNaN,
 return 3;
 }
 
-/* Prefer sNaN over qNaN, in the c, a, b order. */
-if (cIsSNaN) {
-return 2;
-} else if (aIsSNaN) {
-return 0;
-} else if (bIsSNaN) {
-return 1;
-} else if (cIsQNaN) {
-return 2;
-} else if (aIsQNaN) {
-return 0;
+if (status->snan_bit_is_one) {
+/* Prefer sNaN over qNaN, in the a, b, c order. */
+if (aIsSNaN) {
+return 0;
+} else if (bIsSNaN) {
+return 1;
+} else if (cIsSNaN) {
+return 2;
+} else if (aIsQNaN) {
+return 0;
+} else if (bIsQNaN) {
+return 1;
+} else {
+return 2;
+}
 } else {
-return 1;
+/* Prefer sNaN over qNaN, in the c, a, b order. */
+if (cIsSNaN) {
+return 2;
+} else if (aIsSNaN) {
+return 0;
+} else if (bIsSNaN) {
+return 1;
+} else if (cIsQNaN) {
+return 2;
+} else if (aIsQNaN) {
+return 0;
+} else {
+return 1;
+}
 }
 }
 #elif defined(TARGET_PPC)
-- 
1.7.9.5

[Qemu-devel] [PATCH v4 7/9] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Updated handling of instuctions <ABS|NEG>.<S|D>. Note that legacy
(pre-abs2008) ABS and NEG instructions are arithmetic (any NaN operand
signals invalid operation), while abs2008 ones are non-arithmetic, always
changing the sign bit, even for NaN-like operands. Details on these
instructions are documented in [1] p. 35 and 359.

[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/translate.c |   27 +++
 1 file changed, 23 insertions(+), 4 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index de0b224..1d376fc 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1434,6 +1434,8 @@ typedef struct DisasContext {
 bool vp;
 bool cmgcr;
 bool mrp;
+bool abs2008;
+
 } DisasContext;
 
 enum {
@@ -8879,7 +8881,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i32 fp0 = tcg_temp_new_i32();
 
 gen_load_fpr32(ctx, fp0, fs);
-gen_helper_float_abs_s(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_andi_i32(fp0, fp0, 0x7fffUL);
+} else {
+gen_helper_float_abs_s(fp0, fp0);
+}
 gen_store_fpr32(ctx, fp0, fd);
 tcg_temp_free_i32(fp0);
 }
@@ -8898,7 +8904,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i32 fp0 = tcg_temp_new_i32();
 
 gen_load_fpr32(ctx, fp0, fs);
-gen_helper_float_chs_s(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_xori_i32(fp0, fp0, 1UL << 31);
+} else {
+gen_helper_float_chs_s(fp0, fp0);
+}
 gen_store_fpr32(ctx, fp0, fd);
 tcg_temp_free_i32(fp0);
 }
@@ -9369,7 +9379,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i64 fp0 = tcg_temp_new_i64();
 
 gen_load_fpr64(ctx, fp0, fs);
-gen_helper_float_abs_d(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_andi_i64(fp0, fp0, 0x7fffULL);
+} else {
+gen_helper_float_abs_d(fp0, fp0);
+}
 gen_store_fpr64(ctx, fp0, fd);
 tcg_temp_free_i64(fp0);
 }
@@ -9390,7 +9404,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i64 fp0 = tcg_temp_new_i64();
 
 gen_load_fpr64(ctx, fp0, fs);
-gen_helper_float_chs_d(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_xori_i64(fp0, fp0, 1ULL << 63);
+} else {
+gen_helper_float_chs_d(fp0, fp0);
+}
 gen_store_fpr64(ctx, fp0, fd);
 tcg_temp_free_i64(fp0);
 }
@@ -19775,6 +19793,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct 
TranslationBlock *tb)
  (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
 ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
 ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
+ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
 restore_cpu_state(env, );
 #ifdef CONFIG_USER_ONLY
 ctx.mem_idx = MIPS_HFLAG_UM;
-- 
1.7.9.5

[Qemu-devel] [PATCH v4 0/9] target-mips: Initiate IEEE 754-2008 support

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

v4 - Added code cleanup items:
   a. Capitalization of hex constants in softfloat-specialize.h;
   b. White spaces in softfloat-specialize.h;
   c. Order of Mips helpers for CVT.<L|W>.<S|D>.

v3 - Patch series reorganized into 6 patches instead of 2.
   - Commit messages improved.
   - Except commit messages, net result of applying v3 and v2 is the same.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01870.html)

v2 - Relevant CPU initialization code changes revisited for all platforms.
   - In connection with <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> and
 <ABS|NEG>.<S|D> Mips instructions handling, decision on whether
 pre-nan2008/pre-abs2008 or nan2008/abs2008 handling will apply
 moved from run-time to translate-time.
   - For Mips only, in nan2008 cases only, default NaN values fixed.
   - For Mips only, in nan2008 cases only, order in pickNaNMulAdd() fixed.
   - Code cleanup issues:
   a. Constants <floatx80|float128>_default_nan_<low|high> removed;
   b. Suffix <l|w>_<s|d> replaced with _<l|w>_<s|d> for some Mips helpers;
   c. In vicinity of changes, fixed not-beautiful code formatting.
   - Commit messages improved.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01232.html)

V1 - Initial version
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg06082.html)

Mips platform represents the most complex case among QEMU-supported
platforms in reference to certain aspects of floating-point arithmetics.
This is mostly a consequence of the fact that Mips platform, for many
reasons, evolved considerably over time related to floating-point
arithmetics standards (significantly more than other platforms).
It has been difficult for emulators like QEMU to support such variety
of configurations.

This patch series provides number of IEEE 754-2008-related features to
Mips platform. It addresses the most sensitive changes that require
modification of SoftFloat library, that is used by most other platforms.

In order to make develpoment, testing, and integration easier, the patch
is split into two distinct parts:

   1. Part 1 (patches 1/6, 2/6, 3/6) that does not change any calculation
  or behavior on any platform (and, for that matter, even on Mips
  platform). Its sole purpose is to address platform independant
  issues in a non-invasive manner, and to make Part 2 possible.

   2. Part 2 (patches 4/6, 5/6, 6/6) that sets some Mips architecures to
  use provisions from Part 1, and additionally implements some of
  IEEE 754-2008-relates features for Mips, but, at the same time,
  dealing with files located in directory target-mips only.

A limitation of this patch series is that it does not cover all IEEE 754-2008
Mips issues (for example, handling FCR31's FS bit, handling R3 architectures,
some gdb issues, ELF header nan2008-related changes). However, hopefully all
remaining such issues will touch only Mips-specific source code files, and
thus will be much easier to integrate in QEMU, and, of course, will not be
disruptive to orher platforms.

This patch series is based on the original set of patches proposed by Maciej W.
Rozycki: http://lists.nongnu.org/archive/html/qemu-devel/2014-12/msg00968.html

Aleksandar Markovic (9):
  softfloat: Implement run-time-configurable meaning of signaling NaN bit
  softfloat: For Mips only, correct default NaN values
  softfloat: For Mips only, correct order in pickNaNMulAdd()
  softfloat: Clean up hex constants capitalization in softfloat-specialize.h
  softfloat: Clean up white spaces in softfloat-specialize.h
  target-mips: Activate IEEE 274-2008 support
  target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>
  target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
  target-mips: Clean up order of helpers for CVT.<L|W>.<S|D>

 fpu/softfloat-specialize.h|  648 +
 fpu/softfloat.c   |  172 +--
 include/fpu/softfloat.h   |   45 +--
 target-alpha/cpu.c|2 +
 target-arm/helper-a64.c   |   14 +-
 target-arm/helper.c   |   40 +--
 target-m68k/helper.c  |6 +-
 target-microblaze/cpu.c   |2 +
 target-microblaze/op_helper.c |6 +-
 target-mips/helper.h  |   22 +-
 target-mips/msa_helper.c  |   96 +++---
 target-mips/op_helper.c   |  402 +
 target-mips/translate.c   |  157 --
 target-mips/translate_init.c  |   18 +-
 target-ppc/fpu_helper.c   |  120 
 target-ppc/translate_init.c   |2 +
 target-s390x/cpu.c|1 +
 target-s390x/fpu_helper.c |   28 +-
 target-s390x/helper.h |6 +-
 target-s390x/translate.c  |6 +-
 target-sh4/cpu.c  |1 +
 

[Qemu-devel] [PATCH v4 8/9] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

New set of helpers for handling nan2008-syle versions of instructions
<CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>. Details on these instructions
are presented in [1] p. 129, 130, 149, 155, 222, 223, 393, 394, 504, 505.

[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/helper.h|   18 +--
 target-mips/op_helper.c |  334 ---
 target-mips/translate.c |  123 ++---
 3 files changed, 426 insertions(+), 49 deletions(-)

diff --git a/target-mips/helper.h b/target-mips/helper.h
index 133dcfb..61bbda7 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -207,8 +207,6 @@ DEF_HELPER_4(ctc1, void, env, tl, i32, i32)
 DEF_HELPER_2(float_cvtd_s, i64, env, i32)
 DEF_HELPER_2(float_cvtd_w, i64, env, i32)
 DEF_HELPER_2(float_cvtd_l, i64, env, i64)
-DEF_HELPER_2(float_cvtl_d, i64, env, i64)
-DEF_HELPER_2(float_cvtl_s, i64, env, i32)
 DEF_HELPER_2(float_cvtps_pw, i64, env, i64)
 DEF_HELPER_2(float_cvtpw_ps, i64, env, i64)
 DEF_HELPER_2(float_cvts_d, i32, env, i64)
@@ -216,8 +214,6 @@ DEF_HELPER_2(float_cvts_w, i32, env, i32)
 DEF_HELPER_2(float_cvts_l, i32, env, i64)
 DEF_HELPER_2(float_cvts_pl, i32, env, i32)
 DEF_HELPER_2(float_cvts_pu, i32, env, i32)
-DEF_HELPER_2(float_cvtw_s, i32, env, i32)
-DEF_HELPER_2(float_cvtw_d, i32, env, i64)
 
 DEF_HELPER_3(float_addr_ps, i64, env, i64, i64)
 DEF_HELPER_3(float_mulr_ps, i64, env, i64, i64)
@@ -242,14 +238,20 @@ FOP_PROTO(mina)
 #undef FOP_PROTO
 
 #define FOP_PROTO(op)\
-DEF_HELPER_2(float_ ## op ## l_s, i64, env, i32) \
-DEF_HELPER_2(float_ ## op ## l_d, i64, env, i64) \
-DEF_HELPER_2(float_ ## op ## w_s, i32, env, i32) \
-DEF_HELPER_2(float_ ## op ## w_d, i32, env, i64)
+DEF_HELPER_2(float_ ## op ## _l_s, i64, env, i32) \
+DEF_HELPER_2(float_ ## op ## _l_d, i64, env, i64) \
+DEF_HELPER_2(float_ ## op ## _w_s, i32, env, i32) \
+DEF_HELPER_2(float_ ## op ## _w_d, i32, env, i64)
+FOP_PROTO(cvt)
 FOP_PROTO(round)
 FOP_PROTO(trunc)
 FOP_PROTO(ceil)
 FOP_PROTO(floor)
+FOP_PROTO(cvt_2008)
+FOP_PROTO(round_2008)
+FOP_PROTO(trunc_2008)
+FOP_PROTO(ceil_2008)
+FOP_PROTO(floor_2008)
 #undef FOP_PROTO
 
 #define FOP_PROTO(op)\
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index ce7ec9c..841f066 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2448,9 +2448,19 @@ void mips_cpu_unassigned_access(CPUState *cs, hwaddr 
addr,
 
 #define FLOAT_TWO32 make_float32(1 << 30)
 #define FLOAT_TWO64 make_float64(1ULL << 62)
+
 #define FP_TO_INT32_OVERFLOW 0x7fff
 #define FP_TO_INT64_OVERFLOW 0x7fffULL
 
+#define FLT_TO_INT32_OVERFLOW(x) \
+float32_is_any_nan(x) ? 0 : (float32_is_neg(x) ? INT32_MIN : INT32_MAX)
+#define FLT_TO_INT64_OVERFLOW(x) \
+float32_is_any_nan(x) ? 0 : (float32_is_neg(x) ? INT64_MIN : INT64_MAX)
+#define DBL_TO_INT32_OVERFLOW(x) \
+float64_is_any_nan(x) ? 0 : (float64_is_neg(x) ? INT32_MIN : INT32_MAX)
+#define DBL_TO_INT64_OVERFLOW(x) \
+float64_is_any_nan(x) ? 0 : (float64_is_neg(x) ? INT64_MIN : INT64_MAX)
+
 /* convert MIPS rounding mode in FCR31 to IEEE library */
 unsigned int ieee_rm[] = {
 float_round_nearest_even,
@@ -2683,7 +2693,7 @@ uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t 
dt0)
 return fdt2;
 }
 
-uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
+uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
 {
 uint64_t dt2;
 
@@ -2696,7 +2706,7 @@ uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t 
fdt0)
 return dt2;
 }
 
-uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
+uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
 {
 uint64_t dt2;
 
@@ -2791,7 +2801,7 @@ uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t 
wth0)
 return wt2;
 }
 
-uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
+uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
 {
 uint32_t wt2;
 
@@ -2804,7 +2814,7 @@ uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t 
fst0)
 return wt2;
 }
 
-uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
+uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
 {
 uint32_t wt2;
 
@@ -2817,7 +2827,7 @@ uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t 
fdt0)
 return wt2;
 }
 
-uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
+uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
 {

[Qemu-devel] [PATCH v4 4/9] softfloat: Clean up hex constants capitalization in softfloat-specialize.h

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

With this partch, capitals A, B, C, D, E, F are always used for hex
constants in softfloat-specialize.h. The large latter size is chosen
just beacause it is currently prevalent in this file.

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 fpu/softfloat-specialize.h |   34 +-
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 807ecc0..a5680e0 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -230,7 +230,7 @@ int float16_is_quiet_nan(float16 a_, float_status *status)
 if (status->snan_bit_is_one) {
 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
 } else {
-return ((a & ~0x8000) >= 0x7c80);
+return ((a & ~0x8000) >= 0x7C80);
 }
 }
 
@@ -243,7 +243,7 @@ int float16_is_signaling_nan(float16 a_, float_status 
*status)
 {
 uint16_t a = float16_val(a_);
 if (status->snan_bit_is_one) {
-return ((a & ~0x8000) >= 0x7c80);
+return ((a & ~0x8000) >= 0x7C80);
 } else {
 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
 }
@@ -328,9 +328,9 @@ int float32_is_quiet_nan( float32 a_, float_status *status )
 {
 uint32_t a = float32_val(a_);
 if (status->snan_bit_is_one) {
-return (((a >> 22) & 0x1ff) == 0x1fe) && (a & 0x003f);
+return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003F);
 } else {
-return ((uint32_t)(a << 1) >= 0xff80);
+return ((uint32_t)(a << 1) >= 0xFF80);
 }
 }
 
@@ -343,7 +343,7 @@ int float32_is_signaling_nan( float32 a_, float_status 
*status )
 {
 uint32_t a = float32_val(a_);
 if (status->snan_bit_is_one) {
-return ((uint32_t)(a << 1) >= 0xff80);
+return ((uint32_t)(a << 1) >= 0xFF80);
 } else {
 return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003F );
 }
@@ -758,10 +758,10 @@ int float64_is_quiet_nan( float64 a_, float_status 
*status)
 {
 uint64_t a = float64_val(a_);
 if (status->snan_bit_is_one) {
-return (((a >> 51) & 0xfff) == 0xffe)
-   && (a & 0x0007ULL);
+return (((a >> 51) & 0xFFF) == 0xFFE)
+   && (a & 0x0007ULL);
 } else {
-return ((a << 1) >= 0xfff0ULL);
+return ((a << 1) >= 0xFFF0ULL);
 }
 }
 
@@ -774,7 +774,7 @@ int float64_is_signaling_nan( float64 a_, float_status 
*status )
 {
 uint64_t a = float64_val(a_);
 if (status->snan_bit_is_one) {
-return ((a << 1) >= 0xfff0ULL);
+return ((a << 1) >= 0xFFF0ULL);
 } else {
 return
( ( ( a>>51 ) & 0xFFF ) == 0xFFE )
@@ -961,7 +961,7 @@ int floatx80_is_quiet_nan( floatx80 a, float_status *status 
)
 uint64_t aLow;
 
 aLow = a.low & ~0x4000ULL;
-return ((a.high & 0x7fff) == 0x7fff)
+return ((a.high & 0x7FFF) == 0x7FFF)
 && (aLow << 1)
 && (a.low == aLow);
 } else {
@@ -979,7 +979,7 @@ int floatx80_is_quiet_nan( floatx80 a, float_status *status 
)
 int floatx80_is_signaling_nan( floatx80 a, float_status *status )
 {
 if (status->snan_bit_is_one) {
-return ((a.high & 0x7fff) == 0x7fff)
+return ((a.high & 0x7FFF) == 0x7FFF)
 && ((a.low << 1) >= 0x8000ULL);
 } else {
 uint64_t aLow;
@@ -1120,12 +1120,12 @@ int float128_is_signaling_nan(float128 a_, float_status 
*status)
 int float128_is_quiet_nan( float128 a, float_status *status )
 {
 if (status->snan_bit_is_one) {
-return (((a.high >> 47) & 0x) == 0xfffe)
-&& (a.low || (a.high & 0x7fffULL));
+return (((a.high >> 47) & 0x) == 0xFFFE)
+&& (a.low || (a.high & 0x7FFFULL));
 } else {
 return
-((a.high << 1) >= 0xULL)
-&& (a.low || (a.high & 0xULL));
+((a.high << 1) >= 0xULL)
+&& (a.low || (a.high & 0xULL));
 }
 }
 
@@ -1138,8 +1138,8 @@ int float128_is_signaling_nan( float128 a, float_status 
*status )
 {
 if (status->snan_bit_is_one) {
 return
-((a.high << 1) >= 0xULL)
-&& (a.low || (a.high & 0xULL));
+((a.high << 1) >= 0xULL)
+&& (a.low || (a.high & 0xULL));
 } else {
 return
( ( ( a.high>>47 ) & 0x ) == 0xFFFE )
-- 
1.7.9.5

[Qemu-devel] [PATCH v4 9/9] target-mips: Clean up order of helpers for CVT.<L|W>.<S|D>

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch makes position of helpers for CVT.<L|W>.<S|D> consistent with
position of helpers for <CEIL|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>.

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/op_helper.c |   60 +++
 1 file changed, 30 insertions(+), 30 deletions(-)

diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 841f066..6b3d5bd 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2693,32 +2693,6 @@ uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t 
dt0)
 return fdt2;
 }
 
-uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
-{
-uint64_t dt2;
-
-dt2 = float64_to_int64(fdt0, >active_fpu.fp_status);
-if (get_float_exception_flags(>active_fpu.fp_status)
-& (float_flag_invalid | float_flag_overflow)) {
-dt2 = FP_TO_INT64_OVERFLOW;
-}
-update_fcr31(env, GETPC());
-return dt2;
-}
-
-uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
-{
-uint64_t dt2;
-
-dt2 = float32_to_int64(fst0, >active_fpu.fp_status);
-if (get_float_exception_flags(>active_fpu.fp_status)
-& (float_flag_invalid | float_flag_overflow)) {
-dt2 = FP_TO_INT64_OVERFLOW;
-}
-update_fcr31(env, GETPC());
-return dt2;
-}
-
 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
 {
 uint32_t fst2;
@@ -2801,11 +2775,37 @@ uint32_t helper_float_cvts_pu(CPUMIPSState *env, 
uint32_t wth0)
 return wt2;
 }
 
-uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
+uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
+{
+uint64_t dt2;
+
+dt2 = float64_to_int64(fdt0, >active_fpu.fp_status);
+if (get_float_exception_flags(>active_fpu.fp_status)
+& (float_flag_invalid | float_flag_overflow)) {
+dt2 = FP_TO_INT64_OVERFLOW;
+}
+update_fcr31(env, GETPC());
+return dt2;
+}
+
+uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
+{
+uint64_t dt2;
+
+dt2 = float32_to_int64(fst0, >active_fpu.fp_status);
+if (get_float_exception_flags(>active_fpu.fp_status)
+& (float_flag_invalid | float_flag_overflow)) {
+dt2 = FP_TO_INT64_OVERFLOW;
+}
+update_fcr31(env, GETPC());
+return dt2;
+}
+
+uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
 {
 uint32_t wt2;
 
-wt2 = float32_to_int32(fst0, >active_fpu.fp_status);
+wt2 = float64_to_int32(fdt0, >active_fpu.fp_status);
 if (get_float_exception_flags(>active_fpu.fp_status)
 & (float_flag_invalid | float_flag_overflow)) {
 wt2 = FP_TO_INT32_OVERFLOW;
@@ -2814,11 +2814,11 @@ uint32_t helper_float_cvt_w_s(CPUMIPSState *env, 
uint32_t fst0)
 return wt2;
 }
 
-uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
+uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
 {
 uint32_t wt2;
 
-wt2 = float64_to_int32(fdt0, >active_fpu.fp_status);
+wt2 = float32_to_int32(fst0, >active_fpu.fp_status);
 if (get_float_exception_flags(>active_fpu.fp_status)
 & (float_flag_invalid | float_flag_overflow)) {
 wt2 = FP_TO_INT32_OVERFLOW;
-- 
1.7.9.5

[Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch modifies SoftFloat library so that it can be configured in
run-time in relation to the meaning of signaling NaN bit, while, at the
same time, strictly preserving its behavior on all existing platforms.

Background:

In floating-point calculations, there is a need for denoting undefined or
unrepresentable values. This is achieved by defining certain floating-point
numerical values to be NaNs (which stands for "not a number"). For additional
reasons, virtually all modern floating-point unit implementations use two
kinds of NaNs: quiet and signaling. The binary representations of these two
kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally,
the first bit of mantissa).

Up to 2008, standards for floating-point did not specify all details about
binary representation of NaNs. More specifically, the meaning of the bit
that is used for distinguishing between signaling and quiet NaNs was not
strictly prescribed. (IEEE 754-2008 was the first floating-point standard
that defined that meaning clearly, see [1], p. 35) As a result, different
platforms took different approaches, and that presented considerable
challenge for multi-platform emulators like QEMU.

Mips platform represents the most complex case among QEMU-supported
platforms regarding signaling NaN bit. Up to the Release 6 of Mips
architecture, "1" in signaling NaN bit denoted signaling NaN, which is
opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
that, Mips architecture for SIMD (also known as MSA, or vector instructions)
also specifies signaling bit in accordance to IEEE standard. MSA unit can be
implemented with both pre-Release 6 and Release 6 main processor units.

QEMU uses SoftFloat library to implement various floating-point-related
instructions on all platforms. The current QEMU implementation allows for
defining meaning of signaling NaN bit during build time, and is implemented
via preprocessor macro called SNAN_BIT_IS_ONE.

On the other hand, the change in this patch enables SoftFloat library to be
configured in run-time. This configuration is meant to occur during CPU
initialization, at the moment when it is definitely known what desired
behavior for particular CPU (or any additional FPUs) is.

The change is implemented so that it is consistent with existing
implementation of similar cases. This means that structure float_status is
used for passing the information about desired signaling NaN bit on each
invocation of SoftFloat functions. The additional field in float_status is
called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.

IMPORTANT:

This change is not meant to create any change in emulator behavior or
functionality on any platform. It just provides the means for SoftFloat
library to be used in a more flexible way - in other words, it will just
prepare SoftFloat library for usage related to Mips platform and its
specifics regarding signaling bit meaning, which is done in the next patch.

Further break down of changes:

  1) Added field snan_bit_is_one to the structure float_status, and
 correspondent setter function set_snan_bit_is_one().

  2) Constants <float16|float32|float64|floatx80|float128>_default_nan
 (used both internally and externally) converted to functions
 <float16|float32|float64|floatx80|float128>_default_nan(float_status*).
 This is necessary since they are dependent on signaling bit meaning.
 At the same time, for the sake of code cleanup and simplicity, constants
 <floatx80|float128>_default_nan_<low|high> (used only internally within
 SoftFloat library) are removed, as not needed.

  3) Added a float_status* argument to SoftFloat library functions
 XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
 XXX_maybe_silence_nan(XXX a_). This argument must be present in
 order to enable correct invocation of new version of functions
 XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128>
 here)

  4) Updated code for all platforms to reflect changes in SoftFloat library.
 This change is twofolds: it includes modifications of SoftFloat library
 functions invocations, and an addition of invocation of function
 set_snan_bit_is_one() during CPU initialization, with arguments that
 are appropriate for each particular platform.

 In order to be at the same time accurate in relation to floating point
 arithmetics and consistent with a particular platform code, following
 principle is adopted related to invocations of new function
 set_snan_bit_is_one():

 1. If a target platform doesn't use SoftFloat library, nothing is added.
(cris, lm32, moxie)
 2. Else, if a target platform's signaling bit meaning is "1 is
signaling", ex

[Qemu-devel] [PATCH v4 5/9] softfloat: Clean up white spaces in softfloat-specialize.h

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

As the development of SoftFloat library took places, many contributors
had different code styles, and the code was left with inconsistent style,
difficult to read, and hard to maintain.

This patch will make spaces around shift operators and braces consistent
within file fpu/softfloat-specialize.h.

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 fpu/softfloat-specialize.h |   94 ++--
 1 file changed, 47 insertions(+), 47 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index a5680e0..aa2f793 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -283,7 +283,7 @@ static commonNaNT float16ToCommonNaN(float16 a, 
float_status *status)
 }
 z.sign = float16_val(a) >> 15;
 z.low = 0;
-z.high = ((uint64_t) float16_val(a))<<54;
+z.high = ((uint64_t) float16_val(a)) << 54;
 return z;
 }
 
@@ -345,7 +345,7 @@ int float32_is_signaling_nan( float32 a_, float_status 
*status )
 if (status->snan_bit_is_one) {
 return ((uint32_t)(a << 1) >= 0xFF80);
 } else {
-return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003F );
+return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003F);
 }
 }
 #endif
@@ -382,9 +382,9 @@ static commonNaNT float32ToCommonNaN(float32 a, 
float_status *status)
 if (float32_is_signaling_nan(a, status)) {
 float_raise(float_flag_invalid, status);
 }
-z.sign = float32_val(a)>>31;
+z.sign = float32_val(a) >> 31;
 z.low = 0;
-z.high = ( (uint64_t) float32_val(a) )<<41;
+z.high = ((uint64_t)float32_val(a)) << 41;
 return z;
 }
 
@@ -395,7 +395,7 @@ static commonNaNT float32ToCommonNaN(float32 a, 
float_status *status)
 
 static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
 {
-uint32_t mantissa = a.high>>41;
+uint32_t mantissa = a.high >> 41;
 
 if (status->default_nan_mode) {
 return float32_default_nan(status);
@@ -403,7 +403,7 @@ static float32 commonNaNToFloat32(commonNaNT a, 
float_status *status)
 
 if ( mantissa ) {
 return make_float32(
-( ( (uint32_t) a.sign )<<31 ) | 0x7F80 | ( a.high>>41 ) );
+(((uint32_t)a.sign) << 31) | 0x7F80 | (a.high >> 41));
 } else {
 return float32_default_nan(status);
 }
@@ -656,10 +656,10 @@ static float32 propagateFloat32NaN(float32 a, float32 b, 
float_status *status)
 flag aIsLargerSignificand;
 uint32_t av, bv;
 
-aIsQuietNaN = float32_is_quiet_nan( a, status );
-aIsSignalingNaN = float32_is_signaling_nan( a, status );
-bIsQuietNaN = float32_is_quiet_nan( b, status );
-bIsSignalingNaN = float32_is_signaling_nan( b, status );
+aIsQuietNaN = float32_is_quiet_nan(a, status);
+aIsSignalingNaN = float32_is_signaling_nan(a, status);
+bIsQuietNaN = float32_is_quiet_nan(b, status);
+bIsSignalingNaN = float32_is_signaling_nan(b, status);
 av = float32_val(a);
 bv = float32_val(b);
 
@@ -670,9 +670,9 @@ static float32 propagateFloat32NaN(float32 a, float32 b, 
float_status *status)
 if (status->default_nan_mode)
 return float32_default_nan(status);
 
-if ((uint32_t)(av<<1) < (uint32_t)(bv<<1)) {
+if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) {
 aIsLargerSignificand = 0;
-} else if ((uint32_t)(bv<<1) < (uint32_t)(av<<1)) {
+} else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) {
 aIsLargerSignificand = 1;
 } else {
 aIsLargerSignificand = (av < bv) ? 1 : 0;
@@ -777,8 +777,8 @@ int float64_is_signaling_nan( float64 a_, float_status 
*status )
 return ((a << 1) >= 0xFFF0ULL);
 } else {
 return
-   ( ( ( a>>51 ) & 0xFFF ) == 0xFFE )
-&& ( a & LIT64( 0x0007 ) );
+   (((a >> 51) & 0xFFF) == 0xFFE)
+&& (a & LIT64( 0x0007 ));
 }
 }
 #endif
@@ -815,9 +815,9 @@ static commonNaNT float64ToCommonNaN(float64 a, 
float_status *status)
 if (float64_is_signaling_nan(a, status)) {
 float_raise(float_flag_invalid, status);
 }
-z.sign = float64_val(a)>>63;
+z.sign = float64_val(a) >> 63;
 z.low = 0;
-z.high = float64_val(a)<<12;
+z.high = float64_val(a) << 12;
 return z;
 }
 
@@ -828,7 +828,7 @@ static commonNaNT float64ToCommonNaN(float64 a, 
float_status *status)
 
 static float64 commonNaNToFloat64(commonNaNT a, float_status *status)
 {
-uint64_t mantissa = a.high>>12;
+uint64_t mantissa = a.high >> 12;
 
 if (status->default_nan_mode) {
 re

[Qemu-devel] [PATCH v4 2/9] softfloat: For Mips only, correct default NaN values

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Only for Mips platform, and only for cases when snan_bit_is_one is 0,
correct default NaN values (in their 16-, 32-, and 64-bit flavors).

For more info, see [1], page 84, Table 6.3 "Value Supplied When
a New Quiet NaN Is Created", and [2], page 52, table 3.7 "Default
NaN Encodings".

[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

[2] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32® SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 fpu/softfloat-specialize.h |   12 
 1 file changed, 12 insertions(+)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 53dae9b..169246e 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -97,7 +97,11 @@ float16 float16_default_nan(float_status *status)
 if (status->snan_bit_is_one) {
 return const_float16(0x7DFF);
 } else {
+#if defined(TARGET_MIPS)
+return const_float16(0x7E00);
+#else
 return const_float16(0xFE00);
+#endif
 }
 #endif
 }
@@ -116,7 +120,11 @@ float32 float32_default_nan(float_status *status)
 if (status->snan_bit_is_one) {
 return const_float32(0x7FBF);
 } else {
+#if defined(TARGET_MIPS)
+return const_float32(0x7FC0);
+#else
 return const_float32(0xFFC0);
+#endif
 }
 #endif
 }
@@ -135,7 +143,11 @@ float64 float64_default_nan(float_status *status)
 if (status->snan_bit_is_one) {
 return const_float64(LIT64( 0x7FF7 ));
 } else {
+#if defined(TARGET_MIPS)
+return const_float64(LIT64( 0x7FF8 ));
+#else
 return const_float64(LIT64( 0xFFF8 ));
+#endif
 }
 #endif
 }
-- 
1.7.9.5

[Qemu-devel] [PATCH v3 0/6] target-mips: Initiate IEEE 754-2008 support

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

v3 - Patch series reorganized into 6 patches instead of 2.
   - Commit messages improved.
   - Except commit messages, net result of applying v3 and v2 is the same.

v2 - Relevant CPU initialization code changes revisited for all platforms.
   - In connection with <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> and
 <ABS|NEG>.<S|D> Mips instructions handling, decision on whether
 pre-nan2008/pre-abs2008 or nan2008/abs2008 handling will apply
 moved from run-time to translate-time.
   - For Mips only, in nan2008 cases only, default NaN values fixed.
   - For Mips only, in nan2008 cases only, order in pickNaNMulAdd() fixed.
   - Code cleanup issues:
   a. Constants <floatx80|float128>_default_nan_<low|high> removed;
   b. Suffix <l|w>_<s|d> replaced with _<l|w>_<s|d> for some Mips helpers;
   c. In vicinity of changes, fixed not-beautiful code formatting.
   - Commit messages improved.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01232.html)

V1 - Initial version
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg06082.html)

Mips platform represents the most complex case among QEMU-supported
platforms in reference to certain aspects of floating-point arithmetics.
This is mostly a consequence of the fact that Mips platform, for many
reasons, evolved considerably over time related to floating-point
arithmetics standards (significantly more than other platforms).
It has been difficult for emulators like QEMU to support such variety
of configurations.

This patch series provides number of IEEE 754-2008-related features to
Mips platform. It addresses the most sensitive changes that require
modification of SoftFloat library, that is used by most other platforms.

In order to make develpoment, testing, and integration easier, the patch
is split into two distinct parts:

   1. Part 1 (patches 1/6, 2/6, 3/6) that does not change any calculation
  or behavior on any platform (and, for that matter, even on Mips
  platform). Its sole purpose is to address platform independant
  issues in a non-invasive manner, and to make Part 2 possible.

   2. Part 2 (patches 4/6, 5/6, 6/6) that sets some Mips architecures to
  use provisions from Part 1, and additionally implements some of
  IEEE 754-2008-relates features for Mips, but, at the same time,
  dealing with files located in directory target-mips only.

A limitation of this patch series is that it does not cover all IEEE 754-2008
Mips issues (for example, handling FCR31's FS bit, handling R3 architectures,
some gdb issues, ELF header nan2008-related changes). However, hopefully all
remaining such issues will touch only Mips-specific source code files, and
thus will be much easier to integrate in QEMU, and, of course, will not be
disruptive to orher platforms.

This patch series is based on the original set of patches proposed by Maciej W.
Rozycki: http://lists.nongnu.org/archive/html/qemu-devel/2014-12/msg00968.html

Aleksandar Markovic (6):
  softfloat: Implement run-time-configurable meaning of signaling NaN bit
  softfloat: For Mips only, correct default NaN values
  softfloat: For Mips only, correct order in pickNaNMulAdd()
  target-mips: Activate IEEE 274-2008 support
  target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>
  target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

 fpu/softfloat-specialize.h|  606 +
 fpu/softfloat.c   |  172 +---
 include/fpu/softfloat.h   |   45 +--
 target-alpha/cpu.c|2 +
 target-arm/helper-a64.c   |   14 +-
 target-arm/helper.c   |   40 +--
 target-m68k/helper.c  |6 +-
 target-microblaze/cpu.c   |2 +
 target-microblaze/op_helper.c |6 +-
 target-mips/helper.h  |   22 +-
 target-mips/msa_helper.c  |   96 ---
 target-mips/op_helper.c   |  350 ++--
 target-mips/translate.c   |  157 +--
 target-mips/translate_init.c  |   18 +-
 target-ppc/fpu_helper.c   |  120 
 target-ppc/translate_init.c   |2 +
 target-s390x/cpu.c|1 +
 target-s390x/fpu_helper.c |   28 +-
 target-s390x/helper.h |6 +-
 target-s390x/translate.c  |6 +-
 target-sh4/cpu.c  |1 +
 target-sparc/cpu.c|1 +
 target-tricore/helper.c   |1 +
 target-unicore32/cpu.c|2 +
 target-xtensa/cpu.c   |3 +
 25 files changed, 1078 insertions(+), 629 deletions(-)

-- 
1.7.9.5

[Qemu-devel] [PATCH v3 5/6] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Updated handling of instuctions <ABS|NEG>.<S|D>. Note that legacy
(pre-abs2008) ABS and NEG instructions are arithmetic (any NaN operand
signals invalid operation), while abs2008 ones are non-arithmetic, always
changing the sign bit, even for NaN-like operands. Details on these
kxinstructions are documented in [1], pages 35 and 359.

[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/translate.c |   27 +++
 1 file changed, 23 insertions(+), 4 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index de0b224..1d376fc 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1434,6 +1434,8 @@ typedef struct DisasContext {
 bool vp;
 bool cmgcr;
 bool mrp;
+bool abs2008;
+
 } DisasContext;
 
 enum {
@@ -8879,7 +8881,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i32 fp0 = tcg_temp_new_i32();
 
 gen_load_fpr32(ctx, fp0, fs);
-gen_helper_float_abs_s(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_andi_i32(fp0, fp0, 0x7fffUL);
+} else {
+gen_helper_float_abs_s(fp0, fp0);
+}
 gen_store_fpr32(ctx, fp0, fd);
 tcg_temp_free_i32(fp0);
 }
@@ -8898,7 +8904,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i32 fp0 = tcg_temp_new_i32();
 
 gen_load_fpr32(ctx, fp0, fs);
-gen_helper_float_chs_s(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_xori_i32(fp0, fp0, 1UL << 31);
+} else {
+gen_helper_float_chs_s(fp0, fp0);
+}
 gen_store_fpr32(ctx, fp0, fd);
 tcg_temp_free_i32(fp0);
 }
@@ -9369,7 +9379,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i64 fp0 = tcg_temp_new_i64();
 
 gen_load_fpr64(ctx, fp0, fs);
-gen_helper_float_abs_d(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_andi_i64(fp0, fp0, 0x7fffULL);
+} else {
+gen_helper_float_abs_d(fp0, fp0);
+}
 gen_store_fpr64(ctx, fp0, fd);
 tcg_temp_free_i64(fp0);
 }
@@ -9390,7 +9404,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i64 fp0 = tcg_temp_new_i64();
 
 gen_load_fpr64(ctx, fp0, fs);
-gen_helper_float_chs_d(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_xori_i64(fp0, fp0, 1ULL << 63);
+} else {
+gen_helper_float_chs_d(fp0, fp0);
+}
 gen_store_fpr64(ctx, fp0, fd);
 tcg_temp_free_i64(fp0);
 }
@@ -19775,6 +19793,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct 
TranslationBlock *tb)
  (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
 ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
 ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
+ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
 restore_cpu_state(env, );
 #ifdef CONFIG_USER_ONLY
 ctx.mem_idx = MIPS_HFLAG_UM;
-- 
1.7.9.5

[Qemu-devel] [PATCH v3 3/6] softfloat: For Mips only, correct order in pickNaNMulAdd()

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Only for Mips platform, and only for cases when snan_bit_is_one is 0,
correct the order of argument comparisons in pickNaNMulAdd().

For more info, see [2], page 53, section "3.5.3 NaN Propagation".

[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

[2] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32® SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 fpu/softfloat-specialize.h |   41 +
 1 file changed, 29 insertions(+), 12 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 169246e..807ecc0 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -569,19 +569,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag 
bIsQNaN, flag bIsSNaN,
 return 3;
 }
 
-/* Prefer sNaN over qNaN, in the c, a, b order. */
-if (cIsSNaN) {
-return 2;
-} else if (aIsSNaN) {
-return 0;
-} else if (bIsSNaN) {
-return 1;
-} else if (cIsQNaN) {
-return 2;
-} else if (aIsQNaN) {
-return 0;
+if (status->snan_bit_is_one) {
+/* Prefer sNaN over qNaN, in the a, b, c order. */
+if (aIsSNaN) {
+return 0;
+} else if (bIsSNaN) {
+return 1;
+} else if (cIsSNaN) {
+return 2;
+} else if (aIsQNaN) {
+return 0;
+} else if (bIsQNaN) {
+return 1;
+} else {
+return 2;
+}
 } else {
-return 1;
+/* Prefer sNaN over qNaN, in the c, a, b order. */
+if (cIsSNaN) {
+return 2;
+} else if (aIsSNaN) {
+return 0;
+} else if (bIsSNaN) {
+return 1;
+} else if (cIsQNaN) {
+return 2;
+} else if (aIsQNaN) {
+return 0;
+} else {
+return 1;
+}
 }
 }
 #elif defined(TARGET_PPC)
-- 
1.7.9.5

[Qemu-devel] [PATCH v3 4/6] target-mips: Activate IEEE 274-2008 support

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

1) Definitions of Mips processors are updated to reflect supported
   IEEE-754-2008-related features. (file target-mips/translate_init.c)

2) Functions mips_cpu_reset() and msa_reset() are updated so that flag
   snan_bit_is_one is properly set for any Mips configuration.
   (file target-mips/translate_init.c)

Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/translate.c  |6 +-
 target-mips/translate_init.c |   18 +++---
 2 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 496216d..de0b224 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -20129,7 +20129,11 @@ void cpu_state_reset(CPUMIPSState *env)
 env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
 env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
 env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
-set_snan_bit_is_one(1, >active_fpu.fp_status);
+if ((env->active_fpu.fcr31 >> FCR31_NAN2008) & 1) {
+set_snan_bit_is_one(0, >active_fpu.fp_status);
+} else {
+set_snan_bit_is_one(1, >active_fpu.fp_status);
+}
 env->msair = env->cpu_model->MSAIR;
 env->insn_flags = env->cpu_model->insn_flags;
 
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index e81a831..878fef6 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -273,6 +273,7 @@ static const mips_def_t mips_defs[] =
 .CP0_Status_rw_bitmask = 0x3678FF1F,
 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+.CP1_fcr31 = 0,
 .SEGBITS = 32,
 .PABITS = 32,
 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
@@ -303,6 +304,7 @@ static const mips_def_t mips_defs[] =
 (0xff << CP0TCSt_TASID),
 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
+.CP1_fcr31 = 0,
 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
 .CP0_SRSConf0_rw_bitmask = 0x3fff,
 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
@@ -343,6 +345,7 @@ static const mips_def_t mips_defs[] =
 .CP0_Status_rw_bitmask = 0x3778FF1F,
 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+.CP1_fcr31 = 0,
 .SEGBITS = 32,
 .PABITS = 32,
 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
@@ -434,7 +437,7 @@ static const mips_def_t mips_defs[] =
 },
 {
 /* A generic CPU supporting MIPS32 Release 6 ISA.
-   FIXME: Support IEEE 754-2008 FP.
+   FIXME: Complete support for IEEE 754-2008 FP.
   Eventually this should be replaced by a real CPU model. */
 .name = "mips32r6-generic",
 .CP0_PRid = 0x0001,
@@ -485,6 +488,7 @@ static const mips_def_t mips_defs[] =
 .CP0_Status_rw_bitmask = 0x3678,
 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
+.CP1_fcr31 = 0,
 .SEGBITS = 40,
 .PABITS = 36,
 .insn_flags = CPU_MIPS3,
@@ -503,6 +507,7 @@ static const mips_def_t mips_defs[] =
 .CP0_Status_rw_bitmask = 0x3678,
 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
+.CP1_fcr31 = 0,
 .SEGBITS = 40,
 .PABITS = 32,
 .insn_flags = CPU_VR54XX,
@@ -548,6 +553,7 @@ static const mips_def_t mips_defs[] =
 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
+.CP1_fcr31 = 0,
 .SEGBITS = 42,
 .PABITS = 36,
 .insn_flags = CPU_MIPS64,
@@ -575,6 +581,7 @@ static const mips_def_t mips_defs[] =
 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
 (1 << FCR0_D) | (1 << FCR0_S) |
 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
+.CP1_fcr31 = 0,
 .SEGBITS = 40,
 .PABITS = 36,
 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
@@ -601,6 +608,7 @@ static const mips_def_t mips_defs[] =
 .CP1_fcr0 = (1

[Qemu-devel] [PATCH v3 2/6] softfloat: For Mips only, correct default NaN values

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Only for Mips platform, and only for cases when snan_bit_is_one is 0,
correct default NaN values (in their 16-, 32-, and 64-bit flavors).

For more info, see [1], page 84, Table 6.3 "Value Supplied When
a New Quiet NaN Is Created", and [2], page 52, table 3.7 "Default
NaN Encodings".

[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

[2] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32® SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 fpu/softfloat-specialize.h |   12 
 1 file changed, 12 insertions(+)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 53dae9b..169246e 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -97,7 +97,11 @@ float16 float16_default_nan(float_status *status)
 if (status->snan_bit_is_one) {
 return const_float16(0x7DFF);
 } else {
+#if defined(TARGET_MIPS)
+return const_float16(0x7E00);
+#else
 return const_float16(0xFE00);
+#endif
 }
 #endif
 }
@@ -116,7 +120,11 @@ float32 float32_default_nan(float_status *status)
 if (status->snan_bit_is_one) {
 return const_float32(0x7FBF);
 } else {
+#if defined(TARGET_MIPS)
+return const_float32(0x7FC0);
+#else
 return const_float32(0xFFC0);
+#endif
 }
 #endif
 }
@@ -135,7 +143,11 @@ float64 float64_default_nan(float_status *status)
 if (status->snan_bit_is_one) {
 return const_float64(LIT64( 0x7FF7 ));
 } else {
+#if defined(TARGET_MIPS)
+return const_float64(LIT64( 0x7FF8 ));
+#else
 return const_float64(LIT64( 0xFFF8 ));
+#endif
 }
 #endif
 }
-- 
1.7.9.5

[Qemu-devel] [PATCH v3 1/6] softfloat: Implement run-time-configurable meaning of signaling NaN bit

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch modifies SoftFloat library so that it can be configured in
run-time in relation to the meaning of signaling NaN bit, while, at the
same time, strictly preserving its behavior on all existing platforms.

Background:

In floating-point calculations, there is a need for denoting undefined or
unrepresentable values. This is achieved by defining certain floating-point
numerical values to be NaNs (which stands for "not a number"). For additional
reasons, virtually all modern floating-point unit implementations use two
kinds of NaNs: quiet and signaling. The binary representations of these two
kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally,
the first bit of mantissa).

Up to 2008, standards for floating-point did not specify all details about
binary representation of NaNs. More specifically, the meaning of the bit
that is used for distinguishing between signaling and quiet NaNs was not
strictly prescribed. (IEEE 754-2008 was the first floating-point standard
that defined that meaning clearly, see [1], p. 35) As a result, different
platforms took different approaches, and that presented considerable
challenge for multi-platform emulators like QEMU.

Mips platform represents the most complex case among QEMU-supported
platforms regarding signaling NaN bit. Up to the Release 6 of Mips
architecture, "1" in signaling NaN bit denoted signaling NaN, which is
opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
that, Mips architecture for SIMD (also known as MSA, or vector instructions)
also specifies signaling bit in accordance to IEEE standard. MSA unit can be
implemented with both pre-Release 6 and Release 6 main processor units.

QEMU uses SoftFloat library to implement various floating-point-related
instructions on all platforms. The current QEMU implementation allows for
defining meaning of signaling NaN bit during build time, and is implemented
via preprocessor macro called SNAN_BIT_IS_ONE.

On the other hand, the change in this patch enables SoftFloat library to be
configured in run-time. This configuration is meant to occur during CPU
initialization, at the moment when it is definitely known what desired
behavior for particular CPU (or any additional FPUs) is.

The change is implemented so that it is consistent with existing
implementation of similar cases. This means that structure float_status is
used for passing the information about desired signaling NaN bit on each
invocation of SoftFloat functions. The additional field in float_status is
called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.

IMPORTANT:

This change is not meant to create any change in emulator behavior or
functionality on any platform. It just provides the means for SoftFloat
library to be used in a more flexible way - in other words, it will just
prepare SoftFloat library for usage related to Mips platform and its
specifics regarding signaling bit meaning, which is done in the next patch.

Further break down of changes:

  1) Added field snan_bit_is_one to the structure float_status, and
 correspondent setter function set_snan_bit_is_one().

  2) Constants <float16|float32|float64|floatx80|float128>_default_nan
 (used both internally and externally) converted to functions
 <float16|float32|float64|floatx80|float128>_default_nan(float_status*).
 This is necessary since they are dependent on signaling bit meaning.
 At the same time, for the sake of code cleanup and simplicity, constants
 <floatx80|float128>_default_nan_<low|high> (used only internally within
 SoftFloat library) are removed, as not needed.

  3) Added a float_status* argument to SoftFloat library functions
 XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
 XXX_maybe_silence_nan(XXX a_). This argument must be present in
 order to enable correct invocation of new version of functions
 XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128>
 here)

  4) Updated code for all platforms to reflect changes in SoftFloat library.
 This change is twofolds: it includes modifications of SoftFloat library
 functions invocations, and an addition of invocation of function
 set_snan_bit_is_one() during CPU initialization, with arguments that
 are appropriate for each particular platform.

 In order to be at the same time accurate in relation to floating point
 arithmetics and consistent with a particular platform code, following
 principle is adopted related to invocations of new function
 set_snan_bit_is_one():

 1. If a target platform doesn't use SoftFloat library, nothing is added.
(cris, lm32, moxie)
 2. Else, if a target platform's signaling bit meaning is "1 is
signaling", ex

[Qemu-devel] [PATCH v3 6/6] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

New set of helpers for handling nan2008-syle versions of instructions
<CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>. Details on these instructions
are presented in [1], pages 129, 130, 149, 155, 222, 223, 393, 394, 504,
505.

[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/helper.h|   18 +--
 target-mips/op_helper.c |  334 ---
 target-mips/translate.c |  123 ++---
 3 files changed, 426 insertions(+), 49 deletions(-)

diff --git a/target-mips/helper.h b/target-mips/helper.h
index 133dcfb..61bbda7 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -207,8 +207,6 @@ DEF_HELPER_4(ctc1, void, env, tl, i32, i32)
 DEF_HELPER_2(float_cvtd_s, i64, env, i32)
 DEF_HELPER_2(float_cvtd_w, i64, env, i32)
 DEF_HELPER_2(float_cvtd_l, i64, env, i64)
-DEF_HELPER_2(float_cvtl_d, i64, env, i64)
-DEF_HELPER_2(float_cvtl_s, i64, env, i32)
 DEF_HELPER_2(float_cvtps_pw, i64, env, i64)
 DEF_HELPER_2(float_cvtpw_ps, i64, env, i64)
 DEF_HELPER_2(float_cvts_d, i32, env, i64)
@@ -216,8 +214,6 @@ DEF_HELPER_2(float_cvts_w, i32, env, i32)
 DEF_HELPER_2(float_cvts_l, i32, env, i64)
 DEF_HELPER_2(float_cvts_pl, i32, env, i32)
 DEF_HELPER_2(float_cvts_pu, i32, env, i32)
-DEF_HELPER_2(float_cvtw_s, i32, env, i32)
-DEF_HELPER_2(float_cvtw_d, i32, env, i64)
 
 DEF_HELPER_3(float_addr_ps, i64, env, i64, i64)
 DEF_HELPER_3(float_mulr_ps, i64, env, i64, i64)
@@ -242,14 +238,20 @@ FOP_PROTO(mina)
 #undef FOP_PROTO
 
 #define FOP_PROTO(op)\
-DEF_HELPER_2(float_ ## op ## l_s, i64, env, i32) \
-DEF_HELPER_2(float_ ## op ## l_d, i64, env, i64) \
-DEF_HELPER_2(float_ ## op ## w_s, i32, env, i32) \
-DEF_HELPER_2(float_ ## op ## w_d, i32, env, i64)
+DEF_HELPER_2(float_ ## op ## _l_s, i64, env, i32) \
+DEF_HELPER_2(float_ ## op ## _l_d, i64, env, i64) \
+DEF_HELPER_2(float_ ## op ## _w_s, i32, env, i32) \
+DEF_HELPER_2(float_ ## op ## _w_d, i32, env, i64)
+FOP_PROTO(cvt)
 FOP_PROTO(round)
 FOP_PROTO(trunc)
 FOP_PROTO(ceil)
 FOP_PROTO(floor)
+FOP_PROTO(cvt_2008)
+FOP_PROTO(round_2008)
+FOP_PROTO(trunc_2008)
+FOP_PROTO(ceil_2008)
+FOP_PROTO(floor_2008)
 #undef FOP_PROTO
 
 #define FOP_PROTO(op)\
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index ce7ec9c..841f066 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2448,9 +2448,19 @@ void mips_cpu_unassigned_access(CPUState *cs, hwaddr 
addr,
 
 #define FLOAT_TWO32 make_float32(1 << 30)
 #define FLOAT_TWO64 make_float64(1ULL << 62)
+
 #define FP_TO_INT32_OVERFLOW 0x7fff
 #define FP_TO_INT64_OVERFLOW 0x7fffULL
 
+#define FLT_TO_INT32_OVERFLOW(x) \
+float32_is_any_nan(x) ? 0 : (float32_is_neg(x) ? INT32_MIN : INT32_MAX)
+#define FLT_TO_INT64_OVERFLOW(x) \
+float32_is_any_nan(x) ? 0 : (float32_is_neg(x) ? INT64_MIN : INT64_MAX)
+#define DBL_TO_INT32_OVERFLOW(x) \
+float64_is_any_nan(x) ? 0 : (float64_is_neg(x) ? INT32_MIN : INT32_MAX)
+#define DBL_TO_INT64_OVERFLOW(x) \
+float64_is_any_nan(x) ? 0 : (float64_is_neg(x) ? INT64_MIN : INT64_MAX)
+
 /* convert MIPS rounding mode in FCR31 to IEEE library */
 unsigned int ieee_rm[] = {
 float_round_nearest_even,
@@ -2683,7 +2693,7 @@ uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t 
dt0)
 return fdt2;
 }
 
-uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
+uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
 {
 uint64_t dt2;
 
@@ -2696,7 +2706,7 @@ uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t 
fdt0)
 return dt2;
 }
 
-uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
+uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
 {
 uint64_t dt2;
 
@@ -2791,7 +2801,7 @@ uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t 
wth0)
 return wt2;
 }
 
-uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
+uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
 {
 uint32_t wt2;
 
@@ -2804,7 +2814,7 @@ uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t 
fst0)
 return wt2;
 }
 
-uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
+uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
 {
 uint32_t wt2;
 
@@ -2817,7 +2827,7 @@ uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t 
fdt0)
 return wt2;
 }
 
-uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
+uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
 {

[Qemu-devel] [PATCH 1/2] softfloat: Enable run-time-configurable meaning of signaling NaN bit

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch enables SoftFloat library to be configured at run-time in
relation to the meaning of signaling NaN bit.

Background:

In floating-point calculations, there is a need for denoting undefined or
unrepresentable values. This is achieved by defining certain floating-point
numerical values to be NaNs (which stands for "not a number"). For additional
reasons, virtually all modern floating-point unit implementations use two
kinds of NaNs: quiet and signaling. The binary representations of these two
kinds of NaNs, as a rule, differ only in one bit (it is traditionally,
the first bit of mantissa).

Up to 2008, standards for floating-point did not specify all details about
binary representation of NaNs. More specifically, the meaning of the bit
that is used for distinguishing between signaling and quiet NaNs was not
strictly prescribed. (IEEE 754-2008 was the first floating-point standard
that defined that meaning clearly, see [1], p. 35) As a result, different
platforms took different approaches, and this presented certain challenge
in emulators like QEMU.

Mips architecture represent the most complex case among QEMU-supported
architectures regarding signaling NaN bit. Up to Release 6 of Mips
architecture, "1" in signaling NaN bit denoted signaling NaN, which is
opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
that, Mips architecture for SIMD (also known as MSA, or vector instructions)
also specifies signaling bit in accordance to IEEE standard. MSA unit can be
implemented with both pre-Release 6 and Release 6 main processor units.

QEMU uses SoftFloat library to implement various floating-point-related
instructions on all platforms. The current implementation allows for defining
meaning of signaling NaN bit during build time, and is implemented via
preprocessor macro called SNAN_BIT_IS_ONE.

The change in this patch enables SoftFloat library to be configured in
run-time. This configuration is meant to occur during CPU initialization,
when it is definitely known what desired behavior for particular CPU
(or any additional FPUs) is.

The change is implemented so that it is consistent with existing
implementation of similar cases. This means that structure float_status is
used for passing the information about desired signaling NaN bit during each
invocation of SoftFloat functions. The additional field in float_status is
called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.

Further break down of changes:

  (for the sake of brevity, a placeholder XXX is used below and it might
  mean float16, float32, float64, floatx80, or float128)

  1) Added field snan_bit_is_one to the structure float_status,
 and the correspondent setter function set_snan_bit_is_one().

  2) SoftFloat library constants XXX_default_nan converted to functions
 XXX_default_nan(float_status*). This is necessary since they are
 dependant on signaling bit meaning.

  3) Added a float_status* argument to SoftFloat library functions
 XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
 XXX_maybe_silence_nan(XXX a_).

  4) Updated code in all architectures to reflect changes in SoftFloat
 library. This change is twofolds: it includes modification of SoftFloat
 library functions invocations, and addition of invocations of function
 set_snan_bit_is_one() during CPU initialization, with arguments that
 are appropriate for each architecture.

IMPORTANT:

This change is not meant to create any change in emulator behavior or
functionality on any platform. It just provides the means for SoftFloat
library to be used in a more flexible way - in other words, it will just
prepare SoftFloat library for usage related to Mips platform and its
specifics regarding signaling bit meaning, which is done in the next patch.

[1] "IEEE Standard for Floating-Point Arithmetic",
IEEE Computer Society, August 29, 2008.
(http://www.csee.umbc.edu/~tsimo1/CMSC455/IEEE-754-2008.pdf)

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 fpu/softfloat-specialize.h| 546 +-
 fpu/softfloat.c   | 170 +++--
 include/fpu/softfloat.h   |  49 ++--
 target-alpha/cpu.c|   2 +
 target-arm/cpu.c  |   2 +
 target-arm/helper-a64.c   |  14 +-
 target-arm/helper.c   |  40 ++--
 target-i386/cpu.c |   4 +
 target-m68k/cpu.c |   2 +
 target-m68k/helper.c  |   6 +-
 target-microblaze/cpu.c   |   2 +
 target-microblaze/op_helper.c |   6 +-
 target-mips/helper.h  |   4 +-
 target-mips/msa_helper.c  |  96 
 target-mips/op_helper.c   |  13 +-
 target-mips/translate.c   |   4 +-
 target-mips/translate_init.c  |   6 +-
 target-openrisc/cpu.c 

[Qemu-devel] [PATCH 2/2] target-mips: Implement IEEE 754-2008 functionality for R6 and MSA instructions

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch utilizes provisions from the previous patch, and configures
Mips R6 CPUs and Mips MSA units appropriately with reference to the meaning
of the signaling NaN bit (this is mentioned in point 3 in the list below).
The majority of involved MIPS instructions will be fixed just with that
change. Certain number of other IEEE 754-2008 standard-related MIPS issues
are addreessed with this patch as well.

The changes can be summarized this way:

1) Definitions of Mips processors are updated to reflect supported
   IEEE-754-2008-related features. (file target-mips/translate_init.c)

2) Functions fpu_init() and msa_reset() are updated so that flag
   snan_bit_is_one is properly set for any Mips configuration.
   (file target-mips/translate_init.c)

3) Helpers helper_float_abs_() and helper_float_chs_() are
   rewritten to reflect new behavior of instructions ABS.fmt and NEG.fmt
   in MIPS Release 6. Affected MIPS instructions are:

   ABS.S
   ABS.D
   NEG.S
   NEG.D

   Note that legacy (pre-R6) ABS and NEG instructions are arithmetic
   (any NaN operand signals invalid operation), while R6 ones are
   non-arithmetic, always changing the sign bit, even for NaN-like operands.

   Details on these instructions are documented in [1] p. 35 and 359.

   Affected files are target-mips/helper.h and target-mips/op_helper.c.

4) Helpers helper_float_ceilxxx(), helper_float_cvtxxx(),
   helper_float_floorxxx(), helper_float_roundxxx(), and
   helper_float_truncxxx() are rewritten to reflect the behavior of
   relevant instructions if its operands are floating numbers out of
   the range of the integer destination.

   Affected MIPS instructions are:

   CEIL.L.fmt
   CEIL.W.fmt
   CVT.L.fmt
   CVT.W.fmt
   FLOOR.L.fmt
   FLOOR.W.fmt
   ROUND.L.fmt
   ROUND.W.fmt
   TRUNC.L.fmt
   TRUNC.W.fmt

   Details on these instructions are presented in [1] p. 129, 130, 149,
   155, 222, 223, 393, 394, 504, 505.

   Affected files are target-mips/helper.h and target-mips/translate.c.

5) Helpers helper_msa_class_s() and helper_msa_class_d() added so that
   MSA version of instruction CLASS can operate independently of the one
   from the base set of instructions. Affected MIPS instructions are:

   FCLASS.W
   FCLASS.D

   Details on these instructions can be found in [2] p. 158.

   Affected source code files are target-mips/helper.h and
   target-mips/msa_helper.c.

6) Handling og instructions CVT.S.PU and CVT.S.PL is updated to reflect
   the fact that they are removed in Mips R6 architecture and belong to
   so-called paired-single class of instructions. Details on these
   instructions can be found in [1], p. 152 and 153. Affected source
   code file is target-mips/translate.c.

[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015
(https://imagination-technologies-cloudfront-assets.s3.amazonaws.com/
 documentation/MD00087-2B-MIPS64BIS-AFP-06.04.pdf)

[2] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32® SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016
(https://imagination-technologies-cloudfront-assets.s3.amazonaws.com/
 documentation/MD00866-2B-MSA32-AFP-01.12.pdf)

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/helper.h |  10 +-
 target-mips/msa_helper.c |  60 -
 target-mips/op_helper.c  | 516 ---
 target-mips/translate.c  |  16 +-
 target-mips/translate_init.c |  22 +-
 5 files changed, 520 insertions(+), 104 deletions(-)

diff --git a/target-mips/helper.h b/target-mips/helper.h
index 1aaa316..952af63 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -254,10 +254,10 @@ FOP_PROTO(recip)
 FOP_PROTO(rint)
 #undef FOP_PROTO
 
-#define FOP_PROTO(op)   \
-DEF_HELPER_1(float_ ## op ## _s, i32, i32)  \
-DEF_HELPER_1(float_ ## op ## _d, i64, i64)  \
-DEF_HELPER_1(float_ ## op ## _ps, i64, i64)
+#define FOP_PROTO(op)\
+DEF_HELPER_2(float_ ## op ## _s, i32, env, i32)  \
+DEF_HELPER_2(float_ ## op ## _d, i64, env, i64)  \
+DEF_HELPER_2(float_ ## op ## _ps, i64, env, i64)
 FOP_PROTO(abs)
 FOP_PROTO(chs)
 #undef FOP_PROTO
@@ -924,6 +924,8 @@ DEF_HELPER_4(msa_pcnt_df, void, env, i32, i32, i32)
 DEF_HELPER_4(msa_nloc_df, void, env, i32, i32, i32)
 DEF_HELPER_4(msa_nlzc_df, void, env, i32, i32, i32)
 
+DEF_HELPER_2(msa_class_s, i32, env, i32)
+DEF_HELPER_2(msa_class_d, i64, env, i64)
 DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32)
 DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32)
 DEF_HELPER_4(msa_ftrunc_u_df, void, env, i32, i32, i32)
diff --git a/target-mips/msa_helper.c b/target-mips/msa_helper.c
index 47fbba0..fed430d 100644
--- a/target-mips/msa_helper.c
+++ b/target-mips/m

[Qemu-devel] [PATCH 0/2] target-mips: Fix IEEE 754-2008-related issues

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Mips platform represents the most complex case among QEMU-supported
platforms in reference to certain aspects of floating-point arithmetics.
This is mostly a consequence of the fact that Mips platform, for many
reasons, evolved considerably over time related to floating-point
arithmetics standards (significantly more than other platforms).
It has been difficult for emulators like QEMU to support such variety
of configurations.

This patch set provides solution to this problem, and furnishes
accurate emulation of floating-point arithmetics for all Mips cases.

Aleksandar Markovic (2):
  softfloat: Enable run-time-configurable meaning of signaling NaN bit
  target-mips: Implement IEEE 754-2008 functionality for R6 and MSA
instructions

 fpu/softfloat-specialize.h| 546 +-
 fpu/softfloat.c   | 170 +++--
 include/fpu/softfloat.h   |  49 ++--
 target-alpha/cpu.c|   2 +
 target-arm/cpu.c  |   2 +
 target-arm/helper-a64.c   |  14 +-
 target-arm/helper.c   |  40 ++--
 target-i386/cpu.c |   4 +
 target-m68k/cpu.c |   2 +
 target-m68k/helper.c  |   6 +-
 target-microblaze/cpu.c   |   2 +
 target-microblaze/op_helper.c |   6 +-
 target-mips/helper.h  |  14 +-
 target-mips/msa_helper.c  | 144 +++
 target-mips/op_helper.c   | 527 +---
 target-mips/translate.c   |  20 +-
 target-mips/translate_init.c  |  24 +-
 target-openrisc/cpu.c |   2 +
 target-ppc/fpu_helper.c   | 120 +-
 target-ppc/translate_init.c   |   2 +
 target-s390x/cpu.c|   1 +
 target-s390x/fpu_helper.c |  28 ++-
 target-s390x/helper.h |   6 +-
 target-s390x/translate.c  |   6 +-
 target-sh4/cpu.c  |   1 +
 target-sparc/cpu.c|   1 +
 target-tricore/helper.c   |   1 +
 target-unicore32/cpu.c|   1 +
 target-xtensa/cpu.c   |   3 +
 29 files changed, 1119 insertions(+), 625 deletions(-)

-- 
1.9.1

Re: [Qemu-devel] [PATCH 1/2] softfloat: Enable run-time-configurable meaning of signaling NaN bit

[Aleksandar Markovic]

I truly appreciate your guidance and bringing this matter to my attention.

It just seems to me that, in similar case, 16-bit default NaN value should be 
0x7E00. This value is needed for MSA operations. ("MIPS Architecture for 
Programmers Volume IV-j: The MIPS32® SIMD Architecture Module", Revision 1.12, 
(february 3, 2016), page 52, table 3.7 "Default NaN Encodings")

I plan to include all three corrections in the next version of this patch set. 
Please, let me know if you think that I should not.

Yours,
Aleksandar




From: qemu-devel-bounces+aleksandar.markovic=imgtec@nongnu.org 
[qemu-devel-bounces+aleksandar.markovic=imgtec@nongnu.org] on behalf of 
Leon Alrae
Sent: Friday, April 01, 2016 12:02 PM
To: Aleksandar Markovic; qemu-devel@nongnu.org
Cc: peter.mayd...@linaro.org; ehabk...@redhat.com; pro...@gmail.com; 
mark.cave-ayl...@ilande.co.uk; ag...@suse.de; kbast...@mail.uni-paderborn.de; 
Petar Jovanovic; blauwir...@gmail.com; jcmvb...@gmail.com; Miodrag Dinic; 
qemu-...@nongnu.org; qemu-...@nongnu.org; edgar.igles...@gmail.com; 
pbonz...@redhat.com; g...@mprc.pku.edu.cn; afaer...@suse.de; 
aurel...@aurel32.net; r...@twiddle.net
Subject: Re: [Qemu-devel] [PATCH 1/2] softfloat: Enable run-time-configurable 
meaning of signaling NaN bit

On 25/03/16 12:50, Aleksandar Markovic wrote:
>  
> /*
>  | The pattern for a default generated single-precision NaN.
>  
> **/
> +float32 float32_default_nan(float_status *status) {
>  #if defined(TARGET_SPARC)
> -const float32 float32_default_nan = const_float32(0x7FFF);
> +return const_float32(0x7FFF);
>  #elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || 
> \
>defined(TARGET_XTENSA) || defined(TARGET_S390X) || 
> defined(TARGET_TRICORE)
> -const float32 float32_default_nan = const_float32(0x7FC0);
> -#elif SNAN_BIT_IS_ONE
> -const float32 float32_default_nan = const_float32(0x7FBF);
> +return const_float32(0x7FC0);
>  #else
> -const float32 float32_default_nan = const_float32(0xFFC0);
> +if (status->snan_bit_is_one)
> +return const_float32(0x7FBF);
> +else
> +return const_float32(0xFFC0);

Here for MIPS (when FCR31.NAN2008 is set) we should generate 0x7FC0
for single-precision. Reference:
"MIPS Architecture For Programmers, Volume I-A: Introduction to the
MIPS64 Architecture", Imagination Technologies LTD., Document Number:
MD00083, Revision 6.01, August 20, 2014, Table 6.3 "Value Supplied When
a New Quiet NaN Is Created", p. 84

Also, for double-precision we should generate 0x7FF8.

Thanks,
Leon

Re: [Qemu-devel] [PATCH 2/2] target-mips: Implement IEEE 754-2008 functionality for R6 and MSA instructions

[Aleksandar Markovic]

Hello, Leon, thank you very much for the kind feedback. Let me clarify my take 
on the involved issues.

1) Class operations

I am going to correct the code as you hinted.

The reason I wanted separate handling of MSA class operation is code and module 
decoupling. Handling of MSA instructions (in file msa_helper.c) and regular 
instructions (in file op_helper.c) have many overlaping areas - however, my 
understanding is that the designer of MSA module wanted it to be as independant 
on code in other files/modulas as possible. Handling class operation is on of 
the rare instances where code in msa_helper.c relies on the code in 
op_helper.c., and it made sense to me that this dependence should be removed, 
for the sake of consistency within MSA module - even if the functionalitied are 
virtually identical. That said, I will anyway listen to your advice, since you 
most probably see more than myself regarding this, and I am going to revert to 
a single handling of class operations, for both MSA and regular versions.

2) Flush subnormals

My impression is that his set of features should be treated and implemented 
separately, at some later point in time.

Although the implementation seems not to be too complex (defining FCR31_FS, 
invoking appropriately set_flush_to_zero() and set_flush_inputs_to_zero() on 
CPU init, plus special exception handling, like it is already done for MSA 
equivalents), it looks to me that it would have added a lot of risk into a 
patch series that is already touching a lot of sensitive areas, and therefore 
introducing a lot of risks. Once this patch series is hopefully intergrated, 
flush subnormals will be much easier to integrate, since it will be mips-only 
issue. Therefore, if you agree, I will leave it for the future. I will 
definitely mention it in commit messages though (as a limitaion), for future 
reference.

Thanks again for your consideration of this matter.

Sincerely yours,
Aleksandar


 Original Message 
Subject: Re: [PATCH 2/2] target-mips: Implement IEEE 754-2008 functionality for 
R6 and MSA instructions
Date: Friday, April 1, 2016 21:07 CEST
From: Leon Alrae <leon.al...@imgtec.com>
To: Aleksandar Markovic <aleksandar.marko...@rt-rk.com>,<qemu-devel@nongnu.org>
CC: <qemu-...@nongnu.org>, <qemu-...@nongnu.org>, 
<aurel...@aurel32.net>,<peter.mayd...@linaro.org>, <r...@twiddle.net>, 
<afaer...@suse.de>,<pbonz...@redhat.com>, <ehabk...@redhat.com>, 
<edgar.igles...@gmail.com>,<pro...@gmail.com>, <ag...@suse.de>, 
<blauwir...@gmail.com>,<mark.cave-ayl...@ilande.co.uk>, 
<g...@mprc.pku.edu.cn>,<petar.jovano...@imgtec.com>, 
<miodrag.di...@imgtec.com>,<jcmvb...@gmail.com>, 
<kbast...@mail.uni-paderborn.de>
References: 
<1458910214-12239-1-git-send-email-aleksandar.marko...@rt-rk.com><1458910214-12239-3-git-send-email-aleksandar.marko...@rt-rk.com>


 On 25/03/16 12:50, Aleksandar Markovic wrote:
> +#define MSA_CLASS_SIGNALING_NAN 0x001
> +#define MSA_CLASS_QUIET_NAN 0x002
> +#define MSA_CLASS_NEGATIVE_INFINITY 0x004
> +#define MSA_CLASS_NEGATIVE_NORMAL 0x008
> +#define MSA_CLASS_NEGATIVE_SUBNORMAL 0x010
> +#define MSA_CLASS_NEGATIVE_ZERO 0x020
> +#define MSA_CLASS_POSITIVE_INFINITY 0x040
> +#define MSA_CLASS_POSITIVE_NORMAL 0x080
> +#define MSA_CLASS_POSITIVE_SUBNORMAL 0x100
> +#define MSA_CLASS_POSITIVE_ZERO 0x200
> +
> +#define MSA_CLASS(name, bits) \
> +uint ## bits ## _t helper_msa_ ## name (CPUMIPSState *env, \
> + uint ## bits ## _t arg) \
> +{ \
> + if (float ## bits ## _is_signaling_nan(arg, \
> + >active_tc.msa_fp_status)) { \
> + return MSA_CLASS_SIGNALING_NAN; \
> + } else if (float ## bits ## _is_quiet_nan(arg, \
> + >active_tc.msa_fp_status)) { \
> + return MSA_CLASS_QUIET_NAN; \
> + } else if (float ## bits ## _is_neg(arg)) { \
> + if (float ## bits ## _is_infinity(arg)) { \
> + return MSA_CLASS_NEGATIVE_INFINITY; \
> + } else if (float ## bits ## _is_zero(arg)) { \
> + return MSA_CLASS_NEGATIVE_ZERO; \
> + } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
> + return MSA_CLASS_NEGATIVE_SUBNORMAL; \
> + } else { \
> + return MSA_CLASS_NEGATIVE_NORMAL; \
> + } \
> + } else { \
> + if (float ## bits ## _is_infinity(arg)) { \
> + return MSA_CLASS_POSITIVE_INFINITY; \
> + } else if (float ## bits ## _is_zero(arg)) { \
> + return MSA_CLASS_POSITIVE_ZERO; \
> + } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
> + return MSA_CLASS_POSITIVE_SUBNORMAL; \
> + } else { \
> + return MSA_CLASS_POSITIVE_NORMAL; \
> + } \
> + } \
> +}

Duplicating the class operation is unnecessary. We can just have common
function for FPU and MSA which takes additional float_status argument.

Also I noticed that this patch series doesn't provide Flush Subnormals
(the FCSR.FS bit), but probably this functionality can come later...

Leon


 

Re: [Qemu-devel] [PATCH 1/2] softfloat: Enable run-time-configurable meaning of signaling NaN bit

[Aleksandar Markovic]

Hello, Richard.

I truly appreciate your guidance, it is of tremendous help to me.

I plan to address all issues you brought up in this mail in the V2 of my patch 
series.

All is clear to me, except some subtleties regarding initialization of 
platforms.
More specifically, for setting snan bit, I adopted this principle.

1. If target platform doesn't use SoftFloatLibrary, nothing is added.
  (cris, lm32, moxie)
2. Else, if target platform's signalling bit meaning is "1 is signalling",
   explicit invocation of set_snan_bit_is_one(1) is added.
  (mips, sh4, unicore32)
 (for mips this will change in the second patch of this series,
 but this very patch leaves mips features as they currently are.)
3. Else, if target platform explicitely sets other fields of its
   float_status structure(s), explicit invocation of
   set_snan_bit_is_one(0) is added.
  (arm, ppc, s390x, tricore)
4. Else, if target platform doesn't exlpcitely sets its structure CPUXXXState,
   explicit invocation of set_snan_bit_is_one(0) is added.
  (alpha, xtensa)
5. For remaining cases, nothing is added. (Those cases explicitely set
   their CPUXXXState to 0, and implicitly perform set_snan_bit_is_one(0).)
  (i386, m68k, microblaze, openrisc, sparc)

By platforms, this looks like following:

A. alpha - structure CPUAlphaState not explicitely set to 0s,
  explicit invocation of set_snan_bit_is_one(0) added
B. arm - explicitely sets other fields of float_status,
  explicit invocation of set_snan_bit_is_one(0) added
C. cris - does not use SoftFloat library, nothing added
D. i386 - structure CPUX86State explicitely set to 0s,
  nothing added (implicit set_snan_bit_is_one(0))
E. lm32 - does not use SoftFloat library, nothing added
F. m68k - structure CPUM68KState explicitely set to 0s,
  nothing added (implicit set_snan_bit_is_one(0))
G. microblaze - structure CPUMBState explicitely set to 0s,
  nothing added (implicit set_snan_bit_is_one(0))
H. mips - must explicitely invoke set_snan_bit_is_one(1)
I. moxie - does not use SoftFloat library, nothing added
J. openrisc - structure CPUOpenRISCState explicitely set to 0s,
  nothing added (implicit set_snan_bit_is_one(0))
K. ppc - explicitely sets other fields of float_status,
  explicit invocation of set_snan_bit_is_one(0) added
L. s390x - explicitely sets other fields of float_status,
  explicit invocation of set_snan_bit_is_one(0) added
M. sh4 - must explicitely invoke set_snan_bit_is_one(1)
N. sparc - structure CPUSPARCState explicitely set to 0s,
  nothing added (implicit set_snan_bit_is_one(0))
O. tricore - explicitely sets other fields of float_status,
  explicit invocation of set_snan_bit_is_one(0) added
P. unicore32 - must explicitely invoke set_snan_bit_is_one(1)
Q. xtensa - structure CPUXtensaState not explicitely set to 0s,
  explicit invocation of set_snan_bit_is_one(0) added

Does such approach look OK to you?

Feightfully yours,
Aleksandar




From: qemu-devel-bounces+aleksandar.markovic=imgtec@nongnu.org 
[qemu-devel-bounces+aleksandar.markovic=imgtec@nongnu.org] on behalf of 
Richard Henderson [r...@twiddle.net]
Sent: Monday, March 28, 2016 2:36 PM
To: Aleksandar Markovic; qemu-devel@nongnu.org
Cc: peter.mayd...@linaro.org; ehabk...@redhat.com; 
kbast...@mail.uni-paderborn.de; mark.cave-ayl...@ilande.co.uk; ag...@suse.de; 
Petar Jovanovic; blauwir...@gmail.com; jcmvb...@gmail.com; Miodrag Dinic; 
qemu-...@nongnu.org; qemu-...@nongnu.org; edgar.igles...@gmail.com; 
pbonz...@redhat.com; g...@mprc.pku.edu.cn; Leon Alrae; afaer...@suse.de; 
aurel...@aurel32.net; pro...@gmail.com
Subject: Re: [Qemu-devel] [PATCH 1/2] softfloat: Enable run-time-configurable 
meaning of signaling NaN bit

On 03/25/2016 05:50 AM, Aleksandar Markovic wrote:
> +float16 float16_default_nan(float_status *status) {

{ on the next line.

> +return const_float64(LIT64( 0xFFF8 ));

Let's please fix the horrible formatting in this file as we touch the lines,
please.

> -#define floatx80_default_nan_high 0x7FFF
> -#define floatx80_default_nan_low  LIT64(0xBFFF)
> -#else
> -#define floatx80_default_nan_high 0x
> -#define floatx80_default_nan_low  LIT64( 0xC000 )
> -#endif
> +uint16_t floatx80_default_nan_high(float_status *status) {
> +uint64_t floatx80_default_nan_low(float_status *status) {

Why do you need two separate functions for this?

> +floatx80 floatx80_default_nan(float_status *status) {

Seems to me this one is good enough, and indeed preferable.

> -#define float128_default_nan_high LIT64(0x7FFF7FFF)
> -#define float128_default_nan_low  LIT64(0x)
...
> +float128 float128_default_nan(float_status *status) {

Likewise.


> diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
> index 2eab060..1714387 100644
> --- a/target-alpha/cpu.c
> +++ b/targe

Re: [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit

[Aleksandar Markovic]

Hello, Eduardo,

I greatly appreciate your time spent on this matter and your unfailing 
attention to detail.

For Alpha and Xtensa, this is for sure, they will zero their CPU objects, as 
you hinted:

target-alpha/cpu.c:
  162  cpu_class = object_class_by_name(TYPE("ev67"));
  163  }
  164: cpu = ALPHA_CPU(object_new(object_class_get_name(cpu_class)));
  165  
  166  object_property_set_bool(OBJECT(cpu), true, "realized", NULL);

target-xtensa/helper.c:
  125  }
  126  
  127: cpu = XTENSA_CPU(object_new(object_class_get_name(oc)));
  128  env = >env;
  129  

So, I will remove their set_snan_bit_is_one(0) calls, as you suggested.

This leaves only ppc, s390x, and TriCore calling set_snan_bit_is_one(0) it this
patch series..

I'll take one more look at them tomorrow, and will get back to you.

Yours,
Aleksandar


From: Eduardo Habkost [ehabk...@redhat.com]
Sent: Tuesday, April 12, 2016 11:45 AM
To: Aleksandar Markovic
Cc: qemu-devel@nongnu.org; pro...@gmail.com; kbast...@mail.uni-paderborn.de; 
mark.cave-ayl...@ilande.co.uk; ag...@suse.de; Maciej Rozycki; Petar Jovanovic; 
blauwir...@gmail.com; jcmvb...@gmail.com; Aleksandar Markovic; 
qemu-...@nongnu.org; qemu-...@nongnu.org; edgar.igles...@gmail.com; Miodrag 
Dinic; pbonz...@redhat.com; g...@mprc.pku.edu.cn; Leon Alrae; afaer...@suse.de; 
aurel...@aurel32.net; r...@twiddle.net
Subject: Re: [Qemu-devel] [PATCH v4 1/9] softfloat: Implement 
run-time-configurable meaning of signaling NaN bit

On Tue, Apr 12, 2016 at 02:58:03PM +0200, Aleksandar Markovic wrote:
[...]
>   4) Updated code for all platforms to reflect changes in SoftFloat library.
>  This change is twofolds: it includes modifications of SoftFloat library
>  functions invocations, and an addition of invocation of function
>  set_snan_bit_is_one() during CPU initialization, with arguments that
>  are appropriate for each particular platform.
>
>  In order to be at the same time accurate in relation to floating point
>  arithmetics and consistent with a particular platform code, following
>  principle is adopted related to invocations of new function
>  set_snan_bit_is_one():
>
>  1. If a target platform doesn't use SoftFloat library, nothing is added.
> (cris, lm32, moxie)
>  2. Else, if a target platform's signaling bit meaning is "1 is
> signaling", explicit invocation of set_snan_bit_is_one(1) is added.
> (mips, sh4, unicore32)
>   (for mips this will change in the second patch of this
>   series, but this very patch leaves mips features as
>   they currently are.)
>  3. Else, if a target platform explicitly sets other fields of its
> float_status structure(s), explicit invocation of
> set_snan_bit_is_one(0) is added.
> (ppc, s390x, tricore)
>  4. Else, if a target platform doesn't explicitly set its structure
> CPUXXXState, explicit invocation of set_snan_bit_is_one(0) is added.
> (alpha, xtensa)

The CPU struct is zeroed by object_new() when the CPU object is
created, so the field is already set to 0 by default on all
architectures. You shouldn't need set_snan_bit_is_one(0) calls on
CPU initialization on any architecture.


>  5. For remaining cases, nothing is added. (Those cases explicitly set
> their CPUXXXState/float_status structures to 0, and thus implicitly
> perform set_snan_bit_is_one(0).)
> (arm, i386, m68k, microblaze, openrisc, sparc)
>

--
Eduardo

Re: [Qemu-devel] [PATCH v4 3/9] softfloat: For Mips only, correct order in pickNaNMulAdd()

[Aleksandar Markovic]

Thanks, you are right, this area is changed in patch #1 too. However, it was 
not intended to be that way. Patch #1 should leave this function as-is, and the 
entire change for this function should be in this patch. I will organize the 
code as intended in the next version of the series. Yours, Aleksandar

From: Leon Alrae
Sent: Wednesday, April 13, 2016 5:47 AM
To: Aleksandar Markovic; qemu-devel@nongnu.org
Cc: pro...@gmail.com; kbast...@mail.uni-paderborn.de; 
mark.cave-ayl...@ilande.co.uk; ag...@suse.de; blauwir...@gmail.com; 
jcmvb...@gmail.com; Aleksandar Markovic; qemu-...@nongnu.org; 
qemu-...@nongnu.org; Petar Jovanovic; pbonz...@redhat.com; Miodrag Dinic; 
edgar.igles...@gmail.com; g...@mprc.pku.edu.cn; afaer...@suse.de; 
aurel...@aurel32.net; r...@twiddle.net; Maciej Rozycki
Subject: Re: [PATCH v4 3/9] softfloat: For Mips only, correct order in 
pickNaNMulAdd()

On 12/04/16 13:58, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
>
> Only for Mips platform, and only for cases when snan_bit_is_one is 0,
> correct the order of argument comparisons in pickNaNMulAdd().
>
> For more info, see [2], page 53, section "3.5.3 NaN Propagation".
>
> [1] "MIPS® Architecture For Programmers Volume II-A:
> The MIPS64® Instruction Set Reference Manual",
> Imagination Technologies LTD, Revision 6.04, November 13, 2015
>
> [2] "MIPS Architecture for Programmers Volume IV-j:
> The MIPS32® SIMD Architecture Module",
> Imagination Technologies LTD, Revision 1.12, February 3, 2016
>
> Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
> ---
>  fpu/softfloat-specialize.h |   41 +
>  1 file changed, 29 insertions(+), 12 deletions(-)
>
> diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
> index 169246e..807ecc0 100644
> --- a/fpu/softfloat-specialize.h
> +++ b/fpu/softfloat-specialize.h
> @@ -569,19 +569,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, 
> flag bIsQNaN, flag bIsSNaN,
>  return 3;
>  }
>
> -/* Prefer sNaN over qNaN, in the c, a, b order. */
> -if (cIsSNaN) {
> -return 2;
> -} else if (aIsSNaN) {
> -return 0;
> -} else if (bIsSNaN) {
> -return 1;
> -} else if (cIsQNaN) {
> -return 2;
> -} else if (aIsQNaN) {
> -return 0;

Initially I was confused with this part of diff until I realized that
you had modified the original order in pickNaNMulAdd in patch #1 -- was
that intended?

Otherwise:

Reviewed-by: Leon Alrae <leon.al...@imgtec.com>

> +if (status->snan_bit_is_one) {
> +/* Prefer sNaN over qNaN, in the a, b, c order. */
> +if (aIsSNaN) {
> +return 0;
> +} else if (bIsSNaN) {
> +return 1;
> +} else if (cIsSNaN) {
> +return 2;
> +} else if (aIsQNaN) {
> +return 0;
> +} else if (bIsQNaN) {
> +return 1;
> +} else {
> +return 2;
> +}
>  } else {
> -return 1;
> +/* Prefer sNaN over qNaN, in the c, a, b order. */
> +if (cIsSNaN) {
> +return 2;
> +} else if (aIsSNaN) {
> +return 0;
> +} else if (bIsSNaN) {
> +return 1;
> +} else if (cIsQNaN) {
> +return 2;
> +} else if (aIsQNaN) {
> +return 0;
> +} else {
> +return 1;
> +}
>  }
>  }
>  #elif defined(TARGET_PPC)
>

Re: [Qemu-devel] [PATCH v5 5/9] target-mips: Activate IEEE 274-2008 signaling NaN bit meaning

[Aleksandar Markovic]

No, nothing is lost. The plan is to add this functionality at a later time.

From: Maciej Rozycki
Sent: Monday, April 25, 2016 7:06 AM
To: Aleksandar Markovic
Cc: qemu-devel@nongnu.org; peter.mayd...@linaro.org; pro...@gmail.com; 
kbast...@mail.uni-paderborn.de; mark.cave-ayl...@ilande.co.uk; ag...@suse.de; 
blauwir...@gmail.com; jcmvb...@gmail.com; Aleksandar Markovic; 
qemu-...@nongnu.org; qemu-...@nongnu.org; Petar Jovanovic; pbonz...@redhat.com; 
Miodrag Dinic; edgar.igles...@gmail.com; g...@mprc.pku.edu.cn; Leon Alrae; 
afaer...@suse.de; Aurelien Jarno; r...@twiddle.net
Subject: Re: [PATCH v5 5/9] target-mips: Activate IEEE 274-2008 signaling NaN 
bit meaning

On Mon, 18 Apr 2016, Aleksandar Markovic wrote:

> Functions mips_cpu_reset() and msa_reset() are updated so that flag
> snan_bit_is_one is properly set for any Mips FPU/MSA configuration.
> For main FPUs, CPUs with FCR31's FCR31_NAN2008 bit set will invoke
> set_snan_bit_is_one(0). For MSA, as it is IEEE 274-2008 compliant
> from it inception, set_snan_bit_is_one(0) will always be invoked.

 I have skimmed over the series -- have you lost MIPSr3 support (writable
FCSR ABS2008 and NAN2008 bits) in porting?

  Maciej

[Qemu-devel] [PATCH v6 8/9] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

New set of helpers for handling nan2008-syle versions of instructions
<CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>, for Mips R6.

All involved instructions have float operand and integer result. Their
core functionality is implemented via invocations of appropriate SoftFloat
functions. The problematic cases are when the operand is a NaN, and also
when the operand (float) is out of the range of the result.

Here one can distinguish three cases:

CASE MIPS-A: (FCR31.NAN2008 == 1)

   1. Operand is a NaN, result should be 0;
   2. Operand is larger than INT_MAX, result should be INT_MAX;
   2. Operand is smaller than INT_MIN, result should be INT_MIN.

CASE MIPS-B: (FCR31.NAN2008 == 0)

   1. Operand is a NaN, result should be INT_MAX;
   2. Operand is larger than INT_MAX, result should be INT_MAX;
   2. Operand is smaller than INT_MIN, result should be INT_MAX.

CASE SOFTFLOAT:

   1. Operand is a NaN, result is INT_MAX;
   2. Operand is larger than INT_MAX, result is INT_MAX;
   2. Operand is smaller than INT_MIN, result is INT_MIN.

It is interesting that neither MIPS-A nor MIPS-B desired behaviors
are in this sense identical to correspondent SoftFloat behavior.

Current implementation of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
implements case MIPS-B. This patch relates to case MIPS-A. For case
MIPS-A, only return value for NaN-operands should be corrected after
appropriate SoftFloat library function is called.

Related MSA instructions FTRUNC_S and FTINT_S already handle well
all cases, in the fashion similar to the code from this patch.

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/helper.h|  18 +--
 target-mips/op_helper.c | 369 +---
 target-mips/translate.c | 122 +---
 3 files changed, 461 insertions(+), 48 deletions(-)

diff --git a/target-mips/helper.h b/target-mips/helper.h
index 8546177..666936c 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -207,8 +207,6 @@ DEF_HELPER_4(ctc1, void, env, tl, i32, i32)
 DEF_HELPER_2(float_cvtd_s, i64, env, i32)
 DEF_HELPER_2(float_cvtd_w, i64, env, i32)
 DEF_HELPER_2(float_cvtd_l, i64, env, i64)
-DEF_HELPER_2(float_cvtl_d, i64, env, i64)
-DEF_HELPER_2(float_cvtl_s, i64, env, i32)
 DEF_HELPER_2(float_cvtps_pw, i64, env, i64)
 DEF_HELPER_2(float_cvtpw_ps, i64, env, i64)
 DEF_HELPER_2(float_cvts_d, i32, env, i64)
@@ -216,8 +214,6 @@ DEF_HELPER_2(float_cvts_w, i32, env, i32)
 DEF_HELPER_2(float_cvts_l, i32, env, i64)
 DEF_HELPER_2(float_cvts_pl, i32, env, i32)
 DEF_HELPER_2(float_cvts_pu, i32, env, i32)
-DEF_HELPER_2(float_cvtw_s, i32, env, i32)
-DEF_HELPER_2(float_cvtw_d, i32, env, i64)
 
 DEF_HELPER_3(float_addr_ps, i64, env, i64, i64)
 DEF_HELPER_3(float_mulr_ps, i64, env, i64, i64)
@@ -242,14 +238,20 @@ FOP_PROTO(mina)
 #undef FOP_PROTO
 
 #define FOP_PROTO(op)\
-DEF_HELPER_2(float_ ## op ## l_s, i64, env, i32) \
-DEF_HELPER_2(float_ ## op ## l_d, i64, env, i64) \
-DEF_HELPER_2(float_ ## op ## w_s, i32, env, i32) \
-DEF_HELPER_2(float_ ## op ## w_d, i32, env, i64)
+DEF_HELPER_2(float_ ## op ## _l_s, i64, env, i32) \
+DEF_HELPER_2(float_ ## op ## _l_d, i64, env, i64) \
+DEF_HELPER_2(float_ ## op ## _w_s, i32, env, i32) \
+DEF_HELPER_2(float_ ## op ## _w_d, i32, env, i64)
+FOP_PROTO(cvt)
 FOP_PROTO(round)
 FOP_PROTO(trunc)
 FOP_PROTO(ceil)
 FOP_PROTO(floor)
+FOP_PROTO(cvt_2008)
+FOP_PROTO(round_2008)
+FOP_PROTO(trunc_2008)
+FOP_PROTO(ceil_2008)
+FOP_PROTO(floor_2008)
 #undef FOP_PROTO
 
 #define FOP_PROTO(op)\
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 9e7e2e0..0d1e959 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2448,6 +2448,7 @@ void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
 
 #define FLOAT_TWO32 make_float32(1 << 30)
 #define FLOAT_TWO64 make_float64(1ULL << 62)
+
 #define FP_TO_INT32_OVERFLOW 0x7fff
 #define FP_TO_INT64_OVERFLOW 0x7fffULL
 
@@ -2683,7 +2684,7 @@ uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t 
dt0)
 return fdt2;
 }
 
-uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
+uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
 {
 uint64_t dt2;
 
@@ -2696,7 +2697,7 @@ uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t 
fdt0)
 return dt2;
 }
 
-uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
+uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
 {
 uint64_t dt2;
 
@@ -2791,7 +2792,7 @@ uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t 
wth0)
 return wt2;
 }
 
-uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
+uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
 {
 uint32_t wt2;
 
@@ -2804,7 +2805,7 @@ uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t 
fst0)

[Qemu-devel] [PATCH v6 7/9] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Updated handling of instructions <ABS|NEG>.<S|D>. Note that legacy
(pre-abs2008) ABS and NEG instructions are arithmetic (and, therefore,
any NaN operand causes signaling invalid operation), while abs2008
ones are non-arithmetic, always and only changing the sign bit, even
for NaN-like operands. Details on these instructions are documented
in [1] p. 35 and 359.

Implementation-wise, abs2008 versions are implemented without helpers,
for simplicity and performance sake.

[1] "MIPS Architecture For Programmers Volume II-A:
The MIPS64 Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/translate.c | 26 ++
 1 file changed, 22 insertions(+), 4 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 2cdd2bd..3b6b3b5 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1434,6 +1434,7 @@ typedef struct DisasContext {
 bool vp;
 bool cmgcr;
 bool mrp;
+bool abs2008;
 } DisasContext;
 
 enum {
@@ -8879,7 +8880,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i32 fp0 = tcg_temp_new_i32();
 
 gen_load_fpr32(ctx, fp0, fs);
-gen_helper_float_abs_s(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_andi_i32(fp0, fp0, 0x7fffUL);
+} else {
+gen_helper_float_abs_s(fp0, fp0);
+}
 gen_store_fpr32(ctx, fp0, fd);
 tcg_temp_free_i32(fp0);
 }
@@ -8898,7 +8903,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i32 fp0 = tcg_temp_new_i32();
 
 gen_load_fpr32(ctx, fp0, fs);
-gen_helper_float_chs_s(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_xori_i32(fp0, fp0, 1UL << 31);
+} else {
+gen_helper_float_chs_s(fp0, fp0);
+}
 gen_store_fpr32(ctx, fp0, fd);
 tcg_temp_free_i32(fp0);
 }
@@ -9369,7 +9378,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i64 fp0 = tcg_temp_new_i64();
 
 gen_load_fpr64(ctx, fp0, fs);
-gen_helper_float_abs_d(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_andi_i64(fp0, fp0, 0x7fffULL);
+} else {
+gen_helper_float_abs_d(fp0, fp0);
+}
 gen_store_fpr64(ctx, fp0, fd);
 tcg_temp_free_i64(fp0);
 }
@@ -9390,7 +9403,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i64 fp0 = tcg_temp_new_i64();
 
 gen_load_fpr64(ctx, fp0, fs);
-gen_helper_float_chs_d(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_xori_i64(fp0, fp0, 1ULL << 63);
+} else {
+gen_helper_float_chs_d(fp0, fp0);
+}
 gen_store_fpr64(ctx, fp0, fd);
 tcg_temp_free_i64(fp0);
 }
@@ -19775,6 +19792,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct 
TranslationBlock *tb)
  (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
 ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
 ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
+ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
 restore_cpu_state(env, );
 #ifdef CONFIG_USER_ONLY
 ctx.mem_idx = MIPS_HFLAG_UM;
-- 
1.9.1

[Qemu-devel] [PATCH v6 3/9] softfloat: For Mips only, correct default NaN values

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Only for Mips platform, and only for cases when snan_bit_is_one is 0,
correct default NaN values (in their 16-, 32-, and 64-bit flavors).

For more info, see [1], page 84, Table 6.3 "Value Supplied When a New
Quiet NaN Is Created", and [2], page 52, Table 3.7 "Default NaN
Encodings".

[1] "MIPS Architecture For Programmers Volume II-A:
The MIPS64 Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

[2] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32 SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016

Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 fpu/softfloat-specialize.h | 12 
 1 file changed, 12 insertions(+)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index e03a529..093218f 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -97,7 +97,11 @@ float16 float16_default_nan(float_status *status)
 if (status->snan_bit_is_one) {
 return const_float16(0x7DFF);
 } else {
+#if defined(TARGET_MIPS)
+return const_float16(0x7E00);
+#else
 return const_float16(0xFE00);
+#endif
 }
 #endif
 }
@@ -116,7 +120,11 @@ float32 float32_default_nan(float_status *status)
 if (status->snan_bit_is_one) {
 return const_float32(0x7FBF);
 } else {
+#if defined(TARGET_MIPS)
+return const_float32(0x7FC0);
+#else
 return const_float32(0xFFC0);
+#endif
 }
 #endif
 }
@@ -135,7 +143,11 @@ float64 float64_default_nan(float_status *status)
 if (status->snan_bit_is_one) {
 return const_float64(LIT64(0x7FF7));
 } else {
+#if defined(TARGET_MIPS)
+return const_float64(LIT64(0x7FF8));
+#else
 return const_float64(LIT64(0xFFF8));
+#endif
 }
 #endif
 }
-- 
1.9.1

[Qemu-devel] [PATCH v6 2/9] softfloat: Clean code format in fpu/softfloat-specialize.h

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

fpu/softfloat-specialize.h is the most critical file in SoftFloat
library, since it handles numerous differences between platforms in
relation to floating point arithmetics. This patch makes the code
in this file more consistent format-wise, and hopefully easier to
debug and maintain.

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 fpu/softfloat-specialize.h | 99 +++---
 1 file changed, 50 insertions(+), 49 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 4411d3c..e03a529 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -273,7 +273,7 @@ static commonNaNT float16ToCommonNaN(float16 a, 
float_status *status)
 }
 z.sign = float16_val(a) >> 15;
 z.low = 0;
-z.high = ((uint64_t) float16_val(a))<<54;
+z.high = ((uint64_t) float16_val(a)) << 54;
 return z;
 }
 
@@ -284,7 +284,7 @@ static commonNaNT float16ToCommonNaN(float16 a, 
float_status *status)
 
 static float16 commonNaNToFloat16(commonNaNT a, float_status *status)
 {
-uint16_t mantissa = a.high>>54;
+uint16_t mantissa = a.high >> 54;
 
 if (status->default_nan_mode) {
 return float16_default_nan(status);
@@ -372,9 +372,9 @@ static commonNaNT float32ToCommonNaN(float32 a, 
float_status *status)
 if (float32_is_signaling_nan(a, status)) {
 float_raise(float_flag_invalid, status);
 }
-z.sign = float32_val(a)>>31;
+z.sign = float32_val(a) >> 31;
 z.low = 0;
-z.high = ( (uint64_t) float32_val(a) )<<41;
+z.high = ((uint64_t)float32_val(a)) << 41;
 return z;
 }
 
@@ -385,17 +385,18 @@ static commonNaNT float32ToCommonNaN(float32 a, 
float_status *status)
 
 static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
 {
-uint32_t mantissa = a.high>>41;
+uint32_t mantissa = a.high >> 41;
 
 if (status->default_nan_mode) {
 return float32_default_nan(status);
 }
 
-if ( mantissa )
+if (mantissa) {
 return make_float32(
-( ( (uint32_t) a.sign )<<31 ) | 0x7F80 | ( a.high>>41 ) );
-else
-return float32_default_nan;
+(((uint32_t)a.sign) << 31) | 0x7F80 | (a.high >> 41));
+} else {
+return float32_default_nan(status);
+}
 }
 
 /*
@@ -497,11 +498,10 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag 
bIsQNaN, flag bIsSNaN,
 return aIsLargerSignificand ? 0 : 1;
 }
 return bIsQNaN ? 1 : 0;
-}
-else if (aIsQNaN) {
-if (bIsSNaN || !bIsQNaN)
+} else if (aIsQNaN) {
+if (bIsSNaN || !bIsQNaN) {
 return 0;
-else {
+} else {
 return aIsLargerSignificand ? 0 : 1;
 }
 } else {
@@ -644,9 +644,9 @@ static float32 propagateFloat32NaN(float32 a, float32 b, 
float_status *status)
 return float32_default_nan(status);
 }
 
-if ((uint32_t)(av<<1) < (uint32_t)(bv<<1)) {
+if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) {
 aIsLargerSignificand = 0;
-} else if ((uint32_t)(bv<<1) < (uint32_t)(av<<1)) {
+} else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) {
 aIsLargerSignificand = 1;
 } else {
 aIsLargerSignificand = (av < bv) ? 1 : 0;
@@ -789,9 +789,9 @@ static commonNaNT float64ToCommonNaN(float64 a, 
float_status *status)
 if (float64_is_signaling_nan(a, status)) {
 float_raise(float_flag_invalid, status);
 }
-z.sign = float64_val(a)>>63;
+z.sign = float64_val(a) >> 63;
 z.low = 0;
-z.high = float64_val(a)<<12;
+z.high = float64_val(a) << 12;
 return z;
 }
 
@@ -808,13 +808,14 @@ static float64 commonNaNToFloat64(commonNaNT a, 
float_status *status)
 return float64_default_nan(status);
 }
 
-if ( mantissa )
+if (mantissa) {
 return make_float64(
-  ( ( (uint64_t) a.sign )<<63 )
-| LIT64( 0x7FF0 )
-| ( a.high>>12 ));
-else
-return float64_default_nan;
+  (((uint64_t) a.sign) << 63)
+| LIT64(0x7FF0)
+| (a.high >> 12));
+} else {
+return float64_default_nan(status);
+}
 }
 
 /*
@@ -844,9 +845,9 @@ static float64 propagateFloat64NaN(float64 a, float64 b, 
float_status *status)
 return float64_default_nan(status);
 }
 
-if ((uint64_t)(av<<1) < (uint64_t)(bv<<1)) {
+if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) {
 aIsLargerSignificand

[Qemu-devel] [PATCH v6 5/9] linux-user: Update preprocessor constants for Mips-specific e_flags bits

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Missing values EF_MIPS_FP64 and EF_MIPS_NAN2008 added, and the format
of the surrounding code segment adjusted.

Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 include/elf.h | 18 ++
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/include/elf.h b/include/elf.h
index 28d448b..b7f59e4 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -46,14 +46,16 @@ typedef int64_t  Elf64_Sxword;
 #define EF_MIPS_ABI_O320x1000  /* O32 ABI.  */
 #define EF_MIPS_ABI_O640x2000  /* O32 extended for 64 
bit.  */
 
-#define EF_MIPS_NOREORDER 0x0001
-#define EF_MIPS_PIC   0x0002
-#define EF_MIPS_CPIC  0x0004
-#define EF_MIPS_ABI2   0x0020
-#define EF_MIPS_OPTIONS_FIRST  0x0080
-#define EF_MIPS_32BITMODE  0x0100
-#define EF_MIPS_ABI0xf000
-#define EF_MIPS_ARCH  0xf000
+#define EF_MIPS_NOREORDER   0x0001
+#define EF_MIPS_PIC 0x0002
+#define EF_MIPS_CPIC0x0004
+#define EF_MIPS_ABI20x0020
+#define EF_MIPS_OPTIONS_FIRST   0x0080
+#define EF_MIPS_32BITMODE   0x0100
+#define EF_MIPS_FP640x0200
+#define EF_MIPS_NAN2008 0x0400
+#define EF_MIPS_ABI 0xf000
+#define EF_MIPS_ARCH0xf000
 
 /* These constants define the different elf file types */
 #define ET_NONE   0
-- 
1.9.1

[Qemu-devel] [PATCH v6 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch modifies SoftFloat library so that it can be configured in
run-time in relation to the meaning of signaling NaN bit, while, at the
same time, strictly preserving its behavior on all existing platforms.

Background:

In floating-point calculations, there is a need for denoting undefined or
unrepresentable values. This is achieved by defining certain floating-point
numerical values to be NaNs (which stands for "not a number"). For additional
reasons, virtually all modern floating-point unit implementations use two
kinds of NaNs: quiet and signaling. The binary representations of these two
kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally,
the first bit of mantissa).

Up to 2008, standards for floating-point did not specify all details about
binary representation of NaNs. More specifically, the meaning of the bit
that is used for distinguishing between signaling and quiet NaNs was not
strictly prescribed. (IEEE 754-2008 was the first floating-point standard
that defined that meaning clearly, see [1], p. 35) As a result, different
platforms took different approaches, and that presented considerable
challenge for multi-platform emulators like QEMU.

Mips platform represents the most complex case among QEMU-supported
platforms regarding signaling NaN bit. Up to the Release 6 of Mips
architecture, "1" in signaling NaN bit denoted signaling NaN, which is
opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
that, Mips architecture for SIMD (also known as MSA, or vector instructions)
also specifies signaling bit in accordance to IEEE standard. MSA unit can be
implemented with both pre-Release 6 and Release 6 main processor units.

QEMU uses SoftFloat library to implement various floating-point-related
instructions on all platforms. The current QEMU implementation allows for
defining meaning of signaling NaN bit during build time, and is implemented
via preprocessor macro called SNAN_BIT_IS_ONE.

On the other hand, the change in this patch enables SoftFloat library to be
configured in run-time. This configuration is meant to occur during CPU
initialization, at the moment when it is definitely known what desired
behavior for particular CPU (or any additional FPUs) is.

The change is implemented so that it is consistent with existing
implementation of similar cases. This means that structure float_status is
used for passing the information about desired signaling NaN bit on each
invocation of SoftFloat functions. The additional field in float_status is
called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.

IMPORTANT:

This change is not meant to create any change in emulator behavior or
functionality on any platform. It just provides the means for SoftFloat
library to be used in a more flexible way - in other words, it will just
prepare SoftFloat library for usage related to Mips platform and its
specifics regarding signaling bit meaning, which is done in some of
subsequent patches from this series.

Further break down of changes:

  1) Added field snan_bit_is_one to the structure float_status, and
 correspondent setter function set_snan_bit_is_one().

  2) Constants <float16|float32|float64|floatx80|float128>_default_nan
 (used both internally and externally) converted to functions
 <float16|float32|float64|floatx80|float128>_default_nan(float_status*).
 This is necessary since they are dependent on signaling bit meaning.
 At the same time, for the sake of code cleanup and simplicity, constants
 <floatx80|float128>_default_nan_<low|high> (used only internally within
 SoftFloat library) are removed, as not needed.

  3) Added a float_status* argument to SoftFloat library functions
 XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
 XXX_maybe_silence_nan(XXX a_). This argument must be present in
 order to enable correct invocation of new version of functions
 XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128>
 here)

  4) Updated code for all platforms to reflect changes in SoftFloat library.
 This change is twofolds: it includes modifications of SoftFloat library
 functions invocations, and an addition of invocation of function
 set_snan_bit_is_one() during CPU initialization, with arguments that
 are appropriate for each particular platform. It was established that
 all platforms zero their main CPU data structures, so snan_bit_is_one(0)
 in appropriate places is not added, as it is not needed.

[1] "IEEE Standard for Floating-Point Arithmetic",
IEEE Computer Society, August 29, 2008.

Tested-by: Bastian Koppelmann <address@hidden> (TriCore part)
Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej 

[Qemu-devel] [PATCH v6 0/9] IEEE 754-2008 support for Mips

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

v6 - code for hanlding MSA FCLASS instructions slightly simplified.
   - handling of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> corrected for
 nan2008 case.
   - R/W bitmask for FCR31 introduced, and related functionalities
 implemented.
   - cleanup items for SoftFloat library are now in a separate patch.
   - minor errors corrected.

v5 - platform initialization code revisited one more time.
   - handling of CLASS.<S|D> and their MSA counterparts revisited.
   - better orgranization of patches (squashing, splitting).
   - corrected handling of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>.
   - code cleanup item in genfarith() - order of cases.
   - scripts/checkpatch.pl executed and errors addressed.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg02774.html)

v4 - Added code cleanup items:
   a. Capitalization of hex constants in softfloat-specialize.h;
   b. White spaces in softfloat-specialize.h;
   c. Order of Mips helpers for CVT.<L|W>.<S|D>.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01962.html)

v3 - Patch series reorganized into 6 patches instead of 2.
   - Commit messages improved.
   - Except commit messages, net result of applying v3 and v2 is the same.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01870.html)

v2 - Relevant CPU initialization code changes revisited for all platforms.
   - In connection with <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> and
 <ABS|NEG>.<S|D> Mips instructions handling, decision on whether
 pre-nan2008/pre-abs2008 or nan2008/abs2008 handling will apply
 moved from run-time to translate-time.
   - For Mips only, in nan2008 cases only, default NaN values fixed.
   - For Mips only, in nan2008 cases only, order in pickNaNMulAdd() fixed.
   - Code cleanup issues:
   a. Constants <floatx80|float128>_default_nan_<low|high> removed;
   b. Suffix <l|w>_<s|d> replaced with _<l|w>_<s|d> for some Mips helpers;
   c. In vicinity of changes, fixed not-beautiful code formatting.
   - Commit messages improved.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01232.html)

v1 - Initial version
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg06082.html)

Mips platform represents the most complex case among QEMU-supported
platforms in reference to certain aspects of floating-point arithmetics.
This is mostly a consequence of the fact that Mips platform, for many
reasons, evolved considerably over time related to floating-point
arithmetics standards (significantly more than other platforms).
It has been difficult for emulators like QEMU to support such variety
of configurations.

This patch series provides number of IEEE 754-2008-related features to
Mips platform. It addresses the most sensitive changes that require
modification of SoftFloat library, also used by most other platforms.

In order to make develpoment, testing, and integration easier, the patch
is split into two distinct parts:

   1. Part 1 (patches 1/9, 2/9, 3/9, 4/9, 5/9) that does not change any
  calculation or behavior on any platform (and, for that matter, even on
  Mips platform). Its sole purpose is to address platform independant
  issues in a non-invasive manner, and to make Part 2 possible.

   2. Part 2 (patches 6/9, 7/9, 8/9, 9/9) that sets some Mips processors to
  use provisions from Part 1, and additionally implements number of
  IEEE 754-2008-related features for Mips, while, at the same time,
  dealing with files located in directory target-mips only.

This patch series is based on the original set of patches proposed by Maciej W.
Rozycki: http://lists.nongnu.org/archive/html/qemu-devel/2014-12/msg00968.html

Aleksandar Markovic (9):
  softfloat: Implement run-time-configurable meaning of signaling NaN bit
  softfloat: Clean code format in fpu/softfloat-specialize.h
  softfloat: For Mips only, correct default NaN values
  softfloat: For Mips only, correct order in pickNaNMulAdd()
  linux-user: Update preprocessor constants for Mips-specific e_flags bits
  target-mips: Activate IEEE 754-2008 signaling NaN bit meaning
  target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>
  target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
  target-mips: Implement FCR31's R/W bitmask and related functionalities

 fpu/softfloat-specialize.h| 664 +-
 fpu/softfloat.c   | 172 +--
 include/elf.h |  18 +-
 include/fpu/softfloat.h   |  45 +--
 linux-user/main.c |  14 +
 target-arm/helper-a64.c   |  14 +-
 target-arm/helper.c   |  40 +--
 target-m68k/helper.c  |   6 +-
 target-microblaze/op_helper.c |   6 +-
 ta

[Qemu-devel] [PATCH v6 6/9] target-mips: Activate IEEE 754-2008 signaling NaN bit meaning

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Functions mips_cpu_reset() and msa_reset() are updated so that flag
snan_bit_is_one is properly set for any Mips FPU/MSA configuration.
For main FPUs, CPUs with FCR31's FCR31_NAN2008 bit set will invoke
set_snan_bit_is_one(0). For MSA, as it is IEEE 274-2008 compliant
from it inception, set_snan_bit_is_one(0) will always be invoked.

By applying this patch, a number of incorrect behaviors for CPU
configurations that require IEEE 754-2008 compliance will be fixed.
Those are behaviors that (up to the moment of applying this patch)
did not get the desired functionality from SoftFloat library with
respect to distinguishing between quiet and signaling NaN, getting
default NaN values (both quiet and signaling), establishing if a
floating point number is Nan or not, etc.

Two examples:

* <MAX|MAXA>.<D|S> will now correctly detect and propagate NaNs.
* CLASS.<D|S> and FCLASS.<D|S> will now correcty detect NaN flavors.

Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/translate.c  | 6 +-
 target-mips/translate_init.c | 3 ++-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index e934884..2cdd2bd 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -20129,7 +20129,11 @@ void cpu_state_reset(CPUMIPSState *env)
 env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
 env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
 env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
-set_snan_bit_is_one(1, >active_fpu.fp_status);
+if ((env->active_fpu.fcr31 >> FCR31_NAN2008) & 1) {
+set_snan_bit_is_one(0, >active_fpu.fp_status);
+} else {
+set_snan_bit_is_one(1, >active_fpu.fp_status);
+}
 env->msair = env->cpu_model->MSAIR;
 env->insn_flags = env->cpu_model->insn_flags;
 
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index e81a831..a37d8bb 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -893,5 +893,6 @@ static void msa_reset(CPUMIPSState *env)
 /* clear float_status nan mode */
 set_default_nan_mode(0, >active_tc.msa_fp_status);
 
-set_snan_bit_is_one(1, >active_tc.msa_fp_status);
+/* set proper signanling bit meaning ("1" means "quiet") */
+set_snan_bit_is_one(0, >active_tc.msa_fp_status);
 }
-- 
1.9.1

[Qemu-devel] [PATCH v6 4/9] softfloat: For Mips only, correct order in pickNaNMulAdd()

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Only for Mips platform, and only for cases when snan_bit_is_one is 0,
correct the order of argument comparisons in pickNaNMulAdd().

For more info, see [1], page 53, section "3.5.3 NaN Propagation".

[1] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32 SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016

Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 fpu/softfloat-specialize.h | 41 +
 1 file changed, 29 insertions(+), 12 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 093218f..11fc66b 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -571,19 +571,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag 
bIsQNaN, flag bIsSNaN,
 return 3;
 }
 
-/* Prefer sNaN over qNaN, in the a, b, c order. */
-if (aIsSNaN) {
-return 0;
-} else if (bIsSNaN) {
-return 1;
-} else if (cIsSNaN) {
-return 2;
-} else if (aIsQNaN) {
-return 0;
-} else if (bIsQNaN) {
-return 1;
+if (status->snan_bit_is_one) {
+/* Prefer sNaN over qNaN, in the c, a, b order. */
+if (cIsSNaN) {
+return 2;
+} else if (aIsSNaN) {
+return 0;
+} else if (bIsSNaN) {
+return 1;
+} else if (cIsQNaN) {
+return 2;
+} else if (aIsQNaN) {
+return 0;
+} else {
+return 1;
+}
 } else {
-return 2;
+/* Prefer sNaN over qNaN, in the a, b, c order. */
+if (aIsSNaN) {
+return 0;
+} else if (bIsSNaN) {
+return 1;
+} else if (cIsSNaN) {
+return 2;
+} else if (aIsQNaN) {
+return 0;
+} else if (bIsQNaN) {
+return 1;
+} else {
+return 2;
+}
 }
 }
 #elif defined(TARGET_PPC)
-- 
1.9.1

[Qemu-devel] [PATCH v6 9/9] target-mips: Implement FCR31's R/W bitmask and related functionalities

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch implements read and write access rules for Mips floating
point control and status register (FCR31). The change can be divided
into following parts:

- Add preprocessor constants for all bits of FCR31 and related masks
  for its subfields.

- Add correspondant fields that will keep FCR31's R/W bitmask in
  procesor definitions and processor float_status structure.

- Add appropriate value for FCR31's R/W bitmask for each supported
  processor.

- Modify handling of CFC1 and CTC1 instructions (cases 25, 26, 28)
  so that they utilize newly-defind constants. This is just a cosmetic
  change, to make the code more readable, and to avoid usage of
  hardcoded constants.

- Modify handling of CTC1 (case 31) instruction to use FCR31's R/W
  bitmask.

- Modify handling user mode executables for Mips, in relation to the
  bit EF_MIPS_NAN2008 from ELF header, that is in turn related to
  reading and writing to FCR31.

- Modify gdb behavior in relation to FCR31.

Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 linux-user/main.c| 14 
 target-mips/cpu.h| 75 +--
 target-mips/gdbstub.c|  8 ++---
 target-mips/op_helper.c  | 76 +++-
 target-mips/translate.c  |  9 ++
 target-mips/translate_init.c | 54 +++
 6 files changed, 199 insertions(+), 37 deletions(-)

diff --git a/linux-user/main.c b/linux-user/main.c
index 5f3ec97..cc21057 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -4608,6 +4608,20 @@ int main(int argc, char **argv, char **envp)
 if (regs->cp0_epc & 1) {
 env->hflags |= MIPS_HFLAG_M16;
 }
+if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
+((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
+if ((env->active_fpu.fcr31_rw_bitmask &
+  (1 << FCR31_NAN2008)) == 0) {
+fprintf(stderr, "ELF binary's NaN mode not supported by 
CPU\n");
+exit(1);
+}
+if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
+env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
+} else {
+env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
+}
+restore_snan_bit_mode(env);
+}
 }
 #elif defined(TARGET_OPENRISC)
 {
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 6478420..bbf81c7 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -110,9 +110,71 @@ struct CPUMIPSFPUContext {
 #define FCR0_PRID 8
 #define FCR0_REV 0
 /* fcsr */
+uint32_t fcr31_rw_bitmask;
 uint32_t fcr31;
-#define FCR31_ABS2008 19
-#define FCR31_NAN2008 18
+#define FCR31_ROUNDING_MODE_0 0
+#define FCR31_ROUNDING_MODE_1 1
+#define FCR31_FLAGS_INEXACT   2
+#define FCR31_FLAGS_UNDERFLOW 3
+#define FCR31_FLAGS_OVERFLOW  4
+#define FCR31_FLAGS_DIV0  5
+#define FCR31_FLAGS_INVALID   6
+#define FCR31_ENABLE_INEXACT  7
+#define FCR31_ENABLE_UNDERFLOW8
+#define FCR31_ENABLE_OVERFLOW 9
+#define FCR31_ENABLE_DIV0 10
+#define FCR31_ENABLE_INVALID  11
+#define FCR31_CAUSE_INEXACT   12
+#define FCR31_CAUSE_UNDERFLOW 13
+#define FCR31_CAUSE_OVERFLOW  14
+#define FCR31_CAUSE_DIV0  15
+#define FCR31_CAUSE_INVALID   16
+#define FCR31_CAUSE_UNIMPLEMENTED 17
+#define FCR31_NAN2008 18
+#define FCR31_ABS2008 19
+#define FCR31_0   20
+#define FCR31_IMPL_0  21
+#define FCR31_IMPL_1  22
+#define FCR31_FCC_COND23
+#define FCR31_FS  24
+#define FCR31_FCC_COND_1  25
+#define FCR31_FCC_COND_2  26
+#define FCR31_FCC_COND_3  27
+#define FCR31_FCC_COND_4  28
+#define FCR31_FCC_COND_5  29
+#define FCR31_FCC_COND_6  30
+#define FCR31_FCC_COND_7  31
+#define FCR31_ROUNDING_MODE_MASK  ((1 << FCR31_ROUNDING_MODE_0) | \
+   (1 << FCR31_ROUNDING_MODE_1))
+#define FCR31_FLAGS_MASK  ((1 << FCR31_FLAGS_INEXACT) | \
+   (1 << FCR31_FLAGS_UNDERFLOW) | \
+   (1 << FCR31_FLAGS_OVERFLOW) | \
+   (1 << FCR31_FLAGS_DIV0) | \
+   (1 << FCR31_FLAGS_INVALID))
+#define FCR31_ENABLE_MASK ((1 << FCR31_ENABLE_INEXACT) | \
+   (1 << FCR31_ENABLE_UNDERFLOW) | \
+   (1 << FCR31_ENABLE_OVERFLOW) | \
+ 

Re: [Qemu-devel] [PATCH v5 7/9] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

[Aleksandar Markovic]

> > @@ -8919,7 +8920,11 @@ static void gen_farith (DisasContext *ctx, enum 
> > fopcode op1,
> >  TCGv_i64 fp64 = tcg_temp_new_i64();
> >
> >  gen_load_fpr32(ctx, fp32, fs);
> > -gen_helper_float_roundl_s(fp64, cpu_env, fp32);
> > +if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->nan2008)) {

> Why testing the version of the architecture? This will generate wrong
> helper for P5600 which is R5 and IEEE 754-2008 compliant.

The code reflects the documentation.

I just want to bring to your attention following two versions of the paragraph 
detailing return value of ROUND.L.S for some special cases - one version from 
R6 documention, and the other from R5 documentation:

R6: ("MIPS® Architecture For Programmers Volume II-A: The MIPS64® Instruction 
Set Reference Manual", Revision 6.04, page 393)

"When the source value is Infinity, NaN, or rounds to an integer outside the 
range -2 63 to 2 63 -1, the result cannot be
represented correctly and an IEEE Invalid Operation condition exists. The 
Invalid Operation flag is set in the FCSR.
If the Invalid Operation Enable bit is set in the FCSR, no result is written to 
fd and an Invalid Operation exception is
taken immediately. Otherwise, a default result is written to fd. On cores with 
FCSR[NAN2008]=0, the default result is
2^63–1. On cores with FCSR[NAN2008]=1, the default result is:
  • 0 when the input value is NaN
  • 2^63 –1 when the input value is +infinity or rounds to a number larger than 
2^63 –1
  • -2^63 –1 when the input value is –infinity or rounds to a number smaller 
than -2^63 –1"

R5: ("MIPS® Architecture For Programmers Volume II-A: The MIPS64® Instruction 
Set Reference Manual", Revision 5.04, page 314)

"When the source value is Infinity, NaN, or rounds to an integer outside the 
range -2 63 to 2 63 -1, the result cannot be
represented correctly and an IEEE Invalid Operation condition exists. In this 
case the Invalid Operation flag is set in
the FCSR. If the Invalid Operation Enable bit is set in the FCSR, no result is 
written to fd and an Invalid Operation
exception is taken immediately. Otherwise, the default result, 2 63 – 1, is 
written to fd."

It looks to me that the documentation for P5600 does not specify any exception 
or diversion from architecture document in this area.

Please let me know what exception for P5600 I am missing from the documentation.

Thanks,
Aleksandar

[Qemu-devel] [PATCH v5 7/9] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

New set of helpers for handling nan2008-syle versions of instructions
<CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>, for Mips R6.

All involved instructions have float operand and integer result. Their
core functionality is implemented via invocations of appropriate SoftFloat
functions. The problematic cases are when the operand is a NaN, and also
when the operand (float) is out of the range of the result.

Here one can distinguish three cases:

CASE MIPS-A: (MIPS64R6, FCR31.NAN2008 == 1)

   1. Operand is a NaN, result should be 0;
   2. Operand is larger than INT_MAX, result should be INT_MAX;
   2. Operand is smaller than INT_MIN, result should be INT_MIN.

CASE MIPS-B: (MIPS64R6, FCR31.NAN2008 == 0), (MIPS64R5)

   1. Operand is a NaN, result should be INT_MAX;
   2. Operand is larger than INT_MAX, result should be INT_MAX;
   2. Operand is smaller than INT_MIN, result should be INT_MAX.

CASE SOFTFLOAT:

   1. Operand is a NaN, result is INT_MAX;
   2. Operand is larger than INT_MAX, result is INT_MAX;
   2. Operand is smaller than INT_MIN, result is INT_MIN.

It is interesting that neither R6 nor R5 desired behaviors are in this
sense identical to correspondent SoftFloat behavior.

Current implementation of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
implements CASEMIPS-B. This patch relates to CASE-A. For CASE-A,
only return value for NaN-operands should be corrected, after
appropriate SoftFloat library function is called.

Related MSA instructions FTRUNC_S and FTINT_S already handle well
all cases, in the fashion similar to the code from this patch.

Details on <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> instructions
can be found in [1] p. 129, 130, 149, 155, 222, 223, 393, 394, 504, 505,
(for R6) and [2] (for R5).

[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

[2] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
    Imagination Technologies LTD, Revision 5.04, December 11, 2013

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/helper.h|  18 +--
 target-mips/op_helper.c | 365 +---
 target-mips/translate.c | 122 +---
 3 files changed, 457 insertions(+), 48 deletions(-)

diff --git a/target-mips/helper.h b/target-mips/helper.h
index 8546177..666936c 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -207,8 +207,6 @@ DEF_HELPER_4(ctc1, void, env, tl, i32, i32)
 DEF_HELPER_2(float_cvtd_s, i64, env, i32)
 DEF_HELPER_2(float_cvtd_w, i64, env, i32)
 DEF_HELPER_2(float_cvtd_l, i64, env, i64)
-DEF_HELPER_2(float_cvtl_d, i64, env, i64)
-DEF_HELPER_2(float_cvtl_s, i64, env, i32)
 DEF_HELPER_2(float_cvtps_pw, i64, env, i64)
 DEF_HELPER_2(float_cvtpw_ps, i64, env, i64)
 DEF_HELPER_2(float_cvts_d, i32, env, i64)
@@ -216,8 +214,6 @@ DEF_HELPER_2(float_cvts_w, i32, env, i32)
 DEF_HELPER_2(float_cvts_l, i32, env, i64)
 DEF_HELPER_2(float_cvts_pl, i32, env, i32)
 DEF_HELPER_2(float_cvts_pu, i32, env, i32)
-DEF_HELPER_2(float_cvtw_s, i32, env, i32)
-DEF_HELPER_2(float_cvtw_d, i32, env, i64)
 
 DEF_HELPER_3(float_addr_ps, i64, env, i64, i64)
 DEF_HELPER_3(float_mulr_ps, i64, env, i64, i64)
@@ -242,14 +238,20 @@ FOP_PROTO(mina)
 #undef FOP_PROTO
 
 #define FOP_PROTO(op)\
-DEF_HELPER_2(float_ ## op ## l_s, i64, env, i32) \
-DEF_HELPER_2(float_ ## op ## l_d, i64, env, i64) \
-DEF_HELPER_2(float_ ## op ## w_s, i32, env, i32) \
-DEF_HELPER_2(float_ ## op ## w_d, i32, env, i64)
+DEF_HELPER_2(float_ ## op ## _l_s, i64, env, i32) \
+DEF_HELPER_2(float_ ## op ## _l_d, i64, env, i64) \
+DEF_HELPER_2(float_ ## op ## _w_s, i32, env, i32) \
+DEF_HELPER_2(float_ ## op ## _w_d, i32, env, i64)
+FOP_PROTO(cvt)
 FOP_PROTO(round)
 FOP_PROTO(trunc)
 FOP_PROTO(ceil)
 FOP_PROTO(floor)
+FOP_PROTO(cvt_2008)
+FOP_PROTO(round_2008)
+FOP_PROTO(trunc_2008)
+FOP_PROTO(ceil_2008)
+FOP_PROTO(floor_2008)
 #undef FOP_PROTO
 
 #define FOP_PROTO(op)\
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 230aa94..7fecde7 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2448,6 +2448,7 @@ void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
 
 #define FLOAT_TWO32 make_float32(1 << 30)
 #define FLOAT_TWO64 make_float64(1ULL << 62)
+
 #define FP_TO_INT32_OVERFLOW 0x7fff
 #define FP_TO_INT64_OVERFLOW 0x7fffULL
 
@@ -2683,7 +2684,7 @@ uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t 
dt0)
 return fdt2;
 }
 
-uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
+uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
 {
 uint64_t dt2;
 
@@ -2696,7 +2697,7 @@ uint64_t helper_float_cvtl_d(C

[Qemu-devel] [PATCH v5 6/9] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Updated handling of instuctions <ABS|NEG>.<S|D>. Note that legacy
(pre-abs2008) ABS and NEG instructions are arithmetic (and, therefore,
any NaN operand causes signaling invalid operation), while abs2008
ones are non-arithmetic, always and only changing the sign bit, even
for NaN-like operands. Details on these instructions are documented
in [1] p. 35 and 359.

Implementation-wise, abs2008 versions are implemented without helpers,
for simplicity and performance sake.

[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/translate.c | 26 ++
 1 file changed, 22 insertions(+), 4 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 2cdd2bd..3b6b3b5 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1434,6 +1434,7 @@ typedef struct DisasContext {
 bool vp;
 bool cmgcr;
 bool mrp;
+bool abs2008;
 } DisasContext;
 
 enum {
@@ -8879,7 +8880,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i32 fp0 = tcg_temp_new_i32();
 
 gen_load_fpr32(ctx, fp0, fs);
-gen_helper_float_abs_s(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_andi_i32(fp0, fp0, 0x7fffUL);
+} else {
+gen_helper_float_abs_s(fp0, fp0);
+}
 gen_store_fpr32(ctx, fp0, fd);
 tcg_temp_free_i32(fp0);
 }
@@ -8898,7 +8903,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i32 fp0 = tcg_temp_new_i32();
 
 gen_load_fpr32(ctx, fp0, fs);
-gen_helper_float_chs_s(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_xori_i32(fp0, fp0, 1UL << 31);
+} else {
+gen_helper_float_chs_s(fp0, fp0);
+}
 gen_store_fpr32(ctx, fp0, fd);
 tcg_temp_free_i32(fp0);
 }
@@ -9369,7 +9378,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i64 fp0 = tcg_temp_new_i64();
 
 gen_load_fpr64(ctx, fp0, fs);
-gen_helper_float_abs_d(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_andi_i64(fp0, fp0, 0x7fffULL);
+} else {
+gen_helper_float_abs_d(fp0, fp0);
+}
 gen_store_fpr64(ctx, fp0, fd);
 tcg_temp_free_i64(fp0);
 }
@@ -9390,7 +9403,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 TCGv_i64 fp0 = tcg_temp_new_i64();
 
 gen_load_fpr64(ctx, fp0, fs);
-gen_helper_float_chs_d(fp0, fp0);
+if (ctx->abs2008) {
+tcg_gen_xori_i64(fp0, fp0, 1ULL << 63);
+} else {
+gen_helper_float_chs_d(fp0, fp0);
+}
 gen_store_fpr64(ctx, fp0, fd);
 tcg_temp_free_i64(fp0);
 }
@@ -19775,6 +19792,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct 
TranslationBlock *tb)
  (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
 ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
 ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
+ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
 restore_cpu_state(env, );
 #ifdef CONFIG_USER_ONLY
 ctx.mem_idx = MIPS_HFLAG_UM;
-- 
1.9.1

[Qemu-devel] [PATCH v5 3/9] softfloat: For Mips only, correct order in pickNaNMulAdd()

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Only for Mips platform, and only for cases when snan_bit_is_one is 0,
correct the order of argument comparisons in pickNaNMulAdd().

For more info, see [2], page 53, section "3.5.3 NaN Propagation".

[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

[2] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32® SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016

Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 fpu/softfloat-specialize.h | 41 +
 1 file changed, 29 insertions(+), 12 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 093218f..11fc66b 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -571,19 +571,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag 
bIsQNaN, flag bIsSNaN,
 return 3;
 }
 
-/* Prefer sNaN over qNaN, in the a, b, c order. */
-if (aIsSNaN) {
-return 0;
-} else if (bIsSNaN) {
-return 1;
-} else if (cIsSNaN) {
-return 2;
-} else if (aIsQNaN) {
-return 0;
-} else if (bIsQNaN) {
-return 1;
+if (status->snan_bit_is_one) {
+/* Prefer sNaN over qNaN, in the c, a, b order. */
+if (cIsSNaN) {
+return 2;
+} else if (aIsSNaN) {
+return 0;
+} else if (bIsSNaN) {
+return 1;
+} else if (cIsQNaN) {
+return 2;
+} else if (aIsQNaN) {
+return 0;
+} else {
+return 1;
+}
 } else {
-return 2;
+/* Prefer sNaN over qNaN, in the a, b, c order. */
+if (aIsSNaN) {
+return 0;
+} else if (bIsSNaN) {
+return 1;
+} else if (cIsSNaN) {
+return 2;
+} else if (aIsQNaN) {
+return 0;
+} else if (bIsQNaN) {
+return 1;
+} else {
+return 2;
+}
 }
 }
 #elif defined(TARGET_PPC)
-- 
1.9.1

[Qemu-devel] [PATCH v5 0/9] target-mips: Initiate IEEE 754-2008 support for Mips

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

v5 - platform initialization code revisited one more time;
   - handling of CLASS.<S|D> and their MSA counterparts revisited;
   - better orgranization of patches (squashing, splitting);
   - corrected handling of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>;
   - code cleanup item in genfarith() - order of cases;
   - scripts/checkpatch.pl executed and errors addressed.

v4 - Added code cleanup items:
   a. Capitalization of hex constants in softfloat-specialize.h;
   b. White spaces in softfloat-specialize.h;
   c. Order of Mips helpers for CVT.<L|W>.<S|D>.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01962.html)

v3 - Patch series reorganized into 6 patches instead of 2.
   - Commit messages improved.
   - Except commit messages, net result of applying v3 and v2 is the same.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01870.html)

v2 - Relevant CPU initialization code changes revisited for all platforms.
   - In connection with <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> and
 <ABS|NEG>.<S|D> Mips instructions handling, decision on whether
 pre-nan2008/pre-abs2008 or nan2008/abs2008 handling will apply
 moved from run-time to translate-time.
   - For Mips only, in nan2008 cases only, default NaN values fixed.
   - For Mips only, in nan2008 cases only, order in pickNaNMulAdd() fixed.
   - Code cleanup issues:
   a. Constants <floatx80|float128>_default_nan_<low|high> removed;
   b. Suffix <l|w>_<s|d> replaced with _<l|w>_<s|d> for some Mips helpers;
   c. In vicinity of changes, fixed not-beautiful code formatting.
   - Commit messages improved.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01232.html)

V1 - Initial version
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg06082.html)

Mips platform represents the most complex case among QEMU-supported
platforms in reference to certain aspects of floating-point arithmetics.
This is mostly a consequence of the fact that Mips platform, for many
reasons, evolved considerably over time related to floating-point
arithmetics standards (significantly more than other platforms).
It has been difficult for emulators like QEMU to support such variety
of configurations.

This patch series provides number of IEEE 754-2008-related features to
Mips platform. It addresses the most sensitive changes that require
modification of SoftFloat library, that is used by most other platforms.

In order to make develpoment, testing, and integration easier, the patch
is split into two distinct parts:

   1. Part 1 (patches 1/9, 2/9, 3/9) that does not change any calculation
  or behavior on any platform (and, for that matter, even on Mips
  platform). Its sole purpose is to address platform independant
  issues in a non-invasive manner, and to make Part 2 possible.

   2. Part 2 (patches 4/9, 5/9, 6/9, 7/9, 8/9, 9/9) that sets some Mips
  architecures to use provisions from Part 1, and additionally implements
  some of IEEE 754-2008-relates features for Mips, while, at the same time,
  dealing with files located in directory target-mips only.

A limitation of this patch series is that it does not cover all IEEE 754-2008
Mips issues (for example, handling FCR31's FS bit, handling R3 and R5
architectures details, some gdb issues, ELF header nan2008-related changes).
However, hopefully all remaining such issues will touch only Mips-specific
source code files, and thus will be much easier to integrate in QEMU, and,
of course, will not be disruptive to orher platforms.

This patch series is based on the original set of patches proposed by Maciej W.
Rozycki: http://lists.nongnu.org/archive/html/qemu-devel/2014-12/msg00968.html

Aleksandar Markovic (9):
  softfloat: Implement run-time-configurable meaning of signaling NaN bit
  softfloat: For Mips only, correct default NaN values
  softfloat: For Mips only, correct order in pickNaNMulAdd()
  target-mips: Amend processor definitions in relation to FCR31
  target-mips: Activate IEEE 274-2008 signaling NaN bit meaning
  target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>
  target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
  target-mips: Clean up position and order of helpers for CVT.<L|W>.<S|D>
  target-mips: Clean up position of abs2008/nan2008 cases in genfarith()

 fpu/softfloat-specialize.h| 664 +-
 fpu/softfloat.c   | 172 +--
 include/fpu/softfloat.h   |  45 +--
 target-arm/helper-a64.c   |  14 +-
 target-arm/helper.c   |  40 +--
 target-m68k/helper.c  |   6 +-
 target-microblaze/op_helper.c |   6 +-
 target-mips/cpu.h |   5 +
 target-mips/helper.h  |  22

Re: [Qemu-devel] [PATCH v5 7/9] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

[Aleksandar Markovic]

There was a small error in the version of this patch 7/9 sent an hour ago.
Please apply this corrected version. 

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

New set of helpers for handling nan2008-syle versions of instructions
<CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>, for Mips R6.

All involved instructions have float operand and integer result. Their
core functionality is implemented via invocations of appropriate SoftFloat
functions. The problematic cases are when the operand is a NaN, and also
when the operand (float) is out of the range of the result.

Here one can distinguish three cases:

CASE MIPS-A: (MIPS64R6, FCR31.NAN2008 == 1)

   1. Operand is a NaN, result should be 0;
   2. Operand is larger than INT_MAX, result should be INT_MAX;
   2. Operand is smaller than INT_MIN, result should be INT_MIN.

CASE MIPS-B: (MIPS64R6, FCR31.NAN2008 == 0), (MIPS64R5)

   1. Operand is a NaN, result should be INT_MAX;
   2. Operand is larger than INT_MAX, result should be INT_MAX;
   2. Operand is smaller than INT_MIN, result should be INT_MAX.

CASE SOFTFLOAT:

   1. Operand is a NaN, result is INT_MAX;
   2. Operand is larger than INT_MAX, result is INT_MAX;
   2. Operand is smaller than INT_MIN, result is INT_MIN.

It is interesting that neither R6 nor R5 desired behaviors are in this
sense identical to correspondent SoftFloat behavior.

Current implementation of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
implements CASEMIPS-B. This patch relates to CASE-A. For CASE-A,
only return value for NaN-operands should be corrected, after
appropriate SoftFloat library function is called.

Related MSA instructions FTRUNC_S and FTINT_S already handle well
all cases, in the fashion similar to the code from this patch.

Details on <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> instructions
can be found in [1] p. 129, 130, 149, 155, 222, 223, 393, 394, 504, 505,
(for R6) and [2] (for R5).

[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

[2] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
    Imagination Technologies LTD, Revision 5.04, December 11, 2013

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/helper.h|  18 +--
 target-mips/op_helper.c | 365 +---
 target-mips/translate.c | 122 +---
 3 files changed, 457 insertions(+), 48 deletions(-)

diff --git a/target-mips/helper.h b/target-mips/helper.h
index 8546177..666936c 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -207,8 +207,6 @@ DEF_HELPER_4(ctc1, void, env, tl, i32, i32)
 DEF_HELPER_2(float_cvtd_s, i64, env, i32)
 DEF_HELPER_2(float_cvtd_w, i64, env, i32)
 DEF_HELPER_2(float_cvtd_l, i64, env, i64)
-DEF_HELPER_2(float_cvtl_d, i64, env, i64)
-DEF_HELPER_2(float_cvtl_s, i64, env, i32)
 DEF_HELPER_2(float_cvtps_pw, i64, env, i64)
 DEF_HELPER_2(float_cvtpw_ps, i64, env, i64)
 DEF_HELPER_2(float_cvts_d, i32, env, i64)
@@ -216,8 +214,6 @@ DEF_HELPER_2(float_cvts_w, i32, env, i32)
 DEF_HELPER_2(float_cvts_l, i32, env, i64)
 DEF_HELPER_2(float_cvts_pl, i32, env, i32)
 DEF_HELPER_2(float_cvts_pu, i32, env, i32)
-DEF_HELPER_2(float_cvtw_s, i32, env, i32)
-DEF_HELPER_2(float_cvtw_d, i32, env, i64)
 
 DEF_HELPER_3(float_addr_ps, i64, env, i64, i64)
 DEF_HELPER_3(float_mulr_ps, i64, env, i64, i64)
@@ -242,14 +238,20 @@ FOP_PROTO(mina)
 #undef FOP_PROTO
 
 #define FOP_PROTO(op)\
-DEF_HELPER_2(float_ ## op ## l_s, i64, env, i32) \
-DEF_HELPER_2(float_ ## op ## l_d, i64, env, i64) \
-DEF_HELPER_2(float_ ## op ## w_s, i32, env, i32) \
-DEF_HELPER_2(float_ ## op ## w_d, i32, env, i64)
+DEF_HELPER_2(float_ ## op ## _l_s, i64, env, i32) \
+DEF_HELPER_2(float_ ## op ## _l_d, i64, env, i64) \
+DEF_HELPER_2(float_ ## op ## _w_s, i32, env, i32) \
+DEF_HELPER_2(float_ ## op ## _w_d, i32, env, i64)
+FOP_PROTO(cvt)
 FOP_PROTO(round)
 FOP_PROTO(trunc)
 FOP_PROTO(ceil)
 FOP_PROTO(floor)
+FOP_PROTO(cvt_2008)
+FOP_PROTO(round_2008)
+FOP_PROTO(trunc_2008)
+FOP_PROTO(ceil_2008)
+FOP_PROTO(floor_2008)
 #undef FOP_PROTO
 
 #define FOP_PROTO(op)\
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 230aa94..bcc9201 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2448,6 +2448,7 @@ void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
 
 #define FLOAT_TWO32 make_float32(1 << 30)
 #define FLOAT_TWO64 make_float64(1ULL << 62)
+
 #define FP_TO_INT32_OVERFLOW 0x7fff
 #define FP_TO_INT64_OVERFLOW 0x7fffULL
 
@@ -2683,7 +2684,7 @@ uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t 
dt0)
 return fdt2;
 }
 
-uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
+uint64_t helper_floa

[Qemu-devel] [PATCH v5 5/9] target-mips: Activate IEEE 274-2008 signaling NaN bit meaning

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Functions mips_cpu_reset() and msa_reset() are updated so that flag
snan_bit_is_one is properly set for any Mips FPU/MSA configuration.
For main FPUs, CPUs with FCR31's FCR31_NAN2008 bit set will invoke
set_snan_bit_is_one(0). For MSA, as it is IEEE 274-2008 compliant
from it inception, set_snan_bit_is_one(0) will always be invoked.

By applying this patch, a number of incorrect behaviors for CPU
configurations that require IEEE 274-2008 compliance will be fixed.
Those are behaviors that (up to the moment of applying this patch)
did not get the desired functionality from SoftFloat library with
respect to distinguishing between quiet and signaling NaN, getting
default NaN values (both quiet and signaling), establishing if a
floating point number is Nan or not, etc.

Just two examples:

* <MAX|MAXA>.<D|S> will now correctly detect and propagate NaNs.
* CLASS.<D|S> will now correcty detect NaN flavors, both their
  CPU FPU and MSA version.

Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/translate.c  | 6 +-
 target-mips/translate_init.c | 3 ++-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index e934884..2cdd2bd 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -20129,7 +20129,11 @@ void cpu_state_reset(CPUMIPSState *env)
 env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
 env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
 env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
-set_snan_bit_is_one(1, >active_fpu.fp_status);
+if ((env->active_fpu.fcr31 >> FCR31_NAN2008) & 1) {
+set_snan_bit_is_one(0, >active_fpu.fp_status);
+} else {
+set_snan_bit_is_one(1, >active_fpu.fp_status);
+}
 env->msair = env->cpu_model->MSAIR;
 env->insn_flags = env->cpu_model->insn_flags;
 
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 1094baa..bae6183 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -904,5 +904,6 @@ static void msa_reset(CPUMIPSState *env)
 /* clear float_status nan mode */
 set_default_nan_mode(0, >active_tc.msa_fp_status);
 
-set_snan_bit_is_one(1, >active_tc.msa_fp_status);
+/* set proper signanling bit meaning ("1" means "quiet") */
+set_snan_bit_is_one(0, >active_tc.msa_fp_status);
 }
-- 
1.9.1

[Qemu-devel] [PATCH v5 4/9] target-mips: Amend processor definitions in relation to FCR31

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Amend definitions of some Mips processors related to FCR31
(float status control register). Most significantly, FCR31 of
processors mips32r6-generic, mips64r6-generic, and P5600 will
be set so that its FCR31_ABS2008 and FCR31_NAN2008 bits are set
to 1.

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/translate_init.c | 15 +--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index e81a831..1094baa 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -273,6 +273,7 @@ static const mips_def_t mips_defs[] =
 .CP0_Status_rw_bitmask = 0x3678FF1F,
 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+.CP1_fcr31 = 0,
 .SEGBITS = 32,
 .PABITS = 32,
 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
@@ -303,6 +304,7 @@ static const mips_def_t mips_defs[] =
 (0xff << CP0TCSt_TASID),
 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
+.CP1_fcr31 = 0,
 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
 .CP0_SRSConf0_rw_bitmask = 0x3fff,
 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
@@ -343,6 +345,7 @@ static const mips_def_t mips_defs[] =
 .CP0_Status_rw_bitmask = 0x3778FF1F,
 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+.CP1_fcr31 = 0,
 .SEGBITS = 32,
 .PABITS = 32,
 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
@@ -434,7 +437,7 @@ static const mips_def_t mips_defs[] =
 },
 {
 /* A generic CPU supporting MIPS32 Release 6 ISA.
-   FIXME: Support IEEE 754-2008 FP.
+   FIXME: Complete support for IEEE 754-2008 FP.
   Eventually this should be replaced by a real CPU model. */
 .name = "mips32r6-generic",
 .CP0_PRid = 0x0001,
@@ -485,6 +488,7 @@ static const mips_def_t mips_defs[] =
 .CP0_Status_rw_bitmask = 0x3678,
 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
+.CP1_fcr31 = 0,
 .SEGBITS = 40,
 .PABITS = 36,
 .insn_flags = CPU_MIPS3,
@@ -503,6 +507,7 @@ static const mips_def_t mips_defs[] =
 .CP0_Status_rw_bitmask = 0x3678,
 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
+.CP1_fcr31 = 0,
 .SEGBITS = 40,
 .PABITS = 32,
 .insn_flags = CPU_VR54XX,
@@ -548,6 +553,7 @@ static const mips_def_t mips_defs[] =
 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
+.CP1_fcr31 = 0,
 .SEGBITS = 42,
 .PABITS = 36,
 .insn_flags = CPU_MIPS64,
@@ -575,6 +581,7 @@ static const mips_def_t mips_defs[] =
 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
 (1 << FCR0_D) | (1 << FCR0_S) |
 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
+.CP1_fcr31 = 0,
 .SEGBITS = 40,
 .PABITS = 36,
 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
@@ -601,6 +608,7 @@ static const mips_def_t mips_defs[] =
 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
+.CP1_fcr31 = 0,
 .SEGBITS = 42,
 .PABITS = 36,
 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
@@ -653,7 +661,7 @@ static const mips_def_t mips_defs[] =
 },
 {
 /* A generic CPU supporting MIPS64 Release 6 ISA.
-   FIXME: Support IEEE 754-2008 FP.
+   FIXME: Complete support for IEEE 754-2008 FP.
   Eventually this should be replaced by a real CPU model. */
 .name = "MIPS64R6-generic",
 .CP0_PRid = 0x0001,
@@ -704,6 +712,7 @@ static const mips_def_t mips_defs[] =
 .CCRes = 2,
 .CP0_Status_rw_bitmask = 0x35D0,
 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
+.CP1_fcr31 = 0,
 .SEGBITS = 40,
 .PAB

[Qemu-devel] [PATCH v5 2/9] softfloat: For Mips only, correct default NaN values

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Only for Mips platform, and only for cases when snan_bit_is_one is 0,
correct default NaN values (in their 16-, 32-, and 64-bit flavors).

For more info, see [1], page 84, Table 6.3 "Value Supplied When a New
Quiet NaN Is Created", and [2], page 52, Table 3.7 "Default NaN
Encodings".

[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

[2] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32® SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 fpu/softfloat-specialize.h | 12 
 1 file changed, 12 insertions(+)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index e03a529..093218f 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -97,7 +97,11 @@ float16 float16_default_nan(float_status *status)
 if (status->snan_bit_is_one) {
 return const_float16(0x7DFF);
 } else {
+#if defined(TARGET_MIPS)
+return const_float16(0x7E00);
+#else
 return const_float16(0xFE00);
+#endif
 }
 #endif
 }
@@ -116,7 +120,11 @@ float32 float32_default_nan(float_status *status)
 if (status->snan_bit_is_one) {
 return const_float32(0x7FBF);
 } else {
+#if defined(TARGET_MIPS)
+return const_float32(0x7FC0);
+#else
 return const_float32(0xFFC0);
+#endif
 }
 #endif
 }
@@ -135,7 +143,11 @@ float64 float64_default_nan(float_status *status)
 if (status->snan_bit_is_one) {
 return const_float64(LIT64(0x7FF7));
 } else {
+#if defined(TARGET_MIPS)
+return const_float64(LIT64(0x7FF8));
+#else
 return const_float64(LIT64(0xFFF8));
+#endif
 }
 #endif
 }
-- 
1.9.1

[Qemu-devel] [PATCH v5 8/9] target-mips: Clean up position and order of helpers for CVT.<L|W>.<S|D>

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch makes position and order of helpers for CVT.<L|W>.<S|D>
within file target-mips/op_helper.c consistent with position and order
of helpers for <CEIL|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>.

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/op_helper.c | 60 -
 1 file changed, 30 insertions(+), 30 deletions(-)

diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 7fecde7..203975e 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2684,32 +2684,6 @@ uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t 
dt0)
 return fdt2;
 }
 
-uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
-{
-uint64_t dt2;
-
-dt2 = float64_to_int64(fdt0, >active_fpu.fp_status);
-if (get_float_exception_flags(>active_fpu.fp_status)
-& (float_flag_invalid | float_flag_overflow)) {
-dt2 = FP_TO_INT64_OVERFLOW;
-}
-update_fcr31(env, GETPC());
-return dt2;
-}
-
-uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
-{
-uint64_t dt2;
-
-dt2 = float32_to_int64(fst0, >active_fpu.fp_status);
-if (get_float_exception_flags(>active_fpu.fp_status)
-& (float_flag_invalid | float_flag_overflow)) {
-dt2 = FP_TO_INT64_OVERFLOW;
-}
-update_fcr31(env, GETPC());
-return dt2;
-}
-
 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
 {
 uint32_t fst2;
@@ -2792,11 +2766,37 @@ uint32_t helper_float_cvts_pu(CPUMIPSState *env, 
uint32_t wth0)
 return wt2;
 }
 
-uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
+uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
+{
+uint64_t dt2;
+
+dt2 = float64_to_int64(fdt0, >active_fpu.fp_status);
+if (get_float_exception_flags(>active_fpu.fp_status)
+& (float_flag_invalid | float_flag_overflow)) {
+dt2 = FP_TO_INT64_OVERFLOW;
+}
+update_fcr31(env, GETPC());
+return dt2;
+}
+
+uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
+{
+uint64_t dt2;
+
+dt2 = float32_to_int64(fst0, >active_fpu.fp_status);
+if (get_float_exception_flags(>active_fpu.fp_status)
+& (float_flag_invalid | float_flag_overflow)) {
+dt2 = FP_TO_INT64_OVERFLOW;
+}
+update_fcr31(env, GETPC());
+return dt2;
+}
+
+uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
 {
 uint32_t wt2;
 
-wt2 = float32_to_int32(fst0, >active_fpu.fp_status);
+wt2 = float64_to_int32(fdt0, >active_fpu.fp_status);
 if (get_float_exception_flags(>active_fpu.fp_status)
 & (float_flag_invalid | float_flag_overflow)) {
 wt2 = FP_TO_INT32_OVERFLOW;
@@ -2805,11 +2805,11 @@ uint32_t helper_float_cvt_w_s(CPUMIPSState *env, 
uint32_t fst0)
 return wt2;
 }
 
-uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
+uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
 {
 uint32_t wt2;
 
-wt2 = float64_to_int32(fdt0, >active_fpu.fp_status);
+wt2 = float32_to_int32(fst0, >active_fpu.fp_status);
 if (get_float_exception_flags(>active_fpu.fp_status)
 & (float_flag_invalid | float_flag_overflow)) {
 wt2 = FP_TO_INT32_OVERFLOW;
-- 
1.9.1

[Qemu-devel] [PATCH v5 9/9] target-mips: Clean up position of abs2008/nan2008 cases in genfarith()

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch slightly reorders cases in genfarith() so that abs2008/nan2008-
dependant cases are grouped together, for easier maintenantce (code becomes
less prone to errors).

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/translate.c | 152 
 1 file changed, 76 insertions(+), 76 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index b7ab98a..76df972 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -8876,25 +8876,25 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 tcg_temp_free_i32(fp0);
 }
 break;
-case OPC_ABS_S:
+case OPC_MOV_S:
 {
 TCGv_i32 fp0 = tcg_temp_new_i32();
 
 gen_load_fpr32(ctx, fp0, fs);
-if (ctx->abs2008) {
-tcg_gen_andi_i32(fp0, fp0, 0x7fffUL);
-} else {
-gen_helper_float_abs_s(fp0, fp0);
-}
 gen_store_fpr32(ctx, fp0, fd);
 tcg_temp_free_i32(fp0);
 }
 break;
-case OPC_MOV_S:
+case OPC_ABS_S:
 {
 TCGv_i32 fp0 = tcg_temp_new_i32();
 
 gen_load_fpr32(ctx, fp0, fs);
+if (ctx->abs2008) {
+tcg_gen_andi_i32(fp0, fp0, 0x7fffUL);
+} else {
+gen_helper_float_abs_s(fp0, fp0);
+}
 gen_store_fpr32(ctx, fp0, fd);
 tcg_temp_free_i32(fp0);
 }
@@ -8913,6 +8913,23 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 tcg_temp_free_i32(fp0);
 }
 break;
+case OPC_CVT_L_S:
+check_cp1_64bitmode(ctx);
+{
+TCGv_i32 fp32 = tcg_temp_new_i32();
+TCGv_i64 fp64 = tcg_temp_new_i64();
+
+gen_load_fpr32(ctx, fp32, fs);
+if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->nan2008)) {
+gen_helper_float_cvt_2008_l_s(fp64, cpu_env, fp32);
+} else {
+gen_helper_float_cvt_l_s(fp64, cpu_env, fp32);
+}
+tcg_temp_free_i32(fp32);
+gen_store_fpr64(ctx, fp64, fd);
+tcg_temp_free_i64(fp64);
+}
+break;
 case OPC_ROUND_L_S:
 check_cp1_64bitmode(ctx);
 {
@@ -8981,6 +8998,20 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 tcg_temp_free_i64(fp64);
 }
 break;
+case OPC_CVT_W_S:
+{
+TCGv_i32 fp0 = tcg_temp_new_i32();
+
+gen_load_fpr32(ctx, fp0, fs);
+if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->nan2008)) {
+gen_helper_float_cvt_2008_w_s(fp0, cpu_env, fp0);
+} else {
+gen_helper_float_cvt_w_s(fp0, cpu_env, fp0);
+}
+gen_store_fpr32(ctx, fp0, fd);
+tcg_temp_free_i32(fp0);
+}
+break;
 case OPC_ROUND_W_S:
 {
 TCGv_i32 fp0 = tcg_temp_new_i32();
@@ -9276,37 +9307,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 tcg_temp_free_i64(fp64);
 }
 break;
-case OPC_CVT_W_S:
-{
-TCGv_i32 fp0 = tcg_temp_new_i32();
-
-gen_load_fpr32(ctx, fp0, fs);
-if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->nan2008)) {
-gen_helper_float_cvt_2008_w_s(fp0, cpu_env, fp0);
-} else {
-gen_helper_float_cvt_w_s(fp0, cpu_env, fp0);
-}
-gen_store_fpr32(ctx, fp0, fd);
-tcg_temp_free_i32(fp0);
-}
-break;
-case OPC_CVT_L_S:
-check_cp1_64bitmode(ctx);
-{
-TCGv_i32 fp32 = tcg_temp_new_i32();
-TCGv_i64 fp64 = tcg_temp_new_i64();
-
-gen_load_fpr32(ctx, fp32, fs);
-if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->nan2008)) {
-gen_helper_float_cvt_2008_l_s(fp64, cpu_env, fp32);
-} else {
-gen_helper_float_cvt_l_s(fp64, cpu_env, fp32);
-}
-tcg_temp_free_i32(fp32);
-gen_store_fpr64(ctx, fp64, fd);
-tcg_temp_free_i64(fp64);
-}
-break;
 case OPC_CVT_PS_S:
 check_ps(ctx);
 {
@@ -9413,6 +9413,16 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 tcg_temp_free_i64(fp0);
 }
 break;
+case OPC_MOV_D:
+check_cp1_registers(ctx, fs | fd);
+{
+TCGv_i64 fp0 = tcg_temp_new_i64();
+
+gen_load_fpr64(ctx, fp0, fs);
+gen_store_fpr64(ctx, fp0, fd);
+tcg_temp_free_i64(fp0);
+}
+break;
 case OPC_ABS_D:
 check_cp1_registers(ctx, fs | fd);
 

[Qemu-devel] [PATCH v5 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch modifies SoftFloat library so that it can be configured in
run-time in relation to the meaning of signaling NaN bit, while, at the
same time, strictly preserving its behavior on all existing platforms.

Background:

In floating-point calculations, there is a need for denoting undefined or
unrepresentable values. This is achieved by defining certain floating-point
numerical values to be NaNs (which stands for "not a number"). For additional
reasons, virtually all modern floating-point unit implementations use two
kinds of NaNs: quiet and signaling. The binary representations of these two
kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally,
the first bit of mantissa).

Up to 2008, standards for floating-point did not specify all details about
binary representation of NaNs. More specifically, the meaning of the bit
that is used for distinguishing between signaling and quiet NaNs was not
strictly prescribed. (IEEE 754-2008 was the first floating-point standard
that defined that meaning clearly, see [1], p. 35) As a result, different
platforms took different approaches, and that presented considerable
challenge for multi-platform emulators like QEMU.

Mips platform represents the most complex case among QEMU-supported
platforms regarding signaling NaN bit. Up to the Release 6 of Mips
architecture, "1" in signaling NaN bit denoted signaling NaN, which is
opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
that, Mips architecture for SIMD (also known as MSA, or vector instructions)
also specifies signaling bit in accordance to IEEE standard. MSA unit can be
implemented with both pre-Release 6 and Release 6 main processor units.

QEMU uses SoftFloat library to implement various floating-point-related
instructions on all platforms. The current QEMU implementation allows for
defining meaning of signaling NaN bit during build time, and is implemented
via preprocessor macro called SNAN_BIT_IS_ONE.

On the other hand, the change in this patch enables SoftFloat library to be
configured in run-time. This configuration is meant to occur during CPU
initialization, at the moment when it is definitely known what desired
behavior for particular CPU (or any additional FPUs) is.

The change is implemented so that it is consistent with existing
implementation of similar cases. This means that structure float_status is
used for passing the information about desired signaling NaN bit on each
invocation of SoftFloat functions. The additional field in float_status is
called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.

IMPORTANT:

This change is not meant to create any change in emulator behavior or
functionality on any platform. It just provides the means for SoftFloat
library to be used in a more flexible way - in other words, it will just
prepare SoftFloat library for usage related to Mips platform and its
specifics regarding signaling bit meaning, which is done in some of
subsequent patches from this series.

Further break down of changes:

  1) Added field snan_bit_is_one to the structure float_status, and
 correspondent setter function set_snan_bit_is_one().

  2) Constants <float16|float32|float64|floatx80|float128>_default_nan
 (used both internally and externally) converted to functions
 <float16|float32|float64|floatx80|float128>_default_nan(float_status*).
 This is necessary since they are dependent on signaling bit meaning.
 At the same time, for the sake of code cleanup and simplicity, constants
 <floatx80|float128>_default_nan_<low|high> (used only internally within
 SoftFloat library) are removed, as not needed.

  3) Added a float_status* argument to SoftFloat library functions
 XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
 XXX_maybe_silence_nan(XXX a_). This argument must be present in
 order to enable correct invocation of new version of functions
 XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128>
 here)

  4) Updated code for all platforms to reflect changes in SoftFloat library.
 This change is twofolds: it includes modifications of SoftFloat library
 functions invocations, and an addition of invocation of function
 set_snan_bit_is_one() during CPU initialization, with arguments that
 are appropriate for each particular platform. It was established that
 all platforms zero their main CPU data structures, so snan_bit_is_one(0)
 in appropriate places is not added, as it is not needed.

[1] "IEEE Standard for Floating-Point Arithmetic",
IEEE Computer Society, August 29, 2008.

Tested-by: Bastian Koppelmann <address@hidden> (TriCore part)
Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej 

Re: [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit

[Aleksandar Markovic]

Hi, Leon,

I cannot say thank you enough for all your valuable feedback.

Just wanted to give you a heads up that in the next version of this patch 
series (planned for tomorrow (Monday) or the day after tomorrow), I am going to 
integrate all your suggestions from this thread, including name "status" 
instead of "fst", and also following segment in cpu.h:

/* op_helper.c */
uint32_t float_class_s(uint32_t arg, float_status *fst);
uint64_t float_class_d(uint64_t arg, float_status *fst);

(unless you tell me not to do so)

Also, I think there will be some improvements in the patch related to 
<CEIL|CVT|FLOOR|...>, that are currently being analysed and tested here.

Sincerely,
Aleksandar
____
From: Aleksandar Markovic
Sent: Friday, April 15, 2016 4:38 AM
To: Leon Alrae; Aleksandar Markovic; qemu-devel@nongnu.org
Cc: pro...@gmail.com; kbast...@mail.uni-paderborn.de; 
mark.cave-ayl...@ilande.co.uk; ag...@suse.de; blauwir...@gmail.com; 
jcmvb...@gmail.com; qemu-...@nongnu.org; qemu-...@nongnu.org; Petar Jovanovic; 
pbonz...@redhat.com; Miodrag Dinic; edgar.igles...@gmail.com; 
g...@mprc.pku.edu.cn; afaer...@suse.de; aurel...@aurel32.net; r...@twiddle.net; 
Maciej Rozycki
Subject: RE: [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning 
of signaling NaN bit

Hi, Leon,

There is one more subtle point here. The question is: Where to put declarations 
of two new functions? This is a new case in the organization of mips-specific 
source code files. File helpers.h does not seem to be a good place, cpu.h - 
maybe, but still looks clumsy to me.

IMHO, my solution from earlier versions of this patch series, in spite of 
containing code duplication, is superior in the sense of keeping current 
mips-specific source code file relations intact, respecting autonomy of 
msa_helpers.c, and is the best overall.

Yours,
Aleksandar


From: Leon Alrae
Sent: Friday, April 15, 2016 3:41 AM
To: Aleksandar Markovic; Aleksandar Markovic; qemu-devel@nongnu.org
Cc: pro...@gmail.com; kbast...@mail.uni-paderborn.de; 
mark.cave-ayl...@ilande.co.uk; ag...@suse.de; blauwir...@gmail.com; 
jcmvb...@gmail.com; qemu-...@nongnu.org; qemu-...@nongnu.org; Petar Jovanovic; 
pbonz...@redhat.com; Miodrag Dinic; edgar.igles...@gmail.com; 
g...@mprc.pku.edu.cn; afaer...@suse.de; aurel...@aurel32.net; r...@twiddle.net; 
Maciej Rozycki
Subject: Re: [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning 
of signaling NaN bit

On 15/04/16 09:48, Aleksandar Markovic wrote:
> Agreed. This looks much better, and is simpler and faster. Though, it looks 
> to me that "fst" should be called "status" instead (just not to break 
> consistency throughout SoftFloat library and in other places of assigning 
> name "status" to the last argument of any function if its type is 
> float_status*). If you agree, I am going to replace name "fst" with name 
> "status" in the code that you provided, otherwise as-is.

Yes, "status" will be fine.

Leon

Re: [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit

[Aleksandar Markovic]

Agreed. This looks much better, and is simpler and faster. Though, it looks to 
me that "fst" should be called "status" instead (just not to break consistency 
throughout SoftFloat library and in other places of assigning name "status" to 
the last argument of any function if its type is float_status*). If you agree, 
I am going to replace name "fst" with name "status" in the code that you 
provided, otherwise as-is.

From: Leon Alrae
Sent: Thursday, April 14, 2016 8:31 AM
To: Aleksandar Markovic; qemu-devel@nongnu.org
Cc: pro...@gmail.com; kbast...@mail.uni-paderborn.de; 
mark.cave-ayl...@ilande.co.uk; ag...@suse.de; blauwir...@gmail.com; 
jcmvb...@gmail.com; Aleksandar Markovic; qemu-...@nongnu.org; 
qemu-...@nongnu.org; Petar Jovanovic; pbonz...@redhat.com; Miodrag Dinic; 
edgar.igles...@gmail.com; g...@mprc.pku.edu.cn; afaer...@suse.de; 
aurel...@aurel32.net; r...@twiddle.net; Maciej Rozycki
Subject: Re: [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning 
of signaling NaN bit

On 12/04/2016 13:58, Aleksandar Markovic wrote:
> @@ -3200,11 +3200,17 @@ FLOAT_RINT(rint_d, 64)
>  #define FLOAT_CLASS_POSITIVE_ZERO  0x200
>
>  #define FLOAT_CLASS(name, bits)  \
> -uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg)\
> +uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
> + uint ## bits ## _t arg, uint32_t is_msa)\
>  {\
> -if (float ## bits ## _is_signaling_nan(arg)) {   \
> +float_status* fst;   \
> + \
> +fst = (is_msa == 1) ?\
> +>active_tc.msa_fp_status : >active_fpu.fp_status;  \
> + \
> +if (float ## bits ## _is_signaling_nan(arg, fst)) {  \
>  return FLOAT_CLASS_SIGNALING_NAN;\
> -} else if (float ## bits ## _is_quiet_nan(arg)) {\
> +} else if (float ## bits ## _is_quiet_nan(arg, fst)) {   \
>  return FLOAT_CLASS_QUIET_NAN;\
>  } else if (float ## bits ## _is_neg(arg)) {  \
>  if (float ## bits ## _is_infinity(arg)) {\

Let's make it a common function which takes float_status passed from FPU and
MSA helpers and avoid is_msa:


 #define FLOAT_CLASS(name, bits)  \
-uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg)\
+uint ## bits ## _t float_ ## name (uint ## bits ## _t arg,   \
+   float_status *fst)\
 {\
-if (float ## bits ## _is_signaling_nan(arg)) {   \
+if (float ## bits ## _is_signaling_nan(arg, fst)) {  \
 return FLOAT_CLASS_SIGNALING_NAN;\
-} else if (float ## bits ## _is_quiet_nan(arg)) {\
+} else if (float ## bits ## _is_quiet_nan(arg, fst)) {   \
 return FLOAT_CLASS_QUIET_NAN;\
 } else if (float ## bits ## _is_neg(arg)) {  \
 if (float ## bits ## _is_infinity(arg)) {\
@@ -3227,6 +3228,12 @@ uint ## bits ## _t helper_float_ ## name (uint ## bits 
## _t arg)\
 return FLOAT_CLASS_POSITIVE_NORMAL;  \
 }\
 }\
+}\
+ \
+uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
+  uint ## bits ## _t arg)\
+{\
+return float_ ## name(arg, >active_fpu.fp_status);  \
 }

 FLOAT_CLASS(class_s, 32)


And in MSA:


+float_status *status = >active_tc.msa_fp_status;
 if (df == DF_WORD) {
-pwd->w[0] = helper_float_class_s(pws->w[0]);
-pwd->w[1] = helper_float_class_s(pws->w[1]);
-pwd->w[2] = helper_float_class_s(pws->w[2]);
-pwd->w[3] = helper_float_class_s(pws->w[3]);
+pwd->w[0] = float_class_s(pws->w[0], status);
+pwd->w[1] = float_class_s(pws->w[1], status);
+pwd->w[2] = float_class_s(pws->w[2], status);
+ 

Re: [Qemu-devel] [PATCH v5 9/9] target-mips: Clean up position of abs2008/nan2008 cases in genfarith()

[Aleksandar Markovic]

Diff looks messy, but, in fact, this change is just changing location of
six cases in gen_farith().

This is illustrated in the diagram below: (I added indentation of 2 spaces for
abs2008-related cases, and 4 spaces for nan2008-related cases, to stress
the effect of grouping cases with similar handling; right order of cases is
of tremendous help during development; the diagram makes sense only
if it is displayed with fixed width fonts; you can copy/paste it in any editor
if that is not he case)

case OPC_ADD_S   case OPC_ADD_S
case OPC_SUB_S   case OPC_SUB_S
case OPC_MUL_S   case OPC_MUL_S
case OPC_DIV_S   case OPC_DIV_S
case OPC_SQRT_S  case OPC_SQRT_S   
  case OPC_ABS_S  -| case OPC_MOV_S
case OPC_MOV_S |-->case OPC_ABS_S  
  case OPC_NEG_S   case OPC_NEG_S  
case OPC_ROUND_L_S |-->  case OPC_CVT_L_S  
case OPC_TRUNC_L_S | case OPC_ROUND_L_S
case OPC_CEIL_L_S  | case OPC_TRUNC_L_S
case OPC_FLOOR_L_S | case OPC_CEIL_L_S 
case OPC_ROUND_W_S | case OPC_FLOOR_L_S
case OPC_TRUNC_W_S |  |--->  case OPC_CVT_W_S  
case OPC_CEIL_W_S  |  |  case OPC_ROUND_W_S
case OPC_FLOOR_W_S |  |  case OPC_TRUNC_W_S
case OPC_SEL_S |  |  case OPC_CEIL_W_S 
case OPC_SELEQZ_S  |  |  case OPC_FLOOR_W_S
case OPC_SELNEZ_S  |  |  case OPC_SEL_S
case OPC_MOVCF_S   |  |  case OPC_SELEQZ_S 
case OPC_MOVZ_S|  |  case OPC_SELNEZ_S 
case OPC_MOVN_S|  |  case OPC_MOVCF_S  
case OPC_RECIP_S   |  |  case OPC_MOVZ_S   
case OPC_RSQRT_S   |  |  case OPC_MOVN_S   
case OPC_MADDF_S   |  |  case OPC_RECIP_S  
case OPC_MSUBF_S   |  |  case OPC_RSQRT_S  
case OPC_RINT_S|  |  case OPC_MADDF_S  
case OPC_CLASS_S   |  |  case OPC_MSUBF_S  
case OPC_MIN_S |  |  case OPC_RINT_S   
case OPC_MINA_S|  |  case OPC_CLASS_S  
case OPC_MAX_S |  |  case OPC_MIN_S
case OPC_MAXA_S|  |  case OPC_MINA_S   
case OPC_CVT_D_S   |  |  case OPC_MAX_S
case OPC_CVT_W_S  |  case OPC_MAXA_S   
case OPC_CVT_L_S  -| case OPC_CVT_D_S  
case OPC_CVT_PS_Scase OPC_CVT_PS_S 
case OPC_CMP_F_S case OPC_CMP_F_S  
case OPC_CMP_UN_Scase OPC_CMP_UN_S 
case OPC_CMP_EQ_Scase OPC_CMP_EQ_S 
case OPC_CMP_UEQ_S   case OPC_CMP_UEQ_S
case OPC_CMP_OLT_S   case OPC_CMP_OLT_S
case OPC_CMP_ULT_S   case OPC_CMP_ULT_S
case OPC_CMP_OLE_S   case OPC_CMP_OLE_S
case OPC_CMP_ULE_S   case OPC_CMP_ULE_S
case OPC_CMP_SF_Scase OPC_CMP_SF_S 
case OPC_CMP_NGLE_S  case OPC_CMP_NGLE_S   
case OPC_CMP_SEQ_S   case OPC_CMP_SEQ_S
case OPC_CMP_NGL_S   case OPC_CMP_NGL_S
case OPC_CMP_LT_Scase OPC_CMP_LT_S 
case OPC_CMP_NGE_S   case OPC_CMP_NGE_S
case OPC_CMP_LE_Scase OPC_CMP_LE_S 
case OPC_CMP_NGT_S   case OPC_CMP_NGT_S
case OPC_ADD_D   case OPC_ADD_D
case OPC_SUB_D   case OPC_SUB_D
case OPC_MUL_D   case OPC_MUL_D
case OPC_DIV_D   case OPC_DIV_D
case OPC_SQRT_D  case OPC_SQRT_D   
  case OPC_ABS_D  -| case OPC_MOV_D
case OPC_MOV_D |-->case OPC_ABS_D  
  case OPC_NEG_D   case OPC_NEG_D  
case OPC_ROUND_L_D |-->  case OPC_CVT_L_D  
case OPC_TRUNC_L_D | case OPC_ROUND_L_D
case OPC_CEIL_L_D  | case OPC_TRUNC_L_D
case OPC_FLOOR_L_D | case OPC_CEIL_L_D 
case OPC_ROUND_W_D | case OPC_FLOOR_L_D
case OPC_TRUNC_W_D |  |--->  case OPC_CVT_W_D  

Re: [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit

[Aleksandar Markovic]

Hi, Leon,

There is one more subtle point here. The question is: Where to put declarations 
of two new functions? This is a new case in the organization of mips-specific 
source code files. File helpers.h does not seem to be a good place, cpu.h - 
maybe, but still looks clumsy to me.

IMHO, my solution from earlier versions of this patch series, in spite of 
containing code duplication, is superior in the sense of keeping current 
mips-specific source code file relations intact, respecting autonomy of 
msa_helpers.c, and is the best overall.

Yours,
Aleksandar


From: Leon Alrae
Sent: Friday, April 15, 2016 3:41 AM
To: Aleksandar Markovic; Aleksandar Markovic; qemu-devel@nongnu.org
Cc: pro...@gmail.com; kbast...@mail.uni-paderborn.de; 
mark.cave-ayl...@ilande.co.uk; ag...@suse.de; blauwir...@gmail.com; 
jcmvb...@gmail.com; qemu-...@nongnu.org; qemu-...@nongnu.org; Petar Jovanovic; 
pbonz...@redhat.com; Miodrag Dinic; edgar.igles...@gmail.com; 
g...@mprc.pku.edu.cn; afaer...@suse.de; aurel...@aurel32.net; r...@twiddle.net; 
Maciej Rozycki
Subject: Re: [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning 
of signaling NaN bit

On 15/04/16 09:48, Aleksandar Markovic wrote:
> Agreed. This looks much better, and is simpler and faster. Though, it looks 
> to me that "fst" should be called "status" instead (just not to break 
> consistency throughout SoftFloat library and in other places of assigning 
> name "status" to the last argument of any function if its type is 
> float_status*). If you agree, I am going to replace name "fst" with name 
> "status" in the code that you provided, otherwise as-is.

Yes, "status" will be fine.

Leon

Re: [Qemu-devel] [PATCH v6 0/9] IEEE 754-2008 support for Mips

[Aleksandar Markovic]

ping

From: Aleksandar Markovic [aleksandar.marko...@rt-rk.com]
Sent: Monday, May 16, 2016 7:12 AM
To: qemu-devel@nongnu.org
Cc: peter.mayd...@linaro.org; pro...@gmail.com; kbast...@mail.uni-paderborn.de; 
mark.cave-ayl...@ilande.co.uk; ag...@suse.de; blauwir...@gmail.com; 
jcmvb...@gmail.com; Aleksandar Markovic; qemu-...@nongnu.org; 
qemu-...@nongnu.org; Petar Jovanovic; pbonz...@redhat.com; Miodrag Dinic; 
edgar.igles...@gmail.com; g...@mprc.pku.edu.cn; Leon Alrae; afaer...@suse.de; 
aurel...@aurel32.net; r...@twiddle.net; Maciej Rozycki
Subject: [PATCH v6 0/9] IEEE 754-2008 support for Mips

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

v6 - code for hanlding MSA FCLASS instructions slightly simplified.
   - handling of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> corrected for
 nan2008 case.
   - R/W bitmask for FCR31 introduced, and related functionalities
 implemented.
   - cleanup items for SoftFloat library are now in a separate patch.
   - minor errors corrected.

v5 - platform initialization code revisited one more time.
   - handling of CLASS.<S|D> and their MSA counterparts revisited.
   - better orgranization of patches (squashing, splitting).
   - corrected handling of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>.
   - code cleanup item in genfarith() - order of cases.
   - scripts/checkpatch.pl executed and errors addressed.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg02774.html)

v4 - Added code cleanup items:
   a. Capitalization of hex constants in softfloat-specialize.h;
   b. White spaces in softfloat-specialize.h;
   c. Order of Mips helpers for CVT.<L|W>.<S|D>.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01962.html)

v3 - Patch series reorganized into 6 patches instead of 2.
   - Commit messages improved.
   - Except commit messages, net result of applying v3 and v2 is the same.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01870.html)

v2 - Relevant CPU initialization code changes revisited for all platforms.
   - In connection with <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> and
 <ABS|NEG>.<S|D> Mips instructions handling, decision on whether
 pre-nan2008/pre-abs2008 or nan2008/abs2008 handling will apply
 moved from run-time to translate-time.
   - For Mips only, in nan2008 cases only, default NaN values fixed.
   - For Mips only, in nan2008 cases only, order in pickNaNMulAdd() fixed.
   - Code cleanup issues:
   a. Constants <floatx80|float128>_default_nan_<low|high> removed;
   b. Suffix <l|w>_<s|d> replaced with _<l|w>_<s|d> for some Mips helpers;
   c. In vicinity of changes, fixed not-beautiful code formatting.
   - Commit messages improved.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01232.html)

v1 - Initial version
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg06082.html)

Mips platform represents the most complex case among QEMU-supported
platforms in reference to certain aspects of floating-point arithmetics.
This is mostly a consequence of the fact that Mips platform, for many
reasons, evolved considerably over time related to floating-point
arithmetics standards (significantly more than other platforms).
It has been difficult for emulators like QEMU to support such variety
of configurations.

This patch series provides number of IEEE 754-2008-related features to
Mips platform. It addresses the most sensitive changes that require
modification of SoftFloat library, also used by most other platforms.

In order to make develpoment, testing, and integration easier, the patch
is split into two distinct parts:

   1. Part 1 (patches 1/9, 2/9, 3/9, 4/9, 5/9) that does not change any
  calculation or behavior on any platform (and, for that matter, even on
  Mips platform). Its sole purpose is to address platform independant
  issues in a non-invasive manner, and to make Part 2 possible.

   2. Part 2 (patches 6/9, 7/9, 8/9, 9/9) that sets some Mips processors to
  use provisions from Part 1, and additionally implements number of
  IEEE 754-2008-related features for Mips, while, at the same time,
  dealing with files located in directory target-mips only.

This patch series is based on the original set of patches proposed by Maciej W.
Rozycki: http://lists.nongnu.org/archive/html/qemu-devel/2014-12/msg00968.html

Aleksandar Markovic (9):
  softfloat: Implement run-time-configurable meaning of signaling NaN bit
  softfloat: Clean code format in fpu/softfloat-specialize.h
  softfloat: For Mips only, correct default NaN values
  softfloat: For Mips only, correct order in pickNaNMulAdd()
  linux-user: Update preprocessor constants for Mips-specific e_flags bits
  target-mips: Activate IEEE 754-2008 signaling NaN bit meaning
  target-mips

[Qemu-devel] [PATCH v4 5/5] linux-user: Fix certain argument alignment cases for Mips64

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

The function that is changed in this patch is supposed to indicate that
there was certaing argument rearangement related to 64-bit arguments on
32-bit platforms. The background on such rearangements can be found,
for example, in the man page for syscall(2).

However, for 64-bit Mips architectures there is no such rearangement,
and this patch reflects it.

Signed-off-by: Aleksandar Rikalo <aleksandar.rik...@imgtec.com>
---
 linux-user/syscall.c |8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 908f114..6ac669f 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -622,7 +622,13 @@ static inline int regpairs_aligned(void *cpu_env) {
 return CPUARMState *)cpu_env)->eabi) == 1) ;
 }
 #elif defined(TARGET_MIPS)
-static inline int regpairs_aligned(void *cpu_env) { return 1; }
+static inline int regpairs_aligned(void *cpu_env) {
+#if TARGET_ABI_BITS == 32
+return 1;
+#else
+return 0;
+#endif
+}
 #elif defined(TARGET_PPC) && !defined(TARGET_PPC64)
 /* SysV AVI for PPC32 expects 64bit parameters to be passed on odd/even pairs
  * of registers which translates to the same as ARM/MIPS, because we start with
-- 
1.7.9.5

[Qemu-devel] [PATCH v2 0/3] linux-user: Add support for adjtimex(), sysfs(), and ustat() syscalls

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

v1->v2:
- added "#ifdef TARGET_NR_adjtimex" where appropriate in patch 1/3.

This patch series adds support for three syscalls to the Qemu user mode.

Each patch fixes certain LTP test failures that occur if LTP tests are
executed in Qemu user mode. This improvement will affect all platforms
supported by Qemu. Altogether, there are 10 LTP tests fixed by this series.

Where needed, the support for "-strace" switch is included as well.

For each patch, a minimal test example is created that demonstrates
the correctness of the implementation, and such example is compiled and
tested on arm, i386, mips, mipsel, ppc, sh4, and sparc platforms.

All patches are checked with scripts/checkpatch.pl.

Aleksandar Markovic (3):
  linux-user: Add support for adjtimex() syscall
  linux-user: Add support for sysfs() syscall
  linux-user: Add support for ustat() syscall

 linux-user/strace.c   |   37 +++
 linux-user/strace.list|4 +-
 linux-user/syscall.c  |  157 -
 linux-user/syscall_defs.h |   28 
 4 files changed, 221 insertions(+), 5 deletions(-)

-- 
1.7.9.5

[Qemu-devel] [PATCH v4 0/5] linux-user: Fix miscellaneous Mips-specific issues

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

v3->v4:

  - Added a patch on agrument rearangement.

v2 -> v3:

  - Minor fixes in the commit messages.

v1 -> v2:

  - Improved a comment in the patch about target_semid64_ds (now 4/4).
  - Added a patch that fixes TARGET_SIOCATMARK for Mips.
  - Changed order of patches to be more structured.

This series fixes several wrong definitions of preprocessor constants and
structures in Qemu user mode.

It also fixes certain number of LTP test failures, if executed in Qemu
user mode for Mips platform.

All patches from this series affect Mips platform only.

Aleksandar Markovic (5):
  linux-user: Fix TARGET_SIOCATMARK definition for Mips
  linux-user: Fix TARGET_F_GETOWN definition for Mips
  linux-user: Fix structure target_flock definition for Mips
  linux-user: Fix structure target_semid64_ds definition for Mips
  linux-user: Fix certain argument alignment cases for Mips64

 linux-user/mips/target_structs.h |   16 
 linux-user/syscall.c |8 +++-
 linux-user/syscall_defs.h|   12 +++-
 3 files changed, 34 insertions(+), 2 deletions(-)

-- 
1.7.9.5

[Qemu-devel] [PATCH v2 1/5] linux-user: Fix syslog() syscall emulation

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

There are currently several problems related to syslog() support.

For example, if the second argument "bufp" of target syslog() syscall
is NULL, the current implementation always returns error code EFAULT.
However, NULL is a perfectly valid value for the second argument for
many use cases of this syscall. This is, for example, visible from
this excerpt of man page for syslog(2):

> EINVAL Bad arguments (e.g., bad type; or for type 2, 3, or 4, buf is
>NULL, or len is less than zero; or for type 8, the level is
>outside the range 1 to 8).

Moreover, the argument "bufp" is ignored for all cases of values of the
first argument, except 2, 3 and 4. This means that for such cases
(the first argument is not 2, 3 or 4), there is no need to pass "buf"
between host and target, and it can be set to NULL while calling host's
syslog(), without loss of emulation accuracy.

Note also that if "bufp" is NULL and the first argument is 2, 3 or 4, the
correct returned error code is EINVAL, not EFAULT.

All these details are reflected in this patch.

"#ifdef TARGET_NR_syslog" is also proprerly inserted when needed.

Support for Qemu's "-strace" switch for syslog() syscall is included too.

LTP tests syslog11 and syslog12 pass with this patch (while fail without
it), on any platform.

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 linux-user/strace.c   |   68 +
 linux-user/strace.list|2 +-
 linux-user/syscall.c  |   23 +++
 linux-user/syscall_defs.h |   25 +
 4 files changed, 111 insertions(+), 7 deletions(-)

diff --git a/linux-user/strace.c b/linux-user/strace.c
index cc10dc4..ccefc5c 100644
--- a/linux-user/strace.c
+++ b/linux-user/strace.c
@@ -1684,6 +1684,74 @@ print_rt_sigprocmask(const struct syscallname *name,
 }
 #endif
 
+#ifdef TARGET_NR_syslog
+static void
+print_syslog_action(abi_ulong arg, int last)
+{
+switch (arg) {
+case TARGET_SYSLOG_ACTION_CLOSE: {
+gemu_log("%s%s", "SYSLOG_ACTION_CLOSE", get_comma(last));
+break;
+}
+case TARGET_SYSLOG_ACTION_OPEN: {
+gemu_log("%s%s", "SYSLOG_ACTION_OPEN", get_comma(last));
+break;
+}
+case TARGET_SYSLOG_ACTION_READ: {
+gemu_log("%s%s", "SYSLOG_ACTION_READ", get_comma(last));
+break;
+}
+case TARGET_SYSLOG_ACTION_READ_ALL: {
+gemu_log("%s%s", "SYSLOG_ACTION_READ_ALL", get_comma(last));
+break;
+}
+case TARGET_SYSLOG_ACTION_READ_CLEAR: {
+gemu_log("%s%s", "SYSLOG_ACTION_READ_CLEAR", get_comma(last));
+break;
+}
+case TARGET_SYSLOG_ACTION_CLEAR: {
+gemu_log("%s%s", "SYSLOG_ACTION_CLEAR", get_comma(last));
+break;
+}
+case TARGET_SYSLOG_ACTION_CONSOLE_OFF: {
+gemu_log("%s%s", "SYSLOG_ACTION_CONSOLE_OFF", get_comma(last));
+break;
+}
+case TARGET_SYSLOG_ACTION_CONSOLE_ON: {
+gemu_log("%s%s", "SYSLOG_ACTION_CONSOLE_ON", get_comma(last));
+break;
+}
+case TARGET_SYSLOG_ACTION_CONSOLE_LEVEL: {
+gemu_log("%s%s", "SYSLOG_ACTION_CONSOLE_LEVEL", get_comma(last));
+break;
+}
+case TARGET_SYSLOG_ACTION_SIZE_UNREAD: {
+gemu_log("%s%s", "SYSLOG_ACTION_SIZE_UNREAD", get_comma(last));
+break;
+}
+case TARGET_SYSLOG_ACTION_SIZE_BUFFER: {
+gemu_log("%s%s", "SYSLOG_ACTION_SIZE_BUFFER", get_comma(last));
+break;
+}
+default: {
+print_raw_param("%ld", arg, last);
+}
+}
+}
+
+static void
+print_syslog(const struct syscallname *name,
+abi_long arg0, abi_long arg1, abi_long arg2,
+abi_long arg3, abi_long arg4, abi_long arg5)
+{
+print_syscall_prologue(name);
+print_syslog_action(arg0, 0);
+print_pointer(arg1, 0);
+print_raw_param("%d", arg2, 1);
+print_syscall_epilogue(name);
+}
+#endif
+
 #ifdef TARGET_NR_mknod
 static void
 print_mknod(const struct syscallname *name,
diff --git a/linux-user/strace.list b/linux-user/strace.list
index aa967a2..9f4932c 100644
--- a/linux-user/strace.list
+++ b/linux-user/strace.list
@@ -1377,7 +1377,7 @@
 { TARGET_NR_sys_kexec_load, "sys_kexec_load" , NULL, NULL, NULL },
 #endif
 #ifdef TARGET_NR_syslog
-{ TARGET_NR_syslog, "syslog" , NULL, NULL, NULL },
+{ TARGET_NR_syslog, "syslog" , NULL, print_syslog, NULL },
 #endif
 #ifdef TARGET_NR

[Qemu-devel] [PATCH v2 2/3] linux-user: Add support for sysfs() syscall

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch implements Qemu user mode sysfs() syscall support.

Syscall sysfs() involves returning information about the filesystem types
currently present in the kernel, and can operate in three distinct flavors,
depending on its first argument.

The implementation is based on invocation of host's sysfs(), and
its key part is in the correspondent case segment of the main switch
statement of the function do_syscall(), in file linux-user/syscalls.c.
All necessary conversions of data structures from target to host and from
host to target are covered. Based on the value of the first argument, three
cases are distinguished, and such conversions are implemented separately
for each case. Relevant support for "-strace" option is included in files
linux-user/strace.c and linux-user/strace.list.

This patch also fixes failures of LTP tests sysfs01, sysfs02, sysfs03,
sysfs04, sysfs05, and sysfs06, if executed in Qemu user mode.

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 linux-user/strace.c|   25 +
 linux-user/strace.list |2 +-
 linux-user/syscall.c   |   42 +-
 3 files changed, 67 insertions(+), 2 deletions(-)

diff --git a/linux-user/strace.c b/linux-user/strace.c
index 7ddcaf8..a52ff58 100644
--- a/linux-user/strace.c
+++ b/linux-user/strace.c
@@ -2138,6 +2138,31 @@ print_kill(const struct syscallname *name,
 }
 #endif
 
+#if defined(TARGET_NR_sysfs)
+static void
+print_sysfs(const struct syscallname *name,
+abi_long arg0, abi_long arg1, abi_long arg2,
+abi_long arg3, abi_long arg4, abi_long arg5)
+{
+print_syscall_prologue(name);
+switch (arg0) {
+case 1:
+print_raw_param("%d", arg0, 1);
+print_string(arg1, 1);
+break;
+case 2:
+print_raw_param("%d", arg0, 0);
+print_raw_param("%u", arg1, 0);
+print_pointer(arg2, 1);
+break;
+default:
+print_raw_param("%d", arg0, 1);
+break;
+}
+print_syscall_epilogue(name);
+}
+#endif
+
 /*
  * An array of all of the syscalls we know about
  */
diff --git a/linux-user/strace.list b/linux-user/strace.list
index 9a665a8..e8133b0 100644
--- a/linux-user/strace.list
+++ b/linux-user/strace.list
@@ -1368,7 +1368,7 @@
 { TARGET_NR_sys_epoll_wait, "sys_epoll_wait" , NULL, NULL, NULL },
 #endif
 #ifdef TARGET_NR_sysfs
-{ TARGET_NR_sysfs, "sysfs" , NULL, NULL, NULL },
+{ TARGET_NR_sysfs, "sysfs" , NULL, print_sysfs, NULL },
 #endif
 #ifdef TARGET_NR_sysinfo
 { TARGET_NR_sysinfo, "sysinfo" , NULL, NULL, NULL },
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 5643840..38d69f1 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -9532,7 +9532,47 @@ abi_long do_syscall(void *cpu_env, int num, abi_long 
arg1,
 #endif
 #ifdef TARGET_NR_sysfs
 case TARGET_NR_sysfs:
-goto unimplemented;
+switch (arg1) {
+case 1:
+{
+if (arg2 != 0) {
+p = lock_user_string(arg2);
+if (!p) {
+goto efault;
+}
+ret = get_errno(syscall(__NR_sysfs, arg1, p));
+unlock_user(p, arg2, 0);
+} else {
+ret = get_errno(syscall(__NR_sysfs, arg1, NULL));
+}
+}
+break;
+case 2:
+{
+if (arg3 != 0) {
+char buf[PATH_MAX];
+int len;
+memset(buf, 0, PATH_MAX);
+ret = get_errno(syscall(__NR_sysfs, arg1, arg2, buf));
+len = PATH_MAX;
+if (len > strlen(buf)) {
+len = strlen(buf);
+}
+if (copy_to_user(arg3, buf, len) != 0) {
+goto efault;
+}
+} else {
+ret = get_errno(syscall(__NR_sysfs, arg1, arg2, NULL));
+}
+}
+break;
+case 3:
+ret = get_errno(syscall(__NR_sysfs, arg1));
+break;
+default:
+ret = -EINVAL;
+}
+break;
 #endif
 case TARGET_NR_personality:
 ret = get_errno(personality(arg1));
-- 
1.7.9.5

[Qemu-devel] [PATCH v2 0/5] linux user: Fix assorted Qemu user mode issues

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

v1->v2:

- improved usage of "#ifdefs" in patch on syslog()
- removed EIDRM-related code from patch on msgrcv(), since this error
  code is already handled well
- added three cleanup patches

(also, v1 for some reason did not appear on qemu-devel, but mails are sent)

This series fix certain Qemu user mode issues. The fixes mainly originate
from observation of LTP tests failures for execution in Qemu user mode
on various platforms. The series also contains three cleanup patches.

Aleksandar Markovic (5):
  linux-user: Fix syslog() syscall emulation
  linux-user: Fix msgrcv() and msgsnd() syscalls emulation
  linux-user: Remove tabs and trailing spaces from linux-user/main.c
  linux-user: Remove a duplicate item from strace.list
  linux-user: Insert missing #ifdefs for some syscalls

 linux-user/main.c |  812 ++---
 linux-user/strace.c   |   68 
 linux-user/strace.list|5 +-
 linux-user/syscall.c  |   38 ++-
 linux-user/syscall_defs.h |   25 ++
 5 files changed, 532 insertions(+), 416 deletions(-)

-- 
1.7.9.5

[Qemu-devel] [PATCH v2 2/5] linux-user: Fix msgrcv() and msgsnd() syscalls emulation

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

If syscalls msgrcv() and msgsnd() fail, they return E2BIG, EACCES,
EAGAIN, EFAULT, EIDRM, EINTR, EINVAL, ENOMEM, or ENOMSG.

By examining negative scenarios of these syscalls for Mips, it was
established that ENOMSG does not have the same value accross all
platforms, but it is nevertheless not included for conversion in
the correspondant conversion table defined in linux-user/syscall.c.
This is certainly a bug, since it leads to the incorrect emulation
of msgrcv() and msgsnd() for scenarios involving ENOMSG.

This patch fixes this by extending the conversion table to include
ENOMSG.

Also, LTP test msgrcv04 will be fixed for some platforms.

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 linux-user/syscall.c |3 +++
 1 file changed, 3 insertions(+)

diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index c8ccc00..b5d8507 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -748,6 +748,9 @@ static uint16_t 
host_to_target_errno_table[ERRNO_TABLE_SIZE] = {
 #ifdef ENOTRECOVERABLE
 [ENOTRECOVERABLE]  = TARGET_ENOTRECOVERABLE,
 #endif
+#ifdef ENOMSG
+[ENOMSG]= TARGET_ENOMSG,
+#endif
 };
 
 static inline int host_to_target_errno(int err)
-- 
1.7.9.5

[Qemu-devel] [PATCH v2 1/3] linux-user: Add support for adjtimex() syscall

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch implements Qemu user mode adjtimex() syscall support.

Syscall adjtimex() reads and optionally sets parameters for a clock
adjustment algorithm used in network synchonization or similar scenarios.

The implementation is based on invocation of host's adjtimex(), and
its key part is in the correspondent case segment of the main switch
statement of the function do_syscall(), in file linux-user/syscalls.c.
Also, support for related structure "timex" is added to the file
linux-user/syscall_defs.h, based on its definition in Linux kernel. All
necessary conversions of the data structures from target to host and from
host to target are covered. Two new functions, target_to_host_timex() and
host_to_target_timex(), are provided for the purpose of such conversions.
Moreover, the relevant support for "-strace" Qemu option is included in
files linux-user/strace.c and linux-user/strace.list.

This patch also fixes failures of LTP tests adjtimex01 and adjtimex02, if
executed in Qemu user mode.

Signed-off-by: Aleksandar Rikalo <aleksandar.rik...@imgtec.com>
---
 linux-user/strace.c   |   12 ++
 linux-user/strace.list|2 +-
 linux-user/syscall.c  |   90 -
 linux-user/syscall_defs.h |   28 ++
 4 files changed, 130 insertions(+), 2 deletions(-)

diff --git a/linux-user/strace.c b/linux-user/strace.c
index cc10dc4..7ddcaf8 100644
--- a/linux-user/strace.c
+++ b/linux-user/strace.c
@@ -919,6 +919,18 @@ print_access(const struct syscallname *name,
 }
 #endif
 
+#ifdef TARGET_NR_adjtimex
+static void
+print_adjtimex(const struct syscallname *name,
+abi_long arg0, abi_long arg1, abi_long arg2,
+abi_long arg3, abi_long arg4, abi_long arg5)
+{
+print_syscall_prologue(name);
+print_pointer(arg0, 1);
+print_syscall_epilogue(name);
+}
+#endif
+
 #ifdef TARGET_NR_brk
 static void
 print_brk(const struct syscallname *name,
diff --git a/linux-user/strace.list b/linux-user/strace.list
index aa967a2..9a665a8 100644
--- a/linux-user/strace.list
+++ b/linux-user/strace.list
@@ -16,7 +16,7 @@
 { TARGET_NR_add_key, "add_key" , NULL, NULL, NULL },
 #endif
 #ifdef TARGET_NR_adjtimex
-{ TARGET_NR_adjtimex, "adjtimex" , NULL, NULL, NULL },
+{ TARGET_NR_adjtimex, "adjtimex" , NULL, print_adjtimex, NULL },
 #endif
 #ifdef TARGET_NR_afs_syscall
 { TARGET_NR_afs_syscall, "afs_syscall" , NULL, NULL, NULL },
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index ca06943..5643840 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -35,6 +35,7 @@
 #include 
 #include 
 #include 
+#include 
 #ifdef __ia64__
 int __clone2(int (*fn)(void *), void *child_stack_base,
  size_t stack_size, int flags, void *arg, ...);
@@ -6578,6 +6579,78 @@ static inline abi_long target_ftruncate64(void *cpu_env, 
abi_long arg1,
 }
 #endif
 
+#ifdef TARGET_NR_adjtimex
+static inline abi_long target_to_host_timex(struct timex *host_buf,
+abi_long target_addr)
+{
+struct target_timex *target_buf;
+
+if (!lock_user_struct(VERIFY_READ, target_buf, target_addr, 1)) {
+return -TARGET_EFAULT;
+}
+
+host_buf->modes = tswap32(target_buf->modes);
+host_buf->offset = tswapal(target_buf->offset);
+host_buf->freq = tswapal(target_buf->freq);
+host_buf->maxerror = tswapal(target_buf->maxerror);
+host_buf->esterror = tswapal(target_buf->esterror);
+host_buf->status = tswap32(target_buf->status);
+host_buf->constant = tswapal(target_buf->constant);
+host_buf->precision = tswapal(target_buf->precision);
+host_buf->tolerance = tswapal(target_buf->tolerance);
+host_buf->time.tv_sec = tswapal(target_buf->time.tv_sec);
+host_buf->time.tv_usec = tswapal(target_buf->time.tv_usec);
+host_buf->tick = tswapal(target_buf->tick);
+host_buf->ppsfreq = tswapal(target_buf->ppsfreq);
+host_buf->jitter = tswapal(target_buf->jitter);
+host_buf->shift = tswap32(target_buf->shift);
+host_buf->stabil = tswapal(target_buf->stabil);
+host_buf->jitcnt = tswapal(target_buf->jitcnt);
+host_buf->calcnt = tswapal(target_buf->calcnt);
+host_buf->errcnt = tswapal(target_buf->errcnt);
+host_buf->stbcnt = tswapal(target_buf->stbcnt);
+host_buf->tai = tswap32(target_buf->tai);
+
+unlock_user_struct(target_buf, target_addr, 0);
+return 0;
+}
+
+static inline abi_long host_to_target_timex(abi_long target_addr,
+struct timex *host_buf)
+{
+struct target_timex *target_buf;
+
+if (!lock_user_struct(VERIFY_WRITE, target_buf, target_addr, 0)) {
+return -TARGET_EFAULT;
+}
+
+target_buf->modes = tswap32(host_buf->modes);

[Qemu-devel] [PATCH v4 3/5] linux-user: Fix structure target_flock definition for Mips

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Structure flock is defined for Mips in a way different from any
other platform. For reference, see Linux kernel source code files:

arch/mips/include/uapi/asm/fcntl.h#L63 (for Mips)
include/uapi/asm-generic/fcntl.h#L195 (for all other platforms)

This patch fix this problem, by amending structure target_flock,
for Mips only.

Besides, this patch fixes LTP tests fcntl11, fcntl17, fcntl19, fcntl20,
and fcntl21, which are currently failing, if executed in Qemu user mode
for Mips platforms.

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 linux-user/syscall_defs.h |6 ++
 1 file changed, 6 insertions(+)

diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 27d93a8..63527a7 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -2355,7 +2355,13 @@ struct target_flock {
 short l_whence;
 abi_long l_start;
 abi_long l_len;
+#if defined(TARGET_MIPS)
+target_long l_sysid;
+#endif
 int l_pid;
+#if defined(TARGET_MIPS)
+target_long pad[4];
+#endif
 };
 
 struct target_flock64 {
-- 
1.7.9.5

[Qemu-devel] [PATCH v4 2/5] linux-user: Fix TARGET_F_GETOWN definition for Mips

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

For some reason, Qemu's TARGET_F_GETOWN constant for Mips does not
match the correct value of correspondant F_GETOWN. This patch fixes
this problem.

For reference, see Mips' F_GETOWN definition in Linux kernel at
arch/mips/include/uapi/asm/fcntl.h#L44.

This patch also fixes some fcntl()-related LTP tests for Qemu
user mode for Mips.

Signed-off-by: Miodrag Dinic <miodrag.di...@imgtec.com>
---
 linux-user/syscall_defs.h |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index e6171ae..27d93a8 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -2186,7 +2186,7 @@ struct target_statfs64 {
 #define TARGET_F_SETLK 6
 #define TARGET_F_SETLKW7
 #define TARGET_F_SETOWN24   /*  for sockets. */
-#define TARGET_F_GETOWN25   /*  for sockets. */
+#define TARGET_F_GETOWN23   /*  for sockets. */
 #else
 #define TARGET_F_GETLK 5
 #define TARGET_F_SETLK 6
-- 
1.7.9.5

[Qemu-devel] [PATCH v4 1/5] linux-user: Fix TARGET_SIOCATMARK definition for Mips

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch fixes wrong definition of TARGET_SIOCATMARK for Mips.

The current definition is:

  #define SIOCATMARK  0x8905

while the correct definition is:

  #define SIOCATMARK  TARGET_IOR('s', 7, int)

See Linux kernel source file arch/mips/include/uapi/asm/sockios.h#L19
for reference.

This patch also a fixes LTP test failure for test sockioctl01, for Mips.

Signed-off-by: Aleksandar Rikalo <aleksandar.rik...@imgtec.com>
---
 linux-user/syscall_defs.h |4 
 1 file changed, 4 insertions(+)

diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index afd9191..e6171ae 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -926,7 +926,11 @@ struct target_pollfd {
 #define TARGET_KDSETLED0x4B32  /* set led state [lights, not flags] */
 #define TARGET_KDSIGACCEPT 0x4B4E
 
+#if defined(TARGET_MIPS)
+#define TARGET_SIOCATMARK  TARGET_IOR('s', 7, int)
+#else
 #define TARGET_SIOCATMARK  0x8905
+#endif
 
 /* Networking ioctls */
 #define TARGET_SIOCADDRT   0x890B  /* add routing table entry */
-- 
1.7.9.5

[Qemu-devel] [PATCH v4 4/5] linux-user: Fix structure target_semid64_ds definition for Mips

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch corrects target_semid64_ds structure definition for Mips.

See, for example definition of semid64_ds for Mips in Linux kernel:
arch/mips/include/uapi/asm/sembuf.h#L13.

This patch will also fix certain semaphore-related LTP tests for Mips,
if they are executed in Qemu user mode for any Mips platform.

Signed-off-by: Miodrag Dinic <miodrag.di...@imgtec.com>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
---
 linux-user/mips/target_structs.h |   16 
 1 file changed, 16 insertions(+)

diff --git a/linux-user/mips/target_structs.h b/linux-user/mips/target_structs.h
index fbd9955..5ba124d 100644
--- a/linux-user/mips/target_structs.h
+++ b/linux-user/mips/target_structs.h
@@ -45,4 +45,20 @@ struct target_shmid_ds {
 abi_ulong __unused2;
 };
 
+#define TARGET_SEMID64_DS
+
+/*
+ * The semid64_ds structure for the MIPS architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ */
+struct target_semid64_ds {
+struct target_ipc_perm sem_perm;
+abi_ulong sem_otime;
+abi_ulong sem_ctime;
+abi_ulong sem_nsems;
+abi_ulong __unused3;
+abi_ulong __unused4;
+};
+
 #endif
-- 
1.7.9.5

[Qemu-devel] [PATCH v2 4/5] linux-user: Remove a duplicate item from strace.list

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

There is a duplicate item in strace.list. It is benign, but it
shouldn't be there. It is the only duplicate in strace.list. This
patch removes it.

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 linux-user/strace.list |3 ---
 1 file changed, 3 deletions(-)

diff --git a/linux-user/strace.list b/linux-user/strace.list
index 9f4932c..84f06fb 100644
--- a/linux-user/strace.list
+++ b/linux-user/strace.list
@@ -1529,9 +1529,6 @@
 #ifdef TARGET_NR_utimensat
 { TARGET_NR_utimensat, "utimensat", NULL, print_utimensat, NULL },
 #endif
-#ifdef TARGET_NR_sync_file_range
-{ TARGET_NR_sync_file_range, "sync_file_range", NULL, NULL, NULL },
-#endif
 #ifdef TARGET_NR_sync_file_range2
 { TARGET_NR_sync_file_range2, "sync_file_range2", NULL, NULL, NULL },
 #endif
-- 
1.7.9.5

[Qemu-devel] [PATCH v2 3/3] linux-user: Add support for ustat() syscall

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

This patch implements Qemu user mode ustat() syscall support.

Syscall ustat() returns information about a mounted filesystem.

The implementation is similar to the implementations of statfs(),
fstatfs() and other related syscalls. It is based on invocation of
host's ustat(), and its key part is in the correspondent case segment
of the main switch statement of the function do_syscall(), in file
linux-user/syscalls.c. All necessary conversions of data structures
from target to host and from host to target are covered. Sufficient
support for "-strace" option for this syscall is already present,
and this patch does not change it.

This patch also fixes failures of LTP tests ustat01, and ustat02, if
executed on Qemu-emulated systems.

Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 linux-user/syscall.c |   25 -
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 38d69f1..b118bd9 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -48,6 +48,7 @@ int __clone2(int (*fn)(void *), void *child_stack_base,
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -8098,7 +8099,29 @@ abi_long do_syscall(void *cpu_env, int num, abi_long 
arg1,
 break;
 #ifdef TARGET_NR_ustat
 case TARGET_NR_ustat:
-goto unimplemented;
+{
+struct ustat ust;
+int cnt;
+ret = get_errno(ustat(arg1, ));
+
+if (!is_error(ret)) {
+struct ustat *target_ust;
+
+if (!lock_user_struct(VERIFY_WRITE, target_ust, arg2, 0)) {
+goto efault;
+}
+
+__put_user(ust.f_tfree, _ust->f_tfree);
+__put_user(ust.f_tinode, _ust->f_tinode);
+
+for (cnt = 0; cnt < 6; cnt++) {
+__put_user(ust.f_fname[cnt], _ust->f_fname[cnt]);
+__put_user(ust.f_fpack[cnt], _ust->f_fpack[cnt]);
+}
+unlock_user_struct(target_ust, arg2, 1);
+}
+break;
+  }
 #endif
 #ifdef TARGET_NR_dup2
 case TARGET_NR_dup2:
-- 
1.7.9.5