CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Thu Apr 18 16:40:17 UTC 2024
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: viac7temp.c
Log Message:
Pull up following revision(s) (requested by andvar in ticket #1835):
sys/arch/x86/x86/viac7temp.c: revision 1.10
viac7temp(4): define module metadata using MODULE() macro and implement
viac7temp_modcmd() to handle module load/unload events.
Fixes PR kern/58148. Look OK by mrg@.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.8.32.1 src/sys/arch/x86/x86/viac7temp.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/viac7temp.c
diff -u src/sys/arch/x86/x86/viac7temp.c:1.8 src/sys/arch/x86/x86/viac7temp.c:1.8.32.1
--- src/sys/arch/x86/x86/viac7temp.c:1.8 Sun Aug 10 16:44:34 2014
+++ src/sys/arch/x86/x86/viac7temp.c Thu Apr 18 16:40:17 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: viac7temp.c,v 1.8 2014/08/10 16:44:34 tls Exp $ */
+/* $NetBSD: viac7temp.c,v 1.8.32.1 2024/04/18 16:40:17 martin Exp $ */
/*-
* Copyright (c) 2009 Jared D. McNeill
@@ -27,11 +27,12 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: viac7temp.c,v 1.8 2014/08/10 16:44:34 tls Exp $");
+__KERNEL_RCSID(0, "$NetBSD: viac7temp.c,v 1.8.32.1 2024/04/18 16:40:17 martin Exp $");
#include
#include
#include
+#include
#include
#include
@@ -162,3 +163,32 @@ viac7temp_refresh_xcall(void *arg0, void
edata->value_cur += 27315;
edata->state = ENVSYS_SVALID;
}
+
+MODULE(MODULE_CLASS_DRIVER, viac7temp, NULL);
+
+#ifdef _MODULE
+#include "ioconf.c"
+#endif
+
+static int
+viac7temp_modcmd(modcmd_t cmd, void *arg __unused)
+{
+ int error = 0;
+
+ switch (cmd) {
+ case MODULE_CMD_INIT:
+#ifdef _MODULE
+ error = config_init_component(cfdriver_ioconf_viac7temp,
+ cfattach_ioconf_viac7temp, cfdata_ioconf_viac7temp);
+#endif
+ return error;
+ case MODULE_CMD_FINI:
+#ifdef _MODULE
+ error = config_fini_component(cfdriver_ioconf_viac7temp,
+ cfattach_ioconf_viac7temp, cfdata_ioconf_viac7temp);
+#endif
+ return error;
+ default:
+ return ENOTTY;
+ }
+}
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Thu Apr 18 16:40:17 UTC 2024 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: viac7temp.c Log Message: Pull up following revision(s) (requested by andvar in ticket #1835): sys/arch/x86/x86/viac7temp.c: revision 1.10 viac7temp(4): define module metadata using MODULE() macro and implement viac7temp_modcmd() to handle module load/unload events. Fixes PR kern/58148. Look OK by mrg@. To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.8.32.1 src/sys/arch/x86/x86/viac7temp.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src Committed By: martin Date: Wed Aug 23 17:09:09 UTC 2023 Modified Files: src/sys/arch/x86/pci [netbsd-9]: pci_machdep.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #1722): sys/arch/x86/pci/pci_machdep.c: revision 1.94 Fix detection of availability of MSI/MSI-X on some systems. Try to find all functions on bus 0, device 0 to find a PCI host bridge. Some CPU's host bridge is at 0:0.4. Tested by Intel Snow Ridge. To generate a diff of this commit: cvs rdiff -u -r1.86 -r1.86.2.1 src/sys/arch/x86/pci/pci_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src
Committed By: martin
Date: Wed Aug 23 17:09:09 UTC 2023
Modified Files:
src/sys/arch/x86/pci [netbsd-9]: pci_machdep.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1722):
sys/arch/x86/pci/pci_machdep.c: revision 1.94
Fix detection of availability of MSI/MSI-X on some systems.
Try to find all functions on bus 0, device 0 to find a PCI host bridge.
Some CPU's host bridge is at 0:0.4. Tested by Intel Snow Ridge.
To generate a diff of this commit:
cvs rdiff -u -r1.86 -r1.86.2.1 src/sys/arch/x86/pci/pci_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/pci/pci_machdep.c
diff -u src/sys/arch/x86/pci/pci_machdep.c:1.86 src/sys/arch/x86/pci/pci_machdep.c:1.86.2.1
--- src/sys/arch/x86/pci/pci_machdep.c:1.86 Fri May 24 14:28:48 2019
+++ src/sys/arch/x86/pci/pci_machdep.c Wed Aug 23 17:09:09 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_machdep.c,v 1.86 2019/05/24 14:28:48 nonaka Exp $ */
+/* $NetBSD: pci_machdep.c,v 1.86.2.1 2023/08/23 17:09:09 martin Exp $ */
/*-
* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
@@ -73,7 +73,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.86 2019/05/24 14:28:48 nonaka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.86.2.1 2023/08/23 17:09:09 martin Exp $");
#include
#include
@@ -485,6 +485,8 @@ pci_attach_hook(device_t parent, device_
pci_chipset_tag_t pc = pba->pba_pc;
pcitag_t tag;
pcireg_t id, class;
+ int i;
+ bool havehb = false;
#endif
if (pba->pba_bus == 0)
@@ -502,19 +504,25 @@ pci_attach_hook(device_t parent, device_
#ifdef __HAVE_PCI_MSI_MSIX
/*
* In order to decide whether the system supports MSI we look
- * at the host bridge, which should be device 0 function 0 on
- * bus 0. It is better to not enable MSI on systems that
+ * at the host bridge, which should be device 0 on bus 0.
+ * It is better to not enable MSI on systems that
* support it than the other way around, so be conservative
* here. So we don't enable MSI if we don't find a host
* bridge there. We also deliberately don't enable MSI on
* chipsets from low-end manifacturers like VIA and SiS.
*/
- tag = pci_make_tag(pc, 0, 0, 0);
- id = pci_conf_read(pc, tag, PCI_ID_REG);
- class = pci_conf_read(pc, tag, PCI_CLASS_REG);
-
- if (PCI_CLASS(class) != PCI_CLASS_BRIDGE ||
- PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_HOST)
+ for (i = 0; i <= 7; i++) {
+ tag = pci_make_tag(pc, 0, 0, i);
+ id = pci_conf_read(pc, tag, PCI_ID_REG);
+ class = pci_conf_read(pc, tag, PCI_CLASS_REG);
+
+ if (PCI_CLASS(class) == PCI_CLASS_BRIDGE &&
+ PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_HOST) {
+ havehb = true;
+ break;
+ }
+ }
+ if (havehb == false)
return;
/* VMware and KVM use old chipset, but they can use MSI/MSI-X */
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src
Committed By: martin
Date: Tue Aug 22 16:10:21 UTC 2023
Modified Files:
src/sys/arch/x86/pci [netbsd-9]: amdsmn.c amdzentemp.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1720):
sys/arch/x86/pci/amdzentemp.c: revision 1.20
sys/arch/x86/pci/amdsmn.c: revision 1.17
sys/arch/x86/pci/amdzentemp.c: revision 1.19
Add Zen4 Ryzen "Phoenix" support.
Add Zen2 Mendocino APU support.
Add Zen4 Phoenix support.
To generate a diff of this commit:
cvs rdiff -u -r1.5.2.4 -r1.5.2.5 src/sys/arch/x86/pci/amdsmn.c
cvs rdiff -u -r1.9.2.4 -r1.9.2.5 src/sys/arch/x86/pci/amdzentemp.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/pci/amdsmn.c
diff -u src/sys/arch/x86/pci/amdsmn.c:1.5.2.4 src/sys/arch/x86/pci/amdsmn.c:1.5.2.5
--- src/sys/arch/x86/pci/amdsmn.c:1.5.2.4 Wed Jun 21 18:56:58 2023
+++ src/sys/arch/x86/pci/amdsmn.c Tue Aug 22 16:10:21 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: amdsmn.c,v 1.5.2.4 2023/06/21 18:56:58 martin Exp $ */
+/* $NetBSD: amdsmn.c,v 1.5.2.5 2023/08/22 16:10:21 martin Exp $ */
/*-
* Copyright (c) 2017, 2019 Conrad Meyer
@@ -29,7 +29,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: amdsmn.c,v 1.5.2.4 2023/06/21 18:56:58 martin Exp $ ");
+__KERNEL_RCSID(0, "$NetBSD: amdsmn.c,v 1.5.2.5 2023/08/22 16:10:21 martin Exp $ ");
/*
* Driver for the AMD Family 15h (model 60+) and 17h CPU
@@ -112,6 +112,11 @@ static const struct pciid {
.amdsmn_addr_reg = F17H_SMN_ADDR_REG,
.amdsmn_data_reg = F17H_SMN_DATA_REG,
},
+ {
+ .amdsmn_deviceid = PCI_PRODUCT_AMD_F19_7X_RC,
+ .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
+ .amdsmn_data_reg = F17H_SMN_DATA_REG,
+ },
};
static int amdsmn_match(device_t, cfdata_t, void *);
Index: src/sys/arch/x86/pci/amdzentemp.c
diff -u src/sys/arch/x86/pci/amdzentemp.c:1.9.2.4 src/sys/arch/x86/pci/amdzentemp.c:1.9.2.5
--- src/sys/arch/x86/pci/amdzentemp.c:1.9.2.4 Wed Jun 21 18:56:58 2023
+++ src/sys/arch/x86/pci/amdzentemp.c Tue Aug 22 16:10:21 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: amdzentemp.c,v 1.9.2.4 2023/06/21 18:56:58 martin Exp $ */
+/* $NetBSD: amdzentemp.c,v 1.9.2.5 2023/08/22 16:10:21 martin Exp $ */
/* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */
/*
@@ -53,7 +53,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.9.2.4 2023/06/21 18:56:58 martin Exp $ ");
+__KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.9.2.5 2023/08/22 16:10:21 martin Exp $ ");
#include
#include
@@ -370,15 +370,19 @@ amdzentemp_probe_ccd_sensors17h(struct a
{
int maxreg;
- sc->sc_ccd_offset = 0x154;
-
switch (model) {
case 0x00 ... 0x2f: /* Zen1, Zen+ */
+ sc->sc_ccd_offset = 0x154;
maxreg = 4;
break;
case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */
case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */
case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */
+ sc->sc_ccd_offset = 0x154;
+ maxreg = 8;
+ break;
+ case 0xa0 ... 0xaf: /* Zen2 Ryzen (Mendocino APU) */
+ sc->sc_ccd_offset = 0x300;
maxreg = 8;
break;
default:
@@ -403,6 +407,7 @@ amdzentemp_probe_ccd_sensors19h(struct a
maxreg = 8;
break;
case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */
+ case 0x70 ... 0x7f: /* Zen4 Ryzen "Phoenix" */
sc->sc_ccd_offset = 0x308;
maxreg = 8;
break;
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src Committed By: martin Date: Tue Aug 22 16:10:21 UTC 2023 Modified Files: src/sys/arch/x86/pci [netbsd-9]: amdsmn.c amdzentemp.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #1720): sys/arch/x86/pci/amdzentemp.c: revision 1.20 sys/arch/x86/pci/amdsmn.c: revision 1.17 sys/arch/x86/pci/amdzentemp.c: revision 1.19 Add Zen4 Ryzen "Phoenix" support. Add Zen2 Mendocino APU support. Add Zen4 Phoenix support. To generate a diff of this commit: cvs rdiff -u -r1.5.2.4 -r1.5.2.5 src/sys/arch/x86/pci/amdsmn.c cvs rdiff -u -r1.9.2.4 -r1.9.2.5 src/sys/arch/x86/pci/amdzentemp.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Sat Jul 29 11:01:15 UTC 2023
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: coretemp.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #254):
sys/arch/x86/x86/coretemp.c: revision 1.38-1.39 (patch)
coretemp(4): Change limits of Tjmax.
- Change the lower limit from 70 to 60. At least, some BIOSes can change
the value down to 62.
- Change the upper limit from 110 to 120. At least, some BIOSes can change
the value up to 115.
- Print error message when rdmsr(TEMPERATURE_TARGET) failed.
- When Tjmax exceeded the limit, print warning message and use the value
as it is.
- KNF.
To generate a diff of this commit:
cvs rdiff -u -r1.36.4.1 -r1.36.4.2 src/sys/arch/x86/x86/coretemp.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/coretemp.c
diff -u src/sys/arch/x86/x86/coretemp.c:1.36.4.1 src/sys/arch/x86/x86/coretemp.c:1.36.4.2
--- src/sys/arch/x86/x86/coretemp.c:1.36.4.1 Wed Jul 15 14:02:36 2020
+++ src/sys/arch/x86/x86/coretemp.c Sat Jul 29 11:01:14 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: coretemp.c,v 1.36.4.1 2020/07/15 14:02:36 martin Exp $ */
+/* $NetBSD: coretemp.c,v 1.36.4.2 2023/07/29 11:01:14 martin Exp $ */
/*-
* Copyright (c) 2011 The NetBSD Foundation, Inc.
@@ -61,7 +61,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.36.4.1 2020/07/15 14:02:36 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.36.4.2 2023/07/29 11:01:14 martin Exp $");
#include
#include
@@ -102,6 +102,10 @@ __KERNEL_RCSID(0, "$NetBSD: coretemp.c,v
#define MSR_TEMP_TARGET_READOUT __BITS(16, 23)
+#define TJMAX_DEFAULT 100
+#define TJMAX_LIMIT_LOW 60
+#define TJMAX_LIMIT_HIGH 120
+
static int coretemp_match(device_t, cfdata_t, void *);
static void coretemp_attach(device_t, device_t, void *);
static int coretemp_detach(device_t, int);
@@ -259,16 +263,15 @@ coretemp_tjmax(device_t self)
{
struct coretemp_softc *sc = device_private(self);
struct cpu_info *ci = sc->sc_ci;
- uint32_t model, stepping;
uint64_t msr;
+ uint32_t model, stepping;
+ int tjmax;
model = CPUID_TO_MODEL(ci->ci_signature);
stepping = CPUID_TO_STEPPING(ci->ci_signature);
- /*
- * Use 100C as the initial value.
- */
- sc->sc_tjmax = 100;
+ /* Set the initial value. */
+ sc->sc_tjmax = TJMAX_DEFAULT;
if ((model == 0x0f && stepping >= 2) || (model == 0x0e)) {
/*
@@ -304,20 +307,20 @@ coretemp_tjmax(device_t self)
sc->sc_tjmax = 90;
} else {
notee:
- /*
- * Attempt to get Tj(max) from IA32_TEMPERATURE_TARGET,
- * but only consider the interval [70, 110] C as valid.
- * It is not fully known which CPU models have the MSR.
- */
- if (rdmsr_safe(MSR_TEMPERATURE_TARGET, ) == EFAULT)
- return;
-
- msr = __SHIFTOUT(msr, MSR_TEMP_TARGET_READOUT);
-
- if (msr >= 70 && msr <= 110) {
- sc->sc_tjmax = msr;
+ /* Attempt to get Tj(max) from IA32_TEMPERATURE_TARGET. */
+ if (rdmsr_safe(MSR_TEMPERATURE_TARGET, ) == EFAULT) {
+ aprint_error_dev(sc->sc_dev,
+ "Failed to read TEMPERATURE_TARGET MSR. "
+ "Use the default (%d)\n", sc->sc_tjmax);
return;
}
+
+ tjmax = __SHIFTOUT(msr, MSR_TEMP_TARGET_READOUT);
+ if ((tjmax < TJMAX_LIMIT_LOW) || (tjmax > TJMAX_LIMIT_HIGH))
+ aprint_error_dev(sc->sc_dev,
+ "WARNING: Tjmax(%d) might exceeded the limit.\n",
+ tjmax);
+ sc->sc_tjmax = tjmax;
}
}
@@ -334,7 +337,7 @@ coretemp_refresh(struct sysmon_envsys *s
static void
coretemp_refresh_xcall(void *arg0, void *arg1)
{
-struct coretemp_softc *sc = arg0;
+ struct coretemp_softc *sc = arg0;
envsys_data_t *edata = arg1;
uint64_t msr;
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Sat Jul 29 11:01:15 UTC 2023 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: coretemp.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #254): sys/arch/x86/x86/coretemp.c: revision 1.38-1.39 (patch) coretemp(4): Change limits of Tjmax. - Change the lower limit from 70 to 60. At least, some BIOSes can change the value down to 62. - Change the upper limit from 110 to 120. At least, some BIOSes can change the value up to 115. - Print error message when rdmsr(TEMPERATURE_TARGET) failed. - When Tjmax exceeded the limit, print warning message and use the value as it is. - KNF. To generate a diff of this commit: cvs rdiff -u -r1.36.4.1 -r1.36.4.2 src/sys/arch/x86/x86/coretemp.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src
Committed By: martin
Date: Sat Jul 29 09:48:51 UTC 2023
Modified Files:
src/sys/arch/x86/include [netbsd-9]: specialreg.h
Log Message:
Pull up the following revisions, all via patch, requested by msaitoh
in ticket #1669:
sys/arch/x86/include/specialreg.h 1.204-1.206, 1.208
- Add Intel CPUID 0x07 %ecx bit 24 BUS_LOCK_DETECT.
- Add AMD CPUID 0x8008 %ebx bit 30 IBPB_RET and CPUID 0x800a
%edx bit 29 BusLockThreshold.
- Fix typo in comment.
To generate a diff of this commit:
cvs rdiff -u -r1.150.2.14 -r1.150.2.15 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.150.2.14 src/sys/arch/x86/include/specialreg.h:1.150.2.15
--- src/sys/arch/x86/include/specialreg.h:1.150.2.14 Tue Jul 25 09:12:35 2023
+++ src/sys/arch/x86/include/specialreg.h Sat Jul 29 09:48:51 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.150.2.14 2023/07/25 09:12:35 martin Exp $ */
+/* $NetBSD: specialreg.h,v 1.150.2.15 2023/07/29 09:48:51 martin Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -466,6 +466,7 @@
#define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */
#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */
#define CPUID_SEF_KL __BIT(23) /* Key Locker */
+#define CPUID_SEF_BUS_LOCK_DETECT __BIT(24) /* OS bus-lock detection */
#define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */
#define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */
#define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */
@@ -480,7 +481,7 @@
"b\14AVX512_BITALG\0" "b\15TME_EN\0" "b\16AVX512_VPOPCNTDQ\0" \
"b\20LA57\0" \
"f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \
- "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \
+ "b\30BUS_LOCK_DETECT" "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \
"b\34MOVDIR64B\0" "b\35ENQCMD\0" "b\36SGXLC\0" "b\37PKS\0"
/* %ecx = 0, %edx */
@@ -889,6 +890,7 @@
#define CPUID_CAPEX_CPPC __BIT(27) /* Collaborative Processor Perf. Control */
#define CPUID_CAPEX_PSFD __BIT(28) /* Predictive Store Forward Dis */
#define CPUID_CAPEX_BTC_NO __BIT(29) /* Branch Type Confusion NO */
+#define CPUID_CAPEX_IBPB_RET __BIT(30) /* Clear RET address predictor */
#define CPUID_CAPEX_FLAGS "\20" \
"\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" "\4INVLPGB" \
@@ -899,7 +901,7 @@
"\24IBRS_SAMEMODE" \
"\25EFER_LSMSLE_UN""\30PPIN" \
"\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" "\34CPPC" \
- "\35PSFD" "\36BTC_NO"
+ "\35PSFD" "\36BTC_NO" "\37IBPB_RET"
/* %ecx */
#define CPUID_CAPEX_PerfTscSize __BITS(17,16) /* Perf. tstamp counter size */
@@ -939,6 +941,7 @@
#define CPUID_AMD_SVM_IBSVIRT __BIT(26) /* IBS Virtualization */
#define CPUID_AMD_SVM_XLVTOFFFLTCHG __BIT(27) /* Ext LVToffset FLT changed */
#define CPUID_AMD_SVM_VMCBADRCHKCHG __BIT(28) /* VMCB addr check changed */
+#define CPUID_AMD_SVM_BUSLOCKTHRESH __BIT(29) /* Bus Lock Threshold */
#define CPUID_AMD_SVM_FLAGS "\20" \
@@ -951,7 +954,7 @@
"\21" "VGIF" "\22" "GMET" "\23x2AVIC" "\24SSSCHECK" \
"\25" "SPEC_CTRL" "\26" "ROGPT" "\30HOST_MCE_OVERRIDE" \
"\31" "TLBICTL" "\32VNMI" "\33IBSVIRT" "\34ExtLvtOffsetFaultChg" \
- "\35VmcbAddrChkChg"
+ "\35VmcbAddrChkChg" "\36BusLockThreshold"
/*
* AMD Instruction-Based Sampling Capabilities.
@@ -1065,7 +1068,7 @@
#define CPUID_AMDEXT2_FSRC __BIT(11) /* Fast Short Rep Cmpsb */
#define CPUID_AMDEXT2_PREFETCHCTL __BIT(13) /* Prefetch control MSR */
#define CPUID_AMDEXT2_CPUIDUSRDIS __BIT(17) /* CPUID dis. for non-priv. soft */
-#define CPUID_AMDEXT2_EPSF __BIT(18) /* Enhanced Predective Store Fwd */
+#define CPUID_AMDEXT2_EPSF __BIT(18) /* Enhanced Predictive Store Fwd */
#define CPUID_AMDEXT2_FLAGS "\20" \
"\1NoNestedDataBp" "\2FsGsKernelGsBaseNonSerializing" \
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Sat Jul 29 09:48:51 UTC 2023 Modified Files: src/sys/arch/x86/include [netbsd-9]: specialreg.h Log Message: Pull up the following revisions, all via patch, requested by msaitoh in ticket #1669: sys/arch/x86/include/specialreg.h 1.204-1.206, 1.208 - Add Intel CPUID 0x07 %ecx bit 24 BUS_LOCK_DETECT. - Add AMD CPUID 0x8008 %ebx bit 30 IBPB_RET and CPUID 0x800a %edx bit 29 BusLockThreshold. - Fix typo in comment. To generate a diff of this commit: cvs rdiff -u -r1.150.2.14 -r1.150.2.15 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Thu Jul 27 16:40:50 UTC 2023
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: errata.c
Log Message:
Pull up following revision(s) (requested by mrg in ticket #1667):
sys/arch/x86/x86/errata.c: revision 1.32
fix the cpuids for the zen2 client CPUs.
i'm not exactly how i came up with the values i had, though one
of them was still valid and matched my test systems.
To generate a diff of this commit:
cvs rdiff -u -r1.26.2.1 -r1.26.2.2 src/sys/arch/x86/x86/errata.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/errata.c
diff -u src/sys/arch/x86/x86/errata.c:1.26.2.1 src/sys/arch/x86/x86/errata.c:1.26.2.2
--- src/sys/arch/x86/x86/errata.c:1.26.2.1 Tue Jul 25 09:12:36 2023
+++ src/sys/arch/x86/x86/errata.c Thu Jul 27 16:40:50 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: errata.c,v 1.26.2.1 2023/07/25 09:12:36 martin Exp $ */
+/* $NetBSD: errata.c,v 1.26.2.2 2023/07/27 16:40:50 martin Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@@ -45,7 +45,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: errata.c,v 1.26.2.1 2023/07/25 09:12:36 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: errata.c,v 1.26.2.2 2023/07/27 16:40:50 martin Exp $");
#include
#include
@@ -96,8 +96,8 @@ static const u_int cpurevs[] = {
ML_A1, 0x0730F01, ZP_B1, 0x0800F11, ZP_B2, 0x0800F12,
PiR_B2, 0x0800F82, Rome_B0, 0x0830F10,
/* XXX client Zen2 names aren't known yet. */
- Z2_XB, 0x0840F70, Z2_Ren, 0x0860F80, Z2_Luc, 0x0870F10,
- Z2_Mat, 0x0890F70, Z2_VG, 0x0890F80, Z2_Men, 0x08A0F10,
+ Z2_XB, 0x0840F70, Z2_Ren, 0x0860F01, Z2_Luc, 0x0860F81,
+ Z2_Mat, 0x0870F10, Z2_VG, 0x0890F02, Z2_Men, 0x08A0F00,
Milan_B1, 0x0A00F11, Milan_B2, 0x0A00F12,
Genoa_B1, 0x0A10F11,
OINK
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Thu Jul 27 16:40:50 UTC 2023 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: errata.c Log Message: Pull up following revision(s) (requested by mrg in ticket #1667): sys/arch/x86/x86/errata.c: revision 1.32 fix the cpuids for the zen2 client CPUs. i'm not exactly how i came up with the values i had, though one of them was still valid and matched my test systems. To generate a diff of this commit: cvs rdiff -u -r1.26.2.1 -r1.26.2.2 src/sys/arch/x86/x86/errata.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Tue Jul 25 11:34:37 UTC 2023
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: fpu.c
Log Message:
Pull up following revision(s) (requested by riastradh in ticket #1665):
sys/arch/x86/x86/fpu.c: revision 1.86
x86/fpu: Align savefpu to 64 bytes in fpuinit_mxcsr_mask.
16 bytes is not enough.
(Is this why it never worked on Xen some years back? Got lucky and
accidentally had 64-byte alignment on native x86, but not in the call
stack in Xen?)
To generate a diff of this commit:
cvs rdiff -u -r1.55.2.1 -r1.55.2.2 src/sys/arch/x86/x86/fpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/fpu.c
diff -u src/sys/arch/x86/x86/fpu.c:1.55.2.1 src/sys/arch/x86/x86/fpu.c:1.55.2.2
--- src/sys/arch/x86/x86/fpu.c:1.55.2.1 Sun Oct 18 18:42:10 2020
+++ src/sys/arch/x86/x86/fpu.c Tue Jul 25 11:34:37 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: fpu.c,v 1.55.2.1 2020/10/18 18:42:10 martin Exp $ */
+/* $NetBSD: fpu.c,v 1.55.2.2 2023/07/25 11:34:37 martin Exp $ */
/*
* Copyright (c) 2008 The NetBSD Foundation, Inc. All
@@ -96,7 +96,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.55.2.1 2020/10/18 18:42:10 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.55.2.2 2023/07/25 11:34:37 martin Exp $");
#include "opt_multiprocessor.h"
@@ -153,7 +153,7 @@ void
fpuinit_mxcsr_mask(void)
{
#ifndef XENPV
- union savefpu fpusave __aligned(16);
+ union savefpu fpusave __aligned(64);
u_long psl;
memset(, 0, sizeof(fpusave));
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Tue Jul 25 11:34:37 UTC 2023 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: fpu.c Log Message: Pull up following revision(s) (requested by riastradh in ticket #1665): sys/arch/x86/x86/fpu.c: revision 1.86 x86/fpu: Align savefpu to 64 bytes in fpuinit_mxcsr_mask. 16 bytes is not enough. (Is this why it never worked on Xen some years back? Got lucky and accidentally had 64-byte alignment on native x86, but not in the call stack in Xen?) To generate a diff of this commit: cvs rdiff -u -r1.55.2.1 -r1.55.2.2 src/sys/arch/x86/x86/fpu.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86
Module Name:src Committed By: martin Date: Tue Jul 25 09:12:36 UTC 2023 Modified Files: src/sys/arch/x86/include [netbsd-9]: specialreg.h src/sys/arch/x86/x86 [netbsd-9]: errata.c Log Message: Pull up following revision(s) (requested by mrg in ticket #1664): sys/arch/x86/include/specialreg.h: revision 1.207 sys/arch/x86/x86/errata.c: revision 1.31 x86: turn off zenbleed chicken bit on Zen2 cpus. this is based upon Taylor's original work. i just made the list of CPUs to run on correct as i could determine. (also, add some Zen3 and Zen4 cpuids not yet used by any errata.) (might be nice to have a better way to expression revision ranges rather than specific cpuid matches, eg, 0x30-0x4f models in a cpu family, etc.) tested on ryzen 3600, and a ported zenbleed PoC that no longer shows any obtained text. (a similar module-version of it stopped the PoC on a ryzen 3950x without having to reboot.) https://www.amd.com/en/resources/product-security/bulletin/amd-sb-7008.html https://lock.cmpxchg8b.com/zenbleed.html To generate a diff of this commit: cvs rdiff -u -r1.150.2.13 -r1.150.2.14 src/sys/arch/x86/include/specialreg.h cvs rdiff -u -r1.26 -r1.26.2.1 src/sys/arch/x86/x86/errata.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86
Module Name:src
Committed By: martin
Date: Tue Jul 25 09:12:36 UTC 2023
Modified Files:
src/sys/arch/x86/include [netbsd-9]: specialreg.h
src/sys/arch/x86/x86 [netbsd-9]: errata.c
Log Message:
Pull up following revision(s) (requested by mrg in ticket #1664):
sys/arch/x86/include/specialreg.h: revision 1.207
sys/arch/x86/x86/errata.c: revision 1.31
x86: turn off zenbleed chicken bit on Zen2 cpus.
this is based upon Taylor's original work. i just made the list
of CPUs to run on correct as i could determine. (also, add some
Zen3 and Zen4 cpuids not yet used by any errata.)
(might be nice to have a better way to expression revision ranges
rather than specific cpuid matches, eg, 0x30-0x4f models in a cpu
family, etc.)
tested on ryzen 3600, and a ported zenbleed PoC that no longer
shows any obtained text. (a similar module-version of it stopped
the PoC on a ryzen 3950x without having to reboot.)
https://www.amd.com/en/resources/product-security/bulletin/amd-sb-7008.html
https://lock.cmpxchg8b.com/zenbleed.html
To generate a diff of this commit:
cvs rdiff -u -r1.150.2.13 -r1.150.2.14 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.26 -r1.26.2.1 src/sys/arch/x86/x86/errata.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.150.2.13 src/sys/arch/x86/include/specialreg.h:1.150.2.14
--- src/sys/arch/x86/include/specialreg.h:1.150.2.13 Wed Jun 21 19:04:19 2023
+++ src/sys/arch/x86/include/specialreg.h Tue Jul 25 09:12:35 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.150.2.13 2023/06/21 19:04:19 martin Exp $ */
+/* $NetBSD: specialreg.h,v 1.150.2.14 2023/07/25 09:12:35 martin Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -1393,6 +1393,7 @@
#define MSR_DE_CFG 0xc0011029
#define DE_CFG_ERRATA_721 0x0001
#define DE_CFG_LFENCE_SERIALIZE __BIT(1)
+#define DE_CFG_ERRATA_ZENBLEED __BIT(9)
#define DE_CFG_ERRATA_1021 __BIT(13)
#define MSR_BU_CFG2 0xc001102a
Index: src/sys/arch/x86/x86/errata.c
diff -u src/sys/arch/x86/x86/errata.c:1.26 src/sys/arch/x86/x86/errata.c:1.26.2.1
--- src/sys/arch/x86/x86/errata.c:1.26 Sat May 18 07:49:31 2019
+++ src/sys/arch/x86/x86/errata.c Tue Jul 25 09:12:36 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: errata.c,v 1.26 2019/05/18 07:49:31 maxv Exp $ */
+/* $NetBSD: errata.c,v 1.26.2.1 2023/07/25 09:12:36 martin Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@@ -45,7 +45,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: errata.c,v 1.26 2019/05/18 07:49:31 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: errata.c,v 1.26.2.1 2023/07/25 09:12:36 martin Exp $");
#include
#include
@@ -71,9 +71,12 @@ typedef enum cpurev {
JH_E6, SH_B0, SH_B3, SH_C0, SH_CG, SH_D0, SH_E4, SH_E5,
DR_BA, DR_B2, DR_B3, RB_C2, RB_C3, BL_C2, BL_C3, DA_C2,
DA_C3, HY_D0, HY_D1, HY_D1_G34R1, PH_E0, LN_B0, KB_A1,
- ML_A1, ZP_B1, ZP_B2, PiR_B2, OINK
+ ML_A1, ZP_B1, ZP_B2, PiR_B2, Rome_B0, Z2_XB, Z2_Ren,
+ Z2_Luc, Z2_Mat, Z2_VG, Z2_Men, Milan_B1, Milan_B2, Genoa_B1,
+ OINK
} cpurev_t;
+/* These names match names from various AMD Errata/Revision Guides. */
static const u_int cpurevs[] = {
BH_E4, 0x0020fb1, CH_CG, 0xf82, CH_CG, 0xfb2,
CH_D0, 0x0010f80, CH_D0, 0x0010fb0, DH_CG, 0xfc0,
@@ -91,7 +94,12 @@ static const u_int cpurevs[] = {
HY_D0, 0x0100f80, HY_D1, 0x0100f81, HY_D1_G34R1, 0x0100f91,
PH_E0, 0x0100fa0, LN_B0, 0x0300f10, KB_A1, 0x0700F01,
ML_A1, 0x0730F01, ZP_B1, 0x0800F11, ZP_B2, 0x0800F12,
- PiR_B2, 0x0800F82,
+ PiR_B2, 0x0800F82, Rome_B0, 0x0830F10,
+ /* XXX client Zen2 names aren't known yet. */
+ Z2_XB, 0x0840F70, Z2_Ren, 0x0860F80, Z2_Luc, 0x0870F10,
+ Z2_Mat, 0x0890F70, Z2_VG, 0x0890F80, Z2_Men, 0x08A0F10,
+ Milan_B1, 0x0A00F11, Milan_B2, 0x0A00F12,
+ Genoa_B1, 0x0A10F11,
OINK
};
@@ -160,6 +168,10 @@ static const uint8_t x86_errata_set15[]
KB_A1, ML_A1, OINK
};
+static const uint8_t x86_errata_set16[] = {
+ Rome_B0, Z2_XB, Z2_Ren, Z2_Luc, Z2_Mat, Z2_VG, Z2_Men, OINK
+};
+
static bool x86_errata_setmsr(struct cpu_info *, errata_t *);
static bool x86_errata_testmsr(struct cpu_info *, errata_t *);
@@ -359,6 +371,16 @@ static errata_t errata[] = {
1095, FALSE, MSR_LS_CFG, x86_errata_set13,
x86_errata_setmsr, LS_CFG_ERRATA_1095
},
+ /*
+ * Zenbleed:
+ * https://www.amd.com/en/resources/product-security/bulletin/amd-sb-7008.html
+ * https://github.com/google/security-research/security/advisories/GHSA-v6wh-rxpg-cmm8
+ * https://lock.cmpxchg8b.com/zenbleed.html
+ */
+ {
+ -1, FALSE, MSR_DE_CFG, x86_errata_set16,
+ x86_errata_setmsr, DE_CFG_ERRATA_ZENBLEED,
+ },
};
static bool
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Wed Jun 21 19:52:39 UTC 2023
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: procfs_machdep.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1649):
sys/arch/x86/x86/procfs_machdep.c: revision 1.47
Add Intel lam and AMD vnmi.
To generate a diff of this commit:
cvs rdiff -u -r1.33.2.7 -r1.33.2.8 src/sys/arch/x86/x86/procfs_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/procfs_machdep.c
diff -u src/sys/arch/x86/x86/procfs_machdep.c:1.33.2.7 src/sys/arch/x86/x86/procfs_machdep.c:1.33.2.8
--- src/sys/arch/x86/x86/procfs_machdep.c:1.33.2.7 Mon Jan 23 12:23:53 2023
+++ src/sys/arch/x86/x86/procfs_machdep.c Wed Jun 21 19:52:39 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: procfs_machdep.c,v 1.33.2.7 2023/01/23 12:23:53 martin Exp $ */
+/* $NetBSD: procfs_machdep.c,v 1.33.2.8 2023/06/21 19:52:39 martin Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -42,7 +42,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.33.2.7 2023/01/23 12:23:53 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.33.2.8 2023/06/21 19:52:39 martin Exp $");
#include
#include
@@ -151,7 +151,7 @@ static const char * const x86_features[]
"avx_vnni", "avx512_bf16", NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
+ NULL, NULL, "lam", NULL, NULL, NULL, NULL, NULL},
{ /* (13) AMD 0x8008 ebx */
"clzero", "irperf", "xsaveerptr", NULL, "rdpru", NULL, NULL, NULL,
@@ -172,7 +172,7 @@ static const char * const x86_features[]
NULL, NULL, "pausefilter", NULL, "pfthreshold", "avic", NULL,
"v_vmsave_vmload",
"vgif", NULL, "x2avic", NULL, "v_spec_ctrl", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
+ NULL, "vnmi", NULL, NULL, NULL, NULL, NULL, NULL},
{ /* (16) 0x0007:0 ecx */
NULL, "avx512vbmi", "umip", "pku",
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Wed Jun 21 19:52:39 UTC 2023 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: procfs_machdep.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #1649): sys/arch/x86/x86/procfs_machdep.c: revision 1.47 Add Intel lam and AMD vnmi. To generate a diff of this commit: cvs rdiff -u -r1.33.2.7 -r1.33.2.8 src/sys/arch/x86/x86/procfs_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src
Committed By: martin
Date: Wed Jun 21 18:56:58 UTC 2023
Modified Files:
src/sys/arch/x86/pci [netbsd-9]: amdsmn.c amdzentemp.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1644):
sys/arch/x86/pci/amdsmn.c: revision 1.16
sys/arch/x86/pci/amdzentemp.c: revision 1.17
sys/arch/x86/pci/amdzentemp.c: revision 1.18
Reduce diff against DragonFly. No functional change.
amdsmn(4),amdzentemp(4): Add Zen3+ Rembrandt(19h/4xh) & Zen4 Genoa(19h/1xh).
To generate a diff of this commit:
cvs rdiff -u -r1.5.2.3 -r1.5.2.4 src/sys/arch/x86/pci/amdsmn.c
cvs rdiff -u -r1.9.2.3 -r1.9.2.4 src/sys/arch/x86/pci/amdzentemp.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/pci/amdsmn.c
diff -u src/sys/arch/x86/pci/amdsmn.c:1.5.2.3 src/sys/arch/x86/pci/amdsmn.c:1.5.2.4
--- src/sys/arch/x86/pci/amdsmn.c:1.5.2.3 Tue Oct 11 18:16:20 2022
+++ src/sys/arch/x86/pci/amdsmn.c Wed Jun 21 18:56:58 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: amdsmn.c,v 1.5.2.3 2022/10/11 18:16:20 martin Exp $ */
+/* $NetBSD: amdsmn.c,v 1.5.2.4 2023/06/21 18:56:58 martin Exp $ */
/*-
* Copyright (c) 2017, 2019 Conrad Meyer
@@ -29,7 +29,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: amdsmn.c,v 1.5.2.3 2022/10/11 18:16:20 martin Exp $ ");
+__KERNEL_RCSID(0, "$NetBSD: amdsmn.c,v 1.5.2.4 2023/06/21 18:56:58 martin Exp $ ");
/*
* Driver for the AMD Family 15h (model 60+) and 17h CPU
@@ -93,7 +93,17 @@ static const struct pciid {
.amdsmn_data_reg = F17H_SMN_DATA_REG,
},
{
- .amdsmn_deviceid = PCI_PRODUCT_AMD_F17_7X_RC,
+ .amdsmn_deviceid = PCI_PRODUCT_AMD_F17_7X_RC, /* or F19_0X */
+ .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
+ .amdsmn_data_reg = F17H_SMN_DATA_REG,
+ },
+ {
+ .amdsmn_deviceid = PCI_PRODUCT_AMD_F17_AX_RC, /* or F19_4X */
+ .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
+ .amdsmn_data_reg = F17H_SMN_DATA_REG,
+ },
+ {
+ .amdsmn_deviceid = PCI_PRODUCT_AMD_F19_1X_RC,
.amdsmn_addr_reg = F17H_SMN_ADDR_REG,
.amdsmn_data_reg = F17H_SMN_DATA_REG,
},
Index: src/sys/arch/x86/pci/amdzentemp.c
diff -u src/sys/arch/x86/pci/amdzentemp.c:1.9.2.3 src/sys/arch/x86/pci/amdzentemp.c:1.9.2.4
--- src/sys/arch/x86/pci/amdzentemp.c:1.9.2.3 Mon Jan 23 12:27:33 2023
+++ src/sys/arch/x86/pci/amdzentemp.c Wed Jun 21 18:56:58 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: amdzentemp.c,v 1.9.2.3 2023/01/23 12:27:33 martin Exp $ */
+/* $NetBSD: amdzentemp.c,v 1.9.2.4 2023/06/21 18:56:58 martin Exp $ */
/* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */
/*
@@ -53,7 +53,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.9.2.3 2023/01/23 12:27:33 martin Exp $ ");
+__KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.9.2.4 2023/06/21 18:56:58 martin Exp $ ");
#include
#include
@@ -74,7 +74,6 @@ __KERNEL_RCSID(0, "$NetBSD: amdzentemp.c
#include "amdsmn.h"
#define AMD_CURTMP_RANGE_ADJUST 4900 /* in microKelvins (ie, 49C) */
-#define AMD_CURTMP_RANGE_CHECK __BIT(19)
#define F10_TEMP_CURTMP __BITS(31,21) /* XXX same as amdtemp.c */
#define F10_TEMP_CURTMP_MASK 0x7ff
#define F15M60_CURTMP_TJSEL __BITS(17,16)
@@ -96,14 +95,7 @@ __KERNEL_RCSID(0, "$NetBSD: amdzentemp.c
* to -49..206C.
*/
#define AMD_17H_CUR_TMP 0x59800
-
-/*
- * The following register set was discovered experimentally by Ondrej Čerman
- * and collaborators, but is not (yet) documented in a PPR/OSRR (other than
- * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to
- * SMU::THM). It seems plausible and the Linux sensor folks have adopted it.
- */
-#define AMD_17H_CCD_TMP_BASE 0x59954
+#define AMD_17H_CUR_TMP_RANGE_SEL __BIT(19)
#define AMD_17H_CCD_TMP_VALID __BIT(11)
struct amdzentemp_softc {
@@ -114,7 +106,7 @@ struct amdzentemp_softc {
size_t sc_sensor_len;
size_t sc_numsensors;
int32_t sc_offset;
- uint32_t sc_ccd_tmp_base;
+ int32_t sc_ccd_offset;
};
enum {
@@ -129,6 +121,10 @@ enum {
CCD5,
CCD6,
CCD7,
+ CCD8,
+ CCD9,
+ CCD10,
+ CCD11,
CCD_MAX,
NUM_CCDS = CCD_MAX - CCD_BASE
};
@@ -339,14 +335,16 @@ amdzentemp_family17_refresh(struct sysmo
edata->state = ENVSYS_SINVALID;
return;
}
- minus49 = (temp & AMD_CURTMP_RANGE_CHECK) ? true : false;
+ minus49 = (temp & AMD_17H_CUR_TMP_RANGE_SEL) ?
+ true : false;
temp = __SHIFTOUT(temp, F10_TEMP_CURTMP);
break;
case CCD_BASE ... (CCD_MAX - 1):
/* Tccd */
i = edata->private - CCD_BASE;
error = amdsmn_read(sc->sc_smn,
- sc->sc_ccd_tmp_base + (i * sizeof(temp)), );
+ AMD_17H_CUR_TMP + sc->sc_ccd_offset + (i * sizeof(temp)),
+ );
if (error || !ISSET(temp, AMD_17H_CCD_TMP_VALID)) {
edata->state = ENVSYS_SINVALID;
return;
@@ -372,6 +370,8 @@ amdzentemp_probe_ccd_sensors17h(struct a
{
int maxreg;
+ sc->sc_ccd_offset = 0x154;
+
switch (model) {
case 0x00 ... 0x2f: /* Zen1, Zen+ */
maxreg = 4;
@@ -399,12
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src Committed By: martin Date: Wed Jun 21 18:56:58 UTC 2023 Modified Files: src/sys/arch/x86/pci [netbsd-9]: amdsmn.c amdzentemp.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #1644): sys/arch/x86/pci/amdsmn.c: revision 1.16 sys/arch/x86/pci/amdzentemp.c: revision 1.17 sys/arch/x86/pci/amdzentemp.c: revision 1.18 Reduce diff against DragonFly. No functional change. amdsmn(4),amdzentemp(4): Add Zen3+ Rembrandt(19h/4xh) & Zen4 Genoa(19h/1xh). To generate a diff of this commit: cvs rdiff -u -r1.5.2.3 -r1.5.2.4 src/sys/arch/x86/pci/amdsmn.c cvs rdiff -u -r1.9.2.3 -r1.9.2.4 src/sys/arch/x86/pci/amdzentemp.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Wed Feb 22 19:20:45 UTC 2023
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: efi.c
Log Message:
Pull up following revision(s) (requested by riastradh in ticket #1603):
sys/arch/x86/x86/efi_machdep.c: revision 1.3
(applied to sys/arch/x86/x86/efi.c)
x86/efi: Print uuids in slightly more standard notation.
Anyone need a spare hyphen? We had a few extras, apparently.
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.19.4.1 src/sys/arch/x86/x86/efi.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/efi.c
diff -u src/sys/arch/x86/x86/efi.c:1.19 src/sys/arch/x86/x86/efi.c:1.19.4.1
--- src/sys/arch/x86/x86/efi.c:1.19 Mon Dec 3 19:46:43 2018
+++ src/sys/arch/x86/x86/efi.c Wed Feb 22 19:20:45 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: efi.c,v 1.19 2018/12/03 19:46:43 cherry Exp $ */
+/* $NetBSD: efi.c,v 1.19.4.1 2023/02/22 19:20:45 martin Exp $ */
/*-
* Copyright (c) 2016 The NetBSD Foundation, Inc.
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: efi.c,v 1.19 2018/12/03 19:46:43 cherry Exp $");
+__KERNEL_RCSID(0, "$NetBSD: efi.c,v 1.19.4.1 2023/02/22 19:20:45 martin Exp $");
#include
#include
@@ -134,7 +134,7 @@ efi_aprintuuid(const struct uuid * uuid)
aprint_debug("-%04" PRIx16 "", uuid->time_mid);
aprint_debug("-%04" PRIx16 "", uuid->time_hi_and_version);
aprint_debug("-%02" PRIx8 "", uuid->clock_seq_hi_and_reserved);
- aprint_debug("-%02" PRIx8 "", uuid->clock_seq_low);
+ aprint_debug("%02" PRIx8 "", uuid->clock_seq_low);
aprint_debug("-");
for (i = 0; i < _UUID_NODE_LEN; i++) {
aprint_debug("%02" PRIx8 "", uuid->node[i]);
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Wed Feb 22 19:20:45 UTC 2023 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: efi.c Log Message: Pull up following revision(s) (requested by riastradh in ticket #1603): sys/arch/x86/x86/efi_machdep.c: revision 1.3 (applied to sys/arch/x86/x86/efi.c) x86/efi: Print uuids in slightly more standard notation. Anyone need a spare hyphen? We had a few extras, apparently. To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.19.4.1 src/sys/arch/x86/x86/efi.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src Committed By: martin Date: Mon Jan 23 12:27:33 UTC 2023 Modified Files: src/sys/arch/x86/pci [netbsd-9]: amdzentemp.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #1572): sys/arch/x86/pci/amdzentemp.c: revision 1.16 match zen3 "cezanne" (ryzen 5000-series APU.) To generate a diff of this commit: cvs rdiff -u -r1.9.2.2 -r1.9.2.3 src/sys/arch/x86/pci/amdzentemp.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Mon Jan 23 13:00:53 UTC 2023 Modified Files: src/sys/arch/x86/include [netbsd-9]: specialreg.h Log Message: Pull up the following revisions, requested by msaitoh in ticket #1574: sys/arch/x86/include/specialreg.h 1.193-1.198 - Add CPUID Fn_0006 %eax bit 24 IA32_THERM_INTERRUPT MSR bit 25 Hardware Feedback Notification support. - Add CPUID Fn_0007 %ecx bit 29 ENQCMD. - Add CPUID Fn_0007 %edx bit 1 SGX-KEYS. - Add CPUID Fn_0007 %edx bit 5 UINTR(User INTeRrupts). - Add CPUID Fn_0007 %edx bit 11 RTM_ALWAYS_ABORT. - Add CPUID Fn_0007 %edx bit 22 AMX_BF16. - Add CPUID Fn_0007 %edx bit 23 AVX512_FP16. - Add CPUID Fn_0007 %edx bit 24 AMX_TILE. - Add CPUID Fn_0007 %edx bit 25 AMX_INT8. - Add CPUID Fn_0007 sub-leaf 1 %edx bit 18 CET_SSS. - Add CPUID Fn_0007 sub-leaf 2 %edx definitions. - Add CPUID Fn_000d sub-leaf 1 %eax bit 4 XFD. - Add CPUID Fn_001d Tile Information. - Add CPUID Fn_001e TMUL Information. - Add CPUID Fn8000_0007 %eax RAS capabilities. - Add CPUID Fn8000_0008 %ebx BTC_NO, - Add cpuid Fn8000_000a x2AVIC, VNMI, IBSVIRT and ROGPT. - Add CPUID Fn8000_001b Instruction-Based Sampling. - Add CPUID Fn8000_001e Processor Topology Information. - Add CPUID Fn8000_001f %eax RPMQUERY, VmplSSS, TscAuxVirt, VmgexitParam, VirtualTomMsr, IbsVirtGuest, SmtProtection, vsmCommPageMSR and NestedVirtSnpMsr. - Add CPUID Fn8000_0021 AMD Extended Features Identification 2. - Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug. - Rename HW_FEEDBACK to HWI (Hardware Feedback Interface). - Rename TSX_FORCE_ABORT to RTM_FORCE_ABORT. - Modify comment. Both Intel and AMD support CPUID Fn000b. - Modify comment. Hybrid Information -> Native Model ID Information. - Use __BIT(). Add comment. Whitespace fix. To generate a diff of this commit: cvs rdiff -u -r1.150.2.11 -r1.150.2.12 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Mon Jan 23 13:00:53 UTC 2023 Modified Files: src/sys/arch/x86/include [netbsd-9]: specialreg.h Log Message: Pull up the following revisions, requested by msaitoh in ticket #1574: sys/arch/x86/include/specialreg.h 1.193-1.198 - Add CPUID Fn_0006 %eax bit 24 IA32_THERM_INTERRUPT MSR bit 25 Hardware Feedback Notification support. - Add CPUID Fn_0007 %ecx bit 29 ENQCMD. - Add CPUID Fn_0007 %edx bit 1 SGX-KEYS. - Add CPUID Fn_0007 %edx bit 5 UINTR(User INTeRrupts). - Add CPUID Fn_0007 %edx bit 11 RTM_ALWAYS_ABORT. - Add CPUID Fn_0007 %edx bit 22 AMX_BF16. - Add CPUID Fn_0007 %edx bit 23 AVX512_FP16. - Add CPUID Fn_0007 %edx bit 24 AMX_TILE. - Add CPUID Fn_0007 %edx bit 25 AMX_INT8. - Add CPUID Fn_0007 sub-leaf 1 %edx bit 18 CET_SSS. - Add CPUID Fn_0007 sub-leaf 2 %edx definitions. - Add CPUID Fn_000d sub-leaf 1 %eax bit 4 XFD. - Add CPUID Fn_001d Tile Information. - Add CPUID Fn_001e TMUL Information. - Add CPUID Fn8000_0007 %eax RAS capabilities. - Add CPUID Fn8000_0008 %ebx BTC_NO, - Add cpuid Fn8000_000a x2AVIC, VNMI, IBSVIRT and ROGPT. - Add CPUID Fn8000_001b Instruction-Based Sampling. - Add CPUID Fn8000_001e Processor Topology Information. - Add CPUID Fn8000_001f %eax RPMQUERY, VmplSSS, TscAuxVirt, VmgexitParam, VirtualTomMsr, IbsVirtGuest, SmtProtection, vsmCommPageMSR and NestedVirtSnpMsr. - Add CPUID Fn8000_0021 AMD Extended Features Identification 2. - Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug. - Rename HW_FEEDBACK to HWI (Hardware Feedback Interface). - Rename TSX_FORCE_ABORT to RTM_FORCE_ABORT. - Modify comment. Both Intel and AMD support CPUID Fn000b. - Modify comment. Hybrid Information -> Native Model ID Information. - Use __BIT(). Add comment. Whitespace fix. To generate a diff of this commit: cvs rdiff -u -r1.150.2.11 -r1.150.2.12 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.150.2.11 src/sys/arch/x86/include/specialreg.h:1.150.2.12 --- src/sys/arch/x86/include/specialreg.h:1.150.2.11 Sat Oct 15 10:08:40 2022 +++ src/sys/arch/x86/include/specialreg.h Mon Jan 23 13:00:53 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.150.2.11 2022/10/15 10:08:40 martin Exp $ */ +/* $NetBSD: specialreg.h,v 1.150.2.12 2023/01/23 13:00:53 martin Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -124,21 +124,21 @@ /* * Extended Control Register XCR0 */ -#define XCR0_X87 0x0001 /* x87 FPU/MMX state */ -#define XCR0_SSE 0x0002 /* SSE state */ -#define XCR0_YMM_Hi128 0x0004 /* AVX-256 (ymmn registers) */ -#define XCR0_BNDREGS 0x0008 /* Memory protection ext bounds */ -#define XCR0_BNDCSR 0x0010 /* Memory protection ext state */ -#define XCR0_Opmask 0x0020 /* AVX-512 Opmask */ -#define XCR0_ZMM_Hi256 0x0040 /* AVX-512 upper 256 bits low regs */ -#define XCR0_Hi16_ZMM 0x0080 /* AVX-512 512 bits upper registers */ -#define XCR0_PT 0x0100 /* Processor Trace state */ -#define XCR0_PKRU 0x0200 /* Protection Key state */ -#define XCR0_CET_U 0x0800 /* User CET state */ -#define XCR0_CET_S 0x1000 /* Kern CET state */ -#define XCR0_HDC 0x2000 /* Hardware Duty Cycle state */ -#define XCR0_LBR 0x8000 /* Last Branch Record */ -#define XCR0_HWP 0x0001 /* Hardware P-states */ +#define XCR0_X87 __BIT(0) /* x87 FPU/MMX state */ +#define XCR0_SSE __BIT(1) /* SSE state */ +#define XCR0_YMM_Hi128 __BIT(2) /* AVX-256 (ymmn registers) */ +#define XCR0_BNDREGS __BIT(3) /* Memory protection ext bounds */ +#define XCR0_BNDCSR __BIT(4) /* Memory protection ext state */ +#define XCR0_Opmask __BIT(5) /* AVX-512 Opmask */ +#define XCR0_ZMM_Hi256 __BIT(6) /* AVX-512 upper 256 bits low regs */ +#define XCR0_Hi16_ZMM __BIT(7) /* AVX-512 512 bits upper registers */ +#define XCR0_PT __BIT(8) /* Processor Trace state */ +#define XCR0_PKRU __BIT(9) /* Protection Key state */ +#define XCR0_CET_U __BIT(11) /* User CET state */ +#define XCR0_CET_S __BIT(12) /* Kern CET state */ +#define XCR0_HDC __BIT(13) /* Hardware Duty Cycle state */ +#define XCR0_LBR __BIT(15) /* Last Branch Record */ +#define XCR0_HWP __BIT(16) /* Hardware P-states */ #define XCR0_FLAGS1 "\20" \ "\1" "x87" "\2" "SSE" "\3" "AVX" "\4" "BNDREGS" \ @@ -224,38 +224,38 @@ #endif /* %ecx */ -#define CPUID2_SSE3 0x0001 /* Streaming SIMD Extensions 3 */ -#define CPUID2_PCLMULQDQ 0x0002 /* PCLMULQDQ instructions */ -#define CPUID2_DTES64 0x0004 /* 64-bit Debug Trace */ -#define CPUID2_MONITOR 0x0008 /* MONITOR/MWAIT instructions */ -#define CPUID2_DS_CPL 0x0010 /* CPL Qualified Debug Store */ -#define CPUID2_VMX 0x0020 /* Virtual Machine eXtensions */ -#define
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src
Committed By: martin
Date: Mon Jan 23 12:27:33 UTC 2023
Modified Files:
src/sys/arch/x86/pci [netbsd-9]: amdzentemp.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1572):
sys/arch/x86/pci/amdzentemp.c: revision 1.16
match zen3 "cezanne" (ryzen 5000-series APU.)
To generate a diff of this commit:
cvs rdiff -u -r1.9.2.2 -r1.9.2.3 src/sys/arch/x86/pci/amdzentemp.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/pci/amdzentemp.c
diff -u src/sys/arch/x86/pci/amdzentemp.c:1.9.2.2 src/sys/arch/x86/pci/amdzentemp.c:1.9.2.3
--- src/sys/arch/x86/pci/amdzentemp.c:1.9.2.2 Tue Oct 11 18:16:20 2022
+++ src/sys/arch/x86/pci/amdzentemp.c Mon Jan 23 12:27:33 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: amdzentemp.c,v 1.9.2.2 2022/10/11 18:16:20 martin Exp $ */
+/* $NetBSD: amdzentemp.c,v 1.9.2.3 2023/01/23 12:27:33 martin Exp $ */
/* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */
/*
@@ -53,7 +53,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.9.2.2 2022/10/11 18:16:20 martin Exp $ ");
+__KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.9.2.3 2023/01/23 12:27:33 martin Exp $ ");
#include
#include
@@ -398,6 +398,7 @@ amdzentemp_probe_ccd_sensors19h(struct a
switch (model) {
case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */
case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */
+ case 0x50 ... 0x5f: /* Zen3 Ryzen "Cezanne" */
maxreg = 8;
break;
case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Mon Jan 23 12:23:53 UTC 2023 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: procfs_machdep.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #1571): sys/arch/x86/x86/procfs_machdep.c: revision 1.46 Add x2avic. Modify comment. To generate a diff of this commit: cvs rdiff -u -r1.33.2.6 -r1.33.2.7 src/sys/arch/x86/x86/procfs_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Mon Jan 23 12:23:53 UTC 2023
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: procfs_machdep.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1571):
sys/arch/x86/x86/procfs_machdep.c: revision 1.46
Add x2avic. Modify comment.
To generate a diff of this commit:
cvs rdiff -u -r1.33.2.6 -r1.33.2.7 src/sys/arch/x86/x86/procfs_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/procfs_machdep.c
diff -u src/sys/arch/x86/x86/procfs_machdep.c:1.33.2.6 src/sys/arch/x86/x86/procfs_machdep.c:1.33.2.7
--- src/sys/arch/x86/x86/procfs_machdep.c:1.33.2.6 Fri Sep 16 18:36:43 2022
+++ src/sys/arch/x86/x86/procfs_machdep.c Mon Jan 23 12:23:53 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: procfs_machdep.c,v 1.33.2.6 2022/09/16 18:36:43 martin Exp $ */
+/* $NetBSD: procfs_machdep.c,v 1.33.2.7 2023/01/23 12:23:53 martin Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -42,7 +42,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.33.2.6 2022/09/16 18:36:43 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.33.2.7 2023/01/23 12:23:53 martin Exp $");
#include
#include
@@ -171,7 +171,7 @@ static const char * const x86_features[]
"tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
NULL, NULL, "pausefilter", NULL, "pfthreshold", "avic", NULL,
"v_vmsave_vmload",
- "vgif", NULL, NULL, NULL, "v_spec_ctrl", NULL, NULL, NULL,
+ "vgif", NULL, "x2avic", NULL, "v_spec_ctrl", NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
{ /* (16) 0x0007:0 ecx */
@@ -183,7 +183,7 @@ static const char * const x86_features[]
NULL, "cldemote", NULL, "movdiri",
"movdir64b", "enqcmd", "sgx_lc", NULL},
- { /* (17) 0x8007 ebx */
+ { /* (17) AMD 0x8007 ebx */
"overflow_recov", "succor", NULL, "smca", NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
CVS commit: [netbsd-9] src/sys/arch/x86
Module Name:src
Committed By: martin
Date: Tue Oct 11 18:05:44 UTC 2022
Modified Files:
src/sys/arch/x86/include [netbsd-9]: cpu_ucode.h
src/sys/arch/x86/x86 [netbsd-9]: cpu_ucode_intel.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1538):
sys/arch/x86/include/cpu_ucode.h: revision 1.5
sys/arch/x86/x86/cpu_ucode_intel.c: revision 1.19
sys/arch/x86/x86/cpu_ucode_intel.c: revision 1.20
Add missing newline in a message. KNF.
Verify checksum of the extended signature table.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.4.6.1 src/sys/arch/x86/include/cpu_ucode.h
cvs rdiff -u -r1.17 -r1.17.2.1 src/sys/arch/x86/x86/cpu_ucode_intel.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpu_ucode.h
diff -u src/sys/arch/x86/include/cpu_ucode.h:1.4 src/sys/arch/x86/include/cpu_ucode.h:1.4.6.1
--- src/sys/arch/x86/include/cpu_ucode.h:1.4 Sat Mar 17 15:56:32 2018
+++ src/sys/arch/x86/include/cpu_ucode.h Tue Oct 11 18:05:44 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_ucode.h,v 1.4 2018/03/17 15:56:32 christos Exp $ */
+/* $NetBSD: cpu_ucode.h,v 1.4.6.1 2022/10/11 18:05:44 martin Exp $ */
/*
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -69,17 +69,16 @@ struct intel1_ucode_header {
uint32_t uh_reserved[3];
};
-struct intel1_ucode_proc_signature {
- uint32_t ups_signature;
- uint32_t ups_proc_flags;
- uint32_t ups_checksum;
-};
-
struct intel1_ucode_ext_table {
uint32_t uet_count;
uint32_t uet_checksum;
uint32_t uet_reserved[3];
- struct intel1_ucode_proc_signature uet_proc_sig[1];
+};
+
+struct intel1_ucode_proc_signature {
+ uint32_t ups_signature;
+ uint32_t ups_proc_flags;
+ uint32_t ups_checksum;
};
#endif
Index: src/sys/arch/x86/x86/cpu_ucode_intel.c
diff -u src/sys/arch/x86/x86/cpu_ucode_intel.c:1.17 src/sys/arch/x86/x86/cpu_ucode_intel.c:1.17.2.1
--- src/sys/arch/x86/x86/cpu_ucode_intel.c:1.17 Fri May 10 18:21:01 2019
+++ src/sys/arch/x86/x86/cpu_ucode_intel.c Tue Oct 11 18:05:44 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_ucode_intel.c,v 1.17 2019/05/10 18:21:01 maxv Exp $ */
+/* $NetBSD: cpu_ucode_intel.c,v 1.17.2.1 2022/10/11 18:05:44 martin Exp $ */
/*
* Copyright (c) 2012, 2019 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: cpu_ucode_intel.c,v 1.17 2019/05/10 18:21:01 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_ucode_intel.c,v 1.17.2.1 2022/10/11 18:05:44 martin Exp $");
#ifdef _KERNEL_OPT
#include "opt_xen.h"
@@ -111,63 +111,65 @@ static int
cpu_ucode_intel_verify(struct cpu_ucode_softc *sc,
struct intel1_ucode_header *buf)
{
+ struct intel1_ucode_ext_table *ehdr;
uint32_t data_size, total_size, payload_size, ext_size;
uint32_t sum;
+ uint32_t *p;
int i;
if ((buf->uh_header_ver != 1) || (buf->uh_loader_rev != 1))
return EINVAL;
- /*
- * Data size.
- */
- if (buf->uh_data_size == 0) {
+ /* Data size. */
+ if (buf->uh_data_size == 0)
data_size = 2000;
- } else {
+ else
data_size = buf->uh_data_size;
- }
if ((data_size % 4) != 0)
return EINVAL;
if (data_size > sc->sc_blobsize)
return EINVAL;
- /*
- * Total size.
- */
- if (buf->uh_total_size == 0) {
+ /* Total size. */
+ if (buf->uh_total_size == 0)
total_size = data_size + 48;
- } else {
+ else
total_size = buf->uh_total_size;
- }
if ((total_size % 1024) != 0)
return EINVAL;
if (total_size > sc->sc_blobsize)
return EINVAL;
- /*
- * Payload size.
- */
+ /* Payload size. */
payload_size = data_size + 48;
if (payload_size > sc->sc_blobsize)
return EINVAL;
- /*
- * Verify checksum of update data and header. Exclude extended
- * signature.
- */
+ /* Verify checksum of update data and header(s). */
sum = 0;
- for (i = 0; i < (payload_size / sizeof(uint32_t)); i++) {
- sum += *((uint32_t *)buf + i);
- }
+ p = (uint32_t *)buf;
+ for (i = 0; i < (payload_size / sizeof(uint32_t)); i++)
+ sum += p[i];
if (sum != 0)
return EINVAL;
- /*
- * Extended table size. Ignored for now.
- */
ext_size = total_size - payload_size;
if (ext_size > 0) {
- printf("This image has extended signature table.");
+ /* This image has extended signature table. */
+ ehdr = (struct intel1_ucode_ext_table *)
+ ((uint8_t *)buf + sizeof(struct intel1_ucode_header) +
+ data_size);
+ payload_size =
+ sizeof(struct intel1_ucode_ext_table) +
+ sizeof(struct intel1_ucode_proc_signature) *
+ ehdr->uet_count;
+
+ sum = 0;
+ p = (uint32_t *)ehdr;
+ for (i = 0; i < (payload_size / sizeof(uint32_t)); i++)
+ sum += p[i];
+ if (sum != 0)
+ return EINVAL;
}
return 0;
@@ -198,7 +200,8 @@ cpu_ucode_intel_apply(struct cpu_ucode_s
/* Make the buffer 16 byte aligned. */
newbufsize = sc->sc_blobsize + 15;
uha = kmem_alloc(newbufsize, KM_SLEEP);
- uh = (struct
CVS commit: [netbsd-9] src/sys/arch/x86
Module Name:src Committed By: martin Date: Tue Oct 11 18:05:44 UTC 2022 Modified Files: src/sys/arch/x86/include [netbsd-9]: cpu_ucode.h src/sys/arch/x86/x86 [netbsd-9]: cpu_ucode_intel.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #1538): sys/arch/x86/include/cpu_ucode.h: revision 1.5 sys/arch/x86/x86/cpu_ucode_intel.c: revision 1.19 sys/arch/x86/x86/cpu_ucode_intel.c: revision 1.20 Add missing newline in a message. KNF. Verify checksum of the extended signature table. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.4.6.1 src/sys/arch/x86/include/cpu_ucode.h cvs rdiff -u -r1.17 -r1.17.2.1 src/sys/arch/x86/x86/cpu_ucode_intel.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86
Module Name:src
Committed By: martin
Date: Mon Oct 10 15:02:51 UTC 2022
Modified Files:
src/sys/arch/x86/include [netbsd-9]: i82093reg.h
src/sys/arch/x86/x86 [netbsd-9]: ioapic.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1536):
sys/arch/x86/x86/ioapic.c: revision 1.66
sys/arch/x86/include/i82093reg.h: revision 1.7
Print detail about misconfigured APIC ID.
IOAPIC_ID_MASK is 8 bits these days. Fixes PR kern/54276.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.6.2.1 src/sys/arch/x86/include/i82093reg.h
cvs rdiff -u -r1.63 -r1.63.2.1 src/sys/arch/x86/x86/ioapic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/i82093reg.h
diff -u src/sys/arch/x86/include/i82093reg.h:1.6 src/sys/arch/x86/include/i82093reg.h:1.6.2.1
--- src/sys/arch/x86/include/i82093reg.h:1.6 Wed Jun 19 06:32:46 2019
+++ src/sys/arch/x86/include/i82093reg.h Mon Oct 10 15:02:50 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: i82093reg.h,v 1.6 2019/06/19 06:32:46 msaitoh Exp $ */
+/* $NetBSD: i82093reg.h,v 1.6.2.1 2022/10/10 15:02:50 martin Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@@ -60,7 +60,7 @@
#define IOAPIC_ID 0x00
#define IOAPIC_ID_SHIFT 24
-#define IOAPIC_ID_MASK 0x0f00
+#define IOAPIC_ID_MASK 0xff00
/* Version, and maximum interrupt pin number. */
Index: src/sys/arch/x86/x86/ioapic.c
diff -u src/sys/arch/x86/x86/ioapic.c:1.63 src/sys/arch/x86/x86/ioapic.c:1.63.2.1
--- src/sys/arch/x86/x86/ioapic.c:1.63 Wed Jun 19 06:32:46 2019
+++ src/sys/arch/x86/x86/ioapic.c Mon Oct 10 15:02:50 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: ioapic.c,v 1.63 2019/06/19 06:32:46 msaitoh Exp $ */
+/* $NetBSD: ioapic.c,v 1.63.2.1 2022/10/10 15:02:50 martin Exp $ */
/*-
* Copyright (c) 2000, 2009 The NetBSD Foundation, Inc.
@@ -64,7 +64,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: ioapic.c,v 1.63 2019/06/19 06:32:46 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ioapic.c,v 1.63.2.1 2022/10/10 15:02:50 martin Exp $");
#include "opt_ddb.h"
@@ -371,8 +371,9 @@ ioapic_attach(device_t parent, device_t
* mapping later ...
*/
if (apic_id != sc->sc_pic.pic_apicid) {
- aprint_debug_dev(sc->sc_dev, "misconfigured as apic %d\n",
- apic_id);
+ aprint_debug_dev(sc->sc_dev,
+ "apid is misconfigured (%d != %d)\n",
+ apic_id, sc->sc_pic.pic_apicid);
ioapic_write(sc, IOAPIC_ID,
(ioapic_read(sc, IOAPIC_ID) & ~IOAPIC_ID_MASK)
@@ -383,7 +384,8 @@ ioapic_attach(device_t parent, device_t
if (apic_id != sc->sc_pic.pic_apicid)
aprint_error_dev(sc->sc_dev,
- "can't remap to apid %d\n", sc->sc_pic.pic_apicid);
+ "can't remap apid from %d to %d\n",
+ apic_id, sc->sc_pic.pic_apicid);
else
aprint_debug_dev(sc->sc_dev, "remapped to apic %d\n",
sc->sc_pic.pic_apicid);
CVS commit: [netbsd-9] src/sys/arch/x86
Module Name:src Committed By: martin Date: Mon Oct 10 15:02:51 UTC 2022 Modified Files: src/sys/arch/x86/include [netbsd-9]: i82093reg.h src/sys/arch/x86/x86 [netbsd-9]: ioapic.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #1536): sys/arch/x86/x86/ioapic.c: revision 1.66 sys/arch/x86/include/i82093reg.h: revision 1.7 Print detail about misconfigured APIC ID. IOAPIC_ID_MASK is 8 bits these days. Fixes PR kern/54276. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.6.2.1 src/sys/arch/x86/include/i82093reg.h cvs rdiff -u -r1.63 -r1.63.2.1 src/sys/arch/x86/x86/ioapic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Fri Sep 16 18:36:43 UTC 2022
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: procfs_machdep.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1526):
sys/arch/x86/x86/procfs_machdep.c: revision 1.45
Add tdx_guest, brs, hfi, ibt, amx_bf16, amx_tile and amx_int8.
To generate a diff of this commit:
cvs rdiff -u -r1.33.2.5 -r1.33.2.6 src/sys/arch/x86/x86/procfs_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/procfs_machdep.c
diff -u src/sys/arch/x86/x86/procfs_machdep.c:1.33.2.5 src/sys/arch/x86/x86/procfs_machdep.c:1.33.2.6
--- src/sys/arch/x86/x86/procfs_machdep.c:1.33.2.5 Mon Jan 31 17:54:59 2022
+++ src/sys/arch/x86/x86/procfs_machdep.c Fri Sep 16 18:36:43 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: procfs_machdep.c,v 1.33.2.5 2022/01/31 17:54:59 martin Exp $ */
+/* $NetBSD: procfs_machdep.c,v 1.33.2.6 2022/09/16 18:36:43 martin Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -42,7 +42,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.33.2.5 2022/01/31 17:54:59 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.33.2.6 2022/09/16 18:36:43 martin Exp $");
#include
#include
@@ -122,7 +122,7 @@ static const char * const x86_features[]
{ /* (8) Linux mapping */
"tpr_shadow", "vnmi", "flexpriority", "ept", "vpid", NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, "vmmcall",
- NULL, "ept_ad", NULL, NULL, NULL, NULL, NULL, NULL,
+ NULL, "ept_ad", NULL, NULL, NULL, NULL, "tdx_guest", NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
{ /* (9) Intel-defined: 0007 ebx */
@@ -157,13 +157,13 @@ static const char * const x86_features[]
"clzero", "irperf", "xsaveerptr", NULL, "rdpru", NULL, NULL, NULL,
NULL, "wbnoinvd", NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, "ppin",
- NULL, "virt_ssbd", NULL, "cppc", NULL, NULL, NULL, NULL},
+ NULL, "virt_ssbd", NULL, "cppc", NULL, NULL, NULL, "brs"},
{ /* (14) 0x0006 eax */
"dtherm", "ida", "arat", NULL, "pln", NULL, "pts", "hwp",
"hwp_notify", "hwp_act_window", "hwp_epp","hwp_pkg_req",
NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, "hfi", NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
{ /* (15) AMD 0x800a edx */
@@ -193,8 +193,8 @@ static const char * const x86_features[]
NULL, NULL, "avx512_4vnniw", "avx512_4fmaps", "fsrm", NULL, NULL, NULL,
"vp2intersect", NULL, "md_clear", NULL, NULL, NULL, "serialize", NULL,
"tsxldtrk", NULL, "pconfig", "arch_lbr",
- NULL, NULL, NULL, "avx512_fp16",
- NULL, NULL, NULL, NULL,
+ "ibt", NULL, "amx_bf16", "avx512_fp16",
+ "amx_tile", "amx_int8", NULL, NULL,
"flush_l1d", "arch_capabilities", NULL, "ssbd"},
{ /* (19) AMD 0x801f eax */
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Fri Sep 16 18:36:43 UTC 2022 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: procfs_machdep.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #1526): sys/arch/x86/x86/procfs_machdep.c: revision 1.45 Add tdx_guest, brs, hfi, ibt, amx_bf16, amx_tile and amx_int8. To generate a diff of this commit: cvs rdiff -u -r1.33.2.5 -r1.33.2.6 src/sys/arch/x86/x86/procfs_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Fri May 13 11:10:38 UTC 2022 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: pmap.c Log Message: Pull up following revision(s) (requested by bouyer in ticket #1443): sys/arch/x86/x86/pmap.c: revision 1.414 return after calling xen_pagezero(), don't fall back to the legacy pmap_zero_page() method. This should only affect performances. To generate a diff of this commit: cvs rdiff -u -r1.334.2.6 -r1.334.2.7 src/sys/arch/x86/x86/pmap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Fri May 13 11:10:38 UTC 2022
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: pmap.c
Log Message:
Pull up following revision(s) (requested by bouyer in ticket #1443):
sys/arch/x86/x86/pmap.c: revision 1.414
return after calling xen_pagezero(), don't fall back to the legacy
pmap_zero_page() method.
This should only affect performances.
To generate a diff of this commit:
cvs rdiff -u -r1.334.2.6 -r1.334.2.7 src/sys/arch/x86/x86/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/pmap.c
diff -u src/sys/arch/x86/x86/pmap.c:1.334.2.6 src/sys/arch/x86/x86/pmap.c:1.334.2.7
--- src/sys/arch/x86/x86/pmap.c:1.334.2.6 Fri Sep 3 10:27:33 2021
+++ src/sys/arch/x86/x86/pmap.c Fri May 13 11:10:38 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.334.2.6 2021/09/03 10:27:33 martin Exp $ */
+/* $NetBSD: pmap.c,v 1.334.2.7 2022/05/13 11:10:38 martin Exp $ */
/*
* Copyright (c) 2008, 2010, 2016, 2017 The NetBSD Foundation, Inc.
@@ -130,7 +130,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.334.2.6 2021/09/03 10:27:33 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.334.2.7 2022/05/13 11:10:38 martin Exp $");
#include "opt_user_ldt.h"
#include "opt_lockdebug.h"
@@ -3187,8 +3187,10 @@ pmap_zero_page(paddr_t pa)
pagezero(PMAP_DIRECT_MAP(pa));
#else
#if defined(XENPV)
- if (XEN_VERSION_SUPPORTED(3, 4))
+ if (XEN_VERSION_SUPPORTED(3, 4)) {
xen_pagezero(pa);
+ return;
+ }
#endif
struct cpu_info *ci;
pt_entry_t *zpte;
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Mon Jan 31 17:54:59 UTC 2022
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: procfs_machdep.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1419):
sys/arch/x86/x86/procfs_machdep.c: revision 1.43
sys/arch/x86/x86/procfs_machdep.c: revision 1.44
Update for cpuid flags:
- The table 11 was changed from CPUID 0x0f leaf 0 %edx to a Linux mapping.
- The table 12 was changed from CPUID 0x0f leaf 1 %edx to CPUID 0x07 leaf 1
%edx. Print avx_vnni and avx512_bf16.
- Print cppc, enqcmd and arch_lbr.
- Modify linux mapping. No used on NetBSD.
Fix procfs_machdep.c rev. 1.143. Print CPUID 0x0007:1 %eax correctly.
To generate a diff of this commit:
cvs rdiff -u -r1.33.2.4 -r1.33.2.5 src/sys/arch/x86/x86/procfs_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/procfs_machdep.c
diff -u src/sys/arch/x86/x86/procfs_machdep.c:1.33.2.4 src/sys/arch/x86/x86/procfs_machdep.c:1.33.2.5
--- src/sys/arch/x86/x86/procfs_machdep.c:1.33.2.4 Fri Dec 3 19:49:35 2021
+++ src/sys/arch/x86/x86/procfs_machdep.c Mon Jan 31 17:54:59 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: procfs_machdep.c,v 1.33.2.4 2021/12/03 19:49:35 martin Exp $ */
+/* $NetBSD: procfs_machdep.c,v 1.33.2.5 2022/01/31 17:54:59 martin Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -42,7 +42,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.33.2.4 2021/12/03 19:49:35 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.33.2.5 2022/01/31 17:54:59 martin Exp $");
#include
#include
@@ -120,10 +120,8 @@ static const char * const x86_features[]
NULL, "ibrs", "ibpb", "stibp", NULL, NULL, NULL, NULL},
{ /* (8) Linux mapping */
- "tpr_shadow", "vnmi", "flexpriority", "ept",
- "vpid", "npt", "lbrv", "svm_lock",
- "nrip_save", "tsc_scale", "vmcb_clean", "flushbyasid",
- "decodeassists", "pausefilter", "pfthreshold", "vmmcall",
+ "tpr_shadow", "vnmi", "flexpriority", "ept", "vpid", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, "vmmcall",
NULL, "ept_ad", NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
@@ -141,15 +139,16 @@ static const char * const x86_features[]
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
- { /* (11) 0x000f:0 edx */
- NULL, "cqm_llc", NULL, NULL, NULL, NULL, NULL, NULL,
+ { /* (11) Linux mapping */
+ "cqm_llc", "cqm_occup_llc", "cqm_mbm_total", "cqm_mbm_local",
+ NULL, NULL, "split_lock_detect", NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
- { /* (12) 0x000f:1 edx */
- "cqm_occup_llc", "cqm_mbm_total", "cqm_mbm_local", NULL,
+ { /* (12) Intel-defined 0x0007:1 eax */
NULL, NULL, NULL, NULL,
+ "avx_vnni", "avx512_bf16", NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
@@ -158,7 +157,7 @@ static const char * const x86_features[]
"clzero", "irperf", "xsaveerptr", NULL, "rdpru", NULL, NULL, NULL,
NULL, "wbnoinvd", NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, "ppin",
- NULL, "virt_ssbd", NULL, NULL, NULL, NULL, NULL, NULL},
+ NULL, "virt_ssbd", NULL, "cppc", NULL, NULL, NULL, NULL},
{ /* (14) 0x0006 eax */
"dtherm", "ida", "arat", NULL, "pln", NULL, "pts", "hwp",
@@ -181,7 +180,8 @@ static const char * const x86_features[]
"gfni", "vaes", "vpclmulqdq", "avx512_vnni",
"avx512_bitalg", "tme", "avx512_vpopcntdq", NULL,
"la57", NULL, NULL, NULL, NULL, NULL, "rdpid", NULL,
- NULL, "cldemote", NULL, "movdiri", "movdir64b", NULL, "sgx_lc", NULL},
+ NULL, "cldemote", NULL, "movdiri",
+ "movdir64b", "enqcmd", "sgx_lc", NULL},
{ /* (17) 0x8007 ebx */
"overflow_recov", "succor", NULL, "smca", NULL, NULL, NULL, NULL,
@@ -192,7 +192,8 @@ static const char * const x86_features[]
{ /* (18) Intel 0x0007 edx */
NULL, NULL, "avx512_4vnniw", "avx512_4fmaps", "fsrm", NULL, NULL, NULL,
"vp2intersect", NULL, "md_clear", NULL, NULL, NULL, "serialize", NULL,
- "tsxldtrk", NULL, "pconfig", NULL, NULL, NULL, NULL, "avx512_fp16",
+ "tsxldtrk", NULL, "pconfig", "arch_lbr",
+ NULL, NULL, NULL, "avx512_fp16",
NULL, NULL, NULL, NULL,
"flush_l1d", "arch_capabilities", NULL, "ssbd"},
@@ -307,14 +308,11 @@ procfs_getonecpufeatures(struct cpu_info
diff = last - *left;
}
- if (ci->ci_max_cpuid >= 0x0f) {
- x86_cpuid2(0x0f, 0, descs);
- procfs_getonefeatreg(descs[3], x86_features[11], p + diff,
- left);
- diff = last - *left;
+ /* x86_features[11] is Linux defined mapping */
- x86_cpuid2(0x0f, 1, descs);
- procfs_getonefeatreg(descs[3], x86_features[12], p
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Mon Jan 31 17:54:59 UTC 2022 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: procfs_machdep.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #1419): sys/arch/x86/x86/procfs_machdep.c: revision 1.43 sys/arch/x86/x86/procfs_machdep.c: revision 1.44 Update for cpuid flags: - The table 11 was changed from CPUID 0x0f leaf 0 %edx to a Linux mapping. - The table 12 was changed from CPUID 0x0f leaf 1 %edx to CPUID 0x07 leaf 1 %edx. Print avx_vnni and avx512_bf16. - Print cppc, enqcmd and arch_lbr. - Modify linux mapping. No used on NetBSD. Fix procfs_machdep.c rev. 1.143. Print CPUID 0x0007:1 %eax correctly. To generate a diff of this commit: cvs rdiff -u -r1.33.2.4 -r1.33.2.5 src/sys/arch/x86/x86/procfs_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Mon Jan 31 17:42:18 UTC 2022 Modified Files: src/sys/arch/x86/include [netbsd-9]: specialreg.h Log Message: Pull up the following revisions (all via patch), requested by msaitoh in ticket #1417: sys/arch/x86/include/specialreg.h 1.179-1.188 - Add CPUID definitions of Last Branch Record, Thread Director, AVX version of VNNI, Fast short REP MOV, HRESET, PPIN, Architectural LBR, Linear Address Masking and Hybrid Information from the latest Intel SDM. - Add CPUID definitions of AddrMaskExt, INT_WBINVD, IbrsSameMode, EferLmsleUnsupported, PSFD and SecureTSC from AMD APM. - Print CLFSH instead of CLFLUSH because both Intel and AMD documents say so. - Modify comment. Add comment. Fix typo. Use __BIT(). KNF. Sort lines. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.150.2.9 -r1.150.2.10 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.150.2.9 src/sys/arch/x86/include/specialreg.h:1.150.2.10 --- src/sys/arch/x86/include/specialreg.h:1.150.2.9 Wed Dec 8 15:44:16 2021 +++ src/sys/arch/x86/include/specialreg.h Mon Jan 31 17:42:17 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.150.2.9 2021/12/08 15:44:16 martin Exp $ */ +/* $NetBSD: specialreg.h,v 1.150.2.10 2022/01/31 17:42:17 martin Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -97,29 +97,29 @@ /* * CR4 */ -#define CR4_VME 0x0001 /* virtual 8086 mode extension enable */ -#define CR4_PVI 0x0002 /* protected mode virtual interrupt enable */ -#define CR4_TSD 0x0004 /* restrict RDTSC instruction to cpl 0 */ -#define CR4_DE 0x0008 /* debugging extension */ -#define CR4_PSE 0x0010 /* large (4MB) page size enable */ -#define CR4_PAE 0x0020 /* physical address extension enable */ -#define CR4_MCE 0x0040 /* machine check enable */ -#define CR4_PGE 0x0080 /* page global enable */ -#define CR4_PCE 0x0100 /* enable RDPMC instruction for all cpls */ -#define CR4_OSFXSR 0x0200 /* enable fxsave/fxrestor and SSE */ -#define CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */ -#define CR4_UMIP 0x0800 /* user-mode instruction prevention */ +#define CR4_VME 0x0001 /* Virtual 8086 mode extension enable */ +#define CR4_PVI 0x0002 /* Protected mode virtual interrupt enable */ +#define CR4_TSD 0x0004 /* Restrict RDTSC instruction to cpl 0 */ +#define CR4_DE 0x0008 /* Debugging extension */ +#define CR4_PSE 0x0010 /* Large (4MB) page size enable */ +#define CR4_PAE 0x0020 /* Physical address extension enable */ +#define CR4_MCE 0x0040 /* Machine check enable */ +#define CR4_PGE 0x0080 /* Page global enable */ +#define CR4_PCE 0x0100 /* Enable RDPMC instruction for all cpls */ +#define CR4_OSFXSR 0x0200 /* Enable fxsave/fxrestor and SSE */ +#define CR4_OSXMMEXCPT 0x0400 /* Enable unmasked SSE exceptions */ +#define CR4_UMIP 0x0800 /* User Mode Instruction Prevention */ #define CR4_LA57 0x1000 /* 57-bit linear addresses */ -#define CR4_VMXE 0x2000 /* enable VMX operations */ -#define CR4_SMXE 0x4000 /* enable SMX operations */ -#define CR4_FSGSBASE 0x0001 /* enable *FSBASE and *GSBASE instructions */ -#define CR4_PCIDE 0x0002 /* enable Process Context IDentifiers */ -#define CR4_OSXSAVE 0x0004 /* enable xsave and xrestore */ -#define CR4_SMEP 0x0010 /* enable SMEP support */ -#define CR4_SMAP 0x0020 /* enable SMAP support */ -#define CR4_PKE 0x0040 /* enable Protection Keys for user pages */ -#define CR4_CET 0x0080 /* enable CET */ -#define CR4_PKS 0x0100 /* enable Protection Keys for kern pages */ +#define CR4_VMXE 0x2000 /* Enable VMX operations */ +#define CR4_SMXE 0x4000 /* Enable SMX operations */ +#define CR4_FSGSBASE 0x0001 /* Enable *FSBASE and *GSBASE instructions */ +#define CR4_PCIDE 0x0002 /* Enable Process Context IDentifiers */ +#define CR4_OSXSAVE 0x0004 /* Enable xsave and xrestore */ +#define CR4_SMEP 0x0010 /* Enable SMEP support */ +#define CR4_SMAP 0x0020 /* Enable SMAP support */ +#define CR4_PKE 0x0040 /* Enable Protection Keys for user pages */ +#define CR4_CET 0x0080 /* Enable CET */ +#define CR4_PKS 0x0100 /* Enable Protection Keys for kern pages */ /* * Extended Control Register XCR0 @@ -137,14 +137,15 @@ #define XCR0_CET_U 0x0800 /* User CET state */ #define XCR0_CET_S 0x1000 /* Kern CET state */ #define XCR0_HDC 0x2000 /* Hardware Duty Cycle state */ +#define XCR0_LBR 0x8000 /* Last Branch Record */ #define XCR0_HWP 0x0001 /* Hardware P-states */ -#define XCR0_FLAGS1 "\20" \ - "\1" "x87" "\2" "SSE" "\3" "AVX" \ - "\4" "BNDREGS" "\5" "BNDCSR"
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Mon Jan 31 17:42:18 UTC 2022 Modified Files: src/sys/arch/x86/include [netbsd-9]: specialreg.h Log Message: Pull up the following revisions (all via patch), requested by msaitoh in ticket #1417: sys/arch/x86/include/specialreg.h 1.179-1.188 - Add CPUID definitions of Last Branch Record, Thread Director, AVX version of VNNI, Fast short REP MOV, HRESET, PPIN, Architectural LBR, Linear Address Masking and Hybrid Information from the latest Intel SDM. - Add CPUID definitions of AddrMaskExt, INT_WBINVD, IbrsSameMode, EferLmsleUnsupported, PSFD and SecureTSC from AMD APM. - Print CLFSH instead of CLFLUSH because both Intel and AMD documents say so. - Modify comment. Add comment. Fix typo. Use __BIT(). KNF. Sort lines. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.150.2.9 -r1.150.2.10 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Tue Dec 7 12:39:24 UTC 2021 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: identcpu.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #1390): sys/arch/x86/x86/identcpu.c: revision 1.121 make a numeric literal unsigned as it is bit-negated. To generate a diff of this commit: cvs rdiff -u -r1.93.2.2 -r1.93.2.3 src/sys/arch/x86/x86/identcpu.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/x86/identcpu.c diff -u src/sys/arch/x86/x86/identcpu.c:1.93.2.2 src/sys/arch/x86/x86/identcpu.c:1.93.2.3 --- src/sys/arch/x86/x86/identcpu.c:1.93.2.2 Tue Dec 7 12:35:27 2021 +++ src/sys/arch/x86/x86/identcpu.c Tue Dec 7 12:39:23 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: identcpu.c,v 1.93.2.2 2021/12/07 12:35:27 martin Exp $ */ +/* $NetBSD: identcpu.c,v 1.93.2.3 2021/12/07 12:39:23 martin Exp $ */ /*- * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.93.2.2 2021/12/07 12:35:27 martin Exp $"); +__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.93.2.3 2021/12/07 12:39:23 martin Exp $"); #include "opt_xen.h" @@ -478,7 +478,7 @@ cpu_probe_cyrix_cmn(struct cpu_info *ci) /* cyrix's workaround for the "coma bug" */ cyrix_write_reg(0x31, cyrix_read_reg(0x31) | 0xf8); cyrix_write_reg(0x32, cyrix_read_reg(0x32) | 0x7f); - cyrix_write_reg(0x33, cyrix_read_reg(0x33) & ~0xff); + cyrix_write_reg(0x33, cyrix_read_reg(0x33) & ~0xffu); cyrix_write_reg(0x3c, cyrix_read_reg(0x3c) | 0x87); /* disable access to ccr4/ccr5 */ cyrix_write_reg(0xC3, c3);
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Tue Dec 7 12:39:24 UTC 2021 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: identcpu.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #1390): sys/arch/x86/x86/identcpu.c: revision 1.121 make a numeric literal unsigned as it is bit-negated. To generate a diff of this commit: cvs rdiff -u -r1.93.2.2 -r1.93.2.3 src/sys/arch/x86/x86/identcpu.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Tue Dec 7 12:35:27 UTC 2021 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: identcpu.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #1389): sys/arch/x86/x86/identcpu.c: revision 1.103 sys/arch/x86/x86/identcpu.c: revision 1.104 sys/arch/x86/x86/identcpu.c: revision 1.105 Add EX2 for Vortex86 SoCs (Andrius V) use __arraycount, and fix comparison flip the comparison again To generate a diff of this commit: cvs rdiff -u -r1.93.2.1 -r1.93.2.2 src/sys/arch/x86/x86/identcpu.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Tue Dec 7 12:35:27 UTC 2021
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: identcpu.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1389):
sys/arch/x86/x86/identcpu.c: revision 1.103
sys/arch/x86/x86/identcpu.c: revision 1.104
sys/arch/x86/x86/identcpu.c: revision 1.105
Add EX2 for Vortex86 SoCs (Andrius V)
use __arraycount, and fix comparison
flip the comparison again
To generate a diff of this commit:
cvs rdiff -u -r1.93.2.1 -r1.93.2.2 src/sys/arch/x86/x86/identcpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/identcpu.c
diff -u src/sys/arch/x86/x86/identcpu.c:1.93.2.1 src/sys/arch/x86/x86/identcpu.c:1.93.2.2
--- src/sys/arch/x86/x86/identcpu.c:1.93.2.1 Thu Sep 26 18:50:18 2019
+++ src/sys/arch/x86/x86/identcpu.c Tue Dec 7 12:35:27 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: identcpu.c,v 1.93.2.1 2019/09/26 18:50:18 martin Exp $ */
+/* $NetBSD: identcpu.c,v 1.93.2.2 2021/12/07 12:35:27 martin Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.93.2.1 2019/09/26 18:50:18 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.93.2.2 2021/12/07 12:35:27 martin Exp $");
#include "opt_xen.h"
@@ -704,7 +704,7 @@ cpu_probe_vortex86(struct cpu_info *ci)
#define PCI_MODE1_DATA_REG 0x0cfc
#define PCI_MODE1_ENABLE 0x8000UL
- uint32_t reg;
+ uint32_t reg, idx;
if (cpu_vendor != CPUVENDOR_VORTEX86)
return;
@@ -718,17 +718,18 @@ cpu_probe_vortex86(struct cpu_info *ci)
outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE | 0x90);
reg = inl(PCI_MODE1_DATA_REG);
- if ((reg & 0xf8ff) != 0x30504d44) {
- reg = 0;
+ if ((reg & 0xf0ff) != 0x30504d44) {
+ idx = 0;
} else {
- reg = (reg >> 24) & 7;
+ idx = (reg >> 24) & 0xf;
}
static const char *cpu_vortex86_flavor[] = {
- "??", "SX", "DX", "MX", "DX2", "MX+", "DX3", "EX",
+ "??", "SX", "DX", "MX", "DX2", "MX+", "DX3", "EX", "EX2",
};
+ idx = idx < __arraycount(cpu_vortex86_flavor) ? idx : 0;
snprintf(cpu_brand_string, sizeof(cpu_brand_string), "Vortex86%s",
- cpu_vortex86_flavor[reg]);
+ cpu_vortex86_flavor[idx]);
#undef PCI_MODE1_ENABLE
#undef PCI_MODE1_ADDRESS_REG
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Fri Dec 3 19:49:35 UTC 2021
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: procfs_machdep.c
Log Message:
Pull up the following revisions, requested by msaitoh in ticket #1385:
sys/arch/x86/x86/procfs_machdep.c 1.40-1.42
- Add v_spec_ctrl, avx512_fp16, sme, sev, sev_es, sgx, sgx_lc,
serialize and tsxldtrk.
- Whitespace fix.
To generate a diff of this commit:
cvs rdiff -u -r1.33.2.3 -r1.33.2.4 src/sys/arch/x86/x86/procfs_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/procfs_machdep.c
diff -u src/sys/arch/x86/x86/procfs_machdep.c:1.33.2.3 src/sys/arch/x86/x86/procfs_machdep.c:1.33.2.4
--- src/sys/arch/x86/x86/procfs_machdep.c:1.33.2.3 Fri Jul 10 10:36:56 2020
+++ src/sys/arch/x86/x86/procfs_machdep.c Fri Dec 3 19:49:35 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: procfs_machdep.c,v 1.33.2.3 2020/07/10 10:36:56 martin Exp $ */
+/* $NetBSD: procfs_machdep.c,v 1.33.2.4 2021/12/03 19:49:35 martin Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -42,7 +42,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.33.2.3 2020/07/10 10:36:56 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.33.2.4 2021/12/03 19:49:35 martin Exp $");
#include
#include
@@ -82,11 +82,13 @@ static const char * const x86_features[]
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
{ /* (3) Linux mapping */
- "cxmmx", NULL, "cyrix_arr", "centaur_mcr", NULL,
- "constant_tsc", NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
+ "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr", NULL, NULL, NULL, NULL,
+ "constant_tsc", "up", "art", "arch_perfmon",
+ "pebs", "bts", NULL, NULL,
+ "rep_good", NULL, NULL, "acc_power",
+ "nopl", NULL, "xtopology", "tsc_reliable",
+ "nonstop_tsc", "cpuid", "extd_apicid", "amd_dcm",
+ "aperfmperf", "rapl", "nonstop_tsc_s3", "tsc_known_freq"},
{ /* (4) Intel-defined: 0x0001 ecx */
"pni", "pclmulqdq", "dtes64", "monitor", "ds_cpl", "vmx", "smx", "est",
@@ -112,7 +114,7 @@ static const char * const x86_features[]
{ /* (7) Linux mapping */
NULL, NULL, "cpb", "ebp", NULL, "pln", "pts", "dtherm",
- "hw_pstate", "proc_feedback", "sme", NULL,
+ "hw_pstate", "proc_feedback", NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, "ibrs", "ibpb", "stibp", NULL, NULL, NULL, NULL},
@@ -126,7 +128,7 @@ static const char * const x86_features[]
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
{ /* (9) Intel-defined: 0007 ebx */
- "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
+ "fsgsbase", "tsc_adjust", "sgx", "bmi1", "hle", "avx2", NULL, "smep",
"bmi2", "erms", "invpcid", "rtm", "cqm", NULL, "mpx", "rdt_a",
"avx512f", "avx512dq", "rdseed", "adx",
"smap", "avx512ifma", NULL, "clflushopt",
@@ -165,12 +167,12 @@ static const char * const x86_features[]
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
- { /* (15) 0x800a edx */
+ { /* (15) AMD 0x800a edx */
"npt", "lbrv", "svm_lock", "nrip_save",
"tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
NULL, NULL, "pausefilter", NULL, "pfthreshold", "avic", NULL,
"v_vmsave_vmload",
- "vgif", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ "vgif", NULL, NULL, NULL, "v_spec_ctrl", NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
{ /* (16) 0x0007:0 ecx */
@@ -179,7 +181,7 @@ static const char * const x86_features[]
"gfni", "vaes", "vpclmulqdq", "avx512_vnni",
"avx512_bitalg", "tme", "avx512_vpopcntdq", NULL,
"la57", NULL, NULL, NULL, NULL, NULL, "rdpid", NULL,
- NULL, "cldemote", NULL, "movdiri", "movdir64b", NULL, NULL, NULL},
+ NULL, "cldemote", NULL, "movdiri", "movdir64b", NULL, "sgx_lc", NULL},
{ /* (17) 0x8007 ebx */
"overflow_recov", "succor", NULL, "smca", NULL, NULL, NULL, NULL,
@@ -189,10 +191,16 @@ static const char * const x86_features[]
{ /* (18) Intel 0x0007 edx */
NULL, NULL, "avx512_4vnniw", "avx512_4fmaps", "fsrm", NULL, NULL, NULL,
- "vp2intersect", NULL, "md_clear", NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, "pconfig", NULL, NULL, NULL, NULL, NULL,
+ "vp2intersect", NULL, "md_clear", NULL, NULL, NULL, "serialize", NULL,
+ "tsxldtrk", NULL, "pconfig", NULL, NULL, NULL, NULL, "avx512_fp16",
NULL, NULL, NULL, NULL,
"flush_l1d", "arch_capabilities", NULL, "ssbd"},
+
+ { /* (19) AMD 0x801f eax */
+ "sme", "sev", NULL, "sev_es", NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
};
static int procfs_getonecpu(int, struct cpu_info *, char *, size_t *);
@@
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Fri Dec 3 19:49:35 UTC 2021 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: procfs_machdep.c Log Message: Pull up the following revisions, requested by msaitoh in ticket #1385: sys/arch/x86/x86/procfs_machdep.c 1.40-1.42 - Add v_spec_ctrl, avx512_fp16, sme, sev, sev_es, sgx, sgx_lc, serialize and tsxldtrk. - Whitespace fix. To generate a diff of this commit: cvs rdiff -u -r1.33.2.3 -r1.33.2.4 src/sys/arch/x86/x86/procfs_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Fri Sep 3 10:27:33 UTC 2021
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: pmap.c
Log Message:
Pull up following revision(s) (requested by manu in ticket #1341):
sys/arch/x86/x86/pmap.c: revision 1.410
Make pat_init() a NOOP on XENPV; it causes a trap with Xen 4.15
To generate a diff of this commit:
cvs rdiff -u -r1.334.2.5 -r1.334.2.6 src/sys/arch/x86/x86/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/pmap.c
diff -u src/sys/arch/x86/x86/pmap.c:1.334.2.5 src/sys/arch/x86/x86/pmap.c:1.334.2.6
--- src/sys/arch/x86/x86/pmap.c:1.334.2.5 Thu Sep 3 13:45:24 2020
+++ src/sys/arch/x86/x86/pmap.c Fri Sep 3 10:27:33 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.334.2.5 2020/09/03 13:45:24 martin Exp $ */
+/* $NetBSD: pmap.c,v 1.334.2.6 2021/09/03 10:27:33 martin Exp $ */
/*
* Copyright (c) 2008, 2010, 2016, 2017 The NetBSD Foundation, Inc.
@@ -130,7 +130,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.334.2.5 2020/09/03 13:45:24 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.334.2.6 2021/09/03 10:27:33 martin Exp $");
#include "opt_user_ldt.h"
#include "opt_lockdebug.h"
@@ -806,6 +806,7 @@ pmap_exec_fixup(struct vm_map *map, stru
void
pat_init(struct cpu_info *ci)
{
+#ifndef XENPV
uint64_t pat;
if (!(ci->ci_feat_val[0] & CPUID_PAT))
@@ -819,6 +820,7 @@ pat_init(struct cpu_info *ci)
wrmsr(MSR_CR_PAT, pat);
cpu_pat_enabled = true;
+#endif
}
static pt_entry_t
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Fri Sep 3 10:27:33 UTC 2021 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: pmap.c Log Message: Pull up following revision(s) (requested by manu in ticket #1341): sys/arch/x86/x86/pmap.c: revision 1.410 Make pat_init() a NOOP on XENPV; it causes a trap with Xen 4.15 To generate a diff of this commit: cvs rdiff -u -r1.334.2.5 -r1.334.2.6 src/sys/arch/x86/x86/pmap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src
Committed By: martin
Date: Mon Jun 21 17:19:55 UTC 2021
Modified Files:
src/sys/arch/x86/pci [netbsd-9]: dwiic_pci.c
Log Message:
Pull up following revision(s) (requested by riastradh in ticket #1303):
sys/arch/x86/pci/dwiic_pci.c: revision 1.5 (patch)
dwiic(4): Attribute output correctly and relegate to debug-level.
Tidy up a little while here.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.2.4.1 src/sys/arch/x86/pci/dwiic_pci.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/pci/dwiic_pci.c
diff -u src/sys/arch/x86/pci/dwiic_pci.c:1.2 src/sys/arch/x86/pci/dwiic_pci.c:1.2.4.1
--- src/sys/arch/x86/pci/dwiic_pci.c:1.2 Wed Sep 26 19:06:33 2018
+++ src/sys/arch/x86/pci/dwiic_pci.c Mon Jun 21 17:19:55 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: dwiic_pci.c,v 1.2 2018/09/26 19:06:33 jakllsch Exp $ */
+/* $NetBSD: dwiic_pci.c,v 1.2.4.1 2021/06/21 17:19:55 martin Exp $ */
/*-
* Copyright (c) 2017 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: dwiic_pci.c,v 1.2 2018/09/26 19:06:33 jakllsch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dwiic_pci.c,v 1.2.4.1 2021/06/21 17:19:55 martin Exp $");
#include
#include
@@ -68,9 +68,8 @@ struct pci_dwiic_softc {
static uint32_t
lpss_read(struct pci_dwiic_softc *sc, int offset)
{
- u_int32_t b = bus_space_read_4(sc->sc_dwiic.sc_iot, sc->sc_dwiic.sc_ioh,
- offset);
- return b;
+ return bus_space_read_4(sc->sc_dwiic.sc_iot, sc->sc_dwiic.sc_ioh,
+ offset);
}
static void
@@ -169,7 +168,7 @@ pci_dwiic_attach(device_t parent, device
pa->pa_bus, pa->pa_device, pa->pa_function);
if (sc->sc_acpinode) {
- sc->sc_dwiic.sc_iba.iba_child_devices =
+ sc->sc_dwiic.sc_iba.iba_child_devices =
acpi_enter_i2c_devs(sc->sc_acpinode);
} else {
aprint_verbose_dev(self, "no matching ACPI node\n");
@@ -188,13 +187,18 @@ out:
static bool
dwiic_pci_power(struct dwiic_softc *dwsc, bool power)
{
- struct pci_dwiic_softc *sc = (void *)dwsc;
- pcireg_t pmreg;
-
- printf("status 0x%x\n", pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_COMMAND_STATUS_REG));
- printf("reset 0x%x\n", lpss_read(sc, LPSS_RESET));
- printf("rlo 0x%x\n", lpss_read(sc, LPSS_REMAP_LO));
- printf("rho 0x%x\n", lpss_read(sc, LPSS_REMAP_HI));
+ struct pci_dwiic_softc *sc = container_of(dwsc, struct pci_dwiic_softc,
+ sc_dwiic);
+ pcireg_t pmreg, csr;
+ uint32_t reset, rlo, rhi;
+
+ csr = pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_COMMAND_STATUS_REG);
+ reset = lpss_read(sc, LPSS_RESET);
+ rlo = lpss_read(sc, LPSS_REMAP_LO);
+ rhi = lpss_read(sc, LPSS_REMAP_HI);
+ aprint_debug_dev(dwsc->sc_dev,
+ "status 0x%x reset 0x%x rlo 0x%x rhi 0x%x\n",
+ csr, reset, rlo, rhi);
if (!power)
lpss_write(sc, LPSS_CLKGATE, LPSS_CLKGATE_CTRL_OFF);
@@ -205,7 +209,7 @@ dwiic_pci_power(struct dwiic_softc *dwsc
pci_conf_write(sc->sc_pc, sc->sc_ptag, pmreg + PCI_PMCSR,
power ? PCI_PMCSR_STATE_D0 : PCI_PMCSR_STATE_D3);
DELAY(1); /* 10 milliseconds */
- DPRINTF((" -> 0x%x\n",
+ DPRINTF((" -> 0x%x\n",
pci_conf_read(sc->sc_pc, sc->sc_ptag, pmreg + PCI_PMCSR)));
}
if (power) {
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src Committed By: martin Date: Mon Jun 21 17:19:55 UTC 2021 Modified Files: src/sys/arch/x86/pci [netbsd-9]: dwiic_pci.c Log Message: Pull up following revision(s) (requested by riastradh in ticket #1303): sys/arch/x86/pci/dwiic_pci.c: revision 1.5 (patch) dwiic(4): Attribute output correctly and relegate to debug-level. Tidy up a little while here. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.2.4.1 src/sys/arch/x86/pci/dwiic_pci.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Fri Feb 19 17:47:13 UTC 2021
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: intr.c
Log Message:
Pull up following revision(s) (requested by knakahara in ticket #1209):
sys/arch/x86/x86/intr.c: revision 1.154 (via patch)
Fix x86's pci_intr_disestablish clean up routine. Pointed out by t-kusaba@IIJ,
thanks.
Fix panic on x86 by the following code.
sc_ih = pci_intr_establish_xname(sc_pc, ...);
pci_intr_disestablish(sc_pc, sc_ih);
sc_ih = pci_intr_establish(sc_pc, ...);
ena(4) do such processing when ifconfig down/up.
XXX pullup-8,9
To generate a diff of this commit:
cvs rdiff -u -r1.146.2.1 -r1.146.2.2 src/sys/arch/x86/x86/intr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/intr.c
diff -u src/sys/arch/x86/x86/intr.c:1.146.2.1 src/sys/arch/x86/x86/intr.c:1.146.2.2
--- src/sys/arch/x86/x86/intr.c:1.146.2.1 Mon Nov 11 17:20:00 2019
+++ src/sys/arch/x86/x86/intr.c Fri Feb 19 17:47:13 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.c,v 1.146.2.1 2019/11/11 17:20:00 martin Exp $ */
+/* $NetBSD: intr.c,v 1.146.2.2 2021/02/19 17:47:13 martin Exp $ */
/*
* Copyright (c) 2007, 2008, 2009 The NetBSD Foundation, Inc.
@@ -133,7 +133,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.146.2.1 2019/11/11 17:20:00 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.146.2.2 2021/02/19 17:47:13 martin Exp $");
#include "opt_intrdebug.h"
#include "opt_multiprocessor.h"
@@ -704,6 +704,9 @@ intr_source_free(struct cpu_info *ci, in
ci->ci_isources[slot] = NULL;
if (pic != _pic)
idt_vec_free(idtvec);
+
+ isp->is_recurse = NULL;
+ isp->is_resume = NULL;
}
#ifdef MULTIPROCESSOR
@@ -1042,12 +1045,12 @@ intr_disestablish_xcall(void *arg1, void
else
(*pic->pic_hwunmask)(pic, ih->ih_pin);
- /* Re-enable interrupts. */
- x86_write_psl(psl);
-
/* If the source is free we can drop it now. */
intr_source_free(ci, ih->ih_slot, pic, idtvec);
+ /* Re-enable interrupts. */
+ x86_write_psl(psl);
+
DPRINTF(("%s: remove slot %d (pic %s pin %d vec %d)\n",
device_xname(ci->ci_dev), ih->ih_slot, pic->pic_name,
ih->ih_pin, idtvec));
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Fri Feb 19 17:47:13 UTC 2021 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: intr.c Log Message: Pull up following revision(s) (requested by knakahara in ticket #1209): sys/arch/x86/x86/intr.c: revision 1.154 (via patch) Fix x86's pci_intr_disestablish clean up routine. Pointed out by t-kusaba@IIJ, thanks. Fix panic on x86 by the following code. sc_ih = pci_intr_establish_xname(sc_pc, ...); pci_intr_disestablish(sc_pc, sc_ih); sc_ih = pci_intr_establish(sc_pc, ...); ena(4) do such processing when ifconfig down/up. XXX pullup-8,9 To generate a diff of this commit: cvs rdiff -u -r1.146.2.1 -r1.146.2.2 src/sys/arch/x86/x86/intr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Thu Sep 3 13:45:24 UTC 2020 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: pmap.c Log Message: Apply patch, requested by bouyer in ticket #1075: sys/arch/x86/x86/pmap.c (apply patch) Fix double count on ptp entries in pmap_enter_gnt(), which causes a KASSERT at pmap_destroy() time. Call pmap_free_ptp() if needed. We can have a 0 wire count if we had an old mapping and grant map hypercall failed, and this was the only page in this ptp. while there remove ptp != NULL checks for gnt operations: we always have a ptp here. To generate a diff of this commit: cvs rdiff -u -r1.334.2.4 -r1.334.2.5 src/sys/arch/x86/x86/pmap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Thu Sep 3 13:45:24 UTC 2020
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: pmap.c
Log Message:
Apply patch, requested by bouyer in ticket #1075:
sys/arch/x86/x86/pmap.c (apply patch)
Fix double count on ptp entries in pmap_enter_gnt(), which causes a KASSERT
at pmap_destroy() time. Call pmap_free_ptp() if needed. We can have a 0 wire
count if we had an old mapping and grant map hypercall failed,
and this was the only page in this ptp.
while there remove ptp != NULL checks for gnt operations: we always have
a ptp here.
To generate a diff of this commit:
cvs rdiff -u -r1.334.2.4 -r1.334.2.5 src/sys/arch/x86/x86/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/pmap.c
diff -u src/sys/arch/x86/x86/pmap.c:1.334.2.4 src/sys/arch/x86/x86/pmap.c:1.334.2.5
--- src/sys/arch/x86/x86/pmap.c:1.334.2.4 Wed Sep 2 12:40:06 2020
+++ src/sys/arch/x86/x86/pmap.c Thu Sep 3 13:45:24 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.334.2.4 2020/09/02 12:40:06 martin Exp $ */
+/* $NetBSD: pmap.c,v 1.334.2.5 2020/09/03 13:45:24 martin Exp $ */
/*
* Copyright (c) 2008, 2010, 2016, 2017 The NetBSD Foundation, Inc.
@@ -130,7 +130,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.334.2.4 2020/09/02 12:40:06 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.334.2.5 2020/09/03 13:45:24 martin Exp $");
#include "opt_user_ldt.h"
#include "opt_lockdebug.h"
@@ -4559,28 +4559,21 @@ pmap_enter_gnt(struct pmap *pmap, vaddr_
if (__predict_false(op->status != GNTST_okay)) {
printf("%s: GNTTABOP_map_grant_ref status: %d\n",
__func__, op->status);
- if (ptp != NULL) {
- if (have_oldpa) {
-ptp->wire_count--;
- }
+ if (have_oldpa) {
+ ptp->wire_count--;
}
} else {
pgnt->pd_gnt_refs++;
- if (ptp != NULL) {
- if (!have_oldpa) {
-ptp->wire_count++;
- }
+ if (!have_oldpa) {
+ ptp->wire_count++;
}
+ KASSERT(ptp->wire_count > 1);
}
/*
* Update statistics and PTP's reference count.
*/
pmap_stats_update_bypte(pmap, 0, opte);
- if (ptp != NULL && !have_oldpa) {
- ptp->wire_count++;
- }
- KASSERT(ptp == NULL || ptp->wire_count > 1);
/*
* If old page is pv-tracked, remove pv_entry from its list.
@@ -4599,6 +4592,8 @@ pmap_enter_gnt(struct pmap *pmap, vaddr_
old_pve = pmap_remove_pv(old_pp, ptp, va);
old_pp->pp_attrs |= pmap_pte_to_pp_attrs(opte);
}
+ if (ptp->wire_count <= 1)
+ pmap_free_ptp(pmap, ptp, va, ptes, pdes);
pmap_unmap_ptes(pmap, pmap2);
@@ -4687,7 +4682,7 @@ pmap_remove_gnt(struct pmap *pmap, vaddr
* being used, free it!
*/
- if (ptp && ptp->wire_count <= 1)
+ if (ptp->wire_count <= 1)
pmap_free_ptp(pmap, ptp, va, ptes, pdes);
}
pmap_unmap_ptes(pmap, pmap2); /* unlock pmap */
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Wed Sep 2 12:40:06 UTC 2020
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: pmap.c
Log Message:
Pull up following revision(s) (requested by bouyer in ticket #1073):
sys/arch/x86/x86/pmap.c: revision 1.404
Fix braino in pmap_find_gnt(), really return the gnt entry covering the range
and not one that starts just after.
Fixes a KASSERT in pmap_remove_gnt().
To generate a diff of this commit:
cvs rdiff -u -r1.334.2.3 -r1.334.2.4 src/sys/arch/x86/x86/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/pmap.c
diff -u src/sys/arch/x86/x86/pmap.c:1.334.2.3 src/sys/arch/x86/x86/pmap.c:1.334.2.4
--- src/sys/arch/x86/x86/pmap.c:1.334.2.3 Sun Jun 7 12:54:39 2020
+++ src/sys/arch/x86/x86/pmap.c Wed Sep 2 12:40:06 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.334.2.3 2020/06/07 12:54:39 martin Exp $ */
+/* $NetBSD: pmap.c,v 1.334.2.4 2020/09/02 12:40:06 martin Exp $ */
/*
* Copyright (c) 2008, 2010, 2016, 2017 The NetBSD Foundation, Inc.
@@ -130,7 +130,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.334.2.3 2020/06/07 12:54:39 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.334.2.4 2020/09/02 12:40:06 martin Exp $");
#include "opt_user_ldt.h"
#include "opt_lockdebug.h"
@@ -4408,7 +4408,7 @@ pmap_find_gnt(struct pmap *pmap, vaddr_t
headp = pmap->pm_data;
KASSERT(headp != NULL);
SLIST_FOREACH(pgnt, headp, pd_gnt_list) {
- if (pgnt->pd_gnt_sva >= sva && pgnt->pd_gnt_sva <= eva)
+ if (pgnt->pd_gnt_sva <= sva && eva <= pgnt->pd_gnt_eva)
return pgnt;
/* check that we're not overlapping part of a region */
KASSERT(pgnt->pd_gnt_sva >= eva || pgnt->pd_gnt_eva <= sva);
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Wed Sep 2 12:40:06 UTC 2020 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: pmap.c Log Message: Pull up following revision(s) (requested by bouyer in ticket #1073): sys/arch/x86/x86/pmap.c: revision 1.404 Fix braino in pmap_find_gnt(), really return the gnt entry covering the range and not one that starts just after. Fixes a KASSERT in pmap_remove_gnt(). To generate a diff of this commit: cvs rdiff -u -r1.334.2.3 -r1.334.2.4 src/sys/arch/x86/x86/pmap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Sun Aug 2 07:33:38 UTC 2020
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: cpu.c
Log Message:
Apply patch, requested by msaitoh in ticket #1031:
sys/arch/x86/x86/cpu.c patch
Fix a panic on a CPU which has no rdtsc instruction. This bug was
added in ticket #1015.
To generate a diff of this commit:
cvs rdiff -u -r1.171.2.2 -r1.171.2.3 src/sys/arch/x86/x86/cpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/cpu.c
diff -u src/sys/arch/x86/x86/cpu.c:1.171.2.2 src/sys/arch/x86/x86/cpu.c:1.171.2.3
--- src/sys/arch/x86/x86/cpu.c:1.171.2.2 Wed Jul 15 17:25:08 2020
+++ src/sys/arch/x86/x86/cpu.c Sun Aug 2 07:33:38 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.171.2.2 2020/07/15 17:25:08 martin Exp $ */
+/* $NetBSD: cpu.c,v 1.171.2.3 2020/08/02 07:33:38 martin Exp $ */
/*
* Copyright (c) 2000-2012 NetBSD Foundation, Inc.
@@ -62,7 +62,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.171.2.2 2020/07/15 17:25:08 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.171.2.3 2020/08/02 07:33:38 martin Exp $");
#include "opt_ddb.h"
#include "opt_mpbios.h" /* for MPDEBUG */
@@ -1267,18 +1267,19 @@ cpu_get_tsc_freq(struct cpu_info *ci)
{
uint64_t freq = 0, last_tsc;
- if (cpu_hascounter())
+ if (cpu_hascounter()) {
freq = cpu_tsc_freq_cpuid(ci);
- if (freq != 0) {
- /* Use TSC frequency taken from CPUID. */
- ci->ci_data.cpu_cc_freq = freq;
- } else {
- /* Calibrate TSC frequency. */
- last_tsc = cpu_counter_serializing();
- x86_delay(10);
- ci->ci_data.cpu_cc_freq =
- (cpu_counter_serializing() - last_tsc) * 10;
+ if (freq != 0) {
+ /* Use TSC frequency taken from CPUID. */
+ ci->ci_data.cpu_cc_freq = freq;
+ } else {
+ /* Calibrate TSC frequency. */
+ last_tsc = cpu_counter_serializing();
+ x86_delay(10);
+ ci->ci_data.cpu_cc_freq =
+ (cpu_counter_serializing() - last_tsc) * 10;
+ }
}
}
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Sun Aug 2 07:33:38 UTC 2020 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: cpu.c Log Message: Apply patch, requested by msaitoh in ticket #1031: sys/arch/x86/x86/cpu.c patch Fix a panic on a CPU which has no rdtsc instruction. This bug was added in ticket #1015. To generate a diff of this commit: cvs rdiff -u -r1.171.2.2 -r1.171.2.3 src/sys/arch/x86/x86/cpu.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Wed Jul 15 14:02:36 UTC 2020
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: coretemp.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1009):
sys/arch/x86/x86/coretemp.c: revision 1.37
Add special handling for model 0x0f stepping >=2 or mode 0x0e to get Tjmax.
To generate a diff of this commit:
cvs rdiff -u -r1.36 -r1.36.4.1 src/sys/arch/x86/x86/coretemp.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/coretemp.c
diff -u src/sys/arch/x86/x86/coretemp.c:1.36 src/sys/arch/x86/x86/coretemp.c:1.36.4.1
--- src/sys/arch/x86/x86/coretemp.c:1.36 Wed Jul 11 03:36:32 2018
+++ src/sys/arch/x86/x86/coretemp.c Wed Jul 15 14:02:36 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: coretemp.c,v 1.36 2018/07/11 03:36:32 msaitoh Exp $ */
+/* $NetBSD: coretemp.c,v 1.36.4.1 2020/07/15 14:02:36 martin Exp $ */
/*-
* Copyright (c) 2011 The NetBSD Foundation, Inc.
@@ -61,7 +61,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.36 2018/07/11 03:36:32 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.36.4.1 2020/07/15 14:02:36 martin Exp $");
#include
#include
@@ -271,6 +271,19 @@ coretemp_tjmax(device_t self)
sc->sc_tjmax = 100;
if ((model == 0x0f && stepping >= 2) || (model == 0x0e)) {
+ /*
+ * Check MSR_IA32_PLATFORM_ID(0x17) bit 28. It's not documented
+ * in the datasheet, but the following page describes the
+ * detail:
+ * http://software.intel.com/en-us/articles/
+ * mobile-intel-core2-processor-detection-table/
+ * Was: http://softwarecommunity.intel.com/Wiki/Mobility/
+ * 720.htm
+ */
+ if (rdmsr_safe(MSR_IA32_PLATFORM_ID, ) != 0)
+ goto notee;
+ if ((model < 0x17) && ((msr & __BIT(28)) == 0))
+ goto notee;
if (rdmsr_safe(MSR_IA32_EXT_CONFIG, ) == EFAULT)
return;
@@ -290,6 +303,7 @@ coretemp_tjmax(device_t self)
} else
sc->sc_tjmax = 90;
} else {
+notee:
/*
* Attempt to get Tj(max) from IA32_TEMPERATURE_TARGET,
* but only consider the interval [70, 110] C as valid.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Wed Jul 15 14:02:36 UTC 2020 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: coretemp.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #1009): sys/arch/x86/x86/coretemp.c: revision 1.37 Add special handling for model 0x0f stepping >=2 or mode 0x0e to get Tjmax. To generate a diff of this commit: cvs rdiff -u -r1.36 -r1.36.4.1 src/sys/arch/x86/x86/coretemp.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Mon Jul 13 13:33:29 UTC 2020 Modified Files: src/sys/arch/x86/include [netbsd-9]: specialreg.h Log Message: Pull up following revision(s) (requested by msaitoh in ticket #998): sys/arch/x86/include/specialreg.h: revision 1.162 sys/arch/x86/include/specialreg.h: revision 1.164 sys/arch/x86/include/specialreg.h: revision 1.165 sys/arch/x86/include/specialreg.h: revision 1.166 sys/arch/x86/include/specialreg.h: revision 1.167 sys/arch/x86/include/specialreg.h: revision 1.168 - AMD CPUID Fn8000_000a %edx bit 20 is "SPEC_CTRL". - Add some bit definitions of AMD's CPUID Fn8000_001f Encrypted Memory features. - Add AMD INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC intercept bit. - Modify comment. Add AMD MSR_DE_CFG's bit 1 as DE_CFG_LFENCE_SERIALIZE. This bit makes lfence instruction serializing. Add some definitions from the latest Intel SDM plus small fix: - Add CPUID leaf 6 %eax bit 19 for HW_FEEDBACK* and IA32_PACKAGE_TERM* MSRs. - Add CPUID leaf 7 %ecx bit 31 for Protection Keys. - Add definition of Load only TLB and Store only TLB. - Add IF_PSCHANGE_MC_NO bit of IA32_ARCH_CAPABILITIES - Fix HWP_IGNIDL. Add SRBDS_CTRL bit. style and fix typo To generate a diff of this commit: cvs rdiff -u -r1.150.2.6 -r1.150.2.7 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.150.2.6 src/sys/arch/x86/include/specialreg.h:1.150.2.7 --- src/sys/arch/x86/include/specialreg.h:1.150.2.6 Tue Apr 14 17:15:02 2020 +++ src/sys/arch/x86/include/specialreg.h Mon Jul 13 13:33:29 2020 @@ -1,7 +1,7 @@ -/* $NetBSD: specialreg.h,v 1.150.2.6 2020/04/14 17:15:02 martin Exp $ */ +/* $NetBSD: specialreg.h,v 1.150.2.7 2020/07/13 13:33:29 martin Exp $ */ /* - * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. + * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -294,10 +294,10 @@ ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4))) /* CPUID Fn0001 %ebx */ -#define CPUID_BRAND_INDEX __BITS(7,0) -#define CPUID_CLFLUSH_SIZE __BITS(15,8) -#define CPUID_HTT_CORES __BITS(23,16) -#define CPUID_LOCAL_APIC_ID __BITS(31,24) +#define CPUID_BRAND_INDEX __BITS(7,0) +#define CPUID_CLFLUSH_SIZE __BITS(15,8) +#define CPUID_HTT_CORES __BITS(23,16) +#define CPUID_LOCAL_APIC_ID __BITS(31,24) /* * Intel Deterministic Cache Parameter Leaf @@ -367,6 +367,7 @@ #define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */ #define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */ #define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */ +#define CPUID_DSPM_HW_FEEDBACK __BIT(19) /* HW_FEEDBACK*, IA32_PACKAGE_TERM* */ #define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */ #define CPUID_DSPM_FLAGS "\20" \ @@ -374,8 +375,8 @@ "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \ "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \ - "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" \ - "25" "HWP_IGNIDL" + "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" "\24HW_FEEDBACK" \ + "\25" "HWP_IGNIDL" /* * Intel/AMD Digital Thermal Sensor and @@ -388,7 +389,7 @@ /* * Intel/AMD Structured Extended Feature leaf Fn_0007 - * %eax == 0: Subleaf 0 + * %ecx == 0: Subleaf 0 * %eax: The Maximum input value for supported subleaf. * %ebx: Feature bits. * %ecx: Feature bits. @@ -460,6 +461,7 @@ #define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */ #define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */ #define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ +#define CPUID_SEF_PKS __BIT(31) /* Protection Keys */ #define CPUID_SEF_FLAGS1 "\177\20" \ "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ @@ -469,13 +471,14 @@ "f\21\5MAWAU\0" \ "b\26RDPID\0" \ "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ - "b\34MOVDIR64B\0" "b\36SGXLC\0" + "b\34MOVDIR64B\0" "b\36SGXLC\0" "b\37PKS\0" /* %edx */ #define CPUID_SEF_AVX512_4VNNIW __BIT(2) #define CPUID_SEF_AVX512_4FMAPS __BIT(3) #define CPUID_SEF_FSREP_MOV __BIT(4) /* Fast Short REP MOV */ #define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) +#define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */ #define CPUID_SEF_MD_CLEAR __BIT(10) #define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ #define CPUID_SEF_SERIALIZE __BIT(14) @@ -492,7 +495,7 @@ #define CPUID_SEF_FLAGS2 "\20" \ "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \ "\5" "FSREP_MOV" \ - "\11" "VP2INTERSECT" "\13" "MD_CLEAR" \ + "\11VP2INTERSECT" "\12SRBDS_CTRL" "\13MD_CLEAR" \
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Mon Jul 13 13:33:29 UTC 2020 Modified Files: src/sys/arch/x86/include [netbsd-9]: specialreg.h Log Message: Pull up following revision(s) (requested by msaitoh in ticket #998): sys/arch/x86/include/specialreg.h: revision 1.162 sys/arch/x86/include/specialreg.h: revision 1.164 sys/arch/x86/include/specialreg.h: revision 1.165 sys/arch/x86/include/specialreg.h: revision 1.166 sys/arch/x86/include/specialreg.h: revision 1.167 sys/arch/x86/include/specialreg.h: revision 1.168 - AMD CPUID Fn8000_000a %edx bit 20 is "SPEC_CTRL". - Add some bit definitions of AMD's CPUID Fn8000_001f Encrypted Memory features. - Add AMD INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC intercept bit. - Modify comment. Add AMD MSR_DE_CFG's bit 1 as DE_CFG_LFENCE_SERIALIZE. This bit makes lfence instruction serializing. Add some definitions from the latest Intel SDM plus small fix: - Add CPUID leaf 6 %eax bit 19 for HW_FEEDBACK* and IA32_PACKAGE_TERM* MSRs. - Add CPUID leaf 7 %ecx bit 31 for Protection Keys. - Add definition of Load only TLB and Store only TLB. - Add IF_PSCHANGE_MC_NO bit of IA32_ARCH_CAPABILITIES - Fix HWP_IGNIDL. Add SRBDS_CTRL bit. style and fix typo To generate a diff of this commit: cvs rdiff -u -r1.150.2.6 -r1.150.2.7 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src Committed By: martin Date: Sun Jul 12 11:40:58 UTC 2020 Modified Files: src/sys/arch/x86/pci [netbsd-9]: rdcpcib.c Log Message: Additionaly pull up the following revisions for ticket #998 to unbreak the build: sys/arch/x86/pci/rdcpcib.c 1.3 Recognize more RDC devices. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.2.58.1 src/sys/arch/x86/pci/rdcpcib.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src
Committed By: martin
Date: Sun Jul 12 11:40:58 UTC 2020
Modified Files:
src/sys/arch/x86/pci [netbsd-9]: rdcpcib.c
Log Message:
Additionaly pull up the following revisions for ticket #998 to unbreak
the build:
sys/arch/x86/pci/rdcpcib.c 1.3
Recognize more RDC devices.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.2.58.1 src/sys/arch/x86/pci/rdcpcib.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/pci/rdcpcib.c
diff -u src/sys/arch/x86/pci/rdcpcib.c:1.2 src/sys/arch/x86/pci/rdcpcib.c:1.2.58.1
--- src/sys/arch/x86/pci/rdcpcib.c:1.2 Fri Jul 1 18:22:08 2011
+++ src/sys/arch/x86/pci/rdcpcib.c Sun Jul 12 11:40:58 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: rdcpcib.c,v 1.2 2011/07/01 18:22:08 dyoung Exp $ */
+/* $NetBSD: rdcpcib.c,v 1.2.58.1 2020/07/12 11:40:58 martin Exp $ */
/*
* Copyright (c) 2011 Manuel Bouyer.
@@ -31,7 +31,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: rdcpcib.c,v 1.2 2011/07/01 18:22:08 dyoung Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rdcpcib.c,v 1.2.58.1 2020/07/12 11:40:58 martin Exp $");
#include
#include
@@ -88,6 +88,17 @@ CFATTACH_DECL2_NEW(rdcpcib, sizeof(struc
rdcpcibmatch, rdcpcibattach, rdcpcibdetach, NULL,
pcibrescan, pcibchilddet);
+
+static const struct rdcpcib_device {
+ pcireg_t vendor, product;
+} rdcpcib_devices[] = {
+ { PCI_VENDOR_RDC, PCI_PRODUCT_RDC_R6011_PCIB},
+ { PCI_VENDOR_RDC, PCI_PRODUCT_RDC_R6013_PCIB},
+ { PCI_VENDOR_RDC, PCI_PRODUCT_RDC_R6031_PCIB},
+ { PCI_VENDOR_RDC, PCI_PRODUCT_RDC_R6035_PCIB},
+ { PCI_VENDOR_RDC, PCI_PRODUCT_RDC_R6036_PCIB},
+};
+
static int
rdcpcibmatch(device_t parent, cfdata_t match, void *aux)
{
@@ -97,9 +108,11 @@ rdcpcibmatch(device_t parent, cfdata_t m
PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA)
return 0;
- if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RDC &&
- PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RDC_PCIB)
+ for (size_t i = 0; i < __arraycount(rdcpcib_devices); i++) {
+ if (PCI_VENDOR(pa->pa_id) == rdcpcib_devices[i].vendor &&
+ PCI_PRODUCT(pa->pa_id) == rdcpcib_devices[i].product)
return 10;
+ }
return 0;
}
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Fri Jul 10 10:36:56 UTC 2020
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: procfs_machdep.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #993):
sys/arch/x86/x86/procfs_machdep.c: revision 1.37
sys/arch/x86/x86/procfs_machdep.c: revision 1.38
Add AMD protected processor identification number (PPIN).
Lowercase ppin.
To generate a diff of this commit:
cvs rdiff -u -r1.33.2.2 -r1.33.2.3 src/sys/arch/x86/x86/procfs_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/procfs_machdep.c
diff -u src/sys/arch/x86/x86/procfs_machdep.c:1.33.2.2 src/sys/arch/x86/x86/procfs_machdep.c:1.33.2.3
--- src/sys/arch/x86/x86/procfs_machdep.c:1.33.2.2 Tue Apr 14 17:15:02 2020
+++ src/sys/arch/x86/x86/procfs_machdep.c Fri Jul 10 10:36:56 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: procfs_machdep.c,v 1.33.2.2 2020/04/14 17:15:02 martin Exp $ */
+/* $NetBSD: procfs_machdep.c,v 1.33.2.3 2020/07/10 10:36:56 martin Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -42,7 +42,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.33.2.2 2020/04/14 17:15:02 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.33.2.3 2020/07/10 10:36:56 martin Exp $");
#include
#include
@@ -155,7 +155,7 @@ static const char * const x86_features[]
{ /* (13) AMD 0x8008 ebx */
"clzero", "irperf", "xsaveerptr", NULL, "rdpru", NULL, NULL, NULL,
NULL, "wbnoinvd", NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, "ppin",
NULL, "virt_ssbd", NULL, NULL, NULL, NULL, NULL, NULL},
{ /* (14) 0x0006 eax */
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Fri Jul 10 10:36:56 UTC 2020 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: procfs_machdep.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #993): sys/arch/x86/x86/procfs_machdep.c: revision 1.37 sys/arch/x86/x86/procfs_machdep.c: revision 1.38 Add AMD protected processor identification number (PPIN). Lowercase ppin. To generate a diff of this commit: cvs rdiff -u -r1.33.2.2 -r1.33.2.3 src/sys/arch/x86/x86/procfs_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Sat Jun 20 16:03:36 UTC 2020 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: cpu_rng.c Log Message: Pull up following revision(s) (requested by riastradh in ticket #960): sys/arch/x86/x86/cpu_rng.c: revision 1.16 Use x86_read_psl/x86_disable_intr/x86_read_psl to defer interrupts. Using x86_disable_intr/x86_enable_intr causes a bit of a snag when we try it early at boot before we're ready to handle interrupts, because it has the effect of enabling interrupts! Fixes instant reset at boot on VIA CPUs. The instant reset on boot is new since the entropy rework, which initialized the x86 CPU RNG earlier than before, but in principle this could also cause other problems while not early at boot too. XXX pullup To generate a diff of this commit: cvs rdiff -u -r1.9.4.1 -r1.9.4.2 src/sys/arch/x86/x86/cpu_rng.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Sat Jun 20 16:03:36 UTC 2020
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: cpu_rng.c
Log Message:
Pull up following revision(s) (requested by riastradh in ticket #960):
sys/arch/x86/x86/cpu_rng.c: revision 1.16
Use x86_read_psl/x86_disable_intr/x86_read_psl to defer interrupts.
Using x86_disable_intr/x86_enable_intr causes a bit of a snag when we
try it early at boot before we're ready to handle interrupts, because
it has the effect of enabling interrupts!
Fixes instant reset at boot on VIA CPUs. The instant reset on boot
is new since the entropy rework, which initialized the x86 CPU RNG
earlier than before, but in principle this could also cause other
problems while not early at boot too.
XXX pullup
To generate a diff of this commit:
cvs rdiff -u -r1.9.4.1 -r1.9.4.2 src/sys/arch/x86/x86/cpu_rng.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/cpu_rng.c
diff -u src/sys/arch/x86/x86/cpu_rng.c:1.9.4.1 src/sys/arch/x86/x86/cpu_rng.c:1.9.4.2
--- src/sys/arch/x86/x86/cpu_rng.c:1.9.4.1 Fri Nov 1 18:17:55 2019
+++ src/sys/arch/x86/x86/cpu_rng.c Sat Jun 20 16:03:35 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_rng.c,v 1.9.4.1 2019/11/01 18:17:55 martin Exp $ */
+/* $NetBSD: cpu_rng.c,v 1.9.4.2 2020/06/20 16:03:35 martin Exp $ */
/*-
* Copyright (c) 2015 The NetBSD Foundation, Inc.
@@ -142,6 +142,7 @@ exhausted:
static size_t
cpu_rng_via(cpu_rng_t *out)
{
+ u_long psl;
uint32_t creg0, rndsts;
/*
@@ -155,9 +156,9 @@ cpu_rng_via(cpu_rng_t *out)
* even if such a fault is generated.
*
* XXX can this really happen if we don't use "rep xstorrng"?
- *
*/
kpreempt_disable();
+ psl = x86_read_psl();
x86_disable_intr();
creg0 = rcr0();
lcr0(creg0 & ~(CR0_EM|CR0_TS)); /* Permit access to SIMD/FPU path */
@@ -171,7 +172,7 @@ cpu_rng_via(cpu_rng_t *out)
: "=a" (rndsts), "+D" (out) : "d" (0) : "memory");
/* Put CR0 back how it was */
lcr0(creg0);
- x86_enable_intr();
+ x86_write_psl(psl);
kpreempt_enable();
/*
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Sun Jun 7 12:54:39 UTC 2020 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: pmap.c Log Message: Apply patch, requested by bouyer in ticket #941: sys/arch/x86/x86/pmap.c (apply patch) Fix Xen dom0 kernel build with options DIAGNOSTIC. To generate a diff of this commit: cvs rdiff -u -r1.334.2.2 -r1.334.2.3 src/sys/arch/x86/x86/pmap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/x86/pmap.c diff -u src/sys/arch/x86/x86/pmap.c:1.334.2.2 src/sys/arch/x86/x86/pmap.c:1.334.2.3 --- src/sys/arch/x86/x86/pmap.c:1.334.2.2 Sun May 31 10:39:35 2020 +++ src/sys/arch/x86/x86/pmap.c Sun Jun 7 12:54:39 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.c,v 1.334.2.2 2020/05/31 10:39:35 martin Exp $ */ +/* $NetBSD: pmap.c,v 1.334.2.3 2020/06/07 12:54:39 martin Exp $ */ /* * Copyright (c) 2008, 2010, 2016, 2017 The NetBSD Foundation, Inc. @@ -130,7 +130,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.334.2.2 2020/05/31 10:39:35 martin Exp $"); +__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.334.2.3 2020/06/07 12:54:39 martin Exp $"); #include "opt_user_ldt.h" #include "opt_lockdebug.h" @@ -4461,7 +4461,7 @@ pmap_free_gnt(struct pmap *pmap, struct struct pmap_data_gnt_head *headp = pmap->pm_data; int nentries = (pgnt->pd_gnt_eva - pgnt->pd_gnt_sva) / PAGE_SIZE; KASSERT(nentries >= 1); - KASSERT(mutex_owned(>pm_lock)); + KASSERT(mutex_owned(pmap->pm_lock)); KASSERT(pgnt->pd_gnt_refs == 0); SLIST_REMOVE(headp, pgnt, pmap_data_gnt, pd_gnt_list); kmem_free(pgnt, sizeof(*pgnt) +
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Sun Jun 7 12:54:39 UTC 2020 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: pmap.c Log Message: Apply patch, requested by bouyer in ticket #941: sys/arch/x86/x86/pmap.c (apply patch) Fix Xen dom0 kernel build with options DIAGNOSTIC. To generate a diff of this commit: cvs rdiff -u -r1.334.2.2 -r1.334.2.3 src/sys/arch/x86/x86/pmap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Mon May 25 15:39:54 UTC 2020 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: cpu_topology.c Log Message: Pull up following revision(s) (requested by mlelstv in ticket #922): sys/arch/x86/x86/cpu_topology.c: revision 1.18 assert smt_bits value only after it is computed. To generate a diff of this commit: cvs rdiff -u -r1.14 -r1.14.4.1 src/sys/arch/x86/x86/cpu_topology.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Mon May 25 15:39:54 UTC 2020 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: cpu_topology.c Log Message: Pull up following revision(s) (requested by mlelstv in ticket #922): sys/arch/x86/x86/cpu_topology.c: revision 1.18 assert smt_bits value only after it is computed. To generate a diff of this commit: cvs rdiff -u -r1.14 -r1.14.4.1 src/sys/arch/x86/x86/cpu_topology.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/x86/cpu_topology.c diff -u src/sys/arch/x86/x86/cpu_topology.c:1.14 src/sys/arch/x86/x86/cpu_topology.c:1.14.4.1 --- src/sys/arch/x86/x86/cpu_topology.c:1.14 Wed Nov 21 10:34:53 2018 +++ src/sys/arch/x86/x86/cpu_topology.c Mon May 25 15:39:54 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu_topology.c,v 1.14 2018/11/21 10:34:53 msaitoh Exp $ */ +/* $NetBSD: cpu_topology.c,v 1.14.4.1 2020/05/25 15:39:54 martin Exp $ */ /*- * Copyright (c) 2009 Mindaugas Rasiukevicius , @@ -36,7 +36,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: cpu_topology.c,v 1.14 2018/11/21 10:34:53 msaitoh Exp $"); +__KERNEL_RCSID(0, "$NetBSD: cpu_topology.c,v 1.14.4.1 2020/05/25 15:39:54 martin Exp $"); #include #include @@ -157,8 +157,9 @@ x86_cpu_topology(struct cpu_info *ci) x86_cpuid(0x801e, descs); const u_int threads = ((descs[1] >> 8) & 0xff) + 1; - KASSERT(smt_bits == 0 && smt_bits <= core_bits); + KASSERT(smt_bits == 0); smt_bits = ilog2(threads); + KASSERT(smt_bits <= core_bits); core_bits -= smt_bits; }
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src Committed By: martin Date: Wed May 13 12:37:31 UTC 2020 Modified Files: src/sys/arch/x86/pci [netbsd-9]: if_vmx.c Log Message: Pull up following revision(s) (requested by yamaguchi in ticket #902): sys/arch/x86/pci/if_vmx.c: revision 1.60 Fix the wrong logic about making the number of vmx(4) TX/RX queue be power of two reviewed by nonaka@n.o. To generate a diff of this commit: cvs rdiff -u -r1.45.2.6 -r1.45.2.7 src/sys/arch/x86/pci/if_vmx.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src
Committed By: martin
Date: Wed May 13 12:37:31 UTC 2020
Modified Files:
src/sys/arch/x86/pci [netbsd-9]: if_vmx.c
Log Message:
Pull up following revision(s) (requested by yamaguchi in ticket #902):
sys/arch/x86/pci/if_vmx.c: revision 1.60
Fix the wrong logic about making the number of vmx(4) TX/RX queue
be power of two
reviewed by nonaka@n.o.
To generate a diff of this commit:
cvs rdiff -u -r1.45.2.6 -r1.45.2.7 src/sys/arch/x86/pci/if_vmx.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/pci/if_vmx.c
diff -u src/sys/arch/x86/pci/if_vmx.c:1.45.2.6 src/sys/arch/x86/pci/if_vmx.c:1.45.2.7
--- src/sys/arch/x86/pci/if_vmx.c:1.45.2.6 Tue Jan 28 11:01:37 2020
+++ src/sys/arch/x86/pci/if_vmx.c Wed May 13 12:37:31 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: if_vmx.c,v 1.45.2.6 2020/01/28 11:01:37 martin Exp $ */
+/* $NetBSD: if_vmx.c,v 1.45.2.7 2020/05/13 12:37:31 martin Exp $ */
/* $OpenBSD: if_vmx.c,v 1.16 2014/01/22 06:04:17 brad Exp $ */
/*
@@ -19,12 +19,13 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: if_vmx.c,v 1.45.2.6 2020/01/28 11:01:37 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_vmx.c,v 1.45.2.7 2020/05/13 12:37:31 martin Exp $");
#include
#include
#include
#include
+#include
#include
#include
#include
@@ -460,23 +461,11 @@ CFATTACH_DECL3_NEW(vmx, sizeof(struct vm
static int
vmxnet3_calc_queue_size(int n)
{
- int v, q;
- v = n;
- while (v != 0) {
- if (powerof2(n) != 0)
- break;
- v /= 2;
- q = rounddown2(n, v);
- if (q != 0) {
- n = q;
- break;
- }
- }
- if (n == 0)
- n = 1;
+ if (__predict_false(n <= 0))
+ return 1;
- return n;
+ return (1U << (fls32(n) - 1));
}
static inline void
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Tue Jan 21 11:36:37 UTC 2020 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: cpu.c Log Message: Pull up following revision(s) (requested by pgoyette in ticket #623): sys/arch/x86/x86/cpu.c: revision 1.181 If "application processors" were skipped/disabled at boot time (due to RB_MD1 being set), don't try to examine the featurebus info, since it was never retrieved. Addresses kern/54815 XXX pullup-9 To generate a diff of this commit: cvs rdiff -u -r1.171 -r1.171.2.1 src/sys/arch/x86/x86/cpu.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Tue Jan 21 11:36:37 UTC 2020 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: cpu.c Log Message: Pull up following revision(s) (requested by pgoyette in ticket #623): sys/arch/x86/x86/cpu.c: revision 1.181 If "application processors" were skipped/disabled at boot time (due to RB_MD1 being set), don't try to examine the featurebus info, since it was never retrieved. Addresses kern/54815 XXX pullup-9 To generate a diff of this commit: cvs rdiff -u -r1.171 -r1.171.2.1 src/sys/arch/x86/x86/cpu.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/x86/cpu.c diff -u src/sys/arch/x86/x86/cpu.c:1.171 src/sys/arch/x86/x86/cpu.c:1.171.2.1 --- src/sys/arch/x86/x86/cpu.c:1.171 Wed May 29 16:54:41 2019 +++ src/sys/arch/x86/x86/cpu.c Tue Jan 21 11:36:36 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu.c,v 1.171 2019/05/29 16:54:41 maxv Exp $ */ +/* $NetBSD: cpu.c,v 1.171.2.1 2020/01/21 11:36:36 martin Exp $ */ /* * Copyright (c) 2000-2012 NetBSD Foundation, Inc. @@ -62,7 +62,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.171 2019/05/29 16:54:41 maxv Exp $"); +__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.171.2.1 2020/01/21 11:36:36 martin Exp $"); #include "opt_ddb.h" #include "opt_mpbios.h" /* for MPDEBUG */ @@ -521,6 +521,16 @@ cpu_rescan(device_t self, const char *if struct cpufeature_attach_args cfaa; struct cpu_info *ci = sc->sc_info; + /* + * If we booted with RB_MD1 to disable multiprocessor, the + * auto-configuration data still contains the additional + * CPUs. But their initialization was mostly bypassed + * during attach, so we have to make sure we don't look at + * their featurebus info, since it wasn't retrieved. + */ + if (ci == NULL) + return 0; + memset(, 0, sizeof(cfaa)); cfaa.ci = ci;
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Sun Dec 29 09:33:43 UTC 2019 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: x86_machdep.c Log Message: Pull up following revision(s) (requested by pgoyette in ticket #587): sys/arch/x86/x86/x86_machdep.c: revision 1.134 to know this in order to set module_machine correctly, which in turn is needed to set the module_base path from which modules are loaded and which provides the value of sysctl(8) variable kern.module.path Thanks to jnemeth@ for pointing out the problem. To generate a diff of this commit: cvs rdiff -u -r1.127 -r1.127.2.1 src/sys/arch/x86/x86/x86_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Sun Dec 29 09:33:43 UTC 2019 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: x86_machdep.c Log Message: Pull up following revision(s) (requested by pgoyette in ticket #587): sys/arch/x86/x86/x86_machdep.c: revision 1.134 to know this in order to set module_machine correctly, which in turn is needed to set the module_base path from which modules are loaded and which provides the value of sysctl(8) variable kern.module.path Thanks to jnemeth@ for pointing out the problem. To generate a diff of this commit: cvs rdiff -u -r1.127 -r1.127.2.1 src/sys/arch/x86/x86/x86_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/x86/x86_machdep.c diff -u src/sys/arch/x86/x86/x86_machdep.c:1.127 src/sys/arch/x86/x86/x86_machdep.c:1.127.2.1 --- src/sys/arch/x86/x86/x86_machdep.c:1.127 Wed May 29 16:54:41 2019 +++ src/sys/arch/x86/x86/x86_machdep.c Sun Dec 29 09:33:43 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: x86_machdep.c,v 1.127 2019/05/29 16:54:41 maxv Exp $ */ +/* $NetBSD: x86_machdep.c,v 1.127.2.1 2019/12/29 09:33:43 martin Exp $ */ /*- * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi, @@ -31,13 +31,14 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: x86_machdep.c,v 1.127 2019/05/29 16:54:41 maxv Exp $"); +__KERNEL_RCSID(0, "$NetBSD: x86_machdep.c,v 1.127.2.1 2019/12/29 09:33:43 martin Exp $"); #include "opt_modular.h" #include "opt_physmem.h" #include "opt_splash.h" #include "opt_kaslr.h" #include "opt_svs.h" +#include "opt_xen.h" #include #include
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src Committed By: martin Date: Thu Dec 26 20:19:37 UTC 2019 Modified Files: src/sys/arch/x86/pci [netbsd-9]: if_vmx.c Log Message: Pull up following revision(s) (requested by knakahara in ticket #583): sys/arch/x86/pci/if_vmx.c: revision 1.53 Fix missing splnet() for ether_ioctl() caused by if_vmx.c:r1.32. pointed out by nonaka@n.o, thanks. To generate a diff of this commit: cvs rdiff -u -r1.45.2.4 -r1.45.2.5 src/sys/arch/x86/pci/if_vmx.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src
Committed By: martin
Date: Thu Dec 26 20:19:37 UTC 2019
Modified Files:
src/sys/arch/x86/pci [netbsd-9]: if_vmx.c
Log Message:
Pull up following revision(s) (requested by knakahara in ticket #583):
sys/arch/x86/pci/if_vmx.c: revision 1.53
Fix missing splnet() for ether_ioctl() caused by if_vmx.c:r1.32.
pointed out by nonaka@n.o, thanks.
To generate a diff of this commit:
cvs rdiff -u -r1.45.2.4 -r1.45.2.5 src/sys/arch/x86/pci/if_vmx.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/pci/if_vmx.c
diff -u src/sys/arch/x86/pci/if_vmx.c:1.45.2.4 src/sys/arch/x86/pci/if_vmx.c:1.45.2.5
--- src/sys/arch/x86/pci/if_vmx.c:1.45.2.4 Thu Oct 10 17:32:15 2019
+++ src/sys/arch/x86/pci/if_vmx.c Thu Dec 26 20:19:37 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: if_vmx.c,v 1.45.2.4 2019/10/10 17:32:15 martin Exp $ */
+/* $NetBSD: if_vmx.c,v 1.45.2.5 2019/12/26 20:19:37 martin Exp $ */
/* $OpenBSD: if_vmx.c,v 1.16 2014/01/22 06:04:17 brad Exp $ */
/*
@@ -19,7 +19,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: if_vmx.c,v 1.45.2.4 2019/10/10 17:32:15 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_vmx.c,v 1.45.2.5 2019/12/26 20:19:37 martin Exp $");
#include
#include
@@ -3385,7 +3385,9 @@ vmxnet3_ioctl(struct ifnet *ifp, u_long
break;
}
if (ifp->if_mtu != nmtu) {
+ s = splnet();
error = ether_ioctl(ifp, cmd, data);
+ splx(s);
if (error == ENETRESET)
error = vmxnet3_init(ifp);
}
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Tue Dec 17 12:56:45 UTC 2019 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: bus_space.c Log Message: Pull up following revision(s) (requested by riastradh in ticket #566): sys/arch/x86/x86/bus_space.c: revision 1.42 sys/arch/x86/x86/bus_space.c: revision 1.43 Use LFENCE/SFENCE/MFENCE in x86 bus_space_barrier. These are needed for BUS_SPACE_MAP_PREFETCHABLE mappings. On x86, these are WC-type memory regions, which means -- unlike normal WB-type memory regions -- loads can be reordered with loads, requiring LFENCE, and stores can be reordered with stores, requiring SFENCE. Reference: AMD64 Architecture Programmer's Manual, Volume 2: System Programming, Sec. 7.4.1 `Memory Barrier Interaction with Memory Types', Table 7-3 `Memory Access Ordering Rules'. Skip fences in bus_space_barrier on I/O space. I/O operations are issued in program order. Not that I/O operations are usually a performance bottleneck anyway, but maybe it is slightly cheaper to avoid stalling on store buffers or pending loads, and there's very little cost to the skipping criterion here. To generate a diff of this commit: cvs rdiff -u -r1.41 -r1.41.4.1 src/sys/arch/x86/x86/bus_space.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Tue Dec 17 12:56:45 UTC 2019
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: bus_space.c
Log Message:
Pull up following revision(s) (requested by riastradh in ticket #566):
sys/arch/x86/x86/bus_space.c: revision 1.42
sys/arch/x86/x86/bus_space.c: revision 1.43
Use LFENCE/SFENCE/MFENCE in x86 bus_space_barrier.
These are needed for BUS_SPACE_MAP_PREFETCHABLE mappings. On x86,
these are WC-type memory regions, which means -- unlike normal
WB-type memory regions -- loads can be reordered with loads,
requiring LFENCE, and stores can be reordered with stores, requiring
SFENCE.
Reference: AMD64 Architecture Programmer's Manual, Volume 2: System
Programming, Sec. 7.4.1 `Memory Barrier Interaction with Memory
Types', Table 7-3 `Memory Access Ordering Rules'.
Skip fences in bus_space_barrier on I/O space.
I/O operations are issued in program order. Not that I/O operations
are usually a performance bottleneck anyway, but maybe it is slightly
cheaper to avoid stalling on store buffers or pending loads, and
there's very little cost to the skipping criterion here.
To generate a diff of this commit:
cvs rdiff -u -r1.41 -r1.41.4.1 src/sys/arch/x86/x86/bus_space.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/bus_space.c
diff -u src/sys/arch/x86/x86/bus_space.c:1.41 src/sys/arch/x86/x86/bus_space.c:1.41.4.1
--- src/sys/arch/x86/x86/bus_space.c:1.41 Mon Feb 11 14:59:33 2019
+++ src/sys/arch/x86/x86/bus_space.c Tue Dec 17 12:56:45 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space.c,v 1.41 2019/02/11 14:59:33 cherry Exp $ */
+/* $NetBSD: bus_space.c,v 1.41.4.1 2019/12/17 12:56:45 martin Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: bus_space.c,v 1.41 2019/02/11 14:59:33 cherry Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus_space.c,v 1.41.4.1 2019/12/17 12:56:45 martin Exp $");
#include
#include
@@ -878,7 +878,43 @@ bus_space_barrier(bus_space_tag_t tag, b
bus_size_t offset, bus_size_t len, int flags)
{
- /* Function call is enough to prevent reordering of loads. */
+ /* I/O instructions always happen in program order. */
+ if (x86_bus_space_is_io(tag))
+ return;
+
+ /*
+ * For default mappings, which are mapped with UC-type memory
+ * regions, all loads and stores are issued in program order.
+ *
+ * For BUS_SPACE_MAP_PREFETCHABLE mappings, which are mapped
+ * with WC-type memory regions, loads and stores may be issued
+ * out of order, potentially requiring any of the three x86
+ * fences -- LFENCE, SFENCE, MFENCE.
+ *
+ * For BUS_SPACE_MAP_CACHEABLE mappings, which are mapped with
+ * WB-type memory regions (like normal memory), store/load may
+ * be reordered to load/store, potentially requiring MFENCE.
+ *
+ * We can't easily tell here how the region was mapped (without
+ * consulting the page tables), so just issue the fence
+ * unconditionally. Chances are either it's necessary or the
+ * cost is small in comparison to device register I/O.
+ */
+ switch (flags) {
+ case 0:
+ break;
+ case BUS_SPACE_BARRIER_READ:
+ x86_lfence();
+ break;
+ case BUS_SPACE_BARRIER_WRITE:
+ x86_sfence();
+ break;
+ case BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE:
+ x86_mfence();
+ break;
+ default:
+ panic("unknown bus space barrier: 0x%x", (unsigned)flags);
+ }
}
void *
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Sat Dec 14 12:24:23 UTC 2019
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: spectre.c
Log Message:
Pull up following revision(s) (requested by maxv in ticket #550):
sys/arch/x86/x86/spectre.c: revision 1.32
Check CPUID.IBRS in addition to ARCH_CAP.IBRS_ALL. For clarity, and also
because VirtualBox clears the former but forgets to clear the latter (which
makes us hit a #GP on RDMSR).
To generate a diff of this commit:
cvs rdiff -u -r1.29.2.2 -r1.29.2.3 src/sys/arch/x86/x86/spectre.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/spectre.c
diff -u src/sys/arch/x86/x86/spectre.c:1.29.2.2 src/sys/arch/x86/x86/spectre.c:1.29.2.3
--- src/sys/arch/x86/x86/spectre.c:1.29.2.2 Tue Nov 12 18:24:37 2019
+++ src/sys/arch/x86/x86/spectre.c Sat Dec 14 12:24:23 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: spectre.c,v 1.29.2.2 2019/11/12 18:24:37 martin Exp $ */
+/* $NetBSD: spectre.c,v 1.29.2.3 2019/12/14 12:24:23 martin Exp $ */
/*
* Copyright (c) 2018-2019 NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: spectre.c,v 1.29.2.2 2019/11/12 18:24:37 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: spectre.c,v 1.29.2.3 2019/12/14 12:24:23 martin Exp $");
#include "opt_spectre.h"
@@ -126,20 +126,20 @@ v2_detect_method(void)
if (cpuid_level >= 7) {
x86_cpuid(7, descs);
- if (descs[3] & CPUID_SEF_ARCH_CAP) {
-msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
-if (msr & IA32_ARCH_IBRS_ALL) {
- v2_mitigation_method =
- V2_MITIGATION_INTEL_ENHANCED_IBRS;
- return;
+ if (descs[3] & CPUID_SEF_IBRS) {
+if (descs[3] & CPUID_SEF_ARCH_CAP) {
+ msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
+ if (msr & IA32_ARCH_IBRS_ALL) {
+ v2_mitigation_method =
+ V2_MITIGATION_INTEL_ENHANCED_IBRS;
+ return;
+ }
}
- }
#ifdef __x86_64__
- if (descs[3] & CPUID_SEF_IBRS) {
v2_mitigation_method = V2_MITIGATION_INTEL_IBRS;
return;
- }
#endif
+ }
}
v2_mitigation_method = V2_MITIGATION_NONE;
} else if (cpu_vendor == CPUVENDOR_AMD) {
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Sat Dec 14 12:24:23 UTC 2019 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: spectre.c Log Message: Pull up following revision(s) (requested by maxv in ticket #550): sys/arch/x86/x86/spectre.c: revision 1.32 Check CPUID.IBRS in addition to ARCH_CAP.IBRS_ALL. For clarity, and also because VirtualBox clears the former but forgets to clear the latter (which makes us hit a #GP on RDMSR). To generate a diff of this commit: cvs rdiff -u -r1.29.2.2 -r1.29.2.3 src/sys/arch/x86/x86/spectre.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86
Module Name:src Committed By: martin Date: Sun Dec 8 13:09:28 UTC 2019 Modified Files: src/sys/arch/x86/include [netbsd-9]: genfb_machdep.h src/sys/arch/x86/x86 [netbsd-9]: genfb_machdep.c hyperv.c Log Message: Pull up following revision(s) (requested by nonaka in ticket #502): sys/arch/x86/x86/hyperv.c: revision 1.5 sys/arch/x86/include/genfb_machdep.h: revision 1.4 sys/arch/x86/x86/genfb_machdep.c: revision 1.15 Prevent panic when attaching genfb if using a serial console with Hyper-V Gen.2. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.3.60.1 src/sys/arch/x86/include/genfb_machdep.h cvs rdiff -u -r1.13 -r1.13.2.1 src/sys/arch/x86/x86/genfb_machdep.c cvs rdiff -u -r1.4 -r1.4.4.1 src/sys/arch/x86/x86/hyperv.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86
Module Name:src
Committed By: martin
Date: Sun Dec 8 13:09:28 UTC 2019
Modified Files:
src/sys/arch/x86/include [netbsd-9]: genfb_machdep.h
src/sys/arch/x86/x86 [netbsd-9]: genfb_machdep.c hyperv.c
Log Message:
Pull up following revision(s) (requested by nonaka in ticket #502):
sys/arch/x86/x86/hyperv.c: revision 1.5
sys/arch/x86/include/genfb_machdep.h: revision 1.4
sys/arch/x86/x86/genfb_machdep.c: revision 1.15
Prevent panic when attaching genfb if using a serial console with Hyper-V Gen.2.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.3.60.1 src/sys/arch/x86/include/genfb_machdep.h
cvs rdiff -u -r1.13 -r1.13.2.1 src/sys/arch/x86/x86/genfb_machdep.c
cvs rdiff -u -r1.4 -r1.4.4.1 src/sys/arch/x86/x86/hyperv.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/genfb_machdep.h
diff -u src/sys/arch/x86/include/genfb_machdep.h:1.3 src/sys/arch/x86/include/genfb_machdep.h:1.3.60.1
--- src/sys/arch/x86/include/genfb_machdep.h:1.3 Wed Feb 9 13:24:23 2011
+++ src/sys/arch/x86/include/genfb_machdep.h Sun Dec 8 13:09:28 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: genfb_machdep.h,v 1.3 2011/02/09 13:24:23 jmcneill Exp $ */
+/* $NetBSD: genfb_machdep.h,v 1.3.60.1 2019/12/08 13:09:28 martin Exp $ */
/*-
* Copyright (c) 2009 Jared D. McNeill
@@ -29,6 +29,7 @@
#ifndef _X86_GENFB_MACHDEP_H
#define _X86_GENFB_MACHDEP_H
+int x86_genfb_init(void);
int x86_genfb_cnattach(void);
void x86_genfb_mtrr_init(uint64_t, uint32_t);
void x86_genfb_set_console_dev(device_t);
Index: src/sys/arch/x86/x86/genfb_machdep.c
diff -u src/sys/arch/x86/x86/genfb_machdep.c:1.13 src/sys/arch/x86/x86/genfb_machdep.c:1.13.2.1
--- src/sys/arch/x86/x86/genfb_machdep.c:1.13 Sun May 19 07:43:17 2019
+++ src/sys/arch/x86/x86/genfb_machdep.c Sun Dec 8 13:09:28 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: genfb_machdep.c,v 1.13 2019/05/19 07:43:17 mlelstv Exp $ */
+/* $NetBSD: genfb_machdep.c,v 1.13.2.1 2019/12/08 13:09:28 martin Exp $ */
/*-
* Copyright (c) 2009 Jared D. McNeill
@@ -31,7 +31,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: genfb_machdep.c,v 1.13 2019/05/19 07:43:17 mlelstv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: genfb_machdep.c,v 1.13.2.1 2019/12/08 13:09:28 martin Exp $");
#include "opt_mtrr.h"
@@ -136,23 +136,19 @@ x86_genfb_mtrr_init(uint64_t physaddr, u
}
int
-x86_genfb_cnattach(void)
+x86_genfb_init(void)
{
- static int ncalls = 0;
+ static int inited, attached;
struct rasops_info *ri = _genfb_console_screen.scr_ri;
const struct btinfo_framebuffer *fbinfo;
bus_space_tag_t t = x86_bus_space_mem;
bus_space_handle_t h;
void *bits;
- long defattr;
int err;
- /* XXX jmcneill
- * Defer console initialization until UVM is initialized
- */
- ++ncalls;
- if (ncalls < 3)
- return -1;
+ if (inited)
+ return attached;
+ inited = 1;
memset(_genfb_console_screen, 0, sizeof(x86_genfb_console_screen));
@@ -206,6 +202,27 @@ x86_genfb_cnattach(void)
x86_genfb_stdscreen.textops = >ri_ops;
x86_genfb_stdscreen.capabilities = ri->ri_caps;
+ attached = 1;
+ return 1;
+}
+
+int
+x86_genfb_cnattach(void)
+{
+ static int ncalls = 0;
+ struct rasops_info *ri = _genfb_console_screen.scr_ri;
+ long defattr;
+
+ /* XXX jmcneill
+ * Defer console initialization until UVM is initialized
+ */
+ ++ncalls;
+ if (ncalls < 3)
+ return -1;
+
+ if (!x86_genfb_init())
+ return 0;
+
ri->ri_ops.allocattr(ri, 0, 0, 0, );
wsdisplay_preattach(_genfb_stdscreen, ri, 0, 0, defattr);
@@ -213,6 +230,12 @@ x86_genfb_cnattach(void)
}
#else /* NWSDISPLAY > 0 && NGENFB > 0 */
int
+x86_genfb_init(void)
+{
+ return 0;
+}
+
+int
x86_genfb_cnattach(void)
{
return 0;
Index: src/sys/arch/x86/x86/hyperv.c
diff -u src/sys/arch/x86/x86/hyperv.c:1.4 src/sys/arch/x86/x86/hyperv.c:1.4.4.1
--- src/sys/arch/x86/x86/hyperv.c:1.4 Mon Jun 3 09:51:04 2019
+++ src/sys/arch/x86/x86/hyperv.c Sun Dec 8 13:09:28 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: hyperv.c,v 1.4 2019/06/03 09:51:04 nonaka Exp $ */
+/* $NetBSD: hyperv.c,v 1.4.4.1 2019/12/08 13:09:28 martin Exp $ */
/*-
* Copyright (c) 2009-2012,2016-2017 Microsoft Corp.
@@ -33,7 +33,7 @@
*/
#include
#ifdef __KERNEL_RCSID
-__KERNEL_RCSID(0, "$NetBSD: hyperv.c,v 1.4 2019/06/03 09:51:04 nonaka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: hyperv.c,v 1.4.4.1 2019/12/08 13:09:28 martin Exp $");
#endif
#ifdef __FBSDID
__FBSDID("$FreeBSD: head/sys/dev/hyperv/vmbus/hyperv.c 331757 2018-03-30 02:25:12Z emaste $");
@@ -70,7 +70,7 @@ __FBSDID("$FreeBSD: head/sys/dev/hyperv/
#include
#include
-#include
+#include
#include
#include
@@ -1103,6 +1103,9 @@ device_hyperv_register(device_t dev, voi
sizeof(*aa->aa_type)) == 0) {
prop_dictionary_t dict = device_properties(dev);
+ /* Initialize genfb for serial console */
+ x86_genfb_init();
+
/*
* framebuffer drivers other than genfb can work
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src Committed By: martin Date: Sat Nov 16 16:53:13 UTC 2019 Modified Files: src/sys/arch/x86/pci [netbsd-9]: msipic.c Log Message: Pull up following revision(s) (requested by hikaru in ticket #429): sys/arch/x86/pci/msipic.c: revision 1.19 Disable MSI-X before writing the MSI-X table. That fixes MSI-X interrupt lost on VMware ESXi 6.7 PCI passthrough devices. ok knakahara@ To generate a diff of this commit: cvs rdiff -u -r1.17.2.1 -r1.17.2.2 src/sys/arch/x86/pci/msipic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/pci/msipic.c diff -u src/sys/arch/x86/pci/msipic.c:1.17.2.1 src/sys/arch/x86/pci/msipic.c:1.17.2.2 --- src/sys/arch/x86/pci/msipic.c:1.17.2.1 Tue Oct 15 18:08:31 2019 +++ src/sys/arch/x86/pci/msipic.c Sat Nov 16 16:53:13 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: msipic.c,v 1.17.2.1 2019/10/15 18:08:31 martin Exp $ */ +/* $NetBSD: msipic.c,v 1.17.2.2 2019/11/16 16:53:13 martin Exp $ */ /* * Copyright (c) 2015 Internet Initiative Japan Inc. @@ -27,7 +27,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: msipic.c,v 1.17.2.1 2019/10/15 18:08:31 martin Exp $"); +__KERNEL_RCSID(0, "$NetBSD: msipic.c,v 1.17.2.2 2019/11/16 16:53:13 martin Exp $"); #include "opt_intrdebug.h" @@ -548,6 +548,11 @@ msix_addroute(struct pic *pic, struct cp err = pci_get_capability(pc, tag, PCI_CAP_MSIX, , NULL); KASSERT(err != 0); + /* Disable MSI-X before writing MSI-X table */ + ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); + ctl &= ~PCI_MSIX_CTL_ENABLE; + pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl); + entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec; /*
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src Committed By: martin Date: Sat Nov 16 16:53:13 UTC 2019 Modified Files: src/sys/arch/x86/pci [netbsd-9]: msipic.c Log Message: Pull up following revision(s) (requested by hikaru in ticket #429): sys/arch/x86/pci/msipic.c: revision 1.19 Disable MSI-X before writing the MSI-X table. That fixes MSI-X interrupt lost on VMware ESXi 6.7 PCI passthrough devices. ok knakahara@ To generate a diff of this commit: cvs rdiff -u -r1.17.2.1 -r1.17.2.2 src/sys/arch/x86/pci/msipic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86
Module Name:src
Committed By: martin
Date: Tue Nov 12 18:24:37 UTC 2019
Modified Files:
src/sys/arch/x86/include [netbsd-9]: specialreg.h
src/sys/arch/x86/x86 [netbsd-9]: spectre.c
Log Message:
Pull up following revision(s) (requested by maxv in ticket #419):
sys/arch/x86/include/specialreg.h: revision 1.157
sys/arch/x86/x86/spectre.c: revision 1.31
Mitigation for CVE-2019-11135: TSX Asynchronous Abort (TAA).
Two sysctls are added:
machdep.taa.mitigated = {0/1} user-settable
machdep.taa.method = {string} constructed by the kernel
There are two cases:
(1) If the CPU is affected by MDS, then the MDS mitigation will also
mitigate TAA, and we have nothing else to do. We make the 'mitigated' leaf
read-only, and force:
machdep.taa.mitigated = machdep.mds.mitigated
machdep.taa.method = [MDS]
The kernel already enables the MDS mitigation by default.
(2) If the CPU is not affected by MDS but is affected by TAA, then we use
the new TSX_CTRL MSR to disable RTM. This MSR is provided via a microcode
update, now available on the Intel website. The kernel will automatically
enable the TAA mitigation if the updated microcode is present. If the new
microcode is not present, the user can load it via cpuctl, and set
machdep.taa.mitigated=1.
To generate a diff of this commit:
cvs rdiff -u -r1.150.2.3 -r1.150.2.4 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.29.2.1 -r1.29.2.2 src/sys/arch/x86/x86/spectre.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.150.2.3 src/sys/arch/x86/include/specialreg.h:1.150.2.4
--- src/sys/arch/x86/include/specialreg.h:1.150.2.3 Sun Nov 10 13:06:46 2019
+++ src/sys/arch/x86/include/specialreg.h Tue Nov 12 18:24:37 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.150.2.3 2019/11/10 13:06:46 martin Exp $ */
+/* $NetBSD: specialreg.h,v 1.150.2.4 2019/11/12 18:24:37 martin Exp $ */
/*
* Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
@@ -853,9 +853,14 @@
#define IA32_ARCH_SKIP_L1DFL_VMENTRY 0x08
#define IA32_ARCH_SSB_NO 0x10
#define IA32_ARCH_MDS_NO 0x20
+#define IA32_ARCH_TSX_CTRL 0x80
+#define IA32_ARCH_TAA_NO 0x100
#define MSR_IA32_FLUSH_CMD 0x10b
#define IA32_FLUSH_CMD_L1D_FLUSH 0x01
#define MSR_TSX_FORCE_ABORT 0x10f
+#define MSR_IA32_TSX_CTRL 0x122
+#define IA32_TSX_CTRL_RTM_DISABLE __BIT(0)
+#define IA32_TSX_CTRL_TSX_CPUID_CLEAR __BIT(1)
#define MSR_SYSENTER_CS 0x174 /* PII+ only */
#define MSR_SYSENTER_ESP 0x175 /* PII+ only */
#define MSR_SYSENTER_EIP 0x176 /* PII+ only */
Index: src/sys/arch/x86/x86/spectre.c
diff -u src/sys/arch/x86/x86/spectre.c:1.29.2.1 src/sys/arch/x86/x86/spectre.c:1.29.2.2
--- src/sys/arch/x86/x86/spectre.c:1.29.2.1 Thu Sep 26 18:47:14 2019
+++ src/sys/arch/x86/x86/spectre.c Tue Nov 12 18:24:37 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: spectre.c,v 1.29.2.1 2019/09/26 18:47:14 martin Exp $ */
+/* $NetBSD: spectre.c,v 1.29.2.2 2019/11/12 18:24:37 martin Exp $ */
/*
* Copyright (c) 2018-2019 NetBSD Foundation, Inc.
@@ -30,11 +30,11 @@
*/
/*
- * Mitigations for the SpectreV2, SpectreV4 and MDS CPU flaws.
+ * Mitigations for the SpectreV2, SpectreV4, MDS and TAA CPU flaws.
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: spectre.c,v 1.29.2.1 2019/09/26 18:47:14 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: spectre.c,v 1.29.2.2 2019/11/12 18:24:37 martin Exp $");
#include "opt_spectre.h"
@@ -773,6 +773,185 @@ sysctl_machdep_mds_mitigated(SYSCTLFN_AR
/* -- */
+enum taa_mitigation {
+ TAA_MITIGATION_NONE,
+ TAA_MITIGATION_TAA_NO,
+ TAA_MITIGATION_MDS,
+ TAA_MITIGATION_RTM_DISABLE
+};
+
+static char taa_mitigation_name[64] = "(none)";
+
+static enum taa_mitigation taa_mitigation_method = TAA_MITIGATION_NONE;
+static bool taa_mitigation_enabled __read_mostly = false;
+static bool *taa_mitigation_enabled_ptr = _mitigation_enabled;
+
+static void
+mitigation_taa_apply_cpu(struct cpu_info *ci, bool enabled)
+{
+ uint64_t msr;
+
+ switch (taa_mitigation_method) {
+ case TAA_MITIGATION_NONE:
+ case TAA_MITIGATION_TAA_NO:
+ case TAA_MITIGATION_MDS:
+ panic("impossible");
+ case TAA_MITIGATION_RTM_DISABLE:
+ msr = rdmsr(MSR_IA32_TSX_CTRL);
+ if (enabled) {
+ msr |= IA32_TSX_CTRL_RTM_DISABLE;
+ } else {
+ msr &= ~IA32_TSX_CTRL_RTM_DISABLE;
+ }
+ wrmsr(MSR_IA32_TSX_CTRL, msr);
+ break;
+ }
+}
+
+static void
+mitigation_taa_change_cpu(void *arg1, void *arg2)
+{
+ struct cpu_info *ci = curcpu();
+ bool enabled = (bool)arg1;
+
+ mitigation_taa_apply_cpu(ci, enabled);
+}
+
+static void
+taa_detect_method(void)
+{
+ u_int descs[4];
+ uint64_t msr;
+
+ taa_mitigation_enabled_ptr = _mitigation_enabled;
+
+ if (cpu_vendor != CPUVENDOR_INTEL) {
+ taa_mitigation_method = TAA_MITIGATION_TAA_NO;
+
CVS commit: [netbsd-9] src/sys/arch/x86
Module Name:src
Committed By: martin
Date: Tue Nov 12 18:24:37 UTC 2019
Modified Files:
src/sys/arch/x86/include [netbsd-9]: specialreg.h
src/sys/arch/x86/x86 [netbsd-9]: spectre.c
Log Message:
Pull up following revision(s) (requested by maxv in ticket #419):
sys/arch/x86/include/specialreg.h: revision 1.157
sys/arch/x86/x86/spectre.c: revision 1.31
Mitigation for CVE-2019-11135: TSX Asynchronous Abort (TAA).
Two sysctls are added:
machdep.taa.mitigated = {0/1} user-settable
machdep.taa.method = {string} constructed by the kernel
There are two cases:
(1) If the CPU is affected by MDS, then the MDS mitigation will also
mitigate TAA, and we have nothing else to do. We make the 'mitigated' leaf
read-only, and force:
machdep.taa.mitigated = machdep.mds.mitigated
machdep.taa.method = [MDS]
The kernel already enables the MDS mitigation by default.
(2) If the CPU is not affected by MDS but is affected by TAA, then we use
the new TSX_CTRL MSR to disable RTM. This MSR is provided via a microcode
update, now available on the Intel website. The kernel will automatically
enable the TAA mitigation if the updated microcode is present. If the new
microcode is not present, the user can load it via cpuctl, and set
machdep.taa.mitigated=1.
To generate a diff of this commit:
cvs rdiff -u -r1.150.2.3 -r1.150.2.4 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.29.2.1 -r1.29.2.2 src/sys/arch/x86/x86/spectre.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Mon Nov 11 17:20:00 UTC 2019 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: intr.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #416): sys/arch/x86/x86/intr.c: revision 1.147 Fix a bug that evcnt_detach() called twice when the idt vector is full. OK'd by knakahara. To generate a diff of this commit: cvs rdiff -u -r1.146 -r1.146.2.1 src/sys/arch/x86/x86/intr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Mon Nov 11 17:20:00 UTC 2019
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: intr.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #416):
sys/arch/x86/x86/intr.c: revision 1.147
Fix a bug that evcnt_detach() called twice when the idt vector is full.
OK'd by knakahara.
To generate a diff of this commit:
cvs rdiff -u -r1.146 -r1.146.2.1 src/sys/arch/x86/x86/intr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/intr.c
diff -u src/sys/arch/x86/x86/intr.c:1.146 src/sys/arch/x86/x86/intr.c:1.146.2.1
--- src/sys/arch/x86/x86/intr.c:1.146 Mon Jun 17 06:38:30 2019
+++ src/sys/arch/x86/x86/intr.c Mon Nov 11 17:20:00 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.c,v 1.146 2019/06/17 06:38:30 msaitoh Exp $ */
+/* $NetBSD: intr.c,v 1.146.2.1 2019/11/11 17:20:00 martin Exp $ */
/*
* Copyright (c) 2007, 2008, 2009 The NetBSD Foundation, Inc.
@@ -133,7 +133,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.146 2019/06/17 06:38:30 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.146.2.1 2019/11/11 17:20:00 martin Exp $");
#include "opt_intrdebug.h"
#include "opt_multiprocessor.h"
@@ -475,8 +475,10 @@ intr_free_io_intrsource_direct(struct in
SIMPLEQ_REMOVE(_interrupt_sources, isp, intrsource, is_list);
/* Is this interrupt established? */
- if (isp->is_evname[0] != '\0')
+ if (isp->is_evname[0] != '\0') {
evcnt_detach(>is_evcnt);
+ isp->is_evname[0] = '\0';
+ }
kmem_free(isp->is_saved_evcnt,
sizeof(*(isp->is_saved_evcnt)) * ncpu);
@@ -679,6 +681,7 @@ intr_allocate_slot(struct pic *pic, int
}
if (idtvec == 0) {
evcnt_detach(>ci_isources[slot]->is_evcnt);
+ ci->ci_isources[slot]->is_evname[0] = '\0';
ci->ci_isources[slot] = NULL;
return EBUSY;
}
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Sun Nov 10 13:06:47 UTC 2019 Modified Files: src/sys/arch/x86/include [netbsd-9]: specialreg.h Log Message: Pull up following revision(s) (requested by msaitoh in ticket #407): sys/arch/x86/include/specialreg.h: revision 1.156 - GMET is not bit 11 but 17. - Add unknown CPUID Fn8000_000a %edx bit 20. To generate a diff of this commit: cvs rdiff -u -r1.150.2.2 -r1.150.2.3 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src
Committed By: martin
Date: Sun Nov 10 13:06:47 UTC 2019
Modified Files:
src/sys/arch/x86/include [netbsd-9]: specialreg.h
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #407):
sys/arch/x86/include/specialreg.h: revision 1.156
- GMET is not bit 11 but 17.
- Add unknown CPUID Fn8000_000a %edx bit 20.
To generate a diff of this commit:
cvs rdiff -u -r1.150.2.2 -r1.150.2.3 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.150.2.2 src/sys/arch/x86/include/specialreg.h:1.150.2.3
--- src/sys/arch/x86/include/specialreg.h:1.150.2.2 Thu Oct 17 18:56:24 2019
+++ src/sys/arch/x86/include/specialreg.h Sun Nov 10 13:06:46 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.150.2.2 2019/10/17 18:56:24 martin Exp $ */
+/* $NetBSD: specialreg.h,v 1.150.2.3 2019/11/10 13:06:46 martin Exp $ */
/*
* Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
@@ -755,19 +755,20 @@
#define CPUID_AMD_SVM_FlushByASID 0x0040
#define CPUID_AMD_SVM_DecodeAssist 0x0080
#define CPUID_AMD_SVM_PauseFilter 0x0400
-#define CPUID_AMD_SVM_GMET 0x0800
#define CPUID_AMD_SVM_PFThreshold 0x1000 /* PAUSE filter threshold */
#define CPUID_AMD_SVM_AVIC 0x2000 /* AMD Virtual intr. ctrl */
#define CPUID_AMD_SVM_V_VMSAVE_VMLOAD 0x8000 /* Virtual VM{SAVE/LOAD} */
#define CPUID_AMD_SVM_vGIF 0x0001 /* Virtualized GIF */
+#define CPUID_AMD_SVM_GMET 0x0002
#define CPUID_AMD_SVM_FLAGS "\20" \
"\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \
"\5" "TSCRate" "\6" "VMCBCleanBits" \
"\7" "FlushByASID" "\10" "DecodeAssist" \
- "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "GMET" \
+ "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \
"\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \
"\20" "V_VMSAVE_VMLOAD" \
- "\21" "VGIF"
+ "\21" "VGIF" "\22" "GMET" \
+ "\25" "B20"
/*
* AMD Fn8000_0001d Cache Topology Information.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src Committed By: martin Date: Fri Nov 1 18:17:55 UTC 2019 Modified Files: src/sys/arch/x86/x86 [netbsd-9]: cpu_rng.c Log Message: Pull up following revision(s) (requested by taca in ticket #390): sys/arch/x86/x86/cpu_rng.c: revision 1.10 Check CPU support of RDRAND before calling cpu_rng_rdrand(). cpu_earlyrng() checks CPU support of RDSEED and RDRAND before calling cpu_rng_rdseed() and cpu_rng_rdrand(). But cpu_rng_rdseed() did not check CPU support of RDRAND and system had crashed on such an environment. There is no such case with real CPU but some VM environment. Fix kern/54655 and confirmed by msaitoh@. Needs pullup to netbsd-9. To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.9.4.1 src/sys/arch/x86/x86/cpu_rng.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/x86
Module Name:src
Committed By: martin
Date: Fri Nov 1 18:17:55 UTC 2019
Modified Files:
src/sys/arch/x86/x86 [netbsd-9]: cpu_rng.c
Log Message:
Pull up following revision(s) (requested by taca in ticket #390):
sys/arch/x86/x86/cpu_rng.c: revision 1.10
Check CPU support of RDRAND before calling cpu_rng_rdrand().
cpu_earlyrng() checks CPU support of RDSEED and RDRAND before calling
cpu_rng_rdseed() and cpu_rng_rdrand().
But cpu_rng_rdseed() did not check CPU support of RDRAND and system had
crashed on such an environment. There is no such case with real CPU but
some VM environment.
Fix kern/54655 and confirmed by msaitoh@.
Needs pullup to netbsd-9.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.9.4.1 src/sys/arch/x86/x86/cpu_rng.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/cpu_rng.c
diff -u src/sys/arch/x86/x86/cpu_rng.c:1.9 src/sys/arch/x86/x86/cpu_rng.c:1.9.4.1
--- src/sys/arch/x86/x86/cpu_rng.c:1.9 Wed Aug 22 12:07:43 2018
+++ src/sys/arch/x86/x86/cpu_rng.c Fri Nov 1 18:17:55 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_rng.c,v 1.9 2018/08/22 12:07:43 maxv Exp $ */
+/* $NetBSD: cpu_rng.c,v 1.9.4.1 2019/11/01 18:17:55 martin Exp $ */
/*-
* Copyright (c) 2015 The NetBSD Foundation, Inc.
@@ -53,6 +53,8 @@ static enum {
CPU_RNG_VIA
} cpu_rng_mode __read_mostly = CPU_RNG_NONE;
+static bool has_rdrand;
+
bool
cpu_rng_init(void)
{
@@ -131,7 +133,10 @@ cpu_rng_rdseed(cpu_rng_t *out)
* to be seeded even in this case.
*/
exhausted:
- return cpu_rng_rdrand(out);
+ if (has_rdrand)
+ return cpu_rng_rdrand(out);
+ else
+ return 0;
}
static size_t
@@ -213,7 +218,7 @@ cpu_earlyrng(void *out, size_t sz)
int i;
bool has_rdseed = (cpu_feature[5] & CPUID_SEF_RDSEED) != 0;
- bool has_rdrand = (cpu_feature[1] & CPUID2_RDRAND) != 0;
+ has_rdrand = (cpu_feature[1] & CPUID2_RDRAND) != 0;
KASSERT(sz + sizeof(uint64_t) <= SHA512_DIGEST_LENGTH);
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src
Committed By: martin
Date: Wed Oct 16 17:32:17 UTC 2019
Modified Files:
src/sys/arch/x86/include [netbsd-9]: cpufunc.h
Log Message:
Pull up following revision(s) (requested by maxv in ticket #338):
sys/arch/x86/include/cpufunc.h: revision 1.35
Add a memory barrier on wrmsr, because some MSRs control memory access
rights (we don't use them though). Also add barriers on fninit and clts
for safety.
To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.34.2.1 src/sys/arch/x86/include/cpufunc.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpufunc.h
diff -u src/sys/arch/x86/include/cpufunc.h:1.34 src/sys/arch/x86/include/cpufunc.h:1.34.2.1
--- src/sys/arch/x86/include/cpufunc.h:1.34 Fri Jul 5 17:08:55 2019
+++ src/sys/arch/x86/include/cpufunc.h Wed Oct 16 17:32:17 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.h,v 1.34 2019/07/05 17:08:55 maxv Exp $ */
+/* $NetBSD: cpufunc.h,v 1.34.2.1 2019/10/16 17:32:17 martin Exp $ */
/*
* Copyright (c) 1998, 2007, 2019 The NetBSD Foundation, Inc.
@@ -271,7 +271,7 @@ union savefpu;
static inline void
fninit(void)
{
- __asm volatile ("fninit");
+ __asm volatile ("fninit" ::: "memory");
}
static inline void
@@ -303,7 +303,7 @@ fnstsw(uint16_t *val)
static inline void
clts(void)
{
- __asm volatile ("clts");
+ __asm volatile ("clts" ::: "memory");
}
void stts(void);
@@ -433,6 +433,7 @@ wrmsr(u_int msr, uint64_t val)
"wrmsr"
:
: "a" (low), "d" (high), "c" (msr)
+ : "memory"
);
}
CVS commit: [netbsd-9] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Wed Oct 16 17:32:17 UTC 2019 Modified Files: src/sys/arch/x86/include [netbsd-9]: cpufunc.h Log Message: Pull up following revision(s) (requested by maxv in ticket #338): sys/arch/x86/include/cpufunc.h: revision 1.35 Add a memory barrier on wrmsr, because some MSRs control memory access rights (we don't use them though). Also add barriers on fninit and clts for safety. To generate a diff of this commit: cvs rdiff -u -r1.34 -r1.34.2.1 src/sys/arch/x86/include/cpufunc.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src Committed By: martin Date: Tue Oct 15 18:08:31 UTC 2019 Modified Files: src/sys/arch/x86/pci [netbsd-9]: msipic.c Log Message: Pull up following revision(s) (requested by tnn in ticket #305): sys/arch/x86/pci/msipic.c: revision 1.18 change bus_space_map to _x86_memio_map Resolves bus space reservation conflict between MI and MD code. Discussion: http://mail-index.netbsd.org/port-amd64/2019/09/28/msg003014.html To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.17.2.1 src/sys/arch/x86/pci/msipic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-9] src/sys/arch/x86/pci
Module Name:src Committed By: martin Date: Tue Oct 15 18:08:31 UTC 2019 Modified Files: src/sys/arch/x86/pci [netbsd-9]: msipic.c Log Message: Pull up following revision(s) (requested by tnn in ticket #305): sys/arch/x86/pci/msipic.c: revision 1.18 change bus_space_map to _x86_memio_map Resolves bus space reservation conflict between MI and MD code. Discussion: http://mail-index.netbsd.org/port-amd64/2019/09/28/msg003014.html To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.17.2.1 src/sys/arch/x86/pci/msipic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/pci/msipic.c diff -u src/sys/arch/x86/pci/msipic.c:1.17 src/sys/arch/x86/pci/msipic.c:1.17.2.1 --- src/sys/arch/x86/pci/msipic.c:1.17 Wed Jun 26 10:20:06 2019 +++ src/sys/arch/x86/pci/msipic.c Tue Oct 15 18:08:31 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: msipic.c,v 1.17 2019/06/26 10:20:06 knakahara Exp $ */ +/* $NetBSD: msipic.c,v 1.17.2.1 2019/10/15 18:08:31 martin Exp $ */ /* * Copyright (c) 2015 Internet Initiative Japan Inc. @@ -27,7 +27,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: msipic.c,v 1.17 2019/06/26 10:20:06 knakahara Exp $"); +__KERNEL_RCSID(0, "$NetBSD: msipic.c,v 1.17.2.1 2019/10/15 18:08:31 martin Exp $"); #include "opt_intrdebug.h" @@ -711,7 +711,7 @@ msipic_construct_msix_pic(const struct p flags &= ~BUS_SPACE_MAP_PREFETCHABLE; } bssize = roundup(table_size, PAGE_SIZE); - err = bus_space_map(pa->pa_memt, memaddr + table_offset, bssize, flags, + err = _x86_memio_map(pa->pa_memt, memaddr + table_offset, bssize, flags, ); bstag = pa->pa_memt; #endif @@ -739,8 +739,8 @@ msipic_destruct_msix_pic(struct pic *msi KASSERT(msix_pic->pic_type == PIC_MSIX); msipic = msix_pic->pic_msipic; - bus_space_unmap(msipic->mp_bstag, msipic->mp_bshandle, - msipic->mp_bssize); + _x86_memio_unmap(msipic->mp_bstag, msipic->mp_bshandle, + msipic->mp_bssize, NULL); msipic_destruct_common_msi_pic(msix_pic); }
