CVS commit: src/lib/libc/arch/riscv
Module Name:src Committed By: skrll Date: Thu May 30 15:56:43 UTC 2024 Modified Files: src/lib/libc/arch/riscv: genassym.cf src/lib/libc/arch/riscv/sys: __sigtramp2.S Log Message: Annotate the RISC-V signal trampoline with CFI attributes. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/riscv/genassym.cf cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/riscv/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/riscv/sys
Module Name:src
Committed By: skrll
Date: Tue May 28 06:57:17 UTC 2024
Modified Files:
src/lib/libc/arch/riscv/sys: __sigtramp2.S
Log Message:
Change MIPS to RISC-V.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/riscv/sys/__sigtramp2.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/riscv/sys/__sigtramp2.S
diff -u src/lib/libc/arch/riscv/sys/__sigtramp2.S:1.3 src/lib/libc/arch/riscv/sys/__sigtramp2.S:1.4
--- src/lib/libc/arch/riscv/sys/__sigtramp2.S:1.3 Sun May 7 12:41:47 2023
+++ src/lib/libc/arch/riscv/sys/__sigtramp2.S Tue May 28 06:57:17 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: __sigtramp2.S,v 1.3 2023/05/07 12:41:47 skrll Exp $ */
+/* $NetBSD: __sigtramp2.S,v 1.4 2024/05/28 06:57:17 skrll Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
@@ -33,12 +33,12 @@
#include "assym.h"
#if defined(SYSLIBC_SCCS) && !defined(lint)
- RCSID("$NetBSD: __sigtramp2.S,v 1.3 2023/05/07 12:41:47 skrll Exp $")
+ RCSID("$NetBSD: __sigtramp2.S,v 1.4 2024/05/28 06:57:17 skrll Exp $")
#endif /* SYSLIBC_SCCS and not lint */
/*
- * The MIPS signal trampoline is invoked only to return from
+ * The RISC-V signal trampoline is invoked only to return from
* the signal; the kernel calls the signal handler directly.
*
* On entry, stack looks like:
CVS commit: src/lib/libc/arch/riscv/sys
Module Name:src Committed By: skrll Date: Tue May 28 06:57:17 UTC 2024 Modified Files: src/lib/libc/arch/riscv/sys: __sigtramp2.S Log Message: Change MIPS to RISC-V. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/riscv/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/riscv/gen
Module Name:src Committed By: riastradh Date: Thu May 16 01:02:35 UTC 2024 Modified Files: src/lib/libc/arch/riscv/gen: fpgetsticky.c fpsetsticky.c Log Message: riscv: More shiftiness reduction around FCSR in libc. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/riscv/gen/fpgetsticky.c \ src/lib/libc/arch/riscv/gen/fpsetsticky.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/riscv/gen
Module Name:src
Committed By: riastradh
Date: Thu May 16 01:02:35 UTC 2024
Modified Files:
src/lib/libc/arch/riscv/gen: fpgetsticky.c fpsetsticky.c
Log Message:
riscv: More shiftiness reduction around FCSR in libc.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/riscv/gen/fpgetsticky.c \
src/lib/libc/arch/riscv/gen/fpsetsticky.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/riscv/gen/fpgetsticky.c
diff -u src/lib/libc/arch/riscv/gen/fpgetsticky.c:1.3 src/lib/libc/arch/riscv/gen/fpgetsticky.c:1.4
--- src/lib/libc/arch/riscv/gen/fpgetsticky.c:1.3 Sun May 7 12:41:47 2023
+++ src/lib/libc/arch/riscv/gen/fpgetsticky.c Thu May 16 01:02:35 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: fpgetsticky.c,v 1.3 2023/05/07 12:41:47 skrll Exp $ */
+/* $NetBSD: fpgetsticky.c,v 1.4 2024/05/16 01:02:35 riastradh Exp $ */
/*
* Copyright (c) 1999 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
#if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: fpgetsticky.c,v 1.3 2023/05/07 12:41:47 skrll Exp $");
+__RCSID("$NetBSD: fpgetsticky.c,v 1.4 2024/05/16 01:02:35 riastradh Exp $");
#endif /* LIBC_SCCS and not lint */
#include "namespace.h"
@@ -47,5 +47,5 @@ __weak_alias(fpgetsticky,_fpgetsticky)
fp_except
fpgetsticky(void)
{
- return __SHIFTOUT(fcsr_read(), FCSR_FFLAGS);
+ return fcsr_fflags_read();
}
Index: src/lib/libc/arch/riscv/gen/fpsetsticky.c
diff -u src/lib/libc/arch/riscv/gen/fpsetsticky.c:1.3 src/lib/libc/arch/riscv/gen/fpsetsticky.c:1.4
--- src/lib/libc/arch/riscv/gen/fpsetsticky.c:1.3 Sun May 7 12:41:47 2023
+++ src/lib/libc/arch/riscv/gen/fpsetsticky.c Thu May 16 01:02:35 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: fpsetsticky.c,v 1.3 2023/05/07 12:41:47 skrll Exp $ */
+/* $NetBSD: fpsetsticky.c,v 1.4 2024/05/16 01:02:35 riastradh Exp $ */
/*
* Copyright (c) 1999 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
#if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: fpsetsticky.c,v 1.3 2023/05/07 12:41:47 skrll Exp $");
+__RCSID("$NetBSD: fpsetsticky.c,v 1.4 2024/05/16 01:02:35 riastradh Exp $");
#endif /* LIBC_SCCS and not lint */
#include "namespace.h"
@@ -48,5 +48,5 @@ __weak_alias(fpsetsticky,_fpsetsticky)
fp_except
fpsetsticky(fp_except mask)
{
- return __SHIFTOUT(fcsr_fflags_write(__SHIFTIN(mask, FCSR_FFLAGS)), FCSR_FFLAGS);
+ return fcsr_fflags_write(mask);
}
CVS commit: src/lib/libc/arch/riscv/gen
Module Name:src
Committed By: riastradh
Date: Thu May 16 00:56:11 UTC 2024
Modified Files:
src/lib/libc/arch/riscv/gen: fpgetround.c fpsetround.c
Log Message:
riscv: Nix shifting around FRRM and FSRM in libc too.
These read and write the floating-point rounding mode directly, not
the whole floating-point control and status register.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/riscv/gen/fpgetround.c \
src/lib/libc/arch/riscv/gen/fpsetround.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/riscv/gen/fpgetround.c
diff -u src/lib/libc/arch/riscv/gen/fpgetround.c:1.3 src/lib/libc/arch/riscv/gen/fpgetround.c:1.4
--- src/lib/libc/arch/riscv/gen/fpgetround.c:1.3 Sun May 7 12:41:47 2023
+++ src/lib/libc/arch/riscv/gen/fpgetround.c Thu May 16 00:56:11 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: fpgetround.c,v 1.3 2023/05/07 12:41:47 skrll Exp $ */
+/* $NetBSD: fpgetround.c,v 1.4 2024/05/16 00:56:11 riastradh Exp $ */
/*
* Copyright (c) 1999 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
#if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: fpgetround.c,v 1.3 2023/05/07 12:41:47 skrll Exp $");
+__RCSID("$NetBSD: fpgetround.c,v 1.4 2024/05/16 00:56:11 riastradh Exp $");
#endif /* LIBC_SCCS and not lint */
#include "namespace.h"
@@ -47,5 +47,5 @@ __weak_alias(fpgetround,_fpgetround)
fp_rnd
fpgetround(void)
{
- return __SHIFTOUT(fcsr_read(), FCSR_FRM);
+ return fcsr_frm_read();
}
Index: src/lib/libc/arch/riscv/gen/fpsetround.c
diff -u src/lib/libc/arch/riscv/gen/fpsetround.c:1.3 src/lib/libc/arch/riscv/gen/fpsetround.c:1.4
--- src/lib/libc/arch/riscv/gen/fpsetround.c:1.3 Sun May 7 12:41:47 2023
+++ src/lib/libc/arch/riscv/gen/fpsetround.c Thu May 16 00:56:11 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: fpsetround.c,v 1.3 2023/05/07 12:41:47 skrll Exp $ */
+/* $NetBSD: fpsetround.c,v 1.4 2024/05/16 00:56:11 riastradh Exp $ */
/*
* Copyright (c) 1999 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
#if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: fpsetround.c,v 1.3 2023/05/07 12:41:47 skrll Exp $");
+__RCSID("$NetBSD: fpsetround.c,v 1.4 2024/05/16 00:56:11 riastradh Exp $");
#endif /* LIBC_SCCS and not lint */
#include "namespace.h"
@@ -47,5 +47,5 @@ __weak_alias(fpsetround,_fpsetround)
fp_rnd
fpsetround(fp_rnd rnd_dir)
{
- return __SHIFTOUT(fcsr_frm_write(__SHIFTIN(rnd_dir, FCSR_FRM)), FCSR_FRM);
+ return fcsr_frm_write(rnd_dir);
}
CVS commit: src/lib/libc/arch/riscv/gen
Module Name:src Committed By: riastradh Date: Thu May 16 00:56:11 UTC 2024 Modified Files: src/lib/libc/arch/riscv/gen: fpgetround.c fpsetround.c Log Message: riscv: Nix shifting around FRRM and FSRM in libc too. These read and write the floating-point rounding mode directly, not the whole floating-point control and status register. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/riscv/gen/fpgetround.c \ src/lib/libc/arch/riscv/gen/fpsetround.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/riscv/gen
Module Name:src Committed By: skrll Date: Sat May 11 07:40:18 UTC 2024 Modified Files: src/lib/libc/arch/riscv/gen: fpsetmask.c Log Message: Do the '#if FCSR_FMASK == 0' thing that fpgetmask.c does for consistency. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/riscv/gen/fpsetmask.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/riscv/gen
Module Name:src
Committed By: skrll
Date: Sat May 11 07:40:18 UTC 2024
Modified Files:
src/lib/libc/arch/riscv/gen: fpsetmask.c
Log Message:
Do the '#if FCSR_FMASK == 0' thing that fpgetmask.c does for consistency.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/riscv/gen/fpsetmask.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/riscv/gen/fpsetmask.c
diff -u src/lib/libc/arch/riscv/gen/fpsetmask.c:1.3 src/lib/libc/arch/riscv/gen/fpsetmask.c:1.4
--- src/lib/libc/arch/riscv/gen/fpsetmask.c:1.3 Sun May 7 12:41:47 2023
+++ src/lib/libc/arch/riscv/gen/fpsetmask.c Sat May 11 07:40:18 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: fpsetmask.c,v 1.3 2023/05/07 12:41:47 skrll Exp $ */
+/* $NetBSD: fpsetmask.c,v 1.4 2024/05/11 07:40:18 skrll Exp $ */
/*
* Copyright (c) 1999 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
#if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: fpsetmask.c,v 1.3 2023/05/07 12:41:47 skrll Exp $");
+__RCSID("$NetBSD: fpsetmask.c,v 1.4 2024/05/11 07:40:18 skrll Exp $");
#endif /* LIBC_SCCS and not lint */
#include "namespace.h"
@@ -47,9 +47,9 @@ __weak_alias(fpsetmask,_fpsetmask)
fp_except
fpsetmask(fp_except mask)
{
-#if 0
- return __SHIFTOUT(fcsr_fmask_write(__SHIFTIN(mask, FCSR_MASK)), FCSR_FMASK);
-#else
+#if FCSR_FMASK == 0
return 0;
+#else
+ return __SHIFTOUT(fcsr_fmask_write(__SHIFTIN(mask, FCSR_MASK)), FCSR_FMASK);
#endif
}
CVS commit: src/lib/libc/arch/arm/gen
Module Name:src
Committed By: skrll
Date: Mon May 6 06:57:32 UTC 2024
Modified Files:
src/lib/libc/arch/arm/gen: setjmp.S
Log Message:
arm longjmp: Restore stack first, then signal mask.
Otherwise, a pending signal may be delivered on the wrong stack when
we restore the signal mask.
While here:
- Move the botched sp and lr tests earlier.
PR lib/57946
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/lib/libc/arch/arm/gen/setjmp.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/arm/gen/setjmp.S
diff -u src/lib/libc/arch/arm/gen/setjmp.S:1.18 src/lib/libc/arch/arm/gen/setjmp.S:1.19
--- src/lib/libc/arch/arm/gen/setjmp.S:1.18 Tue Dec 13 12:43:32 2022
+++ src/lib/libc/arch/arm/gen/setjmp.S Mon May 6 06:57:32 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: setjmp.S,v 1.18 2022/12/13 12:43:32 skrll Exp $ */
+/* $NetBSD: setjmp.S,v 1.19 2024/05/06 06:57:32 skrll Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe
@@ -142,6 +142,25 @@ ENTRY(__longjmp14)
cmp r3, ip
bne .Lbotch
+ /* Validate sp and lr */
+ ldr r2, [r0, #(_JB_REG_R13 * 4)]
+#if defined(__thumb__) && defined(_ARM_ARCH_T2)
+ cbz r2, .Lbotch
+#else
+ cmp r2, #0
+ beq .Lbotch
+#endif
+
+ ldr r3, [r0, #(_JB_REG_R14 * 4)]
+#if defined(__thumb__) && defined(_ARM_ARCH_T2)
+ cbz r3, .Lbotch
+#else
+ cmp r3, #0
+ beq .Lbotch
+#endif
+ mov sp, r2
+ mov lr, r3
+
/* Restore the signal mask. */
push {r0-r2, lr}
movs r2, #0
@@ -186,25 +205,6 @@ ENTRY(__longjmp14)
adds r0, r0, #4 /* skip ip(r12) */
#endif
- ldmia r0!, {r2-r3}
-
- /* Validate sp and lr */
-#if defined(__thumb__) && defined(_ARM_ARCH_T2)
- cbz r2, .Lbotch
-#else
- cmp r2, #0
- beq .Lbotch
-#endif
- mov sp, r2
-
-#if defined(__thumb__) && defined(_ARM_ARCH_T2)
- cbz r3, .Lbotch
-#else
- cmp r3, #0
- beq .Lbotch
-#endif
- mov lr, r3
-
/* Set return value */
movs r0, r1
#if !defined(__thumb__)
CVS commit: src/lib/libc/arch/arm/gen
Module Name:src Committed By: skrll Date: Mon May 6 06:57:32 UTC 2024 Modified Files: src/lib/libc/arch/arm/gen: setjmp.S Log Message: arm longjmp: Restore stack first, then signal mask. Otherwise, a pending signal may be delivered on the wrong stack when we restore the signal mask. While here: - Move the botched sp and lr tests earlier. PR lib/57946 To generate a diff of this commit: cvs rdiff -u -r1.18 -r1.19 src/lib/libc/arch/arm/gen/setjmp.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/hppa/gen
Module Name:src Committed By: skrll Date: Sat May 4 14:48:28 UTC 2024 Modified Files: src/lib/libc/arch/hppa/gen: _setjmp.S Log Message: Remove magic numbers. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/lib/libc/arch/hppa/gen/_setjmp.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/riscv/gen
Module Name:src Committed By: skrll Date: Sat May 4 12:43:36 UTC 2024 Modified Files: src/lib/libc/arch/riscv/gen: makecontext.c Log Message: makecontext: correct the type to setup register based arguments. Use __greg_t rather than int for register based arguments. This fixes various atf tests. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/lib/libc/arch/riscv/gen/makecontext.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/riscv/gen
Module Name:src
Committed By: skrll
Date: Sat May 4 12:43:36 UTC 2024
Modified Files:
src/lib/libc/arch/riscv/gen: makecontext.c
Log Message:
makecontext: correct the type to setup register based arguments.
Use __greg_t rather than int for register based arguments. This fixes
various atf tests.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/lib/libc/arch/riscv/gen/makecontext.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/riscv/gen/makecontext.c
diff -u src/lib/libc/arch/riscv/gen/makecontext.c:1.2 src/lib/libc/arch/riscv/gen/makecontext.c:1.3
--- src/lib/libc/arch/riscv/gen/makecontext.c:1.2 Sun May 7 12:41:47 2023
+++ src/lib/libc/arch/riscv/gen/makecontext.c Sat May 4 12:43:36 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: makecontext.c,v 1.2 2023/05/07 12:41:47 skrll Exp $ */
+/* $NetBSD: makecontext.c,v 1.3 2024/05/04 12:43:36 skrll Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
#if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: makecontext.c,v 1.2 2023/05/07 12:41:47 skrll Exp $");
+__RCSID("$NetBSD: makecontext.c,v 1.3 2024/05/04 12:43:36 skrll Exp $");
#endif
#include
@@ -75,7 +75,7 @@ makecontext(ucontext_t *ucp, void (*func
va_start(ap, argc);
/* Up to the first eight arguments are passed in a0(x10)-a7(x17) */
for (i = 0; i < argc && i < 8; i++)
- gr[_REG_A0 + i] = va_arg(ap, int);
+ gr[_REG_A0 + i] = va_arg(ap, __greg_t);
/* Pass remaining arguments on the stack above the backchain/lr gap. */
for (sp += 0; i < argc; i++)
*sp++ = va_arg(ap, long);
CVS commit: src/lib/libc/arch/hppa
Module Name:src
Committed By: skrll
Date: Sat Apr 20 14:09:40 UTC 2024
Modified Files:
src/lib/libc/arch/hppa: genassym.cf
src/lib/libc/arch/hppa/gen: __setjmp14.S
Log Message:
Remove some magic numbers by using genassym.cf
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/hppa/genassym.cf
cvs rdiff -u -r1.9 -r1.10 src/lib/libc/arch/hppa/gen/__setjmp14.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/hppa/genassym.cf
diff -u src/lib/libc/arch/hppa/genassym.cf:1.4 src/lib/libc/arch/hppa/genassym.cf:1.5
--- src/lib/libc/arch/hppa/genassym.cf:1.4 Sun Jun 26 14:37:12 2022
+++ src/lib/libc/arch/hppa/genassym.cf Sat Apr 20 14:09:40 2024
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.4 2022/06/26 14:37:12 skrll Exp $
+# $NetBSD: genassym.cf,v 1.5 2024/04/20 14:09:40 skrll Exp $
#
# Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -104,3 +104,16 @@ define _UC_GREGS_R28 offsetof(ucontext_t
define _UC_GREGS_R29 offsetof(ucontext_t, uc_mcontext.__gregs[29])
define _UC_GREGS_R30 offsetof(ucontext_t, uc_mcontext.__gregs[30])
define _UC_GREGS_R31 offsetof(ucontext_t, uc_mcontext.__gregs[31])
+
+define SIZEOF_SIGCONTEXT sizeof(struct sigcontext)
+define _SC_ONSTACK offsetof(struct sigcontext, sc_onstack)
+define _SC_MASK13 offsetof(struct sigcontext, __sc_mask13)
+define _SC_REGS_SP offsetof(struct sigcontext, sc_sp)
+define _SC_REGS_FP offsetof(struct sigcontext, sc_fp)
+define _SC_REGS_AP offsetof(struct sigcontext, sc_ap)
+define _SC_REGS_PCSQH offsetof(struct sigcontext, sc_pcsqh)
+define _SC_REGS_PCOQH offsetof(struct sigcontext, sc_pcoqh)
+define _SC_REGS_PCSQT offsetof(struct sigcontext, sc_pcsqt)
+define _SC_REGS_PCOQT offsetof(struct sigcontext, sc_pcoqt)
+define _SC_REGS_PS offsetof(struct sigcontext, sc_ps)
+define _SC_MASK offsetof(struct sigcontext, sc_mask)
Index: src/lib/libc/arch/hppa/gen/__setjmp14.S
diff -u src/lib/libc/arch/hppa/gen/__setjmp14.S:1.9 src/lib/libc/arch/hppa/gen/__setjmp14.S:1.10
--- src/lib/libc/arch/hppa/gen/__setjmp14.S:1.9 Tue May 5 06:20:55 2020
+++ src/lib/libc/arch/hppa/gen/__setjmp14.S Sat Apr 20 14:09:40 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: __setjmp14.S,v 1.9 2020/05/05 06:20:55 skrll Exp $ */
+/* $NetBSD: __setjmp14.S,v 1.10 2024/04/20 14:09:40 skrll Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
@@ -29,12 +29,14 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include "assym.h"
+
#include
#include
#include
#if defined(LIBC_SCCS) && !defined(lint)
- RCSID("$NetBSD: __setjmp14.S,v 1.9 2020/05/05 06:20:55 skrll Exp $")
+ RCSID("$NetBSD: __setjmp14.S,v 1.10 2024/04/20 14:09:40 skrll Exp $")
#endif /* LIBC_SCCS and not lint */
/*
@@ -54,21 +56,21 @@ ENTRY(__setjmp14,0)
stw %arg0, HPPA_FRAME_ARG(0)(%sp)
/* A sigcontext is at the beginning of our jmp_buf. */
- stw %r0, 4(%arg0) ; unused word (old style signal mask)
- stw %sp, 8(%arg0) ; sc.sc_sp = %sp
- stw %r0, 16(%arg0) ; sc.sc_ap = NULL
+ stw %r0, _SC_MASK13(%arg0) ; unused word (old style signal mask)
+ stw %sp, _SC_REGS_SP(%arg0) ; sc.sc_sp = %sp
+ stw %r0, _SC_REGS_AP(%arg0) ; sc.sc_ap = NULL
mfsp %sr0, %r1
- stw %r1, 20(%arg0) ; sc.sc_pcsqh = %sr0
- stw %rp, 24(%arg0) ; sc.sc_pcoqh = %rp
- stw %r1, 28(%arg0) ; sc.sc_pcsqh = %sr0
+ stw %r1, _SC_REGS_PCSQH(%arg0) ; sc.sc_pcsqh = %sr0
+ stw %rp, _SC_REGS_PCOQH(%arg0) ; sc.sc_pcoqh = %rp
+ stw %r1, _SC_REGS_PCSQT(%arg0) ; sc.sc_pcsqt = %sr0
ldo 4(%rp), %r1
- stw %r1, 32(%arg0) ; sc.sc_pcoqt = %rp + 4
+ stw %r1, _SC_REGS_PCOQT(%arg0) ; sc.sc_pcoqt = %rp + 4
ldil L%PSW_MBS, %r1
ldo R%PSW_MBS(%r1), %r1
- stw %r1, 36(%arg0) ; set sc.sc_ps
+ stw %r1, _SC_REGS_PS(%arg0) ; set sc.sc_ps
/* We store all callee-saved registers after the sigcontext. */
- ldo 56(%arg0), %r1
+ ldo SIZEOF_SIGCONTEXT(%arg0), %r1
stwm %r3, 4(%r1)
stwm %r4, 4(%r1)
stwm %r5, 4(%r1)
@@ -111,7 +113,7 @@ ENTRY(__setjmp14,0)
stw %r1, 0(%arg0) ; sc.sc_onstack
/* Get the signal mask. */
- ldo 40(%arg0), %arg2 ; oset = _mask
+ ldo _SC_MASK(%arg0), %arg2 ; oset = _mask
copy %r0, %arg1 ; set = NULL
bl __sigprocmask14, %rp
copy %r0, %arg0 ; action = 0
CVS commit: src/lib/libc/arch/hppa
Module Name:src Committed By: skrll Date: Sat Apr 20 14:09:40 UTC 2024 Modified Files: src/lib/libc/arch/hppa: genassym.cf src/lib/libc/arch/hppa/gen: __setjmp14.S Log Message: Remove some magic numbers by using genassym.cf To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/hppa/genassym.cf cvs rdiff -u -r1.9 -r1.10 src/lib/libc/arch/hppa/gen/__setjmp14.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/sparc/gen
Module Name:src Committed By: rillig Date: Tue Apr 2 20:42:13 UTC 2024 Modified Files: src/lib/libc/arch/sparc/gen: fpsetround.c Log Message: sparc/fpsetround: fix the nearby signed integer overflow as well Same as for sparc64 a few days ago. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/lib/libc/arch/sparc/gen/fpsetround.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/sparc/gen
Module Name:src
Committed By: rillig
Date: Tue Apr 2 20:42:13 UTC 2024
Modified Files:
src/lib/libc/arch/sparc/gen: fpsetround.c
Log Message:
sparc/fpsetround: fix the nearby signed integer overflow as well
Same as for sparc64 a few days ago.
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/lib/libc/arch/sparc/gen/fpsetround.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/sparc/gen/fpsetround.c
diff -u src/lib/libc/arch/sparc/gen/fpsetround.c:1.7 src/lib/libc/arch/sparc/gen/fpsetround.c:1.8
--- src/lib/libc/arch/sparc/gen/fpsetround.c:1.7 Tue Apr 2 20:27:44 2024
+++ src/lib/libc/arch/sparc/gen/fpsetround.c Tue Apr 2 20:42:12 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: fpsetround.c,v 1.7 2024/04/02 20:27:44 christos Exp $ */
+/* $NetBSD: fpsetround.c,v 1.8 2024/04/02 20:42:12 rillig Exp $ */
/*
* Written by J.T. Conklin, Apr 10, 1995
@@ -7,7 +7,7 @@
#include
#if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: fpsetround.c,v 1.7 2024/04/02 20:27:44 christos Exp $");
+__RCSID("$NetBSD: fpsetround.c,v 1.8 2024/04/02 20:42:12 rillig Exp $");
#endif /* LIBC_SCCS and not lint */
#include "namespace.h"
@@ -27,8 +27,8 @@ fpsetround(fp_rnd rnd_dir)
__asm("st %%fsr,%0" : "=m" (*));
new = old;
- new &= ~(0x03U << 30);
- new |= ((rnd_dir & 0x03) << 30);
+ new &= ~(0x03U << 30);
+ new |= ((rnd_dir & 0x03U) << 30);
__asm("ld %0,%%fsr" : : "m" (*));
CVS commit: src/lib/libc/arch/sparc/gen
Module Name:src Committed By: christos Date: Tue Apr 2 20:27:44 UTC 2024 Modified Files: src/lib/libc/arch/sparc/gen: fpsetround.c Log Message: fix lint To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/lib/libc/arch/sparc/gen/fpsetround.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/sparc/gen
Module Name:src
Committed By: christos
Date: Tue Apr 2 20:27:44 UTC 2024
Modified Files:
src/lib/libc/arch/sparc/gen: fpsetround.c
Log Message:
fix lint
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/lib/libc/arch/sparc/gen/fpsetround.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/sparc/gen/fpsetround.c
diff -u src/lib/libc/arch/sparc/gen/fpsetround.c:1.6 src/lib/libc/arch/sparc/gen/fpsetround.c:1.7
--- src/lib/libc/arch/sparc/gen/fpsetround.c:1.6 Tue Mar 20 20:38:35 2012
+++ src/lib/libc/arch/sparc/gen/fpsetround.c Tue Apr 2 16:27:44 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: fpsetround.c,v 1.6 2012/03/21 00:38:35 christos Exp $ */
+/* $NetBSD: fpsetround.c,v 1.7 2024/04/02 20:27:44 christos Exp $ */
/*
* Written by J.T. Conklin, Apr 10, 1995
@@ -7,7 +7,7 @@
#include
#if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: fpsetround.c,v 1.6 2012/03/21 00:38:35 christos Exp $");
+__RCSID("$NetBSD: fpsetround.c,v 1.7 2024/04/02 20:27:44 christos Exp $");
#endif /* LIBC_SCCS and not lint */
#include "namespace.h"
@@ -27,7 +27,7 @@ fpsetround(fp_rnd rnd_dir)
__asm("st %%fsr,%0" : "=m" (*));
new = old;
- new &= ~(0x03 << 30);
+ new &= ~(0x03U << 30);
new |= ((rnd_dir & 0x03) << 30);
__asm("ld %0,%%fsr" : : "m" (*));
CVS commit: src/lib/libc/arch/sparc64/gen
Module Name:src
Committed By: rillig
Date: Wed Mar 20 06:15:40 UTC 2024
Modified Files:
src/lib/libc/arch/sparc64/gen: fpsetround.c
Log Message:
sparc64/fpsetround: avoid shifting into the sign bit
Lint had warned about the constant expression '0x03 << 30' but not about
the structurally equal nonconstant expression '(rnd_dir & 0x03) << 30'.
No binary change.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/lib/libc/arch/sparc64/gen/fpsetround.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/sparc64/gen/fpsetround.c
diff -u src/lib/libc/arch/sparc64/gen/fpsetround.c:1.8 src/lib/libc/arch/sparc64/gen/fpsetround.c:1.9
--- src/lib/libc/arch/sparc64/gen/fpsetround.c:1.8 Mon Mar 11 23:05:35 2024
+++ src/lib/libc/arch/sparc64/gen/fpsetround.c Wed Mar 20 06:15:39 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: fpsetround.c,v 1.8 2024/03/11 23:05:35 christos Exp $ */
+/* $NetBSD: fpsetround.c,v 1.9 2024/03/20 06:15:39 rillig Exp $ */
/*
* Written by J.T. Conklin, Apr 10, 1995
@@ -7,7 +7,7 @@
#include
#if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: fpsetround.c,v 1.8 2024/03/11 23:05:35 christos Exp $");
+__RCSID("$NetBSD: fpsetround.c,v 1.9 2024/03/20 06:15:39 rillig Exp $");
#endif /* LIBC_SCCS and not lint */
#include "namespace.h"
@@ -36,8 +36,8 @@ fpsetround(fp_rnd rnd_dir)
#endif
new = old;
- new &= ~(0x03U << 30);
- new |= ((rnd_dir & 0x03) << 30);
+ new &= ~(0x03U << 30);
+ new |= ((rnd_dir & 0x03U) << 30);
__asm("ld %0,%%fsr" : : "m" (*));
CVS commit: src/lib/libc/arch/sparc64/gen
Module Name:src Committed By: rillig Date: Wed Mar 20 06:15:40 UTC 2024 Modified Files: src/lib/libc/arch/sparc64/gen: fpsetround.c Log Message: sparc64/fpsetround: avoid shifting into the sign bit Lint had warned about the constant expression '0x03 << 30' but not about the structurally equal nonconstant expression '(rnd_dir & 0x03) << 30'. No binary change. To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/lib/libc/arch/sparc64/gen/fpsetround.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/sparc64/gen
Module Name:src Committed By: christos Date: Mon Mar 11 23:05:35 UTC 2024 Modified Files: src/lib/libc/arch/sparc64/gen: fpsetround.c Log Message: fix lint To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/lib/libc/arch/sparc64/gen/fpsetround.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/sparc64/gen
Module Name:src
Committed By: christos
Date: Mon Mar 11 23:05:35 UTC 2024
Modified Files:
src/lib/libc/arch/sparc64/gen: fpsetround.c
Log Message:
fix lint
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/lib/libc/arch/sparc64/gen/fpsetround.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/sparc64/gen/fpsetround.c
diff -u src/lib/libc/arch/sparc64/gen/fpsetround.c:1.7 src/lib/libc/arch/sparc64/gen/fpsetround.c:1.8
--- src/lib/libc/arch/sparc64/gen/fpsetround.c:1.7 Sun Oct 27 21:06:36 2013
+++ src/lib/libc/arch/sparc64/gen/fpsetround.c Mon Mar 11 19:05:35 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: fpsetround.c,v 1.7 2013/10/28 01:06:36 mrg Exp $ */
+/* $NetBSD: fpsetround.c,v 1.8 2024/03/11 23:05:35 christos Exp $ */
/*
* Written by J.T. Conklin, Apr 10, 1995
@@ -7,7 +7,7 @@
#include
#if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: fpsetround.c,v 1.7 2013/10/28 01:06:36 mrg Exp $");
+__RCSID("$NetBSD: fpsetround.c,v 1.8 2024/03/11 23:05:35 christos Exp $");
#endif /* LIBC_SCCS and not lint */
#include "namespace.h"
@@ -19,14 +19,15 @@ __RCSID("$NetBSD: fpsetround.c,v 1.7 201
__weak_alias(fpsetround,_fpsetround)
#endif
+#ifdef SOFTFLOATSPARC64_FOR_GCC
+extern fp_rnd _softfloat_float_rounding_mode;
+#endif
+
fp_rnd
fpsetround(fp_rnd rnd_dir)
{
fp_rnd old;
fp_rnd new;
-#ifdef SOFTFLOATSPARC64_FOR_GCC
- extern fp_rnd _softfloat_float_rounding_mode;
-#endif
__asm("st %%fsr,%0" : "=m" (*));
@@ -35,7 +36,7 @@ fpsetround(fp_rnd rnd_dir)
#endif
new = old;
- new &= ~(0x03 << 30);
+ new &= ~(0x03U << 30);
new |= ((rnd_dir & 0x03) << 30);
__asm("ld %0,%%fsr" : : "m" (*));
CVS commit: src/lib/libc/arch/sparc/gen
Module Name:src Committed By: uwe Date: Tue Feb 20 00:09:31 UTC 2024 Modified Files: src/lib/libc/arch/sparc/gen: longjmp.c Log Message: fix typo in comment To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/sparc/gen/longjmp.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/lib/libc/arch/sparc/gen/longjmp.c diff -u src/lib/libc/arch/sparc/gen/longjmp.c:1.4 src/lib/libc/arch/sparc/gen/longjmp.c:1.5 --- src/lib/libc/arch/sparc/gen/longjmp.c:1.4 Sun Sep 3 21:41:45 2023 +++ src/lib/libc/arch/sparc/gen/longjmp.c Tue Feb 20 00:09:31 2024 @@ -1,4 +1,4 @@ -/* $NetBSD: longjmp.c,v 1.4 2023/09/03 21:41:45 mrg Exp $ */ +/* $NetBSD: longjmp.c,v 1.5 2024/02/20 00:09:31 uwe Exp $ */ /*- * Copyright (c) 2003 The NetBSD Foundation, Inc. @@ -47,7 +47,7 @@ /* * check that offsets in the above structures match their usage in the * setjmp() side of this setup. a jmp_buf is the 12-word contents of - * the sigcontexst structure, plus 2 more words for g4 and g7. + * the sigcontext structure, plus 2 more words for g4 and g7. */ __CTASSERT(_SIZEOF_SC + _JB_G4 == offsetof(struct __jmp_buf,regs.g4)); __CTASSERT(_SIZEOF_SC + _JB_G7 == offsetof(struct __jmp_buf,regs.g7));
CVS commit: src/lib/libc/arch/sparc/gen
Module Name:src Committed By: uwe Date: Tue Feb 20 00:09:31 UTC 2024 Modified Files: src/lib/libc/arch/sparc/gen: longjmp.c Log Message: fix typo in comment To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/sparc/gen/longjmp.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch
Module Name:src
Committed By: skrll
Date: Wed Oct 11 09:12:21 UTC 2023
Modified Files:
src/lib/libc/arch/ia64/gen: setjmp.S
src/lib/libc/arch/or1k/gen: __setjmp14.S
src/lib/libc/arch/powerpc/gen: __setjmp14.S __sigsetjmp14.S
src/lib/libc/arch/powerpc64/gen: __setjmp14.S __sigsetjmp14.S
src/lib/libc/arch/riscv/gen: __setjmp14.S
src/lib/libc/arch/sh3/gen: setjmp.S sigsetjmp.S
src/lib/libc/arch/sparc/gen: setjmp.S
src/lib/libc/arch/sparc64/gen: setjmp.S
Log Message:
Consistently pass 0 as first and ignored argument to sigprocmask in the
setjmp implementations.
NFCI.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/lib/libc/arch/ia64/gen/setjmp.S
cvs rdiff -u -r1.1 -r1.2 src/lib/libc/arch/or1k/gen/__setjmp14.S
cvs rdiff -u -r1.5 -r1.6 src/lib/libc/arch/powerpc/gen/__setjmp14.S \
src/lib/libc/arch/powerpc/gen/__sigsetjmp14.S
cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/powerpc64/gen/__setjmp14.S
cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/powerpc64/gen/__sigsetjmp14.S
cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/riscv/gen/__setjmp14.S
cvs rdiff -u -r1.10 -r1.11 src/lib/libc/arch/sh3/gen/setjmp.S
cvs rdiff -u -r1.9 -r1.10 src/lib/libc/arch/sh3/gen/sigsetjmp.S
cvs rdiff -u -r1.13 -r1.14 src/lib/libc/arch/sparc/gen/setjmp.S
cvs rdiff -u -r1.11 -r1.12 src/lib/libc/arch/sparc64/gen/setjmp.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/ia64/gen/setjmp.S
diff -u src/lib/libc/arch/ia64/gen/setjmp.S:1.2 src/lib/libc/arch/ia64/gen/setjmp.S:1.3
--- src/lib/libc/arch/ia64/gen/setjmp.S:1.2 Wed Oct 11 06:15:36 2023
+++ src/lib/libc/arch/ia64/gen/setjmp.S Wed Oct 11 09:12:20 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: setjmp.S,v 1.2 2023/10/11 06:15:36 skrll Exp $ */
+/* $NetBSD: setjmp.S,v 1.3 2023/10/11 09:12:20 skrll Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
@@ -30,7 +30,7 @@
#define _LOCORE
#include
-RCSID("$NetBSD: setjmp.S,v 1.2 2023/10/11 06:15:36 skrll Exp $")
+RCSID("$NetBSD: setjmp.S,v 1.3 2023/10/11 09:12:20 skrll Exp $")
#include
@@ -49,7 +49,7 @@ ENTRY(__setjmp14, 1)
alloc loc0=ar.pfs,1,2,3,0
mov loc1=rp
;;
- mov out0=1// how = SIG_BLOCK
+ mov out0=0// how is ignored
mov out1=0// set = NULL
add out2=J_SIGSET,in0 // oset = [J_SIGSET]
br.call.sptk.few rp=_sys___sigprocmask14
Index: src/lib/libc/arch/or1k/gen/__setjmp14.S
diff -u src/lib/libc/arch/or1k/gen/__setjmp14.S:1.1 src/lib/libc/arch/or1k/gen/__setjmp14.S:1.2
--- src/lib/libc/arch/or1k/gen/__setjmp14.S:1.1 Wed Sep 3 19:34:25 2014
+++ src/lib/libc/arch/or1k/gen/__setjmp14.S Wed Oct 11 09:12:21 2023
@@ -1,10 +1,10 @@
-/* $NetBSD: __setjmp14.S,v 1.1 2014/09/03 19:34:25 matt Exp $ */
+/* $NetBSD: __setjmp14.S,v 1.2 2023/10/11 09:12:21 skrll Exp $ */
#include "SYS.h"
#include "assym.h"
#if defined(LIBC_SCCS)
-__RCSID("$NetBSD: __setjmp14.S,v 1.1 2014/09/03 19:34:25 matt Exp $")
+__RCSID("$NetBSD: __setjmp14.S,v 1.2 2023/10/11 09:12:21 skrll Exp $")
#endif
/*
@@ -36,7 +36,7 @@ ENTRY(__setjmp14)
l.sw JB_MAGIC(r3), r4 /* note we saved sigmask */
l.addi r5, r3, JB_SIGMASK #
l.xor r4, r4, r4
- l.addi r3, r0, SIG_BLOCK
+ l.addi r3, r0, 0
_DOSYSCALL(__sigprocmask14) # assume no error XXX
l.xor r11, r11, r11
l.jr lr
Index: src/lib/libc/arch/powerpc/gen/__setjmp14.S
diff -u src/lib/libc/arch/powerpc/gen/__setjmp14.S:1.5 src/lib/libc/arch/powerpc/gen/__setjmp14.S:1.6
--- src/lib/libc/arch/powerpc/gen/__setjmp14.S:1.5 Sat Jan 15 07:31:12 2011
+++ src/lib/libc/arch/powerpc/gen/__setjmp14.S Wed Oct 11 09:12:21 2023
@@ -1,10 +1,10 @@
-/* $NetBSD: __setjmp14.S,v 1.5 2011/01/15 07:31:12 matt Exp $ */
+/* $NetBSD: __setjmp14.S,v 1.6 2023/10/11 09:12:21 skrll Exp $ */
#include "SYS.h"
#include "assym.h"
#if defined(LIBC_SCCS)
-__RCSID("$NetBSD: __setjmp14.S,v 1.5 2011/01/15 07:31:12 matt Exp $")
+__RCSID("$NetBSD: __setjmp14.S,v 1.6 2023/10/11 09:12:21 skrll Exp $")
#endif
/*
@@ -19,8 +19,8 @@ __RCSID("$NetBSD: __setjmp14.S,v 1.5 201
ENTRY(__setjmp14)
mr %r6,%r3
- li %r3,SIG_BLOCK
- li %r4,0
+ li %r3,0 # how is ignored
+ li %r4,0 # set = NULL
addi %r5,%r6,4*(1+24) #
_DOSYSCALL(__sigprocmask14) # assume no error XXX
mflr %r11
Index: src/lib/libc/arch/powerpc/gen/__sigsetjmp14.S
diff -u src/lib/libc/arch/powerpc/gen/__sigsetjmp14.S:1.5 src/lib/libc/arch/powerpc/gen/__sigsetjmp14.S:1.6
--- src/lib/libc/arch/powerpc/gen/__sigsetjmp14.S:1.5 Sat Jan 15 07:31:12 2011
+++ src/lib/libc/arch/powerpc/gen/__sigsetjmp14.S Wed Oct 11 09:12:21 2023
@@ -1,18 +1,18 @@
-/* $NetBSD: __sigsetjmp14.S,v 1.5 2011/01/15 07:31:12 matt Exp $ */
+/* $NetBSD: __sigsetjmp14.S,v 1.6 2023/10/11 09:12:21 skrll Exp $ */
#include "SYS.h"
#include "assym.h"
#if defined(LIBC_SCCS)
-__RCSID("$NetBSD: __sigsetjmp14.S,v 1.5 2011/01/15 07:31:12 matt Exp $")
+__RCSID("$NetBSD: __sigsetjmp14.S,v 1.6
CVS commit: src/lib/libc/arch
Module Name:src Committed By: skrll Date: Wed Oct 11 09:12:21 UTC 2023 Modified Files: src/lib/libc/arch/ia64/gen: setjmp.S src/lib/libc/arch/or1k/gen: __setjmp14.S src/lib/libc/arch/powerpc/gen: __setjmp14.S __sigsetjmp14.S src/lib/libc/arch/powerpc64/gen: __setjmp14.S __sigsetjmp14.S src/lib/libc/arch/riscv/gen: __setjmp14.S src/lib/libc/arch/sh3/gen: setjmp.S sigsetjmp.S src/lib/libc/arch/sparc/gen: setjmp.S src/lib/libc/arch/sparc64/gen: setjmp.S Log Message: Consistently pass 0 as first and ignored argument to sigprocmask in the setjmp implementations. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/lib/libc/arch/ia64/gen/setjmp.S cvs rdiff -u -r1.1 -r1.2 src/lib/libc/arch/or1k/gen/__setjmp14.S cvs rdiff -u -r1.5 -r1.6 src/lib/libc/arch/powerpc/gen/__setjmp14.S \ src/lib/libc/arch/powerpc/gen/__sigsetjmp14.S cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/powerpc64/gen/__setjmp14.S cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/powerpc64/gen/__sigsetjmp14.S cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/riscv/gen/__setjmp14.S cvs rdiff -u -r1.10 -r1.11 src/lib/libc/arch/sh3/gen/setjmp.S cvs rdiff -u -r1.9 -r1.10 src/lib/libc/arch/sh3/gen/sigsetjmp.S cvs rdiff -u -r1.13 -r1.14 src/lib/libc/arch/sparc/gen/setjmp.S cvs rdiff -u -r1.11 -r1.12 src/lib/libc/arch/sparc64/gen/setjmp.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/sparc64/gen
Module Name:src
Committed By: skrll
Date: Wed Oct 11 06:16:13 UTC 2023
Modified Files:
src/lib/libc/arch/sparc64/gen: setjmp.S
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/lib/libc/arch/sparc64/gen/setjmp.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/sparc64/gen/setjmp.S
diff -u src/lib/libc/arch/sparc64/gen/setjmp.S:1.10 src/lib/libc/arch/sparc64/gen/setjmp.S:1.11
--- src/lib/libc/arch/sparc64/gen/setjmp.S:1.10 Thu Sep 12 15:36:16 2013
+++ src/lib/libc/arch/sparc64/gen/setjmp.S Wed Oct 11 06:16:13 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: setjmp.S,v 1.10 2013/09/12 15:36:16 joerg Exp $ */
+/* $NetBSD: setjmp.S,v 1.11 2023/10/11 06:16:13 skrll Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -42,7 +42,7 @@
#if 0
.asciz "@(#)setjmp.s 8.1 (Berkeley) 6/4/93"
#else
- RCSID("$NetBSD: setjmp.S,v 1.10 2013/09/12 15:36:16 joerg Exp $")
+ RCSID("$NetBSD: setjmp.S,v 1.11 2023/10/11 06:16:13 skrll Exp $")
#endif
#endif /* LIBC_SCCS and not lint */
@@ -107,7 +107,7 @@ ENTRY(__setjmp14)
call _C_LABEL(__sigaltstack14)
#endif
add %i0, 8, %o1 /* (foo being part of the sigcontext we're overwriting) */
-
+
lduw [%i0 + 8 + 0x10], %o0 /* foo.ss_flags */
and %o0, 1, %o1 /* onstack = foo.ss_flags & SS_ONSTACK; */
st %o1, [%i0 + 0x00] /* sc.sc_onstack = current onstack; */
CVS commit: src/lib/libc/arch/sparc64/gen
Module Name:src Committed By: skrll Date: Wed Oct 11 06:16:13 UTC 2023 Modified Files: src/lib/libc/arch/sparc64/gen: setjmp.S Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/lib/libc/arch/sparc64/gen/setjmp.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/powerpc64/gen
Module Name:src
Committed By: skrll
Date: Wed Oct 11 06:15:57 UTC 2023
Modified Files:
src/lib/libc/arch/powerpc64/gen: __setjmp14.S
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/powerpc64/gen/__setjmp14.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/powerpc64/gen/__setjmp14.S
diff -u src/lib/libc/arch/powerpc64/gen/__setjmp14.S:1.3 src/lib/libc/arch/powerpc64/gen/__setjmp14.S:1.4
--- src/lib/libc/arch/powerpc64/gen/__setjmp14.S:1.3 Sat Aug 23 02:24:22 2014
+++ src/lib/libc/arch/powerpc64/gen/__setjmp14.S Wed Oct 11 06:15:57 2023
@@ -1,9 +1,9 @@
-/* $NetBSD: __setjmp14.S,v 1.3 2014/08/23 02:24:22 matt Exp $ */
+/* $NetBSD: __setjmp14.S,v 1.4 2023/10/11 06:15:57 skrll Exp $ */
#include "SYS.h"
#if defined(LIBC_SCCS)
-__RCSID("$NetBSD: __setjmp14.S,v 1.3 2014/08/23 02:24:22 matt Exp $")
+__RCSID("$NetBSD: __setjmp14.S,v 1.4 2023/10/11 06:15:57 skrll Exp $")
#endif
/*
@@ -68,7 +68,7 @@ ENTRY(__longjmp14)
ld %r16,72(%r6)
ld %r17,80(%r6)
ld %r18,88(%r6)
- ld %r19,96(%r6)
+ ld %r19,96(%r6)
ld %r20,104(%r6)
ld %r21,112(%r6)
ld %r22,120(%r6)
CVS commit: src/lib/libc/arch/powerpc64/gen
Module Name:src Committed By: skrll Date: Wed Oct 11 06:15:57 UTC 2023 Modified Files: src/lib/libc/arch/powerpc64/gen: __setjmp14.S Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/powerpc64/gen/__setjmp14.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/ia64/gen
Module Name:src Committed By: skrll Date: Wed Oct 11 06:15:37 UTC 2023 Modified Files: src/lib/libc/arch/ia64/gen: setjmp.S Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/lib/libc/arch/ia64/gen/setjmp.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/ia64/gen
Module Name:src
Committed By: skrll
Date: Wed Oct 11 06:15:37 UTC 2023
Modified Files:
src/lib/libc/arch/ia64/gen: setjmp.S
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/lib/libc/arch/ia64/gen/setjmp.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/ia64/gen/setjmp.S
diff -u src/lib/libc/arch/ia64/gen/setjmp.S:1.1 src/lib/libc/arch/ia64/gen/setjmp.S:1.2
--- src/lib/libc/arch/ia64/gen/setjmp.S:1.1 Fri Apr 17 12:51:05 2015
+++ src/lib/libc/arch/ia64/gen/setjmp.S Wed Oct 11 06:15:36 2023
@@ -1,21 +1,21 @@
-/* $NetBSD: setjmp.S,v 1.1 2015/04/17 12:51:05 martin Exp $ */
+/* $NetBSD: setjmp.S,v 1.2 2023/10/11 06:15:36 skrll Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
- *
+ *
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
- *
- * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
- * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
+ *
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
+ * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- *
+ *
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or software.distribut...@cs.cmu.edu
@@ -30,7 +30,7 @@
#define _LOCORE
#include
-RCSID("$NetBSD: setjmp.S,v 1.1 2015/04/17 12:51:05 martin Exp $")
+RCSID("$NetBSD: setjmp.S,v 1.2 2023/10/11 06:15:36 skrll Exp $")
#include
@@ -66,7 +66,7 @@ END(__setjmp14)
ENTRY(__longjmp14, 2)
alloc loc0=ar.pfs,2,2,3,0
mov loc1=rp
- ;;
+ ;;
mov out0=3// how = SIG_SETMASK
add out1=J_SIGSET,in0 // set = [J_SIGSET]
mov out2=0// oset = NULL
CVS commit: src/lib/libc/arch
Module Name:src
Committed By: rin
Date: Thu Sep 14 03:58:50 UTC 2023
Modified Files:
src/lib/libc/arch/or1k/gen: Makefile.inc
src/lib/libc/arch/powerpc64/gen: Makefile.inc
src/lib/libc/arch/riscv/gen: Makefile.inc
Log Message:
libc/arch: Fix copy-paste; or1k, powerpc64, riscv are not powerpc ;)
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/lib/libc/arch/or1k/gen/Makefile.inc
cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/powerpc64/gen/Makefile.inc
cvs rdiff -u -r1.2 -r1.3 src/lib/libc/arch/riscv/gen/Makefile.inc
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/or1k/gen/Makefile.inc
diff -u src/lib/libc/arch/or1k/gen/Makefile.inc:1.1 src/lib/libc/arch/or1k/gen/Makefile.inc:1.2
--- src/lib/libc/arch/or1k/gen/Makefile.inc:1.1 Wed Sep 3 19:34:25 2014
+++ src/lib/libc/arch/or1k/gen/Makefile.inc Thu Sep 14 03:58:50 2023
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile.inc,v 1.1 2014/09/03 19:34:25 matt Exp $
+# $NetBSD: Makefile.inc,v 1.2 2023/09/14 03:58:50 rin Exp $
SRCS+= __setjmp14.S __sigsetjmp14.S _setjmp.S
SRCS+= bswap16.c bswap32.c bswap64.c
@@ -23,7 +23,7 @@ SRCS+= fpgetsticky.c fpsetsticky.c
CPPFLAGS._lwp.c += -D_LIBC_SOURCE
-LSRCS.powerpc.gen=Lint_swapcontext.c
-LSRCS+= ${LSRCS.powerpc.gen}
-DPSRCS+= ${LSRCS.powerpc.gen}
-CLEANFILES+= ${LSRCS.powerpc.gen}
+LSRCS.or1k.gen= Lint_swapcontext.c
+LSRCS+= ${LSRCS.or1k.gen}
+DPSRCS+= ${LSRCS.or1k.gen}
+CLEANFILES+= ${LSRCS.or1k.gen}
Index: src/lib/libc/arch/powerpc64/gen/Makefile.inc
diff -u src/lib/libc/arch/powerpc64/gen/Makefile.inc:1.4 src/lib/libc/arch/powerpc64/gen/Makefile.inc:1.5
--- src/lib/libc/arch/powerpc64/gen/Makefile.inc:1.4 Sun Dec 6 07:12:17 2009
+++ src/lib/libc/arch/powerpc64/gen/Makefile.inc Thu Sep 14 03:58:50 2023
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile.inc,v 1.4 2009/12/06 07:12:17 uebayasi Exp $
+# $NetBSD: Makefile.inc,v 1.5 2023/09/14 03:58:50 rin Exp $
SRCS+= __setjmp14.S __sigsetjmp14.S _setjmp.S
SRCS+= bswap16.c bswap32.c bswap64.c
@@ -21,7 +21,7 @@ SRCS+= fpgetround.c fpsetround.c fpgetma
SRCS+= fpgetsticky.c fpsetsticky.c
.endif
-LSRCS.powerpc.gen=Lint_swapcontext.c
-LSRCS+= ${LSRCS.powerpc.gen}
-DPSRCS+= ${LSRCS.powerpc.gen}
-CLEANFILES+= ${LSRCS.powerpc.gen}
+LSRCS.powerpc64.gen= Lint_swapcontext.c
+LSRCS+= ${LSRCS.powerpc64.gen}
+DPSRCS+= ${LSRCS.powerpc64.gen}
+CLEANFILES+= ${LSRCS.powerpc64.gen}
Index: src/lib/libc/arch/riscv/gen/Makefile.inc
diff -u src/lib/libc/arch/riscv/gen/Makefile.inc:1.2 src/lib/libc/arch/riscv/gen/Makefile.inc:1.3
--- src/lib/libc/arch/riscv/gen/Makefile.inc:1.2 Sat Apr 13 17:54:13 2019
+++ src/lib/libc/arch/riscv/gen/Makefile.inc Thu Sep 14 03:58:50 2023
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile.inc,v 1.2 2019/04/13 17:54:13 maya Exp $
+# $NetBSD: Makefile.inc,v 1.3 2023/09/14 03:58:50 rin Exp $
SRCS+= __setjmp14.S __sigsetjmp14.S _setjmp.S
SRCS+= bswap16.c bswap32.c bswap64.c
@@ -23,7 +23,7 @@ SRCS+= fpgetsticky.c fpsetsticky.c
CPPFLAGS._lwp.c += -D_LIBC_SOURCE
-LSRCS.powerpc.gen=Lint_swapcontext.c
-LSRCS+= ${LSRCS.powerpc.gen}
-DPSRCS+= ${LSRCS.powerpc.gen}
-CLEANFILES+= ${LSRCS.powerpc.gen}
+LSRCS.riscv.gen=Lint_swapcontext.c
+LSRCS+= ${LSRCS.riscv.gen}
+DPSRCS+= ${LSRCS.riscv.gen}
+CLEANFILES+= ${LSRCS.riscv.gen}
CVS commit: src/lib/libc/arch
Module Name:src Committed By: rin Date: Thu Sep 14 03:58:50 UTC 2023 Modified Files: src/lib/libc/arch/or1k/gen: Makefile.inc src/lib/libc/arch/powerpc64/gen: Makefile.inc src/lib/libc/arch/riscv/gen: Makefile.inc Log Message: libc/arch: Fix copy-paste; or1k, powerpc64, riscv are not powerpc ;) To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/lib/libc/arch/or1k/gen/Makefile.inc cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/powerpc64/gen/Makefile.inc cvs rdiff -u -r1.2 -r1.3 src/lib/libc/arch/riscv/gen/Makefile.inc Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/sparc
Module Name:src Committed By: mrg Date: Sun Sep 3 21:41:45 UTC 2023 Modified Files: src/lib/libc/arch/sparc: Makefile.inc src/lib/libc/arch/sparc/gen: Makefile.inc longjmp.c setjmp.S Added Files: src/lib/libc/arch/sparc: genassym.cf src/lib/libc/arch/sparc/gen: sparc_longjmp.h Log Message: avoid array-bounds issues by using more complete types. also, don't cast to a type that includes an extra, unused, member. while here, replace the hard coded offsets in setjmp.S and some asserts in longjmp.c with assym.h and shared structures for all the movings parts, and asserts based upon those structures. avoids GCC 12 warnings. To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/lib/libc/arch/sparc/Makefile.inc cvs rdiff -u -r0 -r1.1 src/lib/libc/arch/sparc/genassym.cf cvs rdiff -u -r1.23 -r1.24 src/lib/libc/arch/sparc/gen/Makefile.inc cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/sparc/gen/longjmp.c cvs rdiff -u -r1.12 -r1.13 src/lib/libc/arch/sparc/gen/setjmp.S cvs rdiff -u -r0 -r1.1 src/lib/libc/arch/sparc/gen/sparc_longjmp.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/sparc
Module Name:src
Committed By: mrg
Date: Sun Sep 3 21:41:45 UTC 2023
Modified Files:
src/lib/libc/arch/sparc: Makefile.inc
src/lib/libc/arch/sparc/gen: Makefile.inc longjmp.c setjmp.S
Added Files:
src/lib/libc/arch/sparc: genassym.cf
src/lib/libc/arch/sparc/gen: sparc_longjmp.h
Log Message:
avoid array-bounds issues by using more complete types.
also, don't cast to a type that includes an extra, unused, member.
while here, replace the hard coded offsets in setjmp.S and some
asserts in longjmp.c with assym.h and shared structures for all
the movings parts, and asserts based upon those structures.
avoids GCC 12 warnings.
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/lib/libc/arch/sparc/Makefile.inc
cvs rdiff -u -r0 -r1.1 src/lib/libc/arch/sparc/genassym.cf
cvs rdiff -u -r1.23 -r1.24 src/lib/libc/arch/sparc/gen/Makefile.inc
cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/sparc/gen/longjmp.c
cvs rdiff -u -r1.12 -r1.13 src/lib/libc/arch/sparc/gen/setjmp.S
cvs rdiff -u -r0 -r1.1 src/lib/libc/arch/sparc/gen/sparc_longjmp.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/sparc/Makefile.inc
diff -u src/lib/libc/arch/sparc/Makefile.inc:1.16 src/lib/libc/arch/sparc/Makefile.inc:1.17
--- src/lib/libc/arch/sparc/Makefile.inc:1.16 Sun Oct 31 22:24:35 2021
+++ src/lib/libc/arch/sparc/Makefile.inc Sun Sep 3 21:41:45 2023
@@ -1,7 +1,9 @@
-# $NetBSD: Makefile.inc,v 1.16 2021/10/31 22:24:35 thorpej Exp $
+# $NetBSD: Makefile.inc,v 1.17 2023/09/03 21:41:45 mrg Exp $
SRCS+= __sigtramp2.S
+CPPFLAGS.assym.h+= -I${LIBCDIR}/arch/sparc/gen
+
.if ${MACHINE} != "sparc64"
# `source' files built from m4 source
# the name `div.o' is taken for the ANSI C `div' function, hence sdiv here
Index: src/lib/libc/arch/sparc/gen/Makefile.inc
diff -u src/lib/libc/arch/sparc/gen/Makefile.inc:1.23 src/lib/libc/arch/sparc/gen/Makefile.inc:1.24
--- src/lib/libc/arch/sparc/gen/Makefile.inc:1.23 Sat Jul 12 19:21:48 2014
+++ src/lib/libc/arch/sparc/gen/Makefile.inc Sun Sep 3 21:41:45 2023
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile.inc,v 1.23 2014/07/12 19:21:48 nakayama Exp $
+# $NetBSD: Makefile.inc,v 1.24 2023/09/03 21:41:45 mrg Exp $
SRCS+= fabs.S modf.S
SRCS+= flt_rounds.c fpgetmask.c fpgetround.c fpgetsticky.c fpsetmask.c \
@@ -29,6 +29,9 @@ SRCS+= mul.S umul.S
SRCS+= fixunsdfsi.S saveregs.S
SRCS+= bswap16.c bswap32.c bswap64.c
+CPPFLAGS.setjmp.S+= -I.
+CPPFLAGS.longjmp.c+= -I.
+
LSRCS.sparc.gen= Lint_swapcontext.c
LSRCS+= ${LSRCS.sparc.gen}
DPSRCS+= ${LSRCS.sparc.gen}
Index: src/lib/libc/arch/sparc/gen/longjmp.c
diff -u src/lib/libc/arch/sparc/gen/longjmp.c:1.3 src/lib/libc/arch/sparc/gen/longjmp.c:1.4
--- src/lib/libc/arch/sparc/gen/longjmp.c:1.3 Sat Apr 30 23:41:12 2011
+++ src/lib/libc/arch/sparc/gen/longjmp.c Sun Sep 3 21:41:45 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: longjmp.c,v 1.3 2011/04/30 23:41:12 martin Exp $ */
+/* $NetBSD: longjmp.c,v 1.4 2023/09/03 21:41:45 mrg Exp $ */
/*-
* Copyright (c) 2003 The NetBSD Foundation, Inc.
@@ -41,20 +41,17 @@
#include
#include
-struct __jmp_buf_regs_t {
- __greg_t g4;
- __greg_t g7;
- __greg_t save_mask;
-};
+#include "assym.h"
+#include "sparc_longjmp.h"
/*
- * setjmp.S uses hard coded offsets into the jump_buf,
- * make sure any changes cause a compile failure here
+ * check that offsets in the above structures match their usage in the
+ * setjmp() side of this setup. a jmp_buf is the 12-word contents of
+ * the sigcontexst structure, plus 2 more words for g4 and g7.
*/
-__CTASSERT(56 == offsetof(struct __jmp_buf_regs_t,save_mask) +
- sizeof(struct sigcontext));
-__CTASSERT(sizeof(sigjmp_buf) >= sizeof(struct __jmp_buf_regs_t) +
- sizeof(struct sigcontext));
+__CTASSERT(_SIZEOF_SC + _JB_G4 == offsetof(struct __jmp_buf,regs.g4));
+__CTASSERT(_SIZEOF_SC + _JB_G7 == offsetof(struct __jmp_buf,regs.g7));
+__CTASSERT(sizeof(jmp_buf) >= sizeof(struct __jmp_buf));
/*
* Use setcontext to reload the stack pointer, program counter , and
@@ -64,8 +61,9 @@ __CTASSERT(sizeof(sigjmp_buf) >= sizeof(
void
__longjmp14(jmp_buf env, int val)
{
- struct sigcontext *sc = (void *)env;
- struct __jmp_buf_regs_t *r = (void*)[1];
+ struct __jmp_buf *context = (void *)env;
+ struct sigcontext *sc = >sc;
+ struct __jmp_buf_regs_t *r = >regs;
ucontext_t uc;
/* Ensure non-zero SP */
Index: src/lib/libc/arch/sparc/gen/setjmp.S
diff -u src/lib/libc/arch/sparc/gen/setjmp.S:1.12 src/lib/libc/arch/sparc/gen/setjmp.S:1.13
--- src/lib/libc/arch/sparc/gen/setjmp.S:1.12 Sat Apr 30 23:41:13 2011
+++ src/lib/libc/arch/sparc/gen/setjmp.S Sun Sep 3 21:41:45 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: setjmp.S,v 1.12 2011/04/30 23:41:13 martin Exp $ */
+/* $NetBSD: setjmp.S,v 1.13 2023/09/03 21:41:45 mrg Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -40,7 +40,7 @@
#if 0
.asciz "@(#)setjmp.s 8.1 (Berkeley) 6/4/93"
#else
-
CVS commit: src/lib/libc/arch
Module Name:src Committed By: skrll Date: Sun Jul 23 07:25:04 UTC 2023 Modified Files: src/lib/libc/arch/aarch64: SYS.h src/lib/libc/arch/arm: SYS.h Log Message: ENTRY / END indentation. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/aarch64/SYS.h cvs rdiff -u -r1.15 -r1.16 src/lib/libc/arch/arm/SYS.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch
Module Name:src Committed By: skrll Date: Sun Jul 23 07:25:04 UTC 2023 Modified Files: src/lib/libc/arch/aarch64: SYS.h src/lib/libc/arch/arm: SYS.h Log Message: ENTRY / END indentation. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/aarch64/SYS.h cvs rdiff -u -r1.15 -r1.16 src/lib/libc/arch/arm/SYS.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/lib/libc/arch/aarch64/SYS.h diff -u src/lib/libc/arch/aarch64/SYS.h:1.3 src/lib/libc/arch/aarch64/SYS.h:1.4 --- src/lib/libc/arch/aarch64/SYS.h:1.3 Sat Mar 9 02:50:07 2019 +++ src/lib/libc/arch/aarch64/SYS.h Sun Jul 23 07:25:04 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: SYS.h,v 1.3 2019/03/09 02:50:07 christos Exp $ */ +/* $NetBSD: SYS.h,v 1.4 2023/07/23 07:25:04 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -39,7 +39,7 @@ #define SYSTRAP(x) svc #(SYS_ ## x) #define _SYSCALL_NOERROR(x,y) \ - ENTRY(x); \ +ENTRY(x);\ SYSTRAP(y) #define _INVOKE_CERROR() \ @@ -60,12 +60,12 @@ #define PSEUDO_NOERROR(x,y) \ _SYSCALL_NOERROR(x,y); \ ret;\ - END(x) +END(x) #define PSEUDO(x,y) \ _SYSCALL(x,y); \ ret;\ - END(x) +END(x) #define RSYSCALL_NOERROR(x) \ PSEUDO_NOERROR(x,x) Index: src/lib/libc/arch/arm/SYS.h diff -u src/lib/libc/arch/arm/SYS.h:1.15 src/lib/libc/arch/arm/SYS.h:1.16 --- src/lib/libc/arch/arm/SYS.h:1.15 Mon Aug 19 22:13:34 2013 +++ src/lib/libc/arch/arm/SYS.h Sun Jul 23 07:25:04 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: SYS.h,v 1.15 2013/08/19 22:13:34 matt Exp $ */ +/* $NetBSD: SYS.h,v 1.16 2023/07/23 07:25:04 skrll Exp $ */ /*- * Copyright (c) 1990 The Regents of the University of California. @@ -79,7 +79,7 @@ #define CURBRK _C_LABEL(__curbrk) #define _SYSCALL_NOERROR(x,y) \ - ENTRY(x); \ +ENTRY(x);\ SYSTRAP(y) #if !defined(__thumb__) || defined(_ARM_ARCH_T2) @@ -102,12 +102,12 @@ #define PSEUDO_NOERROR(x,y) \ _SYSCALL_NOERROR(x,y); \ RET;\ - END(x) +END(x) #define PSEUDO(x,y) \ _SYSCALL(x,y); \ RET;\ - END(x) +END(x) #define RSYSCALL_NOERROR(x) \
CVS commit: src/lib/libc/arch/mips
Module Name:src Committed By: skrll Date: Sun Jul 23 07:24:20 UTC 2023 Modified Files: src/lib/libc/arch/mips: SYS.h Log Message: Indentation consistency. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/lib/libc/arch/mips/SYS.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/lib/libc/arch/mips/SYS.h diff -u src/lib/libc/arch/mips/SYS.h:1.20 src/lib/libc/arch/mips/SYS.h:1.21 --- src/lib/libc/arch/mips/SYS.h:1.20 Sat Feb 25 21:16:50 2017 +++ src/lib/libc/arch/mips/SYS.h Sun Jul 23 07:24:20 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: SYS.h,v 1.20 2017/02/25 21:16:50 joerg Exp $ */ +/* $NetBSD: SYS.h,v 1.21 2023/07/23 07:24:20 skrll Exp $ */ /*- * Copyright (c) 1996 Jonathan Stone @@ -128,7 +128,7 @@ LEAF(x);\ SYSTRAP(y); \ j ra;\ - END(x) +END(x) #define PSEUDO(x,y) \ LEAF(x);\
CVS commit: src/lib/libc/arch/mips
Module Name:src Committed By: skrll Date: Sun Jul 23 07:24:20 UTC 2023 Modified Files: src/lib/libc/arch/mips: SYS.h Log Message: Indentation consistency. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/lib/libc/arch/mips/SYS.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/riscv
Module Name:src Committed By: skrll Date: Fri May 19 06:41:41 UTC 2023 Modified Files: src/lib/libc/arch/riscv: SYS.h Log Message: No need for double semi-colon Indent END the same as ENTRY. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/riscv/SYS.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/lib/libc/arch/riscv/SYS.h diff -u src/lib/libc/arch/riscv/SYS.h:1.4 src/lib/libc/arch/riscv/SYS.h:1.5 --- src/lib/libc/arch/riscv/SYS.h:1.4 Sun May 7 12:41:47 2023 +++ src/lib/libc/arch/riscv/SYS.h Fri May 19 06:41:41 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: SYS.h,v 1.4 2023/05/07 12:41:47 skrll Exp $ */ +/* $NetBSD: SYS.h,v 1.5 2023/05/19 06:41:41 skrll Exp $ */ /*- * Copyright (c) 2014,2022 The NetBSD Foundation, Inc. @@ -71,14 +71,14 @@ * and syscall name are not the same. */ #define PSEUDO_NOERROR(x,y) \ -ENTRY(x);;\ +ENTRY(x);\ SYSTRAP_NOERROR(y) ;\ ret /* success */;\ - END(x) +END(x) #define PSEUDO(x,y) \ -ENTRY(x);;\ +ENTRY(x);\ SYSTRAP(y) ;\ JUMP_TO_CERROR() /* error */;\ ret /* success */;\ - END(x) +END(x)
CVS commit: src/lib/libc/arch/riscv
Module Name:src Committed By: skrll Date: Fri May 19 06:41:41 UTC 2023 Modified Files: src/lib/libc/arch/riscv: SYS.h Log Message: No need for double semi-colon Indent END the same as ENTRY. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/riscv/SYS.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/riscv
Module Name:src Committed By: skrll Date: Fri May 19 06:31:01 UTC 2023 Modified Files: src/lib/libc/arch/riscv: genassym.cf Log Message: KNF To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/lib/libc/arch/riscv/genassym.cf Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/lib/libc/arch/riscv/genassym.cf diff -u src/lib/libc/arch/riscv/genassym.cf:1.2 src/lib/libc/arch/riscv/genassym.cf:1.3 --- src/lib/libc/arch/riscv/genassym.cf:1.2 Fri Mar 27 23:22:20 2015 +++ src/lib/libc/arch/riscv/genassym.cf Fri May 19 06:31:01 2023 @@ -1,4 +1,4 @@ -# $NetBSD: genassym.cf,v 1.2 2015/03/27 23:22:20 matt Exp $ +# $NetBSD: genassym.cf,v 1.3 2023/05/19 06:31:01 skrll Exp $ # # Copyright (c) 2001 The NetBSD Foundation, Inc. @@ -30,8 +30,8 @@ # include -include include +include include include
CVS commit: src/lib/libc/arch/riscv
Module Name:src Committed By: skrll Date: Fri May 19 06:31:01 UTC 2023 Modified Files: src/lib/libc/arch/riscv: genassym.cf Log Message: KNF To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/lib/libc/arch/riscv/genassym.cf Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch
Module Name:src
Committed By: skrll
Date: Sun Apr 2 07:26:18 UTC 2023
Modified Files:
src/lib/libc/arch/i386/gen: _lwp.c
src/lib/libc/arch/m68k/gen: _lwp.c
src/lib/libc/arch/vax/gen: _lwp.c
src/lib/libc/arch/x86_64/gen: _lwp.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/lib/libc/arch/i386/gen/_lwp.c
cvs rdiff -u -r1.8 -r1.9 src/lib/libc/arch/m68k/gen/_lwp.c
cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/vax/gen/_lwp.c
cvs rdiff -u -r1.7 -r1.8 src/lib/libc/arch/x86_64/gen/_lwp.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/i386/gen/_lwp.c
diff -u src/lib/libc/arch/i386/gen/_lwp.c:1.8 src/lib/libc/arch/i386/gen/_lwp.c:1.9
--- src/lib/libc/arch/i386/gen/_lwp.c:1.8 Fri Aug 31 20:57:24 2012
+++ src/lib/libc/arch/i386/gen/_lwp.c Sun Apr 2 07:26:17 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: _lwp.c,v 1.8 2012/08/31 20:57:24 drochner Exp $ */
+/* $NetBSD: _lwp.c,v 1.9 2023/04/02 07:26:17 skrll Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
#if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: _lwp.c,v 1.8 2012/08/31 20:57:24 drochner Exp $");
+__RCSID("$NetBSD: _lwp.c,v 1.9 2023/04/02 07:26:17 skrll Exp $");
#endif /* LIBC_SCCS and not lint */
#include "namespace.h"
@@ -55,14 +55,14 @@ _lwp_makecontext(ucontext_t *u, void (*s
/* LINTED uintptr_t is safe */
u->uc_mcontext.__gregs[_REG_EIP] = (uintptr_t)start;
-
+
/* Align to a 16-byte boundary for SSE */
/* LINTED uintptr_t is safe */
sp = (void **) (((uintptr_t)(stack_base + stack_size - 4) & ~0xf) + 4);
-
+
*--sp = arg;
*--sp = (void *) _lwp_exit;
-
+
/* LINTED uintptr_t is safe */
u->uc_mcontext.__gregs[_REG_UESP] = (uintptr_t) sp;
Index: src/lib/libc/arch/m68k/gen/_lwp.c
diff -u src/lib/libc/arch/m68k/gen/_lwp.c:1.8 src/lib/libc/arch/m68k/gen/_lwp.c:1.9
--- src/lib/libc/arch/m68k/gen/_lwp.c:1.8 Sun Mar 18 16:26:34 2012
+++ src/lib/libc/arch/m68k/gen/_lwp.c Sun Apr 2 07:26:17 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: _lwp.c,v 1.8 2012/03/18 16:26:34 christos Exp $ */
+/* $NetBSD: _lwp.c,v 1.9 2023/04/02 07:26:17 skrll Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
#if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: _lwp.c,v 1.8 2012/03/18 16:26:34 christos Exp $");
+__RCSID("$NetBSD: _lwp.c,v 1.9 2023/04/02 07:26:17 skrll Exp $");
#endif /* LIBC_SCCS and not lint */
#include "namespace.h"
@@ -54,9 +54,9 @@ _lwp_makecontext(ucontext_t *u, void (*s
u->uc_stack.ss_size = stack_size;
u->uc_mcontext.__gregs[_REG_PC] = (int)start;
-
+
sp = (void **)(void *)(stack_base + stack_size);
-
+
*--sp = arg;
*--sp = (void *) _lwp_exit;
Index: src/lib/libc/arch/vax/gen/_lwp.c
diff -u src/lib/libc/arch/vax/gen/_lwp.c:1.3 src/lib/libc/arch/vax/gen/_lwp.c:1.4
--- src/lib/libc/arch/vax/gen/_lwp.c:1.3 Thu Mar 22 17:32:22 2012
+++ src/lib/libc/arch/vax/gen/_lwp.c Sun Apr 2 07:26:18 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: _lwp.c,v 1.3 2012/03/22 17:32:22 christos Exp $ */
+/* $NetBSD: _lwp.c,v 1.4 2023/04/02 07:26:18 skrll Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
#if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: _lwp.c,v 1.3 2012/03/22 17:32:22 christos Exp $");
+__RCSID("$NetBSD: _lwp.c,v 1.4 2023/04/02 07:26:18 skrll Exp $");
#endif /* LIBC_SCCS and not lint */
#include "namespace.h"
@@ -57,7 +57,7 @@ _lwp_makecontext(ucontext_t *u, void (*s
/* Align to a word */
/* LINTED uintptr_t is safe */
sp = (int *)((uintptr_t)(stack_base + stack_size) & ~0x3);
-
+
/*
* Allocate necessary stack space for arguments including arg count
* and call frame
@@ -71,7 +71,7 @@ _lwp_makecontext(ucontext_t *u, void (*s
sp[4] = (int)(uintptr_t)_lwp_exit + 2;/* return via _lwp_exit */
sp[5] = 1; /* argc */
sp[6] = (int)(uintptr_t)arg; /* argv */
-
+
gr[_REG_AP] = (__greg_t)(uintptr_t)(sp + 5);
gr[_REG_SP] = (__greg_t)(uintptr_t)sp;
gr[_REG_FP] = (__greg_t)(uintptr_t)sp;
Index: src/lib/libc/arch/x86_64/gen/_lwp.c
diff -u src/lib/libc/arch/x86_64/gen/_lwp.c:1.7 src/lib/libc/arch/x86_64/gen/_lwp.c:1.8
--- src/lib/libc/arch/x86_64/gen/_lwp.c:1.7 Thu Feb 24 04:28:43 2011
+++ src/lib/libc/arch/x86_64/gen/_lwp.c Sun Apr 2 07:26:18 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: _lwp.c,v 1.7 2011/02/24 04:28:43 joerg Exp $ */
+/* $NetBSD: _lwp.c,v 1.8 2023/04/02 07:26:18 skrll Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
#if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: _lwp.c,v 1.7 2011/02/24 04:28:43 joerg Exp $");
+__RCSID("$NetBSD: _lwp.c,v 1.8 2023/04/02 07:26:18 skrll Exp $");
#endif /* LIBC_SCCS and not lint */
#include "namespace.h"
@@ -56,13 +56,13 @@ _lwp_makecontext(ucontext_t *u, void (*s
CVS commit: src/lib/libc/arch
Module Name:src Committed By: skrll Date: Sun Apr 2 07:26:18 UTC 2023 Modified Files: src/lib/libc/arch/i386/gen: _lwp.c src/lib/libc/arch/m68k/gen: _lwp.c src/lib/libc/arch/vax/gen: _lwp.c src/lib/libc/arch/x86_64/gen: _lwp.c Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/lib/libc/arch/i386/gen/_lwp.c cvs rdiff -u -r1.8 -r1.9 src/lib/libc/arch/m68k/gen/_lwp.c cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/vax/gen/_lwp.c cvs rdiff -u -r1.7 -r1.8 src/lib/libc/arch/x86_64/gen/_lwp.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/arm/gen
Module Name:src Committed By: skrll Date: Tue Dec 13 12:43:32 UTC 2022 Modified Files: src/lib/libc/arch/arm/gen: setjmp.S Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.18 src/lib/libc/arch/arm/gen/setjmp.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/lib/libc/arch/arm/gen/setjmp.S diff -u src/lib/libc/arch/arm/gen/setjmp.S:1.17 src/lib/libc/arch/arm/gen/setjmp.S:1.18 --- src/lib/libc/arch/arm/gen/setjmp.S:1.17 Sat Nov 30 20:20:42 2013 +++ src/lib/libc/arch/arm/gen/setjmp.S Tue Dec 13 12:43:32 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: setjmp.S,v 1.17 2013/11/30 20:20:42 joerg Exp $ */ +/* $NetBSD: setjmp.S,v 1.18 2022/12/13 12:43:32 skrll Exp $ */ /* * Copyright (c) 1997 Mark Brinicombe @@ -136,7 +136,7 @@ ENTRY(__longjmp14) mov ip, r3 ldr r3, [r0] movs r2, #(_JB_MAGIC_SETJMP ^ _JB_MAGIC_SETJMP_VFP) - bics r3, r2 + bics r3, r2 /* r2 is not the magic but we don't need it since we can't do VFP */ #endif cmp r3, ip
CVS commit: src/lib/libc/arch/arm/gen
Module Name:src Committed By: skrll Date: Tue Dec 13 12:43:32 UTC 2022 Modified Files: src/lib/libc/arch/arm/gen: setjmp.S Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.18 src/lib/libc/arch/arm/gen/setjmp.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/mips/sys
Module Name:src
Committed By: skrll
Date: Sat Dec 3 14:04:39 UTC 2022
Modified Files:
src/lib/libc/arch/mips/sys: cerror.S
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/lib/libc/arch/mips/sys/cerror.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/mips/sys/cerror.S
diff -u src/lib/libc/arch/mips/sys/cerror.S:1.20 src/lib/libc/arch/mips/sys/cerror.S:1.21
--- src/lib/libc/arch/mips/sys/cerror.S:1.20 Sat Feb 6 06:58:59 2021
+++ src/lib/libc/arch/mips/sys/cerror.S Sat Dec 3 14:04:39 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cerror.S,v 1.20 2021/02/06 06:58:59 simonb Exp $ */
+/* $NetBSD: cerror.S,v 1.21 2022/12/03 14:04:39 skrll Exp $ */
/*-
* Copyright (c) 1991, 1993
@@ -38,7 +38,7 @@
#if 0
RCSID("from: @(#)cerror.s 8.1 (Berkeley) 6/16/93")
#else
- RCSID("$NetBSD: cerror.S,v 1.20 2021/02/06 06:58:59 simonb Exp $")
+ RCSID("$NetBSD: cerror.S,v 1.21 2022/12/03 14:04:39 skrll Exp $")
#endif
#endif /* LIBC_SCCS and not lint */
@@ -78,7 +78,7 @@ NESTED_NOPROFILE(__cerror, CALLFRAME_SIZ
# on the stack and not in the t3 reg (for the n32/n64 case).
j ra
END(__cerror)
-#else
+#else
.globl _C_LABEL(errno)
LEAF_NOPROFILE(__cerror)
PIC_PROLOGUE(__cerror)
CVS commit: src/lib/libc/arch/mips/sys
Module Name:src Committed By: skrll Date: Sat Dec 3 14:04:39 UTC 2022 Modified Files: src/lib/libc/arch/mips/sys: cerror.S Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/lib/libc/arch/mips/sys/cerror.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/riscv
Module Name:src
Committed By: skrll
Date: Sat Dec 3 09:38:53 UTC 2022
Modified Files:
src/lib/libc/arch/riscv/gdtoa: gd_qnan.h
src/lib/libc/arch/riscv/gen: fpgetmask.c fpgetround.c fpgetsticky.c
fpsetmask.c fpsetround.c fpsetsticky.c resumecontext.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/lib/libc/arch/riscv/gdtoa/gd_qnan.h
cvs rdiff -u -r1.1 -r1.2 src/lib/libc/arch/riscv/gen/fpgetmask.c \
src/lib/libc/arch/riscv/gen/fpgetround.c \
src/lib/libc/arch/riscv/gen/fpgetsticky.c \
src/lib/libc/arch/riscv/gen/fpsetmask.c \
src/lib/libc/arch/riscv/gen/fpsetround.c \
src/lib/libc/arch/riscv/gen/fpsetsticky.c \
src/lib/libc/arch/riscv/gen/resumecontext.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/riscv/gdtoa/gd_qnan.h
diff -u src/lib/libc/arch/riscv/gdtoa/gd_qnan.h:1.2 src/lib/libc/arch/riscv/gdtoa/gd_qnan.h:1.3
--- src/lib/libc/arch/riscv/gdtoa/gd_qnan.h:1.2 Sun Apr 14 19:25:27 2019
+++ src/lib/libc/arch/riscv/gdtoa/gd_qnan.h Sat Dec 3 09:38:53 2022
@@ -1,6 +1,6 @@
-/* $NetBSD: gd_qnan.h,v 1.2 2019/04/14 19:25:27 maya Exp $ */
+/* $NetBSD: gd_qnan.h,v 1.3 2022/12/03 09:38:53 skrll Exp $ */
-/*
+/*
* The RISC-V Instruction Set Manual Volume I: User-Level ISA
* Document Version 2.2
*
Index: src/lib/libc/arch/riscv/gen/fpgetmask.c
diff -u src/lib/libc/arch/riscv/gen/fpgetmask.c:1.1 src/lib/libc/arch/riscv/gen/fpgetmask.c:1.2
--- src/lib/libc/arch/riscv/gen/fpgetmask.c:1.1 Fri Sep 19 17:36:25 2014
+++ src/lib/libc/arch/riscv/gen/fpgetmask.c Sat Dec 3 09:38:53 2022
@@ -1,12 +1,12 @@
-/* $NetBSD: fpgetmask.c,v 1.1 2014/09/19 17:36:25 matt Exp $ */
+/* $NetBSD: fpgetmask.c,v 1.2 2022/12/03 09:38:53 skrll Exp $ */
/*
* Copyright (c) 1999 The NetBSD Foundation, Inc.
* All rights reserved.
- *
+ *
* This code is derived from software contributed to The NetBSD Foundation
* by Dan Winship.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -15,7 +15,7 @@
* 2. Redistributions in binary form must reproduce the above copyright
*notice, this list of conditions and the following disclaimer in the
*documentation and/or other materials provided with the distribution.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
@@ -31,7 +31,7 @@
#include
#if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: fpgetmask.c,v 1.1 2014/09/19 17:36:25 matt Exp $");
+__RCSID("$NetBSD: fpgetmask.c,v 1.2 2022/12/03 09:38:53 skrll Exp $");
#endif /* LIBC_SCCS and not lint */
#include "namespace.h"
Index: src/lib/libc/arch/riscv/gen/fpgetround.c
diff -u src/lib/libc/arch/riscv/gen/fpgetround.c:1.1 src/lib/libc/arch/riscv/gen/fpgetround.c:1.2
--- src/lib/libc/arch/riscv/gen/fpgetround.c:1.1 Fri Sep 19 17:36:25 2014
+++ src/lib/libc/arch/riscv/gen/fpgetround.c Sat Dec 3 09:38:53 2022
@@ -1,12 +1,12 @@
-/* $NetBSD: fpgetround.c,v 1.1 2014/09/19 17:36:25 matt Exp $ */
+/* $NetBSD: fpgetround.c,v 1.2 2022/12/03 09:38:53 skrll Exp $ */
/*
* Copyright (c) 1999 The NetBSD Foundation, Inc.
* All rights reserved.
- *
+ *
* This code is derived from software contributed to The NetBSD Foundation
* by Dan Winship.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -15,7 +15,7 @@
* 2. Redistributions in binary form must reproduce the above copyright
*notice, this list of conditions and the following disclaimer in the
*documentation and/or other materials provided with the distribution.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
@@ -31,7 +31,7 @@
#include
#if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: fpgetround.c,v 1.1 2014/09/19 17:36:25 matt Exp $");
+__RCSID("$NetBSD: fpgetround.c,v 1.2 2022/12/03 09:38:53 skrll Exp $");
#endif /* LIBC_SCCS and not lint */
#include "namespace.h"
Index: src/lib/libc/arch/riscv/gen/fpgetsticky.c
diff -u src/lib/libc/arch/riscv/gen/fpgetsticky.c:1.1 src/lib/libc/arch/riscv/gen/fpgetsticky.c:1.2
--- src/lib/libc/arch/riscv/gen/fpgetsticky.c:1.1 Fri Sep 19 17:36:25 2014
+++ src/lib/libc/arch/riscv/gen/fpgetsticky.c Sat Dec 3 09:38:53 2022
@@ -1,12 +1,12 @@
-/* $NetBSD: fpgetsticky.c,v 1.1 2014/09/19 17:36:25 matt Exp $ */
+/* $NetBSD: fpgetsticky.c,v 1.2 2022/12/03 09:38:53 skrll
CVS commit: src/lib/libc/arch/riscv
Module Name:src Committed By: skrll Date: Sat Dec 3 09:38:53 UTC 2022 Modified Files: src/lib/libc/arch/riscv/gdtoa: gd_qnan.h src/lib/libc/arch/riscv/gen: fpgetmask.c fpgetround.c fpgetsticky.c fpsetmask.c fpsetround.c fpsetsticky.c resumecontext.c Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/lib/libc/arch/riscv/gdtoa/gd_qnan.h cvs rdiff -u -r1.1 -r1.2 src/lib/libc/arch/riscv/gen/fpgetmask.c \ src/lib/libc/arch/riscv/gen/fpgetround.c \ src/lib/libc/arch/riscv/gen/fpgetsticky.c \ src/lib/libc/arch/riscv/gen/fpsetmask.c \ src/lib/libc/arch/riscv/gen/fpsetround.c \ src/lib/libc/arch/riscv/gen/fpsetsticky.c \ src/lib/libc/arch/riscv/gen/resumecontext.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/hppa/sys
Module Name:src Committed By: skrll Date: Mon Jun 6 06:32:44 UTC 2022 Modified Files: src/lib/libc/arch/hppa/sys: ptrace.S Log Message: Save and restore %r19 the "linkage table pointer register" across the call to __cerror so if the ptrace syscall fails we can call __cerror again with the correct %r19 value. Do this even though the call of __cerror doesn't go via the PLT because __cerror calls __errno which does. Analysis and fix from Tom Lane in port-hppa/56864: hppa: ptrace(2) dumps core when returning an error I changed the location of where %r19 is stored on the stack to follow the ABI. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/lib/libc/arch/hppa/sys/ptrace.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/lib/libc/arch/hppa/sys/ptrace.S diff -u src/lib/libc/arch/hppa/sys/ptrace.S:1.7 src/lib/libc/arch/hppa/sys/ptrace.S:1.8 --- src/lib/libc/arch/hppa/sys/ptrace.S:1.7 Sat May 9 08:25:33 2020 +++ src/lib/libc/arch/hppa/sys/ptrace.S Mon Jun 6 06:32:44 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: ptrace.S,v 1.7 2020/05/09 08:25:33 skrll Exp $ */ +/* $NetBSD: ptrace.S,v 1.8 2022/06/06 06:32:44 skrll Exp $ */ /*- * Copyright (c) 2001 The NetBSD Foundation, Inc. @@ -42,10 +42,12 @@ ENTRY(ptrace, HPPA_FRAME_SIZE) stw %arg1, HPPA_FRAME_ARG(1)(%sp) stw %arg2, HPPA_FRAME_ARG(2)(%sp) stw %arg3, HPPA_FRAME_ARG(3)(%sp) + stw %r19, HPPA_FRAME_EDP(%sp) ldo HPPA_FRAME_SIZE(%sp),%sp bl __cerror, %rp copy %r0, %t1 ldo -HPPA_FRAME_SIZE(%sp), %sp + ldw HPPA_FRAME_EDP(%sp), %r19 ldw HPPA_FRAME_ARG(0)(%sp), %arg0 ldw HPPA_FRAME_ARG(1)(%sp), %arg1 ldw HPPA_FRAME_ARG(2)(%sp), %arg2
CVS commit: src/lib/libc/arch/powerpc/string
Module Name:src Committed By: rin Date: Mon May 30 14:43:37 UTC 2022 Modified Files: src/lib/libc/arch/powerpc/string: Makefile.inc Log Message: Obsolete hack for evbppc to replace memcmp(9), memcpy(9), and memmove(9) with strictly-aligned versions. Now all 32-bit powerpc ports share the same libc binary. This change together with the preceding similar change in libkern slightly improve performance for DHT (ibm4xx/405GP) and RB800 (MPC8533E). See changes in bytebench scores: - DHT https://gist.github.com/rokuyama/301063355de9733bea515b84ef574c0a - RB800 https://gist.github.com/rokuyama/60ad665d367d6d110b79ec44707f39ff Improvements may be negligible, but this does not cause performance regressions at least. This hack was for 403, but unaligned memory access is now emulated by kernel. This should result in serious performance regression for 403. We will provide strictly-aligned versions by ld.so.conf. To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/lib/libc/arch/powerpc/string/Makefile.inc Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/powerpc/string
Module Name:src
Committed By: rin
Date: Mon May 30 14:43:37 UTC 2022
Modified Files:
src/lib/libc/arch/powerpc/string: Makefile.inc
Log Message:
Obsolete hack for evbppc to replace memcmp(9), memcpy(9), and memmove(9)
with strictly-aligned versions.
Now all 32-bit powerpc ports share the same libc binary.
This change together with the preceding similar change in libkern slightly
improve performance for DHT (ibm4xx/405GP) and RB800 (MPC8533E).
See changes in bytebench scores:
- DHT https://gist.github.com/rokuyama/301063355de9733bea515b84ef574c0a
- RB800 https://gist.github.com/rokuyama/60ad665d367d6d110b79ec44707f39ff
Improvements may be negligible, but this does not cause performance
regressions at least.
This hack was for 403, but unaligned memory access is now emulated by
kernel. This should result in serious performance regression for 403.
We will provide strictly-aligned versions by ld.so.conf.
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/lib/libc/arch/powerpc/string/Makefile.inc
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/powerpc/string/Makefile.inc
diff -u src/lib/libc/arch/powerpc/string/Makefile.inc:1.15 src/lib/libc/arch/powerpc/string/Makefile.inc:1.16
--- src/lib/libc/arch/powerpc/string/Makefile.inc:1.15 Mon Jul 26 12:49:13 2021
+++ src/lib/libc/arch/powerpc/string/Makefile.inc Mon May 30 14:43:37 2022
@@ -1,16 +1,7 @@
-# $NetBSD: Makefile.inc,v 1.15 2021/07/26 12:49:13 rin Exp $
+# $NetBSD: Makefile.inc,v 1.16 2022/05/30 14:43:37 rin Exp $
SRCS+= bzero.S ffs.S strlen.S
NO_SRCS+= memset.S
-# XXX
-# Disable asm versions that use unaligned memory access and thus break 403.
-.if ${MACHINE} == "evbppc"
-. for name in bcopy memcmp memcpy memmove
-.for suffix in o po pico go d
-${name}.${suffix}: ${name}.c
-.endfor
-. endfor
-.else
+# with unaligned memory access
SRCS+= memcmp.S bcopy.S memcpy.S memmove.S
-.endif
CVS commit: src/lib/libc/arch
Module Name:src
Committed By: skrll
Date: Sat Nov 27 10:00:01 UTC 2021
Modified Files:
src/lib/libc/arch/arm/sys: __sigtramp2.S
src/lib/libc/arch/powerpc/sys: __sigtramp2.S
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/arm/sys/__sigtramp2.S
cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/powerpc/sys/__sigtramp2.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/arm/sys/__sigtramp2.S
diff -u src/lib/libc/arch/arm/sys/__sigtramp2.S:1.4 src/lib/libc/arch/arm/sys/__sigtramp2.S:1.5
--- src/lib/libc/arch/arm/sys/__sigtramp2.S:1.4 Tue Nov 23 18:45:53 2021
+++ src/lib/libc/arch/arm/sys/__sigtramp2.S Sat Nov 27 10:00:01 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: __sigtramp2.S,v 1.4 2021/11/23 18:45:53 thorpej Exp $ */
+/* $NetBSD: __sigtramp2.S,v 1.5 2021/11/27 10:00:01 skrll Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
@@ -67,12 +67,12 @@
.cfi_return_column _REG_R15
CFI_OFFSET(_REG_R15) /* a.k.a. _REG_PC */
-/*
+/*
* The unwind entry includes the one instruction prior to the trampoline
* because the unwinder will look up (return PC - 1) while unwinding.
* Normally this would be the jump / branch, but since there isn't one in
* this case, we place an explicit nop there instead.
- */
+ */
nop
ENTRY_NP(__sigtramp_siginfo_2)
Index: src/lib/libc/arch/powerpc/sys/__sigtramp2.S
diff -u src/lib/libc/arch/powerpc/sys/__sigtramp2.S:1.4 src/lib/libc/arch/powerpc/sys/__sigtramp2.S:1.5
--- src/lib/libc/arch/powerpc/sys/__sigtramp2.S:1.4 Sun Nov 21 21:31:24 2021
+++ src/lib/libc/arch/powerpc/sys/__sigtramp2.S Sat Nov 27 10:00:01 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: __sigtramp2.S,v 1.4 2021/11/21 21:31:24 thorpej Exp $ */
+/* $NetBSD: __sigtramp2.S,v 1.5 2021/11/27 10:00:01 skrll Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
#include "assym.h"
#if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: __sigtramp2.S,v 1.4 2021/11/21 21:31:24 thorpej Exp $")
+__RCSID("$NetBSD: __sigtramp2.S,v 1.5 2021/11/27 10:00:01 skrll Exp $")
#endif /* LIBC_SCCS && !lint */
/*
@@ -115,12 +115,12 @@ __RCSID("$NetBSD: __sigtramp2.S,v 1.4 20
.cfi_return_column DWARF_SIGRETURN_REG
CFI_OFFSET_DWARF_REG(DWARF_SIGRETURN_REG, _REG_PC)
-/*
+/*
* The unwind entry includes one instruction slot prior to the trampoline
* because the unwinder will look up to (return PC - 1 insn) while unwinding.
* Normally this would be the jump / branch, but since there isn't one in
* this case, we place an explicit nop there instead.
- */
+ */
nop
ENTRY_NOPROFILE(__sigtramp_siginfo_2)
CVS commit: src/lib/libc/arch
Module Name:src Committed By: skrll Date: Sat Nov 27 10:00:01 UTC 2021 Modified Files: src/lib/libc/arch/arm/sys: __sigtramp2.S src/lib/libc/arch/powerpc/sys: __sigtramp2.S Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/arm/sys/__sigtramp2.S cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/powerpc/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/vax
Module Name:src
Committed By: thorpej
Date: Wed Nov 24 15:05:16 UTC 2021
Modified Files:
src/lib/libc/arch/vax: genassym.cf
src/lib/libc/arch/vax/sys: __sigtramp3.S
Log Message:
Decorate the VAX signal trampoline with the appropriate .cfi
directives to allow exception unwind / backtrace across a signal
handler.
N.B. This is currently disabled, as these .cfi directives cause
linker warnings about incompatible TEXTREL relocations in .eh_frame.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/lib/libc/arch/vax/genassym.cf
cvs rdiff -u -r1.2 -r1.3 src/lib/libc/arch/vax/sys/__sigtramp3.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/vax/genassym.cf
diff -u src/lib/libc/arch/vax/genassym.cf:1.5 src/lib/libc/arch/vax/genassym.cf:1.6
--- src/lib/libc/arch/vax/genassym.cf:1.5 Tue Jan 25 02:38:15 2011
+++ src/lib/libc/arch/vax/genassym.cf Wed Nov 24 15:05:15 2021
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.5 2011/01/25 02:38:15 matt Exp $
+# $NetBSD: genassym.cf,v 1.6 2021/11/24 15:05:15 thorpej Exp $
#
# Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -43,18 +43,25 @@ define _UC_SIGMASK _UC_SIGMASK
define _UC_STACK _UC_STACK
define _UC_CPU _UC_CPU
-define _REG_R0 4*_REG_R0
-define _REG_R1 4*_REG_R1
-define _REG_R2 4*_REG_R2
-define _REG_R4 4*_REG_R4
-define _REG_R6 4*_REG_R6
-define _REG_R8 4*_REG_R8
-define _REG_R10 4*_REG_R10
-define _REG_AP 4*_REG_AP
-define _REG_SP 4*_REG_SP
-define _REG_FP 4*_REG_FP
-define _REG_PC 4*_REG_PC
-define _REG_PSL 4*_REG_PSL
+define _REG_R0 _REG_R0
+define _REG_R1 _REG_R1
+define _REG_R2 _REG_R2
+define _REG_R3 _REG_R3
+define _REG_R4 _REG_R4
+define _REG_R5 _REG_R5
+define _REG_R6 _REG_R6
+define _REG_R7 _REG_R7
+define _REG_R8 _REG_R8
+define _REG_R9 _REG_R9
+define _REG_R10 _REG_R10
+define _REG_R11 _REG_R11
+define _REG_AP _REG_AP
+define _REG_FP _REG_FP
+define _REG_SP _REG_SP
+define _REG_PC _REG_PC
+define _REG_PSL _REG_PSL
+
+define SIZEOF_SIGINFO sizeof(siginfo_t)
define SS_SP offsetof(stack_t, ss_sp)
define SS_SIZE offsetof(stack_t, ss_size)
Index: src/lib/libc/arch/vax/sys/__sigtramp3.S
diff -u src/lib/libc/arch/vax/sys/__sigtramp3.S:1.2 src/lib/libc/arch/vax/sys/__sigtramp3.S:1.3
--- src/lib/libc/arch/vax/sys/__sigtramp3.S:1.2 Tue Jan 25 02:38:15 2011
+++ src/lib/libc/arch/vax/sys/__sigtramp3.S Wed Nov 24 15:05:16 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: __sigtramp3.S,v 1.2 2011/01/25 02:38:15 matt Exp $ */
+/* $NetBSD: __sigtramp3.S,v 1.3 2021/11/24 15:05:16 thorpej Exp $ */
/*
* Copyright (c) 2003 Matt Thomas
@@ -27,23 +27,70 @@
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include "SYS.h"
+#include "assym.h"
+
+#ifdef SYSLIBC_SCCS
+RCSID("$NetBSD: __sigtramp3.S,v 1.3 2021/11/24 15:05:16 thorpej Exp $")
+#endif
+
/*
* Signal trampoline; registers when called:
* pc, psl - obvious
- * sp, ap - points to argument list
- * 4(ap) -- signo
- * 8(ap) -- pointer to siginfo
- * 12(ap) -- pointer to ucontext
+ * sp, ap - points to a CALLG argument list
* fp - address of signal handler
+ *
+ * Stack is set up like so:
+ * ucontext structure
+ * siginfo structure
+ * CALLG argument list
+ * 12(ap) -- pointer to ucontext
+ * 8(ap) -- pointer to siginfo
+ * 4(ap) -- signal number
+ * sp -> 0(ap) -- argument count
+ * CALLG argument list
+ *
+ * N.B. all of the DWARF register numbers match our _REG_* constants.
+ * Also notice that while the %ap is adjusted inside the trampoline,
+ * the %sp is not adjusted, and so the CFA base does not change.
*/
-#include "SYS.h"
+#define CFI_OFFSET(r) .cfi_offset r, r * 4
-#ifdef SYSLIBC_SCCS
-RCSID("$NetBSD: __sigtramp3.S,v 1.2 2011/01/25 02:38:15 matt Exp $")
+ .text
+#if 0
+ .cfi_startproc simple
+ .cfi_signal_frame
+ .cfi_def_cfa _REG_SP, 16 + SIZEOF_SIGINFO + UC_GREGS
+ CFI_OFFSET(_REG_R0)
+ CFI_OFFSET(_REG_R1)
+ CFI_OFFSET(_REG_R2)
+ CFI_OFFSET(_REG_R3)
+ CFI_OFFSET(_REG_R4)
+ CFI_OFFSET(_REG_R5)
+ CFI_OFFSET(_REG_R6)
+ CFI_OFFSET(_REG_R7)
+ CFI_OFFSET(_REG_R8)
+ CFI_OFFSET(_REG_R9)
+ CFI_OFFSET(_REG_R10)
+ CFI_OFFSET(_REG_R11)
+ CFI_OFFSET(_REG_AP)
+ CFI_OFFSET(_REG_FP)
+ CFI_OFFSET(_REG_SP)
+ CFI_OFFSET(_REG_PC)
+ CFI_OFFSET(_REG_PSL)
#endif
- .text
+/*
+ * The unwind entry includes one instruction slot prior to the trampoline
+ * because the unwinder will look up to (return PC - 1) while unwinding.
+ * Normally this would be the jump / branch, but since there isn't one in
+ * this case, we place an explicit nop there instead.
+ */
+
+#if 0
+ nop
+#endif
_ALIGN_TEXT
.globl _C_LABEL(__sigtramp_siginfo_3)
@@ -53,3 +100,6 @@ _C_LABEL(__sigtramp_siginfo_3):
addl2 $8,%ap # arg is pointer to ucontext
SYSTRAP(setcontext) # exit from here
halt# illegal insn
+#if 0
+ .cfi_endproc
+#endif
CVS commit: src/lib/libc/arch/vax
Module Name:src Committed By: thorpej Date: Wed Nov 24 15:05:16 UTC 2021 Modified Files: src/lib/libc/arch/vax: genassym.cf src/lib/libc/arch/vax/sys: __sigtramp3.S Log Message: Decorate the VAX signal trampoline with the appropriate .cfi directives to allow exception unwind / backtrace across a signal handler. N.B. This is currently disabled, as these .cfi directives cause linker warnings about incompatible TEXTREL relocations in .eh_frame. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/lib/libc/arch/vax/genassym.cf cvs rdiff -u -r1.2 -r1.3 src/lib/libc/arch/vax/sys/__sigtramp3.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/sh3
Module Name:src
Committed By: thorpej
Date: Wed Nov 24 02:01:15 UTC 2021
Modified Files:
src/lib/libc/arch/sh3: Makefile.inc
src/lib/libc/arch/sh3/sys: __sigtramp2.S
Added Files:
src/lib/libc/arch/sh3: genassym.cf
Log Message:
Decorate the SuperH signal trampoline with the appropriate .cfi
directives to allow exception unwind / backtrace across a signal
handler.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/lib/libc/arch/sh3/Makefile.inc
cvs rdiff -u -r0 -r1.1 src/lib/libc/arch/sh3/genassym.cf
cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/sh3/sys/__sigtramp2.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/sh3/Makefile.inc
diff -u src/lib/libc/arch/sh3/Makefile.inc:1.8 src/lib/libc/arch/sh3/Makefile.inc:1.9
--- src/lib/libc/arch/sh3/Makefile.inc:1.8 Sun Oct 31 22:24:35 2021
+++ src/lib/libc/arch/sh3/Makefile.inc Wed Nov 24 02:01:15 2021
@@ -1,7 +1,9 @@
-# $NetBSD: Makefile.inc,v 1.8 2021/10/31 22:24:35 thorpej Exp $
+# $NetBSD: Makefile.inc,v 1.9 2021/11/24 02:01:15 thorpej Exp $
SRCS+= __sigtramp2.S
+CPPFLAGS+= -I.
+
.if ${MKSOFTFLOAT} != "no"
CPPFLAGS+= -DSOFTFLOAT # -DSOFTFLOAT_NEED_FIXUNS
Index: src/lib/libc/arch/sh3/sys/__sigtramp2.S
diff -u src/lib/libc/arch/sh3/sys/__sigtramp2.S:1.4 src/lib/libc/arch/sh3/sys/__sigtramp2.S:1.5
--- src/lib/libc/arch/sh3/sys/__sigtramp2.S:1.4 Thu Oct 15 05:50:15 2020
+++ src/lib/libc/arch/sh3/sys/__sigtramp2.S Wed Nov 24 02:01:15 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: __sigtramp2.S,v 1.4 2020/10/15 05:50:15 skrll Exp $ */
+/* $NetBSD: __sigtramp2.S,v 1.5 2021/11/24 02:01:15 thorpej Exp $ */
/*-
* Copyright (c) 2003 The NetBSD Foundation, Inc.
@@ -30,6 +30,7 @@
*/
#include "SYS.h"
+#include "assym.h"
/*
* The SH signal trampoline is invoked only to return from
@@ -44,11 +45,64 @@
* the top of the stack), because we want to avoid wasting two
* instructions to skip to the ucontext. Not that this order really
* matters, but I think this inconsistency deserves an explanation.
+ *
+ * The DWARF register numbers unforunately do not map directly to our
+ * _REG_* constants that are used to index the general registers in the
+ * ucontext_t at all.
+ *
+ * The stack pointer is, of course, r15, and there are several DWARF
+ * pseudo-registers to represent other bits of the context.
+ */
+
+#define DWARF_REG_PC 16
+#define DWARF_REG_PR 17
+#define DWARF_REG_GBR 18
+#define DWARF_REG_MACH 20
+#define DWARF_REG_MACL 21
+#define DWARF_REG_SR 22
+
+#define CFI_OFFSET_DWARF_REG(d, r) .cfi_offset d, r * 4
+
+ .text
+ .cfi_startproc simple
+ .cfi_signal_frame
+ .cfi_def_cfa 15, _UC_GREGS
+ CFI_OFFSET_DWARF_REG(0, _REG_R0)
+ CFI_OFFSET_DWARF_REG(1, _REG_R1)
+ CFI_OFFSET_DWARF_REG(2, _REG_R2)
+ CFI_OFFSET_DWARF_REG(3, _REG_R3)
+ CFI_OFFSET_DWARF_REG(4, _REG_R4)
+ CFI_OFFSET_DWARF_REG(5, _REG_R5)
+ CFI_OFFSET_DWARF_REG(6, _REG_R6)
+ CFI_OFFSET_DWARF_REG(7, _REG_R7)
+ CFI_OFFSET_DWARF_REG(9, _REG_R8)
+ CFI_OFFSET_DWARF_REG(9, _REG_R9)
+ CFI_OFFSET_DWARF_REG(10, _REG_R10)
+ CFI_OFFSET_DWARF_REG(11, _REG_R11)
+ CFI_OFFSET_DWARF_REG(12, _REG_R12)
+ CFI_OFFSET_DWARF_REG(13, _REG_R13)
+ CFI_OFFSET_DWARF_REG(14, _REG_R14)
+ CFI_OFFSET_DWARF_REG(15, _REG_R15)
+ CFI_OFFSET_DWARF_REG(DWARF_REG_PR, _REG_PR)
+ CFI_OFFSET_DWARF_REG(DWARF_REG_SR, _REG_SR)
+ CFI_OFFSET_DWARF_REG(DWARF_REG_GBR, _REG_GBR)
+ CFI_OFFSET_DWARF_REG(DWARF_REG_MACH, _REG_MACH)
+ CFI_OFFSET_DWARF_REG(DWARF_REG_MACL, _REG_MACL)
+ .cfi_return_column DWARF_REG_PC
+ CFI_OFFSET_DWARF_REG(DWARF_REG_PC, _REG_PC)
+
+/*
+ * The unwind entry includes one instruction slot prior to the trampoline
+ * because the unwinder will look up to (return PC - 1 insn) while unwinding.
+ * Normally this would be the jump / branch, but since there isn't one in
+ * this case, we place an explicit nop there instead.
*/
+ nop
+
NENTRY(__sigtramp_siginfo_2)
mov r15, r4 /* get pointer to ucontext */
SYSTRAP(setcontext) /* and call setcontext() */
mov r0, r4 /* exit with errno */
SYSTRAP(exit) /* if sigreturn fails */
-
+ .cfi_endproc
SET_ENTRY_SIZE(__sigtramp_siginfo_2)
Added files:
Index: src/lib/libc/arch/sh3/genassym.cf
diff -u /dev/null src/lib/libc/arch/sh3/genassym.cf:1.1
--- /dev/null Wed Nov 24 02:01:15 2021
+++ src/lib/libc/arch/sh3/genassym.cf Wed Nov 24 02:01:15 2021
@@ -0,0 +1,58 @@
+# $NetBSD: genassym.cf,v 1.1 2021/11/24 02:01:15 thorpej Exp $
+
+#
+# Copyright (c) 2021 The NetBSD Foundation, Inc.
+# All rights reserved.
+#
+# This code is derived from software contributed to The NetBSD Foundation
+# by Jason R. Thorpe.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# 1. Redistributions of source code must retain the above copyright
+#notice, this list of conditions and the following
CVS commit: src/lib/libc/arch/sh3
Module Name:src Committed By: thorpej Date: Wed Nov 24 02:01:15 UTC 2021 Modified Files: src/lib/libc/arch/sh3: Makefile.inc src/lib/libc/arch/sh3/sys: __sigtramp2.S Added Files: src/lib/libc/arch/sh3: genassym.cf Log Message: Decorate the SuperH signal trampoline with the appropriate .cfi directives to allow exception unwind / backtrace across a signal handler. To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/lib/libc/arch/sh3/Makefile.inc cvs rdiff -u -r0 -r1.1 src/lib/libc/arch/sh3/genassym.cf cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/sh3/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/arm
Module Name:src Committed By: thorpej Date: Tue Nov 23 18:45:53 UTC 2021 Modified Files: src/lib/libc/arch/arm: genassym.cf src/lib/libc/arch/arm/sys: __sigtramp2.S Log Message: Decorate the ARM signal trampoline with the appropriate .cfi directives to allow exception unwind / backtrace across a signal handler. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/arm/genassym.cf cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/arm/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/arm
Module Name:src Committed By: thorpej Date: Tue Nov 23 18:45:53 UTC 2021 Modified Files: src/lib/libc/arch/arm: genassym.cf src/lib/libc/arch/arm/sys: __sigtramp2.S Log Message: Decorate the ARM signal trampoline with the appropriate .cfi directives to allow exception unwind / backtrace across a signal handler. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/arm/genassym.cf cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/arm/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/lib/libc/arch/arm/genassym.cf diff -u src/lib/libc/arch/arm/genassym.cf:1.3 src/lib/libc/arch/arm/genassym.cf:1.4 --- src/lib/libc/arch/arm/genassym.cf:1.3 Sat Oct 24 07:03:11 2020 +++ src/lib/libc/arch/arm/genassym.cf Tue Nov 23 18:45:53 2021 @@ -1,4 +1,4 @@ -# $NetBSD: genassym.cf,v 1.3 2020/10/24 07:03:11 skrll Exp $ +# $NetBSD: genassym.cf,v 1.4 2021/11/23 18:45:53 thorpej Exp $ # # Copyright (c) 2012 The NetBSD Foundation, Inc. @@ -30,21 +30,30 @@ # include +include include +define _UC_GREGS offsetof(ucontext_t, uc_mcontext.__gregs[0]) define _UC_REGS_R0 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_R0]) -define _UC_REGS_R1 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_R1]) -define _UC_REGS_R2 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_R2]) -define _UC_REGS_R3 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_R3]) -define _UC_REGS_R4 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_R4]) -define _UC_REGS_R5 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_R5]) -define _UC_REGS_R6 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_R6]) -define _UC_REGS_R7 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_R7]) -define _UC_REGS_R8 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_R8]) -define _UC_REGS_R9 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_R9]) -define _UC_REGS_R10 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_R10]) -define _UC_REGS_R11 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_R11]) -define _UC_REGS_R12 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_R12]) define _UC_REGS_SP offsetof(ucontext_t, uc_mcontext.__gregs[_REG_SP]) -define _UC_REGS_LR offsetof(ucontext_t, uc_mcontext.__gregs[_REG_LR]) define _UC_REGS_PC offsetof(ucontext_t, uc_mcontext.__gregs[_REG_PC]) + +define SIZEOF_SIGINFO sizeof(siginfo_t) + +define _REG_R0 _REG_R0 +define _REG_R1 _REG_R1 +define _REG_R2 _REG_R2 +define _REG_R3 _REG_R3 +define _REG_R4 _REG_R4 +define _REG_R5 _REG_R5 +define _REG_R6 _REG_R6 +define _REG_R7 _REG_R7 +define _REG_R8 _REG_R8 +define _REG_R9 _REG_R9 +define _REG_R10 _REG_R10 +define _REG_R11 _REG_R11 +define _REG_R12 _REG_R12 +define _REG_R13 _REG_R13 +define _REG_R14 _REG_R14 +define _REG_R15 _REG_R15 +define _REG_SP _REG_SP Index: src/lib/libc/arch/arm/sys/__sigtramp2.S diff -u src/lib/libc/arch/arm/sys/__sigtramp2.S:1.3 src/lib/libc/arch/arm/sys/__sigtramp2.S:1.4 --- src/lib/libc/arch/arm/sys/__sigtramp2.S:1.3 Fri Aug 16 23:20:59 2013 +++ src/lib/libc/arch/arm/sys/__sigtramp2.S Tue Nov 23 18:45:53 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: __sigtramp2.S,v 1.3 2013/08/16 23:20:59 matt Exp $ */ +/* $NetBSD: __sigtramp2.S,v 1.4 2021/11/23 18:45:53 thorpej Exp $ */ /*- * Copyright (c) 2002 The NetBSD Foundation, Inc. @@ -30,6 +30,7 @@ */ #include "SYS.h" +#include "assym.h" /* * The ARM signal trampoline is invoked only to return from @@ -39,12 +40,46 @@ * * ucontext structure * sp-> siginfo structure - * and r5 points to the ucontext + * and r5 points to the ucontext */ + +#define CFI_OFFSET(r) .cfi_offset r, r * 4 + + _TEXT_SECTION + .cfi_startproc + .cfi_signal_frame + .cfi_def_cfa _REG_SP, SIZEOF_SIGINFO + _UC_GREGS + CFI_OFFSET(_REG_R0) + CFI_OFFSET(_REG_R1) + CFI_OFFSET(_REG_R2) + CFI_OFFSET(_REG_R3) + CFI_OFFSET(_REG_R4) + CFI_OFFSET(_REG_R5) + CFI_OFFSET(_REG_R6) + CFI_OFFSET(_REG_R7) + CFI_OFFSET(_REG_R8) + CFI_OFFSET(_REG_R9) + CFI_OFFSET(_REG_R10) + CFI_OFFSET(_REG_R11) + CFI_OFFSET(_REG_R12) + CFI_OFFSET(_REG_R13) /* a.k.a. _REG_SP */ + CFI_OFFSET(_REG_R14) /* a.k.a. _REG_LR */ + .cfi_return_column _REG_R15 + CFI_OFFSET(_REG_R15) /* a.k.a. _REG_PC */ + +/* + * The unwind entry includes the one instruction prior to the trampoline + * because the unwinder will look up (return PC - 1) while unwinding. + * Normally this would be the jump / branch, but since there isn't one in + * this case, we place an explicit nop there instead. + */ + nop + ENTRY_NP(__sigtramp_siginfo_2) mov r0, r5/* set the arg */ SYSTRAP(setcontext) /* and call setcontext */ /* If that failed, exit with the error code. */ SYSTRAP(exit) + .cfi_endproc END(__sigtramp_siginfo_2)
CVS commit: src/lib/libc/arch/aarch64
Module Name:src Committed By: thorpej Date: Tue Nov 23 02:49:56 UTC 2021 Modified Files: src/lib/libc/arch/aarch64: genassym.cf src/lib/libc/arch/aarch64/sys: __sigtramp2.S Log Message: Because the PC is not a general purpose register on aarch64, we need to use DWARF pseudo-register for the signal trampoline return address. Adjust the style to match other platforms. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/aarch64/genassym.cf cvs rdiff -u -r1.6 -r1.7 src/lib/libc/arch/aarch64/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/lib/libc/arch/aarch64/genassym.cf diff -u src/lib/libc/arch/aarch64/genassym.cf:1.4 src/lib/libc/arch/aarch64/genassym.cf:1.5 --- src/lib/libc/arch/aarch64/genassym.cf:1.4 Sat Oct 17 15:44:59 2020 +++ src/lib/libc/arch/aarch64/genassym.cf Tue Nov 23 02:49:55 2021 @@ -1,4 +1,4 @@ -# $NetBSD: genassym.cf,v 1.4 2020/10/17 15:44:59 skrll Exp $ +# $NetBSD: genassym.cf,v 1.5 2021/11/23 02:49:55 thorpej Exp $ #- # Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -33,40 +33,45 @@ include include include +define _UC_GREGS offsetof(ucontext_t, uc_mcontext.__gregs[0]) define _UC_REGS_X0 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X0]) -define _UC_REGS_X1 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X1]) -define _UC_REGS_X2 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X2]) -define _UC_REGS_X3 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X3]) -define _UC_REGS_X4 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X4]) -define _UC_REGS_X5 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X5]) -define _UC_REGS_X6 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X6]) -define _UC_REGS_X7 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X7]) -define _UC_REGS_X8 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X8]) -define _UC_REGS_X9 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X9]) -define _UC_REGS_X10 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X10]) -define _UC_REGS_X11 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X11]) -define _UC_REGS_X12 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X12]) -define _UC_REGS_X13 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X13]) -define _UC_REGS_X14 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X14]) -define _UC_REGS_X15 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X15]) -define _UC_REGS_X16 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X16]) -define _UC_REGS_X17 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X17]) -define _UC_REGS_X18 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X18]) -define _UC_REGS_X19 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X19]) -define _UC_REGS_X20 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X20]) -define _UC_REGS_X21 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X21]) -define _UC_REGS_X22 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X22]) -define _UC_REGS_X23 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X23]) -define _UC_REGS_X24 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X24]) -define _UC_REGS_X25 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X25]) -define _UC_REGS_X26 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X26]) -define _UC_REGS_X27 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X27]) -define _UC_REGS_X28 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X28]) -define _UC_REGS_X29 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_X29]) -define _UC_REGS_LR offsetof(ucontext_t, uc_mcontext.__gregs[_REG_LR]) define _UC_REGS_SP offsetof(ucontext_t, uc_mcontext.__gregs[_REG_SP]) define _UC_REGS_PC offsetof(ucontext_t, uc_mcontext.__gregs[_REG_PC]) +define _REG_X0 _REG_X0 +define _REG_X1 _REG_X1 +define _REG_X2 _REG_X2 +define _REG_X3 _REG_X3 +define _REG_X4 _REG_X4 +define _REG_X5 _REG_X5 +define _REG_X6 _REG_X6 +define _REG_X7 _REG_X7 +define _REG_X8 _REG_X8 +define _REG_X9 _REG_X9 +define _REG_X10 _REG_X10 +define _REG_X11 _REG_X11 +define _REG_X12 _REG_X12 +define _REG_X13 _REG_X13 +define _REG_X14 _REG_X14 +define _REG_X15 _REG_X15 +define _REG_X16 _REG_X16 +define _REG_X17 _REG_X17 +define _REG_X18 _REG_X18 +define _REG_X19 _REG_X19 +define _REG_X20 _REG_X20 +define _REG_X21 _REG_X21 +define _REG_X22 _REG_X22 +define _REG_X23 _REG_X23 +define _REG_X24 _REG_X24 +define _REG_X25 _REG_X25 +define _REG_X26 _REG_X26 +define _REG_X27 _REG_X27 +define _REG_X28 _REG_X28 +define _REG_X29 _REG_X29 +define _REG_X30 _REG_X30 +define _REG_X31 _REG_X31 +define _REG_PC _REG_PC + define _JB_MAGIC_AARCH64__SETJMP _JB_MAGIC_AARCH64__SETJMP define _JB_MAGIC_AARCH64_SETJMP _JB_MAGIC_AARCH64_SETJMP define _JB_MAGIC sizeof(_BSD_JBSLOT_T_ [_JB_MAGIC]) Index: src/lib/libc/arch/aarch64/sys/__sigtramp2.S diff -u src/lib/libc/arch/aarch64/sys/__sigtramp2.S:1.6 src/lib/libc/arch/aarch64/sys/__sigtramp2.S:1.7 --- src/lib/libc/arch/aarch64/sys/__sigtramp2.S:1.6 Sat Oct 24 07:02:20 2020 +++ src/lib/libc/arch/aarch64/sys/__sigtramp2.S
CVS commit: src/lib/libc/arch/aarch64
Module Name:src Committed By: thorpej Date: Tue Nov 23 02:49:56 UTC 2021 Modified Files: src/lib/libc/arch/aarch64: genassym.cf src/lib/libc/arch/aarch64/sys: __sigtramp2.S Log Message: Because the PC is not a general purpose register on aarch64, we need to use DWARF pseudo-register for the signal trampoline return address. Adjust the style to match other platforms. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/aarch64/genassym.cf cvs rdiff -u -r1.6 -r1.7 src/lib/libc/arch/aarch64/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/m68k
Module Name:src Committed By: thorpej Date: Sun Nov 21 23:58:09 UTC 2021 Modified Files: src/lib/libc/arch/m68k: genassym.cf src/lib/libc/arch/m68k/sys: __sigtramp2.S Log Message: Decorate the m68k signal trampoline with the appropriate .cfi directives to allow exception unwind / backtrace across a signal handler. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/lib/libc/arch/m68k/genassym.cf cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/m68k/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/m68k
Module Name:src Committed By: thorpej Date: Sun Nov 21 23:58:09 UTC 2021 Modified Files: src/lib/libc/arch/m68k: genassym.cf src/lib/libc/arch/m68k/sys: __sigtramp2.S Log Message: Decorate the m68k signal trampoline with the appropriate .cfi directives to allow exception unwind / backtrace across a signal handler. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/lib/libc/arch/m68k/genassym.cf cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/m68k/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/lib/libc/arch/m68k/genassym.cf diff -u src/lib/libc/arch/m68k/genassym.cf:1.1 src/lib/libc/arch/m68k/genassym.cf:1.2 --- src/lib/libc/arch/m68k/genassym.cf:1.1 Wed Jul 17 01:41:17 2013 +++ src/lib/libc/arch/m68k/genassym.cf Sun Nov 21 23:58:09 2021 @@ -1,4 +1,4 @@ -# $NetBSD: genassym.cf,v 1.1 2013/07/17 01:41:17 matt Exp $ +# $NetBSD: genassym.cf,v 1.2 2021/11/21 23:58:09 thorpej Exp $ # # Copyright (c) 2013 The NetBSD Foundation, Inc. @@ -36,11 +36,32 @@ include define UC_LINK offsetof(ucontext_t, uc_link) define UC_SIGMASK offsetof(ucontext_t, uc_sigmask) +define UC_GREGS offsetof(ucontext_t, uc_mcontext.__gregs[0]) define UC_MCONTEXT_D0 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_D0]) define UC_MCONTEXT_SP offsetof(ucontext_t, uc_mcontext.__gregs[_REG_A7]) define UC_MCONTEXT_PC offsetof(ucontext_t, uc_mcontext.__gregs[_REG_PC]) define UC_SIZE sizeof(ucontext_t) +define _REG_D0 _REG_D0 +define _REG_D1 _REG_D1 +define _REG_D2 _REG_D2 +define _REG_D3 _REG_D3 +define _REG_D4 _REG_D4 +define _REG_D5 _REG_D5 +define _REG_D6 _REG_D6 +define _REG_D7 _REG_D7 +define _REG_A0 _REG_A0 +define _REG_A1 _REG_A1 +define _REG_A2 _REG_A2 +define _REG_A3 _REG_A3 +define _REG_A4 _REG_A4 +define _REG_A5 _REG_A5 +define _REG_A6 _REG_A6 +define _REG_A7 _REG_A7 +define _REG_PC _REG_PC + +define SIZEOF_SIGINFO sizeof(siginfo_t) + define SC_ONSTACK offsetof(struct sigcontext, sc_onstack) define SC___MASK13 offsetof(struct sigcontext, __sc_mask13) define SC_SP offsetof(struct sigcontext, sc_sp) Index: src/lib/libc/arch/m68k/sys/__sigtramp2.S diff -u src/lib/libc/arch/m68k/sys/__sigtramp2.S:1.4 src/lib/libc/arch/m68k/sys/__sigtramp2.S:1.5 --- src/lib/libc/arch/m68k/sys/__sigtramp2.S:1.4 Tue Jul 16 22:19:16 2013 +++ src/lib/libc/arch/m68k/sys/__sigtramp2.S Sun Nov 21 23:58:09 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: __sigtramp2.S,v 1.4 2013/07/16 22:19:16 matt Exp $ */ +/* $NetBSD: __sigtramp2.S,v 1.5 2021/11/21 23:58:09 thorpej Exp $ */ /*- * Copyright (c) 2003 The NetBSD Foundation, Inc. @@ -27,6 +27,7 @@ */ #include "SYS.h" +#include "assym.h" /* * The m68k signal trampoline is invoked only to return from @@ -39,7 +40,57 @@ * pointer to ucontext structure [8] * pointer to siginfo structure [4] * sp-> signal number[0] + * + * The DWARF register numbers are 0-7 (dX), 8-15 (aX), 16-23 (fpX), + * which maps nicely to _REG_D[0-7] and _REG_A[0-7]. For m68k, there + * is a DWARF pseudo-register for the return address, and additionally + * another DWARF pseudo-register for signal handler return addresses. + * We will specify both return address pseudo-registers (without + * explicitly specifying .cfi_return_column) to keep the compiler + * run-time happy with whichever one it decides to use. + */ + +#define DWARF_RETURN_REG 24 +#if defined(__LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__) +#define DWARF_SIGRETURN_REG __LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__ +#else +#define DWARF_SIGRETURN_REG 25 +#endif + +#define CFI_OFFSET_DWARF_REG(d, r) .cfi_offset d, r * 4 +#define CFI_OFFSET(r) CFI_OFFSET_DWARF_REG(r, r) + + .text + .cfi_startproc simple + .cfi_signal_frame + .cfi_def_cfa _REG_A7, 12 + SIZEOF_SIGINFO + UC_GREGS + CFI_OFFSET(_REG_D0) + CFI_OFFSET(_REG_D1) + CFI_OFFSET(_REG_D2) + CFI_OFFSET(_REG_D3) + CFI_OFFSET(_REG_D4) + CFI_OFFSET(_REG_D5) + CFI_OFFSET(_REG_D6) + CFI_OFFSET(_REG_D7) + CFI_OFFSET(_REG_A0) + CFI_OFFSET(_REG_A1) + CFI_OFFSET(_REG_A2) + CFI_OFFSET(_REG_A3) + CFI_OFFSET(_REG_A4) + CFI_OFFSET(_REG_A5) + CFI_OFFSET(_REG_A6) + CFI_OFFSET(_REG_A7) + CFI_OFFSET_DWARF_REG(DWARF_RETURN_REG, _REG_PC) + CFI_OFFSET_DWARF_REG(DWARF_SIGRETURN_REG, _REG_PC) + +/* + * The unwind entry includes one instruction slot prior to the trampoline + * because the unwinder will look up to (return PC - 1 insn) while unwinding. + * Normally this would be the jump / branch, but since there isn't one in + * this case, we place an explicit nop there instead. */ + nop + ENTRY_NOPROFILE(__sigtramp_siginfo_2) movl 8(%sp),%a0 /* get pointer to ucontext */ movl %a0,4(%sp) /* put it in the argument slot */ @@ -47,4 +98,5 @@ ENTRY_NOPROFILE(__sigtramp_siginfo_2) SYSTRAP(setcontext) movl %d0,4(%sp) /* error code */ SYSTRAP(exit) /* exit */ + .cfi_endproc END(__sigtramp_siginfo_2)
CVS commit: src/lib/libc/arch/powerpc
Module Name:src
Committed By: thorpej
Date: Sun Nov 21 21:31:25 UTC 2021
Modified Files:
src/lib/libc/arch/powerpc: genassym.cf
src/lib/libc/arch/powerpc/sys: __sigtramp2.S
Log Message:
Decorate the powerpc signal trampoline with the appropriate .cfi
directives to allow exception unwind / backtrace across a signal
handler.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/lib/libc/arch/powerpc/genassym.cf
cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/powerpc/sys/__sigtramp2.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/powerpc/genassym.cf
diff -u src/lib/libc/arch/powerpc/genassym.cf:1.5 src/lib/libc/arch/powerpc/genassym.cf:1.6
--- src/lib/libc/arch/powerpc/genassym.cf:1.5 Wed Feb 28 21:00:02 2018
+++ src/lib/libc/arch/powerpc/genassym.cf Sun Nov 21 21:31:24 2021
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.5 2018/02/28 21:00:02 uwe Exp $
+# $NetBSD: genassym.cf,v 1.6 2021/11/21 21:31:24 thorpej Exp $
#
# Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -42,11 +42,50 @@ define CALLFRAME_LR offsetof(struct call
define CALLFRAME_R30 offsetof(struct callframe, cf_r30)
define CALLFRAME_R31 offsetof(struct callframe, cf_r31)
+define UC_GREGS offsetof(ucontext_t, uc_mcontext.__gregs[0])
define UC_GREGS_R1 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_R1])
define UC_GREGS_R3 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_R3])
define UC_GREGS_R30 offsetof(ucontext_t, uc_mcontext.__gregs[_REG_R30])
define UC_GREGS_PC offsetof(ucontext_t, uc_mcontext.__gregs[_REG_PC])
+define _REG_R0 _REG_R0
+define _REG_R1 _REG_R1
+define _REG_R2 _REG_R2
+define _REG_R3 _REG_R3
+define _REG_R4 _REG_R4
+define _REG_R5 _REG_R5
+define _REG_R6 _REG_R6
+define _REG_R7 _REG_R7
+define _REG_R8 _REG_R8
+define _REG_R9 _REG_R9
+define _REG_R10 _REG_R10
+define _REG_R11 _REG_R11
+define _REG_R12 _REG_R12
+define _REG_R13 _REG_R13
+define _REG_R14 _REG_R14
+define _REG_R15 _REG_R15
+define _REG_R16 _REG_R16
+define _REG_R17 _REG_R17
+define _REG_R18 _REG_R18
+define _REG_R19 _REG_R19
+define _REG_R20 _REG_R20
+define _REG_R21 _REG_R21
+define _REG_R22 _REG_R22
+define _REG_R23 _REG_R23
+define _REG_R24 _REG_R24
+define _REG_R25 _REG_R25
+define _REG_R26 _REG_R26
+define _REG_R27 _REG_R27
+define _REG_R28 _REG_R28
+define _REG_R29 _REG_R29
+define _REG_R30 _REG_R30
+define _REG_R31 _REG_R31
+define _REG_CR _REG_CR
+define _REG_LR _REG_LR
+define _REG_PC _REG_PC
+define _REG_CTR _REG_CTR
+define _REG_XER _REG_XER
+
define SIG_BLOCK SIG_BLOCK
define SIG_SETMASK SIG_SETMASK
Index: src/lib/libc/arch/powerpc/sys/__sigtramp2.S
diff -u src/lib/libc/arch/powerpc/sys/__sigtramp2.S:1.3 src/lib/libc/arch/powerpc/sys/__sigtramp2.S:1.4
--- src/lib/libc/arch/powerpc/sys/__sigtramp2.S:1.3 Sat Jan 15 07:31:12 2011
+++ src/lib/libc/arch/powerpc/sys/__sigtramp2.S Sun Nov 21 21:31:24 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: __sigtramp2.S,v 1.3 2011/01/15 07:31:12 matt Exp $ */
+/* $NetBSD: __sigtramp2.S,v 1.4 2021/11/21 21:31:24 thorpej Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
@@ -30,9 +30,10 @@
*/
#include "SYS.h"
+#include "assym.h"
#if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: __sigtramp2.S,v 1.3 2011/01/15 07:31:12 matt Exp $")
+__RCSID("$NetBSD: __sigtramp2.S,v 1.4 2021/11/21 21:31:24 thorpej Exp $")
#endif /* LIBC_SCCS && !lint */
/*
@@ -45,9 +46,86 @@ __RCSID("$NetBSD: __sigtramp2.S,v 1.3 20
* srr0 address of handler
* lr address of this trampoline
*
+ * We use r30 as the CFA base register since it's been conveniently set up
+ * for us that way. The DWARF register numbers used in the .eh_frame are:
+ *
+ * 0 - 31 GPRs
+ * 32 - 63 FPRs
+ * 65 LR
+ * 66 CTR
+ * 68-75 CRs
+ * 76 XER
+ * 77 - 108 AltiVec regs
+ * 99 signal trampoline return address
+ * 109 VRSAVE
+ * 110 VCSR
+ *
+ * N.B. Only one CR slot is used (CR2) in the SVR4 ABI.
*/
+
+#define DWARF_LR_REG 65
+#define DWARF_CTR_REG 66
+#define DWARF_CR2_REG 70
+#define DWARF_XER_REG 76
+#define DWARF_SIGRETURN_REG 99
+
+#define CFI_OFFSET_DWARF_REG(d, r) .cfi_offset d, r * 4
+#define CFI_OFFSET(r) CFI_OFFSET_DWARF_REG(r, r)
+
+ .text
+ .cfi_startproc simple
+ .cfi_signal_frame
+ .cfi_def_cfa _REG_R30, UC_GREGS
+ CFI_OFFSET(_REG_R0)
+ CFI_OFFSET(_REG_R1)
+ CFI_OFFSET(_REG_R2)
+ CFI_OFFSET(_REG_R3)
+ CFI_OFFSET(_REG_R4)
+ CFI_OFFSET(_REG_R5)
+ CFI_OFFSET(_REG_R6)
+ CFI_OFFSET(_REG_R7)
+ CFI_OFFSET(_REG_R8)
+ CFI_OFFSET(_REG_R9)
+ CFI_OFFSET(_REG_R10)
+ CFI_OFFSET(_REG_R11)
+ CFI_OFFSET(_REG_R12)
+ CFI_OFFSET(_REG_R13)
+ CFI_OFFSET(_REG_R14)
+ CFI_OFFSET(_REG_R15)
+ CFI_OFFSET(_REG_R16)
+ CFI_OFFSET(_REG_R17)
+ CFI_OFFSET(_REG_R18)
+ CFI_OFFSET(_REG_R19)
+ CFI_OFFSET(_REG_R20)
+ CFI_OFFSET(_REG_R21)
+ CFI_OFFSET(_REG_R22)
+ CFI_OFFSET(_REG_R23)
+ CFI_OFFSET(_REG_R24)
+ CFI_OFFSET(_REG_R25)
+ CFI_OFFSET(_REG_R26)
+
CVS commit: src/lib/libc/arch/powerpc
Module Name:src Committed By: thorpej Date: Sun Nov 21 21:31:25 UTC 2021 Modified Files: src/lib/libc/arch/powerpc: genassym.cf src/lib/libc/arch/powerpc/sys: __sigtramp2.S Log Message: Decorate the powerpc signal trampoline with the appropriate .cfi directives to allow exception unwind / backtrace across a signal handler. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/lib/libc/arch/powerpc/genassym.cf cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/powerpc/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/alpha/sys
Module Name:src Committed By: thorpej Date: Sat Nov 20 19:26:20 UTC 2021 Modified Files: src/lib/libc/arch/alpha/sys: __sigtramp2.S Log Message: Use the DWARF pseudo-register for the signal trampoline return address. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/lib/libc/arch/alpha/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/lib/libc/arch/alpha/sys/__sigtramp2.S diff -u src/lib/libc/arch/alpha/sys/__sigtramp2.S:1.7 src/lib/libc/arch/alpha/sys/__sigtramp2.S:1.8 --- src/lib/libc/arch/alpha/sys/__sigtramp2.S:1.7 Wed Nov 3 04:52:51 2021 +++ src/lib/libc/arch/alpha/sys/__sigtramp2.S Sat Nov 20 19:26:20 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: __sigtramp2.S,v 1.7 2021/11/03 04:52:51 thorpej Exp $ */ +/* $NetBSD: __sigtramp2.S,v 1.8 2021/11/20 19:26:20 thorpej Exp $ */ /* * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. @@ -38,10 +38,20 @@ * * ucontext structure [128] == sp + sizeof(siginfo_t)] * sp-> siginfo structure [0] + * + * The DWARF register numbers for the general purpose registers are the + * same as the architected register numbers. For Alpha, there is a DWARF + * pseudo-register for signal handler return addresses. */ -#define CFI_OFFSET_REG(n, r) .cfi_offset n, r*8 -#define CFI_OFFSET(r) CFI_OFFSET_REG(r, r) +#if defined(__LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__) +#define DWARF_SIGRETURN_REG __LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__ +#else +#define DWARF_SIGRETURN_REG 64 +#endif + +#define CFI_OFFSET_DWARF_REG(d, r) .cfi_offset d, r*8 +#define CFI_OFFSET(r) CFI_OFFSET_DWARF_REG(r, r) .cfi_startproc simple .cfi_signal_frame @@ -72,11 +82,13 @@ CFI_OFFSET(_REG_T9) CFI_OFFSET(_REG_T10) CFI_OFFSET(_REG_T11) - CFI_OFFSET_REG(_REG_RA, _REG_PC) + CFI_OFFSET(_REG_RA) CFI_OFFSET(_REG_T12) /* a.k.a. _REG_PV */ CFI_OFFSET(_REG_AT) CFI_OFFSET(_REG_GP) CFI_OFFSET(_REG_SP) + .cfi_return_column DWARF_SIGRETURN_REG + CFI_OFFSET_DWARF_REG(DWARF_SIGRETURN_REG, _REG_PC) /* * The unwind entry includes one instruction slot prior to the trampoline
CVS commit: src/lib/libc/arch/alpha/sys
Module Name:src Committed By: thorpej Date: Sat Nov 20 19:26:20 UTC 2021 Modified Files: src/lib/libc/arch/alpha/sys: __sigtramp2.S Log Message: Use the DWARF pseudo-register for the signal trampoline return address. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/lib/libc/arch/alpha/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/mips
Module Name:src
Committed By: thorpej
Date: Thu Nov 18 04:33:20 UTC 2021
Modified Files:
src/lib/libc/arch/mips: genassym.cf
src/lib/libc/arch/mips/sys: __sigtramp2.S
Log Message:
Decorate the MIPS signal trampoline with the appropriate .cfi
directives to allow exception unwind / backtrace across a signal
handler.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/mips/genassym.cf
cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/mips/sys/__sigtramp2.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/mips/genassym.cf
diff -u src/lib/libc/arch/mips/genassym.cf:1.4 src/lib/libc/arch/mips/genassym.cf:1.5
--- src/lib/libc/arch/mips/genassym.cf:1.4 Thu Oct 15 05:27:53 2020
+++ src/lib/libc/arch/mips/genassym.cf Thu Nov 18 04:33:20 2021
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.4 2020/10/15 05:27:53 skrll Exp $
+# $NetBSD: genassym.cf,v 1.5 2021/11/18 04:33:20 thorpej Exp $
#
# Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -40,9 +40,46 @@ define _UC_GREGS_V0 offsetof(ucontext_t,
define _UC_GREGS_GP offsetof(ucontext_t, uc_mcontext.__gregs[_REG_GP])
define _UC_GREGS_SP offsetof(ucontext_t, uc_mcontext.__gregs[_REG_SP])
define _UC_GREGS_EPC offsetof(ucontext_t, uc_mcontext.__gregs[_REG_EPC])
+define _UC_GREGS offsetof(ucontext_t, uc_mcontext.__gregs[0])
define _UC_LINK offsetof(ucontext_t, uc_link)
define UCONTEXT_SIZE sizeof(ucontext_t)
+define _REG_R0 _REG_R0
+define _REG_AT _REG_AT
+define _REG_V0 _REG_V0
+define _REG_V1 _REG_V1
+define _REG_A0 _REG_A0
+define _REG_A1 _REG_A1
+define _REG_A2 _REG_A2
+define _REG_A3 _REG_A3
+define _REG_T0 _REG_T0
+define _REG_T1 _REG_T1
+define _REG_T2 _REG_T2
+define _REG_T3 _REG_T3
+define _REG_T4 _REG_T4
+define _REG_T5 _REG_T5
+define _REG_T6 _REG_T6
+define _REG_T7 _REG_T7
+define _REG_S0 _REG_S0
+define _REG_S1 _REG_S1
+define _REG_S2 _REG_S2
+define _REG_S3 _REG_S3
+define _REG_S4 _REG_S4
+define _REG_S5 _REG_S5
+define _REG_S6 _REG_S6
+define _REG_S7 _REG_S7
+define _REG_T8 _REG_T8
+define _REG_T9 _REG_T9
+define _REG_K0 _REG_K0
+define _REG_K1 _REG_K1
+define _REG_GP _REG_GP
+define _REG_SP _REG_SP
+define _REG_S8 _REG_S8
+define _REG_RA _REG_RA
+define _REG_EPC _REG_EPC
+define _REG_MDLO _REG_MDLO
+define _REG_MDHI _REG_MDHI
+
define _SC_REGS offsetof(struct sigcontext, sc_regs[0])
define _SC_REGS_V0 offsetof(struct sigcontext, sc_regs[_R_V0])
define _SC_REGS_S0 offsetof(struct sigcontext, sc_regs[_R_S0])
Index: src/lib/libc/arch/mips/sys/__sigtramp2.S
diff -u src/lib/libc/arch/mips/sys/__sigtramp2.S:1.3 src/lib/libc/arch/mips/sys/__sigtramp2.S:1.4
--- src/lib/libc/arch/mips/sys/__sigtramp2.S:1.3 Mon Dec 14 01:07:42 2009
+++ src/lib/libc/arch/mips/sys/__sigtramp2.S Thu Nov 18 04:33:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: __sigtramp2.S,v 1.3 2009/12/14 01:07:42 matt Exp $ */
+/* $NetBSD: __sigtramp2.S,v 1.4 2021/11/18 04:33:20 thorpej Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
#include "assym.h"
#if defined(SYSLIBC_SCCS) && !defined(lint)
- RCSID("$NetBSD: __sigtramp2.S,v 1.3 2009/12/14 01:07:42 matt Exp $")
+ RCSID("$NetBSD: __sigtramp2.S,v 1.4 2021/11/18 04:33:20 thorpej Exp $")
#endif /* SYSLIBC_SCCS and not lint */
@@ -43,12 +43,80 @@
*
* On entry, stack looks like:
*
- * sp -> siginfo_t structure
- * sp + SIGINFO_SIZE -> ucontext_t structure
+ * ucontext structure sp + sizeof(siginfo_t)
+ * sp-> siginfo structure
+ *
+ * The DWARF register numbers for the general purpose registers are the
+ * same as the architected register numbers. For MIPS, there is a DWARF
+ * psuedo-register for signal handler return addresses, as well as for the
+ * MDLO and MDHI registers.
*/
+
+#define DWARF_MDHI_REG 64
+#define DWARF_MDLO_REG 65
+
+#if defined(__LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__)
+#define DWARF_SIGRETURN_REG __LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__
+#else
+#define DWARF_SIGRETURN_REG 66
+#endif
+
+#define CFI_OFFSET_DWARF_REG(d, r) .cfi_offset d, r * SZREG
+#define CFI_OFFSET(r) CFI_OFFSET_DWARF_REG(r, r)
+
+ .text
+ .cfi_startproc
+ .cfi_signal_frame
+ .cfi_def_cfa _REG_SP, SIGINFO_SIZE + _UC_GREGS
+ CFI_OFFSET(_REG_R0)
+ CFI_OFFSET(_REG_AT)
+ CFI_OFFSET(_REG_V0)
+ CFI_OFFSET(_REG_V1)
+ CFI_OFFSET(_REG_A0)
+ CFI_OFFSET(_REG_A1)
+ CFI_OFFSET(_REG_A2)
+ CFI_OFFSET(_REG_A3)
+ CFI_OFFSET(_REG_T0)
+ CFI_OFFSET(_REG_T1)
+ CFI_OFFSET(_REG_T2)
+ CFI_OFFSET(_REG_T3)
+ CFI_OFFSET(_REG_T4)
+ CFI_OFFSET(_REG_T5)
+ CFI_OFFSET(_REG_T6)
+ CFI_OFFSET(_REG_T7)
+ CFI_OFFSET(_REG_S0)
+ CFI_OFFSET(_REG_S1)
+ CFI_OFFSET(_REG_S2)
+ CFI_OFFSET(_REG_S3)
+ CFI_OFFSET(_REG_S4)
+ CFI_OFFSET(_REG_S5)
+ CFI_OFFSET(_REG_S6)
+ CFI_OFFSET(_REG_S7)
+ CFI_OFFSET(_REG_T8)
+ CFI_OFFSET(_REG_T9)
+ CFI_OFFSET(_REG_K0)
+ CFI_OFFSET(_REG_K1)
+ CFI_OFFSET(_REG_GP)
+ CFI_OFFSET(_REG_SP)
+ CFI_OFFSET(_REG_S8)
+
CVS commit: src/lib/libc/arch/mips
Module Name:src Committed By: thorpej Date: Thu Nov 18 04:33:20 UTC 2021 Modified Files: src/lib/libc/arch/mips: genassym.cf src/lib/libc/arch/mips/sys: __sigtramp2.S Log Message: Decorate the MIPS signal trampoline with the appropriate .cfi directives to allow exception unwind / backtrace across a signal handler. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/mips/genassym.cf cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/mips/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/alpha/sys
Module Name:src Committed By: thorpej Date: Wed Nov 3 04:52:51 UTC 2021 Modified Files: src/lib/libc/arch/alpha/sys: __sigtramp2.S Log Message: CFI: Saved RA needs to point to the PC slot in the ucontext_t. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/lib/libc/arch/alpha/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/lib/libc/arch/alpha/sys/__sigtramp2.S diff -u src/lib/libc/arch/alpha/sys/__sigtramp2.S:1.6 src/lib/libc/arch/alpha/sys/__sigtramp2.S:1.7 --- src/lib/libc/arch/alpha/sys/__sigtramp2.S:1.6 Wed Nov 3 03:58:31 2021 +++ src/lib/libc/arch/alpha/sys/__sigtramp2.S Wed Nov 3 04:52:51 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: __sigtramp2.S,v 1.6 2021/11/03 03:58:31 thorpej Exp $ */ +/* $NetBSD: __sigtramp2.S,v 1.7 2021/11/03 04:52:51 thorpej Exp $ */ /* * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. @@ -40,7 +40,8 @@ * sp-> siginfo structure [0] */ -#define CFI_OFFSET(r) .cfi_offset r, r*8 +#define CFI_OFFSET_REG(n, r) .cfi_offset n, r*8 +#define CFI_OFFSET(r) CFI_OFFSET_REG(r, r) .cfi_startproc simple .cfi_signal_frame @@ -71,7 +72,7 @@ CFI_OFFSET(_REG_T9) CFI_OFFSET(_REG_T10) CFI_OFFSET(_REG_T11) - CFI_OFFSET(_REG_RA) + CFI_OFFSET_REG(_REG_RA, _REG_PC) CFI_OFFSET(_REG_T12) /* a.k.a. _REG_PV */ CFI_OFFSET(_REG_AT) CFI_OFFSET(_REG_GP)
CVS commit: src/lib/libc/arch/alpha/sys
Module Name:src Committed By: thorpej Date: Wed Nov 3 04:52:51 UTC 2021 Modified Files: src/lib/libc/arch/alpha/sys: __sigtramp2.S Log Message: CFI: Saved RA needs to point to the PC slot in the ucontext_t. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/lib/libc/arch/alpha/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/alpha/sys
Module Name:src Committed By: thorpej Date: Wed Nov 3 03:58:31 UTC 2021 Modified Files: src/lib/libc/arch/alpha/sys: __sigtramp2.S Log Message: Set up the CFI in a slightly more rational way. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/lib/libc/arch/alpha/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/lib/libc/arch/alpha/sys/__sigtramp2.S diff -u src/lib/libc/arch/alpha/sys/__sigtramp2.S:1.5 src/lib/libc/arch/alpha/sys/__sigtramp2.S:1.6 --- src/lib/libc/arch/alpha/sys/__sigtramp2.S:1.5 Wed Oct 21 01:58:30 2020 +++ src/lib/libc/arch/alpha/sys/__sigtramp2.S Wed Nov 3 03:58:31 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: __sigtramp2.S,v 1.5 2020/10/21 01:58:30 thorpej Exp $ */ +/* $NetBSD: __sigtramp2.S,v 1.6 2021/11/03 03:58:31 thorpej Exp $ */ /* * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. @@ -40,11 +40,11 @@ * sp-> siginfo structure [0] */ -#define CFI_OFFSET(r) .cfi_offset r, SIZEOF_SIGINFO + UC_GREGS + r*8 +#define CFI_OFFSET(r) .cfi_offset r, r*8 .cfi_startproc simple .cfi_signal_frame - .cfi_def_cfa _REG_SP, 0 + .cfi_def_cfa _REG_SP, SIZEOF_SIGINFO + UC_GREGS CFI_OFFSET(_REG_V0) CFI_OFFSET(_REG_T0) CFI_OFFSET(_REG_T1)
CVS commit: src/lib/libc/arch/alpha/sys
Module Name:src Committed By: thorpej Date: Wed Nov 3 03:58:31 UTC 2021 Modified Files: src/lib/libc/arch/alpha/sys: __sigtramp2.S Log Message: Set up the CFI in a slightly more rational way. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/lib/libc/arch/alpha/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/aarch64/gen
Module Name:src
Committed By: skrll
Date: Thu Oct 7 06:44:19 UTC 2021
Modified Files:
src/lib/libc/arch/aarch64/gen: _setjmp.S setjmp.S
Log Message:
Fix the lib/libc/setjmp/t_setjmp:{,_}longjmp_zero test cases
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/aarch64/gen/_setjmp.S
cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/aarch64/gen/setjmp.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
CVS commit: src/lib/libc/arch/aarch64/gen
Module Name:src
Committed By: skrll
Date: Thu Oct 7 06:44:19 UTC 2021
Modified Files:
src/lib/libc/arch/aarch64/gen: _setjmp.S setjmp.S
Log Message:
Fix the lib/libc/setjmp/t_setjmp:{,_}longjmp_zero test cases
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/aarch64/gen/_setjmp.S
cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/aarch64/gen/setjmp.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/aarch64/gen/_setjmp.S
diff -u src/lib/libc/arch/aarch64/gen/_setjmp.S:1.4 src/lib/libc/arch/aarch64/gen/_setjmp.S:1.5
--- src/lib/libc/arch/aarch64/gen/_setjmp.S:1.4 Sun May 10 14:05:59 2020
+++ src/lib/libc/arch/aarch64/gen/_setjmp.S Thu Oct 7 06:44:18 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: _setjmp.S,v 1.4 2020/05/10 14:05:59 skrll Exp $ */
+/* $NetBSD: _setjmp.S,v 1.5 2021/10/07 06:44:18 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -99,7 +99,8 @@ ENTRY(_longjmp)
mov x29, x4
mov x30, x5
- mov x0, x1
+ cmp x1, #0
+ csinc x0, x1, xzr, ne
ret
/* validation failed, die die die. */
Index: src/lib/libc/arch/aarch64/gen/setjmp.S
diff -u src/lib/libc/arch/aarch64/gen/setjmp.S:1.3 src/lib/libc/arch/aarch64/gen/setjmp.S:1.4
--- src/lib/libc/arch/aarch64/gen/setjmp.S:1.3 Sun May 10 14:05:59 2020
+++ src/lib/libc/arch/aarch64/gen/setjmp.S Thu Oct 7 06:44:18 2021
@@ -1,4 +1,4 @@
-/*.$NetBSD: setjmp.S,v 1.3 2020/05/10 14:05:59 skrll Exp $.*/
+/*.$NetBSD: setjmp.S,v 1.4 2021/10/07 06:44:18 skrll Exp $.*/
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -114,8 +114,11 @@ ENTRY(__longjmp14)
bl _C_LABEL(__sigprocmask14)
ldp x29, x30, [sp, #16]
- ldr x0, [sp, #8]
+ ldr x1, [sp, #8]
add sp, sp, #32
+
+ cmp x1, #0
+ csinc x0, x1, xzr, ne
ret
/* validation failed, die die die. */
Re: CVS commit: src/lib/libc/arch/powerpc/string
On 2021/07/25 6:32, Joerg Sonnenberger wrote: On Sat, Jul 24, 2021 at 05:27:26AM +, Rin Okuyama wrote: Module Name:src Committed By: rin Date: Sat Jul 24 05:27:26 UTC 2021 Modified Files: src/lib/libc/arch/powerpc/string: Makefile.inc Log Message: For evbppc, use C version of bcopy(3), memcpy(3), memcmp(3), and memmove(3) consistently for debug library (*.go) in order to avoid alignment faults for 403. Why do we want to pessimize all evbppc targets just for issues with the 403 design? Well, for kernel, we can readily switch unaffected machines to assembler versions. For userland, we can provide something like libc_ua.so for machines with capability of unaligned access. Some time, I will benchmark whether it is worth the cost. Thanks, rin
Re: CVS commit: src/lib/libc/arch/powerpc/string
On Sat, Jul 24, 2021 at 05:27:26AM +, Rin Okuyama wrote: > Module Name: src > Committed By: rin > Date: Sat Jul 24 05:27:26 UTC 2021 > > Modified Files: > src/lib/libc/arch/powerpc/string: Makefile.inc > > Log Message: > For evbppc, use C version of bcopy(3), memcpy(3), memcmp(3), and > memmove(3) consistently for debug library (*.go) in order to avoid > alignment faults for 403. Why do we want to pessimize all evbppc targets just for issues with the 403 design? Joerg
Re: CVS commit: src/lib/libc/arch/arm
Oops, this is broken. I will fix shortly... rin On 2021/06/30 8:29, Rin Okuyama wrote: Module Name:src Committed By: rin Date: Tue Jun 29 23:29:12 UTC 2021 Modified Files: src/lib/libc/arch/arm/gen: swapcontext.S src/lib/libc/arch/arm/sys: __clone.S Log Message: Align sp to 8-byte boundary as required by EABI. IIUC, this change only affects libc compiled for ``Thumb-mode userland'', which we've not officially supported yet. To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/lib/libc/arch/arm/gen/swapcontext.S cvs rdiff -u -r1.9 -r1.10 src/lib/libc/arch/arm/sys/__clone.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Re: CVS commit: src/lib/libc/arch/aarch64/softfloat
On Sat, Aug 18, 2018 at 07:11:40PM +0900, Ryo Shimizu wrote:
>
> >On Sat, Aug 11, 2018 at 10:06:41AM +, Ryo Shimizu wrote:
> >> Module Name: src
> >> Committed By: ryo
> >> Date: Sat Aug 11 10:06:41 UTC 2018
> >>
> >> Modified Files:
> >>src/lib/libc/arch/aarch64/softfloat: qp.c
> >>
> >> Log Message:
> >> fix multiple definition of __{ge,lt,gt,le,eq,ne,unordt}tf2 in libc and
> >> libgcc.
> >> this fixes the ATF call_once_static, call_once2_static, cxxruntime_static,
> >> static_destructor_static.
>
>
> >This seems just wrong. libgcc shouldn't provide them IMO.
> >Side question, this likely should be replaced with comparetf2.c and
> >friends in libc/compiler_rt/Makefile.
>
> s/libgcc/libc/ ?
>
> I see. then, is it enough to just remove __{ge,lt,gt,le,eq,ne,unordt}tf2 from
> libc?
> currently, clang seems to link libgcc.
libc should be standalone going forward. The libgcc(_s) dependency
should IMO be strongly considered a legacy-only problem and we shouldn't
extend that to new architectures.
That said, I think the main reason this shows up at all is because the
qp.c variant is all-in-one, unlike the code in compiler-rt.
Joerg
Re: CVS commit: src/lib/libc/arch/aarch64/softfloat
>On Sat, Aug 11, 2018 at 10:06:41AM +, Ryo Shimizu wrote:
>> Module Name: src
>> Committed By:ryo
>> Date:Sat Aug 11 10:06:41 UTC 2018
>>
>> Modified Files:
>> src/lib/libc/arch/aarch64/softfloat: qp.c
>>
>> Log Message:
>> fix multiple definition of __{ge,lt,gt,le,eq,ne,unordt}tf2 in libc and
>> libgcc.
>> this fixes the ATF call_once_static, call_once2_static, cxxruntime_static,
>> static_destructor_static.
>This seems just wrong. libgcc shouldn't provide them IMO.
>Side question, this likely should be replaced with comparetf2.c and
>friends in libc/compiler_rt/Makefile.
s/libgcc/libc/ ?
I see. then, is it enough to just remove __{ge,lt,gt,le,eq,ne,unordt}tf2 from
libc?
currently, clang seems to link libgcc.
--
ryo shimizu
Re: CVS commit: src/lib/libc/arch/aarch64/softfloat
On Sat, Aug 11, 2018 at 10:06:41AM +, Ryo Shimizu wrote:
> Module Name: src
> Committed By: ryo
> Date: Sat Aug 11 10:06:41 UTC 2018
>
> Modified Files:
> src/lib/libc/arch/aarch64/softfloat: qp.c
>
> Log Message:
> fix multiple definition of __{ge,lt,gt,le,eq,ne,unordt}tf2 in libc and libgcc.
> this fixes the ATF call_once_static, call_once2_static, cxxruntime_static,
> static_destructor_static.
This seems just wrong. libgcc shouldn't provide them IMO.
Side question, this likely should be replaced with comparetf2.c and
friends in libc/compiler_rt/Makefile.
Joerg
Re: CVS commit: src/lib/libc/arch/aarch64/gen
On 12/02/2018 22:31, Jonathan A. Kollasch wrote: @@ -47,6 +47,6 @@ END(__sigsetjmp14) ENTRY(__siglongjmp14) ldr x3, [x0, #_JB_MAGIC] - tbz x3, #0, _C_LABEL(__longjmp14) + tbnzx3, #0, _C_LABEL(__longjmp14) b _C_LABEL(_longjmp) END(__siglongjmp14) I don't think this is correct. Should compare against _JB_MAGIC_AARCH64__SETJMP / _JB_MAGIC_AARCH64_SETJMP and branch appropriately Nick
Re: CVS commit: src/lib/libc/arch/mips/gen
On Sat, Aug 13, 2016 at 07:49:32AM +, Nick Hudson wrote: > Module Name: src > Committed By: skrll > Date: Sat Aug 13 07:49:32 UTC 2016 > > Modified Files: > src/lib/libc/arch/mips/gen: _resumecontext.S > > Log Message: > PIC_TAILCALL on n32/n64 would mess up GP, so just use SYSTRAP to call > setcontext. > > Fixes tests/lib/libc/sys/t_getcontext.c:setcontext_link Can you leave a comment to revisit this please? It should do the PIC call, but unbreaking it seems more important for now. Joerg
Re: CVS commit: src/lib/libc/arch
On Wed, Jul 15, 2015 at 02:23:40PM +, Antti Kantee wrote: Modified Files: src/lib/libc/arch/i386/gen: Makefile.inc src/lib/libc/arch/x86_64/gen: Makefile.inc Log Message: Remove objects built from C sources comments. Everyone can see they're built from C sources because the source files end in .c (???) That comment matches the comment about objects built from assembler sources 12-13 lines up. I would put it back... -- David A. Holland dholl...@netbsd.org
Re: CVS commit: src/lib/libc/arch/powerpc/sys
On Sat, Feb 01, 2014 at 08:26:21PM +, Matt Thomas wrote: Modified Files: src/lib/libc/arch/powerpc/sys: __syscall.S syscall.S Log Message: Since powerpc passes 8 arguments in registers and the syscall number in r0, shuffle register argument so the kernel won't need to access the stack to retrieve that last argument. +STRONG_ALIAS(syscall, __syscall) Shouldn't that be weak? -- David A. Holland dholl...@netbsd.org
Re: CVS commit: src/lib/libc/arch/alpha/gen
On Tue, Mar 12, 2013 at 09:20:44PM +, Christos Zoulas wrote: In article 20130312193820.a36b017...@cvs.netbsd.org, Martin Husemann source-changes-d@NetBSD.org wrote: is the memset() in longjmp desired? It will just slow down things. I have a bad feeling setting random values to registers, and we will do a system call right afterwards, so I think it is no big deal performance wise. We can carfully null out only the not initialized/semantically important parts otherwise - I dunno. Martin
Re: CVS commit: src/lib/libc/arch/alpha/gen
On Mar 13, 8:33am, mar...@duskware.de (Martin Husemann) wrote: -- Subject: Re: CVS commit: src/lib/libc/arch/alpha/gen | I have a bad feeling setting random values to registers, and we will | do a system call right afterwards, so I think it is no big deal performance | wise. We can carfully null out only the not initialized/semantically | important parts otherwise - I dunno. But most of the structure is explicitly initialized. It is probably better to explicitly set the missing members that calling memset(). christos
Re: CVS commit: src/lib/libc/arch/alpha/gen
On Wed, Mar 13, 2013 at 08:44:03AM -0400, Christos Zoulas wrote: But most of the structure is explicitly initialized. It is probably better to explicitly set the missing members that calling memset(). I have verified that only argument and scratch registers remain uninitialized, and so removed the memset() now. Martin
Re: CVS commit: src/lib/libc/arch/alpha/gen
In article 20130312193820.a36b017...@cvs.netbsd.org, Martin Husemann source-changes-d@NetBSD.org wrote: is the memset() in longjmp desired? It will just slow down things. christos
Re: CVS commit: src/lib/libc/arch/arm/softfloat
Matt Thomas m...@netbsd.org writes: Module Name: src Committed By: matt Date: Sat Jan 26 07:08:14 UTC 2013 Modified Files: src/lib/libc/arch/arm/softfloat: arm-gcc.h Log Message: Appease clang by making 64-bit literals use ULL To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/arm/softfloat/arm-gcc.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/lib/libc/arch/arm/softfloat/arm-gcc.h diff -u src/lib/libc/arch/arm/softfloat/arm-gcc.h:1.3 src/lib/libc/arch/arm/softfloat/arm-gcc.h:1.4 --- src/lib/libc/arch/arm/softfloat/arm-gcc.h:1.3 Sat Dec 24 21:11:16 2005 +++ src/lib/libc/arch/arm/softfloat/arm-gcc.h Sat Jan 26 07:08:14 2013 @@ -1,4 +1,4 @@ -/* $NetBSD: arm-gcc.h,v 1.3 2005/12/24 21:11:16 perry Exp $ */ +/* $NetBSD: arm-gcc.h,v 1.4 2013/01/26 07:08:14 matt Exp $ */ /* --- @@ -71,7 +71,7 @@ name for the 64-bit integer type. Some defined as the identity macro: `#define LIT64( a ) a'. --- */ -#define LIT64( a ) a##LL +#define LIT64( a ) a##ULL #endif That's a bit strange. Don't we have UINT64_C for this? Or is too early for UINT64_C to be defined? -- HE CE3OH...
Re: CVS commit: src/lib/libc/arch/i386/gen
On Fri, Aug 31, 2012 at 08:57:24PM +, Matthias Drochner wrote: Module Name: src Committed By: drochner Date: Fri Aug 31 20:57:24 UTC 2012 Modified Files: src/lib/libc/arch/i386/gen: _lwp.c Log Message: Align the stack to a 16-byte boundary on LWP creation. This is more than required by the ABI, but it makes programs using SSE in a thread work without extra compiler flags or performance hit. Please revert this. It is pointless and broken. Joerg
Re: CVS commit: src/lib/libc/arch/arm/gen
Hi Veleriy, On Wed, Jul 11, 2012 at 11:08:46PM +0400, Valeriy E. Ushakov wrote: Log Message: On the libc/libgcc clashes cleanup that removed divsi3.o from libc, ARM/evbarm was forgotten. This patch fixes it making static binaries possible again! Please, complete this by moving the .S file out of common into libkern. IIRC the file was never there; it was reaching over already to common. With regards, Reinoud
Re: CVS commit: src/lib/libc/arch/arm/gen
On Thu, Jul 12, 2012 at 22:08:19 +0200, Reinoud Zandijk wrote: On Wed, Jul 11, 2012 at 11:08:46PM +0400, Valeriy E. Ushakov wrote: Log Message: On the libc/libgcc clashes cleanup that removed divsi3.o from libc, ARM/evbarm was forgotten. This patch fixes it making static binaries possible again! Please, complete this by moving the .S file out of common into libkern. IIRC the file was never there; it was reaching over already to common. Right, but now the file is no longer common, so it should be under libkern, where it's used. E.g. http://mail-index.netbsd.org/source-changes/2006/04/22/0047.html -uwe
Re: CVS commit: src/lib/libc/arch/arm/gen
On Wed, Jul 11, 2012 at 18:24:27 +, Reinoud Zandijk wrote: Module Name: src Committed By: reinoud Date: Wed Jul 11 18:24:27 UTC 2012 Modified Files: src/lib/libc/arch/arm/gen: Makefile.inc Log Message: On the libc/libgcc clashes cleanup that removed divsi3.o from libc, ARM/evbarm was forgotten. This patch fixes it making static binaries possible again! Please, complete this by moving the .S file out of common into libkern. -uwe
