CVS commit: [netbsd-6] src/sys/arch/x86/include

2015-01-26 Thread Martin Husemann 
Module Name:src
Committed By:   martin
Date:   Mon Jan 26 13:58:05 UTC 2015

Modified Files:
src/sys/arch/x86/include [netbsd-6]: specialreg.h

Log Message:
Pull up the following, requested by msaitoh in ticket #1240:

sys/arch/x86/include/specialreg.h   1.72 via patch

Add CPUID_TO_*() macros to avoid bug. Old macros are kept for compatibility.
See http://mail-index.netbsd.org/port-amd64/2013/11/12/msg001978.html


To generate a diff of this commit:
cvs rdiff -u -r1.55.2.4 -r1.55.2.5 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.55.2.4 src/sys/arch/x86/include/specialreg.h:1.55.2.5
--- src/sys/arch/x86/include/specialreg.h:1.55.2.4	Mon Dec 29 15:31:06 2014
+++ src/sys/arch/x86/include/specialreg.h	Mon Jan 26 13:58:05 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: specialreg.h,v 1.55.2.4 2014/12/29 15:31:06 martin Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.55.2.5 2015/01/26 13:58:05 martin Exp $	*/
 
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
@@ -221,19 +221,39 @@
 	\31 DEADLINE \32 AES	\33 XSAVE	\34 OSXSAVE \
 	\35 AVX	\36 F16C	\37 RDRAND	\40 RAZ
 
-#define CPUID2FAMILY(cpuid)	(((cpuid)  8)  0xf)
-#define CPUID2MODEL(cpuid)	(((cpuid)  4)  0xf)
-#define CPUID2STEPPING(cpuid)	((cpuid)  0xf)
+/* CPUID Fn0001 %eax */
+
+#define CPUID_TO_BASEFAMILY(cpuid)	(((cpuid)  8)  0xf)
+#define CPUID_TO_BASEMODEL(cpuid)	(((cpuid)  4)  0xf)
+#define CPUID_TO_STEPPING(cpuid)	((cpuid)  0xf)
+
+/* Old macros for compatibility */
+#define CPUID2FAMILY(cpuid)	CPUID_TO_BASEFAMILY(cpuid)
+#define CPUID2MODEL(cpuid)	CPUID_TO_BASEMODEL(cpuid)
+#define CPUID2STEPPING(cpuid)	CPUID_TO_STEPPING(cpuid)
 
 /*
- * The Extended family bits should only be inspected when CPUID2FAMILY()
+ * The Extended family bits should only be inspected when CPUID_TO_BASEFAMILY()
  * returns 15. They are use to encode family value 16 to 270 (add 15).
- * The Extended model hits are the high 4 bits of the model.
+ * The Extended model bits are the high 4 bits of the model.
  * They are only valid for family = 15 or family 6 (intel, but all amd
  * family 6 are documented to return zero bits for them).
  */
-#define CPUID2EXTFAMILY(cpuid)	(((cpuid)  20)  0xff)
-#define CPUID2EXTMODEL(cpuid)	(((cpuid)  16)  0xf)
+#define CPUID_TO_EXTFAMILY(cpuid)	(((cpuid)  20)  0xff)
+#define CPUID_TO_EXTMODEL(cpuid)	(((cpuid)  16)  0xf)
+
+/* Old macros for compatibility */
+#define CPUID2EXTFAMILY(cpuid)	CPUID_TO_EXTFAMILY(cpuid)
+#define CPUID2EXTMODEL(cpuid)	CPUID_TO_EXTMODEL(cpuid)
+
+/* The macros for the Display Family and the Display Model */
+#define CPUID_TO_FAMILY(cpuid)	(CPUID_TO_BASEFAMILY(cpuid)	\
+	+ ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f)		\
+		? 0 : CPUID_TO_EXTFAMILY(cpuid)))
+#define CPUID_TO_MODEL(cpuid)	(CPUID_TO_BASEMODEL(cpuid)	\
+	| ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f)		\
+		 (CPUID_TO_BASEFAMILY(cpuid) != 0x06)		\
+		? 0 : (CPUID_TO_EXTMODEL(cpuid)  4)))
 
 /*
  * Intel Deterministic Cache Parameter Leaf

CVS commit: [netbsd-6] src/sys/arch/x86/include

2014-12-29 Thread Martin Husemann 
Module Name:src
Committed By:   martin
Date:   Mon Dec 29 15:14:27 UTC 2014

Modified Files:
src/sys/arch/x86/include [netbsd-6]: cacheinfo.h

Log Message:
Pullup the following revisions, requested by msaitoh in #1219:

sys/arch/x86/include/cacheinfo.h1.14-1.19

Update Intel's cache and TLB descripotr table. This changes the number
of page coloring on some CPUs.
- Add Shared L2 TLB.
- Support prefetch size.
- Add some new TLB and cache entries from the document.
- Fix some entries:
  - Fix 0x0d's DCACHE entry and 0xeb's L3CACHE entry.
  - Desc 0x55 and 0xb1 are Instruction TLB but not fixed to 4K.
  - Desc 0x5a and 0xc0 are Data TLB but not fixed to 4K.
  - Desc 0x57 and 0x59 are 4K fixed DTLB.
  - Fix string of desc 0xc2 and it's not fixed to 4K.
  - Desc 0xca is 4K fixed L2 shared TLB.


To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.13.2.1 src/sys/arch/x86/include/cacheinfo.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.13 src/sys/arch/x86/include/cacheinfo.h:1.13.2.1
--- src/sys/arch/x86/include/cacheinfo.h:1.13	Sun Dec  4 17:00:10 2011
+++ src/sys/arch/x86/include/cacheinfo.h	Mon Dec 29 15:14:26 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: cacheinfo.h,v 1.13 2011/12/04 17:00:10 chs Exp $	*/
+/*	$NetBSD: cacheinfo.h,v 1.13.2.1 2014/12/29 15:14:26 martin Exp $	*/
 
 #ifndef _X86_CACHEINFO_H_
 #define _X86_CACHEINFO_H_
@@ -8,7 +8,10 @@ struct x86_cache_info {
 	uint8_t		cai_desc;
 	uint8_t		cai_associativity;
 	u_int		cai_totalsize; /* #entries for TLB, bytes for cache */
-	u_int		cai_linesize;	/* or page size for TLB */
+	u_int		cai_linesize;	/*
+	 * or page size for TLB,
+	 * or prefetch size
+	 */
 #ifndef _KERNEL
 	const char	*cai_string;
 #endif
@@ -30,8 +33,11 @@ struct x86_cache_info {
 #define CAI_L2_ITLB2	13		/* L2 Instruction TLB (2/4M pages) */
 #define CAI_L2_DTLB	14		/* L2 Data TLB (4K pages) */
 #define CAI_L2_DTLB2	15		/* L2 Data TLB (2/4M pages) */
+#define CAI_L2_STLB	16		/* Shared L2 TLB (4K pages) */
+#define CAI_L2_STLB2	17		/* Shared L2 TLB (4K/2M pages) */
+#define CAI_PREFETCH	18		/* Prefetch */
 
-#define	CAI_COUNT	16
+#define	CAI_COUNT	19
 
 /*
  * AMD Cache Info:
@@ -209,33 +215,55 @@ struct x86_cache_info {
  */
 #define INTEL_CACHE_INFO { \
 __CI_TBL(CAI_ITLB, 0x01,4, 32,4 * 1024, NULL), \
-__CI_TBL(CAI_ITLB, 0xb0,4,128,4 * 1024, NULL), \
 __CI_TBL(CAI_ITLB2,0x02, 0xff,  2, 4 * 1024 * 1024, NULL), \
 __CI_TBL(CAI_DTLB, 0x03,4, 64,4 * 1024, NULL), \
-__CI_TBL(CAI_DTLB, 0xb3,4,128,4 * 1024, NULL), \
-__CI_TBL(CAI_DTLB, 0xb4,4,256,4 * 1024, NULL), \
 __CI_TBL(CAI_DTLB2,0x04,4,  8, 4 * 1024 * 1024, NULL), \
 __CI_TBL(CAI_DTLB2,0x05,4, 32, 4 * 1024 * 1024, NULL), \
+__CI_TBL(CAI_ITLB2,0x0b,4,  4, 4 * 1024 * 1024, NULL), \
+__CI_TBL(CAI_ITLB, 0x4f, 0xff, 32,4 * 1024, NULL), \
 __CI_TBL(CAI_ITLB, 0x50, 0xff, 64,4 * 1024, 4K/4M: 64 entries), \
 __CI_TBL(CAI_ITLB, 0x51, 0xff, 64,4 * 1024, 4K/4M: 128 entries),\
 __CI_TBL(CAI_ITLB, 0x52, 0xff, 64,4 * 1024, 4K/4M: 256 entries),\
-__CI_TBL(CAI_ITLB, 0x55, 0xff, 64,4 * 1024, 2M/4M: 7 entries), \
+__CI_TBL(CAI_ITLB2,0x55, 0xff, 64,4 * 1024, 2M/4M: 7 entries), \
 __CI_TBL(CAI_DTLB2,0x56,4, 16, 4 * 1024 * 1024, NULL), \
-__CI_TBL(CAI_DTLB2,0x57,4, 16,4 * 1024, NULL), \
-__CI_TBL(CAI_DTLB, 0x5a, 0xff, 64,4 * 1024, 2M/4M: 32 entries (L0)), \
+__CI_TBL(CAI_DTLB, 0x57,4, 16,4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB, 0x59, 0xff, 16,4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB2,0x5a, 0xff, 64,4 * 1024, 2M/4M: 32 entries (L0)), \
 __CI_TBL(CAI_DTLB, 0x5b, 0xff, 64,4 * 1024, 4K/4M: 64 entries), \
 __CI_TBL(CAI_DTLB, 0x5c, 0xff, 64,4 * 1024, 4K/4M: 128 entries),\
 __CI_TBL(CAI_DTLB, 0x5d, 0xff, 64,4 * 1024, 4K/4M: 256 entries),\
-__CI_TBL(CAI_ITLB, 0xb1,4, 64,   0, 8 2M/4 4M entries), \
+__CI_TBL(CAI_ITLB, 0x61, 0xff, 48,4 * 1024, NULL), \
+__CI_TBL(CAI_L1_1GBDTLB,0x63,   4,  4,1024*1024 * 1024, NULL), \
+__CI_TBL(CAI_ITLB2,0x76, 0xff,  8, 4 * 1024 * 1024, 2M/4M: 8 entries), \
+__CI_TBL(CAI_DTLB, 0xa0, 0xff, 32,4 * 1024, NULL), \
+__CI_TBL(CAI_ITLB, 0xb0,4,128,4 * 1024, NULL), \
+__CI_TBL(CAI_ITLB2,0xb1,4, 64,   0, 8 2M/4 4M entries), \
 __CI_TBL(CAI_ITLB, 0xb2,4, 64,4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB, 0xb3,4,128,4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB, 0xb4,4,256,4 * 1024, NULL), \
+__CI_TBL(CAI_ITLB, 0xb5,8, 64,4

CVS commit: [netbsd-6] src/sys/arch/x86/include

2014-12-29 Thread Martin Husemann 
Module Name:src
Committed By:   martin
Date:   Mon Dec 29 15:31:06 UTC 2014

Modified Files:
src/sys/arch/x86/include [netbsd-6]: specialreg.h

Log Message:
Pull up the following revisisions, requested by msaitoh in #1220:

sys/arch/x86/include/specialreg.h   1.59-1.71, 1.73-1.81 (patch)

Update x86 special register definitions:
- Add latest CR4 bits.
- Recognize the P1GB and RDTSCP which were AMD-only on Intel HW too.
- Add some missing bit definitions for CPUID2 and those for XCR0.
- Fix CPUID_AMD_FLAGS4 to not try to print bits \41 and \42.
- Correct the comment about the extended family and model bits.
- Add some definitions related to the process extended state
  enumeration.
- Add Intel Structured Extended Feature leaf (Fn_0007).
- Sort CPUID definitions in initial EAX value.
- Add Intel Deterministic Cache Parameter Leaf (CPUID leaf 4).
- Add some AMD Fn8001 extended features %ecx bits definitions.
- s/MXX/MMXX/ because this bit is MMX eXtention.
- Add some definitions for cpu 'extended state' enumeration
  (Fn000d).
- Add Energy Performance Bias bit of Fn_0006 %ecx.
- Add MSR_IA32_PLATFORM_ID (0x017)
- Modify comment.
- Style fix.


To generate a diff of this commit:
cvs rdiff -u -r1.55.2.3 -r1.55.2.4 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.55.2.3 src/sys/arch/x86/include/specialreg.h:1.55.2.4
--- src/sys/arch/x86/include/specialreg.h:1.55.2.3	Mon May  7 16:37:19 2012
+++ src/sys/arch/x86/include/specialreg.h	Mon Dec 29 15:31:06 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: specialreg.h,v 1.55.2.3 2012/05/07 16:37:19 riz Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.55.2.4 2014/12/29 15:31:06 martin Exp $	*/
 
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
@@ -68,20 +68,55 @@
 /* the remaining 7 bits of this register are reserved */
 
 /*
- * bits in the pentiums %cr4 register:
+ * bits in the %cr4 control register:
  */
+#define CR4_VME		0x0001 /* virtual 8086 mode extension enable */
+#define CR4_PVI		0x0002 /* protected mode virtual interrupt enable */
+#define CR4_TSD		0x0004 /* restrict RDTSC instruction to cpl 0 */
+#define CR4_DE		0x0008 /* debugging extension */
+#define CR4_PSE		0x0010 /* large (4MB) page size enable */
+#define CR4_PAE		0x0020 /* physical address extension enable */
+#define CR4_MCE		0x0040 /* machine check enable */
+#define CR4_PGE		0x0080 /* page global enable */
+#define CR4_PCE		0x0100 /* enable RDPMC instruction for all cpls */
+#define CR4_OSFXSR	0x0200 /* enable fxsave/fxrestor and SSE */
+#define CR4_OSXMMEXCPT	0x0400 /* enable unmasked SSE exceptions */
+#define CR4_VMXE	0x2000 /* enable VMX operations */
+#define CR4_SMXE	0x4000 /* enable SMX operations */
+#define CR4_FSGSBASE	0x0001 /* enable *FSBASE and *GSBASE instructions */
+#define CR4_PCIDE	0x0002 /* enable Process Context IDentifiers */
+#define CR4_OSXSAVE	0x0004 /* enable xsave and xrestore */
+#define CR4_SMEP	0x0010 /* enable SMEP support */
+#define CR4_SMAP	0x0020 /* enable SMAP support */
+
+/*
+ * Extended Control Register XCR0
+ */
+#define	XCR0_X87	0x0001	/* x87 FPU/MMX state */
+#define	XCR0_SSE	0x0002	/* SSE state */
+#define	XCR0_YMM_Hi128	0x0004	/* AVX-256 (ymmn registers) */
+#define	XCR0_BNDREGS	0x0008	/* Memory protection ext bounds */
+#define	XCR0_BNDCSR	0x0010	/* Memory protection ext state */
+#define	XCR0_Opmask	0x0020	/* AVX-512 Opmask */
+#define	XCR0_ZMM_Hi256	0x0040	/* AVX-512 upper 256 bits low regs */
+#define	XCR0_Hi16_ZMM	0x0080	/* AVX-512 512 bits upper registers */
+
+/*
+ * Known fpu bits - only these get enabled
+ * I think the XCR0_BNDREGS and XCR0_BNDCSR would need saving on
+ * every context switch.
+ * The save are is sized for all the fields below (max 2680 bytes).
+ */
+#define XCR0_FPU	(XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \
+			XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM)
+
+#define XCR0_BND	(XCR0_BNDREGS | XCR0_BNDCSR)
+
+#define XCR0_FLAGS1	\20 \
+	\1 x87	\2 SSE	\3 AVX \
+	\4 BNDREGS	\5 BNDCSR \
+	\6 Opmask	\7 ZMM_Hi256 \10 Hi16_ZMM
 
-#define CR4_VME	0x0001	/* virtual 8086 mode extension enable */
-#define CR4_PVI 0x0002	/* protected mode virtual interrupt enable */
-#define CR4_TSD 0x0004	/* restrict RDTSC instruction to cpl 0 only */
-#define CR4_DE	0x0008	/* debugging extension */
-#define CR4_PSE	0x0010	/* large (4MB) page size enable */
-#define CR4_PAE 0x0020	/* physical address extension enable */
-#define CR4_MCE	0x0040	/* machine check enable */
-#define CR4_PGE	0x0080	/* page global enable

CVS commit: [netbsd-6] src/sys/arch/x86/include

2012-10-17 Thread Jeff Rizzo 
Module Name:src
Committed By:   riz
Date:   Wed Oct 17 22:39:26 UTC 2012

Modified Files:
src/sys/arch/x86/include [netbsd-6]: lock.h

Log Message:
Pull up following revision(s) (requested by apb in ticket #606):
sys/arch/x86/include/lock.h: revision 1.26
Change =r to =qQ in a register constraint in an asm statement
for a register that is used with the xchgb instruction in the
definition of __cpu_simple_lock_try().  This fixes PR 45673, or at
least works around the gcc bug that might be behind PR 45673.
The output from objdump -d before and after this change is
identical, for the amd64 GENERIC kernel, the i386 GENERIC kernel,
and the i386 MONOLITHIC kernel.


To generate a diff of this commit:
cvs rdiff -u -r1.25 -r1.25.20.1 src/sys/arch/x86/include/lock.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/lock.h
diff -u src/sys/arch/x86/include/lock.h:1.25 src/sys/arch/x86/include/lock.h:1.25.20.1
--- src/sys/arch/x86/include/lock.h:1.25	Thu Jan 15 01:20:31 2009
+++ src/sys/arch/x86/include/lock.h	Wed Oct 17 22:39:26 2012
@@ -1,4 +1,4 @@
-/*	$NetBSD: lock.h,v 1.25 2009/01/15 01:20:31 pooka Exp $	*/
+/*	$NetBSD: lock.h,v 1.25.20.1 2012/10/17 22:39:26 riz Exp $	*/
 
 /*-
  * Copyright (c) 2000, 2006 The NetBSD Foundation, Inc.
@@ -106,7 +106,7 @@ __cpu_simple_lock_try(__cpu_simple_lock_
 
 	val = __SIMPLELOCK_LOCKED;
 	__asm volatile (xchgb %0,(%2) : 
-	=r (val)
+	=qQ (val)
 	:0 (val), r (lockp));
 	__insn_barrier();
 	return val == __SIMPLELOCK_UNLOCKED;