Re: [PATCH] SPI: SSP SPI Controller driver
I think I've asked this question before, but I can't remember if I've gotten an answer. How is this different from the designware spi controller that is already in the tree for medfield and moorestown MID platforms? (drivers/spi/spi-dw-mid.c). Different devices. ... Okay, so I just went looking for the read_SSSR() function because I wanted to know how it was defined. I just discovered that this driver is the same as drivers/spi/spi-pxa2xx.c with a PCI front end bolted on. Quite possible - I wans't aware of that but they may well come from the same origin. +late_initcall(intel_mid_ssp_spi_init); Why late_initcall()? module_init() should be sufficient. Or better yet replace the init and exit functions with module_pci_driver() Thats a legacy of the old SPI code not handling bus and device registration in random orders. So it's no longer needed I believe. Alan -- LogMeIn Rescue: Anywhere, Anytime Remote support for IT. Free Trial Remotely access PCs and mobile devices and provide instant support Improve your efficiency, and focus on delivering more value-add services Discover what IT Professionals Know. Rescue delivers http://p.sf.net/sfu/logmein_12329d2d ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] SPI: SSP SPI Controller driver
Thats what I was trying to understand. If I am not wrong the latency is time related. Why only some platforms / modes need it also the value is not speed dependent. Because the problem was fixed in the later devices. Also the spi core today doesnt have slave mode support thats a different discussion altogether may be we can leave it for now. I'd rather we kept the support in the driver ready for that. Alan -- Monitor your physical, virtual and cloud infrastructure from a single web console. Get in-depth insight into apps, servers, databases, vmware, SAP, cloud infrastructure, etc. Download 30-day Free Trial. Pricing starts from $795 for 25 servers or applications! http://p.sf.net/sfu/zoho_dev2dev_nov ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] SPI: SSP SPI Controller driver
On Wed, 21 Nov 2012 17:44:21 +0530 Shubhrajyoti Datta omaplinuxker...@gmail.com wrote: On Wed, Nov 21, 2012 at 7:46 AM, chao bi chao...@intel.com wrote: + /* Create the PM_QOS request */ + if (drv_context-quirks QUIRKS_USE_PM_QOS) + pm_qos_add_request(drv_context-pm_qos_req, + PM_QOS_CPU_DMA_LATENCY, + PM_QOS_DEFAULT_VALUE); What happens if the flag is not set if it is absolutely necessary for the driver it should not be a configurable option If you read through the code it's set only when the device is Moorestown/Oaktrail based and only in slave mode. It is not necessary in other configurations. Alan -- Monitor your physical, virtual and cloud infrastructure from a single web console. Get in-depth insight into apps, servers, databases, vmware, SAP, cloud infrastructure, etc. Download 30-day Free Trial. Pricing starts from $795 for 25 servers or applications! http://p.sf.net/sfu/zoho_dev2dev_nov ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH RESEND] intel_mid_ssp_spi: Moorestown and Medfield SPI for SSP devices
From: Mathieu SOULARD mathieux.soul...@intel.com
This driver is a fusion of various internal drivers into a single
driver for the SPI slave/master on the Intel Moorestown and Medfield
SSP devices.
Signed-off-by: Mathieu SOULARD mathieux.soul...@intel.com
[Queueing and runtime pm added]
Signed-off-by: Kristen Carlson Accardi kris...@linux.intel.com
[Ported to the -next tree DMA engine]
Signed-off-by: Alan Cox a...@linux.intel.com
---
drivers/spi/Kconfig |8
drivers/spi/Makefile|2
drivers/spi/spi-intel-mid-ssp.c | 1426 +++
drivers/spi/spi-intel-mid-ssp.h | 308
4 files changed, 1743 insertions(+), 1 deletions(-)
create mode 100644 drivers/spi/spi-intel-mid-ssp.c
create mode 100644 drivers/spi/spi-intel-mid-ssp.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 8293658..90b7ef6 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -163,6 +163,14 @@ config SPI_IMX
This enables using the Freescale i.MX SPI controllers in master
mode.
+config SPI_INTEL_MID_SSP
+ tristate SSP SPI controller driver for Intel MID platforms
(EXPERIMENTAL)
+ depends on SPI_MASTER INTEL_MID_DMAC EXPERIMENTAL
+ help
+ This is the unified SSP SPI slave controller driver for the Intel
+ MID platforms, handling Moorestown Medfield, master slave
+ clock mode.
+
config SPI_LM70_LLP
tristate Parallel port adapter for LM70 eval board (DEVELOPMENT)
depends on PARPORT EXPERIMENTAL
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 61c3261..e81757a 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -58,4 +58,4 @@ obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o
obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
-
+obj-$(CONFIG_SPI_INTEL_MID_SSP)+= spi-intel-mid-ssp.o
diff --git a/drivers/spi/spi-intel-mid-ssp.c b/drivers/spi/spi-intel-mid-ssp.c
new file mode 100644
index 000..77bff9f
--- /dev/null
+++ b/drivers/spi/spi-intel-mid-ssp.c
@@ -0,0 +1,1426 @@
+/*
+ * This driver supports Bulverde SSP core used on Intel MID platforms
+ * It supports the SSP of Medfield platforms and handles clock
+ * slave master modes.
+ *
+ * Copyright (c) 2010, Intel Corporation.
+ * Ken Mills ken.k.mi...@intel.com
+ * Sylvain Centelles sylvain.centel...@intel.com
+ * Mathieu SOULARD
+ * Kristen Carlson Accardi kris...@linux.intel.com
+ * Alan Cox a...@linux.intel.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+/*
+ * Note:
+ *
+ * Supports DMA and non-interrupt polled transfers.
+ *
+ */
+
+#include linux/module.h
+#include linux/delay.h
+#include linux/interrupt.h
+#include linux/highmem.h
+#include linux/pci.h
+#include linux/init.h
+#include linux/interrupt.h
+#include linux/dma-mapping.h
+#include linux/intel_mid_dma.h
+#include linux/pm_qos.h
+#include linux/pm_runtime.h
+
+#include linux/spi/spi.h
+#include spi-intel-mid-ssp.h
+
+#define DRIVER_NAME spi-intel-mid-ssp
+
+MODULE_AUTHOR(Ken Mills);
+MODULE_DESCRIPTION(Bulverde SSP core SPI contoller);
+MODULE_LICENSE(GPL);
+
+static const struct pci_device_id pci_ids[];
+
+#ifdef DUMP_RX
+static void dump_trailer(const struct device *dev, char *buf, int len, int sz)
+{
+ int tlen1 = (len sz ? len : sz);
+ int tlen2 = ((len - sz) sz) ? sz : (len - sz);
+ unsigned char *p;
+ static char msg[MAX_SPI_TRANSFER_SIZE];
+
+ memset(msg, '\0', sizeof(msg));
+ p = buf;
+ while (p buf + tlen1)
+ sprintf(msg, %s%02x, msg, (unsigned int)*p++);
+
+ if (tlen2 0) {
+ sprintf(msg, %s ., msg);
+ p = (buf+len) - tlen2;
+ while (p buf + len)
+ sprintf(msg, %s%02x, msg, (unsigned int)*p++);
+ }
+
+ dev_info(dev, DUMP: %p[0:%d ... %d:%d]:%s, buf, tlen1 - 1,
+ len-tlen2, len - 1, msg);
+}
+#endif
+
+static inline u32 is_tx_fifo_empty(struct ssp_driver_context *drv_context)
+{
+ u32 sssr;
+ sssr = read_SSSR(drv_context-ioaddr);
+ if ((sssr SSSR_TFL_MASK) || (sssr SSSR_TNF) == 0)
+ return 0;
+ else
+ return 1
[PATCH] intel_mid_ssp_spi: Moorestown and Medfield SPI for SSP devices
From: Mathieu SOULARD mathieux.soul...@intel.com
This driver is a fusion of various internal drivers into a single
driver for the SPI slave/master on the Intel Moorestown and Medfield
SSP devices.
Signed-off-by: Mathieu SOULARD mathieux.soul...@intel.com
[Queueing and runtime pm added]
Signed-off-by: Kristen Carlson Accardi kris...@linux.intel.com
[Ported to the -next tree DMA engine, stripped Moorestown, further cleanup]
Signed-off-by: Alan Cox a...@linux.intel.com
---
drivers/spi/Kconfig |8
drivers/spi/Makefile|2
drivers/spi/spi-intel-mid-ssp.c | 1426 +++
drivers/spi/spi-intel-mid-ssp.h | 308
4 files changed, 1743 insertions(+), 1 deletions(-)
create mode 100644 drivers/spi/spi-intel-mid-ssp.c
create mode 100644 drivers/spi/spi-intel-mid-ssp.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 3f9a47e..ed8363e 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -163,6 +163,14 @@ config SPI_IMX
This enables using the Freescale i.MX SPI controllers in master
mode.
+config SPI_INTEL_MID_SSP
+ tristate SSP SPI controller driver for Intel MID platforms
(EXPERIMENTAL)
+ depends on SPI_MASTER INTEL_MID_DMAC EXPERIMENTAL
+ help
+ This is the unified SSP SPI slave controller driver for the Intel
+ MID platforms, handling Moorestown Medfield, master slave
+ clock mode.
+
config SPI_LM70_LLP
tristate Parallel port adapter for LM70 eval board (DEVELOPMENT)
depends on PARPORT EXPERIMENTAL
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 61c3261..e81757a 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -58,4 +58,4 @@ obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o
obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
-
+obj-$(CONFIG_SPI_INTEL_MID_SSP)+= spi-intel-mid-ssp.o
diff --git a/drivers/spi/spi-intel-mid-ssp.c b/drivers/spi/spi-intel-mid-ssp.c
new file mode 100644
index 000..77bff9f
--- /dev/null
+++ b/drivers/spi/spi-intel-mid-ssp.c
@@ -0,0 +1,1426 @@
+/*
+ * This driver supports Bulverde SSP core used on Intel MID platforms
+ * It supports the SSP of Medfield platforms and handles clock
+ * slave master modes.
+ *
+ * Copyright (c) 2010, Intel Corporation.
+ * Ken Mills ken.k.mi...@intel.com
+ * Sylvain Centelles sylvain.centel...@intel.com
+ * Mathieu SOULARD
+ * Kristen Carlson Accardi kris...@linux.intel.com
+ * Alan Cox a...@linux.intel.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+/*
+ * Note:
+ *
+ * Supports DMA and non-interrupt polled transfers.
+ *
+ */
+
+#include linux/module.h
+#include linux/delay.h
+#include linux/interrupt.h
+#include linux/highmem.h
+#include linux/pci.h
+#include linux/init.h
+#include linux/interrupt.h
+#include linux/dma-mapping.h
+#include linux/intel_mid_dma.h
+#include linux/pm_qos.h
+#include linux/pm_runtime.h
+
+#include linux/spi/spi.h
+#include spi-intel-mid-ssp.h
+
+#define DRIVER_NAME spi-intel-mid-ssp
+
+MODULE_AUTHOR(Ken Mills);
+MODULE_DESCRIPTION(Bulverde SSP core SPI contoller);
+MODULE_LICENSE(GPL);
+
+static const struct pci_device_id pci_ids[];
+
+#ifdef DUMP_RX
+static void dump_trailer(const struct device *dev, char *buf, int len, int sz)
+{
+ int tlen1 = (len sz ? len : sz);
+ int tlen2 = ((len - sz) sz) ? sz : (len - sz);
+ unsigned char *p;
+ static char msg[MAX_SPI_TRANSFER_SIZE];
+
+ memset(msg, '\0', sizeof(msg));
+ p = buf;
+ while (p buf + tlen1)
+ sprintf(msg, %s%02x, msg, (unsigned int)*p++);
+
+ if (tlen2 0) {
+ sprintf(msg, %s ., msg);
+ p = (buf+len) - tlen2;
+ while (p buf + len)
+ sprintf(msg, %s%02x, msg, (unsigned int)*p++);
+ }
+
+ dev_info(dev, DUMP: %p[0:%d ... %d:%d]:%s, buf, tlen1 - 1,
+ len-tlen2, len - 1, msg);
+}
+#endif
+
+static inline u32 is_tx_fifo_empty(struct ssp_driver_context *drv_context)
+{
+ u32 sssr;
+ sssr = read_SSSR(drv_context-ioaddr);
+ if ((sssr SSSR_TFL_MASK) || (sssr SSSR_TNF) == 0)
+ return 0;
+ else
Re: [PATCH] intel_mid_ssp_spi: Moorestown and Medfield SPI for SSP devices
On Thu, 26 Jan 2012 12:18:41 -0700 Grant Likely grant.lik...@secretlab.ca wrote: On Thu, Jan 26, 2012 at 10:57 AM, Alan Cox a...@lxorguk.ukuu.org.uk wrote: From: Mathieu SOULARD mathieux.soul...@intel.com This driver is a fusion of various internal drivers into a single driver for the SPI slave/master on the Intel Moorestown and Medfield SSP devices. Signed-off-by: Mathieu SOULARD mathieux.soul...@intel.com [Queueing and runtime pm added] Signed-off-by: Kristen Carlson Accardi kris...@linux.intel.com [Ported to the -next tree DMA engine, stripped Moorestown, further cleanup] Signed-off-by: Alan Cox a...@linux.intel.com --- drivers/spi/Kconfig | 8 drivers/spi/Makefile | 2 drivers/spi/spi-intel-mid-ssp.c | 1426 +++ drivers/spi/spi-intel-mid-ssp.h | 308 Haven't reviewed the patch yet, but I've got a question on this. Are there any other users of this header file? Can I just roll it into the .c file if I pick up the patch? They can be rolled together. There is a driver pending for the device in I²S mode but there isn't anything in common. Alan -- Keep Your Developer Skills Current with LearnDevNow! The most comprehensive online learning library for Microsoft developers is just $99.99! Visual Studio, SharePoint, SQL - plus HTML5, CSS3, MVC3, Metro Style Apps, more. Free future releases when you subscribe now! http://p.sf.net/sfu/learndevnow-d2d ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 1/5] spi-topcliff-pch: add tx-memory clear after complete transmitting
On Tue, 04 Oct 2011 18:15:26 +0900 Tomoya MORINAGA tomoya-li...@dsn.lapis-semi.com wrote: Hi Grant, 1 month has passed. You look very busy, right ? We've been long waiting for your accept. Could you review these patch series ? If you've not had a response in a month for something that is a trivial fix to a driver you maintain anyway then send it direct to Linus with a note that Grant hasn't responded for a month. Ditto the GPIO driver. Alan -- All the data continuously generated in your IT infrastructure contains a definitive record of customers, application performance, security threats, fraudulent activity and more. Splunk takes this data and makes sense of it. Business sense. IT sense. Common sense. http://p.sf.net/sfu/splunk-d2dcopy1 ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 4/4] spi/dw_spi: improve the interrupt mode with the batch ops
On Fri, 18 Mar 2011 15:50:56 +0800 Feng Tang feng.t...@intel.com wrote: spi/dw_spi: improve the interrupt mode with the batch ops Look sane to me - only question I have is should the patches have a From: Alek Du ... on them ? -- Colocation vs. Managed Hosting A question and answer guide to determining the best fit for your organization - today and in the future. http://p.sf.net/sfu/internap-sfd2d ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 4/4] spi/dw_spi: improve the interrupt mode with the batch ops
I've strongly requested Alek to make the patches himself, but he is too busy with his project and just give me a .35 version dw_spi.c. So to get it quickly upstream, I manually separate his change, modify a little, combined with mine, test, add some comments and his Signed-off. Ok I was just wondering why the signed-off and from didn't quite match that's all -- Colocation vs. Managed Hosting A question and answer guide to determining the best fit for your organization - today and in the future. http://p.sf.net/sfu/internap-sfd2d ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 0/8] Intel MID SSP SPI merged driver
This series of patches begins with Russ Gorby's posted driver for the Medfield platform with the SSP providing clock and adds back support for Moorestown in the form of additional quirks, as well as basic support for clock slave. This allows the kernel to have one driver which can drive all the SSP units in these modes rather than different drivers per device/mode. --- Russ Gorby (1): Intel SPI master controller driver for the Medfield platform Alan Cox (7): intel_mid_ssp_spi: Implement slave side quirk intel_mid_ssp_spi: Bounce data through the Langwell SRAM when needed intel_mid_ssp_spi: Add the QoS quirk for slave mode intel_mid_ssp_spi: Add chip definitions intel_mid_ssp_spi: Add the uglies needed for Moorestown master mode intel_mid_ssp_spi: Implement the MRST quirk intel_mid_ssp_spi: Re-introduce quirks fields drivers/spi/Kconfig |7 drivers/spi/Makefile|1 drivers/spi/intel_mid_ssp_spi.c | 1747 +++ drivers/spi/intel_mid_ssp_spi_def.h | 149 +++ 4 files changed, 1904 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/intel_mid_ssp_spi.c create mode 100644 drivers/spi/intel_mid_ssp_spi_def.h -- It's 106 miles to Chicago, we've got a full tank of gas, the sat-nav has crashed, it's dark and we're completely lost -- The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE: Pinpoint memory and threading errors before they happen. Find and fix more than 250 security defects in the development cycle. Locate bottlenecks in serial and parallel code that limit performance. http://p.sf.net/sfu/intel-dev2devfeb ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 1/8] Intel SPI master controller driver for the Medfield platform
From: Russ Gorby russ.go...@intel.com SPI master controller driver for the Intel MID platform Medfield This driver uses the Penwell SSP controller and configures it to be a SPI device (spibus 3). This bus supports a single device - the 3G SPI modem that can operate up to 25Mhz. Signed-off-by: Russ Gorby russ.go...@intel.com Signed-off-by: Alan Cox a...@linux.intel.com --- drivers/spi/Kconfig |7 drivers/spi/Makefile|1 drivers/spi/intel_mid_ssp_spi.c | 1507 +++ drivers/spi/intel_mid_ssp_spi_def.h | 139 +++ 4 files changed, 1654 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/intel_mid_ssp_spi.c create mode 100644 drivers/spi/intel_mid_ssp_spi_def.h diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index bb233a9..60ba339 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -178,6 +178,13 @@ config SPI_IMX This enables using the Freescale i.MX SPI controllers in master mode. +config SPI_INTEL_MID_SSP + tristate SSP SPI controller driver for Intel Medfield platform + depends on SPI_MASTER INTEL_MID_DMAC + help + This is the SPI master controller driver for the Intel + Medfield MID platform. + config SPI_LM70_LLP tristate Parallel port adapter for LM70 eval board (DEVELOPMENT) depends on PARPORT EXPERIMENTAL diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 86d1b5f..c64deb9 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.o obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o +obj-$(CONFIG_SPI_INTEL_MID_SSP) += intel_mid_ssp_spi.o # special build for s3c24xx spi driver with fiq support spi_s3c24xx_hw-y := spi_s3c24xx.o diff --git a/drivers/spi/intel_mid_ssp_spi.c b/drivers/spi/intel_mid_ssp_spi.c new file mode 100644 index 000..19c62bc --- /dev/null +++ b/drivers/spi/intel_mid_ssp_spi.c @@ -0,0 +1,1507 @@ +/* + * intel_mid_ssp_spi.c - Penwell SPI master controller driver + * based on pxa2xx.c + * + * Copyright (C) Intel 2010 + * Ken Mills ken.k.mi...@intel.com + * Russ Gorby russ.go...@intel.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, + * USA + * + */ + +#include linux/delay.h +#include linux/highmem.h +#include linux/pci.h +#include linux/dma-mapping.h +#include linux/pm_qos_params.h +#include linux/intel_mid_dma.h +#include linux/interrupt.h +#include linux/spi/spi.h +#include linux/pm_runtime.h +#include intel_mid_ssp_spi_def.h + +#define DRIVER_NAMEintel_mid_ssp_spi +#define PCI_DMAC_MAXDI 2047 +#define PCI_DMAC_ID0x0827 +/* PM QoS define */ +#define MIN_EXIT_LATENCY 20 + +#define TESTMODE_COMMON_MASK 0x00ff +#define TESTMODE_PRIV_MASK 0xff00 +#define TESTMODE_ENABLE_DMA0x01 +#define TESTMODE_ENABLE_POLL 0x02 +#define TESTMODE_ENABLE_LOOPBACK 0x04 +#define TESTMODE_ENABLE_INTR 0x08 +#define TESTMODE(x)(testmode x) +static unsigned int testmode = (TESTMODE_ENABLE_DMA | TESTMODE_ENABLE_POLL); + +module_param(testmode, uint, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(testmode, supply test mode bits); + +MODULE_AUTHOR(Intel); +MODULE_DESCRIPTION(Penwell SPI3 Master Contoller); +MODULE_LICENSE(GPL); + +#define RX_THRESH_DFLT 8 +#define TX_THRESH_DFLT 8 +#define TIMOUT_DFLT1000 + +/* + * For testing SSCR1 changes that require SSP restart, basically + * everything except the service and interrupt enables + */ + +#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ + | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ + | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ + | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ + | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ + | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) + +#define PNWL_SSPSP (SSPSP_FSRT | SSPSP_SFRMWDTH(1) | SSPSP_SFRMP | \ + SSPSP_SCMODE(3)) + +/* + * clock divider + * 8 bpw + * TUR/ROR do not generate interrupt + * SPI mode operation + * SSP enabled + */ +#define
[PATCH 2/8] intel_mid_ssp_spi: Re-introduce quirks fields
From: Alan Cox a...@linux.intel.com
This adds the quirks field to the driver and the flags. We don't yet
implement any of them so we don't confuse the driver.
Signed-off-by: Alan Cox a...@linux.intel.com
---
drivers/spi/intel_mid_ssp_spi.c | 11 ++-
1 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/drivers/spi/intel_mid_ssp_spi.c b/drivers/spi/intel_mid_ssp_spi.c
index 19c62bc..f201edd 100644
--- a/drivers/spi/intel_mid_ssp_spi.c
+++ b/drivers/spi/intel_mid_ssp_spi.c
@@ -125,6 +125,15 @@ struct driver_data {
/* SPI framework hookup */
struct spi_master *master;
+ /* Chip specific quirks */
+ int quirks;
+#define QUIRKS_PLATFORM_MRST 1
+#define QUIRKS_SRAM_ADDITIONAL_CPY 2
+#define QUIRKS_USE_PM_QOS 4
+#define QUIRKS_BIT_BANGING 8
+#define QUIRKS_SPI_SLAVE_CLOCK_MODE16
+#define QUIRKS_PLATFORM_MDFL 32
+
/* SSP register addresses */
unsigned long paddr;
void __iomem *ioaddr;
@@ -137,7 +146,6 @@ struct driver_data {
u32 clear_sr;
u32 mask_sr;
-
/* Current message transfer state info */
struct tasklet_struct poll_transfer;
struct spi_message *cur_msg;
@@ -1163,6 +1171,7 @@ static int intel_mid_ssp_spi_probe(struct pci_dev *pdev,
}
drv_data = spi_master_get_devdata(master);
+ drv_data-quirks = ent-driver_data;
drv_data-master = master;
drv_data-pdev = pdev;
drv_data-pwrstate = PWRSTATE_ON;
--
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[PATCH 3/8] intel_mid_ssp_spi: Implement the MRST quirk
From: Alan Cox a...@linux.intel.com
This quirk simply changes the ID we use to find the DMA controller. Rename
the define and select a different ID IFF the MRST quirk is set
Signed-off-by: Alan Cox a...@linux.intel.com
---
drivers/spi/intel_mid_ssp_spi.c | 12
1 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/intel_mid_ssp_spi.c b/drivers/spi/intel_mid_ssp_spi.c
index f201edd..a7548e7 100644
--- a/drivers/spi/intel_mid_ssp_spi.c
+++ b/drivers/spi/intel_mid_ssp_spi.c
@@ -35,7 +35,8 @@
#define DRIVER_NAMEintel_mid_ssp_spi
#define PCI_DMAC_MAXDI 2047
-#define PCI_DMAC_ID0x0827
+#define PCI_MDFL_DMAC_ID 0x0827
+#define PCI_MRST_DMAC_ID 0x0814
/* PM QoS define */
#define MIN_EXIT_LATENCY 20
@@ -463,15 +464,18 @@ static void intel_mid_ssp_spi_dma_init(struct driver_data
*drv_data)
{
struct intel_mid_dma_slave *rxs, *txs;
dma_cap_mask_t mask;
+ u16 id = PCI_MDFL_DMAC_ID;
if (drv_data-dma_inited)
return;
- drv_data-dmac1 = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DMAC_ID,
+ if (drv_data-quirks QUIRKS_PLATFORM_MRST)
+ id = PCI_MRST_DMAC_ID;
+
+ drv_data-dmac1 = pci_get_device(PCI_VENDOR_ID_INTEL, id,
NULL);
if (!drv_data-dmac1) {
- dev_warn(drv_data-pdev-dev, Can't find DMAC %x,
-PCI_DMAC_ID);
+ dev_warn(drv_data-pdev-dev, Can't find DMAC %x, id);
return;
}
--
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Pinpoint memory and threading errors before they happen.
Find and fix more than 250 security defects in the development cycle.
Locate bottlenecks in serial and parallel code that limit performance.
http://p.sf.net/sfu/intel-dev2devfeb
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[PATCH 4/8] intel_mid_ssp_spi: Add the uglies needed for Moorestown master mode
From: Alan Cox a...@linux.intel.com
We need to support the bitbanging quirk - triggered only on Moorestown so
should have no impact on any Medfield code paths, and not poke around syscfg
which is for Medfield, so if the Moorestown quirk is set skip that.
Also fix a leak of syscfg in the Medfield path
Merged from earlier work making the driver generic by Mathieu SOULARD
mathieux.soul...@intel.com
Signed-off-by: Alan Cox a...@linux.intel.com
---
drivers/spi/intel_mid_ssp_spi.c | 107 +++
drivers/spi/intel_mid_ssp_spi_def.h |3 +
2 files changed, 98 insertions(+), 12 deletions(-)
diff --git a/drivers/spi/intel_mid_ssp_spi.c b/drivers/spi/intel_mid_ssp_spi.c
index a7548e7..6435adc 100644
--- a/drivers/spi/intel_mid_ssp_spi.c
+++ b/drivers/spi/intel_mid_ssp_spi.c
@@ -140,6 +140,7 @@ struct driver_data {
void __iomem *ioaddr;
u32 iolen;
int irq;
+ void __iomem *I2C_ioaddr; /* For Moorestown fixups */
/* SSP masks*/
u32 dma_cr1;
@@ -851,6 +852,68 @@ static void resume_transfer_work(struct work_struct *work)
transfer(msg-spi, msg);
}
+static void start_bitbanging(struct driver_data *drv_data)
+{
+ u32 sssr;
+ u32 count = 0;
+ u32 cr0;
+ void __iomem *i2c_reg = drv_data-I2C_ioaddr;
+ struct device *dev = drv_data-pdev-dev;
+ void __iomem *reg = drv_data-ioaddr;
+ struct chip_data *chip = spi_get_ctldata(drv_data-cur_msg-spi);
+ cr0 = chip-cr0;
+
+ if (ioread32(reg + SSSR) SSSR_NOT_SYNC)
+ dev_warn(dev, SSP clock desynchronized.\n);
+ if (!(ioread32(reg + SSCR0) SSCR0_SSE))
+ dev_warn(dev, in SSCR0, SSP disabled.\n);
+
+ dev_dbg(dev, SSP not ready, start CLK sync\n);
+
+ iowrite32(cr0 ~SSCR0_SSE, reg + SSCR0);
+ iowrite32(0x02010007, reg + SSPSP);
+ iowrite32(chip-timeout, reg + SSTO);
+ iowrite32(cr0, reg + SSCR0);
+
+ /*
+ * This routine uses the DFx block to override the SSP inputs
+ * and outputs allowing us to bit bang SSPSCLK. On Langwell,
+ * we have to generate the clock to clear busy.
+ */
+ iowrite32(0x3, i2c_reg + 4);
+ udelay(10);
+ iowrite32(0x01070034, i2c_reg);
+ udelay(10);
+ iowrite32(0x0099, i2c_reg + 4);
+ udelay(10);
+ iowrite32(0x01070038, i2c_reg);
+ udelay(10);
+ sssr = ioread32(reg + SSSR);
+
+ /* Bit bang the clock until CSS clears */
+ while ((sssr 0x40) count 1) {
+ iowrite32(0x2, i2c_reg + 4);
+ udelay(10);
+ iowrite32(0x01070034, i2c_reg);
+ udelay(10);
+ iowrite32(0x3, i2c_reg + 4);
+ udelay(10);
+ iowrite32(0x01070034, i2c_reg);
+ udelay(10);
+ sssr = ioread32(reg + SSSR);
+ count++;
+ }
+ if (count = 1)
+ dev_err(dev, ERROR in %s : infinite loop \
+ on bit banging. Aborting\n, __func__);
+
+ dev_dbg(dev, ---Bit bang count=%d\n, count);
+
+ iowrite32(0x0, i2c_reg + 4);
+ udelay(10);
+ iowrite32(0x01070038, i2c_reg);
+}
+
static int transfer(struct spi_device *spi, struct spi_message *msg)
{
struct driver_data *drv_data = spi_master_get_devdata(spi-master);
@@ -978,8 +1041,10 @@ static int transfer(struct spi_device *spi, struct
spi_message *msg)
iowrite32(cr0 ~SSCR0_SSE, reg + SSCR0);
/* first set CR1 without interrupt and service enables */
iowrite32(cr1 SSCR1_CHANGE_MASK, reg + SSCR1);
- /* restart the SSP */
- iowrite32(cr0, reg + SSCR0);
+ if (drv_data-quirks QUIRKS_BIT_BANGING)
+ start_bitbanging(drv_data);
+ else /* restart the SSP */
+ iowrite32(cr0, reg + SSCR0);
}
/* after chip select, release the data by enabling service
@@ -1202,6 +1267,16 @@ static int intel_mid_ssp_spi_probe(struct pci_dev *pdev,
status = -ENOMEM;
goto err_free_2;
}
+
+ if (drv_data-quirks QUIRKS_BIT_BANGING) {
+ drv_data-I2C_ioaddr = ioremap_nocache(I2C_BASE_ADDR, 0x10);
+ if (!drv_data-I2C_ioaddr) {
+ status = -ENOMEM;
+ goto err_free_3;
+ }
+ }
+
+
dev_dbg(dev, paddr = : %08lx, drv_data-paddr);
dev_dbg(dev, ioaddr = : %p, drv_data-ioaddr);
dev_dbg(dev, attaching to IRQ: %04x, pdev-irq);
@@ -1213,19 +1288,21 @@ static int intel_mid_ssp_spi_probe(struct pci_dev *pdev,
intel_mid_ssp_spi, drv_data);
if (status 0) {
dev_err(dev, can not get IRQ %d, drv_data-irq);
- goto err_free_3;
+ goto err_free_4;
}
/* get base address of DMA
[PATCH 5/8] intel_mid_ssp_spi: Add chip definitions
From: Alan Cox a...@linux.intel.com
The quirk tweaks so far are sufficient for us to support master mode on all
the devices. Put the PCI identifiers back. If they are in use for other
things the vendor bits will ensure the driver doesn't claim the wrong ones.
Add the missing MODULE tag so we can do autoloading
Based on previous generic driver work by Mathieu SOULARD
mathieux.soul...@intel.com
Signed-off-by: Alan Cox a...@linux.intel.com
---
drivers/spi/intel_mid_ssp_spi.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/intel_mid_ssp_spi.c b/drivers/spi/intel_mid_ssp_spi.c
index 6435adc..c8cd3bb 100644
--- a/drivers/spi/intel_mid_ssp_spi.c
+++ b/drivers/spi/intel_mid_ssp_spi.c
@@ -1574,9 +1574,14 @@ static const struct dev_pm_ops intel_mid_ssp_spi_pm = {
};
static const struct pci_device_id pci_ids[] __devinitdata = {
+ { PCI_VDEVICE(INTEL, 0x0815),
+ QUIRKS_PLATFORM_MRST | QUIRKS_BIT_BANGING },
{ PCI_VDEVICE(INTEL, 0x0816) },
+ { PCI_VDEVICE(INTEL, 0x0825) },
+ { PCI_VDEVICE(INTEL, 0x0832) },
{ }
};
+MODULE_DEVICE_TABLE(pci, pci_ids);
static struct pci_driver intel_mid_ssp_spi_driver = {
.driver = {
--
The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE:
Pinpoint memory and threading errors before they happen.
Find and fix more than 250 security defects in the development cycle.
Locate bottlenecks in serial and parallel code that limit performance.
http://p.sf.net/sfu/intel-dev2devfeb
___
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[PATCH 6/8] intel_mid_ssp_spi: Add the QoS quirk for slave mode
From: Alan Cox a...@linux.intel.com
This is needed for Moorestown. Again we add this so that the default is off
and the code changed is all within if (quirks ).
Baed on previous generic driver work by Mathieu SOULARD
mathieux.soul...@intel.com
Signed-off-by: Alan Cox a...@linux.intel.com
---
drivers/spi/intel_mid_ssp_spi.c | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/intel_mid_ssp_spi.c b/drivers/spi/intel_mid_ssp_spi.c
index c8cd3bb..26e41c2 100644
--- a/drivers/spi/intel_mid_ssp_spi.c
+++ b/drivers/spi/intel_mid_ssp_spi.c
@@ -186,6 +186,8 @@ struct driver_data {
int rxdma_done;
struct callback_param tx_param;
struct callback_param rx_param;
+ /* PM_QOS request (for Moorestown) */
+ struct pm_qos_request_list pm_qos_req;
};
struct chip_data {
@@ -443,6 +445,10 @@ static void dma_transfer_complete(void *arg)
/* Stop getting Time Outs */
iowrite32(0, reg + SSTO);
+ if (drv_data-quirks QUIRKS_USE_PM_QOS)
+ pm_qos_update_request(drv_data-pm_qos_req,
+ PM_QOS_DEFAULT_VALUE);
+
/* release DMA mappings */
unmap_dma_buffers(drv_data, drv_data-cur_msg);
@@ -556,6 +562,8 @@ static void dma_transfer(struct driver_data *drv_data)
struct dma_slave_config *txconf, *rxconf;
struct device *dev = drv_data-pdev-dev;
+ if (drv_data-quirks QUIRKS_USE_PM_QOS)
+ pm_qos_update_request(drv_data-pm_qos_req, MIN_EXIT_LATENCY);
/* get Data Read/Write address */
ssdr_addr = (dma_addr_t)(drv_data-paddr + 0x10);
flag = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
@@ -1186,6 +1194,9 @@ static void cleanup(struct spi_device *spi)
if (drv_data-dma_inited)
intel_mid_ssp_spi_dma_exit(drv_data);
+ /* Remove the PM_QOS request */
+ if (drv_data-quirks QUIRKS_USE_PM_QOS)
+ pm_qos_remove_request(drv_data-pm_qos_req);
kfree(chip);
spi_set_ctldata(spi, NULL);
}
@@ -1332,6 +1343,11 @@ static int intel_mid_ssp_spi_probe(struct pci_dev *pdev,
pci_set_drvdata(pdev, drv_data);
+ /* Create the PM_QOS request */
+ if (drv_data-quirks QUIRKS_USE_PM_QOS)
+ pm_qos_add_request(drv_data-pm_qos_req,
+ PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
+
pm_runtime_set_active(pdev-dev);
pm_runtime_enable(pdev-dev);
pm_runtime_idle(pdev-dev);
--
The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE:
Pinpoint memory and threading errors before they happen.
Find and fix more than 250 security defects in the development cycle.
Locate bottlenecks in serial and parallel code that limit performance.
http://p.sf.net/sfu/intel-dev2devfeb
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[PATCH 7/8] intel_mid_ssp_spi: Bounce data through the Langwell SRAM when needed
From: Alan Cox a...@linux.intel.com
This is required for Moorestown slave mode operation
Based on earlier generic driver work by Mathieu SOULARD
mathieux.soul...@intel.com
Signed-off-by: Alan Cox a...@linux.intel.com
---
drivers/spi/intel_mid_ssp_spi.c | 123 ++-
drivers/spi/intel_mid_ssp_spi_def.h |7 ++
2 files changed, 125 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/intel_mid_ssp_spi.c b/drivers/spi/intel_mid_ssp_spi.c
index 26e41c2..8d7a157 100644
--- a/drivers/spi/intel_mid_ssp_spi.c
+++ b/drivers/spi/intel_mid_ssp_spi.c
@@ -186,8 +186,11 @@ struct driver_data {
int rxdma_done;
struct callback_param tx_param;
struct callback_param rx_param;
- /* PM_QOS request (for Moorestown) */
+ /* PM_QOS request (for Moorestown slave) */
struct pm_qos_request_list pm_qos_req;
+ /* Bounce buffers for DMA (Moorestown slave) */
+ u8 __iomem *virt_addr_sram_tx;
+ u8 __iomem *virt_addr_sram_rx;
};
struct chip_data {
@@ -414,6 +417,29 @@ static void unmap_dma_buffers(struct driver_data *drv_data,
drv_data-dma_mapped = 0;
}
+/**
+ * unmapcopy_dma_buffers() - Unmap the DMA buffers used during the last
transfer.
+ * @drv_data: Pointer to the private driver data
+ *
+ * Handle the buffer unmap when the data is being bounced through Langwell
+ * (Moorestown in slave mode)
+ */
+static void unmapcopy_dma_buffers(struct driver_data *drv_data,
+ struct spi_message *msg)
+{
+ struct device *dev = drv_data-pdev-dev;
+
+ if (unlikely(!drv_data-dma_mapped)) {
+ dev_err(dev, ERROR : DMA buffers not mapped);
+ return;
+ }
+ if (unlikely(msg-is_dma_mapped))
+ return;
+
+ memcpy_fromio(drv_data-rx, drv_data-virt_addr_sram_rx, drv_data-len);
+ drv_data-dma_mapped = 0;
+}
+
static void dma_transfer_complete(void *arg)
{
@@ -450,7 +476,10 @@ static void dma_transfer_complete(void *arg)
PM_QOS_DEFAULT_VALUE);
/* release DMA mappings */
- unmap_dma_buffers(drv_data, drv_data-cur_msg);
+ if (drv_data-quirks QUIRKS_SRAM_ADDITIONAL_CPY)
+ unmapcopy_dma_buffers(drv_data, drv_data-cur_msg);
+ else
+ unmap_dma_buffers(drv_data, drv_data-cur_msg);
/* Update total byte transfered return count actual bytes read */
drv_data-cur_msg-actual_length = drv_data-len;
@@ -461,6 +490,40 @@ static void dma_transfer_complete(void *arg)
}
/**
+ * intel_mid_ssp_spi_map_sram() - Map SRAM
+ * @drv_data: Pointer to the private driver data
+ *
+ * Map the Langwell SRAM used for bouncing on the Moorestown platform in
+ * slave mode.
+ */
+static int intel_mid_ssp_spi_map_sram(struct driver_data *drv_data)
+{
+ struct device *dev = drv_data-pdev-dev;
+
+ drv_data-virt_addr_sram_rx = ioremap_nocache(SRAM_BASE_ADDR,
+ 2 * MAX_SPI_TRANSFER_SIZE);
+ if (drv_data-virt_addr_sram_rx == NULL) {
+ dev_err(dev, Virt_addr_sram_rx is null\n);
+ return -ENOMEM;
+ }
+ drv_data-virt_addr_sram_tx =
+ drv_data-virt_addr_sram_rx + MAX_SPI_TRANSFER_SIZE;
+ return 0;
+}
+
+/**
+ * intel_mid_ssp_spi_unmap_sram() - Map SRAM
+ * @drv_data: Pointer to the private driver data
+ *
+ * Unmap the Langwell SRAM used for bouncing on the Moorestown platform in
+ * slave mode.
+ */
+static void intel_mid_ssp_spi_unmap_sram(struct driver_data *drv_data)
+{
+ iounmap(drv_data-virt_addr_sram_rx);
+}
+
+/**
* intel_mid_ssp_spi_dma_init() - Initialize DMA
* @drv_data: Pointer to the private driver data
*
@@ -486,6 +549,10 @@ static void intel_mid_ssp_spi_dma_init(struct driver_data
*drv_data)
return;
}
+ if (drv_data-quirks QUIRKS_SRAM_ADDITIONAL_CPY)
+ if (intel_mid_ssp_spi_map_sram(drv_data) 0)
+ return;
+
/* 1. init rx channel */
rxs = drv_data-dmas_rx;
rxs-hs_mode = LNW_DMA_HW_HS;
@@ -534,6 +601,9 @@ static void intel_mid_ssp_spi_dma_init(struct driver_data
*drv_data)
free_rxchan:
dev_err(drv_data-pdev-dev, DMA TX Channel Not available);
dma_release_channel(drv_data-rxchan);
+ if (drv_data-quirks QUIRKS_SRAM_ADDITIONAL_CPY)
+ intel_mid_ssp_spi_unmap_sram(drv_data);
+
err_exit:
dev_err(drv_data-pdev-dev, DMA RX Channel Not available);
pci_dev_put(drv_data-dmac1);
@@ -549,6 +619,8 @@ static void intel_mid_ssp_spi_dma_exit(struct driver_data
*drv_data)
return;
dma_release_channel(drv_data-txchan);
dma_release_channel(drv_data-rxchan);
+ if (drv_data-quirks QUIRKS_SRAM_ADDITIONAL_CPY)
+ intel_mid_ssp_spi_unmap_sram(drv_data);
pci_dev_put
[PATCH 8/8] intel_mid_ssp_spi: Implement slave side quirk
From: Alan Cox a...@linux.intel.com
Signed-off-by: Alan Cox a...@linux.intel.com
---
drivers/spi/intel_mid_ssp_spi.c | 32 +---
1 files changed, 21 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/intel_mid_ssp_spi.c b/drivers/spi/intel_mid_ssp_spi.c
index 8d7a157..91976af 100644
--- a/drivers/spi/intel_mid_ssp_spi.c
+++ b/drivers/spi/intel_mid_ssp_spi.c
@@ -93,15 +93,13 @@ MODULE_LICENSE(GPL);
#define PNWL_CR1_MASTER_ROLE 0
#define PNWL_CR1_SLAVE_ROLE(SSCR1_SFRMDIR | SSCR1_SCLKDIR)
-/* MRST SSP must be slave */
-#define PNWL_CR1_ROLE PNWL_CR1_MASTER_ROLE
-#define PNWL_CR1(spi, chip)\
+#define PNWL_CR1(spi, chip, role) \
((chip-enable_loopback ? SSCR1_LBM : 0) | \
((spi-mode SPI_CPHA) ? SSCR1_SPH : 0) | \
((spi-mode SPI_CPOL) ? SSCR1_SPO : 0) | \
SSCR1_SCFR | \
chip-threshold | \
- PNWL_CR1_ROLE)
+ role)
@@ -603,7 +601,7 @@ free_rxchan:
dma_release_channel(drv_data-rxchan);
if (drv_data-quirks QUIRKS_SRAM_ADDITIONAL_CPY)
intel_mid_ssp_spi_unmap_sram(drv_data);
-
+
err_exit:
dev_err(drv_data-pdev-dev, DMA RX Channel Not available);
pci_dev_put(drv_data-dmac1);
@@ -1203,6 +1201,7 @@ static int setup(struct spi_device *spi)
uint rx_thres = RX_THRESH_DFLT;
u32 clk_div;
struct driver_data *drv_data = spi_master_get_devdata(spi-master);
+ int role = PNWL_CR1_MASTER_ROLE;
if (drv_data-pwrstate == PWRSTATE_OFF) {
dev_dbg(drv_data-pdev-dev, setup: busy, pwrstate:%d,
@@ -1272,15 +1271,20 @@ static int setup(struct spi_device *spi)
set_dma_width(drv_data, spi-bits_per_word);
}
- chip-speed_hz = spi-max_speed_hz;
- clk_div = ssp_get_clk_div(chip-speed_hz);
+ if (drv_data-quirks QUIRKS_SPI_SLAVE_CLOCK_MODE) {
+ role = PNWL_CR1_SLAVE_ROLE;
+ clk_div = 1;
+ } else {
+ chip-speed_hz = spi-max_speed_hz;
+ clk_div = ssp_get_clk_div(chip-speed_hz);
+ }
chip-threshold = (SSCR1_RxTresh(rx_thres) SSCR1_RFT) |
(SSCR1_TxTresh(tx_thres) SSCR1_TFT);
chip-bits_per_word = spi-bits_per_word;
chip-cr0 = PNWL_CR0(clk_div, spi-bits_per_word, spi, chip);
- chip-cr1 = PNWL_CR1(spi, chip);
+ chip-cr1 = PNWL_CR1(spi, chip, role);
dev_dbg(spi-dev,
KHz:%d bpw:%d mode:%d dma:%d poll:%d loop:%d cr0:%x cr1:%x,
@@ -1340,13 +1344,11 @@ static int intel_mid_ssp_spi_probe(struct pci_dev *pdev,
dev_info(dev, No Vendor Specific PCI capability);
goto err_abort_probe;
}
- if ((SSP_CFG_GET_MODE(ssp_cfg) != SSP_CFG_SPI_MODE_ID) ||
- SSP_CFG_IS_SPI_SLAVE(ssp_cfg)) {
+ if (SSP_CFG_GET_MODE(ssp_cfg) != SSP_CFG_SPI_MODE_ID) {
dev_info(dev, Unsupported SSP mode (%02xh),
ssp_cfg);
goto err_abort_probe;
}
-
dev_info(pdev-dev, found PCI SSP controller(ID: %04xh:%04xh
cfg: %02xh), pdev-vendor, pdev-device, ssp_cfg);
@@ -1371,6 +1373,14 @@ static int intel_mid_ssp_spi_probe(struct pci_dev *pdev,
drv_data-wq = create_workqueue(DRIVER_NAME);
INIT_WORK(drv_data-resume_transfer_work, resume_transfer_work);
+ if (SSP_CFG_IS_SPI_SLAVE(ssp_cfg)) {
+ dev_warn(dev, Slave clock mode is experimental);
+ drv_data-quirks |= QUIRKS_SPI_SLAVE_CLOCK_MODE;
+ if (drv_data-quirks QUIRKS_PLATFORM_MRST)
+ drv_data-quirks |= QUIRKS_USE_PM_QOS |
+ QUIRKS_SRAM_ADDITIONAL_CPY;
+ }
+
master-mode_bits = SPI_CPOL | SPI_CPHA;
master-bus_num = SSP_CFG_GET_SPI_BUS_NB(ssp_cfg);
master-num_chipselect = 1;
--
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Re: [PATCH 1/1] spi: intel_mid_ssp_spi: new SPI driver for intel Medfield platform
On Thu, 3 Feb 2011 13:28:00 + Mark Brown broo...@opensource.wolfsonmicro.com wrote: On Wed, Feb 02, 2011 at 10:40:54PM +, Alan Cox wrote: And this is the unified one that handles all the devices, but I gather may need some fixing/test work on Medfield. I've got the same question here as I had with Russ' patch: it looks like there's some overlap with the SSP ports used for audio (it's just a generic programmable serial port so even if it's not normally used for audio that's a possiblity), how is that handled? The SSP has PCI configuration indicating how it is being assigned, which is in vendor capability byte 6. The low 3 bits indicte the mode, where mode 1 is an SPI master/slave, and in that case bit 6 is set for a slave. The SSP/SPI driver will only grab ports that have been assigned to that purpose as part of the system design. I'm just putting the other bits from the generic driver back into the more featured/tested specific driver that Russ posted. Alan -- Special Offer-- Download ArcSight Logger for FREE (a $49 USD value)! Finally, a world-class log management solution at an even better price-free! Download using promo code Free_Logger_4_Dev2Dev. Offer expires February 28th, so secure your free ArcSight Logger TODAY! http://p.sf.net/sfu/arcsight-sfd2d ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 1/1] spi: intel_mid_ssp_spi: new SPI driver for intel Medfield platform
On Wed, 2 Feb 2011 13:01:52 -0800 Russ Gorby russ.go...@intel.com wrote: SPI master controller driver for the Intel MID platform Medfield This driver uses the Penwell SSP controller and configures it to be a SPI device (spibus 3). This bus supports a single device - the 3G SPI modem that can operate up to 25Mhz. NAK this. We have an existing development driver that covers 0x0815, 0x0816, 0x0825, 0x0832 in a single driver which needs tidying up and double checking on all the relevant Medfield and Moorestown devices and is based on work done by Mathieu Soulard. All these devices can be handled by a single driver, and should be. Alan -- Special Offer-- Download ArcSight Logger for FREE (a $49 USD value)! Finally, a world-class log management solution at an even better price-free! Download using promo code Free_Logger_4_Dev2Dev. Offer expires February 28th, so secure your free ArcSight Logger TODAY! http://p.sf.net/sfu/arcsight-sfd2d ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH] dw_spi: add DMA support
From: Feng Tang feng.t...@intel.com
dw_spi driver in upstream only supports PIO mode, and this patch
will support it to cowork with the Designware DMA controller used
on Intel Moorestown platform
It has been tested with a Option GTM501L 3G modem, to use DMA mode,
DMA controller 2 of Moorestown has to be enabled
Signed-off-by: Feng Tang feng.t...@intel.com
[Typo fix and renames to match intel_mid_dma renaming]
Signed-off-by: Vinod Koul vinod.k...@intel.com
[Clean up]
Signed-off-by: Feng Tang feng.t...@intel.com
[Fix timing delay, add cpu_relax]
Signed-off-by: Arjan van de Ven ar...@linux.intel.com
Signed-off-by: Alan Cox a...@linux.intel.com
---
drivers/spi/Kconfig|4 +
drivers/spi/Makefile |3 -
drivers/spi/dw_spi.c | 48 +
drivers/spi/dw_spi_mid.c | 246
drivers/spi/dw_spi_pci.c | 14 ++-
include/linux/spi/dw_spi.h | 15 +++
6 files changed, 305 insertions(+), 25 deletions(-)
create mode 100644 drivers/spi/dw_spi_mid.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 82e45cf..6e6a638 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -404,6 +404,10 @@ config SPI_DW_PCI
tristate PCI interface driver for DW SPI core
depends on SPI_DESIGNWARE PCI
+config SPI_DW_MID_DMA
+ bool DMA support for DW SPI controller on Intel Moorestown platform
+ depends on SPI_DW_PCI INTEL_MID_DMAC
+
config SPI_DW_MMIO
tristate Memory-mapped io interface driver for DW SPI core
depends on SPI_DESIGNWARE HAVE_CLK
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index b427c2e..4949370 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -17,7 +17,8 @@ obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
obj-$(CONFIG_SPI_COLDFIRE_QSPI)+= coldfire_qspi.o
obj-$(CONFIG_SPI_DAVINCI) += davinci_spi.o
obj-$(CONFIG_SPI_DESIGNWARE) += dw_spi.o
-obj-$(CONFIG_SPI_DW_PCI) += dw_spi_pci.o
+obj-$(CONFIG_SPI_DW_PCI) += dw_spi_midpci.o
+dw_spi_midpci-objs := dw_spi_pci.o dw_spi_mid.o
obj-$(CONFIG_SPI_DW_MMIO) += dw_spi_mmio.o
obj-$(CONFIG_SPI_EP93XX) += ep93xx_spi.o
obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
diff --git a/drivers/spi/dw_spi.c b/drivers/spi/dw_spi.c
index 9043931..69cc223 100644
--- a/drivers/spi/dw_spi.c
+++ b/drivers/spi/dw_spi.c
@@ -164,20 +164,23 @@ static inline void mrst_spi_debugfs_remove(struct dw_spi
*dws)
static void wait_till_not_busy(struct dw_spi *dws)
{
- unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
+ unsigned long end = jiffies + 1 + usecs_to_jiffies(5000);
while (time_before(jiffies, end)) {
if (!(dw_readw(dws, sr) SR_BUSY))
return;
+ cpu_relax();
}
dev_err(dws-master-dev,
- DW SPI: Status keeps busy for 1000us after a read/write!\n);
+ DW SPI: Status keeps busy for 5000us after a read/write!\n);
}
static void flush(struct dw_spi *dws)
{
- while (dw_readw(dws, sr) SR_RF_NOT_EMPT)
+ while (dw_readw(dws, sr) SR_RF_NOT_EMPT) {
dw_readw(dws, dr);
+ cpu_relax();
+ }
wait_till_not_busy(dws);
}
@@ -285,8 +288,10 @@ static void *next_transfer(struct dw_spi *dws)
*/
static int map_dma_buffers(struct dw_spi *dws)
{
- if (!dws-cur_msg-is_dma_mapped || !dws-dma_inited
- || !dws-cur_chip-enable_dma)
+ if (!dws-cur_msg-is_dma_mapped
+ || !dws-dma_inited
+ || !dws-cur_chip-enable_dma
+ || !dws-dma_ops)
return 0;
if (dws-cur_transfer-tx_dma)
@@ -338,7 +343,7 @@ static void int_error_stop(struct dw_spi *dws, const char
*msg)
tasklet_schedule(dws-pump_transfers);
}
-static void transfer_complete(struct dw_spi *dws)
+void dw_spi_xfer_done(struct dw_spi *dws)
{
/* Update total byte transfered return count actual bytes read */
dws-cur_msg-actual_length += dws-len;
@@ -353,6 +358,7 @@ static void transfer_complete(struct dw_spi *dws)
} else
tasklet_schedule(dws-pump_transfers);
}
+EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
static irqreturn_t interrupt_transfer(struct dw_spi *dws)
{
@@ -384,7 +390,7 @@ static irqreturn_t interrupt_transfer(struct dw_spi *dws)
if (dws-tx_end dws-tx)
spi_umask_intr(dws, SPI_INT_TXEI);
else
- transfer_complete(dws);
+ dw_spi_xfer_done(dws);
}
return IRQ_HANDLED;
@@ -414,11 +420,7 @@ static void poll_transfer(struct dw_spi *dws)
while (dws-write(dws))
dws-read(dws);
- transfer_complete(dws);
-}
-
-static void dma_transfer(struct dw_spi *dws, int cs_change)
-{
+ dw_spi_xfer_done(dws
Re: [PATCH] input: spi: Driver for SPI data stream driven vibrator
On Mon, 8 Nov 2010 12:08:07 +0100
ilkka.koski...@nokia.com wrote:
Hi,
From: ext Alan Cox [mailto:a...@lxorguk.ukuu.org.uk]
Sent: 08 November, 2010 01:52
+ datalen = p-custom_len * sizeof(p-custom_data[0]);
signed
+ if (datalen MAX_EFFECT_SIZE) {
unsigned
It should be unsigned. I'll fix it.
+ memcpy(einfo-buf, p-custom_data, datalen);
ungood
Yep, that's clearly wrong too. Should be copy_from_user() I suppose.
That I hadn't considered - and I'm not sure whether the caller is passed
a kernel copy or not. The problem I was looking at was just the signed
case
datalen 0
if (datalen MAX ..)
Nope
memcpy(kernel, mysource, vastly more than intended (unsigned))
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Re: [PATCH] input: spi: Driver for SPI data stream driven vibrator
+ datalen = p-custom_len * sizeof(p-custom_data[0]);
signed
+ if (datalen MAX_EFFECT_SIZE) {
unsigned
+ memcpy(einfo-buf, p-custom_data, datalen);
ungood
--
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Re: [PATCH] input: spi: Driver for SPI data stream driven vibrator
The driver could, of course, calculate the bit streams with help of board specific functions. It was just thought that tuning vibration device would be a lot easier, if we could just modify the bit streams provided by user space application. In fact, the bit stream basically consists of series of PWM pulses that are fed to the vibra. Perhaps, calculating the waveforms in the driver at probe time would be the most natural choice :\ Or assuming its a trivial conversion accepting them in a standard format and doing a quick pass across them ? (and failing that adding and documenting the format..) -- Nokia and ATT present the 2010 Calling All Innovators-North America contest Create new apps games for the Nokia N8 for consumers in U.S. and Canada $10 million total in prizes - $4M cash, 500 devices, nearly $6M in marketing Develop with Nokia Qt SDK, Web Runtime, or Java and Publish to Ovi Store http://p.sf.net/sfu/nokia-dev2dev ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] input: spi: Driver for SPI data stream driven vibrator
+ if (!einfo-buf) {
+ einfo-buf = kzalloc(datalen, GFP_KERNEL | GFP_DMA);
+ if (!einfo-buf) {
+ ret = -ENOMEM;
+ goto exit;
+ }
+ }
+
+ memcpy(einfo-buf, p-custom_data, datalen);
It looks like raw data from userspace is being passed on to the
device. Is this sane? Is there already a data format used by other
vibration/feedback devices that should be used here instead and
translated into the form expected by the hardware?
It also seems to be using GFP_DMA not dma_alloc functions which looks a
bit odd and certainly isn't portable.
--
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Re: [PATCH] dw_spi: add DMA support
There *is* a generic runtime channel control interface as of kernel 2.6.36. Compare to this snippet from the PL022 DMA Not when this driver was done. support that was merged into becoming 2.6.37 a day ago or so (behold the beauty in drivers/spi/amba-pl022.c): Funnily enough I've already moved to using the proper fields in the next version of all the DMA using patches so that bit is cool, but I've not done the other stuff you then point out so I'll go through your example and tidy up. -- Nokia and ATT present the 2010 Calling All Innovators-North America contest Create new apps games for the Nokia N8 for consumers in U.S. and Canada $10 million total in prizes - $4M cash, 500 devices, nearly $6M in marketing Develop with Nokia Qt SDK, Web Runtime, or Java and Publish to Ovi Store http://p.sf.net/sfu/nokia-dev2dev ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH v3 01/12] misc: add driver for sequencer serial port
On Thu, 21 Oct 2010 17:01:02 -0400 Cyril Chemparathy cy...@ti.com wrote: TI's sequencer serial port (TI-SSP) is a jack-of-all-trades type of serial port device. It has a built-in programmable execution engine that can be programmed to operate as almost any serial bus (I2C, SPI, EasyScale, and others). This patch adds a driver for this controller device. The driver does not expose a user-land interface. Protocol drivers built on top of this layer are expected to remain in-kernel. I suspect the driver belongs with the mfd drivers not with drivers/misc ? otherwise it looks very nice. -- Nokia and ATT present the 2010 Calling All Innovators-North America contest Create new apps games for the Nokia N8 for consumers in U.S. and Canada $10 million total in prizes - $4M cash, 500 devices, nearly $6M in marketing Develop with Nokia Qt SDK, Web Runtime, or Java and Publish to Ovi Store http://p.sf.net/sfu/nokia-dev2dev ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH] intel_mid_ssp_spi: Moorestown and Medfield SPI for SSP devices
This is a first pass submit of the SSP SPI driver for the Intel MID
platforms (Moorestown and Medfield).
From: Mathieu SOULARD mathieux.soul...@intel.com
This driver is a fusion of various internal drivers into a single
driver for the SPI slave/master on the Intel Moorestown and Medfield
SSP devices.
Signed-off-by: Mathieu SOULARD mathieux.soul...@intel.com
[Ported to the -next tree DMA engine]
Signed-off-by: Alan Cox a...@linux.intel.com
---
drivers/spi/Kconfig |8
drivers/spi/Makefile|1
drivers/spi/intel_mid_ssp_spi.c | 1403 +++
drivers/spi/intel_mid_ssp_spi.h | 321 +
4 files changed, 1733 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/intel_mid_ssp_spi.c
create mode 100644 drivers/spi/intel_mid_ssp_spi.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 78f9fd0..82e45cf 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -167,6 +167,14 @@ config SPI_IMX
This enables using the Freescale i.MX SPI controllers in master
mode.
+config SPI_INTEL_MID_SSP
+ tristate SSP SPI controller driver for Intel MID platforms
(EXPERIMENTAL)
+ depends on SPI_MASTER INTEL_MID_DMAC EXPERIMENTAL
+ help
+ This is the unified SSP SPI slave controller driver for the Intel
+ MID platforms, handling Moorestown Medfield, master slave
+ clock mode.
+
config SPI_LM70_LLP
tristate Parallel port adapter for LM70 eval board (DEVELOPMENT)
depends on PARPORT EXPERIMENTAL
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 8bc1a5a..b427c2e 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_SPI_DW_MMIO) += dw_spi_mmio.o
obj-$(CONFIG_SPI_EP93XX) += ep93xx_spi.o
obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
obj-$(CONFIG_SPI_IMX) += spi_imx.o
+obj-$(CONFIG_SPI_INTEL_MID_SSP)+= intel_mid_ssp_spi.o
obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o
diff --git a/drivers/spi/intel_mid_ssp_spi.c b/drivers/spi/intel_mid_ssp_spi.c
new file mode 100644
index 000..2d6d881
--- /dev/null
+++ b/drivers/spi/intel_mid_ssp_spi.c
@@ -0,0 +1,1403 @@
+/*
+ * intel_mid_ssp_spi.c
+ * This driver supports Bulverde SSP core used on Intel MID platforms
+ * It supports SSP of Moorestown Medfield platforms and handles clock
+ * slave master modes.
+ *
+ * Copyright (c) 2010, Intel Corporation.
+ * Ken Mills ken.k.mi...@intel.com
+ * Sylvain Centelles sylvain.centel...@intel.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+/*
+ * Note:
+ *
+ * Supports DMA and non-interrupt polled transfers.
+ *
+ */
+
+#include linux/delay.h
+#include linux/interrupt.h
+#include linux/highmem.h
+#include linux/pci.h
+#include linux/init.h
+#include linux/interrupt.h
+#include linux/dma-mapping.h
+#include linux/intel_mid_dma.h
+#include linux/pm_qos_params.h
+
+#include linux/spi/spi.h
+#include intel_mid_ssp_spi.h
+
+#define DRIVER_NAME intel_mid_ssp_spi_unified
+
+MODULE_AUTHOR(Ken Mills);
+MODULE_DESCRIPTION(Bulverde SSP core SPI contoller);
+MODULE_LICENSE(GPL);
+
+static const struct pci_device_id pci_ids[];
+
+#ifdef DUMP_RX
+static void dump_trailer(const struct device *dev, char *buf, int len, int sz)
+{
+ int tlen1 = (len sz ? len : sz);
+ int tlen2 = ((len - sz) sz) ? sz : (len - sz);
+ unsigned char *p;
+ static char msg[MAX_SPI_TRANSFER_SIZE];
+
+ memset(msg, '\0', sizeof(msg));
+ p = buf;
+ while (p buf + tlen1)
+ sprintf(msg, %s%02x, msg, (unsigned int)*p++);
+
+ if (tlen2 0) {
+ sprintf(msg, %s ., msg);
+ p = (buf+len) - tlen2;
+ while (p buf + len)
+ sprintf(msg, %s%02x, msg, (unsigned int)*p++);
+ }
+
+ dev_info(dev, DUMP: %p[0:%d ... %d:%d]:%s, buf, tlen1 - 1,
+ len-tlen2, len - 1, msg);
+}
+#endif
+
+static inline u32 is_tx_fifo_empty(struct ssp_driver_context *drv_context)
+{
+ u32 sssr;
+ sssr = read_SSSR(drv_context-ioaddr);
+ if ((sssr SSSR_TFL_MASK) || (sssr SSSR_TNF) == 0)
+ return
[PATCH] dw_spi: add DMA support
From: Feng Tang feng.t...@intel.com
dw_spi driver in upstream only supports PIO mode, and this patch
will support it to cowork with the Designware DMA controller used
on Intel Moorestown platform
It has been tested with a Option GTM501L 3G modem, to use DMA mode,
DMA controller 2 of Moorestown has to be enabled
Signed-off-by: Feng Tang feng.t...@intel.com
[Typo fix and renames to match intel_mid_dma renaming]
Signed-off-by: Vinod Koul vinod.k...@intel.com
[Clean up]
Signed-off-by: Feng Tang feng.t...@intel.com
[Fix timing delay, add cpu_relax]
Signed-off-by: Arjan van de Ven ar...@linux.intel.com
Signed-off-by: Alan Cox a...@linux.intel.com
---
drivers/spi/Kconfig|4 +
drivers/spi/Makefile |3 -
drivers/spi/dw_spi.c | 48 +
drivers/spi/dw_spi_mid.c | 243
drivers/spi/dw_spi_pci.c | 14 ++-
include/linux/spi/dw_spi.h | 15 +++
6 files changed, 302 insertions(+), 25 deletions(-)
create mode 100644 drivers/spi/dw_spi_mid.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 82e45cf..6e6a638 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -404,6 +404,10 @@ config SPI_DW_PCI
tristate PCI interface driver for DW SPI core
depends on SPI_DESIGNWARE PCI
+config SPI_DW_MID_DMA
+ bool DMA support for DW SPI controller on Intel Moorestown platform
+ depends on SPI_DW_PCI INTEL_MID_DMAC
+
config SPI_DW_MMIO
tristate Memory-mapped io interface driver for DW SPI core
depends on SPI_DESIGNWARE HAVE_CLK
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index b427c2e..4949370 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -17,7 +17,8 @@ obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
obj-$(CONFIG_SPI_COLDFIRE_QSPI)+= coldfire_qspi.o
obj-$(CONFIG_SPI_DAVINCI) += davinci_spi.o
obj-$(CONFIG_SPI_DESIGNWARE) += dw_spi.o
-obj-$(CONFIG_SPI_DW_PCI) += dw_spi_pci.o
+obj-$(CONFIG_SPI_DW_PCI) += dw_spi_midpci.o
+dw_spi_midpci-objs := dw_spi_pci.o dw_spi_mid.o
obj-$(CONFIG_SPI_DW_MMIO) += dw_spi_mmio.o
obj-$(CONFIG_SPI_EP93XX) += ep93xx_spi.o
obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
diff --git a/drivers/spi/dw_spi.c b/drivers/spi/dw_spi.c
index 9043931..69cc223 100644
--- a/drivers/spi/dw_spi.c
+++ b/drivers/spi/dw_spi.c
@@ -164,20 +164,23 @@ static inline void mrst_spi_debugfs_remove(struct dw_spi
*dws)
static void wait_till_not_busy(struct dw_spi *dws)
{
- unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
+ unsigned long end = jiffies + 1 + usecs_to_jiffies(5000);
while (time_before(jiffies, end)) {
if (!(dw_readw(dws, sr) SR_BUSY))
return;
+ cpu_relax();
}
dev_err(dws-master-dev,
- DW SPI: Status keeps busy for 1000us after a read/write!\n);
+ DW SPI: Status keeps busy for 5000us after a read/write!\n);
}
static void flush(struct dw_spi *dws)
{
- while (dw_readw(dws, sr) SR_RF_NOT_EMPT)
+ while (dw_readw(dws, sr) SR_RF_NOT_EMPT) {
dw_readw(dws, dr);
+ cpu_relax();
+ }
wait_till_not_busy(dws);
}
@@ -285,8 +288,10 @@ static void *next_transfer(struct dw_spi *dws)
*/
static int map_dma_buffers(struct dw_spi *dws)
{
- if (!dws-cur_msg-is_dma_mapped || !dws-dma_inited
- || !dws-cur_chip-enable_dma)
+ if (!dws-cur_msg-is_dma_mapped
+ || !dws-dma_inited
+ || !dws-cur_chip-enable_dma
+ || !dws-dma_ops)
return 0;
if (dws-cur_transfer-tx_dma)
@@ -338,7 +343,7 @@ static void int_error_stop(struct dw_spi *dws, const char
*msg)
tasklet_schedule(dws-pump_transfers);
}
-static void transfer_complete(struct dw_spi *dws)
+void dw_spi_xfer_done(struct dw_spi *dws)
{
/* Update total byte transfered return count actual bytes read */
dws-cur_msg-actual_length += dws-len;
@@ -353,6 +358,7 @@ static void transfer_complete(struct dw_spi *dws)
} else
tasklet_schedule(dws-pump_transfers);
}
+EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
static irqreturn_t interrupt_transfer(struct dw_spi *dws)
{
@@ -384,7 +390,7 @@ static irqreturn_t interrupt_transfer(struct dw_spi *dws)
if (dws-tx_end dws-tx)
spi_umask_intr(dws, SPI_INT_TXEI);
else
- transfer_complete(dws);
+ dw_spi_xfer_done(dws);
}
return IRQ_HANDLED;
@@ -414,11 +420,7 @@ static void poll_transfer(struct dw_spi *dws)
while (dws-write(dws))
dws-read(dws);
- transfer_complete(dws);
-}
-
-static void dma_transfer(struct dw_spi *dws, int cs_change)
-{
+ dw_spi_xfer_done(dws
Re: [spi-devel-general] [PATCH v1 3/4] max3100: adds console support for MAX3100
1) latency on rx chars becomes very high because we can process incoming transfers only after a full 8 byte (or whatever the spi transfer dimension is). For a 9600 this is too much. There I would partly disagree. Fixing the spi driver clearly makes sense but the serial driver should be batching better. Is there a reason the driver couldn't adjust the size based upon the tty speed when getting a termios request ? 2) even worse is that we can do flow control decision only on such boundary. For serial flow control it doesn't matter, its implicitly asynchronous and if you only turn the fifo on at high speed you response time will be reasonably bounded. 3) this is not reliable: think of what happens if the actual SPI transfer speed we get will be slower that the one we requested. We won't be emptying the RX buffer fastly enough even if could. Consoles are not usually balanced for I/O. I grant you probably don't want to be using full fifo sized blocks but I'm not sure I understand why there is a problem below that ? Alan -- Download Intel#174; Parallel Studio Eval Try the new software tools for yourself. Speed compiling, find bugs proactively, and fine-tune applications for parallel performance. See why Intel Parallel Studio got high marks during beta. http://p.sf.net/sfu/intel-sw-dev ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [spi-devel-general] [RFC][PATCH v3] serial: spi: add spi-uart driver for Maxim 3110
On Wed, 24 Feb 2010 13:11:30 +0800 Feng Tang feng.t...@intel.com wrote: Hi All, Here is a driver for Maxim 3110 SPI-UART device, please help to review. It has been validated with Designware SPI controller (drivers/spi: dw_spi.c dw_spi_pci.c). It supports polling and IRQ mode, supports batch read, and provides a console. Ack for the serial side Acked-by: Alan Cox a...@linux.intel.com -- Download Intel#174; Parallel Studio Eval Try the new software tools for yourself. Speed compiling, find bugs proactively, and fine-tune applications for parallel performance. See why Intel Parallel Studio got high marks during beta. http://p.sf.net/sfu/intel-sw-dev ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [spi-devel-general] [RFC][PATCH v2] serial: spi: add spi-uart driver for Maxim 3110
+ for (i = 0; i len; i++) {
+ obuf[i] = (u8)xmit-buf[xmit-tail] | WD_TAG;
+ xmit-tail = (xmit-tail + 1)
+ (UART_XMIT_SIZE - 1);
Could this driver use include/linux/kfifo.h, rather than open-coding it?
The circ buffer stuff comes from the serial layer. The whole serial layer
wants switching to kfifo (as and when we know why the kfifo changes seem
to have broken USB serial) but the driver can't do that itself and use
the serial core code until then.
(Actually most of the serial_core code wants a rewrite but having had a
couple of goes at doing it I've not figured out any way to do it without
simply breaking all sorts of embedded platform serial drivers that need
specific hardware to fix).
+ }
+ max3110_write_then_read(max, (u8 *)obuf,
+ (u8 *)ibuf, len * 2, 0);
Error codes are ignored.
The drivers/serial midlayer has no provision for reporting them.
Alan
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Re: [spi-devel-general] [Industrial I/O] [0/13] RFC: IIO v3 patchset
have both functions. The sort of devices we are talking typically communicate over I2C or SPI buses though drivers for rs232 devices etc are definitely on the cards. Basically we are interested in devices where direct memory mapped access is not possible. We have I2C and SPI drivers so I assume you will use the lower layers of the stacks to do this ? For discussion of why these don't fit within existing subsystems see http://lkml.org/lkml/2008/5/20/135 and the rest of the associated thread. I don't see much there which says why you can't unify all this in a user space library. For RS232/423/.. devices you can go this path if you want (but I would keep it all in userspace anyway) as you can use a line discipline to sit on top of the port and provide another interface (eg the way PPP does) - This SF.Net email is sponsored by the Moblin Your Move Developer's challenge Build the coolest Linux based applications with Moblin SDK win great prizes Grand prize is a trip for two to an Open Source event anywhere in the world http://moblin-contest.org/redirect.php?banner_id=100url=/ ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [spi-devel-general] [Patch 0/4] IndustrialIO subsystem (ADCs, accelerometers etc)
hwmon is designed for slow I/O. It won't handle an ADC that does a few megasamples/sec. At that rate I would assume you want a memory mapped ring buffer or similar not a sysfs style interface ? - This SF.Net email is sponsored by the Moblin Your Move Developer's challenge Build the coolest Linux based applications with Moblin SDK win great prizes Grand prize is a trip for two to an Open Source event anywhere in the world http://moblin-contest.org/redirect.php?banner_id=100url=/ ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[spi-devel-general] [PATCH] spi: Push the BKL down into the drivers
Another step to removing -ioctl and to removing the BKL
Signed-off-by: Alan Cox [EMAIL PROTECTED]
diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
index b3518ca..67e907c 100644
--- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c
@@ -29,6 +29,7 @@
#include linux/errno.h
#include linux/mutex.h
#include linux/slab.h
+#include linux/smp_lock.h
#include linux/spi/spi.h
#include linux/spi/spidev.h
@@ -240,9 +241,8 @@ done:
return status;
}
-static int
-spidev_ioctl(struct inode *inode, struct file *filp,
- unsigned int cmd, unsigned long arg)
+static long
+spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
int err = 0;
int retval = 0;
@@ -269,6 +269,7 @@ spidev_ioctl(struct inode *inode, struct file *filp,
if (err)
return -EFAULT;
+ lock_kernel();
spidev = filp-private_data;
spi = spidev-spi;
@@ -357,7 +358,8 @@ spidev_ioctl(struct inode *inode, struct file *filp,
/* segmented and/or full-duplex I/O request */
if (_IOC_NR(cmd) != _IOC_NR(SPI_IOC_MESSAGE(0))
|| _IOC_DIR(cmd) != _IOC_WRITE)
- return -ENOTTY;
+ retval = -ENOTTY;
+ break;
tmp = _IOC_SIZE(cmd);
if ((tmp % sizeof(struct spi_ioc_transfer)) != 0) {
@@ -385,6 +387,7 @@ spidev_ioctl(struct inode *inode, struct file *filp,
kfree(ioc);
break;
}
+ unlock_kernel();
return retval;
}
@@ -447,7 +450,7 @@ static struct file_operations spidev_fops = {
*/
.write =spidev_write,
.read = spidev_read,
- .ioctl =spidev_ioctl,
+ .unlocked_ioctl = spidev_ioctl,
.open = spidev_open,
.release = spidev_release,
};
-
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