Octeon II usb
l);
+
+ /* port phy settings */
+ for (port = 0; port < 2; port++) {
+ preg = UCTL_UPHY_PORTX_STATUS + (port * 8);
+ port_ctl = bus_space_read_8(sc->sc_iot, sc->sc_ioh, preg);
+ txvref = 0xf;
+ port_ctl |= (UCTL_UPHY_PORTX_STATUS_TXPREEMPHTUNE |
+ UCTL_UPHY_PORTX_STATUS_TXRISETUNE |
+ (txvref << UCTL_UPHY_PORTX_STATUS_TXVREF_SHIFT));
+ bus_space_write_8(sc->sc_iot, sc->sc_ioh, preg, port_ctl);
+ }
+
+ printf("\n");
+
+ uaa.aa_octuctl_bust = aa->aa_bust;
+ uaa.aa_bust = &octuctl_tag;
+ uaa.aa_dmat = aa->aa_dmat;
+ uaa.aa_ioh = sc->sc_ioh;
+
+ uaa.aa_name = "ehci";
+ config_found(self, &uaa, octuctlprint);
+
+ uaa.aa_name = "ohci";
+ config_found(self, &uaa, octuctlprint);
+}
Index: dev/octuctlreg.h
===
RCS file: dev/octuctlreg.h
diff -N dev/octuctlreg.h
--- /dev/null 1 Jan 1970 00:00:00 -
+++ dev/octuctlreg.h17 Mar 2016 01:43:52 -
@@ -0,0 +1,88 @@
+/* $OpenBSD$ */
+
+/*
+ * Copyright (c) 2015 Jonathan Matthew
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+
+#ifndef _OCTUCTLREG_H_
+#define _OCTUCTLREG_H_
+
+#include
+
+/*
+ * UCTL - octeon II usb controller interface
+ */
+#define UCTL_BASE 0x000118006f00ull
+#define UCTL_SIZE 0x100
+
+#define UCTL_EHCI_BASE 0x00016f00ull
+#define UCTL_EHCI_SIZE 0x100
+#define UCTL_OHCI_BASE 0x00016f000400ull
+#define UCTL_OHCI_SIZE 0x100
+
+#define UCTL_CLK_RST_CTL 0x00
+#define UCTL_CLK_RST_CTL_HRST (1 << 0)
+#define UCTL_CLK_RST_CTL_P_PRST(1 << 1)
+#define UCTL_CLK_RST_CTL_P_POR (1 << 2)
+#define UCTL_CLK_RST_CTL_P_COM_ON (1 << 3)
+#define UCTL_CLK_RST_CTL_P_REFCLK_DIV_SHIFT5
+#define UCTL_CLK_RST_CTL_P_REFCLK_SEL_SHIFT7
+#define UCTL_CLK_RST_CTL_H_DIV_SHIFT 9
+#define UCTL_CLK_RST_CTL_O_CLKDIV_EN (1 << 13)
+#define UCTL_CLK_RST_CTL_H_CLKDIV_EN (1 << 14)
+#define UCTL_CLK_RST_CTL_H_CLKDIV_RST (1 << 15)
+#define UCTL_CLK_RST_CTL_H_CLKDIV_BYP (1 << 16)
+#define UCTL_CLK_RST_CTL_O_CLKDIV_RST (1 << 17)
+#define UCTL_CLK_RST_CTL_APP_START_CLK (1 << 18)
+#define UCTL_CLK_RST_CTL_OHCI_SUSP_LGCY(1 << 19)
+#define UCTL_CLK_RST_CTL_OHCI_SM (1 << 20)
+#define UCTL_CLK_RST_CTL_OHCI_CLKCKTRST(1 << 21)
+#define UCTL_CLK_RST_CTL_EHCI_SM (1 << 22)
+
+#define UCTL_UPHY_STATUS 0x08
+
+#define UCTL_UPHY_PORTX_STATUS 0x10
+#define UCTL_UPHY_PORTX_STATUS_TXVREF_SHIFT28
+#define UCTL_UPHY_PORTX_STATUS_TXRISETUNE (1 << 27)
+#define UCTL_UPHY_PORTX_STATUS_TXPREEMPHTUNE (1 << 26)
+
+#define UCTL_IF_ENA0x30
+#define UCTL_IF_ENA_EN (1 << 0)
+
+#define UCTL_EHCI_CTL 0x80
+#define UCTL_EHCI_CTL_L2C_ADDR_MSB_MASK0xff
+#define UCTL_EHCI_CTL_L2C_ADDR_MSB_SHIFT 0
+#define UCTL_EHCI_CTL_EHCI_64B_ADDR_EN (1 << 8)
+#define UCTL_EHCI_CTL_L2C_DESC_EMOD_SHIFT 10
+#define UCTL_EHCI_CTL_L2C_BUFF_EMOD_SHIFT 12
+
+#define UCTL_OHCI_CTL 0x88
+#define UCTL_OHCI_CTL_L2C_ADDR_MSB_MASK0xff
+#define UCTL_OHCI
Re: Octeon II usb
UCTL_CLK_RST_CTL, ctl);
> +
> + /* set clock divider */
> + lastdiv = 1;
> + for (i = 0; i < nitems(validdiv); i++) {
> + if (div < validdiv[i]) {
> + div = lastdiv;
> + break;
> + }
> + lastdiv = validdiv[i];
> + }
> +
> + ctl &= ~(0xf << UCTL_CLK_RST_CTL_H_DIV_SHIFT);
> + ctl |= (div << UCTL_CLK_RST_CTL_H_DIV_SHIFT);
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL, ctl);
> +
> + /* turn hclk on */
> + ctl = bus_space_read_8(sc->sc_iot, sc->sc_ioh,
> + UCTL_CLK_RST_CTL);
> + ctl |= UCTL_CLK_RST_CTL_H_CLKDIV_EN;
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL, ctl);
> + ctl |= UCTL_CLK_RST_CTL_H_CLKDIV_RST;
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL, ctl);
> +
> + delay(ioclockdelay);
> +
> + /* power-on-reset finished */
> + ctl &= ~UCTL_CLK_RST_CTL_P_POR;
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL, ctl);
> +
> + delay(1000);
> +
> + /* set up ohci clocks */
> + ctl |= UCTL_CLK_RST_CTL_O_CLKDIV_RST;
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL, ctl);
> + ctl |= UCTL_CLK_RST_CTL_O_CLKDIV_EN;
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL, ctl);
> +
> + delay(ioclockdelay);
> +
> + /* phy reset */
> + ctl |= UCTL_CLK_RST_CTL_P_PRST;
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL, ctl);
> +
> + delay(1);
> +
> + /* clear host reset */
> + ctl |= UCTL_CLK_RST_CTL_HRST;
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL, ctl);
> +}
> +
> +void
> +octuctl_attach(struct device *parent, struct device *self, void *aux)
> +{
> + struct octuctl_softc *sc = (struct octuctl_softc *)self;
> + struct iobus_attach_args *aa = aux;
> + struct octuctl_attach_args uaa;
> + uint64_t port_ctl;
> + uint64_t ctl;
> + uint64_t preg;
> + uint64_t txvref;
> + int rc;
> + int port;
> +
> + sc->sc_iot = aa->aa_bust;
> + rc = bus_space_map(sc->sc_iot, UCTL_BASE, UCTL_SIZE,
> + 0, &sc->sc_ioh);
> + KASSERT(rc == 0);
> +
> + /* do clock setup if not already done */
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_IF_ENA,
> + UCTL_IF_ENA_EN);
> + ctl = bus_space_read_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL);
> + if ((ctl & UCTL_CLK_RST_CTL_HRST) == 0)
> + octuctl_clock_setup(sc, ctl);
> +
> + /* port phy settings */
> + for (port = 0; port < 2; port++) {
> + preg = UCTL_UPHY_PORTX_STATUS + (port * 8);
> + port_ctl = bus_space_read_8(sc->sc_iot, sc->sc_ioh, preg);
> + txvref = 0xf;
> + port_ctl |= (UCTL_UPHY_PORTX_STATUS_TXPREEMPHTUNE |
> + UCTL_UPHY_PORTX_STATUS_TXRISETUNE |
> + (txvref << UCTL_UPHY_PORTX_STATUS_TXVREF_SHIFT));
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, preg, port_ctl);
> + }
> +
> + printf("\n");
> +
> + uaa.aa_octuctl_bust = aa->aa_bust;
> + uaa.aa_bust = &octuctl_tag;
> + uaa.aa_dmat = aa->aa_dmat;
> + uaa.aa_ioh = sc->sc_ioh;
> +
> + uaa.aa_name = "ehci";
> + config_found(self, &uaa, octuctlprint);
> +
> + uaa.aa_name = "ohci";
> + config_found(self, &uaa, octuctlprint);
> +}
> Index: dev/octuctlreg.h
> ===
> RCS file: dev/octuctlreg.h
> diff -N dev/octuctlreg.h
> --- /dev/null 1 Jan 1970 00:00:00 -
> +++ dev/octuctlreg.h 17 Mar 2016 01:43:52 -
> @@ -0,0 +1,88 @@
> +/* $OpenBSD$ */
> +
> +/*
> + * Copyright (c) 2015 Jonathan Matthew
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *notice, this list of conditions and the following disclaimer in the
> + *documentation and/or other materials provided with the distribution.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
> + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
Re: Octeon II usb
On Thu, Mar 17, 2016 at 11:43:03AM +0900, Masao Uebayashi wrote: > A bit surprised that code does more than I imagined by reading your > description :) but it looks very good to me! > > A few comments: > > - `struct octuctl_softc' is not using `sc_ehci' and `sc_ohci'? These were leftovers from when I thought I could fit everything in one file. I removed these, then got a friendly reminder from autoconf that I'd forgotten the 'struct device' at the start of the softc. > - Some magic numbers in `octuctl_clock_setup' could be #define'ed Looking at this again, the 64 io clock cycle delay we're supposed to add after enabling USB clocks is always going to be less than a microsecond, so I'll just use delay(1). I'll add a #define for the USB hclk target frequency.
Re: Octeon II usb
t; + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL, ctl);
> +
> + /* set up for 12mhz crystal */
> + ctl &= ~((3 << UCTL_CLK_RST_CTL_P_REFCLK_DIV_SHIFT) |
> + (3 << UCTL_CLK_RST_CTL_P_REFCLK_SEL_SHIFT));
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL, ctl);
> +
> + /* set clock divider */
> + lastdiv = 1;
> + for (i = 0; i < nitems(validdiv); i++) {
> + if (div < validdiv[i]) {
> + div = lastdiv;
> + break;
> + }
> + lastdiv = validdiv[i];
> + }
> +
> + ctl &= ~(0xf << UCTL_CLK_RST_CTL_H_DIV_SHIFT);
> + ctl |= (div << UCTL_CLK_RST_CTL_H_DIV_SHIFT);
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL, ctl);
> +
> + /* turn hclk on */
> + ctl = bus_space_read_8(sc->sc_iot, sc->sc_ioh,
> + UCTL_CLK_RST_CTL);
> + ctl |= UCTL_CLK_RST_CTL_H_CLKDIV_EN;
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL, ctl);
> + ctl |= UCTL_CLK_RST_CTL_H_CLKDIV_RST;
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL, ctl);
> +
> + delay(ioclockdelay);
> +
> + /* power-on-reset finished */
> + ctl &= ~UCTL_CLK_RST_CTL_P_POR;
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL, ctl);
> +
> + delay(1000);
> +
> + /* set up ohci clocks */
> + ctl |= UCTL_CLK_RST_CTL_O_CLKDIV_RST;
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL, ctl);
> + ctl |= UCTL_CLK_RST_CTL_O_CLKDIV_EN;
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL, ctl);
> +
> + delay(ioclockdelay);
> +
> + /* phy reset */
> + ctl |= UCTL_CLK_RST_CTL_P_PRST;
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL, ctl);
> +
> + delay(1);
> +
> + /* clear host reset */
> + ctl |= UCTL_CLK_RST_CTL_HRST;
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL, ctl);
> +}
> +
> +void
> +octuctl_attach(struct device *parent, struct device *self, void *aux)
> +{
> + struct octuctl_softc *sc = (struct octuctl_softc *)self;
> + struct iobus_attach_args *aa = aux;
> + struct octuctl_attach_args uaa;
> + uint64_t port_ctl;
> + uint64_t ctl;
> + uint64_t preg;
> + uint64_t txvref;
> + int rc;
> + int port;
> +
> + sc->sc_iot = aa->aa_bust;
> + rc = bus_space_map(sc->sc_iot, UCTL_BASE, UCTL_SIZE,
> + 0, &sc->sc_ioh);
> + KASSERT(rc == 0);
> +
> + /* do clock setup if not already done */
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, UCTL_IF_ENA,
> + UCTL_IF_ENA_EN);
> + ctl = bus_space_read_8(sc->sc_iot, sc->sc_ioh, UCTL_CLK_RST_CTL);
> + if ((ctl & UCTL_CLK_RST_CTL_HRST) == 0)
> + octuctl_clock_setup(sc, ctl);
> +
> + /* port phy settings */
> + for (port = 0; port < 2; port++) {
> + preg = UCTL_UPHY_PORTX_STATUS + (port * 8);
> + port_ctl = bus_space_read_8(sc->sc_iot, sc->sc_ioh, preg);
> + txvref = 0xf;
> + port_ctl |= (UCTL_UPHY_PORTX_STATUS_TXPREEMPHTUNE |
> + UCTL_UPHY_PORTX_STATUS_TXRISETUNE |
> + (txvref << UCTL_UPHY_PORTX_STATUS_TXVREF_SHIFT));
> + bus_space_write_8(sc->sc_iot, sc->sc_ioh, preg, port_ctl);
> + }
> +
> + printf("\n");
> +
> + uaa.aa_octuctl_bust = aa->aa_bust;
> + uaa.aa_bust = &octuctl_tag;
> + uaa.aa_dmat = aa->aa_dmat;
> + uaa.aa_ioh = sc->sc_ioh;
> +
> + uaa.aa_name = "ehci";
> + config_found(self, &uaa, octuctlprint);
> +
> + uaa.aa_name = "ohci";
> + config_found(self, &uaa, octuctlprint);
> +}
> Index: dev/octuctlreg.h
> ===
> RCS file: dev/octuctlreg.h
> diff -N dev/octuctlreg.h
> --- /dev/null 1 Jan 1970 00:00:00 -
> +++ dev/octuctlreg.h 17 Mar 2016 01:43:52 -
> @@ -0,0 +1,88 @@
> +/* $OpenBSD$ */
> +
> +/*
> + * Copyright (c) 2015 Jonathan Matthew
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *
