Re: mips64, loongson, octeon: switch to clockintr(9)
On Wed, Nov 16, 2022 at 07:00:23AM -0600, Scott Cheloha wrote:
> On Mon, Nov 14, 2022 at 05:19:17PM +, Visa Hankala wrote:
> > I think this clockintr_init() should be in cp0_startclock(). This would
> > let other clock drivers do their own adjusting of the hz variables
> > before clockintr initialization. With this fixed,
>
> Is the attached the change you envisioned?
Yes, but please remove the #ifdef MULTIPROCESSOR line and its #endif
from cp0_startclock(). The #ifdef'ing is redundant because
CPU_IS_PRIMARY() is short-circuited to value 1 in non-MULTIPROCESSOR
builds and the else branch does not use any MULTIPROCESSOR-only items.
if (CPU_IS_PRIMARY(ci)) {
stathz = hz;
profhz = stathz * 10;
clockintr_init(CL_RNDSTAT);
} else {
s = splhigh();
nanouptime(>ci_schedstate.spc_runtime);
splx(s);
/* try to avoid getting clock interrupts early */
cp0_set_compare(cp0_get_count() - 1);
cp0_calibrate(ci);
}
With the above tweak,
OK visa@
Re: mips64, loongson, octeon: switch to clockintr(9)
On Mon, Nov 14, 2022 at 05:19:17PM +, Visa Hankala wrote:
> On Sun, Nov 06, 2022 at 07:48:09PM +, Scott Cheloha wrote:
> > This patch switches loongson and octeon to clockintr(9).
> >
> > It has survived several release builds and upgrades from the resulting
> > bsd.rd images on my ER-4. The ER-4 doesn't have enough RAM to crunch a
> > parallel release build. It chokes on some of the larger LLVM modules.
> >
> > visa@ reports it survived a partial build on a loongson machine (he
> > skipped LLVM). I believe he is also testing this on a package
> > building machine, too.
> >
> > Testing on beefier octeon machines would help demonstrate this is
> > stable. My ER-4 only has USB2.0, which slows things down.
>
> So far, this patch has worked fine on the mips64 package build machines.
>
> > Notes:
> >
> > - octeon and loongson machines now have a randomized statclock().
> >
> > - This patch merely disables the loongson glxclk. If the device has
> > no other use we can fully remove the driver in a separate patch.
>
> Lets keep the driver for now. The disabling is fine for the time being.
>
> > @@ -324,6 +324,10 @@ cpu_initclocks(void)
> > tc_init(_timecounter);
> > }
> >
> > + stathz = hz;
> > + profhz = stathz * 10;
> > + clockintr_init(CL_RNDSTAT);
>
> I think this clockintr_init() should be in cp0_startclock(). This would
> let other clock drivers do their own adjusting of the hz variables
> before clockintr initialization. With this fixed,
Is the attached the change you envisioned?
If so, I'm eyeing end-of-week to commit this. I haven't seen any
fallout from the amd64 and arm64 switch-to-clockintr commits, so it's
probably time to do another batch of platforms.
Index: sys/arch/mips64/include/cpu.h
===
RCS file: /cvs/src/sys/arch/mips64/include/cpu.h,v
retrieving revision 1.139
diff -u -p -r1.139 cpu.h
--- sys/arch/mips64/include/cpu.h 22 Aug 2022 00:35:06 - 1.139
+++ sys/arch/mips64/include/cpu.h 16 Nov 2022 12:57:56 -
@@ -106,6 +106,7 @@
#if defined(_KERNEL) && !defined(_LOCORE)
+#include
#include
#include
#include
@@ -179,8 +180,8 @@ struct cpu_info {
uint32_tci_softpending; /* pending soft interrupts */
int ci_clock_started;
volatile intci_clock_deferred; /* clock interrupt postponed */
- u_int32_t ci_cpu_counter_last;/* last compare value loaded */
- u_int32_t ci_cpu_counter_interval; /* # of counter ticks/tick */
+ struct clockintr_queue
+ ci_queue;
struct pmap *ci_curpmap;
uintci_intrdepth; /* interrupt depth */
Index: sys/arch/mips64/include/_types.h
===
RCS file: /cvs/src/sys/arch/mips64/include/_types.h,v
retrieving revision 1.23
diff -u -p -r1.23 _types.h
--- sys/arch/mips64/include/_types.h5 Mar 2018 01:15:25 - 1.23
+++ sys/arch/mips64/include/_types.h16 Nov 2022 12:57:56 -
@@ -35,6 +35,8 @@
#ifndef _MIPS64__TYPES_H_
#define _MIPS64__TYPES_H_
+#define__HAVE_CLOCKINTR
+
/*
* _ALIGN(p) rounds p (pointer or byte index) up to a correctly-aligned
* value for all data types (int, long, ...). The result is an
Index: sys/arch/mips64/mips64/clock.c
===
RCS file: /cvs/src/sys/arch/mips64/mips64/clock.c,v
retrieving revision 1.47
diff -u -p -r1.47 clock.c
--- sys/arch/mips64/mips64/clock.c 31 Oct 2022 13:59:10 - 1.47
+++ sys/arch/mips64/mips64/clock.c 16 Nov 2022 12:57:56 -
@@ -38,8 +38,10 @@
#include
#include
#include
+#include
#include
#include
+#include
#include
#include
@@ -47,6 +49,8 @@
static struct evcount cp0_clock_count;
static int cp0_clock_irq = 5;
+uint64_t cp0_nsec_cycle_ratio;
+uint64_t cp0_nsec_max;
intclockmatch(struct device *, void *, void *);
void clockattach(struct device *, struct device *, void *);
@@ -59,9 +63,18 @@ const struct cfattach clock_ca = {
sizeof(struct device), clockmatch, clockattach
};
-void cp0_startclock(struct cpu_info *);
-void cp0_trigger_int5(void);
+void cp0_rearm_int5(void *, uint64_t);
+void cp0_trigger_int5_wrapper(void *);
+
+const struct intrclock cp0_intrclock = {
+ .ic_rearm = cp0_rearm_int5,
+ .ic_trigger = cp0_trigger_int5_wrapper
+};
+
uint32_t cp0_int5(uint32_t, struct trapframe *);
+void cp0_startclock(struct cpu_info *);
+void cp0_trigger_int5(void);
+void cp0_trigger_int5_masked(void);
int
clockmatch(struct device *parent, void *vcf, void *aux)
@@ -74,8 +87,13 @@ clockmatch(struct device *parent, void *
void
clockattach(struct device *parent, struct device *self, void *aux)
{
+ uint64_t cp0_freq = curcpu()->ci_hw.clock / CP0_CYCLE_DIVIDER;
+
printf(": int 5\n");
Re: mips64, loongson, octeon: switch to clockintr(9)
On Sun, Nov 06, 2022 at 07:48:09PM +, Scott Cheloha wrote: > This patch switches loongson and octeon to clockintr(9). > > It has survived several release builds and upgrades from the resulting > bsd.rd images on my ER-4. The ER-4 doesn't have enough RAM to crunch a > parallel release build. It chokes on some of the larger LLVM modules. > > visa@ reports it survived a partial build on a loongson machine (he > skipped LLVM). I believe he is also testing this on a package > building machine, too. > > Testing on beefier octeon machines would help demonstrate this is > stable. My ER-4 only has USB2.0, which slows things down. So far, this patch has worked fine on the mips64 package build machines. > Notes: > > - octeon and loongson machines now have a randomized statclock(). > > - This patch merely disables the loongson glxclk. If the device has > no other use we can fully remove the driver in a separate patch. Lets keep the driver for now. The disabling is fine for the time being. > @@ -324,6 +324,10 @@ cpu_initclocks(void) > tc_init(_timecounter); > } > > + stathz = hz; > + profhz = stathz * 10; > + clockintr_init(CL_RNDSTAT); I think this clockintr_init() should be in cp0_startclock(). This would let other clock drivers do their own adjusting of the hz variables before clockintr initialization. With this fixed, OK visa@
mips64, loongson, octeon: switch to clockintr(9)
This patch switches loongson and octeon to clockintr(9).
It has survived several release builds and upgrades from the resulting
bsd.rd images on my ER-4. The ER-4 doesn't have enough RAM to crunch a
parallel release build. It chokes on some of the larger LLVM modules.
visa@ reports it survived a partial build on a loongson machine (he
skipped LLVM). I believe he is also testing this on a package
building machine, too.
Testing on beefier octeon machines would help demonstrate this is
stable. My ER-4 only has USB2.0, which slows things down.
Notes:
- octeon and loongson machines now have a randomized statclock().
- This patch merely disables the loongson glxclk. If the device has
no other use we can fully remove the driver in a separate patch.
Index: sys/arch/mips64/include/cpu.h
===
RCS file: /cvs/src/sys/arch/mips64/include/cpu.h,v
retrieving revision 1.139
diff -u -p -r1.139 cpu.h
--- sys/arch/mips64/include/cpu.h 22 Aug 2022 00:35:06 - 1.139
+++ sys/arch/mips64/include/cpu.h 6 Nov 2022 19:09:21 -
@@ -106,6 +106,7 @@
#if defined(_KERNEL) && !defined(_LOCORE)
+#include
#include
#include
#include
@@ -179,8 +180,8 @@ struct cpu_info {
uint32_tci_softpending; /* pending soft interrupts */
int ci_clock_started;
volatile intci_clock_deferred; /* clock interrupt postponed */
- u_int32_t ci_cpu_counter_last;/* last compare value loaded */
- u_int32_t ci_cpu_counter_interval; /* # of counter ticks/tick */
+ struct clockintr_queue
+ ci_queue;
struct pmap *ci_curpmap;
uintci_intrdepth; /* interrupt depth */
Index: sys/arch/mips64/include/_types.h
===
RCS file: /cvs/src/sys/arch/mips64/include/_types.h,v
retrieving revision 1.23
diff -u -p -r1.23 _types.h
--- sys/arch/mips64/include/_types.h5 Mar 2018 01:15:25 - 1.23
+++ sys/arch/mips64/include/_types.h6 Nov 2022 19:09:21 -
@@ -35,6 +35,8 @@
#ifndef _MIPS64__TYPES_H_
#define _MIPS64__TYPES_H_
+#define__HAVE_CLOCKINTR
+
/*
* _ALIGN(p) rounds p (pointer or byte index) up to a correctly-aligned
* value for all data types (int, long, ...). The result is an
Index: sys/arch/mips64/mips64/clock.c
===
RCS file: /cvs/src/sys/arch/mips64/mips64/clock.c,v
retrieving revision 1.47
diff -u -p -r1.47 clock.c
--- sys/arch/mips64/mips64/clock.c 31 Oct 2022 13:59:10 - 1.47
+++ sys/arch/mips64/mips64/clock.c 6 Nov 2022 19:09:21 -
@@ -38,8 +38,10 @@
#include
#include
#include
+#include
#include
#include
+#include
#include
#include
@@ -47,6 +49,8 @@
static struct evcount cp0_clock_count;
static int cp0_clock_irq = 5;
+uint64_t cp0_nsec_cycle_ratio;
+uint64_t cp0_nsec_max;
intclockmatch(struct device *, void *, void *);
void clockattach(struct device *, struct device *, void *);
@@ -59,9 +63,18 @@ const struct cfattach clock_ca = {
sizeof(struct device), clockmatch, clockattach
};
-void cp0_startclock(struct cpu_info *);
-void cp0_trigger_int5(void);
+void cp0_rearm_int5(void *, uint64_t);
+void cp0_trigger_int5_wrapper(void *);
+
+const struct intrclock cp0_intrclock = {
+ .ic_rearm = cp0_rearm_int5,
+ .ic_trigger = cp0_trigger_int5_wrapper
+};
+
uint32_t cp0_int5(uint32_t, struct trapframe *);
+void cp0_startclock(struct cpu_info *);
+void cp0_trigger_int5(void);
+void cp0_trigger_int5_masked(void);
int
clockmatch(struct device *parent, void *vcf, void *aux)
@@ -74,8 +87,13 @@ clockmatch(struct device *parent, void *
void
clockattach(struct device *parent, struct device *self, void *aux)
{
+ uint64_t cp0_freq = curcpu()->ci_hw.clock / CP0_CYCLE_DIVIDER;
+
printf(": int 5\n");
+ cp0_nsec_cycle_ratio = cp0_freq * (1ULL << 32) / 10;
+ cp0_nsec_max = UINT64_MAX / cp0_nsec_cycle_ratio;
+
/*
* We need to register the interrupt now, for idle_mask to
* be computed correctly.
@@ -100,20 +118,19 @@ clockattach(struct device *parent, struc
uint32_t
cp0_int5(uint32_t mask, struct trapframe *tf)
{
- u_int32_t clkdiff, pendingticks = 0;
struct cpu_info *ci = curcpu();
int s;
+ atomic_inc_long((unsigned long *)_clock_count.ec_count);
+
+ cp0_set_compare(cp0_get_count() - 1); /* clear INT5 */
+
/*
-* If we got an interrupt before we got ready to process it,
-* retrigger it as far as possible. cpu_initclocks() will
-* take care of retriggering it correctly.
+* Just ignore the interrupt if we're not ready to process it.
+* cpu_initclocks() will retrigger it later.
*/
- if (ci->ci_clock_started == 0) {
-
