[time-nuts] Phase noise measurement experiment by Andrew Holme

[Li Ang]

Hi 
I just found Andrew recently post a phase noise measruement page on 
www.aholme.co.uk/PhaseNoise/Main.htm .


He uses 4-channel 14bit ADC to do the sampling work. -170dBc noise floor seems 
not bad for me. 


Since the cross correlation could reduce noise a lot, I am wondering what the 
differences between 14 bits and 16 bits ADC are.


Regards
Li Ang / BI7LNQ
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Re: [time-nuts] PRS10 PRBB Shematics

[Li Ang]

Hi Guys
   I have just bought 2 kinds of PRS10 connectors on taobao.com. (PCB type and 
cable type, refer to the attached photo). It is about 8$ each(the D-SUB + 
center RF part). If you are looking for it, I can send you the link off the 
list. 




Yours


Li Ang / BI7LNQ


-- Original --
From:  "Jacques Tiete";<jacq...@tiete.org>;
Date:  Mon, Oct 9, 2017 11:37 AM
To:  "TimeNuts"<time-nuts@febo.com>;

Subject:  Re: [time-nuts] PRS10 PRBB Shematics



Thanks for the prompt reactions, in the mean time I understood Cannon 
connectors can be a real pain in the xxx :-) to figure out the right one. 

Jacques




Op 6 okt. 2017, om 23:19 heeft Jacques Tiete <jacq...@tiete.org> het volgende 
geschreven:

Fellow timenuts,

I’d like to find some more info about the SRS “PRBB” breakout board for the 
PRS10, schematic diagram, parts list (eg. the cannon pcb connector used) and 
all relevant info.
An internet/timenuts research did not turn up anything relevant.


thanks & 73’s,

Jacques


Jacques Tiete
jacq...@tiete.org
GSM: 32(0)499 99 83 78




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Re: [time-nuts] SR620/PM66xx/CNT-90 input stages

[Li Ang]

Hi
 I think the purpose is to get high input impedance for high frequency signal. 
The input impedance of comparator is high at low frequency range only.


Li Ang / BI7LNQ
---Original---
From: "Attila Kinali"<att...@kinali.ch>
Date: 2017/6/20 15:20:44
To: "Discussion of precise time and frequency measurement"<time-nuts@febo.com>;
Subject: [time-nuts] SR620/PM66xx/CNT-90 input stages


Hi,

I had a look at the PM668x[1] and CNT-90[2] schematics yesterday and
noticed one thing: The input stages are strikingly similar to the
SR620[3] (down to the parts used) and all of them have a gain 1 amplifier
infront of the comparator. The PM668x service manual explicitly calls it
"impedance converter", even. Now, if the downstream circuit would be low
impedance, I could understand that, but the sink is a comparator with a
high impedance input (only a few µA input current). I am sure the engineers
had a good reason to add those amplifiers, but I cannot guess why. Would
someone be so kind and enlighten me?

Attila Kinali

[1] 
http://bee.mif.pg.gda.pl/ciasteczkowypotwor/Fluke/Fluke_PM6681_Service_Manual.pdf
[2] http://assets.fluke.com/manuals/6690smeng.pdf
[3] 
http://www.ko4bb.com/getsimple/index.php?id=download=02_GPS_Timing/Stanford_Research_Systems/SR620_Universal_Time_Interval_Counter_Schematics.pdf

-- 
It is upon moral qualities that a society is ultimately founded. All 
the prosperity and technological sophistication in the world is of no 
use without that foundation.
 -- Miss Matheson, The Diamond Age, Neil Stephenson
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Re: [time-nuts] First batch data of China pulstar observation satellite

[Li Ang]

Hi
The readme.txt inside http://www.beidou.gov.cn/xpnavdata.rar 
1. filename rules
event: Psrname_mmdd_hhmmss.txt (psrname: pulsar name, yyymmmddd_hhmmss: utc 
date of the data)
orbit: orbit_mmdd_hhmmss.txt (utc date of orbit data)


2. orbit file format
time(seconds start from 2008-01-01  00:00:00 UTC)   J2000-x(m) J2000-y(m) 
J2000-z(m)  J2000-vx(m/s) J2000-vy(m/s) J2000-vz(m/s)


3. event file format
TOA (seconds start from 2008-01-01 00:00:00 UTC)  energy(eV)


4. If you are gonna publish the research result please declare the data is from 
www.beidou.gov.cn taken by pulsar observation satellite XPNAV-1.  
5. detector intro: wolter-i focused x-ray detector. energy range: 0.5-10keV. 
view : 2ω=15'.  geometric area: 30cm2@1.5keV. Time resolution:<=1.5us. Energy 
resolution: <=180eV@5.9keV.





-- Original --
From:  "Li Ang";<379...@qq.com>;
Date:  Wed, May 10, 2017 09:45 AM
To:  "time-nuts"<time-nuts@febo.com>; 

Subject:  [time-nuts] First batch data of China pulstar observation satellite



Hi, 
I have just noticed that the data was found at 
http://www.beidou.gov.cn/xpnavdata.rar 
The satellite was built by BD7ILZ's company and launched on 2016.11.10. The 
data is recieved from the Crab nebula.
If you are interested on the data I am happy y to translate the readme.txt 
and related information.


Regards


Li Ang / BI7LNQ
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[time-nuts] First batch data of China pulstar observation satellite

[Li Ang]

Hi, 
I have just noticed that the data was found at 
http://www.beidou.gov.cn/xpnavdata.rar 
The satellite was built by BD7ILZ's company and launched on 2016.11.10. The 
data is recieved from the Crab nebula.
If you are interested on the data I am happy y to translate the readme.txt 
and related information.


Regards


Li Ang / BI7LNQ
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Re: [time-nuts] How to create a super Rb standard

[Li Ang]

Hi
I am wondering if anyone tried to put a Rb unit into a vacuum container. And 
how much the performance is improved? Someone told me that's why the Rb clocks 
are more stable than Cs clocks on the GPS satellites.

LiAng

---Original---
From: "Bob Camp"
Date: 2017/1/17 21:20:23
To: "Discussion of precise time and frequency 
measurement";"Perry Sandeen";
Subject: Re: [time-nuts] How to create a super Rb standard


Hi

Since the physics package in the small Rb’s is different than the stuff in the 
large units, 
you have some basic limits on what you can do to improve them. The main things 
people
have done are to modify them to turn off the temperature compensation and 
replace it
with some sort of precision controlled thermal enclosure. Pressure compensation 
is a good
idea on any of these parts (large or small). How much your particular unit 
benefits is a 
“that depends” sort of thing.

Bob

> On Jan 16, 2017, at 10:24 PM, Perry Sandeen via time-nuts 
>  wrote:
> 
> 
> List
> It looks like their is as infinitely small chance of being able to get 5065.
> So what can be done with the telco Rb's (mine are analog tuned) to wring the 
> best possible performance from them? Sooper Duper power supplies, Peltier 
> (sp) cooling modules?
> Regards,
> Perrier
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Re: [time-nuts] Performance of TDC7200

[Li Ang]

Hi
Thanks for the info. The fpga baesed TDC is something I am interested in. 
However, I am a beginner of fpga programming. Maybe next year I will spend 
sometime study this project. VHDL is quite difficult for a C programmer :(.  


Regards
Li Ang
BI7LNQ
---Original---
From: "Attila Kinali"<att...@kinali.ch>
Date: 2016/12/16 02:00:32
To: "Discussion of precise time and frequency measurement"<time-nuts@febo.com>;
Subject: Re: [time-nuts] Performance of TDC7200


On Fri, 9 Dec 2016 21:29:34 +0800
"Li Ang" <379...@qq.com> wrote:

> I've done some tests with TDC7200 and TDC_GP22 few months 
> ago.(https://www.febo.com/pipermail/time-nuts/2016-May/098170.html)

Thanks for the report. It's interesting to see that the TDC7200 performs
slightly better than the GP22.

BTW: If you are using a large FPGA like the EP4CE22, then you might
want to consider using it directly as a TDC. You can fit four ring oscillator
based TDC easily and have more than enough space for your control logic
(we did a 4 TDC system with an NIOS2 core and some glue and still had
space spare).

The bin with is in the order of 22ps, with excursions up to 100ps.

The code we used was based on the tdc-core by CERN[1] and can be found
on my git server [2]. Special thanks to Florian Huemer who got it
working properly.


Attila Kinali

[1] http://www.ohwr.org/projects/tdc-core/wiki
[2] http://git.kinali.ch/attila/nios2_clocksync/tree/master/fpga/cores/tdc

-- 
It is upon moral qualities that a society is ultimately founded. All 
the prosperity and technological sophistication in the world is of no 
use without that foundation.
 -- Miss Matheson, The Diamond Age, Neil Stephenson
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[time-nuts] Performance of TDC7200

[Li Ang]

I've done some tests with TDC7200 and TDC_GP22 few months 
ago.(https://www.febo.com/pipermail/time-nuts/2016-May/098170.html)


Here is the performance test of my recent board.



http://www.qsl.net/b/bi7lnq/Projects/freqcnt6.0/schematic.pdf
http://www.qsl.net/b/bi7lnq/Projects/freqcnt6.0/freqcntv6.0.jpg


The "analog front end" is 74lvc1g04/nc7sz125. 3 TDC7200s are on the board. Only 
TI mode is tested at the moment.(the truth is I forgot to connect the SPI port 
to FPGA .., I need to reuse the config ports to implement a bidirectional 
SPI to read the counters in FPGA)
DUT and REF are from a homebrew distribution amp( 
http://www.qsl.net/b/bi7lnq/distribution_amp/v1.5/10M_distributor.pdf), the 
source is a FE180 OCXO.


1) the noise of 74LVC and NC7 are different.
2) the performance of my counter in TI mode is almost the same as the Agilent 
53220A
http://www.qsl.net/b/bi7lnq/Projects/freqcnt6.0/data/20161209/nc7sz125_74lvc1g04_53220a.png


I also tried to measure 3 OCXOs at the same time. FE180, OCXO8663, free running 
TBOLT
http://www.qsl.net/b/bi7lnq/Projects/freqcnt6.0/data/20161209/freqcnt_v6_20161209.png
http://www.qsl.net/b/bi7lnq/Projects/freqcnt6.0/data/20161209/freqcnt_v6_20161209_3corneredhat.png


TODO list:
1) web based interface, calculate and show *DEVs with javascript on Chrome 
browser
2) front end experiments




Regards


Li Ang / BI7LNQ
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Re: [time-nuts] New Timestamping / Time Interval Counter: the TICC

[Li Ang]

Great job.

I am doing a similar project too.
I've just sent gerber/pos/bom files to the PCB company.  3 tdc7200s are 
used on my board to support the 3-corner-hat measurement. 

Regards
Li Ang

---Original---
From: "John Ackermann N8UR"<j...@febo.com>
Date: 2016/11/25 22:57:33
To: "Discussion of precise time and frequency 
measurement"<time-nuts@febo.com>;"David"<mcqu...@sonic.net>;
Subject: Re: [time-nuts] New Timestamping / Time Interval Counter: the TICC


Hi Dave --

I should clarify -- this UI is just a character-based menu system using 
a dumb terminal program.  The code is implemented within the Arduino.

It's written in the somewhat nonstandard C/C++ used by the Arduino IDE. 
  This morning I'm going to add a "TODO-UI" file to the git repository 
explaining what the menu system needs to do.

TimeLab is able to read the data stream and plot results in real-time, 
so there's no urgent need for software on the host end.  But I do need 
to allow the user to set a number of configuration parameters without 
having to recompile the code, so that's the urgent goal.

Thanks!
John

On 11/25/2016 03:26 AM, David wrote:
> John,
>
>In what language is the GUI written?  I might be able to help on
> that, or other parts of the software, if someone else hasn't yet
> volunteered.
>
> Dave, WA8YWQ
>
> On 2016-11-24 06:43, John Ackermann N8UR wrote:
>
>> Hi Anders --
>>
>> Thanks, and thanks for the info on the 53230A.  I have not used one of
>> those myself but the data sheet lists 20ps single-shot.
>>
>> Also I should note that the TICC does not compete with counters like
>> the 53230A for high speed measurement, or frequency counting.  It does
>> far fewer measurements per second than the high-end counters -- my
>> design criteria was for use in PPS measuring system.
>>
>> With the current software, the actual measurement processing time is
>> about 1 millisecond; we may be able to optimize a hundred or two
>> microseconds from that as the code currently has more 64 bit
>> operations than are necessary, and there are other things that can
>> surely be tweaked.
>>
>> The killer is the serial output via USB.  It can take up to 10 ms to
>> output 20 characters, and that's what really limits the measurement
>> rate.  I'm pretty sure this can be improved (one idea is to buffer
>> results to reduce USB packetization delays), but there's other
>> functionality that I need to finish first.
>>
>> BTW -- the software is open source and on github at
>> https://github.com/TAPR/TICC , so I welcome anyone who wants to work
>> on it.  Bug fixes are gladly accepted, and if you're looking for work
>> to do, I could use a volunteer to work on a couple of areas, most
>> critically finishing a UI that will allow the user to set operating
>> parameters.
>>
>> John
>> 
>> On 11/24/2016 02:40 AM, Anders Wallin wrote:
>>> Nice work!
>>> On the website in the introduction you mention 22ps single-shot
>>> time-stamping on the 5370A/B.
>>> I think it's well established that the 53230A does about 11-12 ps for
>>> time-intervals, which corresponds to about 9 ps single-channel. see for
>>> example:
>>> http://www.anderswallin.net/wp-content/uploads/2015/04/53230A_PPS_skew.png
>>>
>>> Anders
>>>
>>>
>>> On Wed, Nov 23, 2016 at 11:13 PM, Peter Vince <petervince1...@gmail.com
>>> <mailto:petervince1...@gmail.com>>
>>> wrote:
>>>
>>>> Fantastic John - well done!  Yes, I'll definitely put an order in as soon
>>>> as possible.
>>>>
>>>>   Regards,
>>>>
>>>>   Peter  (G8ZZR, London)
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Re: [time-nuts] 5071A with ATTENTION flashing

[Li Ang]

Hi Tom
It looks very clean inside. I think they should be from some lab. There is 
one with a label CEVA xx on it. 
I told him all the information I collected from the serial port. As a 
reward to travel 200km help him determine the status of these 5071s, he gave me 
2 PRS10 rubidium oscillators. 
I also told him to keep the leaky one running for days and see what's going 
on. If it goes to normal, price will x2 or more. 


regards
Li Ang


---Original---
From: "Tom Van Baak"<t...@leapsecond.com>
Date: 2016/11/13 19:34:59
To: "Discussion of precise time and frequency measurement"<time-nuts@febo.com>;
Subject: Re: [time-nuts] 5071A with ATTENTION flashing


> Since the ion pump current was dropping slowly.(80uA to 76uA in 1 hour), is 
> it possible to be back to normal?

Hi Li,

Yes, is it possible. Never give up on ion current. Give it hours, give it days 
if necessary.

Monitor the LCD or syst:print? periodically and plot the trend. The trend may 
be linear (you may only need to wait for hours). The trend my be logarithmic 
(you may need to wait for days). If the trend looks like it will eventually 
drop below 1 uA that is good news. You just have to wait. If the 5071A gives a 
fatal error and turns off the ion pump for safety, then power cycle to try 
again.

What you are seeing is not normal behavior. But given the chance that you might 
get a tube that works, even for a little while, that is worth something. Do you 
know where these 5071A were installed, or what they were used for?

If it looks like the ion pump current will never drop to 1 uA, even after 
several days, then you may have a vacuum leak or failed ion pump or too much 
outgassing or something. Try swapping tubes to see if the new frame shows a 
similar ion pump reading and trend. If so, then both frames are ok and the tube 
is bad. I don't know of a fix for this. Cesium tubes fail for many reasons, not 
just running out of cesium.

/tvb

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Re: [time-nuts] 5071A with ATTENTION flashing

[Li Ang]

HI
  I just came back from another 5071a seller. 
#1-#3 fatal error: max emult. 
#4 fatal error: overcureent (about 80uA) 
I put the tube from #1 to #4. #4 became a "max emult" one. 

I think the tube #1 is really dead and the circuit of #4 is functional.

Since the ion pump current was dropping slowly.(80uA to 76uA in 1 hour), is it 
possible to be back to normal?

regards
LiAng 
BI7LNQ
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Re: [time-nuts] 5071A with ATTENTION flashing

[Li Ang]

Hi
   I have said goodbye to this one. There are 5 more 5071A with yellow led 
flashing to visit this weekend. 


Regards
LiAng
BI7LNQ
---Original---
From: "Tom Van Baak"<t...@leapsecond.com>
Date: 2016/11/10 06:28:45
To: "Discussion of precise time and frequency measurement"<time-nuts@febo.com>;
Subject: Re: [time-nuts] 5071A with ATTENTION flashing


Hi Li,

1)
When there is a "fatal error" the unit goes back into standby mode, where the 
Cs oven is turned off. Hence the Cs oven temperature error will again be at its 
maximum value (which is that -9.55 number). This is by design.

I use a script to send a scpi syst:print? command once a minute, in additional 
to logging diagnostic information. That way you can see the unit slowly warm up 
and see how each of the readings stabilizes over time. What you may find is 
that the temp error starts at -9.55 and then slowly decreases to zero as the Cs 
oven warms up. If lock is not achieved the oven is turned off and the error 
slowly climbs back down to -9.55. This is by design.

2)
Under ideal conditions a 5071A will lock within 10 to 15 minutes. But if the 
tube has been idle for months or years it can take half an hour or more. During 
this time the ion pump slowly improves the vacuum. So having a log file of 
periodic syst:print output allows you to follow the progress; of the ion pump, 
of the ovens, etc.

The fact that the log has only one entry suggests that someone cleared the 
entire log before you saw the instrument. That's unfortunate. It gives the 
impression the seller had something to hide.

3)
Some comments on the diag information:

> Cs oven is up

This suggests there's nothing wrong with the ion pump or the cesium oven. Your 
oven heater and controller are fine.

> Low Cs beam signal = 3

This is consistent with a tube that's used up all its cesium.

> Raising emult voltage...
> Low Cs signal (37) with max Emult

This is consistent with a 5071 that's trying very hard to get enough beam 
signal, but there just isn't enough cesium left. If a high-performance tube, 
this is expected after 7 to 10 years of use.

> Fatal Error (see Log)

Unlike older cesium standards, the 5071A is quite clever. When there's nothing 
else to do, it does a clean shutdown of ovens and reports a fatal error. The 
unit goes into standby. When I refuse to give up I try powering up the unit 
again and again several times a day.

If I suspect the tube is the problem I swap tubes from a working 5071 frame. 
This is a very simple way to decide if the problem is the frame or the tube. 
After a couple of days of trying, and if the diag messages and fatal errors are 
consistent, then I finally admit defeat and mark the tube bad. The good news is 
you then have an entire frame of spare parts! And also a Cs tube to put on the 
"Dremel" pile!

Finally, remember that even in standby mode, a 5071A makes a very attractive, 
high-quality 10 MHz quartz standard, with multiple output frequencies, with 
high-resolution digital frequency tuning, a LED clock and 1PPS input/output. 
You can turn it into a GPSDO by sending phase or frequency step SCPI commands. 
That is, there's no need for a DAC or EFC; we've talked before on the list 
about the advantages of a DDS-based GPSDO instead of the traditional DAC/EFC 
method.

/tvb

- Original Message - 
From: Li Ang 
To: Tom Van Baak ; Discussion of precise time and frequency measurement 
Sent: Tuesday, November 08, 2016 10:48 PM
Subject: Re: [time-nuts] 5071A with ATTENTION flashing


Hi Tom

I have collected the log from it. Log level is service. The 9.2G pll pass the 
test today. The log during the power-up process is also included.


Regards

Li Ang / BI7LNQ

-



scpi >

MJD0 02:02:18

CBT ID: 3128A00642(H)

Status summary: Fatal Error (see Log)

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Re: [time-nuts] 5071A with ATTENTION flashing

[Li Ang]

According to the Log, "CBT Oven Err: -9.55 C" might be something wrong. 
However, I can't find the correct range in the manual. Does anyone have the 
information about this parameter?


Regards
Li Ang




-- Original --
From:  "Li Ang";<379...@qq.com>;
Date:  Wed, Nov 9, 2016 02:48 PM
To:  "Tom Van Baak"<t...@leapsecond.com>; "Discussion of precise time and 
frequency measurement"<time-nuts@febo.com>; 

Subject:  Re: [time-nuts] 5071A with ATTENTION flashing



Hi Tom

I have collected the log from it. Log level is service. The 9.2G pll pass the 
test today. The log during the power-up process is also included.


Regards

Li Ang / BI7LNQ

-



scpi >

MJD0 02:02:18

CBT ID: 3128A00642(H)

Status summary: Fatal Error (see Log)

Power source: AC

Log status: One entry


Freq Offset:  0e-15  Osc. control: -9.56 %

RF amplitude 1: 6.3 %RF amplitude 2: 6.3 %

Zeeman Freq:  39949 Hz   C-field curr:12.213 mA

E-multiplier:  2553 VSignal Gain:   14.4 %


CBT Oven:   0.0 VCBT Oven Err: -9.55 C

Osc. Oven: -9.1 VIon Pump:   0.4 uA

HW Ionizer:-0.1 VMass spec:12.3 V

SAW Tuning: 0.0 VDRO Tuning: 7.3 V

87MHz PLL:  0.8 VuP Clock PLL:   1.8 V

+12V supply:   12.3 V-12V supply:  -12.3 V

+5V  supply:5.4 VThermometer:   46.2 C



scpi >

scpi > ?

E-103> exit

E-113>

E-113> Log status: One entry


Log 000 of MJD0 00:12:40:  Low Cs signal (60) with max Emult


PASS: CBT register test

PASS: CBT window comp test

PASS: CBT therm test

PASS: CBT Cs oven test

PASS: CBT hw ion test

PASS: CBT mass spec test

PASS: CPU RTDS test

PASS: CPU clock locked test

PASS: DDFS register test

PASS: 87MHz PLL test

PASS: 9.2 GHz PLL test

PASS: Servo register test

PASS: Servo convertor timeout test

PASS: Interface register test

PASS: Interface abus test

PASS: Pps register test

PASS: Pps interrupt test

PASS: power logic signals test

PASS: CBT register test

PASS: CBT window comp test

PASS: CBT therm test

PASS: CBT Cs oven test

PASS: CBT hw ion test

PASS: CBT mass spec test

PASS: CPU RTDS test

PASS: CPU clock locked test

PASS: DDFS register test

PASS: 87MHz PLL test

PASS: 9.2 GHz PLL test

PASS: Servo register test

PASS: Servo convertor timeout test

PASS: Interface register test

PASS: Interface abus test

PASS: Pps register test

PASS: Pps interrupt test

PASS: power logic signals test

PASS: CBT register test

PASS: CBT window comp test

PASS: CBT therm test

PASS: CBT Cs oven test

PASS: CBT hw ion test

PASS: CBT mass spec test

PASS: CPU RTDS test

PASS: CPU clock locked test

PASS: DDFS register test

PASS: 87MHz PLL test

PASS: 9.2 GHz PLL test

PASS: Servo register test

PASS: Servo convertor timeout test

PASS: Interface register test

PASS: Interface abus test

PASS: Pps register test

PASS: Pps interrupt test

PASS: power logic signals test

PASS: CBT register test

PASS: CBT window comp test

PASS: CBT therm test

PASS: CBT Cs oven test

PASS: CBT hw ion test


E-113>

E-113> PASS: CBT register test

PASS: CBT window comp test

PASS: CBT therm test

PASS: CBT Cs oven test

PASS: CBT hw ion test

PASS: CBT mass spec test

PASS: CPU RTDS test

PASS: CPU clock locked test

PASS: DDFS register test

PASS: 87MHz PLL test

PASS: 9.2 GHz PLL test

PASS: Servo register test

PASS: Servo convertor timeout test

PASS: Interface register test

PASS: Interface abus test

PASS: Pps register test

PASS: Pps interrupt test

PASS: power logic signals test

PASS: CBT register test

PASS: CBT window comp test

PASS: CBT therm test

PASS: CBT Cs oven test

PASS: CBT hw ion test

PASS: CBT mass spec test

PASS: CPU RTDS test

PASS: CPU clock locked test

PASS: DDFS register test

PASS: 87MHz PLL test

PASS: 9.2 GHz PLL test

PASS: Servo register test

PASS: Servo convertor timeout test

PASS: Interface register test

PASS: Interface abus test

PASS: Pps register test

PASS: Pps interrupt test

PASS: power logic signals test

PASS: CBT register test

PASS: CBT window comp test

PASS: CBT therm test

PASS: CBT Cs oven test

PASS: CBT hw ion test

PASS: CBT mass spec test

PASS: CPU RTDS test

PASS: CPU clock locked test

PASS: DDFS register test

PASS: 87MHz PLL test

PASS: 9.2 GHz PLL test

PASS: Servo register test

PASS: Servo convertor timeout test

PASS: Interface register test

PASS: Interface abus test

PASS: Pps register test

PASS: Pps interrupt test

PASS: power logic signals test

PASS: CBT register test

PASS: CBT window comp test

PASS: CBT therm test

PASS: CBT Cs oven test

PASS: CBT hw ion test

PASS: CBT mass spec test

PASS: CPU RTDS test

PASS: CPU clock locked test

PASS: DDFS register test

PASS: 87MHz PLL test

PASS: 9.2 GHz PLL test

PASS: Servo register test

PASS: Servo convertor

Re: [time-nuts] 5071A with ATTENTION flashing

[Li Ang]

Hi Tom

I have collected the log from it. Log level is service. The 9.2G pll pass the 
test today. The log during the power-up process is also included.


Regards

Li Ang / BI7LNQ

-



scpi >

MJD0 02:02:18

CBT ID: 3128A00642(H)

Status summary: Fatal Error (see Log)

Power source: AC

Log status: One entry


Freq Offset:  0e-15  Osc. control: -9.56 %

RF amplitude 1: 6.3 %RF amplitude 2: 6.3 %

Zeeman Freq:  39949 Hz   C-field curr:12.213 mA

E-multiplier:  2553 VSignal Gain:   14.4 %


CBT Oven:   0.0 VCBT Oven Err: -9.55 C

Osc. Oven: -9.1 VIon Pump:   0.4 uA

HW Ionizer:-0.1 VMass spec:12.3 V

SAW Tuning: 0.0 VDRO Tuning: 7.3 V

87MHz PLL:  0.8 VuP Clock PLL:   1.8 V

+12V supply:   12.3 V-12V supply:  -12.3 V

+5V  supply:5.4 VThermometer:   46.2 C



scpi >

scpi > ?

E-103> exit

E-113>

E-113> Log status: One entry


Log 000 of MJD0 00:12:40:  Low Cs signal (60) with max Emult


PASS: CBT register test

PASS: CBT window comp test

PASS: CBT therm test

PASS: CBT Cs oven test

PASS: CBT hw ion test

PASS: CBT mass spec test

PASS: CPU RTDS test

PASS: CPU clock locked test

PASS: DDFS register test

PASS: 87MHz PLL test

PASS: 9.2 GHz PLL test

PASS: Servo register test

PASS: Servo convertor timeout test

PASS: Interface register test

PASS: Interface abus test

PASS: Pps register test

PASS: Pps interrupt test

PASS: power logic signals test

PASS: CBT register test

PASS: CBT window comp test

PASS: CBT therm test

PASS: CBT Cs oven test

PASS: CBT hw ion test

PASS: CBT mass spec test

PASS: CPU RTDS test

PASS: CPU clock locked test

PASS: DDFS register test

PASS: 87MHz PLL test

PASS: 9.2 GHz PLL test

PASS: Servo register test

PASS: Servo convertor timeout test

PASS: Interface register test

PASS: Interface abus test

PASS: Pps register test

PASS: Pps interrupt test

PASS: power logic signals test

PASS: CBT register test

PASS: CBT window comp test

PASS: CBT therm test

PASS: CBT Cs oven test

PASS: CBT hw ion test

PASS: CBT mass spec test

PASS: CPU RTDS test

PASS: CPU clock locked test

PASS: DDFS register test

PASS: 87MHz PLL test

PASS: 9.2 GHz PLL test

PASS: Servo register test

PASS: Servo convertor timeout test

PASS: Interface register test

PASS: Interface abus test

PASS: Pps register test

PASS: Pps interrupt test

PASS: power logic signals test

PASS: CBT register test

PASS: CBT window comp test

PASS: CBT therm test

PASS: CBT Cs oven test

PASS: CBT hw ion test


E-113>

E-113> PASS: CBT register test

PASS: CBT window comp test

PASS: CBT therm test

PASS: CBT Cs oven test

PASS: CBT hw ion test

PASS: CBT mass spec test

PASS: CPU RTDS test

PASS: CPU clock locked test

PASS: DDFS register test

PASS: 87MHz PLL test

PASS: 9.2 GHz PLL test

PASS: Servo register test

PASS: Servo convertor timeout test

PASS: Interface register test

PASS: Interface abus test

PASS: Pps register test

PASS: Pps interrupt test

PASS: power logic signals test

PASS: CBT register test

PASS: CBT window comp test

PASS: CBT therm test

PASS: CBT Cs oven test

PASS: CBT hw ion test

PASS: CBT mass spec test

PASS: CPU RTDS test

PASS: CPU clock locked test

PASS: DDFS register test

PASS: 87MHz PLL test

PASS: 9.2 GHz PLL test

PASS: Servo register test

PASS: Servo convertor timeout test

PASS: Interface register test

PASS: Interface abus test

PASS: Pps register test

PASS: Pps interrupt test

PASS: power logic signals test

PASS: CBT register test

PASS: CBT window comp test

PASS: CBT therm test

PASS: CBT Cs oven test

PASS: CBT hw ion test

PASS: CBT mass spec test

PASS: CPU RTDS test

PASS: CPU clock locked test

PASS: DDFS register test

PASS: 87MHz PLL test

PASS: 9.2 GHz PLL test

PASS: Servo register test

PASS: Servo convertor timeout test

PASS: Interface register test

PASS: Interface abus test

PASS: Pps register test

PASS: Pps interrupt test

PASS: power logic signals test

PASS: CBT register test

PASS: CBT window comp test

PASS: CBT therm test

PASS: CBT Cs oven test

PASS: CBT hw ion test

PASS: CBT mass spec test

PASS: CPU RTDS test

PASS: CPU clock locked test

PASS: DDFS register test

PASS: 87MHz PLL test

PASS: 9.2 GHz PLL test

PASS: Servo register test

PASS: Servo convertor timeout test

PASS: Interface register test

PASS: Interface abus test

PASS: Pps register test

PASS: Pps interrupt test

PASS: power logic signals test

PASS: CBT register test

PASS: CBT window comp test

PASS: CBT therm test

PASS: CBT Cs oven test

PASS: CBT hw ion test

PASS: CBT mass spec test

PASS: CPU RTDS test

PASS: CPU clock locked test

PASS: DDFS register test

PASS: 87MHz PLL test

PASS: 9.2 GHz PLL test

PASS: Servo register test

PASS: Servo convertor timeout test

PASS: Interface register test

PASS: Interface abus test

PASS:

Re: [time-nuts] 5071A with ATTENTION flashing

[Li Ang]

Hi Tom
 Thanks for the info. I think I should pay a visit to this 5071a again.  There 
are 5 more 5071a 200km away, I need to visit them next week. :)



regards

Li Ang / BI7LNQ
---Original---
From: "Tom Van Baak"<t...@leapsecond.com>
Date: 2016/11/4 00:42:46
To: "Discussion of precise time and frequency measurement"<time-nuts@febo.com>;
Subject: Re: [time-nuts] 5071A with ATTENTION flashing


Hi Li,

The "Low cs signal with max Emult" is the classic error indicating it's out of 
gas. That's a bad sign. But the "9.2GHz PLL test 10.3v" is something else. So 
maybe there's hope? Or maybe you have two big problems instead of one. Rick 
might know.

For additional information, connect a PC to the serial port and capture the 
diagnostic information. Right after power up, press TOP -> CONFIG -> LOG -> 
SERVICE to set the unit into verbose diagnostic mode. You should see lines 
print every now and then as it undergoes self test and calibration.

You can also press TOP -> INFO -> PRINT to get a nicely formatted summary. Or 
TOP -> LOG -> PRINT to get the entire log history. That sometimes has lots of 
clues. The advantage of using the serial port is you get a permanent record of 
all this information. Viewing all this by the LCD screen can be tedious.

There's more information in 05071-90040, the 5071A Assembly-Level Service 
Manual, copies of which are on the web. Also 05071-90041, Operating and 
Programming Manual.

/tvb

- Original Message - 
From: "Li Ang" <379...@qq.com>
To: "time-nuts" <time-nuts@febo.com>
Sent: Thursday, November 03, 2016 8:10 AM
Subject: [time-nuts] 5071A with ATTENTION flashing


> Hi
>  Today I met one HP 5071A with option 001 at one secondhand equipment 
> company. This one can not enter CONTINUOUS OPERATION status, the ATTENTION 
> led flashes. 
>  There is a "Low cs signal with max Emult" error in the log. I have run the 
> self-test, and it stopped at "9.2GHz PLL test 10.3v".  I can only remember 
> the the pump current was 0.8uA or less, C-filed was about 12mA. 
>   The seller is asking for about 4000$, I am wondering if it's repairable. 
> Since it is a "HP" branded 5071A with 001 option,  I do not know if the Cs 
> tube is dying or not, according to the two current values? 
>   How do I know one 5071A/5061/5062 is dying or is still in good health by 
> the readings?
> 
> 
> Thanks
> 
> 
> de BI7LNQ


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Re: [time-nuts] Time nut soon to be in Shenzhen

[Li Ang]

Hi
   Welcome to Shenzhen. As far as I know there is no market that you can see 
pile of OCXO. They were taken off from equipments, and the process is done in 
the Qingyuan or Shanwei city Guangdong province. The seller might be in 
Shenzhen, but the source is in Qingyuan/Shanwei. These city have a lot of 
people doing the disassembly , recycle and alchemy work. 

However, there are a lot of eletronics markets near Huaqiangbei. I think you 
should pay a visit there. There are some 2nd-hand test equipment sellers in 
Duhui,  Xinyazhou market. Since the rental price is quite high in Huaqiangbei, 
most 2nd-hand test equipment selles and warehouses are not there. 
If you are interested in some other things, maybe I can give you more detailed 
info.(place to buy, reference price, etc.).  

   

---Original---
From: "Christopher Hoover"
Date: 2016/11/6 23:13:55
To: "Discussion of precise time and frequency measurement";
Subject: [time-nuts] Time nut soon to be in Shenzhen


I'm in Shanghai now but will be leaving for Shenzhen in a few days.  Any
one know of any special time nutty stuff to check out in Shenzhen?  I
expect if I can find the right place I might see piles of OCXO's.

Thanks, Christopher and 73 de AI6KG
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[time-nuts] 5071A with ATTENTION flashing

[Li Ang]

Hi
  Today I met one HP 5071A with option 001 at one secondhand equipment company. 
This one can not enter CONTINUOUS OPERATION status, the ATTENTION led flashes. 
  There is a "Low cs signal with max Emult" error in the log. I have run the 
self-test, and it stopped at "9.2GHz PLL test 10.3v".  I can only remember the 
the pump current was 0.8uA or less, C-filed was about 12mA. 
   The seller is asking for about 4000$, I am wondering if it's repairable. 
Since it is a "HP" branded 5071A with 001 option,  I do not know if the Cs tube 
is dying or not, according to the two current values? 
   How do I know one 5071A/5061/5062 is dying or is still in good health by the 
readings?


Thanks


de BI7LNQ
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[time-nuts] TDC-GP22 vs TDC7200

[Li Ang]

Hi
I got 5 samples of TDC7200 from TI a few months ago. I have made a board to 
test it with TDC-GP22 from ACAM. Actually it's a new board of my frequency 
counter. The CPU system is changed from MCU to a OrangePi board. The digital 
part is still a Cyclone 4 FPGA. 


Verilog: http://www.qsl.net/bi7lnq/Projects/freqcnt4.2/100ns_noise_test.v
Picuture: http://www.qsl.net/bi7lnq/Projects/freqcnt4.2/5.2.jpg
Result: http://www.qsl.net/bi7lnq/Projects/freqcnt4.2/100ns_stdev.xls


   The DC-DC part works at 4MHz (MP2560), it generates a lot of noise. (stdev 
of 1000 measures is around 300ps).  It's a mistake to put that on board.  
However, if the 5v is supplied by a HP E3630A, the performance is much more 
stable.
   The 100ns start-and-stop signal is generated by FPGA. I do not know if it's 
a stable way to do that. The 10MHz ref clock is from one FE180 OCXO and shaped 
by NC7SZU04.
   The STDEV of 1000 measurements by TDC_GP22 is 70ps. (45ps double resolution 
mode, STDEV is not given by the datasheet)
   The STDEV of 1000 measurements by TDC7200 is 20ps. (datasheet: 55ps 
resolution, 35ps STDEV RMS  )


So I think the TDC7200 is a better choice for my homebrew frequency 
counter. It's much more friendly to solder(TSSOP vs QFN). It's much more esay 
to config(2 Hours of coding vs 2 weeks of debugging). It's a little more 
expensive than TDC-GP22(9$ vs 4$).






de BI7LNQ
73
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Re: [time-nuts] DMTD - analog multiplier vs. diode mixer ?

[Li Ang]

Hi
 Thanks to all the information here. I can put more items to my experiment
list.


Regads
Li Ang, BI7LNQ

2016-01-11 11:28 GMT+08:00 Magnus Danielson <mag...@rubidium.dyndns.org>:

> Moin,
>
> On 01/10/2016 07:56 PM, Attila Kinali wrote:
>
>> On Sun, 10 Jan 2016 14:30:41 +0100
>> Magnus Danielson <mag...@rubidium.dyndns.org> wrote:
>>
>> SR-flipflop? Are you refering to the JK-FF phase detector or the PFD?
>>>>
>>>
>>> A straight SR-flipflop. I would have written JK-FF or PFD if I meant it.
>>> Also, as I mentioned the PFD directly after, you could have concluded
>>> that was not what I intended.
>>>
>>> A SR-flip-flop with no illegal input states is easy to build from a
>>> 74HC00.
>>>
>>
>> The illegal input states were my concern, indeed. And a quick google
>> didn't show up anything to disperse thesenot until I started reading
>> the 4046 datasheet in detail.
>>
>
> That's one place to look yes.
>
> But there is one thing about the arangement of the SR FF in the 4046[1]
>> that bothers me:
>> Although S = R = 1 is valid, it does lead to the output oscillating
>> between 0 and 1.
>>
>
> Well, the dynamics of the gates will convert the rising edges on S and R
> into short pulses before hitting the SR core. That is what the additional
> AND gates does if you look at figure 1.
>
> The pulses on Sd and Rd will be about three gate-delays long.
>
> If the Sd and Rd '1' pulses overlap, then it becomes a bit hairer to
> analyze the stability.
>
> However, this works pretty well in reality. Rather than having the +/- 90
> degree property of the XOR gate (which has a triangle phase-response, which
> doesn't always is helpful) it has a +/- 180 degree sawtooth phase-response.
>
> Cheers,
> Magnus
>
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Re: [time-nuts] DMTD - analog multiplier vs. diode mixer ?

[Li Ang]

Hi Bob,
In some article, I see people use a D-flipflop to sample the input
signal with reference clock. When you want implement a mixer what's the
difference between D-flipflop and XOR gate? Acorrding to my understanding,
to multiply 1bit with another, I should use an AND gate, right?
When you refer high speed CMOS XOR gate, do you mean 74LVC1G86?

Thanks

BI7LNQ


2016-01-09 6:42 GMT+08:00 Bob Camp :

> Hi
>
> The board I have uses high speed CMOS single gate XOR’s. They have a
> pretty good
> phase noise floor (-170’s) so they should be pretty reasonable.
>
> Bob
>
> > On Jan 8, 2016, at 12:16 PM, Richard (Rick) Karlquist <
> rich...@karlquist.com> wrote:
> >
> >
> >
> > On 1/7/2016 3:11 PM, Bob Camp wrote:
> >> Hi
> >>
> >> If your intention is to run a mixer with saturated inputs …. just run
> >> an X-OR gate. It will handle the high level signals much better than
> >> an over-driven analog part.
> >
> >> Bob
> >>
> >
> > If you look at the schematic of an XOR gate IC and compare it
> > to the schematic of, for example, an MC1496 mixer, you will
> > see a lot of similarity.  If the gate is of the ECL type,
> > it will have the addition of emitter followers, but that
> > it a minor detail of implementation.  I'm not sure there
> > is a huge difference.  ECL is a great logic family in
> > general (self-confessed ECL-phile here :-) but it is
> > probably the worst for phase noise, compared to the
> > saturating logic types.
> >
> > Rick Karlquist N6RK
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Re: [time-nuts] homebrew counter new board test result

[Li Ang]

 Hi
   Thanks about the explanation on hysteresis and comparator.
   The PM6685(http://assets.fluke.com/manuals/PM6685__smeng.pdf )
is using 74ALS176 as the frontend for REF channel.
So
I tried that on the previous board. The performance is better with
74ALS176+74LVC2G14 than MC100LVELT22 at the sin wave input condition.
Since the stdev has reached the spec of TDC chip, I need to do
some more experiments with these chips next.
There are some questions I want to ask:
1) Does the trigger interval need to be very accurate? Now I am using
software scheduler to generate the interval, it might vary few ms.
2) Does any one have the test data of 12 digit/s counter when DUT=REF?
I want to know the gap between mine and a  commercial counter.


Thanks

Li Ang

2015-02-27 4:30 GMT+08:00 Charles Steinmetz csteinm...@yandex.com:

 Magnus wrote:

  A bit of hysteresis can help to avoid flipping back, but considering the
 type of signal, it passes the mid-point (0 V) at highest slew-rate, so
 there is very little risk of flipping back and fourth in the first
 place, so hysteresis may not even be needed.


 A 1 Vrms, 10MHz sine wave has a zero-cross slew rate of 88v/uS (88mV/nS).
 One would think that would be enough to avoid indecision in a comparator
 with 5-10nS of propagation delay.  However, the LT1016 (10nS) is prone to
 jitter problems when operating as a ZCD with such a signal, and external
 hysteresis does not help much because it is delayed by 10nS.  (The problem
 appears to be that the front end has some indecision at this input slew
 rate that happens faster than the propagation delay to the output -- but
 this is just an inference because the internal nodes are not accessible for
 measurement.)  For this application, the small amount of internal
 hysteresis of the LT1719 and LT1720 is very beneficial.

 Best regards,

 Charles





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Re: [time-nuts] homebrew counter new board test result

[Li Ang]

Hi Attila
  Thanks for the history about 74 series.
  BTW, The result.gif is a TDEV chart. I only know that different K means
different kinds of noise. I don't know what it means if the turnning corner
comes earlier or latter.

Hi Charles
 Thanks for the circuit. I have some LT1016 in hand, I will evaluate with
it.



2015-02-25 0:02 GMT+08:00 Attila Kinali att...@kinali.ch:

 On Tue, 24 Feb 2015 14:43:10 +0800
 Li Ang lll...@gmail.com wrote:

  I saw people talking about using 74AC to square the signal, what's
 the
  difference between 74LVC and 74AC? 74AC is not easy to get.

 These are different families of chip production. You can see the 74HCxx as
 the grandfather, 74ACxx as the father and the 74LVCxx as the son.

 IIRC the AC (Advanced CMOS) was introduced in the 80s. The process
 which they were produced got superseeded and also the voltage levels
 went down. The LVC (Low Voltage CMOS) and LVX families are the current
 choice for logic gates. The main difference is that the node size (those nm
 measures people boast with, when they talk about chips these days) went
 down and with that the threshold voltage of the FETs and the maximum
 voltage the chips can withstand. Of course there are differences in the
 timing specs as well.

 TI's Logic Guide[1] and their Logic Migration Guide[2] contain
 additional information.


 Attila Kinali


 [1] http://www.ti.com/lit/sg/sdyu001aa/sdyu001aa.pdf
 [2] http://www.ti.com/lit/ml/scyb032/scyb032.pdf

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Re: [time-nuts] homebrew counter new board test result

[Li Ang]

Hi Magnus,
The C channel is the SMA on the back of the PCB. The input of 74LVC2G14
is set to 0.5vcc with 1k resistor and AC coupled with 100nF.
Today I compared the performance 74LVC2G04, 74LVC2G17, 74LVC2G14.
http://www.qsl.net/b/bi7lnq//freqcntv4.1/test/20150224/  .
I saw people talking about using 74AC to square the signal, what's the
difference between 74LVC and 74AC? 74AC is not easy to get.

Thanks

Li Ang

2015-02-24 5:36 GMT+08:00 Magnus Danielson mag...@rubidium.dyndns.org:

 Dear Li Ang,

 Nice to have you back reporting on your progress!

 Now, you have some pretty impressive performance going on there. Looks
 like a nice little unit too.

 Is the C-channel the SMA on the back of the PCB?

 How did you wire up the 74LVC2G14?

 While it is tempting to use both channels in it, don't if you want to keep
 cross-talk between channels low.

 Cheers,
 Magnus


 On 02/23/2015 02:10 PM, Li Ang wrote:

 Hi,
 I'm back. I have been testing my new borad for days.
 Compared to previous version, this board makes the PCB track of
 signals far from each other and replaces LDO for TDC with LP5907.
 CH_A: simple resistor bias and ac couple front end, CH_B:
 CH_A+MC100LVELT22 LVPECL , CH_C: CH_A+74LVC2G14 .
 At first, the result is worse than previous board. Using CH_B as the
 REF and DUT source, the stdev of the phase measurement is about 160ps. The
 old board can reach about 70ps. CH_A and CH_C are way much better than
 CH_B. That bothers me for days.
 Today, I use the 74LVC2G14 to square the signal from MV89A, and do
 the same test. For all three channel, the stdevs are about 37ps. The spec
 of TDC_GP22 is 35ps. And now the performance looks a little bit better than
 the previous board.  It looks like that the jitter of MC100LVELT22 is much
 bigger at slow slew rate.
 It seems that next step is to play with the front end.


 The raw data is uploaded to http://www.qsl.net/b/bi7lnq/
 freqcntv4.1/test/20150222/
 The pic of this version is uploaded to http://www.qsl.net/b/bi7lnq/
 freqcntv4.1/pic/ ‍




 Regards
 Li Ang



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[time-nuts] homebrew counter new board test result

[Li Ang]

Hi,
   I'm back. I have been testing my new borad for days.
   Compared to previous version, this board makes the PCB track of signals far 
from each other and replaces LDO for TDC with LP5907.
   CH_A: simple resistor bias and ac couple front end, CH_B: 
CH_A+MC100LVELT22 LVPECL , CH_C: CH_A+74LVC2G14 .
   At first, the result is worse than previous board. Using CH_B as the REF and 
DUT source, the stdev of the phase measurement is about 160ps. The old board 
can reach about 70ps. CH_A and CH_C are way much better than CH_B. That bothers 
me for days.
   Today, I use the 74LVC2G14 to square the signal from MV89A, and do the same 
test. For all three channel, the stdevs are about 37ps. The spec of TDC_GP22 is 
35ps. And now the performance looks a little bit better than the previous 
board.  It looks like that the jitter of MC100LVELT22 is much bigger at slow 
slew rate.
   It seems that next step is to play with the front end. 


The raw data is uploaded to 
http://www.qsl.net/b/bi7lnq/freqcntv4.1/test/20150222/
The pic of this version is uploaded to 
http://www.qsl.net/b/bi7lnq/freqcntv4.1/pic/ ‍




Regards
Li Angattachment: results.gif
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Re: [time-nuts] New algorithm, better ADEV

[Li Ang]

2015-01-18 21:44 GMT+08:00, Tom Van Baak t...@leapsecond.com:
 Now, the next step is using two different, but very stable, references that
 have a known frequency offset. The problem with using the same REF/DUT is
 that you do not get exposure across the entire 100 ns period of the 10 MHz
 frequency. An alternative is to try the experiment a few times, with say, a
 10, 20, and 50 ns cable delay in one of the paths.

 /tvb


Hi
  I have done an 8 hour test with X72 as DUT and FE5650 as Reference.
The data is uploaded to
http://www.qsl.net/bi7lnq/freqcntv4/test/20150119/x72_FE5650.tim

Thanks

Li Ang
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Re: [time-nuts] L1 and L2 frequencies

[Li Ang]

Hi
  I have a question about the GPS antenna. Since the GPS signal strength on
the ground is about 20db lower than the thermal noise, does the gain of
antenna matter?

2015-01-16 7:01 GMT+08:00 Björn Gabrielsson b...@lysator.liu.se:

 Magnus,

  If civilian receivers where to implement L2C and L5 which now is
  becoming common, they would gain quite a bit of precision in a similar
  fashion. For car navigation, the GPS would know which lane you are in.
 
  There ARE civilian receivers doing this, and has been for quite some
  years. And its not from only a few vendors - all the big ones have it -
  Trimble, Novatel, Topcon, Javad, Leica, Septentrio and a few more. There
  are now receivers tracking GPS L1/L2/L2C/L5, Galileo
  E1/E5A/E5B/AltBoc/E6, GLONASS L1/L2/L3, BeiDou B1/B2/B3, QZSS L1/L2/L5
 
  The price exceeds my home hobby budget, but so does a replacement
  CS-tube
  a factory new OCXO based GPSDO and many other things you can sometime
  find
  at reasonable cost used/recycled.
 
  I naturally meant with a reasonable price-tag, sorry for being sloppy on
  that detail, and I do know that there is vendors for those signals.
 
  If we had dual or triple frequency receivers below 500 USD things would
  start to be interesting. If high-volume kits would be just twice as
  expensive, it would be possible to consider for more luxury models.

 Receiver with 24 universal channels each of GPS L1/L2/L2C/L5 is cheaper
 than a entry level TCXO-based 19 GPSDO (M300GPS @ Dustin). And about the
 same price as a modern Loran receiver. What is a reasonable commercial
 price?

  But yes, multi frequency GNSS is much more expensive than the Oncore,
 Ublox traditionally used in a GPSDO. Is the performance gain worth the
 cost? Certainly not for all but a few.

 On the oscillator side, we consider everything from XO, TCXO, OCXO, DOCXO,
 to devar based designs - BVAs and others, and rubidiums, cesiums and
 Masers. What are reasonable price-tags for oscillators compared to various
 time transfer capable receiver?

 --

  Björn

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Re: [time-nuts] New algorithm, better ADEV

[Li Ang]

Magnus Danielson magnus@... writes:


 
 Which display is it?
 

Hi Mangus,
I do not know the model name, but I found the same one on ebay (key word 
2.2 TFT SPI). It's a SPI screen, so it shows things quite slow. However, 
320x240 resolution is good to display a lot of slow changing stuffs. I use 
this because it's smaller than the LCD1602 module. 
 

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Re: [time-nuts] New algorithm, better ADEV

[Li Ang]

Tom Van Baak tvb@... writes:


 Just use:
   ref_delta = ref_curr - ref_prev;
   sig_delta = sig_curr - sig_prev;
 
 Not only is it much simpler but it also works in every case (your code 
would fail whenever curr equals prev).
 
 Here's a test program in case you don't believe me: 
http://leapsecond.com/tools/wrap1.c
 
 /tvb
 

Hi Tom,
  Yes, your way is simpler and reliable since the variables are all 
uint32_t type. Thanks for pointing out the mistake.




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[time-nuts] New algorithm, better ADEV

[Li Ang]

Hi
Just now, I changed the way to calculate frequency and get a better
ADEV chart.
http://www.qsl.net/b/bi7lnq/freqcntv4/test/20150114/0114.gif
http://www.qsl.net/b/bi7lnq/freqcntv4/test/20150114/newway.tim
http://www.qsl.net/b/bi7lnq/freqcntv4/test/20150114/oldway.tim


Thanks to John Miles's reply in the thread about ADEV.

 If you feed in frequency samples, it will convert them to phase-difference 
 samples internally, so the
 program itself doesn't really care.  The use of frequency data has a few 
 drawbacks such as less accurate
 ADEV plots due to the counter's dead time between readings, but it's the 
 easiest way to get started and is
 perfectly usable for many purposes.


Old way:
//reset counter every second to avoid the overflow issue
while (1) {
 reset_fpga_counter();
 trigger_and_read_cnt(refA, sigA);
 delay_1s();
 trigger_and_read_cnt(refB, sigB);
 Freq = Calc_freq(refB - refA, sigB - sigA);
}


New way:
//The counter keeps running. The software takes care of the overflow issue.
No dead time.
trigger_and_read_cnt(ref_prev, sig_prev);
while (1) {
   delay_1s();
   trigger_and_read_cnt(ref_curr, sig_curr);
   ref_delta = (ref_curr  ref_prev) ? (ref_curr - ref_prev) : (0x
- ref_prev + ref_curr);
   sig_delta = (sig_curr  sig_prev) ? (sig_curr - sig_prev) : (0x
- sig_prev + sig_curr);

   Freq = CalcFreq(ref_delta, sig_delta);
   ref_prev = ref_curr;
   sig_prev = sig_curr;
}


BTW: I've put the counter into a box.
http://www.qsl.net/b/bi7lnq/freqcntv4/pic/20150114_212857.jpg
more pictures: http://www.qsl.net/b/bi7lnq/freqcntv4/pic/
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Re: [time-nuts] schematics of frequency counter

[Li Ang]

Magnus Danielson magnus@... writes:

 
 Hi,
 
 Darn, not reading all the notes. Again.
 
 Well, in that case, scaling should be done... then you get average of 
 198,5075 ns and 149,8 ps RMS jitter, with 1,1 ns peak-to-peak.
 
 The jitter is okish then, but a little better would indeed be nice.
 
 Cheers,
 Magnus


Hi Magnus,
   I've noticed that they have put stddev in the latest datasheet of 
TDC_GP22.
(http://www.acam.de/fileadmin/Download/pdf/TDC/English/DB_GP22_en.pdf)

Standard deviation(mode1 DOUBLE_RES = 0 Delay = 200ns) is 45ps. My result 
shows 150ps. At least I know the limit is there now. There is something 
need to figure out.

Thanks

Li Ang



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Re: [time-nuts] schematics of frequency counter

[Li Ang]

Hi
   Today I did the same test without these 2 oscillators. The stddev on
20141228 data is 149ps. The stddev of today is 97ps. According to the new
datasheet, stddev will be lower if set to 45ps resolution mode. I did that
and got 76ps stddev. The datasheet does not lie to me :).

  Data is uploaded to
http://www.qsl.net/b/bi7lnq//freqcntv4/test/20150108/tdc_stddev.xls

The configuration of tdc-gp22 is now:
Register_0 = 0x00c42700,
//Register_1 = 0x19498000, //stop2-stop1
Register_1 = 0x01418000,//0x01418000, //stop1-start,
Register_2 = 0xe000,
Register_3 = 0x,
Register_4 = 0x2000,
Register_5 = 0  27,
Register_6 = 1  12;



2015-01-06 7:33 GMT+08:00 Li Ang lll...@gmail.com:

 Hi Bob,
   There are 2 oscillator on board, one 8MHz for MCU one 125MHz for FPGA.
 I've took it down from the board, and changed MCU to use internal RC
 oscillator for MCU and PLL to mutilply refclk to 200MHz for FPGA.
   I will try do the same test tonight thanks.



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Re: [time-nuts] schematics of frequency counter

[Li Ang]

Hi Neil
   Just now, I disconnected TPS79333 from board and used  LR6 battery for
the analog part of TDC. The result does not show improvement. So I think
LDO might not be the primary noise contributor.


Thanks for the suggestion.

2015-01-03 22:01 GMT+08:00 Neil Schroeder gign...@gmail.com:

 I would reconsider the LDOs while you have some time to play with them.
 The TPS79333DBVR is not even remotely ultralow noise at most offsets,
 despite what TI may say.

 For 5V5 and under up to about 600ma, I would suggest you take a look at the
 ADM7155 (adjustable) or ADM7154 (fixed). If you need 800ma, the 7150 is
 here for you.


 http://www.analog.com/en/power-management/linear-regulators/adm7155/products/product.html

 http://www.analog.com/en/power-management/linear-regulators/adm7150/products/product.html

 The TI part has nearly 35 uVRMS of noise  at just 2.8a with not very good
 PSRR.  The 7155 will produce less than  1.0 μVRMS Total Integrated Noise
 from 100 Hz to 100 KHz and 1.6 from 10 to 100 KHz,and that's without an RC
 noise compensation network.  Its a fabulous part for a sensitive
 application like yours.

 I'm hoping I am right in assuming that the noise performance of the LDOs is
 a concern, and don't mean to even dare suggest that you've done anything
 but a great job! :-)

 NS
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Re: [time-nuts] schematics of frequency counter

[Li Ang]

Charles Steinmetz csteinmetz@... writes:

 
 
 Actually, I dont want to ask my colledge for help. Everytime ,for 
each
 guy I ask for help, I need expain the entire system and principle of 
a
 frequency counter to him. They just keep asking questions instead of
   answering mine.
 
 In defense of the hardware guys, there are a lot of questions that 
 NEED to be asked (and answered) before a design that fulfills your 
 requirements can even be attempted.  I don't mean to be unkind, but 
 you skipped all of those questions, designed the software, and now 
 you want someone to hand you a hardware design that solves the 
 problems you are having.  From what I can tell, you still don't even 
 have a good concept of what the hardware needs to do, much less how 
 to specify these needs as coherent project requirements -- and even 
 less how to actually design the circuitry you need.  Furthermore, 
 when someone suggests something that might fix a glaring error in 
 your design, you say you can't do that because (for example) PNP 
 transistors are too expensive.
 
 Ask any competent engineering manager and you will learn that good 
 analog design engineers are the rarest and hardest to find 
 development team members, and that getting the hardware right is very 
 often the hardest part of any design (note that I did not say, most 
 time-consuming -- rather, hardest).
 
 So, now you need the analog hardware for your counter, and you have 
 the mistaken impression that it shouldn't be any effort at 
 all.  Hopefully, you are now beginning to understand that at least as 
 much good thinking needs to go into the hardware as into the 
 software.  And hopefully, you have reviewed the analog circuitry of 
 some good commercial designs to see what sorts of things good analog 
 designers have done in the past to solve the same problems you are 
facing.
 
 You said yourself that you don't really know anything about analog 
 design, and your existing circuit and your comments here on the list 
 show that to be an honest and true assessment.  But you also have 
 resisted advice you have gotten from experienced analog designers, 
 and now you say you can't even be bothered to answer the questions of 
 people who would try to help you!
 
 At this point, I'm afraid that whatever is posted on this thread 
 isn't really going to help you improve on what you have -- it is just 
 so much wasted internet bandwidth.  You need to learn at least enough 
 about analog design to ask and answer intelligent questions about 
 your needs, and you need to be willing to consider the advice you 
 receive, before any of this can help you.
 
 Best regards,
 
 Charles
 
 


Hi Charles,
   I don't mean to offend hardware guys. I've got a lot of help from 
them. The questions I am talking are something like: my 2.4G counter 
costs only 10$, why do you want to build one? Why don't you multiply 
reference clock to 400M with your FPGA as reference? Why do you need so 
many digits? It's PLL age, who needs a frequency counter? ... 
   On this list, a lot of experienced people like you have given me a 
lot of suggestions. If my words sound like resist advises I don't mean 
that. (I did say ADM7150 is too expensive and has different package that 
I can not use it now. However, I have done test of changing FPGA's 
current strength  slew rate to see if the noise of TDC power supply 
matters.)
   Because some are easy to achieve on my current board, some need to 
modify the hardware. I choose the suggestions that can be done at the 
moment. Something like PNP transistor or low noise LDO need new board to 
verify. I have got some BFT92 and looking for pin-pin compatible low 
noise LDO to play with.



Thanks

Li Ang



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Re: [time-nuts] schematics of frequency counter

[Li Ang]

Hi Magnus
You are right, I could compensate it in the software. I've tried that.
The software sets sig=ref=10MHz and measures start-to-stop time t1. Then,
it sets sig=ref=5MHz and measures time t2. With t1  t2, I could get the
time difference between the start path and the stop path. Repeat it 1000
times every second and get the RMS value of it. I use the RMS value to
compensate the result of the following second, but get much worse ADEV
chart.

I've uploaded the verilog code and schematic to
http://www.qsl.net/bi7lnq/freqcntv4/code/freqcnt_v4.zip and
http://www.qsl.net/bi7lnq/freqcntv4/freqcnt_bi7lnq_v4.pdf.
The idea is from http://n1.taur.dk/permanent/*frequency*measurement.pdf
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Re: [time-nuts] schematics of frequency counter

[Li Ang]

Hi Bob,
   Actually, I dont want to ask my colledge for help. Everytime ,for each
guy I ask for help, I need expain the entire system and principle of a
frequency counter to him. They just keep asking questions instead of
 answering mine. :(

   The 2 MV89As are powered by the same power supply right now. Next time I
will use dedicated power supply for them. The linear power supply is just
too noisy in the night.

   Using 10MHz as MCU clock is a good idea. Next time I modify the
schematic I will make the change.
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Re: [time-nuts] schematics of frequency counter

[Li Ang]

Hi
   I've confirmed that it's 198ns between start and stop with my racal dana
1992. I've spent days to learn how to compensate this 2ns in Quartus.
However, it's not something easy for me to do. I will ask some
hardware colleague for help.
   Two days ago, I assembled my 2 mv89a to PCB ,put them into 2 metal
boxes. The test time is longer than before since it's in the holiday. These
data confused me more. I got bigger frequency difference if sig=ref.
   Things are getting more and more compilcated. :(

raw data: http://www.qsl.net/bi7lnq/freqcntv4/test/20150105/0105.zip


Thanks

2014-12-29 4:35 GMT+08:00 Bob Camp kb...@n1k.org:

 Hi


  On Dec 28, 2014, at 9:19 AM, Li Ang lll...@gmail.com wrote:
 
  Hi Bob,
I did some test according to your suggestions. DUT is a symmetricom x72
  rb oscillator. Also, I've tried signal generator as the DUT. RS SMY01 is
  not as good as HP8662A but that the best I've got. The signal geneator is
  also using FE5650 as ref clock.
 
According to my test with the TDC today, this unit is not producing
 very
  stable data.
I don't have accurate pulse generator, so this is how I test the TDC:
  0) power the board with battery.
  1) use FPGA to generate time pulse:
  reg [15:0] shift;
  always @(posedge refclk10M) begin
  shift = {shift[14:0], sw_gate};
  end
  assign tdc_start = shift[3];
  assign tdc_stop1 = shift[5];
 
  2) use MCU to pull down sw_gate, the FPGA sync it to refclk10M domain and
  generate input signal for TDC.
 
  3) use TDC to test the time betwen tdc_start and tdc_stop1
 
  The result is in tdc_test.zip. number * 100ns = time between tdc_start
 and
  tdc_stop1. (TDC highspeed clock is refclk10M/2).
 
  There 2 issues from the test:
  1) As we can see from the data, the number is around 1.98x not 2.00x. So
  there is about 2ns delay between tdc_start and tdc_stop1 for this simple
  test code. If it is from the PCB trace and something inside FPGA, this
 part
  should be a constant value at certain temperature.

 So far all correct. If you are using Quartus, you can fire up the timing
 analyzer and take a look at what it guesses for timing / delay on the
 pulse. It is not a perfect number, but I’d bet it will confirm that the 2
 ns does come from the FPGA.

  I can calculate it by
  measuring 2 cycles and 3 cylces. My current code has not implement this
  part, it should provide some improvement. 2ns time error for 1s gate,
 that
  is something.

 The delay probably is from the input / output fabric on the FPGA ( =
 output driver). The test you propose should demonstrate this.

  2) For a 90ps TDC, I think the result should be something like +-0.001
  cycle. But I get something like +-0.003 cycle. I do not know the reason
 for
  now.

 Two reasonable *guesses* would be crosstalk and noise.

 1)  If there are any other clocks running around during this test, I’d see
 if they can be shut down. Things like an free running OCXO are good for
 this - they are easy to isolate.

 2) Noise could be internal to the TDC. If it’s 90 ns at one sigma, then
 you will indeed see +’/- 3 X that (or more) depending on how long you watch
 it. At least by my math the one sigma on the data is 149 ps. That’s a bit
 over 90 ps, but not terribly far.

 Delaying the signals relative to each other (clock and output) as Magnus
 suggests in another post is probably a real good idea for sorting some of
 this out.

 Bob

 
 
 
 
  2014-12-27 22:58 GMT+08:00 Bob Camp kb...@n1k.org:
 
  Hi
 
  (In reply to several posts. It’s easier for me this way)
 
  Ok, that’s good news !!! (and useful data)
 
  Your counter performance degraded a bit when you put in 5 db and not
 much
  when you put in 8 db.
 
  It’s also maybe *too* good news. I suspect that cross talk between the
  channels may be impacting your results.
 
  Next step is to try it with two independent sources and a bit more
  attenuation. When you try it with two sources, you need to attenuate
 first
  one source and then switch the attenuators to the other source. That
 will
  help you see if crosstalk from one channel is more of a problem than
 from
  the other channel.
 
  One parts hint:
 
  Cable TV attenuators are much cheaper than their fancy 50 ohm
 MIniCircuits
  cousins. They are also something you can pick up down at the corner
  electronics store. For this sort of testing they are perfectly fine to
 use.
  At this point in the testing the mismatch between 75 ohms and 50 ohms is
  not a big deal. You will need to adapt connectors, but you probably
 still
  will save money.
 
  ===
 
  Op-amps that have enough bandwidth and performance for a high input
  impedance counter input are rare items. They also are not cheap. Often
 they
  come as some sort of current feedback part with low(er) input
 impedance. If
  you want your counter to work to 300 MHz, it should accept a 300 MHz
 square
  wave. That might mean passing the third or even the fifth harmonic of
 the
  square wave. An input channel with 900 or 1500 MHz

Re: [time-nuts] schematics of frequency counter

[Li Ang]

Hi Bob,
  There are 2 oscillator on board, one 8MHz for MCU one 125MHz for FPGA.
I've took it down from the board, and changed MCU to use internal RC
oscillator for MCU and PLL to mutilply refclk to 200MHz for FPGA.
  I will try do the same test tonight thanks.


2014-12-29 4:35 GMT+08:00 Bob Camp kb...@n1k.org:

 Hi


  On Dec 28, 2014, at 9:19 AM, Li Ang lll...@gmail.com wrote:
 
  Hi Bob,
I did some test according to your suggestions. DUT is a symmetricom x72
  rb oscillator. Also, I've tried signal generator as the DUT. RS SMY01 is
  not as good as HP8662A but that the best I've got. The signal geneator is
  also using FE5650 as ref clock.
 
According to my test with the TDC today, this unit is not producing
 very
  stable data.
I don't have accurate pulse generator, so this is how I test the TDC:
  0) power the board with battery.
  1) use FPGA to generate time pulse:
  reg [15:0] shift;
  always @(posedge refclk10M) begin
  shift = {shift[14:0], sw_gate};
  end
  assign tdc_start = shift[3];
  assign tdc_stop1 = shift[5];
 
  2) use MCU to pull down sw_gate, the FPGA sync it to refclk10M domain and
  generate input signal for TDC.
 
  3) use TDC to test the time betwen tdc_start and tdc_stop1
 
  The result is in tdc_test.zip. number * 100ns = time between tdc_start
 and
  tdc_stop1. (TDC highspeed clock is refclk10M/2).
 
  There 2 issues from the test:
  1) As we can see from the data, the number is around 1.98x not 2.00x. So
  there is about 2ns delay between tdc_start and tdc_stop1 for this simple
  test code. If it is from the PCB trace and something inside FPGA, this
 part
  should be a constant value at certain temperature.

 So far all correct. If you are using Quartus, you can fire up the timing
 analyzer and take a look at what it guesses for timing / delay on the
 pulse. It is not a perfect number, but I’d bet it will confirm that the 2
 ns does come from the FPGA.

  I can calculate it by
  measuring 2 cycles and 3 cylces. My current code has not implement this
  part, it should provide some improvement. 2ns time error for 1s gate,
 that
  is something.

 The delay probably is from the input / output fabric on the FPGA ( =
 output driver). The test you propose should demonstrate this.

  2) For a 90ps TDC, I think the result should be something like +-0.001
  cycle. But I get something like +-0.003 cycle. I do not know the reason
 for
  now.

 Two reasonable *guesses* would be crosstalk and noise.

 1)  If there are any other clocks running around during this test, I’d see
 if they can be shut down. Things like an free running OCXO are good for
 this - they are easy to isolate.

 2) Noise could be internal to the TDC. If it’s 90 ns at one sigma, then
 you will indeed see +’/- 3 X that (or more) depending on how long you watch
 it. At least by my math the one sigma on the data is 149 ps. That’s a bit
 over 90 ps, but not terribly far.

 Delaying the signals relative to each other (clock and output) as Magnus
 suggests in another post is probably a real good idea for sorting some of
 this out.

 Bob

 
 
 
 
  2014-12-27 22:58 GMT+08:00 Bob Camp kb...@n1k.org:
 
  Hi
 
  (In reply to several posts. It’s easier for me this way)
 
  Ok, that’s good news !!! (and useful data)
 
  Your counter performance degraded a bit when you put in 5 db and not
 much
  when you put in 8 db.
 
  It’s also maybe *too* good news. I suspect that cross talk between the
  channels may be impacting your results.
 
  Next step is to try it with two independent sources and a bit more
  attenuation. When you try it with two sources, you need to attenuate
 first
  one source and then switch the attenuators to the other source. That
 will
  help you see if crosstalk from one channel is more of a problem than
 from
  the other channel.
 
  One parts hint:
 
  Cable TV attenuators are much cheaper than their fancy 50 ohm
 MIniCircuits
  cousins. They are also something you can pick up down at the corner
  electronics store. For this sort of testing they are perfectly fine to
 use.
  At this point in the testing the mismatch between 75 ohms and 50 ohms is
  not a big deal. You will need to adapt connectors, but you probably
 still
  will save money.
 
  ===
 
  Op-amps that have enough bandwidth and performance for a high input
  impedance counter input are rare items. They also are not cheap. Often
 they
  come as some sort of current feedback part with low(er) input
 impedance. If
  you want your counter to work to 300 MHz, it should accept a 300 MHz
 square
  wave. That might mean passing the third or even the fifth harmonic of
 the
  square wave. An input channel with 900 or 1500 MHz bandwidth is quite a
  challenge.
 
  One very simple solution is to just grab a high speed comparator like
 the
  one used by Fluke / Pendulum (ADCMP565). Drive it directly with your
 input
  or clock. Make it your front end device. That’s not an ideal solution,
 but
  it will give you the bandwidth and a reasonable

Re: [time-nuts] schematics of frequency counter

[Li Ang]

hi Neil,
  TPS79333 is quite cheap and adm7150 is 60 times the price of it. These 2
ldo has different package, it not easy to replace it directly. I have tried
power the system with 18650 battery, the performace is almost the same with
5v from laptop USB port. So I think psrr might not be a issue.
 If the noise generated by LDO is the problem, can I filter it out by
puting more caps?

Neil Schroeder gign...@gmail.com于2015年1月3日星期六写道：
 I would reconsider the LDOs while you have some time to play with them.
 The TPS79333DBVR is not even remotely ultralow noise at most offsets,
 despite what TI may say.

 For 5V5 and under up to about 600ma, I would suggest you take a look at
the
 ADM7155 (adjustable) or ADM7154 (fixed). If you need 800ma, the 7150 is
 here for you.


http://www.analog.com/en/power-management/linear-regulators/adm7155/products/product.html

http://www.analog.com/en/power-management/linear-regulators/adm7150/products/product.html

 The TI part has nearly 35 uVRMS of noise  at just 2.8a with not very good
 PSRR.  The 7155 will produce less than  1.0 μVRMS Total Integrated Noise
 from 100 Hz to 100 KHz and 1.6 from 10 to 100 KHz,and that's without an RC
 noise compensation network.  Its a fabulous part for a sensitive
 application like yours.

 I'm hoping I am right in assuming that the noise performance of the LDOs
is
 a concern, and don't mean to even dare suggest that you've done anything
 but a great job! :-)

 NS

 On Sat, Dec 27, 2014 at 5:34 AM, Li Ang lll...@gmail.com wrote:

 Hi Charles,
In my circuit, the VCC is 5v. I've noticed my bias and emitter
resistor
 is something need to be changed. I will play with the resistors and see
if
 it improves. Thanks.

 2014-12-27 6:42 GMT+08:00 Charles Steinmetz csteinm...@yandex.com:

  Li Ang wrote:
 
   RF pnp transistor is harder to get. I would like the front end works
  at 300MHz.
 
  My questions:
  1) why the difference of DC bias of the 2 NPN matters?  I thought only
 the
  frequency part is useful to a counter, amplitude information is
useless
  right?
 
 
  You want the circuit to switch near the mid-point of the input sine
wave,
  and at exactly the same place every time.  How you bias the transistors
  determines how well this is accomplished.
 
  You also want the output to switch fast and cleanly between a low
voltage
  very near 0v (ground) to a high voltage very near 3v (Vcc, logic
high).
  An NPN cannot do that, biased the way that you have them connected (the
  emitter of the output transistor Q301 can only pull the output down to
a
  little less than 1v due to R315, which may sort of work but is not a
 proper
  way to run 3v logic).  This operation also saturates Q301, which is bad
 for
  performance.  See simulated results below.
 
  In order for an NPN to provide a useful output for 3v logic, (i) its
  emitter must be grounded, and (ii) it must either be run into
saturation
 or
  use a Baker clamp.  Running the transistor into saturation must be
 avoided,
  particularly if you want to reach 300MHz, and a Baker clamp raises the
  logic low output voltage to 0.5v (not a good thing with 3v logic).
 So,
  it is very much better to use a PNP differential pair.  For a 300MHz
  circuit, I would use BFT93 (and even that barely gets you to 300MHz).
 
   2) what's is the C4 in your circuit for?
 
 
  C4 makes Q1 and Q2 a differential (emitter-coupled) pair at RF
  frequencies, but not at DC.  So, the circuit has no gain at DC and
  therefore the DC errors between Q1 and Q2 cause much less output error
 than
  they would if the emitters were connected directly together.
 
   3) If the noise is more important than the gain, what kind of
transistor
  should I choose? The Ft near 300MHz ones(BFS17, 2SC9018) or Ft far
 beyond
  300MHz ones(BFP420, BFP183,BFR93) ?
 
 
  Far beyond.  The Ft is the frequency where a transistor completely runs
  out of gain.  You want to operate at a much lower frequency where the
  transistor still has substantial gain, particularly with fast RF
  transistors, which generally have much lower DC hfe than
general-purpose
  transistors like 3904 and 3906.  Note that the simulation of the
circuit
  you published (simulated results below) barely works at even 20MHz.
As I
  noted above, even the BFT93 barely gets you to 300MHz with a 1Vrms
input.
 
  Best regards,
 
  Charles
 
 
  ___
  time-nuts mailing list -- time-nuts@febo.com
  To unsubscribe, go to
  https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
  and follow the instructions there.
 
 ___
 time-nuts mailing list -- time-nuts@febo.com
 To unsubscribe, go to
 https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
 and follow the instructions there.

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 To unsubscribe, go to
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 and follow the instructions

Re: [time-nuts] schematics of frequency counter

[Li Ang]

Hi Magnus

   Thanks for the detailed information.
btw,  I've found an easier way to get histogram :   sort tdc_test.txt |
uniq -c




2014-12-31 23:37 GMT+08:00 Magnus Danielson mag...@rubidium.dyndns.org:

 Hi,

 First I did a statistical histogram simply by counting how many times a
 particular delay measure occurred, thus creating bins of occurrence count
 for each value. I did this by doing

 grep 1.987 tdc_test.txt | wc -l
 648

 So, the 1.987 bin has a count of 648.
 I sent you the full histogram in the first reply.

 Then, I calculated the average delay by multiply each delay with the count
 of that delay, and then add these products to a sum, and divide by the
 total count (5100).

 Using this average, I then subtract that for the measure of each bin, thus
 getting the distance from the average. This difference is then squared, and
 multiplied with the count for it's bin-count. Again this is being summed,
 divided by the total count minus 1 (5099) to produce the variance, and
 square root produces the standard deviation.

 So far, it relative simple operations.

 These operations could be done directly on the sample-set, but the
 histogram is also good in that you can now see if it is unbalanced.

 One analysis you can do is to analyse how well the histogram matches up
 the expected Gaussian distribution bell for the noise you have. This can be
 done in several ways, but for a coarse set of bins like this, I think the
 best is to generate a matching Gaussian bin count from the bin positions,
 average and deviation. The difference with the actual bin count will then
 illustrate any major deviations. The trained eye will see deviation in the
 histogram anyway. However, to do this requires the erfc.

 Hope this have shown you enough of the magic. But to assist you further,
 please find a spread-sheet of it attached.

 Notice that I scaled the values by 100 ns before further processing.

 Cheers,
 Magnus


 On 12/31/2014 01:03 PM, Li Ang wrote:

 Hi Magnus,
 I'm not familar with error analysis and statistics, can you tell me
 how
 to calculate the jitter with my data? Can you tell me some articles or
 tutorials about the calculation that a time-nut usually use?  I want to
 learn stuffs. :)

 Thanks.

 2014-12-29 21:58 GMT+08:00 Magnus Danielson mag...@rubidium.dyndns.org:

  Hi,

 Darn, not reading all the notes. Again.

 Well, in that case, scaling should be done... then you get average of
 198,5075 ns and 149,8 ps RMS jitter, with 1,1 ns peak-to-peak.

 The jitter is okish then, but a little better would indeed be nice.

 Cheers,
 Magnus


 On 12/29/2014 01:55 PM, Li Ang wrote:

  Hi Magnus,
  The unit of these data is not ns but reference clock cycles
 (100ns).
 TDC_GP22 measures the time between the edge of tdc_start and
 tdc_stop1, then it measures the reference clock automaticly. The result
 you
 get from it is the ratio of them.

 2014-12-29 19:58 GMT+08:00 Magnus Danielson mag...@rubidium.dyndns.org
 :

   Hi,


 Some quick statistic-processing.

 Histogram of your data:
 1.979 0
 1.980 2
 1.98146
 1.982   173
 1.983   523
 1.984  1031
 1.985  1301
 1.986  1131
 1.987   648
 1.988   236
 1.989 8
 1.990 1
 1.991 0

 The total sample count is 5100 (wc -l only gives 5099 since there is a
 missing end of line, but word count is 5100).

 The average is about 1,985075 ns and it is reasonably gaussian, but
 with
 some systematics, notice how the slope is more abrupt on the higher end
 than the lower end. A quick and dirty spreadsheet gives me about 2,243
 ps
 RMS jitter, which isn't all that bad. Yes, it will spread out to that
 11
 ps
 peak-to-peak jitter, but it is to be expected.

 It's pretty respectable for a home-built.

 Cheers,
 Magnus


 On 12/28/2014 03:19 PM, Li Ang wrote:

   Hi Bob,

   I did some test according to your suggestions. DUT is a
 symmetricom
 x72
 rb oscillator. Also, I've tried signal generator as the DUT. RS SMY01
 is
 not as good as HP8662A but that the best I've got. The signal geneator
 is
 also using FE5650 as ref clock.

   According to my test with the TDC today, this unit is not
 producing
 very
 stable data.
   I don't have accurate pulse generator, so this is how I test the
 TDC:
 0) power the board with battery.
 1) use FPGA to generate time pulse:
 reg [15:0] shift;
 always @(posedge refclk10M) begin
 shift = {shift[14:0], sw_gate};
 end
 assign tdc_start = shift[3];
 assign tdc_stop1 = shift[5];

 2) use MCU to pull down sw_gate, the FPGA sync it to refclk10M domain
 and
 generate input signal for TDC.

 3) use TDC to test the time betwen tdc_start and tdc_stop1

 The result is in tdc_test.zip. number * 100ns = time between tdc_start
 and
 tdc_stop1. (TDC highspeed clock is refclk10M/2).

 There 2 issues from the test:
 1) As we can see from the data, the number is around 1.98x not 2.00x.
 So
 there is about 2ns delay between tdc_start and tdc_stop1 for this
 simple
 test code. If it is from the PCB trace

Re: [time-nuts] schematics of frequency counter

[Li Ang]

Hi Magnus,
   I'm not familar with error analysis and statistics, can you tell me how
to calculate the jitter with my data? Can you tell me some articles or
tutorials about the calculation that a time-nut usually use?  I want to
learn stuffs. :)

Thanks.

2014-12-29 21:58 GMT+08:00 Magnus Danielson mag...@rubidium.dyndns.org:

 Hi,

 Darn, not reading all the notes. Again.

 Well, in that case, scaling should be done... then you get average of
 198,5075 ns and 149,8 ps RMS jitter, with 1,1 ns peak-to-peak.

 The jitter is okish then, but a little better would indeed be nice.

 Cheers,
 Magnus


 On 12/29/2014 01:55 PM, Li Ang wrote:

 Hi Magnus,
 The unit of these data is not ns but reference clock cycles (100ns).
 TDC_GP22 measures the time between the edge of tdc_start and
 tdc_stop1, then it measures the reference clock automaticly. The result
 you
 get from it is the ratio of them.

 2014-12-29 19:58 GMT+08:00 Magnus Danielson mag...@rubidium.dyndns.org:

  Hi,

 Some quick statistic-processing.

 Histogram of your data:
 1.979 0
 1.980 2
 1.98146
 1.982   173
 1.983   523
 1.984  1031
 1.985  1301
 1.986  1131
 1.987   648
 1.988   236
 1.989 8
 1.990 1
 1.991 0

 The total sample count is 5100 (wc -l only gives 5099 since there is a
 missing end of line, but word count is 5100).

 The average is about 1,985075 ns and it is reasonably gaussian, but with
 some systematics, notice how the slope is more abrupt on the higher end
 than the lower end. A quick and dirty spreadsheet gives me about 2,243 ps
 RMS jitter, which isn't all that bad. Yes, it will spread out to that 11
 ps
 peak-to-peak jitter, but it is to be expected.

 It's pretty respectable for a home-built.

 Cheers,
 Magnus


 On 12/28/2014 03:19 PM, Li Ang wrote:

  Hi Bob,
  I did some test according to your suggestions. DUT is a symmetricom
 x72
 rb oscillator. Also, I've tried signal generator as the DUT. RS SMY01
 is
 not as good as HP8662A but that the best I've got. The signal geneator
 is
 also using FE5650 as ref clock.

  According to my test with the TDC today, this unit is not producing
 very
 stable data.
  I don't have accurate pulse generator, so this is how I test the
 TDC:
 0) power the board with battery.
 1) use FPGA to generate time pulse:
 reg [15:0] shift;
 always @(posedge refclk10M) begin
 shift = {shift[14:0], sw_gate};
 end
 assign tdc_start = shift[3];
 assign tdc_stop1 = shift[5];

 2) use MCU to pull down sw_gate, the FPGA sync it to refclk10M domain
 and
 generate input signal for TDC.

 3) use TDC to test the time betwen tdc_start and tdc_stop1

 The result is in tdc_test.zip. number * 100ns = time between tdc_start
 and
 tdc_stop1. (TDC highspeed clock is refclk10M/2).

 There 2 issues from the test:
 1) As we can see from the data, the number is around 1.98x not 2.00x. So
 there is about 2ns delay between tdc_start and tdc_stop1 for this simple
 test code. If it is from the PCB trace and something inside FPGA, this
 part
 should be a constant value at certain temperature. I can calculate it by
 measuring 2 cycles and 3 cylces. My current code has not implement this
 part, it should provide some improvement. 2ns time error for 1s gate,
 that
 is something.
 2) For a 90ps TDC, I think the result should be something like +-0.001
 cycle. But I get something like +-0.003 cycle. I do not know the reason
 for
 now.





 2014-12-27 22:58 GMT+08:00 Bob Camp kb...@n1k.org:

   Hi


 (In reply to several posts. It’s easier for me this way)

 Ok, that’s good news !!! (and useful data)

 Your counter performance degraded a bit when you put in 5 db and not
 much
 when you put in 8 db.

 It’s also maybe *too* good news. I suspect that cross talk between the
 channels may be impacting your results.

 Next step is to try it with two independent sources and a bit more
 attenuation. When you try it with two sources, you need to attenuate
 first
 one source and then switch the attenuators to the other source. That
 will
 help you see if crosstalk from one channel is more of a problem than
 from
 the other channel.

 One parts hint:

 Cable TV attenuators are much cheaper than their fancy 50 ohm
 MIniCircuits
 cousins. They are also something you can pick up down at the corner
 electronics store. For this sort of testing they are perfectly fine to
 use.
 At this point in the testing the mismatch between 75 ohms and 50 ohms
 is
 not a big deal. You will need to adapt connectors, but you probably
 still
 will save money.

 ===

 Op-amps that have enough bandwidth and performance for a high input
 impedance counter input are rare items. They also are not cheap. Often
 they
 come as some sort of current feedback part with low(er) input
 impedance.
 If
 you want your counter to work to 300 MHz, it should accept a 300 MHz
 square
 wave. That might mean passing the third or even the fifth harmonic of
 the
 square wave. An input channel with 900 or 1500 MHz bandwidth is quite a
 challenge

Re: [time-nuts] New GPSDO on EBAY From China

[Li Ang]

Hi
 One of my friend had one. Here is the test result from him.



Bob Camp kb...@n1k.org于2014年12月29日星期一写道：
 Hi

 Ok, well that’s a move forward on this GPSDO. There is a *lot* more data
on that listing than there was a month ago.

 Thanks for digging it up  and posting the link.

 If you look at the ADEV at 1 second, it’s running at 2.67 x10^-11. That’s
all coming from the Erratum Rb that they are using as a reference. At 100
seconds the Rb should be around 2.67 x10^-12 and the MV-89 should be about
 2x10^-11. They combine as the square root, so that would be 3.3 ppt or
less. The unit is running at 4.8 ppt so the filter is having some impact at
that point.

 Out around 5,000 seconds the unit has a major hump. The Nortel GPSTM has
a similar hump, but much closer in. It’s performance at 5K seconds is much
better. The Lucent KS boxes beat this part across the entire range. That
makes some assumptions, since there is no good ADEV data inside 100 seconds
on the plot.

 The final question about the plot would be - what happens at longer tau?
The run was stopped before it really got past the peak in the filter. It
would be nice to see some data that at least gets back down to  1 ppt at
the longer tau’s. Without that data it’s unclear how well the whole system
is doing. That’s not to say it’s not doing well. It could be doing a great
job, there’s just no way to know from the data.

 

 My guess is that this is very much like your counter project, just a bit
further along. They have a nice looking unit, but are still trying to
figure out the bugs and finish up the software …

 Bob

 On Dec 28, 2014, at 6:19 PM, Li Ang lll...@gmail.com wrote:

 Hi
   This unit is done by BG7TBL. In his store on taobao.com, there is a
adev
 chart. Please refrer to this link

http://item.taobao.com/item.htm?spm=a1z10.3.w4002-1278071728.49.XHJlQLid=42336500072




 2014-12-29 1:56 GMT+08:00 Dan Rae dan...@verizon.net:

 On 12/28/2014 7:25 AM, David Smith wrote:

 Hello Friends,
 I found this new inexpensive GPSDO on ebay listed from a seller from
 China:

 Dave, these have been discussed in the past at some length on this list.
 I would point out that they use a re-cycled Morion OCXO.  I have had
two of
 these ovens from China; one worked fine, the other has a very high
level of
 spurious outputs.  I would be wary of using these in anything without
first
 testing them thoroughly.

 Dan

 ___
 time-nuts mailing list -- time-nuts@febo.com
 To unsubscribe, go to https://www.febo.com/cgi-bin/
 mailman/listinfo/time-nuts
 and follow the instructions there.

 ___
 time-nuts mailing list -- time-nuts@febo.com
 To unsubscribe, go to
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 and follow the instructions there.

 ___
 time-nuts mailing list -- time-nuts@febo.com
 To unsubscribe, go to
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 and follow the instructions there.

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To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Re: [time-nuts] schematics of frequency counter

[Li Ang]

Hi Magnus,
   The unit of these data is not ns but reference clock cycles (100ns).
TDC_GP22 measures the time between the edge of tdc_start and
tdc_stop1, then it measures the reference clock automaticly. The result you
get from it is the ratio of them.

2014-12-29 19:58 GMT+08:00 Magnus Danielson mag...@rubidium.dyndns.org:

 Hi,

 Some quick statistic-processing.

 Histogram of your data:
 1.979 0
 1.980 2
 1.98146
 1.982   173
 1.983   523
 1.984  1031
 1.985  1301
 1.986  1131
 1.987   648
 1.988   236
 1.989 8
 1.990 1
 1.991 0

 The total sample count is 5100 (wc -l only gives 5099 since there is a
 missing end of line, but word count is 5100).

 The average is about 1,985075 ns and it is reasonably gaussian, but with
 some systematics, notice how the slope is more abrupt on the higher end
 than the lower end. A quick and dirty spreadsheet gives me about 2,243 ps
 RMS jitter, which isn't all that bad. Yes, it will spread out to that 11 ps
 peak-to-peak jitter, but it is to be expected.

 It's pretty respectable for a home-built.

 Cheers,
 Magnus


 On 12/28/2014 03:19 PM, Li Ang wrote:

 Hi Bob,
 I did some test according to your suggestions. DUT is a symmetricom
 x72
 rb oscillator. Also, I've tried signal generator as the DUT. RS SMY01 is
 not as good as HP8662A but that the best I've got. The signal geneator is
 also using FE5650 as ref clock.

 According to my test with the TDC today, this unit is not producing
 very
 stable data.
 I don't have accurate pulse generator, so this is how I test the TDC:
 0) power the board with battery.
 1) use FPGA to generate time pulse:
 reg [15:0] shift;
 always @(posedge refclk10M) begin
 shift = {shift[14:0], sw_gate};
 end
 assign tdc_start = shift[3];
 assign tdc_stop1 = shift[5];

 2) use MCU to pull down sw_gate, the FPGA sync it to refclk10M domain and
 generate input signal for TDC.

 3) use TDC to test the time betwen tdc_start and tdc_stop1

 The result is in tdc_test.zip. number * 100ns = time between tdc_start and
 tdc_stop1. (TDC highspeed clock is refclk10M/2).

 There 2 issues from the test:
 1) As we can see from the data, the number is around 1.98x not 2.00x. So
 there is about 2ns delay between tdc_start and tdc_stop1 for this simple
 test code. If it is from the PCB trace and something inside FPGA, this
 part
 should be a constant value at certain temperature. I can calculate it by
 measuring 2 cycles and 3 cylces. My current code has not implement this
 part, it should provide some improvement. 2ns time error for 1s gate, that
 is something.
 2) For a 90ps TDC, I think the result should be something like +-0.001
 cycle. But I get something like +-0.003 cycle. I do not know the reason
 for
 now.





 2014-12-27 22:58 GMT+08:00 Bob Camp kb...@n1k.org:

  Hi

 (In reply to several posts. It’s easier for me this way)

 Ok, that’s good news !!! (and useful data)

 Your counter performance degraded a bit when you put in 5 db and not much
 when you put in 8 db.

 It’s also maybe *too* good news. I suspect that cross talk between the
 channels may be impacting your results.

 Next step is to try it with two independent sources and a bit more
 attenuation. When you try it with two sources, you need to attenuate
 first
 one source and then switch the attenuators to the other source. That will
 help you see if crosstalk from one channel is more of a problem than from
 the other channel.

 One parts hint:

 Cable TV attenuators are much cheaper than their fancy 50 ohm
 MIniCircuits
 cousins. They are also something you can pick up down at the corner
 electronics store. For this sort of testing they are perfectly fine to
 use.
 At this point in the testing the mismatch between 75 ohms and 50 ohms is
 not a big deal. You will need to adapt connectors, but you probably still
 will save money.

 ===

 Op-amps that have enough bandwidth and performance for a high input
 impedance counter input are rare items. They also are not cheap. Often
 they
 come as some sort of current feedback part with low(er) input impedance.
 If
 you want your counter to work to 300 MHz, it should accept a 300 MHz
 square
 wave. That might mean passing the third or even the fifth harmonic of the
 square wave. An input channel with 900 or 1500 MHz bandwidth is quite a
 challenge.

 One very simple solution is to just grab a high speed comparator like the
 one used by Fluke / Pendulum (ADCMP565). Drive it directly with your
 input
 or clock. Make it your front end device. That’s not an ideal solution,
 but
 it will give you the bandwidth and a reasonable input impedance. It
 requires messy things like a negative supply  or a “fake” ground (so
 would
 the op amp). It also has an ECL output that needs to be converted to
 match
 your FPGA ( hint: use the clock inputs, they are LVPECL compatible).
 Driving into the FPGA with a differential signal is probably needed to
 reduce crosstalk.

 No matter how you do it, input channels are *not* an easy

Re: [time-nuts] New GPSDO on EBAY From China

[Li Ang]

Hi
   This unit is done by BG7TBL. In his store on taobao.com, there is a adev
chart. Please refrer to this link
http://item.taobao.com/item.htm?spm=a1z10.3.w4002-1278071728.49.XHJlQLid=42336500072




2014-12-29 1:56 GMT+08:00 Dan Rae dan...@verizon.net:

 On 12/28/2014 7:25 AM, David Smith wrote:

 Hello Friends,
 I found this new inexpensive GPSDO on ebay listed from a seller from
 China:

 Dave, these have been discussed in the past at some length on this list.
 I would point out that they use a re-cycled Morion OCXO.  I have had two of
 these ovens from China; one worked fine, the other has a very high level of
 spurious outputs.  I would be wary of using these in anything without first
 testing them thoroughly.

 Dan

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Re: [time-nuts] schematics of frequency counter

[Li Ang]

Hi  Bob,

   You are right. My analog circuit skill is so limited, I need to be
realistic.  I will make some modification to the circuit according to the
suggestions from you guys when new board is going to make. I've sent the
MV89A board to the factory and got 2 3db attenuators from minicircuit.

   However, I'm still wondering why SRS/Agilent/Fluke dont use high speed
opamp(something like LMH6624). They all choose jfet + opamp to convert the
impedance.


2014-12-26 22:12 GMT+08:00 Bob Camp kb...@n1k.org:

 Hi

 Don’t go to crazy on the front end. You can spend a year optimizing
 something like this. The objective is to see if the front end is a big
 problem now.  It’s very easy to get to many things going on in a project.
 That makes it hard to complete.

 All front end circuits will work better with worse with a 1 mV input than
 with a larger input signal. Some very common circuits have odd things
 (frequency doubling…) that happen as the input drops. Chains with a lot of
 gain can oscillate with certain combinations of input level and source
 impedance.

 Some decisions you will eventually need to make:

 Do you need a high input impedance counter input?

 Most commercial counters have a = 1 mega ohm input impedance capability.
 This lets you put an oscilloscope probe on the counter. It’s nice for
 probing around in a circuit. I have rarely used this feature. It’s *much*
 more convenient to take the output of the oscilloscope and feed it into the
 counter. That way the probe stays on the scope and you can *see* the signal
 you are probing as well as count it.

 Do you need to deal with low frequency signals?

 Things like pulse per second inputs are a TimeNut thing to look at. Most
 of the world does not try to count 1 Hz. Timing signals tend to be DC
 coupled. They often have odd duty cycles even if they are not low
 frequency. A DC coupled input channel implies a range of adjustable trigger
 levels. This can get very crazy very fast. A simple TTL compatible input
 that triggers at ~ 1 V and will accept 2 to 5V logic signals is an easy way
 to go. Is that enough?

 

 Some decisions that commercial counter people get to make:

 Do you need to deal with low level RF signals?

 Do you need to deal with modulated RF signals?

 Do you need to deal with microwave signals?

 Do you need adjustable front end filtering to reject RF on your signals?

 Do you need to tolerate 250V AC or 1KV DC on the counter input?

 

 For now I’d think about the second set of decisions, but not worry about
 them. Even the two decisions in the first group are not all that important
 to make right now. They all have many sub decisions associated with them.
 One example is adding a negative power supply to allow a DC trigger at zero
 volts.

 A very common solution: Build the counter with just logic level inputs.
 Keep things on the main board simple and easy to work with. Run that board
 with it’s own regulators. Get it running with 3.3V signals. Once that is
 done, build the input channel(s) on their own board(s). They will need
 their own regulators to keep noise down (regulators are cheap). You can
 optimize the input channel circuits as part of a separate project.

 Bob




  On Dec 26, 2014, at 8:21 AM, Li Ang lll...@gmail.com wrote:
 
  Hi
 Thanks for the suggestion. I will do some experiments with the front
  end :)
 
  2014-12-25 4:32 GMT+08:00 Bob Camp kb...@n1k.org:
 
  Hi
 
  Very interesting !! Thanks for sharing.
 
  As you can see from the Fluke schematics, the input amplifiers on
 counters
  can get quite complex. I would definitely recommend playing a bit with
 the
  input channels on your board. Here’s what I would do, there are many
 other
  approaches:
 
  1) Set up a high speed CMOS biased gate limiter with an OCXO. Quick
  approach is two 10K ohm resistors for bias (one to B+ one to ground), AC
  couple the sine wave into the junction. Junction also goes to the gate
  input.
 
  2) Assume that the signal is good. (it may not be).
 
  3) Compare the CMOS signal on one channel to your input amplifier on the
  other channel.
 
  4) Attenuate the signal to the input amplifier and see what happens.
 
  Again, there are *lots* of different ways to do the same sort of thing.
 I
  would not go overboard doing this with complicated circuits. You simply
  want a way to figure out what the input circuits are doing.
 
  Have Fun!
 
  Bob
 
 
  On Dec 24, 2014, at 11:19 AM, Li Ang lll...@gmail.com wrote:
 
  http://www.qsl.net/bi7lnq/freqcnt_bi7lnq_v4.pdf  this is my current
  board.
  I'm not a hardware guy, feel free to correct my mistakes. :)
 
 
  http://assets.fluke.com/manuals/6690smeng.pdf schematic of
 cnt90
  aka pm6690
 
 
  Happy holidays
 
 
  Li Ang
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Re: [time-nuts] schematics of frequency counter

[Li Ang]

Hi Charles,
   In my circuit, the VCC is 5v. I've noticed my bias and emitter resistor
is something need to be changed. I will play with the resistors and see if
it improves. Thanks.

2014-12-27 6:42 GMT+08:00 Charles Steinmetz csteinm...@yandex.com:

 Li Ang wrote:

  RF pnp transistor is harder to get. I would like the front end works
 at 300MHz.

 My questions:
 1) why the difference of DC bias of the 2 NPN matters?  I thought only the
 frequency part is useful to a counter, amplitude information is useless
 right?


 You want the circuit to switch near the mid-point of the input sine wave,
 and at exactly the same place every time.  How you bias the transistors
 determines how well this is accomplished.

 You also want the output to switch fast and cleanly between a low voltage
 very near 0v (ground) to a high voltage very near 3v (Vcc, logic high).
 An NPN cannot do that, biased the way that you have them connected (the
 emitter of the output transistor Q301 can only pull the output down to a
 little less than 1v due to R315, which may sort of work but is not a proper
 way to run 3v logic).  This operation also saturates Q301, which is bad for
 performance.  See simulated results below.

 In order for an NPN to provide a useful output for 3v logic, (i) its
 emitter must be grounded, and (ii) it must either be run into saturation or
 use a Baker clamp.  Running the transistor into saturation must be avoided,
 particularly if you want to reach 300MHz, and a Baker clamp raises the
 logic low output voltage to 0.5v (not a good thing with 3v logic).  So,
 it is very much better to use a PNP differential pair.  For a 300MHz
 circuit, I would use BFT93 (and even that barely gets you to 300MHz).

  2) what's is the C4 in your circuit for?


 C4 makes Q1 and Q2 a differential (emitter-coupled) pair at RF
 frequencies, but not at DC.  So, the circuit has no gain at DC and
 therefore the DC errors between Q1 and Q2 cause much less output error than
 they would if the emitters were connected directly together.

  3) If the noise is more important than the gain, what kind of transistor
 should I choose? The Ft near 300MHz ones(BFS17, 2SC9018) or Ft far beyond
 300MHz ones(BFP420, BFP183,BFR93) ?


 Far beyond.  The Ft is the frequency where a transistor completely runs
 out of gain.  You want to operate at a much lower frequency where the
 transistor still has substantial gain, particularly with fast RF
 transistors, which generally have much lower DC hfe than general-purpose
 transistors like 3904 and 3906.  Note that the simulation of the circuit
 you published (simulated results below) barely works at even 20MHz.  As I
 noted above, even the BFT93 barely gets you to 300MHz with a 1Vrms input.

 Best regards,

 Charles


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Re: [time-nuts] schematics of frequency counter

[Li Ang]

Hi Bob,
  Here is the data and test scheme.
  It does not show much difference.

2014-12-26 22:12 GMT+08:00 Bob Camp kb...@n1k.org:

 Hi

 Don’t go to crazy on the front end. You can spend a year optimizing
 something like this. The objective is to see if the front end is a big
 problem now.  It’s very easy to get to many things going on in a project.
 That makes it hard to complete.

 All front end circuits will work better with worse with a 1 mV input than
 with a larger input signal. Some very common circuits have odd things
 (frequency doubling…) that happen as the input drops. Chains with a lot of
 gain can oscillate with certain combinations of input level and source
 impedance.

 Some decisions you will eventually need to make:

 Do you need a high input impedance counter input?

 Most commercial counters have a = 1 mega ohm input impedance capability.
 This lets you put an oscilloscope probe on the counter. It’s nice for
 probing around in a circuit. I have rarely used this feature. It’s *much*
 more convenient to take the output of the oscilloscope and feed it into the
 counter. That way the probe stays on the scope and you can *see* the signal
 you are probing as well as count it.

 Do you need to deal with low frequency signals?

 Things like pulse per second inputs are a TimeNut thing to look at. Most
 of the world does not try to count 1 Hz. Timing signals tend to be DC
 coupled. They often have odd duty cycles even if they are not low
 frequency. A DC coupled input channel implies a range of adjustable trigger
 levels. This can get very crazy very fast. A simple TTL compatible input
 that triggers at ~ 1 V and will accept 2 to 5V logic signals is an easy way
 to go. Is that enough?

 

 Some decisions that commercial counter people get to make:

 Do you need to deal with low level RF signals?

 Do you need to deal with modulated RF signals?

 Do you need to deal with microwave signals?

 Do you need adjustable front end filtering to reject RF on your signals?

 Do you need to tolerate 250V AC or 1KV DC on the counter input?

 

 For now I’d think about the second set of decisions, but not worry about
 them. Even the two decisions in the first group are not all that important
 to make right now. They all have many sub decisions associated with them.
 One example is adding a negative power supply to allow a DC trigger at zero
 volts.

 A very common solution: Build the counter with just logic level inputs.
 Keep things on the main board simple and easy to work with. Run that board
 with it’s own regulators. Get it running with 3.3V signals. Once that is
 done, build the input channel(s) on their own board(s). They will need
 their own regulators to keep noise down (regulators are cheap). You can
 optimize the input channel circuits as part of a separate project.

 Bob




  On Dec 26, 2014, at 8:21 AM, Li Ang lll...@gmail.com wrote:
 
  Hi
 Thanks for the suggestion. I will do some experiments with the front
  end :)
 
  2014-12-25 4:32 GMT+08:00 Bob Camp kb...@n1k.org:
 
  Hi
 
  Very interesting !! Thanks for sharing.
 
  As you can see from the Fluke schematics, the input amplifiers on
 counters
  can get quite complex. I would definitely recommend playing a bit with
 the
  input channels on your board. Here’s what I would do, there are many
 other
  approaches:
 
  1) Set up a high speed CMOS biased gate limiter with an OCXO. Quick
  approach is two 10K ohm resistors for bias (one to B+ one to ground), AC
  couple the sine wave into the junction. Junction also goes to the gate
  input.
 
  2) Assume that the signal is good. (it may not be).
 
  3) Compare the CMOS signal on one channel to your input amplifier on the
  other channel.
 
  4) Attenuate the signal to the input amplifier and see what happens.
 
  Again, there are *lots* of different ways to do the same sort of thing.
 I
  would not go overboard doing this with complicated circuits. You simply
  want a way to figure out what the input circuits are doing.
 
  Have Fun!
 
  Bob
 
 
  On Dec 24, 2014, at 11:19 AM, Li Ang lll...@gmail.com wrote:
 
  http://www.qsl.net/bi7lnq/freqcnt_bi7lnq_v4.pdf  this is my current
  board.
  I'm not a hardware guy, feel free to correct my mistakes. :)
 
 
  http://assets.fluke.com/manuals/6690smeng.pdf schematic of
 cnt90
  aka pm6690
 
 
  Happy holidays
 
 
  Li Ang
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Re: [time-nuts] schematics of frequency counter

[Li Ang]

Hi
Thanks for the suggestion. I will do some experiments with the front
end :)

2014-12-25 4:32 GMT+08:00 Bob Camp kb...@n1k.org:

 Hi

 Very interesting !! Thanks for sharing.

 As you can see from the Fluke schematics, the input amplifiers on counters
 can get quite complex. I would definitely recommend playing a bit with the
 input channels on your board. Here’s what I would do, there are many other
 approaches:

 1) Set up a high speed CMOS biased gate limiter with an OCXO. Quick
 approach is two 10K ohm resistors for bias (one to B+ one to ground), AC
 couple the sine wave into the junction. Junction also goes to the gate
 input.

 2) Assume that the signal is good. (it may not be).

 3) Compare the CMOS signal on one channel to your input amplifier on the
 other channel.

 4) Attenuate the signal to the input amplifier and see what happens.

 Again, there are *lots* of different ways to do the same sort of thing. I
 would not go overboard doing this with complicated circuits. You simply
 want a way to figure out what the input circuits are doing.

 Have Fun!

 Bob


  On Dec 24, 2014, at 11:19 AM, Li Ang lll...@gmail.com wrote:
 
  http://www.qsl.net/bi7lnq/freqcnt_bi7lnq_v4.pdf  this is my current
 board.
  I'm not a hardware guy, feel free to correct my mistakes. :)
 
 
  http://assets.fluke.com/manuals/6690smeng.pdf schematic of cnt90
  aka pm6690
 
 
  Happy holidays
 
 
  Li Ang
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Re: [time-nuts] schematics of frequency counter

[Li Ang]

Hi Charles  Bruce


   I'm not good at analog circuits. My circuit is modified from wenzel's,
since RF pnp transistor is harder to get. I would like the front end works
at 300MHz.
My questions:
1) why the difference of DC bias of the 2 NPN matters?  I thought only the
frequency part is useful to a counter, amplitude information is useless
right?
2) what's is the C4 in your circuit for?
3) If the noise is more important than the gain, what kind of transistor
should I choose? The Ft near 300MHz ones(BFS17, 2SC9018) or Ft far beyond
300MHz ones(BFP420, BFP183,BFR93) ?

Thanks



2014-12-26 4:31 GMT+08:00 Charles Steinmetz csteinm...@yandex.com:

 In reply to Li Ang, Bruce wrote:

  The CLK1 input circuit produces an output incompatible with the 3.3V CMOS
 device it drives.A pair of pnp transistors in an otherwise similar circuit
 is capable of producing a 3.3V CMOS compatible output signal.
 Using independent voltage dividers to bias the transistor bases is a bad
 idea in that resistor tolerances may lead to a dc input offset of several
 tens of millivolts even with 1% resistors,


 I agree with Bruce.  The circuit below avoids these problems.  It is
 generally known as a Wenzel squarer (after Charles Wenzel, who
 popularized it -- see http://www.wenzel.com/library/time-frequency-
 articles/waveform-conversion-part-i-sine-to-square/). I revised and
 simulated a circuit I use all the time for 5v output to produce a 3v
 output, but I did not build it, so some adjustment may be required.  All
 resistors should be metal film.  The 1uF capacitors should be X7R, and the
 100nF and 10nF capacitors should be NP0/C0G.  Design center for this
 circuit is a 10MHz input at 1Vrms (not shown is the 50 ohm input resistor
 that would terminate a 1Vrms, 50 ohm source).

 Note that the circuit needs some overhead voltage to bias the PNP
 devices, so a 5v power supply is shown.  Both this supply and the base
 reference supply need to be quieter than the precision you expect from the
 circuit.  The decoupling shown should be significantly better than required
 for your purposes here, but keep this in mind if you push on to
 significantly higher resolution.

 I don't know what the highest frequency you expect to count is.  The 3906s
 are as fast as the 3904s you are using, and are fine at 10MHz and even up
 toward 100MHz -- but at some point you would need faster transistors.  The
 MMBT5179 and BFT93 are two possibilities.  Note that these faster
 transistors also reduce the sloping of the top of the square wave output
 (which is due to capacitive feedthrough of the B-E junction of the input
 transistor).  With less current available from this feedthrough (due to
 lower junction capacitance), you will probably need to increase the output
 resistor (R6) to achieve a full 3v output level if you use faster
 transistors.  [Note -- the attached simulated scope traces show the output
 (Q2 collector) and reference (Q2 base).  You want to keep Q2 out of
 saturation, so the peak collector voltage needs to be no more positive than
 the base voltage, as shown.]

 Note also that the input capacitor and the emitter coupling capacitor
 limit the lowest frequency you can count.

 Finally, note that the circuit does not have a lot of gain, so the
 low-signal limit is higher than on most commercial counters.  A 0.2Vp-p
 input produces a 0-2.6v, mostly sinusoidal output.  By 1Vp-p input, it is
 nicely square.  I'd limit the input voltage to ~5Vp-p.  If you need better
 sensitivity, you can add a preamp.   (If this were to be used as a
 general-purpose counter, I'd design a limiting preamp for the input.)

 Best regards,

 Charles


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[time-nuts] schematics of frequency counter

[Li Ang]

http://www.qsl.net/bi7lnq/freqcnt_bi7lnq_v4.pdf  this is my current board.
I'm not a hardware guy, feel free to correct my mistakes. :)


http://assets.fluke.com/manuals/6690smeng.pdf schematic of cnt90
aka pm6690


Happy holidays


Li Ang
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[time-nuts] Homebrew frequency counter, new board test result

[Li Ang]

Hi
It's me again. I was debugging the new FPGA version board this week.
The attached file is the test result of this new board, and 2 tests of CPLD
version(2014/12/11) are also included. There are few things changed between
these 2 version:
1) CPLD - FPGA
2) XC6206 - TPS79333 for TDC power supply. Analog and digital part of TDC
use dedicated LDO.
3) 2 layer - 4 layer
4) add 74ALV2G14 since FPGA does not support schmitt input

A little bit better than before. :)



mistakes of current version:
1) the board is 1cm bigger than expected...
2) the themral pad of FPGA should be connected to ground

test instruments
1) HP6622A as power supply
2) FE5650 rb as reference
3) PRS10 rb as DUT



Li Ang
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Re: [time-nuts] Homebrew frequency counter, need help

[Li Ang]

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Re: [time-nuts] Fw: Homebrew frequency counter, need help

[Li Ang]

Thanks Tom,

The front end is still 75ALS176, but I put another simple transistor
circuit from wenzel to to compare the performance.
http://www.wenzel.com/wp-content/uploads/diffsqr.gif



2014-12-12 17:04 GMT+08:00, Tom Van Baak t...@leapsecond.com:
 This large posting is from Li Ang.
 /tvb

 - Original Message -
 From: Li Ang
 To: Discussion of precise time and frequency measurement
 Sent: Thursday, December 11, 2014 7:37 AM
 Subject: Re: [time-nuts] Homebrew frequency counter, need help


 Hi Bob,
I've sent the PCB to the factory and I am waiting for the new board. This
 time, it's a 4-layer borad and changed from CPLD to FPGA. This is the first
 time of FPGA  4-layer project. Hope everthing be OK.
TPS79333 as the LDO for TDC. Better PSRR and noise spec than before
 (XC6206). Analog and digital parts have their dedicated LDO.


While I'm waiting the the new board. I did a test with PRS10  FE5650
 with current board. It's strange that the 20s adev of without linear
 regression is better than with linear regression.
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Re: [time-nuts] Homebrew frequency counter, need help

[Li Ang]

Hi Bob,
The job done by linear regression is to reduce the uncertainty. This
counter is designed to use continous timestamp method. My current design
can measure 9000 times/second. If I only use the 1st and last one to
calculate, it's the traditional recipocal + interploator method. This is
what you can see on the chart named without linear regression. The
uncertainty of slope(the frequency ratio of ref and signal ) is contributed
by these 2 measurements. With linear regression of all 9000 data within one
second, the uncertainty will reduced to smaller one. (I really can't
remember the ratio. Something like sqrt(9000)).


while(1) {
double t3;  //fraction part of refcnt, measured by tdc_gp22
double ref_curr;
uint32_t sig_curr;
static double ref_start;
static uint32_t sig_start;
uint32_t refcnt, sigcnt;
const uint32_t gate_time = 1000; // 1000ms gate time

if (i == 0) {
init_regression(rv);
cpld_rst();
timestamp(refcnt, sigcnt, t3);
ref_start = refcnt - t3;
sig_start = sigcnt;
i++;
continue;
}

timestamp(refcnt, sigcnt, t3);

regression_enter_data(rv, refcnt - t3 - ref_start, sigcnt - sig_start);
if (msecond  gate_time) {
i++;
continue;
} else  {
t = regression_slope(rv) ; // with linear regression
printf(\r\nFreq=%.*f, 14, t);
ref_curr = refcnt - t3;
sig_curr = sigcnt;

t = CalcFreq(ref_curr - ref_start, sig_curr -
sig_start); // without linear regression
printf( Interpolated=%.*f, 12, t);

msecond = 0;
  i = 0;
}
}

2014-12-12 21:18 GMT+08:00 Bob Camp kb...@n1k.org:

 HI

  On Dec 12, 2014, at 4:04 AM, Tom Van Baak t...@leapsecond.com wrote:
 
  This large posting is from Li Ang.
  /tvb
 
  - Original Message -
  From: Li Ang
  To: Discussion of precise time and frequency measurement
  Sent: Thursday, December 11, 2014 7:37 AM
  Subject: Re: [time-nuts] Homebrew frequency counter, need help
 
 
  Hi Bob,
I've sent the PCB to the factory and I am waiting for the new board.
 This time, it's a 4-layer borad and changed from CPLD to FPGA. This is the
 first time of FPGA  4-layer project. Hope everthing be OK.

 Very nice looking. I hope it works !!!

TPS79333 as the LDO for TDC. Better PSRR and noise spec than before
 (XC6206). Analog and digital parts have their dedicated LDO.
 
 
While I'm waiting the the new board. I did a test with PRS10  FE5650
 with current board. It's strange that the 20s adev of without linear
 regression is better than with linear regression”

 Be careful pre-processing ADEV data. There are a variety of statistical
 “traps” you can fall into. An overly simple explanation is that ADEV looks
 at noise and that most pre-processing is a filter. Filters take out noise.
 Finding one that only takes out the “bad noise” and keeps the “good noise”
 can be quite difficult.

 What exactly are you doing in your linear regression computation?

 Bob

 
 .bottom_layer.GIFpower_plane.GIFtop_layer.GIFadev.gif___
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Re: [time-nuts] Homebrew frequency counter, need help

[Li Ang]

Yes, you are right. 5650_5650 is sig=ref case. prs10_5650 is sig=prs10 and
ref=5650 case.

Since I really want to reduce the noise, what is the best test set you
suggest? All the frequency source I have: FE5650 Rb , PRS10 Rb , MV89a*2
OCXO, Thunderbolt GPSDO, 8663-XS*2 OCXO, Wenzel 100M OCXO(not sure).

How to analyze the ADEV plot to get information about noise?

Thanks


2014-12-13 0:31 GMT+08:00 Bob Camp kb...@n1k.org:

 Hi

 In your original data:

 Is the blue “5650 to 5650” trace looking at the same source for input and
 reference?

 Is the green “PRS10 to 5650” trace looking at two independent sources (one
 reference and the other as input)?

 I’m guessing that the answer is yes in both cases.

 Bob


  On Dec 12, 2014, at 10:40 AM, Li Ang lll...@gmail.com wrote:
 
  Hi Bob,
 The job done by linear regression is to reduce the uncertainty. This
  counter is designed to use continous timestamp method. My current design
  can measure 9000 times/second. If I only use the 1st and last one to
  calculate, it's the traditional recipocal + interploator method. This is
  what you can see on the chart named without linear regression. The
  uncertainty of slope(the frequency ratio of ref and signal ) is
 contributed
  by these 2 measurements. With linear regression of all 9000 data within
 one
  second, the uncertainty will reduced to smaller one. (I really can't
  remember the ratio. Something like sqrt(9000)).
 
 
  while(1) {
 double t3;  //fraction part of refcnt, measured by tdc_gp22
 double ref_curr;
 uint32_t sig_curr;
 static double ref_start;
 static uint32_t sig_start;
 uint32_t refcnt, sigcnt;
 const uint32_t gate_time = 1000; // 1000ms gate time
 
 if (i == 0) {
 init_regression(rv);
 cpld_rst();
 timestamp(refcnt, sigcnt, t3);
 ref_start = refcnt - t3;
 sig_start = sigcnt;
 i++;
 continue;
 }
 
 timestamp(refcnt, sigcnt, t3);
 
 regression_enter_data(rv, refcnt - t3 - ref_start, sigcnt -
 sig_start);
 if (msecond  gate_time) {
 i++;
 continue;
 } else  {
 t = regression_slope(rv) ; // with linear regression
 printf(\r\nFreq=%.*f, 14, t);
 ref_curr = refcnt - t3;
 sig_curr = sigcnt;
 
 t = CalcFreq(ref_curr - ref_start, sig_curr -
  sig_start); // without linear regression
 printf( Interpolated=%.*f, 12, t);
 
 msecond = 0;
   i = 0;
 }
  }
 
  2014-12-12 21:18 GMT+08:00 Bob Camp kb...@n1k.org:
 
  HI
 
  On Dec 12, 2014, at 4:04 AM, Tom Van Baak t...@leapsecond.com wrote:
 
  This large posting is from Li Ang.
  /tvb
 
  - Original Message -
  From: Li Ang
  To: Discussion of precise time and frequency measurement
  Sent: Thursday, December 11, 2014 7:37 AM
  Subject: Re: [time-nuts] Homebrew frequency counter, need help
 
 
  Hi Bob,
   I've sent the PCB to the factory and I am waiting for the new board.
  This time, it's a 4-layer borad and changed from CPLD to FPGA. This is
 the
  first time of FPGA  4-layer project. Hope everthing be OK.
 
  Very nice looking. I hope it works !!!
 
   TPS79333 as the LDO for TDC. Better PSRR and noise spec than before
  (XC6206). Analog and digital parts have their dedicated LDO.
 
 
   While I'm waiting the the new board. I did a test with PRS10  FE5650
  with current board. It's strange that the 20s adev of without linear
  regression is better than with linear regression”
 
  Be careful pre-processing ADEV data. There are a variety of statistical
  “traps” you can fall into. An overly simple explanation is that ADEV
 looks
  at noise and that most pre-processing is a filter. Filters take out
 noise.
  Finding one that only takes out the “bad noise” and keeps the “good
 noise”
  can be quite difficult.
 
  What exactly are you doing in your linear regression computation?
 
  Bob
 
 
 
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Re: [time-nuts] Homebrew frequency counter, need help

[Li Ang]

2014-11-29 1:41 GMT+08:00 Bob Camp kb...@n1k.org:

 Hi

  On Nov 28, 2014, at 10:14 AM, Li Ang lll...@gmail.com wrote:
 
 
  1) What frequency is the crystal at? (can you drive the chip from an
 OCXO?)
 
  I'm clking this chip with the refclk/2=5Mhz, which is done by cpld.
  something like always @(posedge refclk) tdc_clk = ~tdc_clk; Not sure if
  it's noisy.

 If the clock source into the CPLD is clean, the output should not be to
 bad.

 
  2) Is there more bypassing on the circuit than shown? (If not, add some
  more).
 
  Since there is only few power supply pins, I just put 100uF + 100nF
 there.
  I can try put more to see if helps. And I'm going to use dedicated LDO
 for
  digital part and analog part next time to make a new pcb.

 I suspect that a few more 100nF caps might be a good idea. They may not
 help, but it would rule out the supply as an issue.

 
  3) How confident are you of your input signal? (can you check it with a
  “known good” counter?)
 
  The best counter I get is the RACAL DANA 1992. That is not good enough.
 I
  think the accurarcy is not a problem, as if the reference is good enough,

 That’s correct. I was hoping you might be able to borrow a SR620 or 53132
 for a few minutes to check your input signal.

  it's only the matter of math. I prefer to enhance the resolution and
 reduce
  noise.

 If the noise is on your test signal, it can be very frustrating to chase
 it with a lot of software work.

  I'm using Trimble GPSDO(NTPX26AB) as the signal source

 The GPSDO should be fairly quiet, but it has an ADEV that’s a bit high.
 The outputs also can have noise on them.

  and FE5650 Rb

 The FE Rb’s tend to have a lot of spurs on the output. In some cases that
 can get you in trouble.

  as the ref. I've tried Rb+MV89A

 If the MV89A is working properly, it should be a pretty good source. Based
 on some of the prices I’ve seen on the internal China market, you might get
 a couple of them as sources.

  and Rb + SMY01 signal generator, same
  performance. The 2nd-hand 53132A,PM6690,SR620 about 600~800$ here in
 China.
  I'm trying not to get one unless necessary. If I have get one to compare
  the performance, what's your suggested model?

 The SR620 is a good counter, so is the 53132. They both can have problems.
 The 53132 display wears out and it’s power supply can fail. The 620 can run
 a bit hot, which kills a variety of parts in it. It’s better to pay a bit
 more for one you can actually check out before you buy than to get one
 shipped in.

 
 
  4) Have you tried jumping the 10 ohm resistor on the regulator output?
 (it
  may not be helping things …)
 
  I'll try to remove that tomorrow

 It may be allowing the supply to drop a bit when the chip goes into some
 sort of computation. Often these things happen at just the wrong time …


 

 If you have a CPLD and a MV89:

 1) With a 10 MHz sine wave  out of the OCXO, you need to convert it to
 logic first. A biased input is a pretty good way to do this.

 2) Generate 200 or 400 ns wide pulses out of the CPLD for testing. That
 will eliminate any issues from the 5 MHz crystal in the MV-89.

 3) Keep the PCB as simple as you can. You need at least a double sided
 board (one side ground plane). If you can get a cheap 4 layer board, go for
 it. A full internal ground plane is a good thing.

 4) Route the high speed signals (like the OCXO output) through solid
 connections. Flying wire leads are not a good idea. Mounting a MV89 direct
 to the PCB is a good way to do things. SMA connectors are also good.

 5) If you have an oscilloscope or can borrow one, take a look at the
 signals on your board. Even a quick check can tell you a lot about signals
 that are not what they should be.

 6) Be careful of ground loops and power supply issues. I’ve spent a *lot*
 of time on breadboards that didn’t work because I had power line noise
 running around.

 Good luck !!

 Bob


 
 
  All of which is *plenty* good enough to make a decent counter.  That
  assumes that they are talking about accuracy (even 1 sigma) rather than
  just the resolution of the LSB. Specs are often confusing on parts like
  this.
 
  I guess the accuracy is not important in the interpolator scenario.  It
 has
  a feature to output the result of delta_time / ref_cycle_time(it will
  measure the 2cycle_time - 1cycle_time after the delta_time measurement
 and
  do the float calculation).  All I need is this part(it's the fraction
 part
  of refcnt). So if I can reach 90ps resolution they claim, the counter can
  tell 1/1000 of one reference cycle. That's 3 digits.
 
 
 
  Thanks.
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Re: [time-nuts] Homebrew frequency counter, need help

[Li Ang]

Hi
   Thanks for the great article.
   I did a little test just now. To measure the refclk of itself. And this
is the result(I kept 10 digits of the fraction part):

### Frequency Counter startup ###
gate=1s #=8985  freq=10.02
gate=1s #=9038  freq=10.01
gate=1s #=9039  freq=10.02
gate=1s #=9038  freq=10.00
gate=1s #=9034  freq=10.02
gate=1s #=9038  freq=10.02
gate=1s #=9037  freq=10.02
gate=1s #=9038  freq=10.01
gate=1s #=9037  freq=10.01
gate=1s #=9038  freq=10.01
gate=1s #=9039  freq=10.00
gate=1s #=9034  freq=10.02
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq=10.02
gate=1s #=9038  freq=10.02
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq=10.02
gate=1s #=9038  freq=10.02
gate=1s #=9038  freq=10.00
gate=1s #=9034  freq=10.00
gate=1s #=9029  freq=10.00
gate=1s #=9034  freq= 9.99
gate=1s #=9034  freq=10.01
gate=1s #=9030  freq=10.02
gate=1s #=9037  freq=10.02
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq=10.00
gate=1s #=9034  freq=10.02
gate=1s #=9038  freq=10.03
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq=10.03
gate=1s #=9037  freq=10.01
gate=1s #=9038  freq=10.02
gate=1s #=9038  freq=10.02
gate=1s #=9038  freq=10.00
gate=1s #=9030  freq=10.03
gate=1s #=9038  freq=10.00
gate=1s #=9034  freq=10.01
gate=1s #=9038  freq=10.01
gate=1s #=9039  freq=10.01
gate=1s #=9038  freq=10.01
gate=1s #=9037  freq=10.00
gate=1s #=9030  freq=10.01
gate=1s #=9038  freq=10.01
gate=1s #=9037  freq= 9.99
gate=1s #=9035  freq=10.00
gate=1s #=9039  freq=10.02
gate=1s #=9037  freq= 9.99
gate=1s #=9034  freq=10.02
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq=10.02
gate=1s #=9038  freq=10.00
gate=1s #=9034  freq=10.00
gate=1s #=9030  freq=10.01
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq=10.00
gate=1s #=9030  freq=10.01
gate=1s #=9030  freq=10.00
gate=1s #=9034  freq=10.01
gate=1s #=9038  freq= 9.99
gate=1s #=9034  freq=10.02
gate=1s #=9038  freq=10.01
gate=1s #=9030  freq= 9.99
gate=1s #=9034  freq=10.00
gate=1s #=9030  freq=10.01
gate=1s #=9038  freq=10.00
gate=1s #=9031  freq=10.01
gate=1s #=9038  freq=10.00
gate=1s #=9039  freq=10.00
gate=1s #=9034  freq=10.01
gate=1s #=9038  freq=10.00
gate=1s #=9039  freq=10.01
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq=10.00
gate=1s #=9034  freq=10.00
gate=1s #=9039  freq=10.01
gate=1s #=9037  freq=10.01
gate=1s #=9038  freq=10.03
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq=10.01
gate=1s #=9030  freq=10.02
gate=1s #=9038  freq=10.01
gate=1s #=9037  freq=10.01
gate=1s #=9030  freq=10.01
gate=1s #=9037  freq= 9.99
gate=1s #=9034  freq=10.00
gate=1s #=9030  freq=10.00
gate=1s #=9034  freq=10.02
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq=10.00
gate=1s #=9030  freq=10.02
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq= 9.99
gate=1s #=9034  freq=10.01
gate=1s #=9038  freq=10.02
gate=1s #=9037  freq= 9.99
gate=1s #=9034  freq=10.02
gate=1s #=9038  freq=10.01
gate=1s #=9038  freq= 9.99
gate=1s #=9034  freq=10.00
gate=1s #=9030  freq=10.01

2014-11-29 5:57 GMT+08:00 Kasper Pedersen time-n...@kasperkp.dk:

 On 11/27/2014 03:08 PM, lllaaa wrote:
  Hi guys,
  I've just get my homebrew counter working. And the resolution seems
 10x
  better than my RACAL DANA 1992.
  This counter is heavily inspired by the idea from Kasper Pedersen.
  http://n1.taur.dk/permanent/frequencymeasurement.pdf
  STM32F051RB  EMP240T100C5 do the control and counting job. TDC-GP22
 as
  the interpolator. Linear regression is done by CPU.
  There are no fancy analog front for both signal path and refclk path.
  I'm using two SN75ALS176 and the schmitt input of CPLD to do the job.
  I've noticed that the 10s gate does not get more meaningful
  digits(looks worse than 1s gate). So here are the questions:
  1) I'm wondering if I could say this is an 11 digits/s counter?
  2) How can I improve that? Is it limited by the 485 transceiver? I
 can
  switch to a faster MCU, that gets more measures per second, but I 

Re: [time-nuts] Homebrew frequency counter, need help

[Li Ang]

I did a little calculation and it's a 10 digits counter.
log(10,000,000,005) = 10.
There is still a big gap between this one and 53132A :(

For 53132A, the time resolution is 150ps, which I think is 10digits/s with
interpolator. According to the schematics the only difference between
53132A  53131A is the ADC of interpolator. It is the reason why 53131A
only has time resolution of 500ps (also 10digits/s). However, 53132A is a
12 digits/s counter. I guess the 2 more digits come from software. Linear
regression maybe ?

2014-11-28 11:15 GMT+08:00 Bob Camp kb...@n1k.org:

 Hi

 One way of looking at resolution is at the one standard deviation point.
 Another way of looking at it is as a +/- 1 digit accuracy point. Each
 approach has it’s advantages. It’s more common to see single shot timing
 specified as one sigma and frequency specified as +/- 1 count. Often you
 need to read the fine print to see just what is being spec’d.


  On Nov 27, 2014, at 5:30 PM, LiAng lll...@gmail.com wrote:
 
  Thanks for the info.
 
  What's the standard to be 11 digits/s? For real 11 digits/s, the ADEV
  needs to reach the 1e-11 level? I'm not sure if my GPSDO  Rb is stable
  enough. Maybe 2 MV89A as the refclk and signal?

 For the “easy” approach, first feed the counter’s reference back into the
 input. That will usually give you a “best result no matter what” sort of
 reading. It also will suppress a variety of problems coming from the
 reference signal.

 A source with a 1x10^-12 ADEV at 1 second should be good enough for
 testing a 10 to 11 digit counter. It’s not going to do the trick for a 12
 digit device. In the case of a 12 digit device, use a second copy of what
 ever you are using for the reference for the counter ….

 ——

 Another approach, don’t measure frequency, measure period / time / phase.
 Generating a pulse that is 100 ns wide is fairly easy. Doing so with  1 ps
 jitter is not impossible. If your signal source is good to a few ppm, your
 pulse generation accuracy will be “plenty good enough”. Things like rise
 and fall times through buffers will be a much bigger deal in the delivered
 result than the absolute accuracy of the clock feeding the circuit. If the
 counter measures the resulting pulse with a 10 ps one sigma error, you have
 a 10 ps counter. If it says that 100 ns is 102 ns, that’s to be expected
 with a simple pulse generation technique. Yes, you eventually do need to
 verify that 100 ns is 100 ns, but that can be done a different way.

 Bob

 
 
  TDC-GP22 has it problem, I will post some data/schematic/source code
  about it later.
 
  Thanks
 
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Re: [time-nuts] Homebrew frequency counter, need help

[Li Ang]

 1) What frequency is the crystal at? (can you drive the chip from an OCXO?)

I'm clking this chip with the refclk/2=5Mhz, which is done by cpld.
something like always @(posedge refclk) tdc_clk = ~tdc_clk; Not sure if
it's noisy.

2) Is there more bypassing on the circuit than shown? (If not, add some
 more).

Since there is only few power supply pins, I just put 100uF + 100nF there.
I can try put more to see if helps. And I'm going to use dedicated LDO for
digital part and analog part next time to make a new pcb.

3) How confident are you of your input signal? (can you check it with a
 “known good” counter?)

The best counter I get is the RACAL DANA 1992. That is not good enough.  I
think the accurarcy is not a problem, as if the reference is good enough,
it's only the matter of math. I prefer to enhance the resolution and reduce
noise. I'm using Trimble GPSDO(NTPX26AB) as the signal source and FE5650 Rb
as the ref. I've tried Rb+MV89A and Rb + SMY01 signal generator, same
performance. The 2nd-hand 53132A,PM6690,SR620 about 600~800$ here in China.
I'm trying not to get one unless necessary. If I have get one to compare
the performance, what's your suggested model?


 4) Have you tried jumping the 10 ohm resistor on the regulator output? (it
 may not be helping things …)

I'll try to remove that tomorrow


All of which is *plenty* good enough to make a decent counter.  That
 assumes that they are talking about accuracy (even 1 sigma) rather than
 just the resolution of the LSB. Specs are often confusing on parts like
 this.

I guess the accuracy is not important in the interpolator scenario.  It has
a feature to output the result of delta_time / ref_cycle_time(it will
measure the 2cycle_time - 1cycle_time after the delta_time measurement and
do the float calculation).  All I need is this part(it's the fraction part
of refcnt). So if I can reach 90ps resolution they claim, the counter can
tell 1/1000 of one reference cycle. That's 3 digits.



Thanks.
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