Re: [time-nuts] FE-5680A clock shaping (sine - square wave)
On Tue, 03 Jan 2012 07:01:13 +0100, ehydra ehy...@arcor.de wrote: David schrieb: I could analyze it on SPICE but I suspect the real world construction parasitics will be what limits the performance. I just sketched it out in my notebook but I will see if I can post it somewhere. Is there a quick and dirty online schematic capture site? Scan it. I will make a LTspice file. It is not that complicated being a differential amplifier driving complementary pair of emitter followers, a pair of voltage clamps, and then a pair of complementary current mirrors configured as transconductance amplifiers. I want to SEE it including all circuit parameters. Thank you. I am entering it into LT Spice for practice. I will post the results and files here when done. I need to rethink the level shift configuration. When you say symmetry limiting do you mean to prevent second harmonic distortion like for driving a mixer? I was thinking of this more for driving a single ended transmission line cleanly while maximizing the edge rates and minimizing jitter. Duty cycle correction could be added pretty easily. Hm. I think second harmonic distortion looks very much like intentional symmetric waveform in the first instance. The fun begins if we decide to look for equal time distance or equal power for both phases. Interesting. The circuit you linked is going to have a little problem since both the 2N5769 and the 2N5770 are NPN and the circuit requires a pair of PNPs. Other than that it looks perfect for driving a high level mixer. As far as I know driving a mixer was the circuit intention. I SPICEd it with BFR93 types. The circuit has a high reflection coefficient, unfortunately. Maybe this is unavoidable and we need a diplexer. The output is low impedance, unmatched, and I suspect not quite symmetrical so I would expect this. Does it matter though if the mixer is close by? Yes, looks like an typo for having 4 NPNs there. I will clarify this with Chris Trask. Thanks. Unfortunately, RF PNP transistors tend to be rare or expensive so when I saw that schematic my first thought was, Hmm. I wonder if that is the RF PNP I have been looking for. I did not know the 2N5770 had a PNP complement. Wait a sec . . . I have been considering the PNP BFG21 and NPN BFG97 made by NXP. They are SOT-223 so should be easier to prototype with than a smaller package. The On Semiconductor TO-92 NPN MPSH10 and PNP MPSH81 would be good also but the later is being discontinued. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] FE-5680A clock shaping (sine - square wave)
Is it possible to sketch the circuit? I can SPICE it. Symmetry limiting is the holy grail and it is questionable if a discrete design is way better than one of the chips. Here is another limiter circuit (by Chris Trask): http://ehydra.dyndns.info/NG/LTspice/Negative%20Impedance%20LO%20Driver.pdf - Henry David schrieb: What kind of performance would you expect in this application? Low jitter? 50 ohm output? TTL or better signal levels? Fast rise and fall times? Duty cycle correction? After reading your post I was thinking about how to go about it and ended up with an 8 transistor discrete design using a differential amplifier input and pair of current mirror transconductance amplifiers for the output. I have been looking into designing a pulse generator for oscilloscope calibration and have an interest in GPSDOs so maybe I will prototype this as well just to see what kind of performance a bunch of 2N3904 and 2N4401 jelly bean transistors can provide. On Thu, 29 Dec 2011 21:14:30 -0800, John Beale be...@bealecorner.com wrote: In case it's useful... there are many ways to get a square wave out from a sine wave in, but one straightforward way is with a comparator. Some work better than others. The slow ones won't work at all at 10 MHz, and the very fast comparators (MAX999, ADCMP600, LT1116 etc.) are more expensive, and perhaps harder to work with. I tried a MAX9013 in SO-8 package and it works well for the job. You can see my schematic, circuit and scope plots at the bottom of this page: -- ehydra.dyndns.info ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] FE-5680A clock shaping (sine - square wave)
Hi In most cases it's a T section (two coils, one cap) low pass filter tacked on to the output of a logic gate (or FPGA output). Net result is a reasonable sine wave *if* you terminate it correctly. Based on the observations posted on the list, the filter in the FE-5680 seems to be set up for a 50 ohm resistive load and is mis-terminated when run into a scope probe. Not to surprisingly, you get a lot less output voltage into the correct load than into an open circuit. With a filter, the difference can be significantly more than 2:1. The logic gate / FPGA is putting out about 3 volts p-p, so that will be the filter went away output level. The matched value will be quite a bit lower to keep the gate / FPGA from going a bit nuts power wise. Bob On Jan 2, 2012, at 9:52 AM, ehydra wrote: Is it possible to sketch the circuit? I can SPICE it. Symmetry limiting is the holy grail and it is questionable if a discrete design is way better than one of the chips. Here is another limiter circuit (by Chris Trask): http://ehydra.dyndns.info/NG/LTspice/Negative%20Impedance%20LO%20Driver.pdf - Henry David schrieb: What kind of performance would you expect in this application? Low jitter? 50 ohm output? TTL or better signal levels? Fast rise and fall times? Duty cycle correction? After reading your post I was thinking about how to go about it and ended up with an 8 transistor discrete design using a differential amplifier input and pair of current mirror transconductance amplifiers for the output. I have been looking into designing a pulse generator for oscilloscope calibration and have an interest in GPSDOs so maybe I will prototype this as well just to see what kind of performance a bunch of 2N3904 and 2N4401 jelly bean transistors can provide. On Thu, 29 Dec 2011 21:14:30 -0800, John Beale be...@bealecorner.com wrote: In case it's useful... there are many ways to get a square wave out from a sine wave in, but one straightforward way is with a comparator. Some work better than others. The slow ones won't work at all at 10 MHz, and the very fast comparators (MAX999, ADCMP600, LT1116 etc.) are more expensive, and perhaps harder to work with. I tried a MAX9013 in SO-8 package and it works well for the job. You can see my schematic, circuit and scope plots at the bottom of this page: -- ehydra.dyndns.info ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] FE-5680A clock shaping (sine - square wave)
The output level and impedance is why I ended up with the circuit I did. The complementary transconductance output allows a near 5 volt rail to rail swing from a 5 volt supply while driving a 50 ohm transmission line and 50 ohm shunt termination to 5 volts on the driver side. It would be a power hog though with the output stage drawing about 100mA with a correctly terminated load which is why you would not typically find it on an IC. On Mon, 2 Jan 2012 10:41:01 -0500, Bob Camp li...@rtty.us wrote: Hi In most cases it's a T section (two coils, one cap) low pass filter tacked on to the output of a logic gate (or FPGA output). Net result is a reasonable sine wave *if* you terminate it correctly. Based on the observations posted on the list, the filter in the FE-5680 seems to be set up for a 50 ohm resistive load and is mis-terminated when run into a scope probe. Not to surprisingly, you get a lot less output voltage into the correct load than into an open circuit. With a filter, the difference can be significantly more than 2:1. The logic gate / FPGA is putting out about 3 volts p-p, so that will be the filter went away output level. The matched value will be quite a bit lower to keep the gate / FPGA from going a bit nuts power wise. Bob On Jan 2, 2012, at 9:52 AM, ehydra wrote: Is it possible to sketch the circuit? I can SPICE it. Symmetry limiting is the holy grail and it is questionable if a discrete design is way better than one of the chips. Here is another limiter circuit (by Chris Trask): http://ehydra.dyndns.info/NG/LTspice/Negative%20Impedance%20LO%20Driver.pdf - Henry David schrieb: What kind of performance would you expect in this application? Low jitter? 50 ohm output? TTL or better signal levels? Fast rise and fall times? Duty cycle correction? After reading your post I was thinking about how to go about it and ended up with an 8 transistor discrete design using a differential amplifier input and pair of current mirror transconductance amplifiers for the output. I have been looking into designing a pulse generator for oscilloscope calibration and have an interest in GPSDOs so maybe I will prototype this as well just to see what kind of performance a bunch of 2N3904 and 2N4401 jelly bean transistors can provide. On Thu, 29 Dec 2011 21:14:30 -0800, John Beale be...@bealecorner.com wrote: In case it's useful... there are many ways to get a square wave out from a sine wave in, but one straightforward way is with a comparator. Some work better than others. The slow ones won't work at all at 10 MHz, and the very fast comparators (MAX999, ADCMP600, LT1116 etc.) are more expensive, and perhaps harder to work with. I tried a MAX9013 in SO-8 package and it works well for the job. You can see my schematic, circuit and scope plots at the bottom of this page: -- ehydra.dyndns.info ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] FE-5680A clock shaping (sine - square wave)
I could analyze it on SPICE but I suspect the real world construction parasitics will be what limits the performance. I just sketched it out in my notebook but I will see if I can post it somewhere. Is there a quick and dirty online schematic capture site? It is not that complicated being a differential amplifier driving complementary pair of emitter followers, a pair of voltage clamps, and then a pair of complementary current mirrors configured as transconductance amplifiers. When you say symmetry limiting do you mean to prevent second harmonic distortion like for driving a mixer? I was thinking of this more for driving a single ended transmission line cleanly while maximizing the edge rates and minimizing jitter. Duty cycle correction could be added pretty easily. The circuit you linked is going to have a little problem since both the 2N5769 and the 2N5770 are NPN and the circuit requires a pair of PNPs. Other than that it looks perfect for driving a high level mixer. On Mon, 02 Jan 2012 15:52:18 +0100, ehydra ehy...@arcor.de wrote: Is it possible to sketch the circuit? I can SPICE it. Symmetry limiting is the holy grail and it is questionable if a discrete design is way better than one of the chips. Here is another limiter circuit (by Chris Trask): http://ehydra.dyndns.info/NG/LTspice/Negative%20Impedance%20LO%20Driver.pdf - Henry David schrieb: What kind of performance would you expect in this application? Low jitter? 50 ohm output? TTL or better signal levels? Fast rise and fall times? Duty cycle correction? After reading your post I was thinking about how to go about it and ended up with an 8 transistor discrete design using a differential amplifier input and pair of current mirror transconductance amplifiers for the output. I have been looking into designing a pulse generator for oscilloscope calibration and have an interest in GPSDOs so maybe I will prototype this as well just to see what kind of performance a bunch of 2N3904 and 2N4401 jelly bean transistors can provide. On Thu, 29 Dec 2011 21:14:30 -0800, John Beale be...@bealecorner.com wrote: In case it's useful... there are many ways to get a square wave out from a sine wave in, but one straightforward way is with a comparator. Some work better than others. The slow ones won't work at all at 10 MHz, and the very fast comparators (MAX999, ADCMP600, LT1116 etc.) are more expensive, and perhaps harder to work with. I tried a MAX9013 in SO-8 package and it works well for the job. You can see my schematic, circuit and scope plots at the bottom of this page: ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] FE-5680A clock shaping (sine - square wave)
David schrieb: I could analyze it on SPICE but I suspect the real world construction parasitics will be what limits the performance. I just sketched it out in my notebook but I will see if I can post it somewhere. Is there a quick and dirty online schematic capture site? Scan it. I will make a LTspice file. It is not that complicated being a differential amplifier driving complementary pair of emitter followers, a pair of voltage clamps, and then a pair of complementary current mirrors configured as transconductance amplifiers. I want to SEE it including all circuit parameters. Thank you. When you say symmetry limiting do you mean to prevent second harmonic distortion like for driving a mixer? I was thinking of this more for driving a single ended transmission line cleanly while maximizing the edge rates and minimizing jitter. Duty cycle correction could be added pretty easily. Hm. I think second harmonic distortion looks very much like intentional symmetric waveform in the first instance. The fun begins if we decide to look for equal time distance or equal power for both phases. Interesting. The circuit you linked is going to have a little problem since both the 2N5769 and the 2N5770 are NPN and the circuit requires a pair of PNPs. Other than that it looks perfect for driving a high level mixer. As far as I know driving a mixer was the circuit intention. I SPICEd it with BFR93 types. The circuit has a high reflection coefficient, unfortunately. Maybe this is unavoidable and we need a diplexer. Yes, looks like an typo for having 4 NPNs there. I will clarify this with Chris Trask. Thanks. Here is another limiter circuit (by Chris Trask): http://ehydra.dyndns.info/NG/LTspice/Negative%20Impedance%20LO%20Driver.pdf - Henry -- ehydra.dyndns.info ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] FE-5680A clock shaping (sine - square wave)
On Thu, 29 Dec 2011 21:14:30 -0800, John Beale be...@bealecorner.com wrote: In case it's useful... there are many ways to get a square wave out from a sine wave in, but one straightforward way is with a comparator. [...] FWIW, I decided on a more straightforward way to get a square wave output from my FE-5680A: bypass the internal sine-wave filter, and take the original 10 MHz output direct from the XC9572 CPLD ! (now, I vaguely recall, this may have already been described on the list...) Here's a photo of the modification I did: unsolder and rotate the 15 ohm resistor on CPLD pin 49, so it now feeds a short ribbon cable, which runs through the hole in the case intended for the (non-working) trim pot: https://picasaweb.google.com/lh/photo/YkQseTWUZolGYd5VSwE9odMTjNZETYmyPJy0liipFm0?feat=directlink What the square wave looks like coming out through the cable, on a TDS-210 with 10x probe, no termination load: https://picasaweb.google.com/lh/photo/lcFB0P5rEEd10K508nWCv9MTjNZETYmyPJy0liipFm0?feat=directlink I see a 10 MHz 3.3V square wave with ~5 ns risetime and about 0.3 Vpp of ringing, probably as good as I could expect with this scope and wiring arrangement. I suspect this way I will get better jitter performance than I could expect trying to square up the standard sine wave output by whatever means. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] FE-5680A clock shaping (sine - square wave)
What kind of performance would you expect in this application? Low jitter? 50 ohm output? TTL or better signal levels? Fast rise and fall times? Duty cycle correction? After reading your post I was thinking about how to go about it and ended up with an 8 transistor discrete design using a differential amplifier input and pair of current mirror transconductance amplifiers for the output. I have been looking into designing a pulse generator for oscilloscope calibration and have an interest in GPSDOs so maybe I will prototype this as well just to see what kind of performance a bunch of 2N3904 and 2N4401 jelly bean transistors can provide. On Thu, 29 Dec 2011 21:14:30 -0800, John Beale be...@bealecorner.com wrote: In case it's useful... there are many ways to get a square wave out from a sine wave in, but one straightforward way is with a comparator. Some work better than others. The slow ones won't work at all at 10 MHz, and the very fast comparators (MAX999, ADCMP600, LT1116 etc.) are more expensive, and perhaps harder to work with. I tried a MAX9013 in SO-8 package and it works well for the job. You can see my schematic, circuit and scope plots at the bottom of this page: https://picasaweb.google.com/bealevideo/FE5680A My circuit works best with a sine wave input amplitude above 100 mVpp. Below that level, the duty cycle starts to become noticeably worse. I am using some hysteresis, but it may not be necessary. Previous to those pics on the page, you also see a circuit which did not work so well, using a MAR-1 (broadband DC-1GHz MMIC amp). It's intended as a linear amp, and it does not saturate in a symmetric way even with large input signals. Here are a few other circuits of interest, which I did not try: http://www.ko4bb.com/~bruce/CLKSHPR.html http://www.ko4bb.com/Timing/ClockShaper.php ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] FE-5680A clock shaping (sine - square wave)
The spec is over the entire temp range, and it may not be linear to temp. It could be more sensitive at some temps than others.. Especially if the temp is digitally compensated inside the unit. Sent From iPhone On Dec 29, 2011, at 23:55, Chris Albertson albertson.ch...@gmail.com wrote: On Thu, Dec 29, 2011 at 9:14 PM, John Beale be...@bealecorner.com wrote: ...and by the way, my FE-5680A shows a consistent -7E-12 per degree C temperature sensitivity (measured at case temp 42 and 52 C). The spec says 3E-10 from -5C to 50C So (3E-10)/55 = 5.5E-12 and you got 7E-12 I'd say it close to what's advertized. Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] FE-5680A clock shaping (sine - square wave)
Heck- for a really good risetime, all you need is a mercury-wetted relay :-) Don David What kind of performance would you expect in this application? Low jitter? 50 ohm output? TTL or better signal levels? Fast rise and fall times? Duty cycle correction? After reading your post I was thinking about how to go about it and ended up with an 8 transistor discrete design using a differential amplifier input and pair of current mirror transconductance amplifiers for the output. I have been looking into designing a pulse generator for oscilloscope calibration and have an interest in GPSDOs so maybe I will prototype this as well just to see what kind of performance a bunch of 2N3904 and 2N4401 jelly bean transistors can provide. On Thu, 29 Dec 2011 21:14:30 -0800, John Beale be...@bealecorner.com wrote: In case it's useful... there are many ways to get a square wave out from a sine wave in, but one straightforward way is with a comparator. Some work better than others. The slow ones won't work at all at 10 MHz, and the very fast comparators (MAX999, ADCMP600, LT1116 etc.) are more expensive, and perhaps harder to work with. I tried a MAX9013 in SO-8 package and it works well for the job. You can see my schematic, circuit and scope plots at the bottom of this page: https://picasaweb.google.com/bealevideo/FE5680A My circuit works best with a sine wave input amplitude above 100 mVpp. Below that level, the duty cycle starts to become noticeably worse. I am using some hysteresis, but it may not be necessary. Previous to those pics on the page, you also see a circuit which did not work so well, using a MAR-1 (broadband DC-1GHz MMIC amp). It's intended as a linear amp, and it does not saturate in a symmetric way even with large input signals. Here are a few other circuits of interest, which I did not try: http://www.ko4bb.com/~bruce/CLKSHPR.html http://www.ko4bb.com/Timing/ClockShaper.php ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Neither the voice of authority nor the weight of reason and argument are as significant as experiment, for thence comes quiet to the mind. R. Bacon If you don't know what it is, don't poke it. Ghost in the Shell Dr. Don Latham AJ7LL Six Mile Systems LLP 17850 Six Mile Road POB 134 Huson, MT, 59846 VOX 406-626-4304 www.lightningforensics.com www.sixmilesystems.com ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] FE-5680A clock shaping (sine - square wave)
In case it's useful... there are many ways to get a square wave out from a sine wave in, but one straightforward way is with a comparator. Some work better than others. The slow ones won't work at all at 10 MHz, and the very fast comparators (MAX999, ADCMP600, LT1116 etc.) are more expensive, and perhaps harder to work with. I tried a MAX9013 in SO-8 package and it works well for the job. You can see my schematic, circuit and scope plots at the bottom of this page: https://picasaweb.google.com/bealevideo/FE5680A My circuit works best with a sine wave input amplitude above 100 mVpp. Below that level, the duty cycle starts to become noticeably worse. I am using some hysteresis, but it may not be necessary. Previous to those pics on the page, you also see a circuit which did not work so well, using a MAR-1 (broadband DC-1GHz MMIC amp). It's intended as a linear amp, and it does not saturate in a symmetric way even with large input signals. Here are a few other circuits of interest, which I did not try: http://www.ko4bb.com/~bruce/CLKSHPR.html http://www.ko4bb.com/Timing/ClockShaper.php ...and by the way, my FE-5680A shows a consistent -7E-12 per degree C temperature sensitivity (measured at case temp 42 and 52 C). Has anyone else measured theirs? -john beale ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] FE-5680A clock shaping (sine - square wave)
On Thu, Dec 29, 2011 at 9:14 PM, John Beale be...@bealecorner.com wrote: ...and by the way, my FE-5680A shows a consistent -7E-12 per degree C temperature sensitivity (measured at case temp 42 and 52 C). The spec says 3E-10 from -5C to 50C So (3E-10)/55 = 5.5E-12 and you got 7E-12 I'd say it close to what's advertized. Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
