Re: [time-nuts] 1 PPS 50-ohm driver

[Florian Teply]

Am Mon, 18 Apr 2016 18:15:22 -0400
schrieb Bob Camp :

> Hi
> 
> If our approach was to fabricate an IC totally from scratch for this
> or that application, there are a lot of things that could be done.
> Unfortunately, for most of us, doing that to wire up an output on a
> board … not so much. 
> 
I fully agree, usually this is totally out of question. But, IF one
does need something like that, AND has the proper tools/skills
available, this would be feasible at not so high cost. Having Skills
and tools available does not necessarily mean to personally have these.
Quite a number of university groups do work on IC design of some sort.
Where I work, we regularly do MPW runs for all sorts of customers,
among which are quite a number of universities. In our basic 250nm
process, MPW goes at slightly less than 3k Euro per square millimetre
for up to 40 parts. One square millimetre does get you quite far in
250nm technologies. Sure, this does not include packaging as we don't do
that. And yes, one can easily get plain CMOS for much less than that
elsewhere. But for that sort of money you'd actually get a full SiGe
BiCMOS process. No, I definitely wouldn't recommend that sort of pricing
for production of millions of pieces a year, but that's not our main
target in any case, as we're a research institution, not a commercial
foundry. Plain 250nm CMOS through educational outfits like europractice
or MOSIS, I'd expect to run at about half to one third that price.

> Starting back in the 1970’s people stopped making packaged inverters
> with single transistor pairs. The problem was they didn’t get enough
> gain or isolation through a single pair. For the few places that
> *did* keep making the single pair parts, they carefully labeled them
> as such so you would not misuse them. 
> 
> Once you get into packaged logic designed in the 80’s or later,
> “unbuffered” gates pretty much vanish. An inverter is made of three
> transistor pairs and a “non inverter” is made from two transistor
> pairs. The net result is that the “non inverter” is slightly faster.
> Again, this does not apply if you make your own chip from scratch on
> a silicon wafer. It only applies if you want to buy pre-packaged
> parts from somebody like TI. 
> 
> The speed difference is not as great as you might think. The
> capacitance on the internal nodes is mighty low. That makes the
> “internal” inverter very fast compared to the rest of the circuit. 
> 
I'd consider something on the order of 100 ps of gate delay per stage.
But this strongly depends on load. In "standard" 250 nm CMOS with about
5 nm Gate Oxide, gate capacitance is on the order of 50fF/um^2, so a
single minimum drive strength inverter would be slightly more than 10fF.
Agreed, that's not very much. As a matter of fact, I myself would
ignore it at PCB level. But with transistor saturation currents on the
order of 100uA, it'll take some time to charge and discharge...

And If you're trying to meet JEDEC standards for CMOS drive strength,
you'll end up with transistors of a hundred microns gate width or more,
which by themselves already pose a significant capacitive load on the
order of a few picofarads. Well, insignificant in most PCB
environments, but on chip this is pretty significant. And when one
needs to go from core logic (about one micron gate width, 10-30 fF
capacitance, max current 100uA) to PCB (capacitive loads of tens of
picofarads, several milliamps of current drive at low voltage drops),
the optimization isn't that straightforward: a high number of stages
with low relative capacitive load (meaning that one stage has a low
multiple of its own input capacitance as a load on its output) might or
might not be preferred over a low number of stages, where each one sees
huge relative capacitive loads and therefore has long transition times.
In the end it's a tradeoff between Input-to-Output delay, risetime and
power consumption. But certainly a higher number of stages does not
necessarily mean higher input-to-output delay.

> Of course if you *did* fabricate a single transistor pair on your
> own, you also would need to invent a way to dice it so that pair was
> not “swimming” in an ocean of un-used silicon. The capacitance of all
> that real estate counts as well …
>
Oh yeah. A single inverter would need something on the order of maybe
2umx5um.Compared to that, even a single bond pad would be really
huge with 80um x 80um. And one would need at least four bond pads.
If one needs to add proper ESD protection, we'll get to something like
300um x 300um, which is about the smallest we could actually
reliably dice out of an 8 inch wafer. But hold your breath while
handling ;-)

But, in the case you mentioned, one would try and get away from the
silicon as soon as possible, up the layer stack. And then capacitance
to the silicon bulk is no longer that much of a problem as the distance
between conductor and silicon is increased roughly by a factor of
thousand. In case this 

Re: [time-nuts] 1 PPS 50-ohm driver

[Bob Camp]

Hi

If our approach was to fabricate an IC totally from scratch for this or that 
application, 
there are a lot of things that could be done. Unfortunately, for most of us, 
doing that
to wire up an output on a board … not so much. 

Starting back in the 1970’s people stopped making packaged inverters with 
single 
transistor pairs. The problem was they didn’t get enough gain or isolation 
through 
a single pair. For the few places that *did* keep making the single pair parts, 
they 
carefully labeled them as such so you would not misuse them. 

Once you get into packaged logic designed in the 80’s or later, “unbuffered” 
gates
pretty much vanish. An inverter is made of three transistor pairs and a “non 
inverter” 
is made from two transistor pairs. The net result is that the “non inverter” is 
slightly 
faster. Again, this does not apply if you make your own chip from scratch on a 
silicon wafer. It only applies if you want to buy pre-packaged parts from 
somebody 
like TI. 

The speed difference is not as great as you might think. The capacitance on the 
internal 
nodes is mighty low. That makes the “internal” inverter very fast compared to 
the rest
of the circuit. 

Of course if you *did* fabricate a single transistor pair on your own, you also 
would need
to invent a way to dice it so that pair was not “swimming” in an ocean of 
un-used silicon. 
The capacitance of all that real estate counts as well …

Lots of Fun.

Bob


> On Apr 18, 2016, at 2:24 PM, Florian Teply  wrote:
> 
> Am Sun, 17 Apr 2016 23:03:11 +0200
> schrieb Gerhard Hoffmann :
> 
>> Am 17.04.2016 um 16:59 schrieb Wojciech Owczarek:
>>> A slightly naive question(s) perhaps, so do excuse me, but I reckon
>>> this is a good opportunity to ask since I am approaching the same
>>> design questions (this is a 1PPS in + 1PPS out driver for the
>>> Beaglebone Black, to/from its PTP clock). This involves 5v / 3.3v
>>> conversion but that's another topic.
>>> 
>>> IC spec sheets are one thing, but since the Time Nuts have seen and
>>> done it all... Why an inverting buffer? Is there an advantage in
>>> using inverted logic for 1PPS? I have come across other timing kit
>>> that internally uses falling edge, which is eventually inverted
>>> when interfacing with the outside world. Is this common, and why?
>>> If my output is rising edge right from the PWM pin I'm using to
>>> generate my 1PPS (again, separate topic), do I gain anything by
>>> inverting it and using an inverting buffer? Is this a matter of
>>> different rise/fall propagation delays over the various ICs?
>>> 
>> 
>> In CMOS logic, an inverter is the smallest and fastest gate, just 2 
>> transistors.
>> A minimum buffer then would be 2 inverters in series. somewhat slower 
>> and 4 transistors.
>> If you need an inverter or buffer that drives a heavy load, you may
>> need more than
>> just 1 minimum transistor pair in parallel. That presents more load
>> to the source,  so
>> one may have to amplify the source signal in several stages. As a
>> rule of thumb,
>> quadrupling the number of transistors per stage gives the best 
>> compromise between
>> delay for heavy loading and delay from many stages. (on-chip)
>> So for any given source/load combination the optimum may be either an 
>> inverting or a
>> non-inverting buffer.
>> 
> Most likely this goes without saying, but as we're addressing a
> question that has been marked as somewhat naive by the poster, I'd
> still like to point a few things out which are not necessarily clear to
> the uninitiated in IC design, especially in CMOS digital core logic.
> And, to be honest, quite often they background is even lost on seasoned
> digital IC design guys because as soon someone implemented a
> digital library, the rest is done on a higher level of abstraction
> using VHDL and the like. If you all know this by heart already, just
> ignore it...
> 
> The reason the simple inverter is the smallest and fastest gate usually
> as already pointed out by Gerhard is essentially due to two reasons:
> a) It indeed only has two transistors. As MOS transistors pose a
> capacitive load to the gate driving it, the more transistors need to be
> driven, the higher the capacitive load. Combined with the fact that
> drive current is limited, higher capacitance leads to longer rise times
> and consequently to longer gate delay.
> b) more complex gates require series connections of transistors. As a
> first order approximation, two transistors in series have twice the
> on-resistance of a single transistor and therefore can source only
> half the current than a single transistor.
> 
>> In CMOS, the falling edge is usually slightly faster than the rising.
>> 
> Just for the sake of completeness, there is no natural law that
> actually calls for this. It just happens, that for the commonly used
> silicon as transistor material, due to the lower hole mobility compared
> to electron mobility, p-type MOS devices have 

Re: [time-nuts] 1 PPS 50-ohm driver

[Wojciech Owczarek]

Florian, Gerhard, All,

Thank you for the extensive answers. Just to think that at some point I
passed exams where I had to implement truth tables in "raw" NMOS/PMOS -
things evaporate quickly enough if you don't refresh, and then years go by
and you wish you had been paying more attention. The moment you mentioned
that a CMOS NOT gate only requires two transistors, it all came back.

As to Beaglebone Black and "use use whatever you have", fine for 1PPS
input, I'm using an SN74AHCT125 for the moment, I may revisit that. But for
the output, I do want the slope to look decent and the signal to be able to
travel over some length of coax, even if not so precise. I am developing a
PTP slave timing probe based on the BBB - you sync it to PTP and take a
reference 1PPS input to compare the phase. Or alternatively, sync time to
GPS + 1PPS, or just phase to 1PPS, and run PTP read-only and report the
observed offset.

The hardware right now is the bare minimum required to get the signals in.
On the software side, for 1PPS input, I am able to stay within the
resolution of the counter used for event capture, which runs at ~24 MHz, so
about +/-40 ns, I'm getting a pretty clean sawtooth. For the 1PPS output,
I'm using a PWM pulse, which is aligned to top of PTP second using a PI
servo (counter overflow generates a PWM pulse and a timestamp at the same
time). PI servo because it's a standalone device and the real frequency can
be unknown. Well, I can experiment with pure correct-and-rearm next, PI was
a quick and lazy solution. Also the PTP clock resolution is 4 ns, so
quantisation error is a problem, more for the output than for the input. I
can't test the quality of the output until this is hooked up to a proper
counter. Well, in fact I can't compensate for the h/w interface delays
either until I run this against a decent scope.

Yet another embedded project, but I will be happy to share the results when
ready. This is definitely not lab-grade stuff, but it is designed to be
used environments where you're aiming for sub-100 us accuracy, so 100 ns is
well enough, and for cheap. BBB is 100 megabit, but the upcoming BBB
Enhanced (third party fork) is gigabit.

Kind regards,
Wojciech
___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Re: [time-nuts] 1 PPS 50-ohm driver

[Florian Teply]

Am Sun, 17 Apr 2016 23:03:11 +0200
schrieb Gerhard Hoffmann :

> Am 17.04.2016 um 16:59 schrieb Wojciech Owczarek:
> > A slightly naive question(s) perhaps, so do excuse me, but I reckon
> > this is a good opportunity to ask since I am approaching the same
> > design questions (this is a 1PPS in + 1PPS out driver for the
> > Beaglebone Black, to/from its PTP clock). This involves 5v / 3.3v
> > conversion but that's another topic.
> >
> > IC spec sheets are one thing, but since the Time Nuts have seen and
> > done it all... Why an inverting buffer? Is there an advantage in
> > using inverted logic for 1PPS? I have come across other timing kit
> > that internally uses falling edge, which is eventually inverted
> > when interfacing with the outside world. Is this common, and why?
> > If my output is rising edge right from the PWM pin I'm using to
> > generate my 1PPS (again, separate topic), do I gain anything by
> > inverting it and using an inverting buffer? Is this a matter of
> > different rise/fall propagation delays over the various ICs?
> >
> 
> In CMOS logic, an inverter is the smallest and fastest gate, just 2 
> transistors.
> A minimum buffer then would be 2 inverters in series. somewhat slower 
> and 4 transistors.
> If you need an inverter or buffer that drives a heavy load, you may
> need more than
> just 1 minimum transistor pair in parallel. That presents more load
> to the source,  so
> one may have to amplify the source signal in several stages. As a
> rule of thumb,
> quadrupling the number of transistors per stage gives the best 
> compromise between
> delay for heavy loading and delay from many stages. (on-chip)
> So for any given source/load combination the optimum may be either an 
> inverting or a
> non-inverting buffer.
> 
Most likely this goes without saying, but as we're addressing a
question that has been marked as somewhat naive by the poster, I'd
still like to point a few things out which are not necessarily clear to
the uninitiated in IC design, especially in CMOS digital core logic.
And, to be honest, quite often they background is even lost on seasoned
digital IC design guys because as soon someone implemented a
digital library, the rest is done on a higher level of abstraction
using VHDL and the like. If you all know this by heart already, just
ignore it...

The reason the simple inverter is the smallest and fastest gate usually
as already pointed out by Gerhard is essentially due to two reasons:
a) It indeed only has two transistors. As MOS transistors pose a
capacitive load to the gate driving it, the more transistors need to be
driven, the higher the capacitive load. Combined with the fact that
drive current is limited, higher capacitance leads to longer rise times
and consequently to longer gate delay.
b) more complex gates require series connections of transistors. As a
first order approximation, two transistors in series have twice the
on-resistance of a single transistor and therefore can source only
half the current than a single transistor.

> In CMOS, the falling edge is usually slightly faster than the rising.
> 
Just for the sake of completeness, there is no natural law that
actually calls for this. It just happens, that for the commonly used
silicon as transistor material, due to the lower hole mobility compared
to electron mobility, p-type MOS devices have approximately half the
saturation current of n-type devices, IF geometry and dimensions are
identical. Usually, this is somewhat offset by different sizing of the
transistors. Often, it is not taken that far that current drive is
actually equal, as, as said above, this would impose higher capacitive
load which again would slow down things. Additionally, higher
capacitance also increases dynamic power consumption in operation as
more charge is stored on the gate which needs to be moved for the
gate to switch. The result of the optimization process happens to be
such that usually, the current drive capability for the PMOS path is
lower than that of the NMOS path, which then leads to the mentioned
sligthly faster falling edges.

In principle, it is perfectly possible to have CMOS core logic where
the falling edge has exactly the same risetime as the rising edge. But
it would need more chip area than the way it usually is done, it would
have higher dynamic power dissipation. There are a few applications,
where the benefit outweighs the drawbacks, but 99% of the users are
fine with the standard logic libraries offered and/or supported by the
foundries.

Hope this clears up a bit the background of why it usually is the way
it is.

Best regards,
Florian
___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Re: [time-nuts] 1 PPS 50-ohm driver

[Magnus Danielson]

Hi,

On 04/18/2016 06:14 AM, Bill Byrom wrote:

For most oscilloscopes with bandwidth no greater than around 1 GHz, the
response is Gaussian with a BT (bandwidth * risetime) product of about
0.35. So a 1 GHz oscilloscope has a risetime of about 350 ps. The 10%-
90% risetime of a series connected system is given by the square root of
the sum of the squares of the individual risetimes.

So if you had a 2 ns risetime pulse measured by a 350 ps (1 GHz BW)
scope, the expected displayed risetime would be:
sqrt( 4 + 0.1225) =  2.03 ns. So the scope bandwidth is unimportant in
this case.


Indeed.


More important is the oscilloscope probe (if used) and/or coaxial cable,
launch into the cable,  and connectors. The slow rise after the initial
edge in your scope image might be due to skin effect losses in the PC
board, coax cable, and/or scope probe (or errors in an uncalibrated
scope). But the rising edge looks great to me.


The slowly rising slope after the transition is complete is a sure 
tell-sign of skin effect. If you have reflections, they would give 
sections of higher/lower voltage and this one looks relatively clean in 
that regard. In practice, as long as you have a clean swift transition 
and no reflections large enough to be interpreted as another transition, 
you are fine. It may look ugly but still work for many digital signals. 
I this regard your transition is very clean.



The problem with fast edges and fast login on the receiving end is that
reflections due to impedance mismatch cause great difficulties. For
example, if the load was a 50 ohm resistor in parallel with 20 pF to
ground, a negative-going reflection would travel back to the source. If
the round-trip propagation delay is 2 ns or less, the reflection will
end up causing a reduced risetime or ringing at the source. Your setup
has a good source match which should keep re-reflection to a minimum, so
there shouldn't be any significant re-reflection problems.


Indeed. Making sure that both source and destination have relatively 
good impedance match is a good way towards clean signals.


Cheers,
Magnus
___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Re: [time-nuts] 1 PPS 50-ohm driver

[Bill Byrom]

For most oscilloscopes with bandwidth no greater than around 1 GHz, the
response is Gaussian with a BT (bandwidth * risetime) product of about
0.35. So a 1 GHz oscilloscope has a risetime of about 350 ps. The 10%-
90% risetime of a series connected system is given by the square root of
the sum of the squares of the individual risetimes.
 
So if you had a 2 ns risetime pulse measured by a 350 ps (1 GHz BW)
scope, the expected displayed risetime would be:
sqrt( 4 + 0.1225) =  2.03 ns. So the scope bandwidth is unimportant in
this case.
 
More important is the oscilloscope probe (if used) and/or coaxial cable,
launch into the cable,  and connectors. The slow rise after the initial
edge in your scope image might be due to skin effect losses in the PC
board, coax cable, and/or scope probe (or errors in an uncalibrated
scope). But the rising edge looks great to me.
 
The problem with fast edges and fast login on the receiving end is that
reflections due to impedance mismatch cause great difficulties. For
example, if the load was a 50 ohm resistor in parallel with 20 pF to
ground, a negative-going reflection would travel back to the source. If
the round-trip propagation delay is 2 ns or less, the reflection will
end up causing a reduced risetime or ringing at the source. Your setup
has a good source match which should keep re-reflection to a minimum, so
there shouldn't be any significant re-reflection problems.
--
Bill Byrom N5BB
(Tektronix Application Engineer)
 
 
 
On Sun, Apr 17, 2016, at 09:11 PM, Stewart Cobb wrote:
> Sorry, newer scopes annotate a little better. Settings were 0.5
> V/div and
> 2
> ns/div. Trigger level is 1.4 V. Scope is HP 54720D with 54712A plugin
> (built in 50-ohm termination). The installed bandwidth of the
> plugin is
> somewhere between 1.0 and 1.5 GHz. I should have mentioned all that in
> the
> previous post.
>
> Cheers!
> --Stu
> _
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to
> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
 
___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Re: [time-nuts] 1 PPS 50-ohm driver

[Hal Murray]

dk...@arcor.de said:
> BTW: Is there a way on the BeagleBoneBlack to map the IO-Pins like an
> ancient data bus? some addresses, data, read, write or so? Something to get
> into an FPGA without much ado, with medium-speed data rates? 

I haven't seen a HOWTO type recipe for that, but I haven't been looking.

The I/O pins in most ARM SOC chips have several uses per pin.  You have to 
get the chip specs to see what your choices are and look at the board 
schematics to see which pins are already used.

For medium speed, you might find that the BBB is already setup for SPI or 
something similar.

There are probably a couple of plain old serial ports.  You might check how 
fast they will run.


-- 
These are my opinions.  I hate spam.



___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Re: [time-nuts] 1 PPS 50-ohm driver

[Stewart Cobb]

Sorry, newer scopes annotate a little better. Settings were 0.5 V/div and 2
ns/div. Trigger level is 1.4 V. Scope is HP 54720D with 54712A plugin
(built in 50-ohm termination). The installed bandwidth of the plugin is
somewhere between 1.0 and 1.5 GHz. I should have mentioned all that in the
previous post.

Cheers!
--Stu
___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Re: [time-nuts] 1 PPS 50-ohm driver

[Gerhard Hoffmann]

Am 17.04.2016 um 16:59 schrieb Wojciech Owczarek:

A slightly naive question(s) perhaps, so do excuse me, but I reckon this is
a good opportunity to ask since I am approaching the same design questions
(this is a 1PPS in + 1PPS out driver for the Beaglebone Black, to/from its
PTP clock). This involves 5v / 3.3v conversion but that's another topic.

IC spec sheets are one thing, but since the Time Nuts have seen and done it
all... Why an inverting buffer? Is there an advantage in using inverted
logic for 1PPS? I have come across other timing kit that internally uses
falling edge, which is eventually inverted when interfacing with the
outside world. Is this common, and why? If my output is rising edge right
from the PWM pin I'm using to generate my 1PPS (again, separate topic), do
I gain anything by inverting it and using an inverting buffer? Is this a
matter of different rise/fall propagation delays over the various ICs?



In CMOS logic, an inverter is the smallest and fastest gate, just 2 
transistors.
A minimum buffer then would be 2 inverters in series. somewhat slower 
and 4 transistors.
If you need an inverter or buffer that drives a heavy load, you may need 
more than
just 1 minimum transistor pair in parallel. That presents more load to 
the source,  so
one may have to amplify the source signal in several stages. As a rule 
of thumb,
quadrupling the number of transistors per stage gives the best 
compromise between

delay for heavy loading and delay from many stages. (on-chip)
So for any given source/load combination the optimum may be either an 
inverting or a

non-inverting buffer.

In CMOS, the falling edge is usually slightly faster than the rising.

In TTL, which is somehow the precursor of CMOS, feeding an input with a 
LOW signal
required more energy than feeding a high. In fact, feeding nothing at 
all was a high,
although that is frowned upon. That led to low-active chip enables and 
write enables

since people expected bigger noise immunity against false triggers.

Use whatever you have for the BBB, it makes no difference. I seem to 
remember
that some signals on the BBB use surprisingly low voltages and it is 
possible to

break it, so check the pins you use.

In my frequency doubler board for the Lucent KS24361 there is also a 
1PPS CMOS

driver since the Lucent has only a RS422 output on a DB9 connector.
It uses 74LVCxxx, that has an abs. max rating of 6.5V, so if you are 
rough enough
you can generate full swing for 3V3 CMOS, serial terminated at the 
source and

parallel terminated at the load. That gives nice waveforms.

In that Lucent board I only had 5V without spending an extra regulator, 
so I accepted
a 2V5 high level. That works for 3V3 CMOS ( nominal switching level 
1.6V) and for

74HCT it's even better.

Fairchild 74LVX has 7V abs.max.

< http://www.hoffmann-hochfrequenz.de/downloads/DoubDist.pdf >
has the circuits and resulting waveforms.

As there was interest in SRDs; Sky and Macom still produce some, IIRC there
is even sth. available at Digikey.

regards, Gerhard

BTW:
Is there a way on the BeagleBoneBlack to map the IO-Pins like an ancient
data bus? some addresses, data, read, write or so? Something to get into
an FPGA without much ado, with medium-speed data rates?




___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Re: [time-nuts] 1 PPS 50-ohm driver

[David C. Partridge]

Or put another way think 4 layer boards with power and ground planes.

Dave

-Original Message-
From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of ed breya
Sent: 17 April 2016 21:04
To: time-nuts@febo.com
Subject: Re: [time-nuts] 1 PPS 50-ohm driver

For high-drive outputs, my favorite is the 74AC541 octal bus driver, which is 
very nice for paralleling outputs through small series Rs. If you look at the 
pinout, you'll see why.

BTW with any of these high-drive circuits, it is essential to provide good 
bypassing of the supplies, and be sure of clean low impedance pathways for the 
signal output and return currents.

Ed
___
time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to 
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Re: [time-nuts] 1 PPS 50-ohm driver

[ed breya]

For high-drive outputs, my favorite is the 74AC541 octal bus driver, 
which is very nice for paralleling outputs through small series Rs. If 
you look at the pinout, you'll see why.


BTW with any of these high-drive circuits, it is essential to provide 
good bypassing of the supplies, and be sure of clean low impedance 
pathways for the signal output and return currents.


Ed
___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Re: [time-nuts] 1 PPS 50-ohm driver

[Bob Camp]

Hi

If the PPS is being generated by an FPGA or a MCU, inverted is as easy to 
generate as
not inverted. Many decades ago an “un buffered” inverter was the speed king. 
These days,
as you have noticed, the difference between inverters and bufferers is not 
significant. For
non-inverting setups the ‘125 and ‘126 gates are normally used.

Bob

> On Apr 17, 2016, at 10:59 AM, Wojciech Owczarek  
> wrote:
> 
> A slightly naive question(s) perhaps, so do excuse me, but I reckon this is
> a good opportunity to ask since I am approaching the same design questions
> (this is a 1PPS in + 1PPS out driver for the Beaglebone Black, to/from its
> PTP clock). This involves 5v / 3.3v conversion but that's another topic.
> 
> IC spec sheets are one thing, but since the Time Nuts have seen and done it
> all... Why an inverting buffer? Is there an advantage in using inverted
> logic for 1PPS? I have come across other timing kit that internally uses
> falling edge, which is eventually inverted when interfacing with the
> outside world. Is this common, and why? If my output is rising edge right
> from the PWM pin I'm using to generate my 1PPS (again, separate topic), do
> I gain anything by inverting it and using an inverting buffer? Is this a
> matter of different rise/fall propagation delays over the various ICs?
> 
> Thanks,
> Wojciech
> 
> -- 
> -
> 
> Wojciech Owczarek
> ___
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.

___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Re: [time-nuts] 1 PPS 50-ohm driver

[Wojciech Owczarek]

A slightly naive question(s) perhaps, so do excuse me, but I reckon this is
a good opportunity to ask since I am approaching the same design questions
(this is a 1PPS in + 1PPS out driver for the Beaglebone Black, to/from its
PTP clock). This involves 5v / 3.3v conversion but that's another topic.

IC spec sheets are one thing, but since the Time Nuts have seen and done it
all... Why an inverting buffer? Is there an advantage in using inverted
logic for 1PPS? I have come across other timing kit that internally uses
falling edge, which is eventually inverted when interfacing with the
outside world. Is this common, and why? If my output is rising edge right
from the PWM pin I'm using to generate my 1PPS (again, separate topic), do
I gain anything by inverting it and using an inverting buffer? Is this a
matter of different rise/fall propagation delays over the various ICs?

Thanks,
Wojciech

-- 
-

Wojciech Owczarek
___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Re: [time-nuts] 1 PPS 50-ohm driver

[wb6bnq]

Hi Douglas,

Blowing up the picture shows some lettering in the white bar at the 
bottom of the display (fairly fuzzy).  It looks like it is saying 2 
volts for the signal with the scope set to 0.5 volts per division.


BillWB6BNQ


Douglas Bercich wrote:


I was looking but can't find a V/div anywhere on that. Maybe my old eyes or not 
enough coffee. 500mV?

 


On Apr 16, 2016, at 11:58 PM, Stewart Cobb  wrote:

Here's a scope photo from a PPS driver built exactly to the description in
my earlier post.  It's a 74ACT04 in a TSSOP package, with five parallel
outputs driving five 220-ohm resistors (0402 SMT) to form a 50-ohm output.

The photo shows 2 ns rise time for the leading edge of the pulse. The scope
bandwidth is around 1 GHz, so this measurement is pushing its limits.  The
pulse looks fairly clean, but with a bit more care in layout and cabling,
it might get even better.

Cheers!
--Stu

___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
   


___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

 



___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Re: [time-nuts] 1 PPS 50-ohm driver

[Douglas Bercich]

I was looking but can't find a V/div anywhere on that. Maybe my old eyes or not 
enough coffee. 500mV?

> On Apr 16, 2016, at 11:58 PM, Stewart Cobb  wrote:
> 
> Here's a scope photo from a PPS driver built exactly to the description in
> my earlier post.  It's a 74ACT04 in a TSSOP package, with five parallel
> outputs driving five 220-ohm resistors (0402 SMT) to form a 50-ohm output.
> 
> The photo shows 2 ns rise time for the leading edge of the pulse. The scope
> bandwidth is around 1 GHz, so this measurement is pushing its limits.  The
> pulse looks fairly clean, but with a bit more care in layout and cabling,
> it might get even better.
> 
> Cheers!
> --Stu
> 
> ___
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Re: [time-nuts] 1 PPS 50-ohm driver

[Bob Camp]

Hi

If the resistors are typical thick film SMT parts, they will begin to have 
issues below
1 GHz. Thin film resistors will get you a bit higher than thick films. In both 
cases board
layout to achieve 1 GHz performance is going to be a challenge. 

All that said, for a 1 PPS output the waveform looks fine. A 5 ns rise time is 
equally 
fine for a 1 pps. The faster edge will bother radios a bit more. Both are 
plenty fast
enough to properly trigger anything you have “down stream” of the device. Since 
faster
than 5 is trivial to do, why not get the faster speed. 

When run through normal lab cables and connectors, the open termination at the 
far end will be
more of an issue than a 2 to 5 ns rise time. Your “got a great deal” cables and 
connectors 
are not perfect into the 100’s of MHz.  If you are completely wired with hard 
line and APC-7’s 
this does not apply to you :)

Bob

> On Apr 17, 2016, at 12:58 AM, Stewart Cobb  wrote:
> 
> Here's a scope photo from a PPS driver built exactly to the description in
> my earlier post.  It's a 74ACT04 in a TSSOP package, with five parallel
> outputs driving five 220-ohm resistors (0402 SMT) to form a 50-ohm output.
> 
> The photo shows 2 ns rise time for the leading edge of the pulse. The scope
> bandwidth is around 1 GHz, so this measurement is pushing its limits.  The
> pulse looks fairly clean, but with a bit more care in layout and cabling,
> it might get even better.
> 
> Cheers!
> --Stu
> ___
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.

___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.