Am 17.04.2016 um 16:59 schrieb Wojciech Owczarek:
A slightly naive question(s) perhaps, so do excuse me, but I reckon this is
a good opportunity to ask since I am approaching the same design questions
(this is a 1PPS in + 1PPS out driver for the Beaglebone Black, to/from its
PTP clock). This involves 5v / 3.3v conversion but that's another topic.
IC spec sheets are one thing, but since the Time Nuts have seen and done it
all... Why an inverting buffer? Is there an advantage in using inverted
logic for 1PPS? I have come across other timing kit that internally uses
falling edge, which is eventually inverted when interfacing with the
outside world. Is this common, and why? If my output is rising edge right
from the PWM pin I'm using to generate my 1PPS (again, separate topic), do
I gain anything by inverting it and using an inverting buffer? Is this a
matter of different rise/fall propagation delays over the various ICs?
In CMOS logic, an inverter is the smallest and fastest gate, just 2
transistors.
A minimum buffer then would be 2 inverters in series. somewhat slower
and 4 transistors.
If you need an inverter or buffer that drives a heavy load, you may need
more than
just 1 minimum transistor pair in parallel. That presents more load to
the source, so
one may have to amplify the source signal in several stages. As a rule
of thumb,
quadrupling the number of transistors per stage gives the best
compromise between
delay for heavy loading and delay from many stages. (on-chip)
So for any given source/load combination the optimum may be either an
inverting or a
non-inverting buffer.
In CMOS, the falling edge is usually slightly faster than the rising.
In TTL, which is somehow the precursor of CMOS, feeding an input with a
LOW signal
required more energy than feeding a high. In fact, feeding nothing at
all was a high,
although that is frowned upon. That led to low-active chip enables and
write enables
since people expected bigger noise immunity against false triggers.
Use whatever you have for the BBB, it makes no difference. I seem to
remember
that some signals on the BBB use surprisingly low voltages and it is
possible to
break it, so check the pins you use.
In my frequency doubler board for the Lucent KS24361 there is also a
1PPS CMOS
driver since the Lucent has only a RS422 output on a DB9 connector.
It uses 74LVCxxx, that has an abs. max rating of 6.5V, so if you are
rough enough
you can generate full swing for 3V3 CMOS, serial terminated at the
source and
parallel terminated at the load. That gives nice waveforms.
In that Lucent board I only had 5V without spending an extra regulator,
so I accepted
a 2V5 high level. That works for 3V3 CMOS ( nominal switching level
1.6V) and for
74HCT it's even better.
Fairchild 74LVX has 7V abs.max.
< http://www.hoffmann-hochfrequenz.de/downloads/DoubDist.pdf >
has the circuits and resulting waveforms.
As there was interest in SRDs; Sky and Macom still produce some, IIRC there
is even sth. available at Digikey.
regards, Gerhard
BTW:
Is there a way on the BeagleBoneBlack to map the IO-Pins like an ancient
data bus? some addresses, data, read, write or so? Something to get into
an FPGA without much ado, with medium-speed data rates?
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