Re: [time-nuts] Unified VCXO Carrier Board

[Bruce Griffiths]

Charles
I have a bunch of LM329's purchased from a large distributor.I guess I should 
make some noise measurements.Some have even been installed in low noise 
regulators.
Another item to add to the to do list( repair mill, complete dual fibre  point 
diffraction interferometer, rebuild RF PN interferometer ).Probably a good 
excuse to build that low noise JFET input preamp with the somewhat unusual 
input coupling architecture.
Bruce


Bruce
 


 On Wednesday, 28 October 2015 6:00 PM, Charles Steinmetz 
 wrote:
   

 Gerhard wrote:

>It's bad, but not that bad.  10 times the voltage is 20 dB more. So
>
>0dB  = 1nV/sqrt Hz
>20 dB = 10 nV
>40 dB = 100 nV
>60 dB = 1uV
>80 dB = 10 uV/sqrt Hz

So I got ~40dB and ~30dB right, but screwed up and turned 10uV into 
1mV.  How'd I do that?

>The wideband noise at, say, 46 dB would be 200 nV/sqrt Hz  versus 
>the claimed 75 nV typical
>but the corner frequency is really bad. I bought them last year from 
>Digi-key, still with
>National as manufacturer on the bag, not TI.
>
>I'll test a few more next weekend.

Even Digi-Key is not immune from counterfeits.  I received some 
counterfeit voltage references last year, but before I used any I got 
a message recalling them.

Thinking on it a bit more, your results look like what one might 
expect if someone put up bandgap reference dice in fake LM329 
packages.  On the other hand, they could be from a lot of real NS 
parts that had serious fab issues or catastrophic storage issues.

In any case, if the others you have are like that one, throw them out 
and get some new ones that meet spec (and just in case, buy from 
another vendor, and perhaps another manufacturer).  You can buy them 
direct from Linear Technology , 
but only in the plastic TO-92 package (all the 329s I've used have 
been in the hermetic package, but those appear to be history now).

Best regards,

Charles


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Re: [time-nuts] Unified VCXO Carrier Board

[Charles Steinmetz]

Gerhard wrote:


It's bad, but not that bad.  10 times the voltage is 20 dB more. So

0dB   = 1nV/sqrt Hz
20 dB = 10 nV
40 dB = 100 nV
60 dB = 1uV
80 dB = 10 uV/sqrt Hz


So I got ~40dB and ~30dB right, but screwed up and turned 10uV into 
1mV.  How'd I do that?


The wideband noise at, say, 46 dB would be 200 nV/sqrt Hz  versus 
the claimed 75 nV typical
but the corner frequency is really bad. I bought them last year from 
Digi-key, still with

National as manufacturer on the bag, not TI.

I'll test a few more next weekend.


Even Digi-Key is not immune from counterfeits.  I received some 
counterfeit voltage references last year, but before I used any I got 
a message recalling them.


Thinking on it a bit more, your results look like what one might 
expect if someone put up bandgap reference dice in fake LM329 
packages.  On the other hand, they could be from a lot of real NS 
parts that had serious fab issues or catastrophic storage issues.


In any case, if the others you have are like that one, throw them out 
and get some new ones that meet spec (and just in case, buy from 
another vendor, and perhaps another manufacturer).  You can buy them 
direct from Linear Technology , 
but only in the plastic TO-92 package (all the 329s I've used have 
been in the hermetic package, but those appear to be history now).


Best regards,

Charles


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Re: [time-nuts] Unified VCXO Carrier Board

[Charles Steinmetz]

Bruce wrote:

I have a bunch of LM329's purchased from a large distributor.I guess 
I should make some noise measurements.Some have even been installed 
in low noise regulators.


I'd think if you used LM329s as bad as the ones Gerhard tested in 
sensitive circuits, it would have been obvious on testing.


The probability that you receive genuine parts is much higher if you 
buy from a major distributor (for many parts, including almost all 
hard-to-find semiconductors, if you buy on ebay the probability 
approaches zero very closely).  But big distributors are not immune 
from the problem.


I sometimes buy ten-turn WW potentiometers from China that purport to 
be Bourns 3590S parts but are, in fact, counterfeit, right down to 
the molded-in "Made in Mexico" legend.  I have to throw away about 
25% of them, but even so I get ten for the price of one genuine, 
made-in-Mexico Bourns and the selected ones are good enough for many 
applications.  I will not use counterfeit semiconductors, because 
invariably the very specs that you want the part for are the ones it 
doesn't meet (which means that after many attempts I no longer buy 
semiconductors on ebay, EVER, from ANYBODY).


Best regards,

Charles


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Re: [time-nuts] Unified VCXO Carrier Board

[Charles Steinmetz]

Gerhard wrote:


Since the LM329 was mentioned above, I tried it also. Another surprise.
HOW CAN THEY MAKE SUCH A NOISY SUBSURFACE ZENER???

0 dB = 1nV/sqrt Hz


The datasheet for both NS and LT LM329s shows broadband noise of 
<70nV/sqrtHz, with a corner at ~100Hz, rising to a touch over 
100nV/sqrtHz at 10Hz.  That is consistent with the LM329s I have used.


So, according to the datasheet, the 10Hz noise ought to be a touch 
above 40dB on your graph and the curve should level off above 100Hz 
at about 30dB -- if I have done my dBs right.  Still somewhat higher 
than most of the other diodes you tested, but not outlandishly so.


Your data seems to be *much* worse than this, with a 1/f noise corner 
at ~10kHz (!!), rising to what appears to be about 1mV/sqrtHz (!!) at 
10Hz.  Is it possible you got fakes?  (I know someone who bought a 
quantity of LTZ1000s that turned out to be fakes.  Not just abused 
parts dismounted with a blowtorch and with new leads welded on -- 
actual, never-were-real-LTZ1000s.  And they came from a second-tier 
distributor, not an ebay scammer, although further investigation 
revealed that the distributor had been dropped by LT some time 
prior.)  Or is the one you tried just broken?  In any case, the 
results you obtained are several orders of magnitude worse than the 
specs for the part.



Are there differences between Fairchild and Motorola?  [MPSH81/MMBTH81]


Probably, although I don't know if any differences there are would 
have a noticeable effect on the performance of the circuit.  My 
current stock of H81s is all Fairchild.  I know I have used Motorolas 
in the past, and never had any reason to question whether there was a 
significant difference -- but I never compared them side-by-side, 
either.  But I don't think that Motorola/ONsemi has made them for a 
long time, anyway.  Indeed, I see now that even the Fairchild 
through-hole part (MPSH81) seems to be gone.  The SMD part (MMBTH81) 
seems to be available still.


Best regards,

Charles


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Re: [time-nuts] Unified VCXO Carrier Board

[Gerhard Hoffmann]

Am 27.10.2015 um 13:50 schrieb Charles Steinmetz:

Gerhard wrote:


Since the LM329 was mentioned above, I tried it also. Another surprise.
HOW CAN THEY MAKE SUCH A NOISY SUBSURFACE ZENER???

0 dB = 1nV/sqrt Hz


The datasheet for both NS and LT LM329s shows broadband noise of 
<70nV/sqrtHz, with a corner at ~100Hz, rising to a touch over 
100nV/sqrtHz at 10Hz.  That is consistent with the LM329s I have used. 
So, according to the datasheet, the 10Hz noise ought to be a touch 
above 40dB on your graph and the curve should level off above 100Hz at 
about 30dB -- if I have done my dBs right. Still somewhat higher than 
most of the other diodes you tested, but not outlandishly so.


Your data seems to be *much* worse than this, with a 1/f noise corner 
at ~10kHz (!!), rising to what appears to be about 1mV/sqrtHz (!!) at 
10Hz.  Is it possible you got fakes?  (I know someone who 


It's bad, but not that bad.  10 times the voltage is 20 dB more. So

0dB   = 1nV/sqrt Hz
20 dB = 10 nV
40 dB = 100 nV
60 dB = 1uV
80 dB = 10 uV/sqrt Hz

The wideband noise at, say, 46 dB would be 200 nV/sqrt Hz  versus the 
claimed 75 nV typical
but the corner frequency is really bad. I bought them last year from 
Digi-key, still with

National as manufacturer on the bag, not TI.

I'll test a few more next weekend.

regards, Gerhard



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Re: [time-nuts] Unified VCXO Carrier Board

[Gerhard Hoffmann]

Am 24.10.2015 um 22:21 schrieb Bruce Griffiths:

On Saturday, October 24, 2015 09:03:21 AM Charles Steinmetz wrote:

The spec sheet says both TimePod inputs accept -5 to +20dBm into 50
ohms.  -5dBm is less than 0.4Vp-p, which requires less than +/-4mA
from the source, so a 0-5v comparator output feeding a
capacitor and a 560 ohm series resistor should work fine as long as
the comparator can source and sink at least 4mA.

The fly in the ointment is that with such low level inputs (the LTC6957-4
evaluation board will deliver +4dBm into 50 ohm) the Timepod phase noise
floor is uncomfortably close to the phase noise floor of the LTC6957.

Alternatively, a 0-5v comparator output could be buffered with three
'AC04 inverters in parallel, or an 'AC line driver -- but that adds s
the PN of the gates.


Not if one uses a pair of drivers one to drive the Timepod Ch0 input and
one to drive the Timepod CH2 input.
...
It would perhaps be useful to measure the PN characteristics of several
comparators and other sine to square converter circuits using a Timepod
or equivalent.


For the sake of repeatability, could we agree on a common setup?
Timepod would be ok for me. Levels, sources, filters, splitters...

regards, Gerhard


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Re: [time-nuts] Unified VCXO Carrier Board

[Neil Schroeder]

I would be pleased to contribute a 100 MHz wenzel onyx for testing if
that'd be of value. I don't see myself getting to it anytime soon and this
project directly benefits almost half the things on my "never to do but
wish I could" list
On Sun, Oct 25, 2015 at 7:00 PM Bruce Griffiths 
wrote:

> On Sunday, October 25, 2015 09:21:02 AM Charles Steinmetz wrote:
> > I wrote:
> > >>According to the simulation, the resistor has no effect on the output
> > >>amplitude until it is well below 1k ohms
> >
> > Bruce replied:
> > >even 10k increases the output signal amplitude by 130mV or 2.6%.
> > >However that is smaller than the tilt/sag in the high level output due
> to
> > >feedthrough via Cbe of the input transistor when it is off.
> >
> > Bruce is correct, although I don't consider 130mV to be a significant
> > effect on a 5v logic level.  My fault, I guess, for saying "no"
> > effect instead of "no significant" or "no material" effect.
> >
> > But, do we really need to dispute every insignificant, niggling
> > little detail like this?  Even in science, there must be *some*
> > allowance for the use of everyday language instead of requiring
> > absolute explicit clarification of every possible point, or all
> > communications would be unbearably tedious from all of the
> > qualifications.  I say this as someone who is often criticized for
> > overclarifying to the point of being pedantic and tedious.
> >
> > There was simply no need, nor excuse, for the prior (incorrect)
> > suggestion that a resistor to ground from Point "A" would not be
> > effective in canceling the small asymmetry of the circuit, OR for the
> > suggestion that such a resistor would be a useful means to adjust the
> > output amplitude (this because of (i) the concomitant ill effect on
> > symmetry and (ii) the much more direct and efficacious means of
> > achieving the result by adjusting R6 or R1 and R2).
> >
> > Best regards,
> >
> > Charles
> >
> >
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> > instructions there.
> Charles
>
> There was no such suggestion, merely  a note that the amplitude was also
> affected by this. This effect is important in that its probably advisable
> to
> ensure that the input protection diodes of any gate being driven by the
> output don't enter into conduction (I discovered that at least for the
> 74HC04 that the propagation delay jitter increased dramatically once the
> input protection diodes began to conduct). Thus an increase in output
> amplitude by a few hundred mV could be detrimental to the performance
> of the driven logic device.
>
> Whilst the symmetry adjustment effect is real its actually achieved by
> adjusting the ratio of the emitter currents of the 2 transistors (its not a
> threshold effect due to Vbe changes -they are too small but an adjustment
> of the differential switching delays of the 2 transistors).
> Consequently adjusting the ratio of emitter currents of Q1 and Q2 is best
> made via a pot (200 ohm??) connected between the upper ends of R1 and
> R2 (reduce R1 and R2 to 910 ohm) with its wiper connected to the C5, C6,
> C7, R7 node.
> Adjusting the wiper position has very little effect (tens of mV) on the
> output amplitude whilst allowing adequate range of adjustment of the
> output signal duty cycle.
>
> Adjusting the value of R6 can be counter productive in that it spoils the
> match to a 50 ohm load achieved via simple 2:1 (turns ratio) stepdown RF
> transformer for the purposes of measuring the PN of the circuit.
>
> Bruce
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Re: [time-nuts] Unified VCXO Carrier Board

[Gerhard Hoffmann]

Am 23.10.2015 um 21:27 schrieb Charles Steinmetz:


Use medium-speed transistors, bias both bases from the same low-noise 
voltage reference such as an LM329, capacitively couple the emitters, 
and use a higher supply voltage, for starters.  I use 
This evening, I have measured some oh so noisy zeners and was pleasantly 
surprised.

Other than one 40+ year old glass diode all of them were pretty low noise.

Since the LM329 was mentioned above, I tried it also. Another surprise.
HOW CAN THEY MAKE SUCH A NOISY SUBSURFACE ZENER???

Bias for the DUTs was a 1K wire resistor from 10 NiMH cells. The bias 
source does not
add any visible noise. The "shorted" trace shows the noise floor of the 
system. That is
about 220 pV/sqrt Hz.  FFT analyzer is an Agilent 89441A. It has strong 
1/f noise that is

barely hidden by the preamp. 0 dB = 1nV/sqrt Hz

MPSH81/MMBTH81s and a power supply of around 20v (see attached 
schematic) for a reasonably 
optimized implementation.  Other transistors can be used, but I've 
found that the H81s work better for squaring 1-10MHz sine waves than 
anything else I've tried -- they hit the sweet spot of the 
bandwidth/gain tradeoff and have a nice flat gain vs. current 
characteristic.


Are there differences between Fairchild and Motorola?

regards, Gerhard

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Re: [time-nuts] Unified VCXO Carrier Board

[Bruce Griffiths]

On Sunday, October 25, 2015 11:56:13 PM Gerhard Hoffmann wrote:
> Am 24.10.2015 um 22:21 schrieb Bruce Griffiths:
> > On Saturday, October 24, 2015 09:03:21 AM Charles Steinmetz wrote:
> >> The spec sheet says both TimePod inputs accept -5 to +20dBm into 
50
> >> ohms.  -5dBm is less than 0.4Vp-p, which requires less than +/-4mA
> >> from the source, so a 0-5v comparator output feeding a
> >> capacitor and a 560 ohm series resistor should work fine as long as
> >> the comparator can source and sink at least 4mA.
> > 
> > The fly in the ointment is that with such low level inputs (the LTC6957-4
> > evaluation board will deliver +4dBm into 50 ohm) the Timepod phase 
noise
> > floor is uncomfortably close to the phase noise floor of the LTC6957.
> > 
> >> Alternatively, a 0-5v comparator output could be buffered with three
> >> 'AC04 inverters in parallel, or an 'AC line driver -- but that adds s
> >> the PN of the gates.
> > 
> > Not if one uses a pair of drivers one to drive the Timepod Ch0 input 
and
> > one to drive the Timepod CH2 input.
> > 
> > It would perhaps be useful to measure the PN characteristics of 
several
> > comparators and other sine to square converter circuits using a 
Timepod
> > or equivalent.
> 
> For the sake of repeatability, could we agree on a common setup?
> Timepod would be ok for me. Levels, sources, filters, splitters...
> 
> regards, Gerhard
> 
> 
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Gerhard

I'll start another thread on this initially detailing how I measured the PN of 
the LT6957-4.

Bruce
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Re: [time-nuts] Unified VCXO Carrier Board

[Bruce Griffiths]

On Sunday, October 25, 2015 09:21:02 AM Charles Steinmetz wrote:
> I wrote:
> >>According to the simulation, the resistor has no effect on the output
> >>amplitude until it is well below 1k ohms
> 
> Bruce replied:
> >even 10k increases the output signal amplitude by 130mV or 2.6%.
> >However that is smaller than the tilt/sag in the high level output due to
> >feedthrough via Cbe of the input transistor when it is off.
> 
> Bruce is correct, although I don't consider 130mV to be a significant
> effect on a 5v logic level.  My fault, I guess, for saying "no"
> effect instead of "no significant" or "no material" effect.
> 
> But, do we really need to dispute every insignificant, niggling
> little detail like this?  Even in science, there must be *some*
> allowance for the use of everyday language instead of requiring
> absolute explicit clarification of every possible point, or all
> communications would be unbearably tedious from all of the
> qualifications.  I say this as someone who is often criticized for
> overclarifying to the point of being pedantic and tedious.
> 
> There was simply no need, nor excuse, for the prior (incorrect)
> suggestion that a resistor to ground from Point "A" would not be
> effective in canceling the small asymmetry of the circuit, OR for the
> suggestion that such a resistor would be a useful means to adjust the
> output amplitude (this because of (i) the concomitant ill effect on
> symmetry and (ii) the much more direct and efficacious means of
> achieving the result by adjusting R6 or R1 and R2).
> 
> Best regards,
> 
> Charles
> 
> 
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> time-nuts mailing list -- time-nuts@febo.com
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> https://www.febo.com/cgi-in/mailman/listinfo/time-nuts and follow the
> instructions there.
Charles

There was no such suggestion, merely  a note that the amplitude was also 
affected by this. This effect is important in that its probably advisable to 
ensure that the input protection diodes of any gate being driven by the 
output don't enter into conduction (I discovered that at least for the 
74HC04 that the propagation delay jitter increased dramatically once the 
input protection diodes began to conduct). Thus an increase in output 
amplitude by a few hundred mV could be detrimental to the performance 
of the driven logic device.

Whilst the symmetry adjustment effect is real its actually achieved by 
adjusting the ratio of the emitter currents of the 2 transistors (its not a 
threshold effect due to Vbe changes -they are too small but an adjustment 
of the differential switching delays of the 2 transistors).
Consequently adjusting the ratio of emitter currents of Q1 and Q2 is best 
made via a pot (200 ohm??) connected between the upper ends of R1 and 
R2 (reduce R1 and R2 to 910 ohm) with its wiper connected to the C5, C6, 
C7, R7 node.
Adjusting the wiper position has very little effect (tens of mV) on the 
output amplitude whilst allowing adequate range of adjustment of the 
output signal duty cycle.

Adjusting the value of R6 can be counter productive in that it spoils the 
match to a 50 ohm load achieved via simple 2:1 (turns ratio) stepdown RF 
transformer for the purposes of measuring the PN of the circuit.

Bruce 
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Re: [time-nuts] Unified VCXO Carrier Board

[Charles Steinmetz]

I wrote:


According to the simulation, the resistor has no effect on the output
amplitude until it is well below 1k ohms


Bruce replied:


even 10k increases the output signal amplitude by 130mV or 2.6%.
However that is smaller than the tilt/sag in the high level output due to
feedthrough via Cbe of the input transistor when it is off.


Bruce is correct, although I don't consider 130mV to be a significant 
effect on a 5v logic level.  My fault, I guess, for saying "no" 
effect instead of "no significant" or "no material" effect.


But, do we really need to dispute every insignificant, niggling 
little detail like this?  Even in science, there must be *some* 
allowance for the use of everyday language instead of requiring 
absolute explicit clarification of every possible point, or all 
communications would be unbearably tedious from all of the 
qualifications.  I say this as someone who is often criticized for 
overclarifying to the point of being pedantic and tedious.


There was simply no need, nor excuse, for the prior (incorrect) 
suggestion that a resistor to ground from Point "A" would not be 
effective in canceling the small asymmetry of the circuit, OR for the 
suggestion that such a resistor would be a useful means to adjust the 
output amplitude (this because of (i) the concomitant ill effect on 
symmetry and (ii) the much more direct and efficacious means of 
achieving the result by adjusting R6 or R1 and R2).


Best regards,

Charles


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Re: [time-nuts] Unified VCXO Carrier Board

[David C. Partridge]

All, 

I wish that people had said that the ADCMP600 was a mediocre comparator when I 
designed the board - I’d have used a better one!

I can't find the post about the design and die level issues in a quick search 
(I've been off line for a few weeks).

Bruce,

I couldn't find your post about your measurements of my board for the same 
reason.

Regards,
David Partridge 
-Original Message-
From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of Charles 
Steinmetz
Sent: 24 October 2015 14:03
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Unified VCXO Carrier Board

Bruce wrote:

>The comparator circuit measured was the front end of David Partridge's 
>divider. I merely measured the 10MHz output.

The MAX999 and ADCMP600 are the two comparator options noted on David's 
schematic.  Both parts suffer from a number of the design and die-level issues 
I noted in my previous message, and I have never obtained particularly good PN 
with either one.  Also, even the relatively direct path to the 10MHz output 
goes through two 'AC04 inverters and an 'AC541 line driver, which contribute 
additional PN.

>One thing that I have found is that at low offset frequencies the 
>measured PN is substantially reduced when air currents and other 
>sources of thermal fluctuations are reduced. Even the effect of a thin 
>piece of paper used as an air current shield can be easily seen.
>With careful shielding from thermal fluctuations I measure the low 
>frequency offset PN to be substantially lower than the datasheet values.
>I've seen this effect with everything for which I've measured the PN.

Agreed.  Whether or not it is explicitly stated, I take "all circuitry to be 
enclosed and protected from drafts, and allowed to stabilize thermally before 
testing" as a given with any sensitive time or voltage circuit.

>One problem with comparators when attempting to measure their PN is 
>that they don't have sufficient output to drive the TimePod input directly.
>An amplifier is required.

The spec sheet says both TimePod inputs accept -5 to +20dBm into 50 ohms.  
-5dBm is less than 0.4Vp-p, which requires less than +/-4mA from the source, so 
a 0-5v comparator output feeding a coupling capacitor and a 560 ohm series 
resistor should work fine as long as the comparator can source and sink at 
least 4mA.

Alternatively, a 0-5v comparator output could be buffered with three
'AC04 inverters in parallel, or an 'AC line driver -- but that adds the PN of 
the gates.

>A resistor from point A to ground in the Wenzel style shaper you 
>attached has little effect on the output symmetry due to C4.

It has just enough effect to correct the very small (<1%) asymmetry due to the 
unbalanced drive.  (With no resistor at Point A, the duty cycle is ~51%/49% 
high/low.)

>However it does allow the output amplitude to be adjusted.

According to the simulation, the resistor has no effect on the output amplitude 
until it is well below 1k ohms (at 1k ohm, the symmetry has been WAY 
overcompensated and the duty cycle is ~45%/55% high/low.

Best regards,

Charles


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Re: [time-nuts] Unified VCXO Carrier Board

[Charles Steinmetz]

Bruce wrote:


The comparator circuit measured was the front end of David Partridge's
divider. I merely measured the 10MHz output.


The MAX999 and ADCMP600 are the two comparator options noted on 
David's schematic.  Both parts suffer from a number of the design and 
die-level issues I noted in my previous message, and I have never 
obtained particularly good PN with either one.  Also, even the 
relatively direct path to the 10MHz output goes through two 'AC04 
inverters and an 'AC541 line driver, which contribute additional PN.



One thing that I have found is that at low offset frequencies the measured
PN is substantially reduced when air currents and other sources of thermal
fluctuations are reduced. Even the effect of a thin piece of paper used as
an air current shield can be easily seen.
With careful shielding from thermal fluctuations I measure the low
frequency offset PN to be substantially lower than the datasheet values.
I've seen this effect with everything for which I've measured the PN.


Agreed.  Whether or not it is explicitly stated, I take "all 
circuitry to be enclosed and protected from drafts, and allowed to 
stabilize thermally before testing" as a given with any sensitive 
time or voltage circuit.



One problem with comparators when attempting to measure their PN is
that they don't have sufficient output to drive the TimePod input directly.
An amplifier is required.


The spec sheet says both TimePod inputs accept -5 to +20dBm into 50 
ohms.  -5dBm is less than 0.4Vp-p, which requires less than +/-4mA 
from the source, so a 0-5v comparator output feeding a coupling 
capacitor and a 560 ohm series resistor should work fine as long as 
the comparator can source and sink at least 4mA.


Alternatively, a 0-5v comparator output could be buffered with three 
'AC04 inverters in parallel, or an 'AC line driver -- but that adds 
the PN of the gates.



A resistor from point A to ground in the Wenzel style shaper you attached
has little effect on the output symmetry due to C4.


It has just enough effect to correct the very small (<1%) asymmetry 
due to the unbalanced drive.  (With no resistor at Point A, the duty 
cycle is ~51%/49% high/low.)



However it does allow the output amplitude to be adjusted.


According to the simulation, the resistor has no effect on the output 
amplitude until it is well below 1k ohms (at 1k ohm, the symmetry has 
been WAY overcompensated and the duty cycle is ~45%/55% high/low.


Best regards,

Charles


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Re: [time-nuts] Unified VCXO Carrier Board

[Charles Steinmetz]

The schematic I posted yesterday of the optimized Wenzel-style 
squarer did not specify capacitor types for C1, C3, and C4.  All 
three should be C0G/NP0, and C4 *must* be C0G/NP0.  The attached 
schematic is revised accordingly.


Best regards,

Charles
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Re: [time-nuts] Unified VCXO Carrier Board

[Hal Murray]

csteinm...@yandex.com said:
> The schematic I posted yesterday of the optimized Wenzel-style  squarer did
> not specify capacitor types for C1, C3, and C4.  All  three should be C0G/
> NP0, and C4 *must* be C0G/NP0. 

What property of those capicitors is important in that circuit?



-- 
These are my opinions.  I hate spam.



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Re: [time-nuts] Unified VCXO Carrier Board

[Charles Steinmetz]

Hal wrote:


What property of those capicitors is important in that circuit?


For C4, dielectric absorption, voltage coefficient, tempco, and 
dissipation factor.


For C3, tempco, voltage coefficient, and dissipation factor.

For C2 and C1, best design practices.

Best regards,

Charles


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Re: [time-nuts] Unified VCXO Carrier Board

[Bruce Griffiths]

On Saturday, October 24, 2015 09:03:21 AM Charles Steinmetz wrote:
> Bruce wrote:
> >The comparator circuit measured was the front end of David 
Partridge's
> >divider. I merely measured the 10MHz output.
> 
> The MAX999 and ADCMP600 are the two comparator options noted on
> David's schematic.  Both parts suffer from a number of the design and
> die-level issues I noted in my previous message, and I have never
> obtained particularly good PN with either one.  Also, even the
> relatively direct path to the 10MHz output goes through two 'AC04
> inverters and an 'AC541 line driver, which contribute additional PN.
> 
> >One thing that I have found is that at low offset frequencies the 
measured
> >PN is substantially reduced when air currents and other sources of 
thermal
> >fluctuations are reduced. Even the effect of a thin piece of paper used 
as
> >an air current shield can be easily seen.
> >With careful shielding from thermal fluctuations I measure the low
> >frequency offset PN to be substantially lower than the datasheet 
values.
> >I've seen this effect with everything for which I've measured the PN.
> 
> Agreed.  Whether or not it is explicitly stated, I take "all
> circuitry to be enclosed and protected from drafts, and allowed to
> stabilize thermally before testing" as a given with any sensitive
> time or voltage circuit.
> 
> >One problem with comparators when attempting to measure their PN is
> >that they don't have sufficient output to drive the TimePod input 
directly.
> >An amplifier is required.
> 
> The spec sheet says both TimePod inputs accept -5 to +20dBm into 50
> ohms.  -5dBm is less than 0.4Vp-p, which requires less than +/-4mA
> from the source, so a 0-5v comparator output feeding a
> capacitor and a 560 ohm series resistor should work fine as long as
> the comparator can source and sink at least 4mA.
The fly in the ointment is that with such low level inputs (the LTC6957-4 
evaluation board will deliver +4dBm into 50 ohm) the Timepod phase noise 
floor is uncomfortably close to the phase noise floor of the LTC6957.
> 
> Alternatively, a 0-5v comparator output could be buffered with three
> 'AC04 inverters in parallel, or an 'AC line driver -- but that adds s
> the PN of the gates.
> 
Not if one uses a pair of drivers one to drive the Timepod Ch0 input and 
one to drive the Timepod CH2 input.
> >A resistor from point A to ground in the Wenzel style shaper you 
attached
> >has little effect on the output symmetry due to C4.
> 
> It has just enough effect to correct the very small (<1%) asymmetry
> due to the unbalanced drive.  (With no resistor at Point A, the duty
> cycle is ~51%/49% high/low.)
> 
> >However it does allow the output amplitude to be adjusted.
> 
> According to the simulation, the resistor has no effect on the output
> amplitude until it is well below 1k ohms (at 1k ohm, the symmetry has
> been WAY overcompensated and the duty cycle is ~45%/55% high/low.
> 
Not true even 10k increases the output signal amplitude by 130mV or 
2.6%.
However that is smaller than the tilt/sag in the high level output due to 
feedthrough via Cbe of the input transistor when it is off.
> Best regards,
> 
> Charles
> 
It would perhaps be useful to measure the PN characteristics of several 
comparators and other sine to square converter circuits using a Timepod 
or equivalent.


Bruce
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Re: [time-nuts] Unified VCXO Carrier Board

[Charles Steinmetz]

Bruce wrote:

Your statement about the PN of comparators conflicts with my 
measurements. The LTC6957 evaluation board had an 18dBc/Hz lower 
phase noise floor than a comparator circuit with 10MHz 15dBm inputs. 
However I only measured a single comparator circuit. The Holzworth 
sine to CMOS converter had a comparable PN to the LTC6957-4.
I haven't, as yet measured the PN of an optimised Wenzel circuit.My 
setup for this measurement had a PN floor of around -180dBc/Hz.


There are many, many ways of getting unnecessarily poor PN 
performance from comparators (including Wenzel-style squarers) -- one 
has to make sure not to make any of myriad mistakes in both design 
and execution.  You didn't say which comparator you tried, or in what 
circuit, so I'm not in a position to suggest things to check (or to 
confirm that the comparator you tried performs similarly poorly in my 
tests, if that is the case).


One sanity check you can try -- disable the filtering on your 6957 
eval board.  According to the LT data presented in the chart I 
posted, which agrees very closely with my test results, at 
10MHz/15dBm there should be essentially no change in the PN compared 
to the results you obtained with filtering enabled.  If you see a 
significant difference, then something is causing anomalous results.


Best regards,

Charles


ps.  You often respond to one message by replying to a different 
message, as you did in this case.  It would be helpful for someone 
who just joins a thread, and for continuity in general, if you would 
reply to the message to which you are actually responding.  That way, 
readers who are new to the thread will have the context they need, 
and your interlocutor will have his or her previous message 
conveniently available to refer to in any further message.





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Re: [time-nuts] Unified VCXO Carrier Board

[Bob Camp]

Hi

There are a wide range of OCXO’s listed for this project. I certainly
do not have a sample of ever single one of them. For the ones that 
I *do* have samples of, a properly done CMOS gate sine to square
converter will not degrade the close in phase noise or ADEV of the OCXO.
Based on TimePod measurements, I believe it would be adequate for 
all the ones I’ve seen specs for. 

With far removed phase noise spec’d into the “past 180 dbc/Hz” range on
some parts - no logic is going to handle that. Since the CPLD on the board
will floor out well before that, doing a “perfect” conversion and then degrading
it as soon as you hit the bulk logic does not make a lot of sense. 

Bob

> On Oct 23, 2015, at 5:31 AM, Charles Steinmetz  wrote:
> 
> Bruce wrote:
> 
>> Your statement about the PN of comparators conflicts with my measurements. 
>> The LTC6957 evaluation board had an 18dBc/Hz lower phase noise floor than a 
>> comparator circuit with 10MHz 15dBm inputs. However I only measured a single 
>> comparator circuit. The Holzworth sine to CMOS converter had a comparable PN 
>> to the LTC6957-4.
>> I haven't, as yet measured the PN of an optimised Wenzel circuit.My setup 
>> for this measurement had a PN floor of around -180dBc/Hz.
> 
> There are many, many ways of getting unnecessarily poor PN performance from 
> comparators (including Wenzel-style squarers) -- one has to make sure not to 
> make any of myriad mistakes in both design and execution.  You didn't say 
> which comparator you tried, or in what circuit, so I'm not in a position to 
> suggest things to check (or to confirm that the comparator you tried performs 
> similarly poorly in my tests, if that is the case).
> 
> One sanity check you can try -- disable the filtering on your 6957 eval 
> board.  According to the LT data presented in the chart I posted, which 
> agrees very closely with my test results, at 10MHz/15dBm there should be 
> essentially no change in the PN compared to the results you obtained with 
> filtering enabled.  If you see a significant difference, then something is 
> causing anomalous results.
> 
> Best regards,
> 
> Charles
> 
> 
> ps.  You often respond to one message by replying to a different message, as 
> you did in this case.  It would be helpful for someone who just joins a 
> thread, and for continuity in general, if you would reply to the message to 
> which you are actually responding.  That way, readers who are new to the 
> thread will have the context they need, and your interlocutor will have his 
> or her previous message conveniently available to refer to in any further 
> message.
> 
> 
> 
> 
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Re: [time-nuts] Unified VCXO Carrier Board

[Bruce Griffiths]

On Friday, October 23, 2015 03:27:39 PM Charles Steinmetz wrote:
> Gerhard wrote:
> >What do you consider a run-of-the-mill comparator? LM139, LMV7219,
> >AD8561, ADCMP580?
> 
> For squaring 1-10MHz sine waves, the LT1719 and 1720 are the best
> that I've found.  This is a matter of how much internal hysteresis
> the comparator has, how smoothly the internal hysteresis acts, how
> much gain the part has and how it is structured, how fast it is (both
> risetime and propagation delay), whether it suffers from thermal
> feedback from the output stage to the input stage, how much internal
> ground bounce it has, and a host of other die-level issues.
> 
> The LT1719 uses bipolar input supplies, so ground can be the
> reference voltage and also be in the center of the input common-mode
> range.  This is always quieter than biasing the inputs to the middle
> of a single supply, which is usually done with the 1720 and many
> other comparators.  (Like other single-supply comparators, the 1720
> will work referenced to ground with only a positive supply -- but (i)
> the inputs are then at the very edge of the input common-mode range,
> and (ii) you can only drive the input 100mV below ground, so you have
> to figure out how to clamp the input signal.  It is much easier to
> just use an LT1719 with +/-5v on the input stage, and it works better, 
too.)
> 
> Page 22 of the LT1719 datasheet shows the simplest possible circuit
> and discusses its performance.
> 
> >What optimizations?  I have seen the "Wenzel" circuit in cheapish
> >frequency counter inputs in
> >the late seventies, maybe with a diode bridge added as input 
protection..
> 
> Use medium-speed transistors, bias both bases from the same low-noise
> voltage reference such as an LM329, capacitively couple the emitters,
> and use a higher supply voltage, for starters.  I use MPSH81/MMBTH81s
> and a power supply of around 20v (see attached schematic) for a
> reasonably optimized implementation.  Other transistors can be used,
> but I've found that the H81s work better for squaring 1-10MHz sine
> waves than anything else I've tried -- they hit the sweet spot of the
> bandwidth/gain tradeoff and have a nice flat gain vs. current
> characteristic.
> >so it shows that one can replace filtering by signal power :-)
> 
> It's a matter of the slew rate of the input sine wave at
> zero-cross.  Once you reach the critical slew rate for any particular
> input architecture, the comparator is hard-switched fast enough that
> it doesn't spend significant time in the linear region generating noise.
> 
> >Any objections against the AD9901 phase comparator?
> 
> That should work fine.
> 
> Best regards,
> 
> Charles
Charles

A resistor from point A to ground in the Wenzel style shaper you attached 
has little effect on the output symmetry due to C4. However it does allow 
the output amplitude to be adjusted.

Bruce
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Re: [time-nuts] Unified VCXO Carrier Board

[Bruce Griffiths]

On Friday, October 23, 2015 05:31:46 AM Charles Steinmetz wrote:
> Bruce wrote:
> >Your statement about the PN of comparators conflicts with my
> >measurements. The LTC6957 evaluation board had an 18dBc/Hz lower
> >phase noise floor than a comparator circuit with 10MHz 15dBm inputs.
> >However I only measured a single comparator circuit. The Holzworth
> >sine to CMOS converter had a comparable PN to the LTC6957-4.
> >I haven't, as yet measured the PN of an optimised Wenzel circuit.My
> >setup for this measurement had a PN floor of around -180dBc/Hz.
> 
> There are many, many ways of getting unnecessarily poor PN
> performance from comparators (including Wenzel-style squarers) -- one
> has to make sure not to make any of myriad mistakes in both design
> and execution.  You didn't say which comparator you tried, or in what
> circuit, so I'm not in a position to suggest things to check (or to
> confirm that the comparator you tried performs similarly poorly in my
> tests, if that is the case).
> 
> One sanity check you can try -- disable the filtering on your 6957
> eval board.  According to the LT data presented in the chart If amplier PN 
I split the comparator output and feed it to 2 separa
> posted, which agrees very closely with my test results, at
> 10MHz/15dBm there should be essentially no change in the PN 
compared
> to the results you obtained with filtering enabled.  If you see a
> significant difference, then something is causing anomalous results.
> 
> Best regards,
> 
> Charles
> 

The comparator circuit measured was the front end of David Partridge's 
divider. I merely measured the 10MHz output.

I thought that I had made measurements for various filter settings and 
input levels. If I did, I don't appear to have saved them. I certainly named 
the various TIM files to indicate the filter settings.

I'll try and repeat the measurements for various input levels and filter 
settings.
One thing that I have found is that at low offset frequencies the measured 
PN is substantially reduced when air currents and other sources of thermal 
fluctuations are reduced. Even the effect of a thin piece of paper used as 
an air current shield can be easily seen.
With careful shielding from thermal fluctuations I measure the low 
frequency offset PN to be substantially lower than the datasheet values.
I've seen this effect with everything for which I've measured the PN.
I may machine a custom housing for the evaluation board rather than just 
using an oversize die cast box.
This may take a while as I'll need to check the compatibility of various 
hardware/software with Windows 10 that runs on my Quadcore laptop.
Failing that I do have a quad core PC with water cooled CPU that runs 
Windows 7.

One problem with comparators when attempting to measure their PN is 
that they don't have sufficient output to drive the TimePod input directly. 
An amplifier is required. To reduce the Amplifier PN contribution I split the 
comparator output and drive a separate amplifier from each splitter output 
and then use cross correlation. This makes the amplifier PN much less 
critical. Finding low PN amplifiers with relatively low gain ( ~ 10dB or so) 
with low distortion at 13dBm or so output is somewhat problematic. A low 
noise single transistor discrete amp with 30dB or more reverse isolation 
with a gain of 10dBm ought to be feasible at 10MHz.

> 
> ps.  You often respond to one message by replying to a different
> message, as you did in this case.  It would be helpful for someone
> who just joins a thread, and for continuity in general, if you would
> reply to the message to which you are actually responding.  That way,
> readers who are new to the thread will have the context they need,
> and your interlocutor will have his or her previous message
> conveniently 'available to refer to in any further message.
> 
> 

I dont always have convenient access to my email machine and sometimes 
resort to using a browser to compose a reply via my ISP's interface to my 
email.
This apparently messes up the reply so it is associated with a different 
message to the one I believed I was replying to. This is a fairly recent 
phenomenon.

Bruce
> 
> 
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Re: [time-nuts] Unified VCXO Carrier Board

[Bob Camp]

Hi

If you are buying the “right” 0.5 ppm / C resistors, they often run well over 
$10 each. You have
a *lot* of them in a circuit….

Bob

> On Oct 22, 2015, at 5:09 PM, Dimitri.p  wrote:
> 
> The price of the resistors is small change compared to the $8 connector for 
> the 10811.
> Then again maybe the plan is not to actually build one board with all the 
> parts that will accomodate any of the OCXOs on the list
> 
> 
> Dimitri
> 
> At 04:44 AM 10/22/2015, Bob Camp wrote:
>> > 2. It provides unified tuning: 0V = lowest possible frequency, 3V3 or 5V = 
>> > highest possible frequency, no matter of the VCXO tuning sense and range.
>> 
>> That immediately gets you into op amps and feedback resistor stability. With 
>> a number of combinations, the required resistors can get pretty expensive. It
>> also gets you into dual supplies with some OCXO’s.
> 
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Re: [time-nuts] Unified VCXO Carrier Board

[Gerhard Hoffmann]

Am 22.10.2015 um 22:04 schrieb Charles Steinmetz:
As I have said before, there is very little if any advantage to using 
an LTC6957 at 10MHz (as opposed to using a run-of-the-mill comparator),


What do you consider a run-of-the-mill comparator? LM139, LMV7219, 
AD8561, ADCMP580?


and the LTC6957 is not as good, even with filtering on, as a circuit 
with lower inherent jitter such as an optimized Wenzel-style squarer.
What optimizations?  I have seen the "Wenzel" circuit in cheapish 
frequency counter inputs in

the late seventies, maybe with a diode bridge added as input protection..


The graph compares an optimized 6957 implementation without filtering 
and with optimum filtering.  At an input level of -10dBm, the phase 
noise floor is 7dB lower with filtering, and at an input of +10dBm, 
the improvenent is <2.5dB.  Extrapolating beyond the graph to the 
right, at an input level of +13dBm (= 1Vrms, the customary level for 
frequency references), the improvement with filtering will be very 
near 0dB. 


so it shows that one can replace filtering by signal power :-)


I realize that you did not say you expect to use the board only at 
10MHz, and the LTC6957 with filtering may provide some improvement at 
lower frequencies (compared to the 6957 without filtering). But even 
with filtering on, the 6957 will not outperform an optimized 
Wenzel-type squarer until you get well down into the kHz range. 


But in the KHz range, the filter corner frequency should be much lower 
than in the 6957...


The 100 MHz range would be more interesting. The Wenzel squarer would 
then need
"real transistors" with higher 1/f corner. The PLL would have a sub-Hz 
BW in this application,
so the race for the lowest floor seems not too important. OK, maybe for 
the 1pps.


The 6957 takes one square centimeter including transformer and works for 
all frequencies.

Any objections against the AD9901 phase comparator? I have a tube of them.

regards, Gerhard
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Re: [time-nuts] Unified VCXO Carrier Board

[Charles Steinmetz]

Gerhard wrote:

What do you consider a run-of-the-mill comparator? LM139, LMV7219, 
AD8561, ADCMP580?


For squaring 1-10MHz sine waves, the LT1719 and 1720 are the best 
that I've found.  This is a matter of how much internal hysteresis 
the comparator has, how smoothly the internal hysteresis acts, how 
much gain the part has and how it is structured, how fast it is (both 
risetime and propagation delay), whether it suffers from thermal 
feedback from the output stage to the input stage, how much internal 
ground bounce it has, and a host of other die-level issues.


The LT1719 uses bipolar input supplies, so ground can be the 
reference voltage and also be in the center of the input common-mode 
range.  This is always quieter than biasing the inputs to the middle 
of a single supply, which is usually done with the 1720 and many 
other comparators.  (Like other single-supply comparators, the 1720 
will work referenced to ground with only a positive supply -- but (i) 
the inputs are then at the very edge of the input common-mode range, 
and (ii) you can only drive the input 100mV below ground, so you have 
to figure out how to clamp the input signal.  It is much easier to 
just use an LT1719 with +/-5v on the input stage, and it works better, too.)


Page 22 of the LT1719 datasheet shows the simplest possible circuit 
and discusses its performance.


What optimizations?  I have seen the "Wenzel" circuit in cheapish 
frequency counter inputs in

the late seventies, maybe with a diode bridge added as input protection..


Use medium-speed transistors, bias both bases from the same low-noise 
voltage reference such as an LM329, capacitively couple the emitters, 
and use a higher supply voltage, for starters.  I use MPSH81/MMBTH81s 
and a power supply of around 20v (see attached schematic) for a 
reasonably optimized implementation.  Other transistors can be used, 
but I've found that the H81s work better for squaring 1-10MHz sine 
waves than anything else I've tried -- they hit the sweet spot of the 
bandwidth/gain tradeoff and have a nice flat gain vs. current characteristic.



so it shows that one can replace filtering by signal power :-)


It's a matter of the slew rate of the input sine wave at 
zero-cross.  Once you reach the critical slew rate for any particular 
input architecture, the comparator is hard-switched fast enough that 
it doesn't spend significant time in the linear region generating noise.



Any objections against the AD9901 phase comparator?


That should work fine.

Best regards,

Charles

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Re: [time-nuts] Unified VCXO Carrier Board

[Gerhard Hoffmann]

Am 22.10.2015 um 19:58 schrieb Garry Thorp:


To make things a bit more complicated, Pascall oscillators' tune voltage range is 
0 - 10V. Tuning to the nominal frequency is likely to require >5V.




That would not stop me, that is in the reach of most op amps, but I was
quoted €4k2 + 19% VAT for a 100 MHz unit a month ago IIRC. Then I can
have someone select the crystals myself.
Nevertheless, we use them from time to time, but not for pure fun 
activities.


:-)   Gerhard   DK4XP
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Re: [time-nuts] Unified VCXO Carrier Board

[Charles Steinmetz]

Gerhard wrote:

5.Board has 2 reference frequency inputs with LTC6957 receivers. One 
of them can interface the onboard VCXO to the CPLD.


As I have said before, there is very little if any advantage to using 
an LTC6957 at 10MHz (as opposed to using a run-of-the-mill 
comparator), and the LTC6957 is not as good, even with filtering on, 
as a circuit with lower inherent jitter such as an optimized 
Wenzel-style squarer.


LT published an app note that shows the improvement with filtering 
enabled, using a 10MHz input.  The relevant graph is attached below.


The graph compares an optimized 6957 implementation without filtering 
and with optimum filtering.  At an input level of -10dBm, the phase 
noise floor is 7dB lower with filtering, and at an input of +10dBm, 
the improvenent is <2.5dB.  Extrapolating beyond the graph to the 
right, at an input level of +13dBm (= 1Vrms, the customary level for 
frequency references), the improvement with filtering will be very 
near 0dB.  It is not hard to add 10dB or more of gain at 10MHz with a 
residual phase noise penalty in the -180dB range.  So, with a 10MHz 
input, even if the output level of the source is lower than +13dBm, 
you can easily do just as well with a 6957 with the filtering off as 
with it on.  And with a squaring circuit that has inherently lower 
residual PN than the 6957 (e.g., an optimized Wenzel-type squarer), 
you can do better than with any permutation of the 6957.


These data are consistent with testing I have done of the LTC6957 and 
other squaring circuits.


I realize that you did not say you expect to use the board only at 
10MHz, and the LTC6957 with filtering may provide some improvement at 
lower frequencies (compared to the 6957 without filtering).  But even 
with filtering on, the 6957 will not outperform an optimized 
Wenzel-type squarer until you get well down into the kHz range.  And 
for the usual time-nuts case -- 10MHz at ~13dBm -- the 6957 is not 
the best solution, even with filtering enabled.


Best regards,

Charles
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Re: [time-nuts] Unified VCXO Carrier Board

[Dimitri.p]

The price of the resistors is small change 
compared to the $8 connector for the 10811.
Then again maybe the plan is not to actually 
build one board with all the parts that will 
accomodate any of the OCXOs on the list



Dimitri

At 04:44 AM 10/22/2015, Bob Camp wrote:
> 2. It provides unified tuning: 0V = lowest 
possible frequency, 3V3 or 5V = highest 
possible frequency, no matter of the VCXO tuning sense and range.


That immediately gets you into op amps and 
feedback resistor stability. With a number of 
combinations, the required resistors can get pretty expensive. It

also gets you into dual supplies with some OCXO’s.


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Re: [time-nuts] Unified VCXO Carrier Board

[Bob Camp]

Hi

> On Oct 22, 2015, at 3:40 AM, Gerhard Hoffmann  wrote:
> 
> I'd like to design a unified VCXO Carrier Board to these requirements:
> 
> 
> 1. It can host one of the the following VCXOs:
> 
> 1.1. HP 10811A-6111 (as from 5370A)
> 
> 1.2 Morion MV89A
> 
> 1.3 MTI 260
> 
> 1.4 CV-950
> 
> 1.5 Timetech
> 
> 1.6 Axtal
> 
> 1.7 Pascall

Multiple footprints are fine and they don’t generally take up a lot of space. 
The 10811 is a bit of a hassle in that respect. 

> 
> 
> 2. It provides unified tuning: 0V = lowest possible frequency, 3V3 or 5V = 
> highest possible frequency, no matter of the VCXO tuning sense and range.

That immediately gets you into op amps and feedback resistor stability. With a 
number of combinations, the required resistors can get pretty expensive. It
also gets you into dual supplies with some OCXO’s. 

> 
> 3. provides a 5V tuning voltage reference for those VCXOs that don't have one 
> of their own.

This gets you into the same sort of “is 1 ppm stability on the tuning good 
enough” set of questions.There are a number of OCXO’s out there that have odd
reference voltages.(10 V etc)

> 
> 4. Frequency can be adjusted from external Vtune input and from a 10 turn pot.

Sounds good. Consider ground loops and offsets on the external input. 

> 
> 5.Board has 2 reference frequency inputs with LTC6957 receivers. One of them 
> can interface the onboard VCXO to the CPLD.

I’m not sure these are needed if the destination is a CPLD.

> 
> 6. Board has a 1pps input 3V3 CMOS level

Hopefully buffered with discrete logic. CPLD’s often are not very rugged in 
terms of over voltage on the inputs. 

> 
> 7. It can lock the VCXO to the reference frequency or the 1pps in. Provides 
> LED lock indication.

Probably not easily with a 64 flip flop CPLD. For a full narrow bandwidth PLL 
you will need some more “stuff” on the board. With a 
wideband loop, you will have a lot of noise on the oscillator. 

> 
> 8. It features a Xilinx Coolrunner2 2C64 CPLD, complexity 64 FlipFlops + 
> combin. Logic. Unused Pins are brought out to Testpoints in 100 mil grid. The 
> Coolrunner remembers its configuration and can be reprogrammed using the 
> standard Xilinx USB dongle. It has a 10 pin 2mm header for this purpose. 
> Small circuits can run at 200 MHz. This function exists already:
> < 
> https://picasaweb.google.com/lh/photo/4Bpcfouj8WH0shNGIyuVUtMTjNZETYmyPJy0liipFm0?feat=directlink
>  >

Given the number of much larger devices in the 10 to 100X larger range that are 
still under $10, I’d look at another device. 

> 
> 9. The Coolrunner provides a standard 1pps /20us out, maybe 10/100/1000 pps.
> 
> 10. 2 Monoflops for 1pps LEDs in/out

ok.

> 
> 11. There are 2 output buffers that drive valid 3V3 CMOS into 50 Ohms. They 
> can be re-clocked to LTC6957 outputs with 1G74 flip-flops.

I would dedicate a couple of discrete (sot-23 logic) buffers to the 1 pps 
outputs. 

> 
> 12. Unbuffered VCXO output is available on SMA connector
> 
> 13. One additional buffered output (LMH6702/AD8009 or discrete to avoid neg. 
> supply). This is not meant to be a distribution amplifier.
> 
> 14. Regulators for the voltages needed.
> 
> 15. Requires soldering skills 0603 / sot23-5 / MSOP. No commercial interest. 
> Could be TAPR or DIY.

With all this stuff on the board, layout will be “interesting”. Keeping it all 
from cross talking will be a challenge. 
That gets even more complex as the number of external connections goes up. The 
more configurations, the 
more things to worry about …

One simple example of the above:

Your OCXO:

1)  pulls 3 ppm with a 5V tune.
2) has a stability over -30 to +70C of 1 ppb
3) has an ADEV at 1 second of 1 ppt

That comes out to:

Stability wise, that’s 10 ppt / C
Tune wise you have 0.6 ppm / volt or 0.6 ppt / uV

To maintain the 10 ppt/C your reference / tune voltage needs to be better than 
that. For instance, 5X better is a fairly
common design goal in many systems. That’s 2 ppt/C from the tune. Roughly 4 uV 
of stability would do it. 

With a 5V reference the same 4uV is a 1 ppm / C reference. The same math 
applies to the stability of the resistors
in the tune circuits and the offset drift on the op-amps. 

Lots to think about !!!


Bob

> 
> 
> I'm open to suggestions & ideas.
> 
> regards,
> Gerhard, DK4XP
> 
> 
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