Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-17 Thread ewkehren via time-nuts
Good choice                    Bert Kehren


Sent from my Galaxy Tab® A
 Original message From: Gerhard Hoffmann  Date: 
9/16/18  6:30 PM  (GMT-05:00) To: time-nuts@lists.febo.com Subject: Re: 
[time-nuts] Programmable clock for BFO usenoise 


Am 16.09.2018 um 23:11 schrieb Attila Kinali:
> On Sun, 16 Sep 2018 22:08:19 +0200
> Gerhard Hoffmann  wrote:
>
>> I'm also not a fan of using slowish, slew-rate challenged  logic as a
>> replacement
>> for a low pass. When I want a low pass, I make it from nice,
>> time-invariant RLC.
> Unfortunately, using a low pass after the divider will not
> prevent the down-mixing. The down-mixing happens as an inherent
> property of digital circuits. Any filtering you do afterwards
> will be too late. If you want to have low noise, then the only
> way is to produce a non-square wave signal. Or in other words:
> use a divider built from harmonic mixers*.
Why do you assume that slew-rate limited mixers are any
better than mixers with an ultra-short analog time window
for doing mess?

We should sort that out offline, we are just 20 miles apart?
I propose the Zwickel pub in Dudweiler; I'm there with the
mostly emerited Fraunhofer people on Friday evenings
now & then.        :-)  :-)  :-)
> * That is, if you don't like Λ-dividers or DDS
I do like DDS, and I don't see  a reason for the D/A converters
in front of the mixers. D/A converters remove the fun when you
can just instantiate a multiplier.

Cheers,

Gerhard



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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-16 Thread Gerhard Hoffmann



Am 16.09.2018 um 23:11 schrieb Attila Kinali:

On Sun, 16 Sep 2018 22:08:19 +0200
Gerhard Hoffmann  wrote:


I'm also not a fan of using slowish, slew-rate challenged  logic as a
replacement
for a low pass. When I want a low pass, I make it from nice,
time-invariant RLC.

Unfortunately, using a low pass after the divider will not
prevent the down-mixing. The down-mixing happens as an inherent
property of digital circuits. Any filtering you do afterwards
will be too late. If you want to have low noise, then the only
way is to produce a non-square wave signal. Or in other words:
use a divider built from harmonic mixers*.

Why do you assume that slew-rate limited mixers are any
better than mixers with an ultra-short analog time window
for doing mess?

We should sort that out offline, we are just 20 miles apart?
I propose the Zwickel pub in Dudweiler; I'm there with the
mostly emerited Fraunhofer people on Friday evenings
now & then.        :-)  :-)  :-)

* That is, if you don't like Λ-dividers or DDS

I do like DDS, and I don't see  a reason for the D/A converters
in front of the mixers. D/A converters remove the fun when you
can just instantiate a multiplier.

Cheers,

Gerhard



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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-16 Thread Gerhard Hoffmann

Am 16.09.2018 um 20:00 schrub Mark Goldberg:

For a radio BFO you want something with low phase noise (low jitter). The
SI5351 is not designed for that, and it's jitter spec is 70 ps, which is
pretty noisy. It even has a spread spectrum mode that would be even worse.
They do have other parts designed for low jitter (< 1ps). Leo Bodnar's
GPSDOs with variable output clock frequencies are based on  those chips and
they provide low phase noise, certainly enough for a radio


Oh, a half of a 12AX7 has always been good enough for my needs as a BFO,
xtal controlled or LC free running. 30 dB above the noise is S5, what more
do you want? The real problems of a receiver are IP3 and that you have
a preselector and a mixer that simply work without producing mess.
LO jitter is probably > 100 times more important than the BFO, that is just
for conversion of IF to audio.

cheers,
Gerhard, DK4XP

(I do not use many 12AX7 any more, in real life that is just a down 
converter

block in a corner of of a Virtex FPGA. )


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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-16 Thread Mark Goldberg
For a radio BFO you want something with low phase noise (low jitter). The
SI5351 is not designed for that, and it's jitter spec is 70 ps, which is
pretty noisy. It even has a spread spectrum mode that would be even worse.
They do have other parts designed for low jitter (< 1ps). Leo Bodnar's
GPSDOs with variable output clock frequencies are based on  those chips and
they provide low phase noise, certainly enough for a radio.

Regards,

Mark


On Sun, Sep 16, 2018 at 10:22 AM, Chris Waldrup  wrote:

> How about using a ProgRock on Hans Summers QRP Labs website? This is a
> programmable crystal replacement.
>
> Chris
> KD4PBJ
>
> > On Sep 14, 2018, at 8:06 PM, paul swed  wrote:
> >
> > The beauty of a $2 arduino and a drop of code snitched from Engineer
> google.
> > OK enough of that back to the thread.
> > Regards
> > Paul
> > WB8TSL
> >
> >> On Fri, Sep 14, 2018 at 8:04 PM, Mike Feher  wrote:
> >>
> >> Not when I built them in the late 60's and early 70's. All discrete. 73
> -
> >> Mike
> >>
> >>
> >>
> >> Mike B. Feher, N4FS
> >>
> >> 89 Arnold Blvd.
> >>
> >> Howell NJ 07731
> >>
> >> 848-245-9115
> >>
> >>
> >>
> >> -----Original Message-----
> >> From: time-nuts  On Behalf Of Richard
> >> (Rick) Karlquist
> >> Sent: Friday, September 14, 2018 7:15 PM
> >> To: Discussion of precise time and frequency measurement
> >> ; ed breya 
> >> Subject: Re: [time-nuts] Programmable clock for BFO usenoise
> >>
> >>
> >>
> >>
> >>> Finally, of course, you can use DDS. This is nearly an ideal case for
> >>
> >>
> >>
> >> The trouble with a DDS is that you need a microcontroller with software
> >> just
> >> to baby sit the thing.
> >>
> >>
> >>
> >> Rick N6RK
> >>
> >>
> >>
> >> ___
> >>
> >> time-nuts mailing list --  <mailto:time-nuts@lists.febo.com>
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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-16 Thread Attila Kinali
On Sun, 16 Sep 2018 22:08:19 +0200
Gerhard Hoffmann  wrote:

> I'm also not a fan of using slowish, slew-rate challenged  logic as a 
> replacement
> for a low pass. When I want a low pass, I make it from nice, 
> time-invariant RLC.

Unfortunately, using a low pass after the divider will not
prevent the down-mixing. The down-mixing happens as an inherent
property of digital circuits. Any filtering you do afterwards
will be too late. If you want to have low noise, then the only
way is to produce a non-square wave signal. Or in other words:
use a divider built from harmonic mixers*.

Attila Kinali

* That is, if you don't like Λ-dividers or DDS
-- 
The bad part of Zurich is where the degenerates
throw DARK chocolate at you.

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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-16 Thread lstoskopf
Just the info I wanted!  Thanks, N0UU

> On September 16, 2018 at 8:49 AM Didier Juges  wrote:
> 
> Not the same part number but probably similar in terms of performance:
> 
> 
> http://www.ko4bb.com/getsimple/index.php?id=microprocessor-crystal-oscillator-comparison
> 
> Bottom line: use a true crystal oscillator, or make your own PLL, not a 
> programmable "microprocessor crystal"
> 
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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-16 Thread Gerhard Hoffmann

Am 15.09.2018 um 17:38 schrieb Richard (Rick) Karlquist:


If you divide by something that is not a power of 2, then it is 
important
that each stage produces an output waveform with a 50% duty cycle. 
Otherwise
flicker noise which has been up-mixed by a previous stage, will be 
down-mixed

into the signal band, increasing the close-in phase-noise.


Wow, another thing I never knew.  The conventional wisdom was to
divide by any number (even or odd) and then follow that divider
with a divide by 2 flip flop to get 50%.  Now, that is in question.
The now correct answer is to us a variable modulus prescaler to
divide by P and P+1, controlled by a toggle flip flop to make
half the divisions at P and half at P+1.


Resynchronize the output of the divider to the undivided clock with 
another D-FF
and everything but that last D-FF will fall out of the equation for 
phase noise.


I'm also not a fan of using slowish, slew-rate challenged  logic as a 
replacement
for a low pass. When I want a low pass, I make it from nice, 
time-invariant RLC.


regards, Gerhard.



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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-16 Thread Magnus Danielson
Hi Chris,

On 09/16/2018 07:22 PM, Chris Waldrup wrote:
> How about using a ProgRock on Hans Summers QRP Labs website? This is a 
> programmable crystal replacement. 

I have one of those but have not had the time to put it up for a real
test. Also got the GPS module that should fit, as you can train it to
slave a PPS. It would be interesting to take the setup for a test-ride.

Need to clean the desk with other things in order to be able to focus on
fun projects like that.

Cheers,
Magnus

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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-16 Thread Chris Waldrup
How about using a ProgRock on Hans Summers QRP Labs website? This is a 
programmable crystal replacement. 

Chris
KD4PBJ

> On Sep 14, 2018, at 8:06 PM, paul swed  wrote:
> 
> The beauty of a $2 arduino and a drop of code snitched from Engineer google.
> OK enough of that back to the thread.
> Regards
> Paul
> WB8TSL
> 
>> On Fri, Sep 14, 2018 at 8:04 PM, Mike Feher  wrote:
>> 
>> Not when I built them in the late 60's and early 70's. All discrete. 73 -
>> Mike
>> 
>> 
>> 
>> Mike B. Feher, N4FS
>> 
>> 89 Arnold Blvd.
>> 
>> Howell NJ 07731
>> 
>> 848-245-9115
>> 
>> 
>> 
>> -Original Message-
>> From: time-nuts  On Behalf Of Richard
>> (Rick) Karlquist
>> Sent: Friday, September 14, 2018 7:15 PM
>> To: Discussion of precise time and frequency measurement
>> ; ed breya 
>> Subject: Re: [time-nuts] Programmable clock for BFO usenoise
>> 
>> 
>> 
>> 
>>> Finally, of course, you can use DDS. This is nearly an ideal case for
>> 
>> 
>> 
>> The trouble with a DDS is that you need a microcontroller with software
>> just
>> to baby sit the thing.
>> 
>> 
>> 
>> Rick N6RK
>> 
>> 
>> 
>> ___
>> 
>> time-nuts mailing list --  <mailto:time-nuts@lists.febo.com>
>> time-nuts@lists.febo.com To unsubscribe, go to
>> <http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com>
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>> 
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>> 
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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-16 Thread Bob kb8tq
Hi

Coming back to the basics of the design:

If you are playing with a normal radio, a BFO that drifts under a few Hertz is 
going to be pretty much un-noticable. Drift is a bit of an elastic term in this 
case
since it can cover a bunch of different parameters on an oscillator 
(temperature 
as things warm up / aging / retrace / voltage stability ….). 

For fun, lets say that 25.3 Hz over a day and 5C is “adequate” for the task. 
Oddly
enough this makes the math easy. 25.3 Hz / 253 KHz = 1 / 10,000 = 100 ppm. 

A crystal that drifts  1 ppm / C is not a super duper part at room temperature. 
Over
our 5C range, that’s only 5 ppm. It would have to be 10X worse to really eat 
into
our budget. 

Aging / warmup / retrace wise, a crystal that moves a couple ppm in the first 
day
is moving a lot. Again not a big hit to our budget.

Voltage stability on a properly designed circuit with a normal voltage 
regulator should  
be very small compared to the budget. Maybe it’s a ppm, probably less. 

Bottom line - the crystal likely is doing >10X better than what our arbitrary 
spec would 
require. That’s why a lot of radios do just fine with an L/C based BFO. 

For even more fun, take a look at the likely drift of the mechanical filters 
involved. They
are not going to be as stable as the crystal ….. Even a crystal filter at 
250KHz isn’t 
going to be as stable as the AT cut based evaluation above. 

Bob


> On Sep 16, 2018, at 7:49 AM, Didier Juges  wrote:
> 
> Not the same part number but probably similar in terms of performance:
> 
> http://www.ko4bb.com/getsimple/index.php?id=microprocessor-crystal-oscillator-comparison
> 
> Bottom line: use a true crystal oscillator, or make your own PLL, not a
> programmable "microprocessor crystal"
> 
> On Fri, Sep 14, 2018, 11:15 AM  wrote:
> 
>> Off topic for this list, but you guys are experts in oscillator noise!
>> 
>> Playing with some mechanical filters.  Need USB and LSB crystals for the
>> BFO.  No one seems to make crystals anymore, especially in the 253 KHz
>> range!
>> 
>> Looking at the DigiKey Cardinal programmable oscillators.  Cheap and
>> available: CPPC1LZ A5B6
>> 
>> Anyone have an idea how noisy these would be after a division by 4 to get
>> them in range?
>> 
>> Thanks,
>> 
>> N0UU
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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-15 Thread Bob kb8tq
Hi

Most of the traditional rules about phase noise apply out to 10 or 20% of the 
“carrier”
frequency. If the carrier is 1Hz, then you are talking about the traditional 
definitions holding 
out to 0.1 or 0.2 Hz relative to carrier. That’s *deep* in the 1/F noise part 
of the divider’s 
“noise curve”.

Since the ADEV of the 1 PPS is typically no worse than the ADEV of the 10 MHz, 
it would be
hard to come up with a model where the 1 PPS has picked up a lot of extra noise.

Bob

> On Sep 15, 2018, at 9:05 PM, Scott Stobbe  wrote:
> 
> That is fascinating. So, the 1PPS line on a GPSDO (a divide by 10Meg in
> many cases) is 70 dB worse than the traditional 20log(N) PN scaling?
> 
> On Sat, Sep 15, 2018 at 11:40 AM Richard (Rick) Karlquist <
> rich...@karlquist.com> wrote:
> 
>> Another great posting from Attila that keeps the S/N ratio
>> on this list high.
>> 
>> On 9/15/2018 3:26 AM, Attila Kinali wrote:
>> 
>>> possible logic family for the task. Otherwise the harmonics of the
>>> switching of the FF will down-mix high frequency white noise down
>>> to the signal band (this is the reason for the 10*log(N) noise scaling
>>> of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
>>> mentioned).
>> 
>> Wow, I never knew this in 45 years of designing synthesizers!
>> I do remember that some of the frequency counter engineers at HP
>> talked about noise aliasing.  I think this is another way of
>> describing the same problem.
>> 
>> About 10 years ago, the frequency synthesizer chip vendors started
>> talking about a Figure of Merit (FOM) that predicted phase noise floor,
>> and it also included the 10 LOG N noise scaling.  An application
>> engineer at ADI told me this was a characteristic of the sampling phase
>> detector that all these chips used.  But I always wondered if the
>> frequency divider could come into play.  The way FOM is defined,
>> it doesn't distinguish between phase detector and divider noise.
>> 
>> At Agilent, we used to make a lot of lab demos using a Centellax
>> (now Microsemi AKA Microchip) frequency divider that could divide by any
>> number between 8 and 511 up to 10 GHz.  It was absolutely fabulous for
>> dividing 10 GHz down to 2.5 GHz.  But 20 LOG N quit working if I tried
>> to divide down to 50 MHz.  Now you have explained it.
>>> 
>>> If you divide by something that is not a power of 2, then it is important
>>> that each stage produces an output waveform with a 50% duty cycle.
>> Otherwise
>>> flicker noise which has been up-mixed by a previous stage, will be
>> down-mixed
>>> into the signal band, increasing the close-in phase-noise.
>> 
>> Wow, another thing I never knew.  The conventional wisdom was to
>> divide by any number (even or odd) and then follow that divider
>> with a divide by 2 flip flop to get 50%.  Now, that is in question.
>> The now correct answer is to us a variable modulus prescaler to
>> divide by P and P+1, controlled by a toggle flip flop to make
>> half the divisions at P and half at P+1.
>> 
>> Does anyone else have experience with these issues?
>> 
>> Rick N6RK
>> 
>> 
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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-15 Thread Scott Stobbe
That is fascinating. So, the 1PPS line on a GPSDO (a divide by 10Meg in
many cases) is 70 dB worse than the traditional 20log(N) PN scaling?

On Sat, Sep 15, 2018 at 11:40 AM Richard (Rick) Karlquist <
rich...@karlquist.com> wrote:

> Another great posting from Attila that keeps the S/N ratio
> on this list high.
>
> On 9/15/2018 3:26 AM, Attila Kinali wrote:
>
> > possible logic family for the task. Otherwise the harmonics of the
> > switching of the FF will down-mix high frequency white noise down
> > to the signal band (this is the reason for the 10*log(N) noise scaling
> > of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
> > mentioned).
>
> Wow, I never knew this in 45 years of designing synthesizers!
> I do remember that some of the frequency counter engineers at HP
> talked about noise aliasing.  I think this is another way of
> describing the same problem.
>
> About 10 years ago, the frequency synthesizer chip vendors started
> talking about a Figure of Merit (FOM) that predicted phase noise floor,
> and it also included the 10 LOG N noise scaling.  An application
> engineer at ADI told me this was a characteristic of the sampling phase
> detector that all these chips used.  But I always wondered if the
> frequency divider could come into play.  The way FOM is defined,
> it doesn't distinguish between phase detector and divider noise.
>
> At Agilent, we used to make a lot of lab demos using a Centellax
> (now Microsemi AKA Microchip) frequency divider that could divide by any
> number between 8 and 511 up to 10 GHz.  It was absolutely fabulous for
> dividing 10 GHz down to 2.5 GHz.  But 20 LOG N quit working if I tried
> to divide down to 50 MHz.  Now you have explained it.
> >
> > If you divide by something that is not a power of 2, then it is important
> > that each stage produces an output waveform with a 50% duty cycle.
> Otherwise
> > flicker noise which has been up-mixed by a previous stage, will be
> down-mixed
> > into the signal band, increasing the close-in phase-noise.
>
> Wow, another thing I never knew.  The conventional wisdom was to
> divide by any number (even or odd) and then follow that divider
> with a divide by 2 flip flop to get 50%.  Now, that is in question.
> The now correct answer is to us a variable modulus prescaler to
> divide by P and P+1, controlled by a toggle flip flop to make
> half the divisions at P and half at P+1.
>
> Does anyone else have experience with these issues?
>
> Rick N6RK
>
>
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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-15 Thread Richard (Rick) Karlquist

Another great posting from Attila that keeps the S/N ratio
on this list high.

On 9/15/2018 3:26 AM, Attila Kinali wrote:


possible logic family for the task. Otherwise the harmonics of the
switching of the FF will down-mix high frequency white noise down
to the signal band (this is the reason for the 10*log(N) noise scaling
of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
mentioned).


Wow, I never knew this in 45 years of designing synthesizers!
I do remember that some of the frequency counter engineers at HP
talked about noise aliasing.  I think this is another way of
describing the same problem.

About 10 years ago, the frequency synthesizer chip vendors started
talking about a Figure of Merit (FOM) that predicted phase noise floor, 
and it also included the 10 LOG N noise scaling.  An application 
engineer at ADI told me this was a characteristic of the sampling phase 
detector that all these chips used.  But I always wondered if the 
frequency divider could come into play.  The way FOM is defined,

it doesn't distinguish between phase detector and divider noise.

At Agilent, we used to make a lot of lab demos using a Centellax
(now Microsemi AKA Microchip) frequency divider that could divide by any 
number between 8 and 511 up to 10 GHz.  It was absolutely fabulous for 
dividing 10 GHz down to 2.5 GHz.  But 20 LOG N quit working if I tried 
to divide down to 50 MHz.  Now you have explained it.


If you divide by something that is not a power of 2, then it is important
that each stage produces an output waveform with a 50% duty cycle. Otherwise
flicker noise which has been up-mixed by a previous stage, will be down-mixed
into the signal band, increasing the close-in phase-noise.


Wow, another thing I never knew.  The conventional wisdom was to
divide by any number (even or odd) and then follow that divider
with a divide by 2 flip flop to get 50%.  Now, that is in question.
The now correct answer is to us a variable modulus prescaler to
divide by P and P+1, controlled by a toggle flip flop to make
half the divisions at P and half at P+1.

Does anyone else have experience with these issues?

Rick N6RK


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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-15 Thread ewkehren via time-nuts
The question was deviding a Rb  20 MHz to 10 that is easy to but how much 
effort is dependant what it is used for and that in turn determines what to use 
on the input. We have 4 choices depending on the requirementBert


Sent from my Galaxy Tab® A
 Original message From: Attila Kinali  Date: 
9/15/18  8:34 AM  (GMT-05:00) To: Discussion of precise time and frequency 
measurement  Subject: Re: [time-nuts] Programmable 
clock for BFO usenoise 
Hoi Bert,

On Sat, 15 Sep 2018 11:09:18 + (UTC)
ew via time-nuts  wrote:

> What about the application and the trigger circuit

Sorry, I don't understand what you mean.

Attila Kinali

-- 
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    throw DARK chocolate at you.

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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-15 Thread Attila Kinali
Hoi Bert,

On Sat, 15 Sep 2018 11:09:18 + (UTC)
ew via time-nuts  wrote:

> What about the application and the trigger circuit

Sorry, I don't understand what you mean.

Attila Kinali

-- 
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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-15 Thread Attila Kinali
On Sat, 15 Sep 2018 13:13:40 +0200
Club-Internet Clemgill  wrote:

> Very interesting, thanks.  
> I found ref (2) by seems that need to pay or be to registered as a researcher 
> to get ref (1). 
> Is there a easier way to get a copy ? 

Yes, use sci-hub: https://sci-hub.tw/10.1109/58.56498

Attila Kinali

-- 
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throw DARK chocolate at you.

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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-15 Thread Club-Internet Clemgill
Hi Attila, 
Very interesting, thanks.  
I found ref (2) by seems that need to pay or be to registered as a researcher 
to get ref (1). 
Is there a easier way to get a copy ? 
Thx,
Gilles. 

> Le 15 sept. 2018 à 12:26, Attila Kinali  a écrit :
> 
> On Fri, 14 Sep 2018 21:42:05 +
> Bryan _  wrote:
> 
>> I would be interested in hearing more of the more suitable classes of
>> logic chips. I have a 20Mhz rubidium that I wanted to divide down to 10Mhz
> 
> Any logic family works, as long as it is fast enough to handle your
> input frequency. Due to the non-linear (aka digital) behaviour
> of a D-Flipflop style divider, it is recommended to use the slowest
> possible logic family for the task. Otherwise the harmonics of the
> switching of the FF will down-mix high frequency white noise down
> to the signal band (this is the reason for the 10*log(N) noise scaling
> of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others 
> mentioned).
> 
> As a rule of thumb, I'd say that the FF should not be more than 10 to 20
> times faster than the input frequency, to limit noise down-mixing.
> If your FF is too fast or you want to reduce the noise floor, capacitively
> loading and/or having some additional resistance in the Vcc and GND lines
> will help slow it down. But ensure that the resistance is still low enough
> that the FF's supply stays within specs at all time. Similarly, the
> capacitive loading should be low enough that the output current is within
> reasonable bounds.
> 
> Alternatively, using the Λ-divider approach[2] and introducing voltage
> steps between 0 and 1 will also reduce down-mixing.
> 
> If you divide by something that is not a power of 2, then it is important
> that each stage produces an output waveform with a 50% duty cycle. Otherwise
> flicker noise which has been up-mixed by a previous stage, will be down-mixed
> into the signal band, increasing the close-in phase-noise.
> 
> 
>   Attila Kinali
> 
> [1] "Modeling Phase Noise in Frequency Dividers," by Egan, 1990
> 
> [2] "The Sampling Theorem in Pi and Lambda Digital Frequency Dividers,"
> by Calosso and Rubiola 2013
> 
> -- 
>   The bad part of Zurich is where the degenerates
>throw DARK chocolate at you.
> 
> ___
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> http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-15 Thread ew via time-nuts
What about the application and the trigger circuit
In a message dated 9/15/2018 6:27:50 AM Eastern Standard Time, att...@kinali.ch 
writes:

On Fri, 14 Sep 2018 21:42:05 +
Bryan _  wrote:

> I would be interested in hearing more of the more suitable classes of
> logic chips. I have a 20Mhz rubidium that I wanted to divide down to 10Mhz

Any logic family works, as long as it is fast enough to handle your
input frequency. Due to the non-linear (aka digital) behaviour
of a D-Flipflop style divider, it is recommended to use the slowest
possible logic family for the task. Otherwise the harmonics of the
switching of the FF will down-mix high frequency white noise down
to the signal band (this is the reason for the 10*log(N) noise scaling
of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others 
mentioned).

As a rule of thumb, I'd say that the FF should not be more than 10 to 20
times faster than the input frequency, to limit noise down-mixing.
If your FF is too fast or you want to reduce the noise floor, capacitively
loading and/or having some additional resistance in the Vcc and GND lines
will help slow it down. But ensure that the resistance is still low enough
that the FF's supply stays within specs at all time. Similarly, the
capacitive loading should be low enough that the output current is within
reasonable bounds.

Alternatively, using the Λ-divider approach[2] and introducing voltage
steps between 0 and 1 will also reduce down-mixing.

If you divide by something that is not a power of 2, then it is important
that each stage produces an output waveform with a 50% duty cycle. Otherwise
flicker noise which has been up-mixed by a previous stage, will be down-mixed
into the signal band, increasing the close-in phase-noise.


            Attila Kinali

[1] "Modeling Phase Noise in Frequency Dividers," by Egan, 1990

[2] "The Sampling Theorem in Pi and Lambda Digital Frequency Dividers,"
by Calosso and Rubiola 2013

-- 
    The bad part of Zurich is where the degenerates
                throw DARK chocolate at you.

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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-15 Thread Dr. Ulrich L. Rohde via time-nuts
Good points, Ulrich Rohde 

Sent from my iPhone

> On Sep 15, 2018, at 6:26 AM, Attila Kinali  wrote:
> 
> On Fri, 14 Sep 2018 21:42:05 +
> Bryan _  wrote:
> 
>> I would be interested in hearing more of the more suitable classes of
>> logic chips. I have a 20Mhz rubidium that I wanted to divide down to 10Mhz
> 
> Any logic family works, as long as it is fast enough to handle your
> input frequency. Due to the non-linear (aka digital) behaviour
> of a D-Flipflop style divider, it is recommended to use the slowest
> possible logic family for the task. Otherwise the harmonics of the
> switching of the FF will down-mix high frequency white noise down
> to the signal band (this is the reason for the 10*log(N) noise scaling
> of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others 
> mentioned).
> 
> As a rule of thumb, I'd say that the FF should not be more than 10 to 20
> times faster than the input frequency, to limit noise down-mixing.
> If your FF is too fast or you want to reduce the noise floor, capacitively
> loading and/or having some additional resistance in the Vcc and GND lines
> will help slow it down. But ensure that the resistance is still low enough
> that the FF's supply stays within specs at all time. Similarly, the
> capacitive loading should be low enough that the output current is within
> reasonable bounds.
> 
> Alternatively, using the Λ-divider approach[2] and introducing voltage
> steps between 0 and 1 will also reduce down-mixing.
> 
> If you divide by something that is not a power of 2, then it is important
> that each stage produces an output waveform with a 50% duty cycle. Otherwise
> flicker noise which has been up-mixed by a previous stage, will be down-mixed
> into the signal band, increasing the close-in phase-noise.
> 
> 
>Attila Kinali
> 
> [1] "Modeling Phase Noise in Frequency Dividers," by Egan, 1990
> 
> [2] "The Sampling Theorem in Pi and Lambda Digital Frequency Dividers,"
> by Calosso and Rubiola 2013
> 
> -- 
> The bad part of Zurich is where the degenerates
>throw DARK chocolate at you.
> 
> ___
> time-nuts mailing list -- time-nuts@lists.febo.com
> To unsubscribe, go to 
> http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-15 Thread Attila Kinali
On Fri, 14 Sep 2018 21:42:05 +
Bryan _  wrote:

> I would be interested in hearing more of the more suitable classes of
> logic chips. I have a 20Mhz rubidium that I wanted to divide down to 10Mhz

Any logic family works, as long as it is fast enough to handle your
input frequency. Due to the non-linear (aka digital) behaviour
of a D-Flipflop style divider, it is recommended to use the slowest
possible logic family for the task. Otherwise the harmonics of the
switching of the FF will down-mix high frequency white noise down
to the signal band (this is the reason for the 10*log(N) noise scaling
of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others 
mentioned).

As a rule of thumb, I'd say that the FF should not be more than 10 to 20
times faster than the input frequency, to limit noise down-mixing.
If your FF is too fast or you want to reduce the noise floor, capacitively
loading and/or having some additional resistance in the Vcc and GND lines
will help slow it down. But ensure that the resistance is still low enough
that the FF's supply stays within specs at all time. Similarly, the
capacitive loading should be low enough that the output current is within
reasonable bounds.

Alternatively, using the Λ-divider approach[2] and introducing voltage
steps between 0 and 1 will also reduce down-mixing.

If you divide by something that is not a power of 2, then it is important
that each stage produces an output waveform with a 50% duty cycle. Otherwise
flicker noise which has been up-mixed by a previous stage, will be down-mixed
into the signal band, increasing the close-in phase-noise.


Attila Kinali

[1] "Modeling Phase Noise in Frequency Dividers," by Egan, 1990

[2] "The Sampling Theorem in Pi and Lambda Digital Frequency Dividers,"
by Calosso and Rubiola 2013

-- 
The bad part of Zurich is where the degenerates
throw DARK chocolate at you.

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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-15 Thread Adrian Godwin
Depending on the cost of those mems devices, a microcontroller can be so
trivial that you can just consider it as a smart eprom. Like Tom's PICDIV
dividers, which act more like perfect-for-pupose division chip than a micro.



On Sat, Sep 15, 2018 at 4:31 AM, Forrest Christian (List Account) <
li...@packetflux.com> wrote:

> Would a mems oscillator such as a dsc6183 possibly work for you?  I'm
> uncertain if the characteristics of a mems oscillator is compatible with
> your application.
>
> For odd frequencies I often head toward a mems oscillator since many can be
> programmed to any reasonable frequency.   For example one can buy dsc6183
> blanks and use a programmer to program it to your desired frequency.
>
> The dsc61xx series happens to be one time programmable so you only get one
> shot at it per blank.  The programmer is relatively inexpensive, but might
> be more than one would want to pay for a one off.  I have found that having
> a collection of blanks and a programmer is very useful since it allows me
> to generate any frequency oscillator I need.
>
> There are other mems oscillator models out there, with various specs and
> programming (or not) options.
>
>
>
>
>
>
> On Fri, Sep 14, 2018, 11:16 AM  wrote:
>
> > Off topic for this list, but you guys are experts in oscillator noise!
> >
> > Playing with some mechanical filters.  Need USB and LSB crystals for the
> > BFO.  No one seems to make crystals anymore, especially in the 253 KHz
> > range!
> >
> > Looking at the DigiKey Cardinal programmable oscillators.  Cheap and
> > available: CPPC1LZ A5B6
> >
> > Anyone have an idea how noisy these would be after a division by 4 to get
> > them in range?
> >
> > Thanks,
> >
> > N0UU
> > ___
> > time-nuts mailing list -- time-nuts@lists.febo.com
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> > http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
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> >
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Re: [time-nuts] Programmable clock for BFO use....noise Thanks to all

2018-09-14 Thread Pete Lancashire
Somebody send me the URL to that board thank you

On Fri, Sep 14, 2018, 9:21 PM  wrote:

>  Got a whole bunch of answers all with useful info.  I think I will go
> with Hans' 4 output board to see if the project works at all and go from
> there.  Off on a three week tour of Italy to Malta and should have the
> parts when I get back.  This is one of those weird design things so maybe
> the oscillators won't be the problem!
>
> N0UU
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Re: [time-nuts] Programmable clock for BFO use....noise Thanks to all

2018-09-14 Thread lstoskopf
 Got a whole bunch of answers all with useful info.  I think I will go with 
Hans' 4 output board to see if the project works at all and go from there.  Off 
on a three week tour of Italy to Malta and should have the parts when I get 
back.  This is one of those weird design things so maybe the oscillators won't 
be the problem!

N0UU
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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-14 Thread Forrest Christian (List Account)
Would a mems oscillator such as a dsc6183 possibly work for you?  I'm
uncertain if the characteristics of a mems oscillator is compatible with
your application.

For odd frequencies I often head toward a mems oscillator since many can be
programmed to any reasonable frequency.   For example one can buy dsc6183
blanks and use a programmer to program it to your desired frequency.

The dsc61xx series happens to be one time programmable so you only get one
shot at it per blank.  The programmer is relatively inexpensive, but might
be more than one would want to pay for a one off.  I have found that having
a collection of blanks and a programmer is very useful since it allows me
to generate any frequency oscillator I need.

There are other mems oscillator models out there, with various specs and
programming (or not) options.






On Fri, Sep 14, 2018, 11:16 AM  wrote:

> Off topic for this list, but you guys are experts in oscillator noise!
>
> Playing with some mechanical filters.  Need USB and LSB crystals for the
> BFO.  No one seems to make crystals anymore, especially in the 253 KHz
> range!
>
> Looking at the DigiKey Cardinal programmable oscillators.  Cheap and
> available: CPPC1LZ A5B6
>
> Anyone have an idea how noisy these would be after a division by 4 to get
> them in range?
>
> Thanks,
>
> N0UU
> ___
> time-nuts mailing list -- time-nuts@lists.febo.com
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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-14 Thread paul swed
The beauty of a $2 arduino and a drop of code snitched from Engineer google.
OK enough of that back to the thread.
Regards
Paul
WB8TSL

On Fri, Sep 14, 2018 at 8:04 PM, Mike Feher  wrote:

> Not when I built them in the late 60's and early 70's. All discrete. 73 -
> Mike
>
>
>
> Mike B. Feher, N4FS
>
> 89 Arnold Blvd.
>
> Howell NJ 07731
>
> 848-245-9115
>
>
>
> -Original Message-
> From: time-nuts  On Behalf Of Richard
> (Rick) Karlquist
> Sent: Friday, September 14, 2018 7:15 PM
> To: Discussion of precise time and frequency measurement
> ; ed breya 
> Subject: Re: [time-nuts] Programmable clock for BFO usenoise
>
>
>
> >
>
> > Finally, of course, you can use DDS. This is nearly an ideal case for
>
>
>
> The trouble with a DDS is that you need a microcontroller with software
> just
> to baby sit the thing.
>
>
>
> Rick N6RK
>
>
>
> ___
>
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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-14 Thread Mike Feher
Not when I built them in the late 60's and early 70's. All discrete. 73 -
Mike 

 

Mike B. Feher, N4FS

89 Arnold Blvd.

Howell NJ 07731

848-245-9115

 

-Original Message-
From: time-nuts  On Behalf Of Richard
(Rick) Karlquist
Sent: Friday, September 14, 2018 7:15 PM
To: Discussion of precise time and frequency measurement
; ed breya 
Subject: Re: [time-nuts] Programmable clock for BFO usenoise

 

> 

> Finally, of course, you can use DDS. This is nearly an ideal case for

 

The trouble with a DDS is that you need a microcontroller with software just
to baby sit the thing.

 

Rick N6RK

 

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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-14 Thread ed breya

Rick said:
"The trouble with a DDS is that you need a microcontroller with software 
just to baby sit the thing."


Yes, I know what you mean. I wouldn't want to go through all that. I'm 
picturing more like the small, cheap DDS boards that show up on ebay. 
Maybe the right stuff could be found that can stand alone, for maybe a 
tenth the cost of a custom crystal or XO.


I've always been kind of frustrated with not being able to readily use 
most of the cool new technologies in ICs, due to the SMT packaging, and 
the need for programming them via serial ports. I have saved a number of 
comparatively old-school, obsolete DDS and PLL devices, because they are 
parallel controlled, and can be hard-wired for fixed or limited functions.


Also, speaking of PLLs, maybe that would be the way to go for the OP - 
depending on the particular frequencies needed, and the resulting 
complexity of the divider(s).


Ed

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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-14 Thread Richard (Rick) Karlquist


Finally, of course, you can use DDS. This is nearly an ideal case for 


The trouble with a DDS is that you need a microcontroller with
software just to baby sit the thing.

Rick N6RK

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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-14 Thread ed breya
Those programmable oscillators look interesting. I went to Cardinal the 
website to learn more, but they're pretty sparse on details. It looks 
like they make all sorts of crystals, OC, TC, and VT XO modules, etc, 
and these programmable ones, which are apparently PLL-based oscillators 
locked to an XO. They don't say much more, but if you asked, maybe 
they'd give some usable info.


There was also some mention of their own shortcomings with phase noise 
and jitter, circa 2005, and how the later generations are much improved.


I'd say that since the programmed frequency is at least XO-based, then 
its stability seems to be specified and can be good, but the noise etc 
of the associated PLL inside does not seem to specified. It may be OK 
for the application to just pick a certain frequency that would be 
easier on the PLL (if you knew more about it and the XO frequency they 
would use), and easy to divide down to your end results. I would wonder 
what the few-off cost would be for the appropriate base parts and 
programming.


They also seem to have custom crystal building service, which could be 
very handy, depending on the cost. I've often needed oddball frequencies 
for various projects, and wished it was easy and cheap to just order 
some up.


Another trick you can try, that I've resorted to a number of times, is 
to find two "standard" or common (or oddball ones that you happen to 
already have) crystal frequencies that you can mix to get the desired 
result. The combinations of various crystals and possible dividing 
ratios may yield something close enough to tweak in. An EXCEL sheet can 
help organize the info and choices.


Finally, of course, you can use DDS. This is nearly an ideal case for 
this, since you want to make stuff around 250 kHz, but necessarily must 
(for lack of in-range XOs) use a clock in the MHz region - maybe ten to 
a hundred times higher than the output, so easy to get a good sine out. 
Between the various XO clock frequencies available, and the program 
choices in the DDS, it should be possible to come up with a nice scheme 
to make whatever you want down in that range.


Ed

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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-14 Thread Bryan _
I would be interested in hearing more of the more suitable classes of logic 
chips. I have a 20Mhz rubidium that I wanted to divide down to 10Mhz

-=Bryan=-


From: time-nuts  on behalf of Dana Whitlow 

Sent: September 14, 2018 12:55 PM
To: lstosk...@cox.net; Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Programmable clock for BFO usenoise

Frequency dividers can be pretty low noise, if you choose the right class
of logic.  I remember that
at one time in the distant past, LSTTL was considered king.  Unfortunately
I've been out of touch
with frequency dividers long enough to be ignorant of what works well today.

i'd suggest trying something with either HC-series or AC-series CMOS,
chances are fair that you'd
be happy.  Write me off list and I'll tell you which well-known distributor
still has an excellent
selection of HC and AC parts in stock.

Dana


On Fri, Sep 14, 2018 at 11:14 AM,  wrote:

> Off topic for this list, but you guys are experts in oscillator noise!
>
> Playing with some mechanical filters.  Need USB and LSB crystals for the
> BFO.  No one seems to make crystals anymore, especially in the 253 KHz
> range!
>
> Looking at the DigiKey Cardinal programmable oscillators.  Cheap and
> available: CPPC1LZ A5B6
>
> Anyone have an idea how noisy these would be after a division by 4 to get
> them in range?
>
> Thanks,
>
> N0UU
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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-14 Thread paul swed
As a suggestion I collaborate with a Canadian ham some 5 years ago using a
DDS as a BFO for the HP 3586. Those details were shared on time-nuts if
they are still in the archives.That worked really well. I recall he was a
VE3??? The 3586 had 2 crystals for the BFO while the entire rest of the
system was locked to a single reference. Adding the DDS really reduced the
BFO behaviors that we typical hams wouldn't really notice. It also sound
very clean.
Regards
Paul
WB8TSL

On Fri, Sep 14, 2018 at 4:26 PM, Richard (Rick) Karlquist <
rich...@karlquist.com> wrote:

> The AC series is really quite good on phase noise; I used it in
> the 5071A at 80 MHz.
>
> Rick N6RK
>
> On 9/14/2018 12:55 PM, Dana Whitlow wrote:
>
>> Frequency dividers can be pretty low noise, if you choose the right class
>> of logic.  I remember that
>> at one time in the distant past, LSTTL was considered king.  Unfortunately
>> I've been out of touch
>> with frequency dividers long enough to be ignorant of what works well
>> today.
>>
>> i'd suggest trying something with either HC-series or AC-series CMOS,
>>
>
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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-14 Thread Richard (Rick) Karlquist

The AC series is really quite good on phase noise; I used it in
the 5071A at 80 MHz.

Rick N6RK

On 9/14/2018 12:55 PM, Dana Whitlow wrote:

Frequency dividers can be pretty low noise, if you choose the right class
of logic.  I remember that
at one time in the distant past, LSTTL was considered king.  Unfortunately
I've been out of touch
with frequency dividers long enough to be ignorant of what works well today.

i'd suggest trying something with either HC-series or AC-series CMOS,


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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-14 Thread Richard (Rick) Karlquist

I encountered these oscillators on a circuit I inherited
from another engineer.  The spectrum of these is quite
dirty and they should only be considered as digital clock
oscillators.  An additional annoyance is that they are
not marked with the frequency they are programmed to,
so if you have USB and LSB you'll have to put a dot
of paint on them or something to tell them apart.

Dividing by 4 or N will reduce spurs by 20 LOG N as
any time nut knows.  If you get a programmable oscillator
at a frequency around 32 MHz and divide it down by 128
to ~253 kHz, you might get enough clean up for your
purposes.  20 LOG 128 = 42 dB.

Alternately, find a conventional clock
oscillator that can be divided by an even integer to hit
your BFO frequency.  For example, 20 MHz divided by
78 = 256.4 kHz.  20 MHz divided by 80 = 250 kHz.
Divide by 39 followed by divide by 2 or divide by 40
followed by divide by 2, in order to get a square wave
at the output.

Rick N6RK

On 9/14/2018 9:14 AM, lstosk...@cox.net wrote:

Off topic for this list, but you guys are experts in oscillator noise!

Playing with some mechanical filters.  Need USB and LSB crystals for the BFO.  
No one seems to make crystals anymore, especially in the 253 KHz range!

Looking at the DigiKey Cardinal programmable oscillators.  Cheap and available: 
CPPC1LZ A5B6

Anyone have an idea how noisy these would be after a division by 4 to get them 
in range?

Thanks,

N0UU
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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-14 Thread Dana Whitlow
Frequency dividers can be pretty low noise, if you choose the right class
of logic.  I remember that
at one time in the distant past, LSTTL was considered king.  Unfortunately
I've been out of touch
with frequency dividers long enough to be ignorant of what works well today.

i'd suggest trying something with either HC-series or AC-series CMOS,
chances are fair that you'd
be happy.  Write me off list and I'll tell you which well-known distributor
still has an excellent
selection of HC and AC parts in stock.

Dana


On Fri, Sep 14, 2018 at 11:14 AM,  wrote:

> Off topic for this list, but you guys are experts in oscillator noise!
>
> Playing with some mechanical filters.  Need USB and LSB crystals for the
> BFO.  No one seems to make crystals anymore, especially in the 253 KHz
> range!
>
> Looking at the DigiKey Cardinal programmable oscillators.  Cheap and
> available: CPPC1LZ A5B6
>
> Anyone have an idea how noisy these would be after a division by 4 to get
> them in range?
>
> Thanks,
>
> N0UU
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> listinfo/time-nuts_lists.febo.com
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>
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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-14 Thread Wes
I'd look for the appropriate crystals. If it will help, I have a 250.00 kHz one 
you can have.


Wes  N7WS

On 9/14/2018 9:14 AM, lstosk...@cox.net wrote:

Off topic for this list, but you guys are experts in oscillator noise!

Playing with some mechanical filters.  Need USB and LSB crystals for the BFO.  
No one seems to make crystals anymore, especially in the 253 KHz range!

Looking at the DigiKey Cardinal programmable oscillators.  Cheap and available: 
CPPC1LZ A5B6

Anyone have an idea how noisy these would be after a division by 4 to get them 
in range?

Thanks,

N0UU
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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-14 Thread Hal Murray


paulsw...@gmail.com said:
> I looked at those types of units. I thought they were factory programmed. I
> may be wrong but was not of the opinion they were single unit buys. 

I think the business model is distributor programmed.  The distributor stocks 
a small set of internal xtal frequencies and programs them to order.

-- 
These are my opinions.  I hate spam.




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Re: [time-nuts] Programmable clock for BFO use....noise

2018-09-14 Thread paul swed
Not sure it would be the noise divided by 4. Not a useful answer.
I looked at those types of units. I thought they were factory programmed.
I may be wrong but was not of the opinion they were single unit buys.
Regards
WB8TSL

On Fri, Sep 14, 2018 at 12:14 PM,  wrote:

> Off topic for this list, but you guys are experts in oscillator noise!
>
> Playing with some mechanical filters.  Need USB and LSB crystals for the
> BFO.  No one seems to make crystals anymore, especially in the 253 KHz
> range!
>
> Looking at the DigiKey Cardinal programmable oscillators.  Cheap and
> available: CPPC1LZ A5B6
>
> Anyone have an idea how noisy these would be after a division by 4 to get
> them in range?
>
> Thanks,
>
> N0UU
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> listinfo/time-nuts_lists.febo.com
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